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moving MUL unit into ALU unit

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This commit is contained in:
Blaise Tine
2021-02-23 13:49:02 -08:00
parent 1792571e1b
commit 700f9eea19
30 changed files with 112978 additions and 9680 deletions
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33
hw/rtl/libs/VX_fifo_queue.v
View File

@@ -105,33 +105,16 @@ module VX_fifo_queue #(
if (0 == BUFFERED) begin
if (FASTRAM) begin
`USE_FAST_BRAM reg [DATAW-1:0] shift_reg [SIZE];
reg [1:0][DATAW-1:0] shift_reg;
always @(posedge clk) begin
if (push) begin
shift_reg[1] <= shift_reg[0];
shift_reg[0] <= data_in;
end
always @(posedge clk) begin
if (push) begin
shift_reg[1] <= shift_reg[0];
shift_reg[0] <= data_in;
end
assign data_out = shift_reg[~used_r[0]];
end else begin
reg [DATAW-1:0] shift_reg [SIZE];
always @(posedge clk) begin
if (push) begin
shift_reg[1] <= shift_reg[0];
shift_reg[0] <= data_in;
end
end
assign data_out = shift_reg[~used_r[0]];
end
assign data_out = shift_reg[!used_r[0]];
end else begin
@@ -142,7 +125,7 @@ module VX_fifo_queue #(
if (push) begin
buffer <= data_in;
end
if (push && (empty_r || ((used_r == ADDRW'(1)) && pop))) begin
if (push && (empty_r || (used_r && pop))) begin
data_out_r <= data_in;
end else if (pop) begin
data_out_r <= buffer;

11
hw/rtl/libs/VX_skid_buffer.v
View File

@@ -59,6 +59,7 @@ module VX_skid_buffer #(
reg use_buffer;
wire push = valid_in && ready_in;
wire pop = !valid_out_r || ready_out;
always @(posedge clk) begin
if (reset) begin
@@ -68,11 +69,11 @@ module VX_skid_buffer #(
if (ready_out) begin
use_buffer <= 0;
end
if (push && valid_out_r && !ready_out) begin
if (push && !pop) begin
assert(!use_buffer);
use_buffer <= 1;
end
if (!valid_out_r || ready_out) begin
if (pop) begin
valid_out_r <= valid_in || use_buffer;
end
end
@@ -82,7 +83,7 @@ module VX_skid_buffer #(
if (push) begin
buffer <= data_in;
end
if (!valid_out_r || ready_out) begin
if (pop) begin
data_out_r <= use_buffer ? buffer : data_in;
end
end
@@ -118,8 +119,8 @@ module VX_skid_buffer #(
);
assign ready_in = !q_full;
assign valid_out = !q_empty;
assign valid_out = !q_empty;
end
end