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moving MUL unit into ALU unit

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This commit is contained in:
Blaise Tine
2021-02-23 13:49:02 -08:00
parent 1792571e1b
commit 700f9eea19
30 changed files with 112978 additions and 9680 deletions
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4
hw/rtl/interfaces/VX_alu_req_if.v
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@@ -10,8 +10,8 @@ interface VX_alu_req_if ();
wire [`NUM_THREADS-1:0] tmask;
wire [31:0] PC;
wire [31:0] next_PC;
wire [`ALU_BR_BITS-1:0] op_type;
wire is_br_op;
wire [`ALU_BITS-1:0] op_type;
wire [`MOD_BITS-1:0] op_mod;
wire rs1_is_PC;
wire rs2_is_imm;
wire [31:0] imm;

25
hw/rtl/interfaces/VX_mul_req_if.v
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@@ -1,25 +0,0 @@
`ifndef VX_MUL_REQ_IF
`define VX_MUL_REQ_IF
`include "VX_define.vh"
`ifndef EXT_M_ENABLE
`IGNORE_WARNINGS_BEGIN
`endif
interface VX_mul_req_if ();
wire valid;
wire [`NW_BITS-1:0] wid;
wire [`NUM_THREADS-1:0] tmask;
wire [31:0] PC;
wire [`MUL_BITS-1:0] op_type;
wire [`NUM_THREADS-1:0][31:0] rs1_data;
wire [`NUM_THREADS-1:0][31:0] rs2_data;
wire [`NR_BITS-1:0] rd;
wire wb;
wire ready;
endinterface
`endif

3
hw/rtl/interfaces/VX_perf_pipeline_if.v
View File

@@ -10,9 +10,6 @@ interface VX_perf_pipeline_if ();
wire [63:0] csr_stalls;
wire [63:0] alu_stalls;
wire [63:0] gpu_stalls;
`ifdef EXT_M_ENABLE
wire [63:0] mul_stalls;
`endif
`ifdef EXT_F_ENABLE
wire [63:0] fpu_stalls;
`endif