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moving MUL unit into ALU unit

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This commit is contained in:
Blaise Tine
2021-02-23 13:49:02 -08:00
parent 1792571e1b
commit 700f9eea19
30 changed files with 112978 additions and 9680 deletions
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80
hw/rtl/VX_writeback.v
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@@ -10,17 +10,15 @@ module VX_writeback #(
VX_commit_if alu_commit_if,
VX_commit_if ld_commit_if,
VX_commit_if csr_commit_if,
VX_commit_if mul_commit_if,
VX_commit_if fpu_commit_if,
// outputs
VX_writeback_if writeback_if
);
wire alu_valid = alu_commit_if.valid && alu_commit_if.wb;
wire ld_valid = ld_commit_if.valid && ld_commit_if.wb;
wire ld_valid = ld_commit_if.valid && ld_commit_if.wb;
wire fpu_valid = fpu_commit_if.valid && fpu_commit_if.wb;
wire csr_valid = csr_commit_if.valid && csr_commit_if.wb;
wire mul_valid = mul_commit_if.valid && mul_commit_if.wb;
/*wire fpu_valid = fpu_commit_if.valid && fpu_commit_if.wb;*/
wire alu_valid = alu_commit_if.valid && alu_commit_if.wb;
wire wb_valid;
wire [`NW_BITS-1:0] wb_wid;
@@ -30,47 +28,40 @@ module VX_writeback #(
wire [`NUM_THREADS-1:0][31:0] wb_data;
wire wb_eop;
assign wb_valid = alu_valid ? alu_commit_if.valid :
ld_valid ? ld_commit_if.valid :
csr_valid ? csr_commit_if.valid :
mul_valid ? mul_commit_if.valid :
/*fpu_valid ?*/ fpu_commit_if.valid;
assign wb_valid = ld_valid |
fpu_valid |
csr_valid |
alu_valid;
assign wb_wid = alu_valid ? alu_commit_if.wid :
ld_valid ? ld_commit_if.wid :
csr_valid ? csr_commit_if.wid :
mul_valid ? mul_commit_if.wid :
/*fpu_valid ?*/ fpu_commit_if.wid;
assign wb_wid = ld_valid ? ld_commit_if.wid :
fpu_valid ? fpu_commit_if.wid :
csr_valid ? csr_commit_if.wid :
/*alu_valid ?*/ alu_commit_if.wid;
assign wb_PC = alu_valid ? alu_commit_if.PC :
ld_valid ? ld_commit_if.PC :
csr_valid ? csr_commit_if.PC :
mul_valid ? mul_commit_if.PC :
/*fpu_valid ?*/ fpu_commit_if.PC;
assign wb_PC = ld_valid ? ld_commit_if.PC :
fpu_valid ? fpu_commit_if.PC :
csr_valid ? csr_commit_if.PC :
/*alu_valid ?*/ alu_commit_if.PC;
assign wb_tmask = alu_valid ? alu_commit_if.tmask :
ld_valid ? ld_commit_if.tmask :
csr_valid ? csr_commit_if.tmask :
mul_valid ? mul_commit_if.tmask :
/*fpu_valid ?*/ fpu_commit_if.tmask;
assign wb_tmask = ld_valid ? ld_commit_if.tmask :
fpu_valid ? fpu_commit_if.tmask :
csr_valid ? csr_commit_if.tmask :
/*alu_valid ?*/ alu_commit_if.tmask;
assign wb_rd = alu_valid ? alu_commit_if.rd :
ld_valid ? ld_commit_if.rd :
csr_valid ? csr_commit_if.rd :
mul_valid ? mul_commit_if.rd :
/*fpu_valid ?*/ fpu_commit_if.rd;
assign wb_rd = ld_valid ? ld_commit_if.rd :
fpu_valid ? fpu_commit_if.rd :
csr_valid ? csr_commit_if.rd :
/*alu_valid ?*/ alu_commit_if.rd;
assign wb_data = alu_valid ? alu_commit_if.data :
ld_valid ? ld_commit_if.data :
csr_valid ? csr_commit_if.data :
mul_valid ? mul_commit_if.data :
/*fpu_valid ?*/ fpu_commit_if.data;
assign wb_data = ld_valid ? ld_commit_if.data :
fpu_valid ? fpu_commit_if.data :
csr_valid ? csr_commit_if.data :
/*alu_valid ?*/ alu_commit_if.data;
assign wb_eop = alu_valid ? alu_commit_if.eop :
ld_valid ? ld_commit_if.eop :
csr_valid ? csr_commit_if.eop :
mul_valid ? mul_commit_if.eop :
/*fpu_valid ?*/ fpu_commit_if.eop;
assign wb_eop = ld_valid ? ld_commit_if.eop :
fpu_valid ? fpu_commit_if.eop :
csr_valid ? csr_commit_if.eop :
/*alu_valid ?*/ alu_commit_if.eop;
wire stall = ~writeback_if.ready && writeback_if.valid;
@@ -85,11 +76,10 @@ module VX_writeback #(
.data_out ({writeback_if.valid, writeback_if.wid, writeback_if.PC, writeback_if.tmask, writeback_if.rd, writeback_if.data, writeback_if.eop})
);
assign alu_commit_if.ready = !stall;
assign ld_commit_if.ready = !stall && !alu_valid;
assign csr_commit_if.ready = !stall && !alu_valid && !ld_valid;
assign mul_commit_if.ready = !stall && !alu_valid && !ld_valid && !csr_valid;
assign fpu_commit_if.ready = !stall && !alu_valid && !ld_valid && !csr_valid && !mul_valid;
assign ld_commit_if.ready = !stall;
assign fpu_commit_if.ready = !stall && !ld_valid;
assign csr_commit_if.ready = !stall && !ld_valid && !fpu_valid;
assign alu_commit_if.ready = !stall && !ld_valid && !fpu_valid && !csr_valid;
// special workaround to get RISC-V tests Pass/Fail status
reg [31:0] last_wb_value [`NUM_REGS-1:0] /* verilator public */;