moving MUL unit into ALU unit

This commit is contained in:
Blaise Tine
2021-02-23 13:49:02 -08:00
parent 1792571e1b
commit 700f9eea19
30 changed files with 112978 additions and 9680 deletions

View File

@@ -21,10 +21,10 @@ module VX_decode #(
wire [31:0] instr = ifetch_rsp_if.instr;
reg [`ALU_BITS-1:0] alu_op;
reg [`BR_BITS-1:0] br_op;
reg [`BR_BITS-1:0] br_op;
reg [`MUL_BITS-1:0] mul_op;
reg [`LSU_BITS-1:0] lsu_op;
reg [`CSR_BITS-1:0] csr_op;
reg [`MUL_BITS-1:0] mul_op;
reg [`FPU_BITS-1:0] fpu_op;
reg [`GPU_BITS-1:0] gpu_op;
@@ -120,16 +120,11 @@ module VX_decode #(
`INST_JAL: br_op = `BR_JAL;
`INST_JALR: br_op = `BR_JALR;
`INST_SYS: begin
if (is_jals) begin
case (u_12)
12'h000: br_op = `BR_ECALL;
12'h001: br_op = `BR_EBREAK;
12'h302: br_op = `BR_MRET;
12'h102: br_op = `BR_SRET;
12'h7B2: br_op = `BR_DRET;
default:;
endcase
end
if (is_jals && u_12 == 12'h000) br_op = `BR_ECALL;
if (is_jals && u_12 == 12'h001) br_op = `BR_EBREAK;
if (is_jals && u_12 == 12'h302) br_op = `BR_MRET;
if (is_jals && u_12 == 12'h102) br_op = `BR_SRET;
if (is_jals && u_12 == 12'h7B2) br_op = `BR_DRET;
end
default:;
endcase
@@ -174,7 +169,7 @@ module VX_decode #(
// MUL
`ifdef EXT_M_ENABLE
wire is_mul = is_rtype && (func7 == 7'h1);
wire is_mul = is_rtype && (func7 == 7'h1);
always @(*) begin
mul_op = `MUL_MUL;
case (func3)
@@ -238,11 +233,11 @@ module VX_decode #(
7'h0C: fpu_op = `FPU_DIV;
7'h10: begin
fpu_op = `FPU_MISC;
frm = func3[1] ? 2 : (func3[0] ? 1 : 0);
frm = func3[1] ? 3'b010 : {2'b0, func3[0]};
end
7'h14: begin
fpu_op = `FPU_MISC;
frm = (func3 == 3'h0) ? 3 : 4;
frm = (func3 == 3'h0) ? 3'b011 : 3'b100;
end
7'h2C: begin
fpu_op = `FPU_SQRT;
@@ -272,6 +267,7 @@ module VX_decode #(
wire is_fpu = 0;
wire is_fpu_no_mem= 0;
wire [2:0] frm = 0;
wire is_fsqrt = 0;
always @(*) begin
fpu_op = `FPU_MISC;
@@ -334,25 +330,23 @@ module VX_decode #(
assign decode_if.tmask = ifetch_rsp_if.tmask;
assign decode_if.PC = ifetch_rsp_if.PC;
assign decode_if.ex_type = is_lsu ? `EX_LSU :
assign decode_if.ex_type = is_gpu ? `EX_GPU :
is_csr ? `EX_CSR :
is_mul ? `EX_MUL :
is_fpu_no_mem ? `EX_FPU :
is_gpu ? `EX_GPU :
is_br ? `EX_ALU :
(is_rtype || is_itype || is_lui || is_auipc) ? `EX_ALU :
`EX_NOP;
is_fpu_no_mem ? `EX_FPU :
is_lsu ? `EX_LSU :
(is_br || is_rtype || is_itype || is_lui || is_auipc) ? `EX_ALU :
`EX_NOP;
assign decode_if.op_type = is_lsu ? `OP_BITS'(lsu_op) :
assign decode_if.op_type = is_gpu ? `OP_BITS'(gpu_op) :
is_csr ? `OP_BITS'(csr_op) :
is_mul ? `OP_BITS'(mul_op) :
is_fpu_no_mem ? `OP_BITS'(fpu_op) :
is_gpu ? `OP_BITS'(gpu_op) :
is_fpu_no_mem ? `OP_BITS'(fpu_op) :
is_lsu ? `OP_BITS'(lsu_op) :
is_br ? `OP_BITS'(br_op) :
(is_rtype || is_itype || is_lui || is_auipc) ? `OP_BITS'(alu_op) :
0;
assign decode_if.wb = use_rd;
assign decode_if.wb = use_rd && (decode_if.ex_type != `EX_NOP);
`ifdef EXT_F_ENABLE
wire rd_is_fp = is_fpu && ~(is_fcmp || is_fcvti || is_fmvw_clss);
@@ -370,13 +364,10 @@ module VX_decode #(
assign decode_if.rs3 = rs3;
`endif
wire is_nop = (decode_if.ex_type == `EX_NOP);
assign decode_if.used_regs = is_nop ? `NUM_REGS'(0) :
((`NUM_REGS'(use_rd) << decode_if.rd)
| (`NUM_REGS'(use_rs1) << decode_if.rs1)
| (`NUM_REGS'(use_rs2) << decode_if.rs2)
| (`NUM_REGS'(use_rs3) << decode_if.rs3));
assign decode_if.used_regs = (`NUM_REGS'(use_rd) << decode_if.rd)
| (`NUM_REGS'(use_rs1) << decode_if.rs1)
| (`NUM_REGS'(use_rs2) << decode_if.rs2)
| (`NUM_REGS'(use_rs3) << decode_if.rs3);
assign decode_if.imm = (is_lui || is_auipc) ? {upper_imm, 12'(0)} :
(is_jal || is_jalr || is_jals) ? jalx_offset :
@@ -386,7 +377,7 @@ module VX_decode #(
assign decode_if.rs1_is_PC = is_auipc || is_btype || is_jal || is_jals;
assign decode_if.rs2_is_imm = is_itype || is_lui || is_auipc || is_csr_imm || is_br;
wire [`MOD_BITS-1:0] alu_mod = is_br ? 1 : 0;
wire [`MOD_BITS-1:0] alu_mod = {1'b0, is_mul, is_br};
assign decode_if.op_mod = is_fpu_no_mem ? frm : alu_mod;
///////////////////////////////////////////////////////////////////////////