wu-arch/vortex
1
0
Fork 0
Code Issues Pull Requests Actions Packages Projects Releases Wiki Activity

Modelsim Makefile compile + simulate - DPI

Browse Source
This commit is contained in:
felsabbagh3
2019-10-26 19:01:49 -04:00
parent ad46194d1b
commit 6fda88b68f
6 changed files with 238 additions and 6 deletions
Download Patch File Download Diff File Expand all files Collapse all files

124
rtl/modelsim/Makefile Normal file
View File

@@ -0,0 +1,124 @@
###############################################################################
#
# ICARUS VERILOG & GTKWAVE MAKEFILE
# MADE BY WILLIAM GIBB FOR HACDC
# williamgibb@gmail.com
#
# USE THE FOLLOWING COMMANDS WITH THIS MAKEFILE
# "make check" - compiles your verilog design - good for checking code
# "make simulate" - compiles your design+TB & simulates your design
# "make display" - compiles, simulates and displays waveforms
#
###############################################################################
#
# CHANGE THESE THREE LINES FOR YOUR DESIGN
#
ALL:sim
#TOOL INPUT
SRC = \
vortex_tb.v \
../VX_define.v \
../interfaces/VX_branch_response_inter.v \
../interfaces/VX_csr_req_inter.v \
../interfaces/VX_csr_wb_inter.v \
../interfaces/VX_dcache_request_inter.v \
../interfaces/VX_dcache_response_inter.v \
../interfaces/VX_dram_req_rsp_inter.v \
../interfaces/VX_exec_unit_req_inter.v \
../interfaces/VX_frE_to_bckE_req_inter.v \
../interfaces/VX_gpr_clone_inter.v \
../interfaces/VX_gpr_data_inter.v \
../interfaces/VX_gpr_jal_inter.v \
../interfaces/VX_gpr_read_inter.v \
../interfaces/VX_gpr_wspawn_inter.v \
../interfaces/VX_gpu_inst_req_inter.v \
../interfaces/VX_icache_request_inter.v \
../interfaces/VX_icache_response_inter.v \
../interfaces/VX_inst_exec_wb_inter.v \
../interfaces/VX_inst_mem_wb_inter.v \
../interfaces/VX_inst_meta_inter.v \
../interfaces/VX_jal_response_inter.v \
../interfaces/VX_join_inter.v \
../interfaces/VX_lsu_req_inter.v \
../interfaces/VX_mem_req_inter.v \
../interfaces/VX_mw_wb_inter.v \
../interfaces/VX_warp_ctl_inter.v \
../interfaces/VX_wb_inter.v \
../interfaces/VX_wstall_inter.v \
../VX_alu.v \
../VX_back_end.v \
../VX_csr_handler.v \
../VX_csr_wrapper.v \
../VX_decode.v \
../VX_dmem_controller.v \
../VX_execute_unit.v \
../VX_fetch.v \
../VX_front_end.v \
../VX_generic_priority_encoder.v \
../VX_generic_register.v \
../VX_generic_stack.v \
../VX_gpgpu_inst.v \
../VX_gpr.v \
../VX_gpr_stage.v \
../VX_gpr_wrapper.v \
../VX_inst_multiplex.v \
../VX_lsu.v \
../VX_lsu_addr_gen.v \
../VX_priority_encoder.v \
../VX_priority_encoder_w_mask.v \
../VX_scheduler.v \
../VX_warp.v \
../VX_countones.v \
../VX_warp_scheduler.v \
../VX_writeback.v \
../Vortex.v \
../byte_enabled_simple_dual_port_ram.v \
../cache/VX_Cache_Bank.v \
../cache/VX_cache_bank_valid.v \
../cache/VX_cache_data.v \
../cache/VX_d_cache.v \
../cache/VX_generic_pe.v \
../cache/cache_set.v \
../pipe_regs/VX_d_e_reg.v \
../pipe_regs/VX_f_d_reg.v \
../shared_memory/VX_bank_valids.v \
../shared_memory/VX_priority_encoder_sm.v \
../shared_memory/VX_shared_memory.v \
../shared_memory/VX_shared_memory_block.v
CMD= \
-do "vcd file vortex.vcd; \
run"
# ../shared_memory/VX_set_bit.v \
# ../cache/bank.v \
# ../cache/VX_d_cache_tb.v \
# ../cache/VX_d_cache_encapsulate.v \
# ../VX_rename.v \
# ../cache/VX_Cache_Block_DM.v \
# ../VX_one_counter.v \
###############################################################################
# BE CAREFUL WHEN CHANGING ITEMS BELOW THIS LINE
###############################################################################
#TOOLS
#TOOL OUTPUT
###############################################################################
#MAKE DIRECTIVES
# setup: source cshrc.modelsim
# vlib
comp:
vlog -sv -sv12compat -work vortex_lib $(SRC)
sim: comp
vsim vortex_tb -logfile vortex_tb.log -c -lib vortex_lib $(CMD)

8
rtl/modelsim/cshrc.modelsim Normal file
View File

@@ -0,0 +1,8 @@
setenv PATH "${PATH}:/tools/mentor/modelsim/ms106a/modeltech/bin"
setenv MTI_VCO_MODE 1
if (${?LM_LICENSE_FILE}) then
setenv LM_LICENSE_FILE "1717@ece-linlic.ece.gatech.edu:${LM_LICENSE_FILE}"
else
setenv LM_LICENSE_FILE "1717@ece-linlic.ece.gatech.edu"
endif
setenv MGLS_LICENSE_FILE 1717@ece-linlic.ece.gatech.edu

65
rtl/modelsim/vortex_tb.v Normal file
View File

@@ -0,0 +1,65 @@
// `include "../VX_define.v"
// `include "../Vortex.v"
`timescale 1ns/1ps
module vortex_tb (
);
reg clk;
reg reset;
reg[31:0] icache_response_instruction;
reg[31:0] icache_request_pc_address;
// IO
reg io_valid;
reg[31:0] io_data;
// Req
reg [31:0] o_m_read_addr;
reg [31:0] o_m_evict_addr;
reg o_m_valid;
reg [31:0] o_m_writedata[8 - 1:0][4-1:0];
reg o_m_read_or_write;
// Rsp
reg [31:0] i_m_readdata[8 - 1:0][4-1:0];
reg i_m_ready;
reg out_ebreak;
integer temp;
initial begin
for (temp = 0; temp < 10; temp=temp+1)
begin
icache_response_instruction = 32'h0;
$display("SIMULATING");
end
// while (!out_ebreak) begin
// icache_response_instruction = 0;
// end
end
Vortex vortex(
.clk (clk),
.reset (reset),
.icache_response_instruction(icache_response_instruction),
.icache_request_pc_address (icache_request_pc_address),
.io_valid (io_valid),
.io_data (io_data),
.o_m_read_addr (o_m_read_addr),
.o_m_evict_addr (o_m_evict_addr),
.o_m_valid (o_m_valid),
.o_m_writedata (o_m_writedata),
.o_m_read_or_write (o_m_read_or_write),
.i_m_readdata (i_m_readdata),
.i_m_ready (i_m_ready),
.out_ebreak (out_ebreak)
);
always @(clk) #5 clk <= ~clk;
endmodule