diff --git a/simX/instruction.cpp b/simX/instruction.cpp index 4da4272e..c1b21760 100644 --- a/simX/instruction.cpp +++ b/simX/instruction.cpp @@ -1507,6 +1507,7 @@ void Instruction::executeOn(Warp &c, trace_inst_t * trace_inst) { break; case 2: { + Word VLMAX = (c.vtype.vlmul * c.VLEN)/c.vtype.vsew; switch(func6){ case 24: //vmandnot { @@ -1526,6 +1527,10 @@ void Instruction::executeOn(Warp &c, trace_inst_t * trace_inst) { uint8_t * result_ptr = (uint8_t *) vd[i].val; *result_ptr = result; } + for(uint8_t i = c.vl; i < VLMAX; i++){ + uint8_t *result_ptr = (uint8_t *) vd[i].val; + *result_ptr = 0; + } } else if(c.vtype.vsew == 16) { for(uint16_t i = 0; i < c.vl; i++){ @@ -1539,6 +1544,10 @@ void Instruction::executeOn(Warp &c, trace_inst_t * trace_inst) { uint16_t * result_ptr = (uint16_t *) vd[i].val; *result_ptr = result; } + for(uint16_t i = c.vl; i < VLMAX; i++){ + uint16_t *result_ptr = (uint16_t *) vd[i].val; + *result_ptr = 0; + } } else if(c.vtype.vsew == 32) { for(uint32_t i = 0; i < c.vl; i++){ @@ -1552,6 +1561,10 @@ void Instruction::executeOn(Warp &c, trace_inst_t * trace_inst) { uint32_t * result_ptr = (uint32_t *) vd[i].val; *result_ptr = result; } + for(Word i = c.vl; i < VLMAX; i++){ + uint32_t *result_ptr = (uint32_t *) vd[i].val; + *result_ptr = 0; + } } } break; @@ -1573,6 +1586,10 @@ void Instruction::executeOn(Warp &c, trace_inst_t * trace_inst) { uint8_t * result_ptr = (uint8_t *) vd[i].val; *result_ptr = result; } + for(uint8_t i = c.vl; i < VLMAX; i++){ + uint8_t *result_ptr = (uint8_t *) vd[i].val; + *result_ptr = 0; + } } else if(c.vtype.vsew == 16) { for(uint16_t i = 0; i < c.vl; i++){ @@ -1586,6 +1603,10 @@ void Instruction::executeOn(Warp &c, trace_inst_t * trace_inst) { uint16_t * result_ptr = (uint16_t *) vd[i].val; *result_ptr = result; } + for(uint16_t i = c.vl; i < VLMAX; i++){ + uint16_t *result_ptr = (uint16_t *) vd[i].val; + *result_ptr = 0; + } } else if(c.vtype.vsew == 32) { for(uint32_t i = 0; i < c.vl; i++){ @@ -1599,6 +1620,10 @@ void Instruction::executeOn(Warp &c, trace_inst_t * trace_inst) { uint32_t * result_ptr = (uint32_t *) vd[i].val; *result_ptr = result; } + for(Word i = c.vl; i < VLMAX; i++){ + uint32_t *result_ptr = (uint32_t *) vd[i].val; + *result_ptr = 0; + } } } break; @@ -1620,7 +1645,13 @@ void Instruction::executeOn(Warp &c, trace_inst_t * trace_inst) { uint8_t * result_ptr = (uint8_t *) vd[i].val; *result_ptr = result; } + for(uint8_t i = c.vl; i < VLMAX; i++){ + uint8_t *result_ptr = (uint8_t *) vd[i].val; + *result_ptr = 0; + } + } else if(c.vtype.vsew == 16) { + uint16_t *result_ptr; for(uint16_t i = 0; i < c.vl; i++){ uint16_t *first_ptr = (uint16_t *)vr1[i].val; uint16_t *second_ptr = (uint16_t *)vr2[i].val; @@ -1629,11 +1660,16 @@ void Instruction::executeOn(Warp &c, trace_inst_t * trace_inst) { uint16_t result = (first_value | second_value); cout << "Comparing " << *first_ptr << " + " << *second_ptr << " = " << result << '\n'; - uint16_t * result_ptr = (uint16_t *) vd[i].val; + result_ptr = (uint16_t *) vd[i].val; *result_ptr = result; } + for(uint16_t i = c.vl; i < VLMAX; i++){ + result_ptr = (uint16_t *) vd[i].val; + *result_ptr = 0; + } } else if(c.vtype.vsew == 32) { + uint32_t *result_ptr; for(uint32_t i = 0; i < c.vl; i++){ uint32_t *first_ptr = (uint32_t *)vr1[i].val; uint32_t *second_ptr = (uint32_t *)vr2[i].val; @@ -1642,15 +1678,21 @@ void Instruction::executeOn(Warp &c, trace_inst_t * trace_inst) { uint32_t result = (first_value | second_value); cout << "Comparing " << *first_ptr << " + " << *second_ptr << " = " << result << '\n'; - uint32_t * result_ptr = (uint32_t *) vd[i].val; + result_ptr = (uint32_t *) vd[i].val; *result_ptr = result; } + cout << "VLMAX: " << VLMAX << endl; + for(Word i = c.vl; i < VLMAX; i++){ + result_ptr = (uint32_t *) vd[i].val; + *result_ptr = 0; + } } } break; case 27: //vmxor { D(3, "vmxor"); + uint8_t *result_ptr; vector> vr1 = c.vreg[rsrc[0]]; vector> vr2 = c.vreg[rsrc[1]]; vector> vd = c.vreg[rdest]; @@ -1663,11 +1705,16 @@ void Instruction::executeOn(Warp &c, trace_inst_t * trace_inst) { uint8_t result = (first_value ^ second_value); cout << "Comparing " << *first_ptr << " + " << *second_ptr << " = " << result << '\n'; - uint8_t * result_ptr = (uint8_t *) vd[i].val; + result_ptr = (uint8_t *) vd[i].val; *result_ptr = result; } + for(uint8_t i = c.vl; i < VLMAX; i++){ + result_ptr = (uint8_t *) vd[i].val; + *result_ptr = 0; + } } else if(c.vtype.vsew == 16) { + uint16_t *result_ptr; for(uint16_t i = 0; i < c.vl; i++){ uint16_t *first_ptr = (uint16_t *)vr1[i].val; uint16_t *second_ptr = (uint16_t *)vr2[i].val; @@ -1676,11 +1723,16 @@ void Instruction::executeOn(Warp &c, trace_inst_t * trace_inst) { uint16_t result = (first_value ^ second_value); cout << "Comparing " << *first_ptr << " + " << *second_ptr << " = " << result << '\n'; - uint16_t * result_ptr = (uint16_t *) vd[i].val; + result_ptr = (uint16_t *) vd[i].val; *result_ptr = result; } + for(uint16_t i = c.vl; i < VLMAX; i++){ + uint16_t *result_ptr = (uint16_t *) vd[i].val; + *result_ptr = 0; + } } else if(c.vtype.vsew == 32) { + uint32_t *result_ptr; for(uint32_t i = 0; i < c.vl; i++){ uint32_t *first_ptr = (uint32_t *)vr1[i].val; uint32_t *second_ptr = (uint32_t *)vr2[i].val; @@ -1689,9 +1741,13 @@ void Instruction::executeOn(Warp &c, trace_inst_t * trace_inst) { uint32_t result = (first_value ^ second_value); cout << "Comparing " << *first_ptr << " + " << *second_ptr << " = " << result << '\n'; - uint32_t * result_ptr = (uint32_t *) vd[i].val; + result_ptr = (uint32_t *) vd[i].val; *result_ptr = result; } + for(Word i = c.vl; i < VLMAX; i++){ + uint32_t *result_ptr = (uint32_t *) vd[i].val; + *result_ptr = 0; + } } } break; @@ -1713,6 +1769,10 @@ void Instruction::executeOn(Warp &c, trace_inst_t * trace_inst) { uint8_t * result_ptr = (uint8_t *) vd[i].val; *result_ptr = result; } + for(uint8_t i = c.vl; i < VLMAX; i++){ + uint8_t *result_ptr = (uint8_t *) vd[i].val; + *result_ptr = 0; + } } else if(c.vtype.vsew == 16) { for(uint16_t i = 0; i < c.vl; i++){ @@ -1726,6 +1786,10 @@ void Instruction::executeOn(Warp &c, trace_inst_t * trace_inst) { uint16_t * result_ptr = (uint16_t *) vd[i].val; *result_ptr = result; } + for(uint16_t i = c.vl; i < VLMAX; i++){ + uint16_t *result_ptr = (uint16_t *) vd[i].val; + *result_ptr = 0; + } } else if(c.vtype.vsew == 32) { for(uint32_t i = 0; i < c.vl; i++){ @@ -1739,6 +1803,10 @@ void Instruction::executeOn(Warp &c, trace_inst_t * trace_inst) { uint32_t * result_ptr = (uint32_t *) vd[i].val; *result_ptr = result; } + for(Word i = c.vl; i < VLMAX; i++){ + uint32_t *result_ptr = (uint32_t *) vd[i].val; + *result_ptr = 0; + } } } break; @@ -1760,6 +1828,10 @@ void Instruction::executeOn(Warp &c, trace_inst_t * trace_inst) { uint8_t * result_ptr = (uint8_t *) vd[i].val; *result_ptr = result; } + for(uint8_t i = c.vl; i < VLMAX; i++){ + uint8_t *result_ptr = (uint8_t *) vd[i].val; + *result_ptr = 0; + } } else if(c.vtype.vsew == 16) { for(uint16_t i = 0; i < c.vl; i++){ @@ -1773,6 +1845,10 @@ void Instruction::executeOn(Warp &c, trace_inst_t * trace_inst) { uint16_t * result_ptr = (uint16_t *) vd[i].val; *result_ptr = result; } + for(uint16_t i = c.vl; i < VLMAX; i++){ + uint16_t *result_ptr = (uint16_t *) vd[i].val; + *result_ptr = 0; + } } else if(c.vtype.vsew == 32) { for(uint32_t i = 0; i < c.vl; i++){ @@ -1786,6 +1862,10 @@ void Instruction::executeOn(Warp &c, trace_inst_t * trace_inst) { uint32_t * result_ptr = (uint32_t *) vd[i].val; *result_ptr = result; } + for(Word i = c.vl; i < VLMAX; i++){ + uint32_t *result_ptr = (uint32_t *) vd[i].val; + *result_ptr = 0; + } } } break; @@ -1796,6 +1876,7 @@ void Instruction::executeOn(Warp &c, trace_inst_t * trace_inst) { vector> vr2 = c.vreg[rsrc[1]]; vector> vd = c.vreg[rdest]; if(c.vtype.vsew == 8){ + uint8_t *result_ptr; for(uint8_t i = 0; i < c.vl; i++){ uint8_t *first_ptr = (uint8_t *)vr1[i].val; uint8_t *second_ptr = (uint8_t *)vr2[i].val; @@ -1804,9 +1885,13 @@ void Instruction::executeOn(Warp &c, trace_inst_t * trace_inst) { uint8_t result = !(first_value | second_value); cout << "Comparing " << *first_ptr << " + " << *second_ptr << " = " << result << '\n'; - uint8_t * result_ptr = (uint8_t *) vd[i].val; + result_ptr = (uint8_t *) vd[i].val; *result_ptr = result; } + for(uint8_t i = c.vl; i < VLMAX; i++){ + result_ptr = (uint8_t *) vd[i].val; + *result_ptr = 0; + } } else if(c.vtype.vsew == 16) { for(uint16_t i = 0; i < c.vl; i++){ @@ -1820,8 +1905,13 @@ void Instruction::executeOn(Warp &c, trace_inst_t * trace_inst) { uint16_t * result_ptr = (uint16_t *) vd[i].val; *result_ptr = result; } + for(uint16_t i = c.vl; i < VLMAX; i++){ + uint16_t *result_ptr = (uint16_t *) vd[i].val; + *result_ptr = 0; + } } else if(c.vtype.vsew == 32) { + for(uint32_t i = 0; i < c.vl; i++){ uint32_t *first_ptr = (uint32_t *)vr1[i].val; uint32_t *second_ptr = (uint32_t *)vr2[i].val; @@ -1833,12 +1923,17 @@ void Instruction::executeOn(Warp &c, trace_inst_t * trace_inst) { uint32_t * result_ptr = (uint32_t *) vd[i].val; *result_ptr = result; } + for(Word i = c.vl; i < VLMAX; i++){ + uint32_t *result_ptr = (uint32_t *) vd[i].val; + *result_ptr = 0; + } } } break; case 31: //vmxnor { D(3, "vmxnor"); + uint8_t *result_ptr; vector> vr1 = c.vreg[rsrc[0]]; vector> vr2 = c.vreg[rsrc[1]]; vector> vd = c.vreg[rdest]; @@ -1851,11 +1946,15 @@ void Instruction::executeOn(Warp &c, trace_inst_t * trace_inst) { uint8_t result = !(first_value ^ second_value); cout << "Comparing " << *first_ptr << " + " << *second_ptr << " = " << result << '\n'; - uint8_t * result_ptr = (uint8_t *) vd[i].val; + result_ptr = (uint8_t *) vd[i].val; *result_ptr = result; } - + for(uint8_t i = c.vl; i < VLMAX; i++){ + result_ptr = (uint8_t *) vd[i].val; + *result_ptr = 0; + } } else if(c.vtype.vsew == 16) { + uint16_t *result_ptr; for(uint16_t i = 0; i < c.vl; i++){ uint16_t *first_ptr = (uint16_t *)vr1[i].val; uint16_t *second_ptr = (uint16_t *)vr2[i].val; @@ -1864,11 +1963,16 @@ void Instruction::executeOn(Warp &c, trace_inst_t * trace_inst) { uint16_t result = !(first_value ^ second_value); cout << "Comparing " << *first_ptr << " + " << *second_ptr << " = " << result << '\n'; - uint16_t * result_ptr = (uint16_t *) vd[i].val; + result_ptr = (uint16_t *) vd[i].val; *result_ptr = result; } + for(uint16_t i = c.vl; i < VLMAX; i++){ + result_ptr = (uint16_t *) vd[i].val; + *result_ptr = 0; + } } else if(c.vtype.vsew == 32) { + uint32_t *result_ptr; for(uint32_t i = 0; i < c.vl; i++){ uint32_t *first_ptr = (uint32_t *)vr1[i].val; uint32_t *second_ptr = (uint32_t *)vr2[i].val; @@ -1877,9 +1981,13 @@ void Instruction::executeOn(Warp &c, trace_inst_t * trace_inst) { uint32_t result = !(first_value ^ second_value); cout << "Comparing " << *first_ptr << " + " << *second_ptr << " = " << result << '\n'; - uint32_t * result_ptr = (uint32_t *) vd[i].val; + result_ptr = (uint32_t *) vd[i].val; *result_ptr = result; } + for(Word i = c.vl; i < VLMAX; i++){ + result_ptr = (uint32_t *) vd[i].val; + *result_ptr = 0; + } } } break; @@ -1944,10 +2052,10 @@ void Instruction::executeOn(Warp &c, trace_inst_t * trace_inst) { //trace_inst->is_lw = true; //trace_inst->mem_addresses[t] = memAddr; } - for(Word i = c.vl; i < VLMAX; i++){ + /*for(Word i = c.vl; i < VLMAX; i++){ int * result_ptr = (int *) vd[i].val; *result_ptr = 0; - } + }*/ D(3, "Vector Register state after addition:"); for(int i=0; i < c.vreg.size(); i++) diff --git a/simX/obj_dir/Vcache_simX b/simX/obj_dir/Vcache_simX new file mode 100755 index 00000000..c9d72f9e Binary files /dev/null and b/simX/obj_dir/Vcache_simX differ diff --git a/simX/obj_dir/Vcache_simX.cpp b/simX/obj_dir/Vcache_simX.cpp new file mode 100644 index 00000000..0c2bd96c --- /dev/null +++ b/simX/obj_dir/Vcache_simX.cpp @@ -0,0 +1,6268 @@ +// Verilated -*- C++ -*- +// DESCRIPTION: Verilator output: Design implementation internals +// See Vcache_simX.h for the primary calling header + +#include "Vcache_simX.h" +#include "Vcache_simX__Syms.h" + + +//-------------------- +// STATIC VARIABLES + +CData/*1:0*/ Vcache_simX::__Vtable1_cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__vx_priority_encoder_sm__DOT____Vcellout__genblk2__BRA__0__KET____DOT__vx_priority_encoder__index[16]; +CData/*0:0*/ Vcache_simX::__Vtable1_cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__vx_priority_encoder_sm__DOT____Vcellout__genblk2__BRA__0__KET____DOT__vx_priority_encoder__found[16]; +IData/*31:0*/ Vcache_simX::__Vtable1_cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__vx_priority_encoder_sm__DOT__genblk2__BRA__0__KET____DOT__vx_priority_encoder__DOT__i[16]; +CData/*1:0*/ Vcache_simX::__Vtable2_cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__vx_priority_encoder_sm__DOT____Vcellout__genblk2__BRA__1__KET____DOT__vx_priority_encoder__index[16]; +CData/*0:0*/ Vcache_simX::__Vtable2_cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__vx_priority_encoder_sm__DOT____Vcellout__genblk2__BRA__1__KET____DOT__vx_priority_encoder__found[16]; +IData/*31:0*/ Vcache_simX::__Vtable2_cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__vx_priority_encoder_sm__DOT__genblk2__BRA__1__KET____DOT__vx_priority_encoder__DOT__i[16]; +CData/*1:0*/ Vcache_simX::__Vtable3_cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__vx_priority_encoder_sm__DOT____Vcellout__genblk2__BRA__2__KET____DOT__vx_priority_encoder__index[16]; +CData/*0:0*/ Vcache_simX::__Vtable3_cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__vx_priority_encoder_sm__DOT____Vcellout__genblk2__BRA__2__KET____DOT__vx_priority_encoder__found[16]; +IData/*31:0*/ Vcache_simX::__Vtable3_cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__vx_priority_encoder_sm__DOT__genblk2__BRA__2__KET____DOT__vx_priority_encoder__DOT__i[16]; +CData/*1:0*/ Vcache_simX::__Vtable4_cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__vx_priority_encoder_sm__DOT____Vcellout__genblk2__BRA__3__KET____DOT__vx_priority_encoder__index[16]; +CData/*0:0*/ Vcache_simX::__Vtable4_cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__vx_priority_encoder_sm__DOT____Vcellout__genblk2__BRA__3__KET____DOT__vx_priority_encoder__found[16]; +IData/*31:0*/ Vcache_simX::__Vtable4_cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__vx_priority_encoder_sm__DOT__genblk2__BRA__3__KET____DOT__vx_priority_encoder__DOT__i[16]; +CData/*1:0*/ Vcache_simX::__Vtable5_cache_simX__DOT__dmem_controller__DOT__dcache__DOT__miss_bank_index[16]; +CData/*0:0*/ Vcache_simX::__Vtable5_cache_simX__DOT__dmem_controller__DOT__dcache__DOT__miss_found[16]; +IData/*31:0*/ Vcache_simX::__Vtable5_cache_simX__DOT__dmem_controller__DOT__dcache__DOT__get_miss_index__DOT__i[16]; +CData/*1:0*/ Vcache_simX::__Vtable6_cache_simX__DOT__dmem_controller__DOT__dcache__DOT____Vcellout__genblk1__BRA__0__KET____DOT__choose_thread__index[16]; +CData/*0:0*/ Vcache_simX::__Vtable6_cache_simX__DOT__dmem_controller__DOT__dcache__DOT____Vcellout__genblk1__BRA__0__KET____DOT__choose_thread__found[16]; +IData/*31:0*/ Vcache_simX::__Vtable6_cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk1__BRA__0__KET____DOT__choose_thread__DOT__i[16]; +CData/*1:0*/ Vcache_simX::__Vtable7_cache_simX__DOT__dmem_controller__DOT__dcache__DOT____Vcellout__genblk1__BRA__1__KET____DOT__choose_thread__index[16]; +CData/*0:0*/ Vcache_simX::__Vtable7_cache_simX__DOT__dmem_controller__DOT__dcache__DOT____Vcellout__genblk1__BRA__1__KET____DOT__choose_thread__found[16]; +IData/*31:0*/ Vcache_simX::__Vtable7_cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk1__BRA__1__KET____DOT__choose_thread__DOT__i[16]; +CData/*1:0*/ Vcache_simX::__Vtable8_cache_simX__DOT__dmem_controller__DOT__dcache__DOT____Vcellout__genblk1__BRA__2__KET____DOT__choose_thread__index[16]; +CData/*0:0*/ Vcache_simX::__Vtable8_cache_simX__DOT__dmem_controller__DOT__dcache__DOT____Vcellout__genblk1__BRA__2__KET____DOT__choose_thread__found[16]; +IData/*31:0*/ Vcache_simX::__Vtable8_cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk1__BRA__2__KET____DOT__choose_thread__DOT__i[16]; +CData/*1:0*/ Vcache_simX::__Vtable9_cache_simX__DOT__dmem_controller__DOT__dcache__DOT____Vcellout__genblk1__BRA__3__KET____DOT__choose_thread__index[16]; +CData/*0:0*/ Vcache_simX::__Vtable9_cache_simX__DOT__dmem_controller__DOT__dcache__DOT____Vcellout__genblk1__BRA__3__KET____DOT__choose_thread__found[16]; +IData/*31:0*/ Vcache_simX::__Vtable9_cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk1__BRA__3__KET____DOT__choose_thread__DOT__i[16]; + +//-------------------- + +VL_CTOR_IMP(Vcache_simX) { + Vcache_simX__Syms* __restrict vlSymsp = __VlSymsp = new Vcache_simX__Syms(this, name()); + Vcache_simX* __restrict vlTOPp VL_ATTR_UNUSED = vlSymsp->TOPp; + VL_CELL(__PVT__cache_simX__DOT__VX_dram_req_rsp_icache, Vcache_simX_VX_dram_req_rsp_inter__N1_NB4); + VL_CELL(__PVT__cache_simX__DOT__VX_dcache_req, Vcache_simX_VX_dcache_request_inter); + VL_CELL(__PVT__cache_simX__DOT__VX_dram_req_rsp, Vcache_simX_VX_dram_req_rsp_inter__N4_NB4); + VL_CELL(__PVT__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__0__KET____DOT__bank_structure, Vcache_simX_VX_Cache_Bank__pi7); + VL_CELL(__PVT__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__1__KET____DOT__bank_structure, Vcache_simX_VX_Cache_Bank__pi7); + VL_CELL(__PVT__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__2__KET____DOT__bank_structure, Vcache_simX_VX_Cache_Bank__pi7); + VL_CELL(__PVT__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__3__KET____DOT__bank_structure, Vcache_simX_VX_Cache_Bank__pi7); + // Reset internal values + + // Reset structure values + _ctor_var_reset(); +} + +void Vcache_simX::__Vconfigure(Vcache_simX__Syms* vlSymsp, bool first) { + if (0 && first) {} // Prevent unused + this->__VlSymsp = vlSymsp; +} + +Vcache_simX::~Vcache_simX() { + delete __VlSymsp; __VlSymsp=NULL; +} + +//-------------------- + + +void Vcache_simX::eval() { + VL_DEBUG_IF(VL_DBG_MSGF("+++++TOP Evaluate Vcache_simX::eval\n"); ); + Vcache_simX__Syms* __restrict vlSymsp = this->__VlSymsp; // Setup global symbol table + Vcache_simX* __restrict vlTOPp VL_ATTR_UNUSED = vlSymsp->TOPp; +#ifdef VL_DEBUG + // Debug assertions + _eval_debug_assertions(); +#endif // VL_DEBUG + // Initialize + if (VL_UNLIKELY(!vlSymsp->__Vm_didInit)) _eval_initial_loop(vlSymsp); + // Evaluate till stable + int __VclockLoop = 0; + QData __Vchange = 1; + do { + VL_DEBUG_IF(VL_DBG_MSGF("+ Clock loop\n");); + vlSymsp->__Vm_activity = true; + _eval(vlSymsp); + if (VL_UNLIKELY(++__VclockLoop > 100)) { + // About to fail, so enable debug to see what's not settling. + // Note you must run make with OPT=-DVL_DEBUG for debug prints. + int __Vsaved_debug = Verilated::debug(); + Verilated::debug(1); + __Vchange = _change_request(vlSymsp); + Verilated::debug(__Vsaved_debug); + VL_FATAL_MT("cache_simX.v", 4, "", + "Verilated model didn't converge\n" + "- See DIDNOTCONVERGE in the Verilator manual"); + } else { + __Vchange = _change_request(vlSymsp); + } + } while (VL_UNLIKELY(__Vchange)); +} + +void Vcache_simX::_eval_initial_loop(Vcache_simX__Syms* __restrict vlSymsp) { + vlSymsp->__Vm_didInit = true; + _eval_initial(vlSymsp); + vlSymsp->__Vm_activity = true; + // Evaluate till stable + int __VclockLoop = 0; + QData __Vchange = 1; + do { + _eval_settle(vlSymsp); + _eval(vlSymsp); + if (VL_UNLIKELY(++__VclockLoop > 100)) { + // About to fail, so enable debug to see what's not settling. + // Note you must run make with OPT=-DVL_DEBUG for debug prints. + int __Vsaved_debug = Verilated::debug(); + Verilated::debug(1); + __Vchange = _change_request(vlSymsp); + Verilated::debug(__Vsaved_debug); + VL_FATAL_MT("cache_simX.v", 4, "", + "Verilated model didn't DC converge\n" + "- See DIDNOTCONVERGE in the Verilator manual"); + } else { + __Vchange = _change_request(vlSymsp); + } + } while (VL_UNLIKELY(__Vchange)); +} + +//-------------------- +// Internal Methods + +VL_INLINE_OPT void Vcache_simX::_combo__TOP__1(Vcache_simX__Syms* __restrict vlSymsp) { + VL_DEBUG_IF(VL_DBG_MSGF("+ Vcache_simX::_combo__TOP__1\n"); ); + Vcache_simX* __restrict vlTOPp VL_ATTR_UNUSED = vlSymsp->TOPp; + // Body + vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache_driver_in_mem_read + = ((IData)(vlTOPp->in_icache_valid_pc_addr) + ? ((IData)(vlTOPp->in_icache_valid_pc_addr) + ? 2U : 7U) : 7U); + vlSymsp->TOP__cache_simX__DOT__VX_dcache_req.out_cache_driver_in_valid + = ((0xeU & (IData)(vlSymsp->TOP__cache_simX__DOT__VX_dcache_req.out_cache_driver_in_valid)) + | vlTOPp->in_dcache_in_valid[0U]); + vlSymsp->TOP__cache_simX__DOT__VX_dcache_req.out_cache_driver_in_valid + = ((0xdU & (IData)(vlSymsp->TOP__cache_simX__DOT__VX_dcache_req.out_cache_driver_in_valid)) + | (vlTOPp->in_dcache_in_valid[1U] << 1U)); + vlSymsp->TOP__cache_simX__DOT__VX_dcache_req.out_cache_driver_in_valid + = ((0xbU & (IData)(vlSymsp->TOP__cache_simX__DOT__VX_dcache_req.out_cache_driver_in_valid)) + | (vlTOPp->in_dcache_in_valid[2U] << 2U)); + vlSymsp->TOP__cache_simX__DOT__VX_dcache_req.out_cache_driver_in_valid + = ((7U & (IData)(vlSymsp->TOP__cache_simX__DOT__VX_dcache_req.out_cache_driver_in_valid)) + | (vlTOPp->in_dcache_in_valid[3U] << 3U)); +} + +void Vcache_simX::_settle__TOP__2(Vcache_simX__Syms* __restrict vlSymsp) { + VL_DEBUG_IF(VL_DBG_MSGF("+ Vcache_simX::_settle__TOP__2\n"); ); + Vcache_simX* __restrict vlTOPp VL_ATTR_UNUSED = vlSymsp->TOPp; + // Variables + WData/*31:0*/ __Vtemp19[4]; + WData/*31:0*/ __Vtemp20[4]; + WData/*31:0*/ __Vtemp21[4]; + WData/*31:0*/ __Vtemp22[4]; + // Body + vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache_driver_in_mem_read + = ((IData)(vlTOPp->in_icache_valid_pc_addr) + ? ((IData)(vlTOPp->in_icache_valid_pc_addr) + ? 2U : 7U) : 7U); + vlSymsp->TOP__cache_simX__DOT__VX_dcache_req.out_cache_driver_in_valid + = ((0xeU & (IData)(vlSymsp->TOP__cache_simX__DOT__VX_dcache_req.out_cache_driver_in_valid)) + | vlTOPp->in_dcache_in_valid[0U]); + vlSymsp->TOP__cache_simX__DOT__VX_dcache_req.out_cache_driver_in_valid + = ((0xdU & (IData)(vlSymsp->TOP__cache_simX__DOT__VX_dcache_req.out_cache_driver_in_valid)) + | (vlTOPp->in_dcache_in_valid[1U] << 1U)); + vlSymsp->TOP__cache_simX__DOT__VX_dcache_req.out_cache_driver_in_valid + = ((0xbU & (IData)(vlSymsp->TOP__cache_simX__DOT__VX_dcache_req.out_cache_driver_in_valid)) + | (vlTOPp->in_dcache_in_valid[2U] << 2U)); + vlSymsp->TOP__cache_simX__DOT__VX_dcache_req.out_cache_driver_in_valid + = ((7U & (IData)(vlSymsp->TOP__cache_simX__DOT__VX_dcache_req.out_cache_driver_in_valid)) + | (vlTOPp->in_dcache_in_valid[3U] << 3U)); + vlSymsp->TOP__cache_simX__DOT__VX_dcache_req.out_cache_driver_in_address[0U] + = vlTOPp->in_dcache_in_address[0U]; + vlSymsp->TOP__cache_simX__DOT__VX_dcache_req.out_cache_driver_in_address[1U] + = vlTOPp->in_dcache_in_address[1U]; + vlSymsp->TOP__cache_simX__DOT__VX_dcache_req.out_cache_driver_in_address[2U] + = vlTOPp->in_dcache_in_address[2U]; + vlSymsp->TOP__cache_simX__DOT__VX_dcache_req.out_cache_driver_in_address[3U] + = vlTOPp->in_dcache_in_address[3U]; + vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__way_to_update + = vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__global_way_to_evict; + vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__use_valid + = ((IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__stored_valid) + ? (IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__stored_valid) + : (IData)(vlTOPp->in_icache_valid_pc_addr)); + vlTOPp->cache_simX__DOT__dmem_controller__DOT__sm_driver_in_valid + = ((IData)(vlSymsp->TOP__cache_simX__DOT__VX_dcache_req.out_cache_driver_in_valid) + & VL_NEGATE_I((IData)((0xffU == (0xffU & + ((vlSymsp->TOP__cache_simX__DOT__VX_dcache_req.out_cache_driver_in_address[1U] + << 8U) + | (vlSymsp->TOP__cache_simX__DOT__VX_dcache_req.out_cache_driver_in_address[0U] + >> 0x18U))))))); + vlTOPp->cache_simX__DOT__dmem_controller__DOT__cache_driver_in_valid + = ((IData)(vlSymsp->TOP__cache_simX__DOT__VX_dcache_req.out_cache_driver_in_valid) + & VL_NEGATE_I((IData)((0xffU != (0xffU & + ((vlSymsp->TOP__cache_simX__DOT__VX_dcache_req.out_cache_driver_in_address[1U] + << 8U) + | (vlSymsp->TOP__cache_simX__DOT__VX_dcache_req.out_cache_driver_in_address[0U] + >> 0x18U))))))); + vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__multip_banks__DOT____Vlvbound1 + = vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__use_valid; + vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT____Vcellout__multip_banks__thread_track_banks + = vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__multip_banks__DOT____Vlvbound1; + vlTOPp->cache_simX__DOT__dmem_controller__DOT__sm_driver_in_mem_read + = ((0U != (IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__sm_driver_in_valid)) + ? (IData)(vlTOPp->in_dcache_mem_read) : 7U); + vlTOPp->cache_simX__DOT__dmem_controller__DOT__sm_driver_in_mem_write + = ((0U != (IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__sm_driver_in_valid)) + ? (IData)(vlTOPp->in_dcache_mem_write) : 7U); + vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__orig_in_valid + = ((0xeU & (IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__orig_in_valid)) + | (1U & (IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__sm_driver_in_valid))); + vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__orig_in_valid + = ((0xdU & (IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__orig_in_valid)) + | (2U & (IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__sm_driver_in_valid))); + vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__orig_in_valid + = ((0xbU & (IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__orig_in_valid)) + | (4U & (IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__sm_driver_in_valid))); + vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__orig_in_valid + = ((7U & (IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__orig_in_valid)) + | (8U & (IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__sm_driver_in_valid))); + vlTOPp->cache_simX__DOT__dmem_controller__DOT__read_or_write + = ((7U != (IData)(vlTOPp->in_dcache_mem_write)) + & (0U != (IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__cache_driver_in_valid))); + vlTOPp->cache_simX__DOT__dmem_controller__DOT__cache_driver_in_mem_write + = ((0U != (IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__cache_driver_in_valid)) + ? (IData)(vlTOPp->in_dcache_mem_write) : 7U); + vlTOPp->cache_simX__DOT__dmem_controller__DOT__cache_driver_in_mem_read + = ((0U != (IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__cache_driver_in_valid)) + ? (IData)(vlTOPp->in_dcache_mem_read) : 7U); + vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT__use_valid + = ((0U == (IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT__stored_valid)) + ? (IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__cache_driver_in_valid) + : (IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT__stored_valid)); + vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__valid_per_bank = 0U; + if (vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT____Vcellout__multip_banks__thread_track_banks) { + vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__valid_per_bank = 1U; + } + vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT____Vcellout__genblk1__BRA__0__KET____DOT__choose_thread__index = 0U; + if (vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT____Vcellout__multip_banks__thread_track_banks) { + vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT____Vcellout__genblk1__BRA__0__KET____DOT__choose_thread__index = 0U; + } + vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__vx_priority_encoder_sm__DOT__use_valid + = ((0U != (IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__vx_priority_encoder_sm__DOT__left_requests)) + ? (IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__vx_priority_encoder_sm__DOT__left_requests) + : (IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__orig_in_valid)); + vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT____Vcellout__multip_banks__thread_track_banks = 0U; + vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT____Vcellout__multip_banks__thread_track_banks + = (((~ ((IData)(1U) << (0xcU & vlSymsp->TOP__cache_simX__DOT__VX_dcache_req.out_cache_driver_in_address[0U]))) + & (IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT____Vcellout__multip_banks__thread_track_banks)) + | ((1U & (IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT__use_valid)) + << (0xcU & vlSymsp->TOP__cache_simX__DOT__VX_dcache_req.out_cache_driver_in_address[0U]))); + vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT____Vcellout__multip_banks__thread_track_banks + = (((~ ((IData)(1U) << (0xfU & ((IData)(1U) + + (0xcU & vlSymsp->TOP__cache_simX__DOT__VX_dcache_req.out_cache_driver_in_address[1U]))))) + & (IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT____Vcellout__multip_banks__thread_track_banks)) + | ((1U & ((IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT__use_valid) + >> 1U)) << (0xfU & ((IData)(1U) + + (0xcU & + vlSymsp->TOP__cache_simX__DOT__VX_dcache_req.out_cache_driver_in_address[1U]))))); + vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT____Vcellout__multip_banks__thread_track_banks + = (((~ ((IData)(1U) << (0xfU & ((IData)(2U) + + (0xcU & vlSymsp->TOP__cache_simX__DOT__VX_dcache_req.out_cache_driver_in_address[2U]))))) + & (IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT____Vcellout__multip_banks__thread_track_banks)) + | ((1U & ((IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT__use_valid) + >> 2U)) << (0xfU & ((IData)(2U) + + (0xcU & + vlSymsp->TOP__cache_simX__DOT__VX_dcache_req.out_cache_driver_in_address[2U]))))); + vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT____Vcellout__multip_banks__thread_track_banks + = (((~ ((IData)(1U) << (0xfU & ((IData)(3U) + + (0xcU & vlSymsp->TOP__cache_simX__DOT__VX_dcache_req.out_cache_driver_in_address[3U]))))) + & (IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT____Vcellout__multip_banks__thread_track_banks)) + | ((1U & ((IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT__use_valid) + >> 3U)) << (0xfU & ((IData)(3U) + + (0xcU & + vlSymsp->TOP__cache_simX__DOT__VX_dcache_req.out_cache_driver_in_address[3U]))))); + vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__use_valid_in + = (((2U == (IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__state)) + & (IData)(vlTOPp->cache_simX__DOT__icache_i_m_ready)) + | ((~ ((2U == (IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__state)) + & (~ (IData)(vlTOPp->cache_simX__DOT__icache_i_m_ready)))) + & ((1U != (IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__state)) + & (IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__valid_per_bank)))); + vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_addr + = ((1U == (IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__state)) + ? vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__miss_addr + : ((2U == (IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__state)) + ? vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__miss_addr + : (vlTOPp->in_icache_pc_addr >> (0x1fU + & ((IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT____Vcellout__genblk1__BRA__0__KET____DOT__choose_thread__index) + << 5U))))); + vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__vx_priority_encoder_sm__DOT____Vcellout__vx_bank_valid__bank_valids + = ((0xfffeU & (IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__vx_priority_encoder_sm__DOT____Vcellout__vx_bank_valid__bank_valids)) + | ((IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__vx_priority_encoder_sm__DOT__use_valid) + & (0U == (3U & ((vlSymsp->TOP__cache_simX__DOT__VX_dcache_req.out_cache_driver_in_address[1U] + << 0x1eU) | (vlSymsp->TOP__cache_simX__DOT__VX_dcache_req.out_cache_driver_in_address[0U] + >> 2U)))))); + vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__vx_priority_encoder_sm__DOT____Vcellout__vx_bank_valid__bank_valids + = ((0xfffdU & (IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__vx_priority_encoder_sm__DOT____Vcellout__vx_bank_valid__bank_valids)) + | (0xfffffffeU & ((IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__vx_priority_encoder_sm__DOT__use_valid) + & ((0U == (3U & ((vlSymsp->TOP__cache_simX__DOT__VX_dcache_req.out_cache_driver_in_address[2U] + << 0x1eU) + | (vlSymsp->TOP__cache_simX__DOT__VX_dcache_req.out_cache_driver_in_address[1U] + >> 2U)))) + << 1U)))); + vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__vx_priority_encoder_sm__DOT____Vcellout__vx_bank_valid__bank_valids + = ((0xfffbU & (IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__vx_priority_encoder_sm__DOT____Vcellout__vx_bank_valid__bank_valids)) + | (0xfffffffcU & ((IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__vx_priority_encoder_sm__DOT__use_valid) + & ((0U == (3U & ((vlSymsp->TOP__cache_simX__DOT__VX_dcache_req.out_cache_driver_in_address[3U] + << 0x1eU) + | (vlSymsp->TOP__cache_simX__DOT__VX_dcache_req.out_cache_driver_in_address[2U] + >> 2U)))) + << 2U)))); + vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__vx_priority_encoder_sm__DOT____Vcellout__vx_bank_valid__bank_valids + = ((0xfff7U & (IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__vx_priority_encoder_sm__DOT____Vcellout__vx_bank_valid__bank_valids)) + | (0xfffffff8U & ((IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__vx_priority_encoder_sm__DOT__use_valid) + & ((0U == (3U & (vlSymsp->TOP__cache_simX__DOT__VX_dcache_req.out_cache_driver_in_address[3U] + >> 2U))) + << 3U)))); + vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__vx_priority_encoder_sm__DOT____Vcellout__vx_bank_valid__bank_valids + = ((0xffefU & (IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__vx_priority_encoder_sm__DOT____Vcellout__vx_bank_valid__bank_valids)) + | (((IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__vx_priority_encoder_sm__DOT__use_valid) + & (1U == (3U & ((vlSymsp->TOP__cache_simX__DOT__VX_dcache_req.out_cache_driver_in_address[1U] + << 0x1eU) | (vlSymsp->TOP__cache_simX__DOT__VX_dcache_req.out_cache_driver_in_address[0U] + >> 2U))))) + << 4U)); + vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__vx_priority_encoder_sm__DOT____Vcellout__vx_bank_valid__bank_valids + = ((0xffdfU & (IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__vx_priority_encoder_sm__DOT____Vcellout__vx_bank_valid__bank_valids)) + | (0xffffffe0U & (((IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__vx_priority_encoder_sm__DOT__use_valid) + << 4U) & ((1U == (3U + & ((vlSymsp->TOP__cache_simX__DOT__VX_dcache_req.out_cache_driver_in_address[2U] + << 0x1eU) + | (vlSymsp->TOP__cache_simX__DOT__VX_dcache_req.out_cache_driver_in_address[1U] + >> 2U)))) + << 5U)))); + vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__vx_priority_encoder_sm__DOT____Vcellout__vx_bank_valid__bank_valids + = ((0xffbfU & (IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__vx_priority_encoder_sm__DOT____Vcellout__vx_bank_valid__bank_valids)) + | (0xffffffc0U & (((IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__vx_priority_encoder_sm__DOT__use_valid) + << 4U) & ((1U == (3U + & ((vlSymsp->TOP__cache_simX__DOT__VX_dcache_req.out_cache_driver_in_address[3U] + << 0x1eU) + | (vlSymsp->TOP__cache_simX__DOT__VX_dcache_req.out_cache_driver_in_address[2U] + >> 2U)))) + << 6U)))); + vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__vx_priority_encoder_sm__DOT____Vcellout__vx_bank_valid__bank_valids + = ((0xff7fU & (IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__vx_priority_encoder_sm__DOT____Vcellout__vx_bank_valid__bank_valids)) + | (0xffffff80U & (((IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__vx_priority_encoder_sm__DOT__use_valid) + << 4U) & ((1U == (3U + & (vlSymsp->TOP__cache_simX__DOT__VX_dcache_req.out_cache_driver_in_address[3U] + >> 2U))) + << 7U)))); + vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__vx_priority_encoder_sm__DOT____Vcellout__vx_bank_valid__bank_valids + = ((0xfeffU & (IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__vx_priority_encoder_sm__DOT____Vcellout__vx_bank_valid__bank_valids)) + | (((IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__vx_priority_encoder_sm__DOT__use_valid) + & (2U == (3U & ((vlSymsp->TOP__cache_simX__DOT__VX_dcache_req.out_cache_driver_in_address[1U] + << 0x1eU) | (vlSymsp->TOP__cache_simX__DOT__VX_dcache_req.out_cache_driver_in_address[0U] + >> 2U))))) + << 8U)); + vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__vx_priority_encoder_sm__DOT____Vcellout__vx_bank_valid__bank_valids + = ((0xfdffU & (IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__vx_priority_encoder_sm__DOT____Vcellout__vx_bank_valid__bank_valids)) + | (0xfffffe00U & (((IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__vx_priority_encoder_sm__DOT__use_valid) + << 8U) & ((2U == (3U + & ((vlSymsp->TOP__cache_simX__DOT__VX_dcache_req.out_cache_driver_in_address[2U] + << 0x1eU) + | (vlSymsp->TOP__cache_simX__DOT__VX_dcache_req.out_cache_driver_in_address[1U] + >> 2U)))) + << 9U)))); + vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__vx_priority_encoder_sm__DOT____Vcellout__vx_bank_valid__bank_valids + = ((0xfbffU & (IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__vx_priority_encoder_sm__DOT____Vcellout__vx_bank_valid__bank_valids)) + | (0xfffffc00U & (((IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__vx_priority_encoder_sm__DOT__use_valid) + << 8U) & ((2U == (3U + & ((vlSymsp->TOP__cache_simX__DOT__VX_dcache_req.out_cache_driver_in_address[3U] + << 0x1eU) + | (vlSymsp->TOP__cache_simX__DOT__VX_dcache_req.out_cache_driver_in_address[2U] + >> 2U)))) + << 0xaU)))); + vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__vx_priority_encoder_sm__DOT____Vcellout__vx_bank_valid__bank_valids + = ((0xf7ffU & (IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__vx_priority_encoder_sm__DOT____Vcellout__vx_bank_valid__bank_valids)) + | (0xfffff800U & (((IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__vx_priority_encoder_sm__DOT__use_valid) + << 8U) & ((2U == (3U + & (vlSymsp->TOP__cache_simX__DOT__VX_dcache_req.out_cache_driver_in_address[3U] + >> 2U))) + << 0xbU)))); + vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__vx_priority_encoder_sm__DOT____Vcellout__vx_bank_valid__bank_valids + = ((0xefffU & (IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__vx_priority_encoder_sm__DOT____Vcellout__vx_bank_valid__bank_valids)) + | (((IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__vx_priority_encoder_sm__DOT__use_valid) + & (3U == (3U & ((vlSymsp->TOP__cache_simX__DOT__VX_dcache_req.out_cache_driver_in_address[1U] + << 0x1eU) | (vlSymsp->TOP__cache_simX__DOT__VX_dcache_req.out_cache_driver_in_address[0U] + >> 2U))))) + << 0xcU)); + vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__vx_priority_encoder_sm__DOT____Vcellout__vx_bank_valid__bank_valids + = ((0xdfffU & (IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__vx_priority_encoder_sm__DOT____Vcellout__vx_bank_valid__bank_valids)) + | (0xffffe000U & (((IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__vx_priority_encoder_sm__DOT__use_valid) + << 0xcU) & ((3U == (3U + & ((vlSymsp->TOP__cache_simX__DOT__VX_dcache_req.out_cache_driver_in_address[2U] + << 0x1eU) + | (vlSymsp->TOP__cache_simX__DOT__VX_dcache_req.out_cache_driver_in_address[1U] + >> 2U)))) + << 0xdU)))); + vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__vx_priority_encoder_sm__DOT____Vcellout__vx_bank_valid__bank_valids + = ((0xbfffU & (IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__vx_priority_encoder_sm__DOT____Vcellout__vx_bank_valid__bank_valids)) + | (0xffffc000U & (((IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__vx_priority_encoder_sm__DOT__use_valid) + << 0xcU) & ((3U == (3U + & ((vlSymsp->TOP__cache_simX__DOT__VX_dcache_req.out_cache_driver_in_address[3U] + << 0x1eU) + | (vlSymsp->TOP__cache_simX__DOT__VX_dcache_req.out_cache_driver_in_address[2U] + >> 2U)))) + << 0xeU)))); + vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__vx_priority_encoder_sm__DOT____Vcellout__vx_bank_valid__bank_valids + = ((0x7fffU & (IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__vx_priority_encoder_sm__DOT____Vcellout__vx_bank_valid__bank_valids)) + | (0xffff8000U & (((IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__vx_priority_encoder_sm__DOT__use_valid) + << 0xcU) & ((3U == (3U + & (vlSymsp->TOP__cache_simX__DOT__VX_dcache_req.out_cache_driver_in_address[3U] + >> 2U))) + << 0xfU)))); + vlTOPp->__Vtableidx6 = (0xfU & (IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT____Vcellout__multip_banks__thread_track_banks)); + vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT____Vcellout__genblk1__BRA__0__KET____DOT__choose_thread__index + = vlTOPp->__Vtable6_cache_simX__DOT__dmem_controller__DOT__dcache__DOT____Vcellout__genblk1__BRA__0__KET____DOT__choose_thread__index + [vlTOPp->__Vtableidx6]; + vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT____Vcellout__genblk1__BRA__0__KET____DOT__choose_thread__found + = vlTOPp->__Vtable6_cache_simX__DOT__dmem_controller__DOT__dcache__DOT____Vcellout__genblk1__BRA__0__KET____DOT__choose_thread__found + [vlTOPp->__Vtableidx6]; + vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk1__BRA__0__KET____DOT__choose_thread__DOT__i + = vlTOPp->__Vtable6_cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk1__BRA__0__KET____DOT__choose_thread__DOT__i + [vlTOPp->__Vtableidx6]; + vlTOPp->__Vtableidx7 = (0xfU & ((IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT____Vcellout__multip_banks__thread_track_banks) + >> 4U)); + vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT____Vcellout__genblk1__BRA__1__KET____DOT__choose_thread__index + = vlTOPp->__Vtable7_cache_simX__DOT__dmem_controller__DOT__dcache__DOT____Vcellout__genblk1__BRA__1__KET____DOT__choose_thread__index + [vlTOPp->__Vtableidx7]; + vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT____Vcellout__genblk1__BRA__1__KET____DOT__choose_thread__found + = vlTOPp->__Vtable7_cache_simX__DOT__dmem_controller__DOT__dcache__DOT____Vcellout__genblk1__BRA__1__KET____DOT__choose_thread__found + [vlTOPp->__Vtableidx7]; + vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk1__BRA__1__KET____DOT__choose_thread__DOT__i + = vlTOPp->__Vtable7_cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk1__BRA__1__KET____DOT__choose_thread__DOT__i + [vlTOPp->__Vtableidx7]; + vlTOPp->__Vtableidx8 = (0xfU & ((IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT____Vcellout__multip_banks__thread_track_banks) + >> 8U)); + vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT____Vcellout__genblk1__BRA__2__KET____DOT__choose_thread__index + = vlTOPp->__Vtable8_cache_simX__DOT__dmem_controller__DOT__dcache__DOT____Vcellout__genblk1__BRA__2__KET____DOT__choose_thread__index + [vlTOPp->__Vtableidx8]; + vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT____Vcellout__genblk1__BRA__2__KET____DOT__choose_thread__found + = vlTOPp->__Vtable8_cache_simX__DOT__dmem_controller__DOT__dcache__DOT____Vcellout__genblk1__BRA__2__KET____DOT__choose_thread__found + [vlTOPp->__Vtableidx8]; + vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk1__BRA__2__KET____DOT__choose_thread__DOT__i + = vlTOPp->__Vtable8_cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk1__BRA__2__KET____DOT__choose_thread__DOT__i + [vlTOPp->__Vtableidx8]; + vlTOPp->__Vtableidx9 = (0xfU & ((IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT____Vcellout__multip_banks__thread_track_banks) + >> 0xcU)); + vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT____Vcellout__genblk1__BRA__3__KET____DOT__choose_thread__index + = vlTOPp->__Vtable9_cache_simX__DOT__dmem_controller__DOT__dcache__DOT____Vcellout__genblk1__BRA__3__KET____DOT__choose_thread__index + [vlTOPp->__Vtableidx9]; + vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT____Vcellout__genblk1__BRA__3__KET____DOT__choose_thread__found + = vlTOPp->__Vtable9_cache_simX__DOT__dmem_controller__DOT__dcache__DOT____Vcellout__genblk1__BRA__3__KET____DOT__choose_thread__found + [vlTOPp->__Vtableidx9]; + vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk1__BRA__3__KET____DOT__choose_thread__DOT__i + = vlTOPp->__Vtable9_cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk1__BRA__3__KET____DOT__choose_thread__DOT__i + [vlTOPp->__Vtableidx9]; + vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__write_from_mem + = ((2U == (IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__state)) + & (IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__use_valid_in)); + vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__access + = ((0U == (IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__state)) + & (IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__use_valid_in)); + vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__sb_mask + = ((0U == (3U & vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_addr)) + ? 1U : ((1U == (3U & vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_addr)) + ? 2U : ((2U == (3U & vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_addr)) + ? 4U : 8U))); + vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__data_structures__DOT____Vcellout__each_way__BRA__0__KET____DOT__data_structures__dirty_use + = vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__dirty + [(0x1fU & (vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_addr + >> 4U))]; + vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__data_structures__DOT____Vcellout__each_way__BRA__1__KET____DOT__data_structures__dirty_use + = vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__data_structures__DOT__each_way__BRA__1__KET____DOT__data_structures__DOT__dirty + [(0x1fU & (vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_addr + >> 4U))]; + vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__data_structures__DOT__data_use_per_way[0U] + = vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__data + [(0x1fU & (vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_addr + >> 4U))][0U]; + vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__data_structures__DOT__data_use_per_way[1U] + = vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__data + [(0x1fU & (vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_addr + >> 4U))][1U]; + vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__data_structures__DOT__data_use_per_way[2U] + = vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__data + [(0x1fU & (vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_addr + >> 4U))][2U]; + vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__data_structures__DOT__data_use_per_way[3U] + = vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__data + [(0x1fU & (vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_addr + >> 4U))][3U]; + vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__data_structures__DOT__data_use_per_way[4U] + = vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__data_structures__DOT__each_way__BRA__1__KET____DOT__data_structures__DOT__data + [(0x1fU & (vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_addr + >> 4U))][0U]; + vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__data_structures__DOT__data_use_per_way[5U] + = vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__data_structures__DOT__each_way__BRA__1__KET____DOT__data_structures__DOT__data + [(0x1fU & (vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_addr + >> 4U))][1U]; + vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__data_structures__DOT__data_use_per_way[6U] + = vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__data_structures__DOT__each_way__BRA__1__KET____DOT__data_structures__DOT__data + [(0x1fU & (vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_addr + >> 4U))][2U]; + vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__data_structures__DOT__data_use_per_way[7U] + = vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__data_structures__DOT__each_way__BRA__1__KET____DOT__data_structures__DOT__data + [(0x1fU & (vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_addr + >> 4U))][3U]; + vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__data_structures__DOT__tag_use_per_way + = ((VL_ULL(0x3fffff800000) & vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__data_structures__DOT__tag_use_per_way) + | (IData)((IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__tag + [(0x1fU & (vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_addr + >> 4U))]))); + vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__data_structures__DOT__tag_use_per_way + = ((VL_ULL(0x7fffff) & vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__data_structures__DOT__tag_use_per_way) + | ((QData)((IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__data_structures__DOT__each_way__BRA__1__KET____DOT__data_structures__DOT__tag + [(0x1fU & (vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_addr + >> 4U))])) + << 0x17U)); + vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__data_structures__DOT__valid_use_per_way + = ((2U & (IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__data_structures__DOT__valid_use_per_way)) + | vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__valid + [(0x1fU & (vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_addr + >> 4U))]); + vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__data_structures__DOT__valid_use_per_way + = ((1U & (IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__data_structures__DOT__valid_use_per_way)) + | (vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__data_structures__DOT__each_way__BRA__1__KET____DOT__data_structures__DOT__valid + [(0x1fU & (vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_addr + >> 4U))] << 1U)); + vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__vx_priority_encoder_sm__DOT__genblk1__BRA__0__KET____DOT__num_valids = 0U; + if ((8U & (IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__vx_priority_encoder_sm__DOT____Vcellout__vx_bank_valid__bank_valids))) { + vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__vx_priority_encoder_sm__DOT__genblk1__BRA__0__KET____DOT__num_valids + = (7U & ((IData)(1U) + (IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__vx_priority_encoder_sm__DOT__genblk1__BRA__0__KET____DOT__num_valids))); + } + if ((4U & (IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__vx_priority_encoder_sm__DOT____Vcellout__vx_bank_valid__bank_valids))) { + vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__vx_priority_encoder_sm__DOT__genblk1__BRA__0__KET____DOT__num_valids + = (7U & ((IData)(1U) + (IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__vx_priority_encoder_sm__DOT__genblk1__BRA__0__KET____DOT__num_valids))); + } + if ((2U & (IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__vx_priority_encoder_sm__DOT____Vcellout__vx_bank_valid__bank_valids))) { + vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__vx_priority_encoder_sm__DOT__genblk1__BRA__0__KET____DOT__num_valids + = (7U & ((IData)(1U) + (IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__vx_priority_encoder_sm__DOT__genblk1__BRA__0__KET____DOT__num_valids))); + } + if ((1U & (IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__vx_priority_encoder_sm__DOT____Vcellout__vx_bank_valid__bank_valids))) { + vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__vx_priority_encoder_sm__DOT__genblk1__BRA__0__KET____DOT__num_valids + = (7U & ((IData)(1U) + (IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__vx_priority_encoder_sm__DOT__genblk1__BRA__0__KET____DOT__num_valids))); + } + vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__vx_priority_encoder_sm__DOT__genblk1__BRA__1__KET____DOT__num_valids = 0U; + if ((0x80U & (IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__vx_priority_encoder_sm__DOT____Vcellout__vx_bank_valid__bank_valids))) { + vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__vx_priority_encoder_sm__DOT__genblk1__BRA__1__KET____DOT__num_valids + = (7U & ((IData)(1U) + (IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__vx_priority_encoder_sm__DOT__genblk1__BRA__1__KET____DOT__num_valids))); + } + if ((0x40U & (IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__vx_priority_encoder_sm__DOT____Vcellout__vx_bank_valid__bank_valids))) { + vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__vx_priority_encoder_sm__DOT__genblk1__BRA__1__KET____DOT__num_valids + = (7U & ((IData)(1U) + (IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__vx_priority_encoder_sm__DOT__genblk1__BRA__1__KET____DOT__num_valids))); + } + if ((0x20U & (IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__vx_priority_encoder_sm__DOT____Vcellout__vx_bank_valid__bank_valids))) { + vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__vx_priority_encoder_sm__DOT__genblk1__BRA__1__KET____DOT__num_valids + = (7U & ((IData)(1U) + (IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__vx_priority_encoder_sm__DOT__genblk1__BRA__1__KET____DOT__num_valids))); + } + if ((0x10U & (IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__vx_priority_encoder_sm__DOT____Vcellout__vx_bank_valid__bank_valids))) { + vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__vx_priority_encoder_sm__DOT__genblk1__BRA__1__KET____DOT__num_valids + = (7U & ((IData)(1U) + (IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__vx_priority_encoder_sm__DOT__genblk1__BRA__1__KET____DOT__num_valids))); + } + vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__vx_priority_encoder_sm__DOT__genblk1__BRA__2__KET____DOT__num_valids = 0U; + if ((0x800U & (IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__vx_priority_encoder_sm__DOT____Vcellout__vx_bank_valid__bank_valids))) { + vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__vx_priority_encoder_sm__DOT__genblk1__BRA__2__KET____DOT__num_valids + = (7U & ((IData)(1U) + (IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__vx_priority_encoder_sm__DOT__genblk1__BRA__2__KET____DOT__num_valids))); + } + if ((0x400U & (IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__vx_priority_encoder_sm__DOT____Vcellout__vx_bank_valid__bank_valids))) { + vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__vx_priority_encoder_sm__DOT__genblk1__BRA__2__KET____DOT__num_valids + = (7U & ((IData)(1U) + (IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__vx_priority_encoder_sm__DOT__genblk1__BRA__2__KET____DOT__num_valids))); + } + if ((0x200U & (IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__vx_priority_encoder_sm__DOT____Vcellout__vx_bank_valid__bank_valids))) { + vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__vx_priority_encoder_sm__DOT__genblk1__BRA__2__KET____DOT__num_valids + = (7U & ((IData)(1U) + (IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__vx_priority_encoder_sm__DOT__genblk1__BRA__2__KET____DOT__num_valids))); + } + if ((0x100U & (IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__vx_priority_encoder_sm__DOT____Vcellout__vx_bank_valid__bank_valids))) { + vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__vx_priority_encoder_sm__DOT__genblk1__BRA__2__KET____DOT__num_valids + = (7U & ((IData)(1U) + (IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__vx_priority_encoder_sm__DOT__genblk1__BRA__2__KET____DOT__num_valids))); + } + vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__vx_priority_encoder_sm__DOT__genblk1__BRA__3__KET____DOT__num_valids = 0U; + if ((0x8000U & (IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__vx_priority_encoder_sm__DOT____Vcellout__vx_bank_valid__bank_valids))) { + vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__vx_priority_encoder_sm__DOT__genblk1__BRA__3__KET____DOT__num_valids + = (7U & ((IData)(1U) + (IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__vx_priority_encoder_sm__DOT__genblk1__BRA__3__KET____DOT__num_valids))); + } + if ((0x4000U & (IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__vx_priority_encoder_sm__DOT____Vcellout__vx_bank_valid__bank_valids))) { + vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__vx_priority_encoder_sm__DOT__genblk1__BRA__3__KET____DOT__num_valids + = (7U & ((IData)(1U) + (IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__vx_priority_encoder_sm__DOT__genblk1__BRA__3__KET____DOT__num_valids))); + } + if ((0x2000U & (IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__vx_priority_encoder_sm__DOT____Vcellout__vx_bank_valid__bank_valids))) { + vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__vx_priority_encoder_sm__DOT__genblk1__BRA__3__KET____DOT__num_valids + = (7U & ((IData)(1U) + (IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__vx_priority_encoder_sm__DOT__genblk1__BRA__3__KET____DOT__num_valids))); + } + if ((0x1000U & (IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__vx_priority_encoder_sm__DOT____Vcellout__vx_bank_valid__bank_valids))) { + vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__vx_priority_encoder_sm__DOT__genblk1__BRA__3__KET____DOT__num_valids + = (7U & ((IData)(1U) + (IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__vx_priority_encoder_sm__DOT__genblk1__BRA__3__KET____DOT__num_valids))); + } + vlTOPp->__Vtableidx1 = (0xfU & (IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__vx_priority_encoder_sm__DOT____Vcellout__vx_bank_valid__bank_valids)); + vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__vx_priority_encoder_sm__DOT____Vcellout__genblk2__BRA__0__KET____DOT__vx_priority_encoder__index + = vlTOPp->__Vtable1_cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__vx_priority_encoder_sm__DOT____Vcellout__genblk2__BRA__0__KET____DOT__vx_priority_encoder__index + [vlTOPp->__Vtableidx1]; + vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__vx_priority_encoder_sm__DOT____Vcellout__genblk2__BRA__0__KET____DOT__vx_priority_encoder__found + = vlTOPp->__Vtable1_cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__vx_priority_encoder_sm__DOT____Vcellout__genblk2__BRA__0__KET____DOT__vx_priority_encoder__found + [vlTOPp->__Vtableidx1]; + vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__vx_priority_encoder_sm__DOT__genblk2__BRA__0__KET____DOT__vx_priority_encoder__DOT__i + = vlTOPp->__Vtable1_cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__vx_priority_encoder_sm__DOT__genblk2__BRA__0__KET____DOT__vx_priority_encoder__DOT__i + [vlTOPp->__Vtableidx1]; + vlTOPp->__Vtableidx2 = (0xfU & ((IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__vx_priority_encoder_sm__DOT____Vcellout__vx_bank_valid__bank_valids) + >> 4U)); + vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__vx_priority_encoder_sm__DOT____Vcellout__genblk2__BRA__1__KET____DOT__vx_priority_encoder__index + = vlTOPp->__Vtable2_cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__vx_priority_encoder_sm__DOT____Vcellout__genblk2__BRA__1__KET____DOT__vx_priority_encoder__index + [vlTOPp->__Vtableidx2]; + vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__vx_priority_encoder_sm__DOT____Vcellout__genblk2__BRA__1__KET____DOT__vx_priority_encoder__found + = vlTOPp->__Vtable2_cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__vx_priority_encoder_sm__DOT____Vcellout__genblk2__BRA__1__KET____DOT__vx_priority_encoder__found + [vlTOPp->__Vtableidx2]; + vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__vx_priority_encoder_sm__DOT__genblk2__BRA__1__KET____DOT__vx_priority_encoder__DOT__i + = vlTOPp->__Vtable2_cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__vx_priority_encoder_sm__DOT__genblk2__BRA__1__KET____DOT__vx_priority_encoder__DOT__i + [vlTOPp->__Vtableidx2]; + vlTOPp->__Vtableidx3 = (0xfU & ((IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__vx_priority_encoder_sm__DOT____Vcellout__vx_bank_valid__bank_valids) + >> 8U)); + vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__vx_priority_encoder_sm__DOT____Vcellout__genblk2__BRA__2__KET____DOT__vx_priority_encoder__index + = vlTOPp->__Vtable3_cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__vx_priority_encoder_sm__DOT____Vcellout__genblk2__BRA__2__KET____DOT__vx_priority_encoder__index + [vlTOPp->__Vtableidx3]; + vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__vx_priority_encoder_sm__DOT____Vcellout__genblk2__BRA__2__KET____DOT__vx_priority_encoder__found + = vlTOPp->__Vtable3_cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__vx_priority_encoder_sm__DOT____Vcellout__genblk2__BRA__2__KET____DOT__vx_priority_encoder__found + [vlTOPp->__Vtableidx3]; + vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__vx_priority_encoder_sm__DOT__genblk2__BRA__2__KET____DOT__vx_priority_encoder__DOT__i + = vlTOPp->__Vtable3_cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__vx_priority_encoder_sm__DOT__genblk2__BRA__2__KET____DOT__vx_priority_encoder__DOT__i + [vlTOPp->__Vtableidx3]; + vlTOPp->__Vtableidx4 = (0xfU & ((IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__vx_priority_encoder_sm__DOT____Vcellout__vx_bank_valid__bank_valids) + >> 0xcU)); + vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__vx_priority_encoder_sm__DOT____Vcellout__genblk2__BRA__3__KET____DOT__vx_priority_encoder__index + = vlTOPp->__Vtable4_cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__vx_priority_encoder_sm__DOT____Vcellout__genblk2__BRA__3__KET____DOT__vx_priority_encoder__index + [vlTOPp->__Vtableidx4]; + vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__vx_priority_encoder_sm__DOT____Vcellout__genblk2__BRA__3__KET____DOT__vx_priority_encoder__found + = vlTOPp->__Vtable4_cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__vx_priority_encoder_sm__DOT____Vcellout__genblk2__BRA__3__KET____DOT__vx_priority_encoder__found + [vlTOPp->__Vtableidx4]; + vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__vx_priority_encoder_sm__DOT__genblk2__BRA__3__KET____DOT__vx_priority_encoder__DOT__i + = vlTOPp->__Vtable4_cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__vx_priority_encoder_sm__DOT__genblk2__BRA__3__KET____DOT__vx_priority_encoder__DOT__i + [vlTOPp->__Vtableidx4]; + vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT__valid_per_bank + = ((0xeU & (IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT__valid_per_bank)) + | (IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT____Vcellout__genblk1__BRA__0__KET____DOT__choose_thread__found)); + vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT__use_mask_per_bank + = ((0xfff0U & (IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT__use_mask_per_bank)) + | ((IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT____Vcellout__genblk1__BRA__0__KET____DOT__choose_thread__found) + ? (0xfU & ((IData)(1U) << (IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT____Vcellout__genblk1__BRA__0__KET____DOT__choose_thread__index))) + : 0U)); + vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT__index_per_bank + = ((0xfcU & (IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT__index_per_bank)) + | (IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT____Vcellout__genblk1__BRA__0__KET____DOT__choose_thread__index)); + vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT__valid_per_bank + = ((0xdU & (IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT__valid_per_bank)) + | ((IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT____Vcellout__genblk1__BRA__1__KET____DOT__choose_thread__found) + << 1U)); + vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT__use_mask_per_bank + = ((0xff0fU & (IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT__use_mask_per_bank)) + | (((IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT____Vcellout__genblk1__BRA__1__KET____DOT__choose_thread__found) + ? (0xfU & ((IData)(1U) << (IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT____Vcellout__genblk1__BRA__1__KET____DOT__choose_thread__index))) + : 0U) << 4U)); + vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT__index_per_bank + = ((0xf3U & (IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT__index_per_bank)) + | ((IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT____Vcellout__genblk1__BRA__1__KET____DOT__choose_thread__index) + << 2U)); + vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT__valid_per_bank + = ((0xbU & (IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT__valid_per_bank)) + | ((IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT____Vcellout__genblk1__BRA__2__KET____DOT__choose_thread__found) + << 2U)); + vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT__use_mask_per_bank + = ((0xf0ffU & (IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT__use_mask_per_bank)) + | (((IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT____Vcellout__genblk1__BRA__2__KET____DOT__choose_thread__found) + ? (0xfU & ((IData)(1U) << (IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT____Vcellout__genblk1__BRA__2__KET____DOT__choose_thread__index))) + : 0U) << 8U)); + vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT__index_per_bank + = ((0xcfU & (IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT__index_per_bank)) + | ((IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT____Vcellout__genblk1__BRA__2__KET____DOT__choose_thread__index) + << 4U)); + vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT__valid_per_bank + = ((7U & (IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT__valid_per_bank)) + | ((IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT____Vcellout__genblk1__BRA__3__KET____DOT__choose_thread__found) + << 3U)); + vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT__use_mask_per_bank + = ((0xfffU & (IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT__use_mask_per_bank)) + | (((IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT____Vcellout__genblk1__BRA__3__KET____DOT__choose_thread__found) + ? (0xfU & ((IData)(1U) << (IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT____Vcellout__genblk1__BRA__3__KET____DOT__choose_thread__index))) + : 0U) << 0xcU)); + vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT__index_per_bank + = ((0x3fU & (IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT__index_per_bank)) + | ((IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT____Vcellout__genblk1__BRA__3__KET____DOT__choose_thread__index) + << 6U)); + vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__data_write[0U] + = ((IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__write_from_mem) + ? vlSymsp->TOP__cache_simX__DOT__VX_dram_req_rsp_icache.i_m_readdata[0U] + : 0U); + vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__data_write[1U] + = ((IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__write_from_mem) + ? vlSymsp->TOP__cache_simX__DOT__VX_dram_req_rsp_icache.i_m_readdata[1U] + : 0U); + vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__data_write[2U] + = ((IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__write_from_mem) + ? vlSymsp->TOP__cache_simX__DOT__VX_dram_req_rsp_icache.i_m_readdata[2U] + : 0U); + vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__data_write[3U] + = ((IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__write_from_mem) + ? vlSymsp->TOP__cache_simX__DOT__VX_dram_req_rsp_icache.i_m_readdata[3U] + : 0U); + vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__we + = ((0xfff0U & (IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__we)) + | ((IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__write_from_mem) + ? 0xfU : 0U)); + vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__we + = ((0xff0fU & (IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__we)) + | (((IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__write_from_mem) + ? 0xfU : 0U) << 4U)); + vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__we + = ((0xf0ffU & (IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__we)) + | (((IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__write_from_mem) + ? 0xfU : 0U) << 8U)); + vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__we + = ((0xfffU & (IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__we)) + | (((IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__write_from_mem) + ? 0xfU : 0U) << 0xcU)); + vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__data_structures__DOT__dirty_use_per_way + = ((2U & (IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__data_structures__DOT__dirty_use_per_way)) + | (IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__data_structures__DOT____Vcellout__each_way__BRA__0__KET____DOT__data_structures__dirty_use)); + vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__data_structures__DOT__dirty_use_per_way + = ((1U & (IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__data_structures__DOT__dirty_use_per_way)) + | ((IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__data_structures__DOT____Vcellout__each_way__BRA__1__KET____DOT__data_structures__dirty_use) + << 1U)); + vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__data_structures__DOT__invalid_found = 0U; + if ((1U & (~ ((IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__data_structures__DOT__valid_use_per_way) + >> 1U)))) { + vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__data_structures__DOT__invalid_found = 1U; + } + if ((1U & (~ (IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__data_structures__DOT__valid_use_per_way)))) { + vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__data_structures__DOT__invalid_found = 1U; + } + vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__data_structures__DOT__invalid_index = 0U; + if ((1U & (~ ((IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__data_structures__DOT__valid_use_per_way) + >> 1U)))) { + vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__data_structures__DOT__invalid_index = 1U; + } + if ((1U & (~ (IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__data_structures__DOT__valid_use_per_way)))) { + vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__data_structures__DOT__invalid_index = 0U; + } + vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__data_structures__DOT__hit_per_way + = ((2U & (IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__data_structures__DOT__hit_per_way)) + | (((IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__data_structures__DOT__valid_use_per_way) + & ((0x7fffffU & (IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__data_structures__DOT__tag_use_per_way)) + == (0x7fffffU & (vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_addr + >> 9U)))) ? 1U : 0U)); + vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__data_structures__DOT__hit_per_way + = ((1U & (IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__data_structures__DOT__hit_per_way)) + | (((((IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__data_structures__DOT__valid_use_per_way) + >> 1U) & ((0x7fffffU & (IData)((vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__data_structures__DOT__tag_use_per_way + >> 0x17U))) + == (0x7fffffU & (vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_addr + >> 9U)))) + ? 1U : 0U) << 1U)); + vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__vx_priority_encoder_sm__DOT__more_than_one_valid + = ((0xeU & (IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__vx_priority_encoder_sm__DOT__more_than_one_valid)) + | (1U < (IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__vx_priority_encoder_sm__DOT__genblk1__BRA__0__KET____DOT__num_valids))); + vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__vx_priority_encoder_sm__DOT__more_than_one_valid + = ((0xdU & (IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__vx_priority_encoder_sm__DOT__more_than_one_valid)) + | ((1U < (IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__vx_priority_encoder_sm__DOT__genblk1__BRA__1__KET____DOT__num_valids)) + << 1U)); + vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__vx_priority_encoder_sm__DOT__more_than_one_valid + = ((0xbU & (IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__vx_priority_encoder_sm__DOT__more_than_one_valid)) + | ((1U < (IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__vx_priority_encoder_sm__DOT__genblk1__BRA__2__KET____DOT__num_valids)) + << 2U)); + vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__vx_priority_encoder_sm__DOT__more_than_one_valid + = ((7U & (IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__vx_priority_encoder_sm__DOT__more_than_one_valid)) + | ((1U < (IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__vx_priority_encoder_sm__DOT__genblk1__BRA__3__KET____DOT__num_valids)) + << 3U)); + vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__vx_priority_encoder_sm__DOT__internal_req_num + = ((0xfcU & (IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__vx_priority_encoder_sm__DOT__internal_req_num)) + | (IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__vx_priority_encoder_sm__DOT____Vcellout__genblk2__BRA__0__KET____DOT__vx_priority_encoder__index)); + vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__vx_priority_encoder_sm__DOT__internal_out_valid + = ((0xeU & (IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__vx_priority_encoder_sm__DOT__internal_out_valid)) + | (IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__vx_priority_encoder_sm__DOT____Vcellout__genblk2__BRA__0__KET____DOT__vx_priority_encoder__found)); + vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__vx_priority_encoder_sm__DOT__internal_req_num + = ((0xf3U & (IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__vx_priority_encoder_sm__DOT__internal_req_num)) + | ((IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__vx_priority_encoder_sm__DOT____Vcellout__genblk2__BRA__1__KET____DOT__vx_priority_encoder__index) + << 2U)); + vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__vx_priority_encoder_sm__DOT__internal_out_valid + = ((0xdU & (IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__vx_priority_encoder_sm__DOT__internal_out_valid)) + | ((IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__vx_priority_encoder_sm__DOT____Vcellout__genblk2__BRA__1__KET____DOT__vx_priority_encoder__found) + << 1U)); + vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__vx_priority_encoder_sm__DOT__internal_req_num + = ((0xcfU & (IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__vx_priority_encoder_sm__DOT__internal_req_num)) + | ((IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__vx_priority_encoder_sm__DOT____Vcellout__genblk2__BRA__2__KET____DOT__vx_priority_encoder__index) + << 4U)); + vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__vx_priority_encoder_sm__DOT__internal_out_valid + = ((0xbU & (IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__vx_priority_encoder_sm__DOT__internal_out_valid)) + | ((IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__vx_priority_encoder_sm__DOT____Vcellout__genblk2__BRA__2__KET____DOT__vx_priority_encoder__found) + << 2U)); + vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__vx_priority_encoder_sm__DOT__internal_req_num + = ((0x3fU & (IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__vx_priority_encoder_sm__DOT__internal_req_num)) + | ((IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__vx_priority_encoder_sm__DOT____Vcellout__genblk2__BRA__3__KET____DOT__vx_priority_encoder__index) + << 6U)); + vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__vx_priority_encoder_sm__DOT__internal_out_valid + = ((7U & (IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__vx_priority_encoder_sm__DOT__internal_out_valid)) + | ((IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__vx_priority_encoder_sm__DOT____Vcellout__genblk2__BRA__3__KET____DOT__vx_priority_encoder__found) + << 3U)); + vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__0__KET____DOT__use_valid_in + = (((2U == (IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT__state)) + & (IData)(vlTOPp->cache_simX__DOT__dcache_i_m_ready)) + | ((~ ((2U == (IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT__state)) + & (~ (IData)(vlTOPp->cache_simX__DOT__dcache_i_m_ready)))) + & ((1U != (IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT__state)) + & (IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT__valid_per_bank)))); + vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__1__KET____DOT__use_valid_in + = (((2U == (IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT__state)) + & (IData)(vlTOPp->cache_simX__DOT__dcache_i_m_ready)) + | ((~ ((2U == (IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT__state)) + & (~ (IData)(vlTOPp->cache_simX__DOT__dcache_i_m_ready)))) + & ((1U != (IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT__state)) + & ((IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT__valid_per_bank) + >> 1U)))); + vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__2__KET____DOT__use_valid_in + = (((2U == (IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT__state)) + & (IData)(vlTOPp->cache_simX__DOT__dcache_i_m_ready)) + | ((~ ((2U == (IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT__state)) + & (~ (IData)(vlTOPp->cache_simX__DOT__dcache_i_m_ready)))) + & ((1U != (IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT__state)) + & ((IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT__valid_per_bank) + >> 2U)))); + vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__3__KET____DOT__use_valid_in + = (((2U == (IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT__state)) + & (IData)(vlTOPp->cache_simX__DOT__dcache_i_m_ready)) + | ((~ ((2U == (IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT__state)) + & (~ (IData)(vlTOPp->cache_simX__DOT__dcache_i_m_ready)))) + & ((1U != (IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT__state)) + & ((IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT__valid_per_bank) + >> 3U)))); + vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__0__KET____DOT__bank_addr + = ((1U == (IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT__state)) + ? vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT__miss_addr + : ((2U == (IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT__state)) + ? vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT__miss_addr + : vlSymsp->TOP__cache_simX__DOT__VX_dcache_req.out_cache_driver_in_address[ + (3U & (IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT__index_per_bank))])); + vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__1__KET____DOT__bank_addr + = ((1U == (IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT__state)) + ? vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT__miss_addr + : ((2U == (IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT__state)) + ? vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT__miss_addr + : vlSymsp->TOP__cache_simX__DOT__VX_dcache_req.out_cache_driver_in_address[ + (3U & ((IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT__index_per_bank) + >> 2U))])); + vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__2__KET____DOT__bank_addr + = ((1U == (IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT__state)) + ? vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT__miss_addr + : ((2U == (IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT__state)) + ? vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT__miss_addr + : vlSymsp->TOP__cache_simX__DOT__VX_dcache_req.out_cache_driver_in_address[ + (3U & ((IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT__index_per_bank) + >> 4U))])); + vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__3__KET____DOT__bank_addr + = ((1U == (IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT__state)) + ? vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT__miss_addr + : ((2U == (IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT__state)) + ? vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT__miss_addr + : vlSymsp->TOP__cache_simX__DOT__VX_dcache_req.out_cache_driver_in_address[ + (3U & ((IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT__index_per_bank) + >> 6U))])); + vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__data_structures__DOT__data_write_per_way[0U] + = vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__data_write[0U]; + vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__data_structures__DOT__data_write_per_way[1U] + = vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__data_write[1U]; + vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__data_structures__DOT__data_write_per_way[2U] + = vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__data_write[2U]; + vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__data_structures__DOT__data_write_per_way[3U] + = vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__data_write[3U]; + vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__data_structures__DOT__data_write_per_way[4U] + = vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__data_write[0U]; + vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__data_structures__DOT__data_write_per_way[5U] + = vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__data_write[1U]; + vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__data_structures__DOT__data_write_per_way[6U] + = vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__data_write[2U]; + vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__data_structures__DOT__data_write_per_way[7U] + = vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__data_write[3U]; + vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__data_structures__DOT__genblk1__DOT__way_indexing__DOT__found = 0U; + if ((2U & (IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__data_structures__DOT__hit_per_way))) { + vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__data_structures__DOT__genblk1__DOT__way_indexing__DOT__found = 1U; + } + if ((1U & (IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__data_structures__DOT__hit_per_way))) { + vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__data_structures__DOT__genblk1__DOT__way_indexing__DOT__found = 1U; + } + vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__data_structures__DOT__way_index = 0U; + if ((2U & (IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__data_structures__DOT__hit_per_way))) { + vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__data_structures__DOT__way_index = 1U; + } + if ((1U & (IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__data_structures__DOT__hit_per_way))) { + vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__data_structures__DOT__way_index = 0U; + } + vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__vx_priority_encoder_sm__DOT__serviced = 0U; + vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__vx_priority_encoder_sm__DOT__serviced + = ((IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__vx_priority_encoder_sm__DOT__serviced) + | ((IData)(1U) << (3U & (IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__vx_priority_encoder_sm__DOT__internal_req_num)))); + vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__vx_priority_encoder_sm__DOT__serviced + = ((IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__vx_priority_encoder_sm__DOT__serviced) + | ((IData)(1U) << (3U & ((IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__vx_priority_encoder_sm__DOT__internal_req_num) + >> 2U)))); + vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__vx_priority_encoder_sm__DOT__serviced + = ((IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__vx_priority_encoder_sm__DOT__serviced) + | ((IData)(1U) << (3U & ((IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__vx_priority_encoder_sm__DOT__internal_req_num) + >> 4U)))); + vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__vx_priority_encoder_sm__DOT__serviced + = ((IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__vx_priority_encoder_sm__DOT__serviced) + | ((IData)(1U) << (3U & ((IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__vx_priority_encoder_sm__DOT__internal_req_num) + >> 6U)))); + __Vtemp19[0U] = 0U; + __Vtemp19[1U] = 0U; + __Vtemp19[2U] = 0U; + __Vtemp19[3U] = 0U; + vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT____Vcellout__vx_priority_encoder_sm__out_data[0U] + = ((1U & (IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__vx_priority_encoder_sm__DOT__internal_out_valid)) + ? __Vtemp19[(3U & (IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__vx_priority_encoder_sm__DOT__internal_req_num))] + : 0U); + __Vtemp20[0U] = 0U; + __Vtemp20[1U] = 0U; + __Vtemp20[2U] = 0U; + __Vtemp20[3U] = 0U; + vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT____Vcellout__vx_priority_encoder_sm__out_data[1U] + = ((2U & (IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__vx_priority_encoder_sm__DOT__internal_out_valid)) + ? __Vtemp20[(3U & ((IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__vx_priority_encoder_sm__DOT__internal_req_num) + >> 2U))] : 0U); + __Vtemp21[0U] = 0U; + __Vtemp21[1U] = 0U; + __Vtemp21[2U] = 0U; + __Vtemp21[3U] = 0U; + vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT____Vcellout__vx_priority_encoder_sm__out_data[2U] + = ((4U & (IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__vx_priority_encoder_sm__DOT__internal_out_valid)) + ? __Vtemp21[(3U & ((IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__vx_priority_encoder_sm__DOT__internal_req_num) + >> 4U))] : 0U); + __Vtemp22[0U] = 0U; + __Vtemp22[1U] = 0U; + __Vtemp22[2U] = 0U; + __Vtemp22[3U] = 0U; + vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT____Vcellout__vx_priority_encoder_sm__out_data[3U] + = ((8U & (IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__vx_priority_encoder_sm__DOT__internal_out_valid)) + ? __Vtemp22[(3U & ((IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__vx_priority_encoder_sm__DOT__internal_req_num) + >> 6U))] : 0U); + vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__genblk2__BRA__0__KET____DOT__shm_write + = ((7U != (IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__sm_driver_in_mem_write)) + & (IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__vx_priority_encoder_sm__DOT__internal_out_valid)); + vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__genblk2__BRA__1__KET____DOT__shm_write + = ((7U != (IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__sm_driver_in_mem_write)) + & ((IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__vx_priority_encoder_sm__DOT__internal_out_valid) + >> 1U)); + vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__genblk2__BRA__2__KET____DOT__shm_write + = ((7U != (IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__sm_driver_in_mem_write)) + & ((IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__vx_priority_encoder_sm__DOT__internal_out_valid) + >> 2U)); + vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__genblk2__BRA__3__KET____DOT__shm_write + = ((7U != (IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__sm_driver_in_mem_write)) + & ((IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__vx_priority_encoder_sm__DOT__internal_out_valid) + >> 3U)); + vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT____Vcellout__vx_priority_encoder_sm__out_address[0U] + = ((1U & (IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__vx_priority_encoder_sm__DOT__internal_out_valid)) + ? vlSymsp->TOP__cache_simX__DOT__VX_dcache_req.out_cache_driver_in_address[ + (3U & (IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__vx_priority_encoder_sm__DOT__internal_req_num))] + : 0U); + vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT____Vcellout__vx_priority_encoder_sm__out_address[1U] + = ((2U & (IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__vx_priority_encoder_sm__DOT__internal_out_valid)) + ? vlSymsp->TOP__cache_simX__DOT__VX_dcache_req.out_cache_driver_in_address[ + (3U & ((IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__vx_priority_encoder_sm__DOT__internal_req_num) + >> 2U))] : 0U); + vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT____Vcellout__vx_priority_encoder_sm__out_address[2U] + = ((4U & (IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__vx_priority_encoder_sm__DOT__internal_out_valid)) + ? vlSymsp->TOP__cache_simX__DOT__VX_dcache_req.out_cache_driver_in_address[ + (3U & ((IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__vx_priority_encoder_sm__DOT__internal_req_num) + >> 4U))] : 0U); + vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT____Vcellout__vx_priority_encoder_sm__out_address[3U] + = ((8U & (IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__vx_priority_encoder_sm__DOT__internal_out_valid)) + ? vlSymsp->TOP__cache_simX__DOT__VX_dcache_req.out_cache_driver_in_address[ + (3U & ((IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__vx_priority_encoder_sm__DOT__internal_req_num) + >> 6U))] : 0U); + vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__data_structures__DOT__way_use_Qual + = ((0U != (IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__state)) + ? (IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__way_to_update) + : (IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__data_structures__DOT__way_index)); + vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__vx_priority_encoder_sm__DOT__serviced_qual + = ((IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__orig_in_valid) + & (IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__vx_priority_encoder_sm__DOT__serviced)); + vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__block_we = 0U; + if ((1U & (IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__vx_priority_encoder_sm__DOT__internal_out_valid))) { + if ((0xffU == (0xffU & ((vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT____Vcellout__vx_priority_encoder_sm__out_address[1U] + << 8U) | (vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT____Vcellout__vx_priority_encoder_sm__out_address[0U] + >> 0x18U))))) { + if ((7U != (IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__sm_driver_in_mem_write))) { + if ((0U != (IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__sm_driver_in_mem_write))) { + if ((1U != (IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__sm_driver_in_mem_write))) { + if ((2U == (IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__sm_driver_in_mem_write))) { + vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__block_we + = ((0xfcU & (IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__block_we)) + | (3U & ((vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT____Vcellout__vx_priority_encoder_sm__out_address[1U] + << 0x1cU) + | (vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT____Vcellout__vx_priority_encoder_sm__out_address[0U] + >> 4U)))); + } + } + } + } + } + } + if ((2U & (IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__vx_priority_encoder_sm__DOT__internal_out_valid))) { + if ((0xffU == (0xffU & ((vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT____Vcellout__vx_priority_encoder_sm__out_address[2U] + << 8U) | (vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT____Vcellout__vx_priority_encoder_sm__out_address[1U] + >> 0x18U))))) { + if ((7U != (IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__sm_driver_in_mem_write))) { + if ((0U != (IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__sm_driver_in_mem_write))) { + if ((1U != (IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__sm_driver_in_mem_write))) { + if ((2U == (IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__sm_driver_in_mem_write))) { + vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__block_we + = ((0xf3U & (IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__block_we)) + | (0xcU & ((vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT____Vcellout__vx_priority_encoder_sm__out_address[2U] + << 0x1eU) + | (0x3ffffffcU + & (vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT____Vcellout__vx_priority_encoder_sm__out_address[1U] + >> 2U))))); + } + } + } + } + } + } + if ((4U & (IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__vx_priority_encoder_sm__DOT__internal_out_valid))) { + if ((0xffU == (0xffU & ((vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT____Vcellout__vx_priority_encoder_sm__out_address[3U] + << 8U) | (vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT____Vcellout__vx_priority_encoder_sm__out_address[2U] + >> 0x18U))))) { + if ((7U != (IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__sm_driver_in_mem_write))) { + if ((0U != (IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__sm_driver_in_mem_write))) { + if ((1U != (IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__sm_driver_in_mem_write))) { + if ((2U == (IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__sm_driver_in_mem_write))) { + vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__block_we + = ((0xcfU & (IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__block_we)) + | (0x30U & vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT____Vcellout__vx_priority_encoder_sm__out_address[2U])); + } + } + } + } + } + } + if ((8U & (IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__vx_priority_encoder_sm__DOT__internal_out_valid))) { + if ((0xffU == (0xffU & (vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT____Vcellout__vx_priority_encoder_sm__out_address[3U] + >> 0x18U)))) { + if ((7U != (IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__sm_driver_in_mem_write))) { + if ((0U != (IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__sm_driver_in_mem_write))) { + if ((1U != (IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__sm_driver_in_mem_write))) { + if ((2U == (IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__sm_driver_in_mem_write))) { + vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__block_we + = ((0x3fU & (IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__block_we)) + | (0xc0U & (vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT____Vcellout__vx_priority_encoder_sm__out_address[3U] + << 2U))); + } + } + } + } + } + } + vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__block_wdata[0U] = 0U; + vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__block_wdata[1U] = 0U; + vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__block_wdata[2U] = 0U; + vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__block_wdata[3U] = 0U; + vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__block_wdata[4U] = 0U; + vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__block_wdata[5U] = 0U; + vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__block_wdata[6U] = 0U; + vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__block_wdata[7U] = 0U; + vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__block_wdata[8U] = 0U; + vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__block_wdata[9U] = 0U; + vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__block_wdata[0xaU] = 0U; + vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__block_wdata[0xbU] = 0U; + vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__block_wdata[0xcU] = 0U; + vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__block_wdata[0xdU] = 0U; + vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__block_wdata[0xeU] = 0U; + vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__block_wdata[0xfU] = 0U; + if ((1U & (IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__vx_priority_encoder_sm__DOT__internal_out_valid))) { + if ((0xffU == (0xffU & ((vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT____Vcellout__vx_priority_encoder_sm__out_address[1U] + << 8U) | (vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT____Vcellout__vx_priority_encoder_sm__out_address[0U] + >> 0x18U))))) { + if ((7U != (IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__sm_driver_in_mem_write))) { + if ((0U != (IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__sm_driver_in_mem_write))) { + if ((1U != (IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__sm_driver_in_mem_write))) { + if ((2U == (IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__sm_driver_in_mem_write))) { + VL_ASSIGNSEL_WIII(32,(0x60U + & (vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT____Vcellout__vx_priority_encoder_sm__out_address[0U] + << 1U)), vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__block_wdata, + vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT____Vcellout__vx_priority_encoder_sm__out_data[0U]); + } + } + } + } + } + } + if ((2U & (IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__vx_priority_encoder_sm__DOT__internal_out_valid))) { + if ((0xffU == (0xffU & ((vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT____Vcellout__vx_priority_encoder_sm__out_address[2U] + << 8U) | (vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT____Vcellout__vx_priority_encoder_sm__out_address[1U] + >> 0x18U))))) { + if ((7U != (IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__sm_driver_in_mem_write))) { + if ((0U != (IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__sm_driver_in_mem_write))) { + if ((1U != (IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__sm_driver_in_mem_write))) { + if ((2U == (IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__sm_driver_in_mem_write))) { + VL_ASSIGNSEL_WIII(32,(0x1ffU + & ((IData)(0x80U) + + + (0x60U + & (vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT____Vcellout__vx_priority_encoder_sm__out_address[1U] + << 1U)))), vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__block_wdata, + vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT____Vcellout__vx_priority_encoder_sm__out_data[1U]); + } + } + } + } + } + } + if ((4U & (IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__vx_priority_encoder_sm__DOT__internal_out_valid))) { + if ((0xffU == (0xffU & ((vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT____Vcellout__vx_priority_encoder_sm__out_address[3U] + << 8U) | (vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT____Vcellout__vx_priority_encoder_sm__out_address[2U] + >> 0x18U))))) { + if ((7U != (IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__sm_driver_in_mem_write))) { + if ((0U != (IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__sm_driver_in_mem_write))) { + if ((1U != (IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__sm_driver_in_mem_write))) { + if ((2U == (IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__sm_driver_in_mem_write))) { + VL_ASSIGNSEL_WIII(32,(0x1ffU + & ((IData)(0x100U) + + + (0x60U + & (vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT____Vcellout__vx_priority_encoder_sm__out_address[2U] + << 1U)))), vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__block_wdata, + vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT____Vcellout__vx_priority_encoder_sm__out_data[2U]); + } + } + } + } + } + } + if ((8U & (IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__vx_priority_encoder_sm__DOT__internal_out_valid))) { + if ((0xffU == (0xffU & (vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT____Vcellout__vx_priority_encoder_sm__out_address[3U] + >> 0x18U)))) { + if ((7U != (IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__sm_driver_in_mem_write))) { + if ((0U != (IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__sm_driver_in_mem_write))) { + if ((1U != (IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__sm_driver_in_mem_write))) { + if ((2U == (IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__sm_driver_in_mem_write))) { + VL_ASSIGNSEL_WIII(32,(0x1ffU + & ((IData)(0x180U) + + + (0x60U + & (vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT____Vcellout__vx_priority_encoder_sm__out_address[3U] + << 1U)))), vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__block_wdata, + vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT____Vcellout__vx_priority_encoder_sm__out_data[3U]); + } + } + } + } + } + } + if ((1U & (IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__vx_priority_encoder_sm__DOT__internal_out_valid))) { + if ((0xffU == (0xffU & ((vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT____Vcellout__vx_priority_encoder_sm__out_address[1U] + << 8U) | (vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT____Vcellout__vx_priority_encoder_sm__out_address[0U] + >> 0x18U))))) { + if ((7U == (IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__sm_driver_in_mem_write))) { + if ((7U != (IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__sm_driver_in_mem_read))) { + if ((0U != (IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__sm_driver_in_mem_read))) { + if ((1U != (IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__sm_driver_in_mem_read))) { + if ((2U == (IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__sm_driver_in_mem_read))) { + vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__temp_out_valid + = ((IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__temp_out_valid) + | ((IData)(1U) + << (3U & (IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__vx_priority_encoder_sm__DOT__internal_req_num)))); + } + } + } + } + } + } + } + if ((2U & (IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__vx_priority_encoder_sm__DOT__internal_out_valid))) { + if ((0xffU == (0xffU & ((vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT____Vcellout__vx_priority_encoder_sm__out_address[2U] + << 8U) | (vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT____Vcellout__vx_priority_encoder_sm__out_address[1U] + >> 0x18U))))) { + if ((7U == (IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__sm_driver_in_mem_write))) { + if ((7U != (IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__sm_driver_in_mem_read))) { + if ((0U != (IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__sm_driver_in_mem_read))) { + if ((1U != (IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__sm_driver_in_mem_read))) { + if ((2U == (IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__sm_driver_in_mem_read))) { + vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__temp_out_valid + = ((IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__temp_out_valid) + | ((IData)(1U) + << (3U & + ((IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__vx_priority_encoder_sm__DOT__internal_req_num) + >> 3U)))); + } + } + } + } + } + } + } + if ((4U & (IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__vx_priority_encoder_sm__DOT__internal_out_valid))) { + if ((0xffU == (0xffU & ((vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT____Vcellout__vx_priority_encoder_sm__out_address[3U] + << 8U) | (vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT____Vcellout__vx_priority_encoder_sm__out_address[2U] + >> 0x18U))))) { + if ((7U == (IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__sm_driver_in_mem_write))) { + if ((7U != (IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__sm_driver_in_mem_read))) { + if ((0U != (IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__sm_driver_in_mem_read))) { + if ((1U != (IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__sm_driver_in_mem_read))) { + if ((2U == (IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__sm_driver_in_mem_read))) { + vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__temp_out_valid + = ((IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__temp_out_valid) + | ((IData)(1U) + << (3U & + ((IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__vx_priority_encoder_sm__DOT__internal_req_num) + >> 6U)))); + } + } + } + } + } + } + } + if ((8U & (IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__vx_priority_encoder_sm__DOT__internal_out_valid))) { + if ((0xffU == (0xffU & (vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT____Vcellout__vx_priority_encoder_sm__out_address[3U] + >> 0x18U)))) { + if ((7U == (IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__sm_driver_in_mem_write))) { + if ((7U != (IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__sm_driver_in_mem_read))) { + if ((0U != (IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__sm_driver_in_mem_read))) { + if ((1U != (IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__sm_driver_in_mem_read))) { + if ((2U == (IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__sm_driver_in_mem_read))) { + vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__temp_out_valid + = ((IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__temp_out_valid) + | ((IData)(1U) + << (3U & + ((IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__vx_priority_encoder_sm__DOT__internal_req_num) + >> 9U)))); + } + } + } + } + } + } + } + vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__block_addr = 0U; + if ((1U & (IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__vx_priority_encoder_sm__DOT__internal_out_valid))) { + if ((0xffU == (0xffU & ((vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT____Vcellout__vx_priority_encoder_sm__out_address[1U] + << 8U) | (vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT____Vcellout__vx_priority_encoder_sm__out_address[0U] + >> 0x18U))))) { + if ((7U != (IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__sm_driver_in_mem_write))) { + if ((0U != (IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__sm_driver_in_mem_write))) { + if ((1U != (IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__sm_driver_in_mem_write))) { + if ((2U == (IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__sm_driver_in_mem_write))) { + vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT____Vlvbound1 + = (0x7fU & ((vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT____Vcellout__vx_priority_encoder_sm__out_address[1U] + << 0x1aU) + | (vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT____Vcellout__vx_priority_encoder_sm__out_address[0U] + >> 6U))); + vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__block_addr + = ((0xfffff80U & vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__block_addr) + | (IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT____Vlvbound1)); + } + } + } + } else { + if ((7U != (IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__sm_driver_in_mem_read))) { + if ((0U != (IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__sm_driver_in_mem_read))) { + if ((1U != (IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__sm_driver_in_mem_read))) { + if ((2U == (IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__sm_driver_in_mem_read))) { + vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT____Vlvbound2 + = (0x7fU & ((vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT____Vcellout__vx_priority_encoder_sm__out_address[1U] + << 0x1aU) + | (vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT____Vcellout__vx_priority_encoder_sm__out_address[0U] + >> 6U))); + vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__block_addr + = ((0xfffff80U + & vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__block_addr) + | (IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT____Vlvbound2)); + } + } + } + } + } + } + } + if ((2U & (IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__vx_priority_encoder_sm__DOT__internal_out_valid))) { + if ((0xffU == (0xffU & ((vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT____Vcellout__vx_priority_encoder_sm__out_address[2U] + << 8U) | (vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT____Vcellout__vx_priority_encoder_sm__out_address[1U] + >> 0x18U))))) { + if ((7U != (IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__sm_driver_in_mem_write))) { + if ((0U != (IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__sm_driver_in_mem_write))) { + if ((1U != (IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__sm_driver_in_mem_write))) { + if ((2U == (IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__sm_driver_in_mem_write))) { + vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT____Vlvbound1 + = (0x7fU & ((vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT____Vcellout__vx_priority_encoder_sm__out_address[2U] + << 0x1aU) + | (vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT____Vcellout__vx_priority_encoder_sm__out_address[1U] + >> 6U))); + vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__block_addr + = ((0xfffc07fU & vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__block_addr) + | ((IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT____Vlvbound1) + << 7U)); + } + } + } + } else { + if ((7U != (IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__sm_driver_in_mem_read))) { + if ((0U != (IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__sm_driver_in_mem_read))) { + if ((1U != (IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__sm_driver_in_mem_read))) { + if ((2U == (IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__sm_driver_in_mem_read))) { + vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT____Vlvbound2 + = (0x7fU & ((vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT____Vcellout__vx_priority_encoder_sm__out_address[2U] + << 0x1aU) + | (vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT____Vcellout__vx_priority_encoder_sm__out_address[1U] + >> 6U))); + vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__block_addr + = ((0xfffc07fU + & vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__block_addr) + | ((IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT____Vlvbound2) + << 7U)); + } + } + } + } + } + } + } + if ((4U & (IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__vx_priority_encoder_sm__DOT__internal_out_valid))) { + if ((0xffU == (0xffU & ((vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT____Vcellout__vx_priority_encoder_sm__out_address[3U] + << 8U) | (vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT____Vcellout__vx_priority_encoder_sm__out_address[2U] + >> 0x18U))))) { + if ((7U != (IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__sm_driver_in_mem_write))) { + if ((0U != (IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__sm_driver_in_mem_write))) { + if ((1U != (IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__sm_driver_in_mem_write))) { + if ((2U == (IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__sm_driver_in_mem_write))) { + vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT____Vlvbound1 + = (0x7fU & ((vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT____Vcellout__vx_priority_encoder_sm__out_address[3U] + << 0x1aU) + | (vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT____Vcellout__vx_priority_encoder_sm__out_address[2U] + >> 6U))); + vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__block_addr + = ((0xfe03fffU & vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__block_addr) + | ((IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT____Vlvbound1) + << 0xeU)); + } + } + } + } else { + if ((7U != (IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__sm_driver_in_mem_read))) { + if ((0U != (IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__sm_driver_in_mem_read))) { + if ((1U != (IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__sm_driver_in_mem_read))) { + if ((2U == (IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__sm_driver_in_mem_read))) { + vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT____Vlvbound2 + = (0x7fU & ((vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT____Vcellout__vx_priority_encoder_sm__out_address[3U] + << 0x1aU) + | (vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT____Vcellout__vx_priority_encoder_sm__out_address[2U] + >> 6U))); + vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__block_addr + = ((0xfe03fffU + & vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__block_addr) + | ((IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT____Vlvbound2) + << 0xeU)); + } + } + } + } + } + } + } + if ((8U & (IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__vx_priority_encoder_sm__DOT__internal_out_valid))) { + if ((0xffU == (0xffU & (vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT____Vcellout__vx_priority_encoder_sm__out_address[3U] + >> 0x18U)))) { + if ((7U != (IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__sm_driver_in_mem_write))) { + if ((0U != (IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__sm_driver_in_mem_write))) { + if ((1U != (IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__sm_driver_in_mem_write))) { + if ((2U == (IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__sm_driver_in_mem_write))) { + vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT____Vlvbound1 + = (0x7fU & (vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT____Vcellout__vx_priority_encoder_sm__out_address[3U] + >> 6U)); + vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__block_addr + = ((0x1fffffU & vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__block_addr) + | ((IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT____Vlvbound1) + << 0x15U)); + } + } + } + } else { + if ((7U != (IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__sm_driver_in_mem_read))) { + if ((0U != (IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__sm_driver_in_mem_read))) { + if ((1U != (IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__sm_driver_in_mem_read))) { + if ((2U == (IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__sm_driver_in_mem_read))) { + vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT____Vlvbound2 + = (0x7fU & (vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT____Vcellout__vx_priority_encoder_sm__out_address[3U] + >> 6U)); + vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__block_addr + = ((0x1fffffU & vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__block_addr) + | ((IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT____Vlvbound2) + << 0x15U)); + } + } + } + } + } + } + } + vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__data_structures__DOT__write_from_mem_per_way + = ((2U & (IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__data_structures__DOT__write_from_mem_per_way)) + | ((IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__write_from_mem) + & (~ (IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__data_structures__DOT__way_use_Qual)))); + vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__data_structures__DOT__we_per_way + = ((0xffff0000U & vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__data_structures__DOT__we_per_way) + | ((IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__data_structures__DOT__way_use_Qual) + ? 0U : (0xffffU & (IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__we)))); + vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__data_structures__DOT__write_from_mem_per_way + = ((1U & (IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__data_structures__DOT__write_from_mem_per_way)) + | (((IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__write_from_mem) + & (IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__data_structures__DOT__way_use_Qual)) + << 1U)); + vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__data_structures__DOT__we_per_way + = ((0xffffU & vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__data_structures__DOT__we_per_way) + | (((IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__data_structures__DOT__way_use_Qual) + ? (0xffffU & (IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__we)) + : 0U) << 0x10U)); + vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__data_unQual + = (((0U == (3U & vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_addr)) + | (2U == (IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache_driver_in_mem_read))) + ? (((0U == (0x1fU & (((IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__data_structures__DOT__way_use_Qual) + << 7U) + (0x60U & + (vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_addr + << 3U))))) + ? 0U : (vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__data_structures__DOT__data_use_per_way[ + ((IData)(1U) + (7U & ((((IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__data_structures__DOT__way_use_Qual) + << 7U) + + (0x60U + & (vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_addr + << 3U))) + >> 5U)))] + << ((IData)(0x20U) - (0x1fU + & (((IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__data_structures__DOT__way_use_Qual) + << 7U) + + + (0x60U + & (vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_addr + << 3U))))))) + | (vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__data_structures__DOT__data_use_per_way[ + (7U & ((((IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__data_structures__DOT__way_use_Qual) + << 7U) + (0x60U & (vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_addr + << 3U))) + >> 5U))] >> (0x1fU & (((IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__data_structures__DOT__way_use_Qual) + << 7U) + + (0x60U + & (vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_addr + << 3U)))))) + : ((1U == (3U & vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_addr)) + ? ((((0U == (0x1fU & (((IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__data_structures__DOT__way_use_Qual) + << 7U) + (0x60U + & (vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_addr + << 3U))))) + ? 0U : (vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__data_structures__DOT__data_use_per_way[ + ((IData)(1U) + (7U & + ((((IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__data_structures__DOT__way_use_Qual) + << 7U) + + (0x60U + & (vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_addr + << 3U))) + >> 5U)))] + << ((IData)(0x20U) - + (0x1fU & (((IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__data_structures__DOT__way_use_Qual) + << 7U) + + (0x60U + & (vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_addr + << 3U))))))) + | (vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__data_structures__DOT__data_use_per_way[ + (7U & ((((IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__data_structures__DOT__way_use_Qual) + << 7U) + (0x60U & (vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_addr + << 3U))) + >> 5U))] >> (0x1fU & + (((IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__data_structures__DOT__way_use_Qual) + << 7U) + + (0x60U + & (vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_addr + << 3U)))))) + >> 8U) : ((2U == (3U & vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_addr)) + ? ((((0U == (0x1fU & + (((IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__data_structures__DOT__way_use_Qual) + << 7U) + + (0x60U + & (vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_addr + << 3U))))) + ? 0U : (vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__data_structures__DOT__data_use_per_way[ + ((IData)(1U) + + (7U + & ((((IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__data_structures__DOT__way_use_Qual) + << 7U) + + + (0x60U + & (vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_addr + << 3U))) + >> 5U)))] + << ((IData)(0x20U) + - (0x1fU + & (((IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__data_structures__DOT__way_use_Qual) + << 7U) + + + (0x60U + & (vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_addr + << 3U))))))) + | (vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__data_structures__DOT__data_use_per_way[ + (7U & ((((IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__data_structures__DOT__way_use_Qual) + << 7U) + + (0x60U + & (vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_addr + << 3U))) + >> 5U))] + >> (0x1fU & (((IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__data_structures__DOT__way_use_Qual) + << 7U) + + + (0x60U + & (vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_addr + << 3U)))))) + >> 0x10U) : ((((0U + == + (0x1fU + & (((IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__data_structures__DOT__way_use_Qual) + << 7U) + + + (0x60U + & (vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_addr + << 3U))))) + ? 0U + : + (vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__data_structures__DOT__data_use_per_way[ + ((IData)(1U) + + + (7U + & ((((IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__data_structures__DOT__way_use_Qual) + << 7U) + + + (0x60U + & (vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_addr + << 3U))) + >> 5U)))] + << + ((IData)(0x20U) + - + (0x1fU + & (((IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__data_structures__DOT__way_use_Qual) + << 7U) + + + (0x60U + & (vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_addr + << 3U))))))) + | (vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__data_structures__DOT__data_use_per_way[ + (7U + & ((((IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__data_structures__DOT__way_use_Qual) + << 7U) + + + (0x60U + & (vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_addr + << 3U))) + >> 5U))] + >> + (0x1fU + & (((IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__data_structures__DOT__way_use_Qual) + << 7U) + + + (0x60U + & (vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_addr + << 3U)))))) + >> 0x18U)))); + vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__tag_use + = ((0x2dU >= (0x3fU & ((IData)(0x17U) * (IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__data_structures__DOT__way_use_Qual)))) + ? (0x7fffffU & (IData)((vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__data_structures__DOT__tag_use_per_way + >> (0x3fU & ((IData)(0x17U) + * (IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__data_structures__DOT__way_use_Qual)))))) + : 0U); + vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__valid_use + = (1U & ((IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__data_structures__DOT__valid_use_per_way) + >> (IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__data_structures__DOT__way_use_Qual))); + vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__vx_priority_encoder_sm__DOT__new_left_requests + = ((0U == (IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__vx_priority_encoder_sm__DOT__left_requests)) + ? ((IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__orig_in_valid) + & (~ (IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__vx_priority_encoder_sm__DOT__serviced_qual))) + : ((IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__vx_priority_encoder_sm__DOT__left_requests) + & (~ (IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__vx_priority_encoder_sm__DOT__serviced_qual)))); + vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__block_rdata[0U] + = ((IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__genblk2__BRA__0__KET____DOT__shm_write) + ? 0U : vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__genblk2__BRA__0__KET____DOT__vx_shared_memory_block__DOT__shared_memory + [(0x7fU & vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__block_addr)][0U]); + vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__block_rdata[1U] + = ((IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__genblk2__BRA__0__KET____DOT__shm_write) + ? 0U : vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__genblk2__BRA__0__KET____DOT__vx_shared_memory_block__DOT__shared_memory + [(0x7fU & vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__block_addr)][1U]); + vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__block_rdata[2U] + = ((IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__genblk2__BRA__0__KET____DOT__shm_write) + ? 0U : vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__genblk2__BRA__0__KET____DOT__vx_shared_memory_block__DOT__shared_memory + [(0x7fU & vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__block_addr)][2U]); + vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__block_rdata[3U] + = ((IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__genblk2__BRA__0__KET____DOT__shm_write) + ? 0U : vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__genblk2__BRA__0__KET____DOT__vx_shared_memory_block__DOT__shared_memory + [(0x7fU & vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__block_addr)][3U]); + vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__block_rdata[4U] + = ((IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__genblk2__BRA__1__KET____DOT__shm_write) + ? 0U : vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__genblk2__BRA__1__KET____DOT__vx_shared_memory_block__DOT__shared_memory + [(0x7fU & (vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__block_addr + >> 7U))][0U]); + vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__block_rdata[5U] + = ((IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__genblk2__BRA__1__KET____DOT__shm_write) + ? 0U : vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__genblk2__BRA__1__KET____DOT__vx_shared_memory_block__DOT__shared_memory + [(0x7fU & (vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__block_addr + >> 7U))][1U]); + vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__block_rdata[6U] + = ((IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__genblk2__BRA__1__KET____DOT__shm_write) + ? 0U : vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__genblk2__BRA__1__KET____DOT__vx_shared_memory_block__DOT__shared_memory + [(0x7fU & (vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__block_addr + >> 7U))][2U]); + vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__block_rdata[7U] + = ((IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__genblk2__BRA__1__KET____DOT__shm_write) + ? 0U : vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__genblk2__BRA__1__KET____DOT__vx_shared_memory_block__DOT__shared_memory + [(0x7fU & (vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__block_addr + >> 7U))][3U]); + vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__block_rdata[8U] + = ((IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__genblk2__BRA__2__KET____DOT__shm_write) + ? 0U : vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__genblk2__BRA__2__KET____DOT__vx_shared_memory_block__DOT__shared_memory + [(0x7fU & (vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__block_addr + >> 0xeU))][0U]); + vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__block_rdata[9U] + = ((IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__genblk2__BRA__2__KET____DOT__shm_write) + ? 0U : vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__genblk2__BRA__2__KET____DOT__vx_shared_memory_block__DOT__shared_memory + [(0x7fU & (vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__block_addr + >> 0xeU))][1U]); + vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__block_rdata[0xaU] + = ((IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__genblk2__BRA__2__KET____DOT__shm_write) + ? 0U : vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__genblk2__BRA__2__KET____DOT__vx_shared_memory_block__DOT__shared_memory + [(0x7fU & (vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__block_addr + >> 0xeU))][2U]); + vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__block_rdata[0xbU] + = ((IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__genblk2__BRA__2__KET____DOT__shm_write) + ? 0U : vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__genblk2__BRA__2__KET____DOT__vx_shared_memory_block__DOT__shared_memory + [(0x7fU & (vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__block_addr + >> 0xeU))][3U]); + vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__block_rdata[0xcU] + = ((IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__genblk2__BRA__3__KET____DOT__shm_write) + ? 0U : vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__genblk2__BRA__3__KET____DOT__vx_shared_memory_block__DOT__shared_memory + [(0x7fU & (vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__block_addr + >> 0x15U))][0U]); + vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__block_rdata[0xdU] + = ((IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__genblk2__BRA__3__KET____DOT__shm_write) + ? 0U : vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__genblk2__BRA__3__KET____DOT__vx_shared_memory_block__DOT__shared_memory + [(0x7fU & (vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__block_addr + >> 0x15U))][1U]); + vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__block_rdata[0xeU] + = ((IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__genblk2__BRA__3__KET____DOT__shm_write) + ? 0U : vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__genblk2__BRA__3__KET____DOT__vx_shared_memory_block__DOT__shared_memory + [(0x7fU & (vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__block_addr + >> 0x15U))][2U]); + vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__block_rdata[0xfU] + = ((IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__genblk2__BRA__3__KET____DOT__shm_write) + ? 0U : vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__genblk2__BRA__3__KET____DOT__vx_shared_memory_block__DOT__shared_memory + [(0x7fU & (vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__block_addr + >> 0x15U))][3U]); + vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__hit_per_bank + = (((IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__access) + & (vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__tag_use + == (0x7fffffU & (vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_addr + >> 9U)))) & (IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__valid_use)); + if ((1U & (IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__vx_priority_encoder_sm__DOT__internal_out_valid))) { + if ((0xffU == (0xffU & ((vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT____Vcellout__vx_priority_encoder_sm__out_address[1U] + << 8U) | (vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT____Vcellout__vx_priority_encoder_sm__out_address[0U] + >> 0x18U))))) { + if ((7U == (IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__sm_driver_in_mem_write))) { + if ((7U != (IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__sm_driver_in_mem_read))) { + if ((0U != (IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__sm_driver_in_mem_read))) { + if ((1U != (IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__sm_driver_in_mem_read))) { + if ((2U == (IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__sm_driver_in_mem_read))) { + VL_ASSIGNSEL_WIII(32, + (0x60U + & ((IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__vx_priority_encoder_sm__DOT__internal_req_num) + << 5U)), vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__temp_out_data, + vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__block_rdata[ + (3U + & (vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT____Vcellout__vx_priority_encoder_sm__out_address[0U] + >> 4U))]); + } + } + } + } + } + } + } + if ((2U & (IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__vx_priority_encoder_sm__DOT__internal_out_valid))) { + if ((0xffU == (0xffU & ((vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT____Vcellout__vx_priority_encoder_sm__out_address[2U] + << 8U) | (vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT____Vcellout__vx_priority_encoder_sm__out_address[1U] + >> 0x18U))))) { + if ((7U == (IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__sm_driver_in_mem_write))) { + if ((7U != (IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__sm_driver_in_mem_read))) { + if ((0U != (IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__sm_driver_in_mem_read))) { + if ((1U != (IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__sm_driver_in_mem_read))) { + if ((2U == (IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__sm_driver_in_mem_read))) { + VL_ASSIGNSEL_WIII(32, + (0x60U + & ((IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__vx_priority_encoder_sm__DOT__internal_req_num) + << 2U)), vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__temp_out_data, + (((0U + == + (0x1fU + & ((IData)(0x80U) + + + (0x60U + & (vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT____Vcellout__vx_priority_encoder_sm__out_address[1U] + << 1U))))) + ? 0U + : + (vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__block_rdata[ + ((IData)(1U) + + + (0xfU + & (((IData)(0x80U) + + + (0x60U + & (vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT____Vcellout__vx_priority_encoder_sm__out_address[1U] + << 1U))) + >> 5U)))] + << + ((IData)(0x20U) + - + (0x1fU + & ((IData)(0x80U) + + + (0x60U + & (vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT____Vcellout__vx_priority_encoder_sm__out_address[1U] + << 1U))))))) + | (vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__block_rdata[ + (0xfU + & (((IData)(0x80U) + + + (0x60U + & (vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT____Vcellout__vx_priority_encoder_sm__out_address[1U] + << 1U))) + >> 5U))] + >> + (0x1fU + & ((IData)(0x80U) + + + (0x60U + & (vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT____Vcellout__vx_priority_encoder_sm__out_address[1U] + << 1U))))))); + } + } + } + } + } + } + } + if ((4U & (IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__vx_priority_encoder_sm__DOT__internal_out_valid))) { + if ((0xffU == (0xffU & ((vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT____Vcellout__vx_priority_encoder_sm__out_address[3U] + << 8U) | (vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT____Vcellout__vx_priority_encoder_sm__out_address[2U] + >> 0x18U))))) { + if ((7U == (IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__sm_driver_in_mem_write))) { + if ((7U != (IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__sm_driver_in_mem_read))) { + if ((0U != (IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__sm_driver_in_mem_read))) { + if ((1U != (IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__sm_driver_in_mem_read))) { + if ((2U == (IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__sm_driver_in_mem_read))) { + VL_ASSIGNSEL_WIII(32, + (0x60U + & ((IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__vx_priority_encoder_sm__DOT__internal_req_num) + >> 1U)), vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__temp_out_data, + (((0U + == + (0x1fU + & ((IData)(0x100U) + + + (0x60U + & (vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT____Vcellout__vx_priority_encoder_sm__out_address[2U] + << 1U))))) + ? 0U + : + (vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__block_rdata[ + ((IData)(1U) + + + (0xfU + & (((IData)(0x100U) + + + (0x60U + & (vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT____Vcellout__vx_priority_encoder_sm__out_address[2U] + << 1U))) + >> 5U)))] + << + ((IData)(0x20U) + - + (0x1fU + & ((IData)(0x100U) + + + (0x60U + & (vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT____Vcellout__vx_priority_encoder_sm__out_address[2U] + << 1U))))))) + | (vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__block_rdata[ + (0xfU + & (((IData)(0x100U) + + + (0x60U + & (vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT____Vcellout__vx_priority_encoder_sm__out_address[2U] + << 1U))) + >> 5U))] + >> + (0x1fU + & ((IData)(0x100U) + + + (0x60U + & (vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT____Vcellout__vx_priority_encoder_sm__out_address[2U] + << 1U))))))); + } + } + } + } + } + } + } + if ((8U & (IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__vx_priority_encoder_sm__DOT__internal_out_valid))) { + if ((0xffU == (0xffU & (vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT____Vcellout__vx_priority_encoder_sm__out_address[3U] + >> 0x18U)))) { + if ((7U == (IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__sm_driver_in_mem_write))) { + if ((7U != (IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__sm_driver_in_mem_read))) { + if ((0U != (IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__sm_driver_in_mem_read))) { + if ((1U != (IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__sm_driver_in_mem_read))) { + if ((2U == (IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__sm_driver_in_mem_read))) { + VL_ASSIGNSEL_WIII(32, + (0x60U + & ((IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__vx_priority_encoder_sm__DOT__internal_req_num) + >> 4U)), vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__temp_out_data, + (((0U + == + (0x1fU + & ((IData)(0x180U) + + + (0x60U + & (vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT____Vcellout__vx_priority_encoder_sm__out_address[3U] + << 1U))))) + ? 0U + : + (vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__block_rdata[ + ((IData)(1U) + + + (0xfU + & (((IData)(0x180U) + + + (0x60U + & (vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT____Vcellout__vx_priority_encoder_sm__out_address[3U] + << 1U))) + >> 5U)))] + << + ((IData)(0x20U) + - + (0x1fU + & ((IData)(0x180U) + + + (0x60U + & (vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT____Vcellout__vx_priority_encoder_sm__out_address[3U] + << 1U))))))) + | (vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__block_rdata[ + (0xfU + & (((IData)(0x180U) + + + (0x60U + & (vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT____Vcellout__vx_priority_encoder_sm__out_address[3U] + << 1U))) + >> 5U))] + >> + (0x1fU + & ((IData)(0x180U) + + + (0x60U + & (vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT____Vcellout__vx_priority_encoder_sm__out_address[3U] + << 1U))))))); + } + } + } + } + } + } + } + vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__new_final_data_read = 0U; + if (vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__hit_per_bank) { + vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__new_final_data_read + = (((~ ((IData)(0xffffffffU) << (0x1fU + & ((IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT____Vcellout__genblk1__BRA__0__KET____DOT__choose_thread__index) + << 5U)))) + & vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__new_final_data_read) + | (((IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__access) + ? ((0U == (IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache_driver_in_mem_read)) + ? ((0x80U & vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__data_unQual) + ? (0xffffff00U | vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__data_unQual) + : (0xffU & vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__data_unQual)) + : ((1U == (IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache_driver_in_mem_read)) + ? ((0x8000U & vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__data_unQual) + ? (0xffff0000U | vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__data_unQual) + : (0xffffU & vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__data_unQual)) + : ((5U == (IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache_driver_in_mem_read)) + ? (0xffffU & vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__data_unQual) + : ((4U == (IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache_driver_in_mem_read)) + ? (0xffU & vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__data_unQual) + : vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__data_unQual)))) + : 0U) << (0x1fU & ((IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT____Vcellout__genblk1__BRA__0__KET____DOT__choose_thread__index) + << 5U)))); + } + vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__detect_bank_miss + = ((IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__valid_per_bank) + & (~ (IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__hit_per_bank))); + vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__debug_hit_per_bank_mask[0U] + = vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__hit_per_bank; + vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__miss_found = 0U; + if (vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__detect_bank_miss) { + vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__miss_found = 1U; + } + vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__miss_bank_index = 0U; + if (vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__detect_bank_miss) { + vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__miss_bank_index = 0U; + } + vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__new_state + = (((0U == (IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__state)) + & (IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__detect_bank_miss)) + ? 1U : ((1U == (IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__state)) + ? 2U : (((2U == (IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__state)) + & (~ (IData)(vlTOPp->cache_simX__DOT__icache_i_m_ready))) + ? 2U : 0U))); + vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__threads_serviced_per_bank + = (((IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__valid_per_bank) + ? ((IData)(1U) << (IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT____Vcellout__genblk1__BRA__0__KET____DOT__choose_thread__index)) + : 0U) & vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__debug_hit_per_bank_mask + [0U]); + vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__new_final_data_read_Qual + = ((IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__threads_serviced_per_bank) + ? vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__new_final_data_read + : vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__final_data_read); + vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__new_stored_valid + = ((IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__use_valid) + & (~ (IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__threads_serviced_per_bank))); + vlTOPp->out_icache_stall = ((IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__new_stored_valid) + | (0U != (IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__state))); +} + +VL_INLINE_OPT void Vcache_simX::_settle__TOP__3(Vcache_simX__Syms* __restrict vlSymsp) { + VL_DEBUG_IF(VL_DBG_MSGF("+ Vcache_simX::_settle__TOP__3\n"); ); + Vcache_simX* __restrict vlTOPp VL_ATTR_UNUSED = vlSymsp->TOPp; + // Body + vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT__eviction_wb + = ((0xeU & (IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT__eviction_wb)) + | (1U & ((IData)(vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__0__KET____DOT__bank_structure.__PVT__data_structures__DOT__dirty_use_per_way) + >> (IData)(vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__0__KET____DOT__bank_structure.__PVT__data_structures__DOT__way_use_Qual)))); + vlTOPp->cache_simX__DOT__dmem_controller__DOT____Vcellout__dcache__o_m_writedata[0U] + = vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__0__KET____DOT__bank_structure.__Vcellout__data_structures__data_use[0U]; + vlTOPp->cache_simX__DOT__dmem_controller__DOT____Vcellout__dcache__o_m_writedata[1U] + = vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__0__KET____DOT__bank_structure.__Vcellout__data_structures__data_use[1U]; + vlTOPp->cache_simX__DOT__dmem_controller__DOT____Vcellout__dcache__o_m_writedata[2U] + = vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__0__KET____DOT__bank_structure.__Vcellout__data_structures__data_use[2U]; + vlTOPp->cache_simX__DOT__dmem_controller__DOT____Vcellout__dcache__o_m_writedata[3U] + = vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__0__KET____DOT__bank_structure.__Vcellout__data_structures__data_use[3U]; + vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT__eviction_addr_per_bank[0U] + = ((vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__0__KET____DOT__bank_structure.__PVT__tag_use + << 0xbU) | (0x7c0U & vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__0__KET____DOT__bank_addr)); + vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT__hit_per_bank + = ((0xeU & (IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT__hit_per_bank)) + | (((IData)(vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__0__KET____DOT__bank_structure.__PVT__access) + & (vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__0__KET____DOT__bank_structure.__PVT__tag_use + == (0x1fffffU & (vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__0__KET____DOT__bank_addr + >> 0xbU)))) & (IData)(vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__0__KET____DOT__bank_structure.__PVT__valid_use))); + vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT__readdata_per_bank[0U] + = ((IData)(vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__0__KET____DOT__bank_structure.__PVT__access) + ? ((0U == (IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__cache_driver_in_mem_read)) + ? ((0x80U & vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__0__KET____DOT__bank_structure.__PVT__data_unQual) + ? (0xffffff00U | vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__0__KET____DOT__bank_structure.__PVT__data_unQual) + : (0xffU & vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__0__KET____DOT__bank_structure.__PVT__data_unQual)) + : ((1U == (IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__cache_driver_in_mem_read)) + ? ((0x8000U & vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__0__KET____DOT__bank_structure.__PVT__data_unQual) + ? (0xffff0000U | vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__0__KET____DOT__bank_structure.__PVT__data_unQual) + : (0xffffU & vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__0__KET____DOT__bank_structure.__PVT__data_unQual)) + : ((5U == (IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__cache_driver_in_mem_read)) + ? (0xffffU & vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__0__KET____DOT__bank_structure.__PVT__data_unQual) + : ((4U == (IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__cache_driver_in_mem_read)) + ? (0xffU & vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__0__KET____DOT__bank_structure.__PVT__data_unQual) + : vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__0__KET____DOT__bank_structure.__PVT__data_unQual)))) + : 0U); + vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT__eviction_wb + = ((0xdU & (IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT__eviction_wb)) + | (2U & (((IData)(vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__1__KET____DOT__bank_structure.__PVT__data_structures__DOT__dirty_use_per_way) + >> (IData)(vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__1__KET____DOT__bank_structure.__PVT__data_structures__DOT__way_use_Qual)) + << 1U))); + vlTOPp->cache_simX__DOT__dmem_controller__DOT____Vcellout__dcache__o_m_writedata[4U] + = vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__1__KET____DOT__bank_structure.__Vcellout__data_structures__data_use[0U]; + vlTOPp->cache_simX__DOT__dmem_controller__DOT____Vcellout__dcache__o_m_writedata[5U] + = vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__1__KET____DOT__bank_structure.__Vcellout__data_structures__data_use[1U]; + vlTOPp->cache_simX__DOT__dmem_controller__DOT____Vcellout__dcache__o_m_writedata[6U] + = vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__1__KET____DOT__bank_structure.__Vcellout__data_structures__data_use[2U]; + vlTOPp->cache_simX__DOT__dmem_controller__DOT____Vcellout__dcache__o_m_writedata[7U] + = vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__1__KET____DOT__bank_structure.__Vcellout__data_structures__data_use[3U]; + vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT__eviction_addr_per_bank[1U] + = ((vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__1__KET____DOT__bank_structure.__PVT__tag_use + << 0xbU) | (0x7c0U & vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__1__KET____DOT__bank_addr)); + vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT__hit_per_bank + = ((0xdU & (IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT__hit_per_bank)) + | ((((IData)(vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__1__KET____DOT__bank_structure.__PVT__access) + & (vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__1__KET____DOT__bank_structure.__PVT__tag_use + == (0x1fffffU & (vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__1__KET____DOT__bank_addr + >> 0xbU)))) & (IData)(vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__1__KET____DOT__bank_structure.__PVT__valid_use)) + << 1U)); + vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT__readdata_per_bank[1U] + = ((IData)(vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__1__KET____DOT__bank_structure.__PVT__access) + ? ((0U == (IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__cache_driver_in_mem_read)) + ? ((0x80U & vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__1__KET____DOT__bank_structure.__PVT__data_unQual) + ? (0xffffff00U | vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__1__KET____DOT__bank_structure.__PVT__data_unQual) + : (0xffU & vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__1__KET____DOT__bank_structure.__PVT__data_unQual)) + : ((1U == (IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__cache_driver_in_mem_read)) + ? ((0x8000U & vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__1__KET____DOT__bank_structure.__PVT__data_unQual) + ? (0xffff0000U | vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__1__KET____DOT__bank_structure.__PVT__data_unQual) + : (0xffffU & vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__1__KET____DOT__bank_structure.__PVT__data_unQual)) + : ((5U == (IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__cache_driver_in_mem_read)) + ? (0xffffU & vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__1__KET____DOT__bank_structure.__PVT__data_unQual) + : ((4U == (IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__cache_driver_in_mem_read)) + ? (0xffU & vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__1__KET____DOT__bank_structure.__PVT__data_unQual) + : vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__1__KET____DOT__bank_structure.__PVT__data_unQual)))) + : 0U); + vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT__eviction_wb + = ((0xbU & (IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT__eviction_wb)) + | (4U & (((IData)(vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__2__KET____DOT__bank_structure.__PVT__data_structures__DOT__dirty_use_per_way) + >> (IData)(vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__2__KET____DOT__bank_structure.__PVT__data_structures__DOT__way_use_Qual)) + << 2U))); + vlTOPp->cache_simX__DOT__dmem_controller__DOT____Vcellout__dcache__o_m_writedata[8U] + = vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__2__KET____DOT__bank_structure.__Vcellout__data_structures__data_use[0U]; + vlTOPp->cache_simX__DOT__dmem_controller__DOT____Vcellout__dcache__o_m_writedata[9U] + = vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__2__KET____DOT__bank_structure.__Vcellout__data_structures__data_use[1U]; + vlTOPp->cache_simX__DOT__dmem_controller__DOT____Vcellout__dcache__o_m_writedata[0xaU] + = vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__2__KET____DOT__bank_structure.__Vcellout__data_structures__data_use[2U]; + vlTOPp->cache_simX__DOT__dmem_controller__DOT____Vcellout__dcache__o_m_writedata[0xbU] + = vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__2__KET____DOT__bank_structure.__Vcellout__data_structures__data_use[3U]; + vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT__eviction_addr_per_bank[2U] + = ((vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__2__KET____DOT__bank_structure.__PVT__tag_use + << 0xbU) | (0x7c0U & vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__2__KET____DOT__bank_addr)); + vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT__hit_per_bank + = ((0xbU & (IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT__hit_per_bank)) + | ((((IData)(vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__2__KET____DOT__bank_structure.__PVT__access) + & (vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__2__KET____DOT__bank_structure.__PVT__tag_use + == (0x1fffffU & (vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__2__KET____DOT__bank_addr + >> 0xbU)))) & (IData)(vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__2__KET____DOT__bank_structure.__PVT__valid_use)) + << 2U)); + vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT__readdata_per_bank[2U] + = ((IData)(vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__2__KET____DOT__bank_structure.__PVT__access) + ? ((0U == (IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__cache_driver_in_mem_read)) + ? ((0x80U & vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__2__KET____DOT__bank_structure.__PVT__data_unQual) + ? (0xffffff00U | vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__2__KET____DOT__bank_structure.__PVT__data_unQual) + : (0xffU & vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__2__KET____DOT__bank_structure.__PVT__data_unQual)) + : ((1U == (IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__cache_driver_in_mem_read)) + ? ((0x8000U & vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__2__KET____DOT__bank_structure.__PVT__data_unQual) + ? (0xffff0000U | vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__2__KET____DOT__bank_structure.__PVT__data_unQual) + : (0xffffU & vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__2__KET____DOT__bank_structure.__PVT__data_unQual)) + : ((5U == (IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__cache_driver_in_mem_read)) + ? (0xffffU & vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__2__KET____DOT__bank_structure.__PVT__data_unQual) + : ((4U == (IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__cache_driver_in_mem_read)) + ? (0xffU & vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__2__KET____DOT__bank_structure.__PVT__data_unQual) + : vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__2__KET____DOT__bank_structure.__PVT__data_unQual)))) + : 0U); + vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT__eviction_wb + = ((7U & (IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT__eviction_wb)) + | (8U & (((IData)(vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__3__KET____DOT__bank_structure.__PVT__data_structures__DOT__dirty_use_per_way) + >> (IData)(vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__3__KET____DOT__bank_structure.__PVT__data_structures__DOT__way_use_Qual)) + << 3U))); + vlTOPp->cache_simX__DOT__dmem_controller__DOT____Vcellout__dcache__o_m_writedata[0xcU] + = vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__3__KET____DOT__bank_structure.__Vcellout__data_structures__data_use[0U]; + vlTOPp->cache_simX__DOT__dmem_controller__DOT____Vcellout__dcache__o_m_writedata[0xdU] + = vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__3__KET____DOT__bank_structure.__Vcellout__data_structures__data_use[1U]; + vlTOPp->cache_simX__DOT__dmem_controller__DOT____Vcellout__dcache__o_m_writedata[0xeU] + = vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__3__KET____DOT__bank_structure.__Vcellout__data_structures__data_use[2U]; + vlTOPp->cache_simX__DOT__dmem_controller__DOT____Vcellout__dcache__o_m_writedata[0xfU] + = vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__3__KET____DOT__bank_structure.__Vcellout__data_structures__data_use[3U]; + vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT__eviction_addr_per_bank[3U] + = ((vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__3__KET____DOT__bank_structure.__PVT__tag_use + << 0xbU) | (0x7c0U & vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__3__KET____DOT__bank_addr)); + vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT__hit_per_bank + = ((7U & (IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT__hit_per_bank)) + | ((((IData)(vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__3__KET____DOT__bank_structure.__PVT__access) + & (vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__3__KET____DOT__bank_structure.__PVT__tag_use + == (0x1fffffU & (vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__3__KET____DOT__bank_addr + >> 0xbU)))) & (IData)(vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__3__KET____DOT__bank_structure.__PVT__valid_use)) + << 3U)); + vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT__readdata_per_bank[3U] + = ((IData)(vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__3__KET____DOT__bank_structure.__PVT__access) + ? ((0U == (IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__cache_driver_in_mem_read)) + ? ((0x80U & vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__3__KET____DOT__bank_structure.__PVT__data_unQual) + ? (0xffffff00U | vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__3__KET____DOT__bank_structure.__PVT__data_unQual) + : (0xffU & vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__3__KET____DOT__bank_structure.__PVT__data_unQual)) + : ((1U == (IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__cache_driver_in_mem_read)) + ? ((0x8000U & vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__3__KET____DOT__bank_structure.__PVT__data_unQual) + ? (0xffff0000U | vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__3__KET____DOT__bank_structure.__PVT__data_unQual) + : (0xffffU & vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__3__KET____DOT__bank_structure.__PVT__data_unQual)) + : ((5U == (IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__cache_driver_in_mem_read)) + ? (0xffffU & vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__3__KET____DOT__bank_structure.__PVT__data_unQual) + : ((4U == (IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__cache_driver_in_mem_read)) + ? (0xffU & vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__3__KET____DOT__bank_structure.__PVT__data_unQual) + : vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__3__KET____DOT__bank_structure.__PVT__data_unQual)))) + : 0U); + vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT__detect_bank_miss + = ((IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT__valid_per_bank) + & (~ (IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT__hit_per_bank))); + vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT__debug_hit_per_bank_mask[0U] + = (0xfU & VL_NEGATE_I((IData)((1U & (IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT__hit_per_bank))))); + vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT__debug_hit_per_bank_mask[1U] + = (0xfU & VL_NEGATE_I((IData)((1U & ((IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT__hit_per_bank) + >> 1U))))); + vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT__debug_hit_per_bank_mask[2U] + = (0xfU & VL_NEGATE_I((IData)((1U & ((IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT__hit_per_bank) + >> 2U))))); + vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT__debug_hit_per_bank_mask[3U] + = (0xfU & VL_NEGATE_I((IData)((1U & ((IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT__hit_per_bank) + >> 3U))))); + vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT__new_final_data_read[0U] = 0U; + vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT__new_final_data_read[1U] = 0U; + vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT__new_final_data_read[2U] = 0U; + vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT__new_final_data_read[3U] = 0U; + if ((1U & (IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT__hit_per_bank))) { + VL_ASSIGNSEL_WIII(32,(0x60U & ((IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT__index_per_bank) + << 5U)), vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT__new_final_data_read, + vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT__readdata_per_bank[0U]); + } + if ((2U & (IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT__hit_per_bank))) { + VL_ASSIGNSEL_WIII(32,(0x60U & ((IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT__index_per_bank) + << 3U)), vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT__new_final_data_read, + vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT__readdata_per_bank[1U]); + } + if ((4U & (IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT__hit_per_bank))) { + VL_ASSIGNSEL_WIII(32,(0x60U & ((IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT__index_per_bank) + << 1U)), vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT__new_final_data_read, + vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT__readdata_per_bank[2U]); + } + if ((8U & (IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT__hit_per_bank))) { + VL_ASSIGNSEL_WIII(32,(0x60U & ((IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT__index_per_bank) + >> 1U)), vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT__new_final_data_read, + vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT__readdata_per_bank[3U]); + } + vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT__new_state + = (((0U == (IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT__state)) + & (0U != (IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT__detect_bank_miss))) + ? 1U : ((1U == (IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT__state)) + ? 2U : (((2U == (IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT__state)) + & (~ (IData)(vlTOPp->cache_simX__DOT__dcache_i_m_ready))) + ? 2U : 0U))); + vlTOPp->__Vtableidx5 = vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT__detect_bank_miss; + vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT__miss_bank_index + = vlTOPp->__Vtable5_cache_simX__DOT__dmem_controller__DOT__dcache__DOT__miss_bank_index + [vlTOPp->__Vtableidx5]; + vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT__miss_found + = vlTOPp->__Vtable5_cache_simX__DOT__dmem_controller__DOT__dcache__DOT__miss_found + [vlTOPp->__Vtableidx5]; + vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT__get_miss_index__DOT__i + = vlTOPp->__Vtable5_cache_simX__DOT__dmem_controller__DOT__dcache__DOT__get_miss_index__DOT__i + [vlTOPp->__Vtableidx5]; + vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT__threads_serviced_per_bank + = ((0xfff0U & (IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT__threads_serviced_per_bank)) + | ((IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT__use_mask_per_bank) + & vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT__debug_hit_per_bank_mask + [0U])); + vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT__threads_serviced_per_bank + = ((0xff0fU & (IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT__threads_serviced_per_bank)) + | (0xfffffff0U & ((IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT__use_mask_per_bank) + & (vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT__debug_hit_per_bank_mask + [1U] << 4U)))); + vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT__threads_serviced_per_bank + = ((0xf0ffU & (IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT__threads_serviced_per_bank)) + | (0xffffff00U & ((IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT__use_mask_per_bank) + & (vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT__debug_hit_per_bank_mask + [2U] << 8U)))); + vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT__threads_serviced_per_bank + = ((0xfffU & (IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT__threads_serviced_per_bank)) + | (0xfffff000U & ((IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT__use_mask_per_bank) + & (vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT__debug_hit_per_bank_mask + [3U] << 0xcU)))); + vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT__threads_serviced_Qual + = (0xfU & (IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT__threads_serviced_per_bank)); + vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT__threads_serviced_Qual + = (0xfU & ((IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT__threads_serviced_Qual) + | ((IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT__threads_serviced_per_bank) + >> 4U))); + vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT__threads_serviced_Qual + = (0xfU & ((IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT__threads_serviced_Qual) + | ((IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT__threads_serviced_per_bank) + >> 8U))); + vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT__threads_serviced_Qual + = (0xfU & ((IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT__threads_serviced_Qual) + | ((IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT__threads_serviced_per_bank) + >> 0xcU))); + vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT__new_final_data_read_Qual[0U] + = ((1U & (IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT__threads_serviced_Qual)) + ? vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT__new_final_data_read[0U] + : vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT__final_data_read[0U]); + vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT__new_final_data_read_Qual[1U] + = ((2U & (IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT__threads_serviced_Qual)) + ? vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT__new_final_data_read[1U] + : vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT__final_data_read[1U]); + vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT__new_final_data_read_Qual[2U] + = ((4U & (IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT__threads_serviced_Qual)) + ? vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT__new_final_data_read[2U] + : vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT__final_data_read[2U]); + vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT__new_final_data_read_Qual[3U] + = ((8U & (IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT__threads_serviced_Qual)) + ? vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT__new_final_data_read[3U] + : vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT__final_data_read[3U]); + vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT__new_stored_valid + = ((IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT__use_valid) + & (~ (IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT__threads_serviced_Qual))); + vlTOPp->out_dcache_stall = ((0U != (IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__vx_priority_encoder_sm__DOT__more_than_one_valid)) + | ((0U != (IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT__new_stored_valid)) + | (0U != (IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT__state)))); +} + +VL_INLINE_OPT void Vcache_simX::_sequent__TOP__4(Vcache_simX__Syms* __restrict vlSymsp) { + VL_DEBUG_IF(VL_DBG_MSGF("+ Vcache_simX::_sequent__TOP__4\n"); ); + Vcache_simX* __restrict vlTOPp VL_ATTR_UNUSED = vlSymsp->TOPp; + // Variables + CData/*0:0*/ __Vdlyvset__cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__valid__v0; + CData/*4:0*/ __Vdlyvdim0__cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__valid__v32; + CData/*0:0*/ __Vdlyvset__cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__valid__v32; + CData/*0:0*/ __Vdlyvset__cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__tag__v0; + CData/*4:0*/ __Vdlyvdim0__cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__tag__v32; + CData/*0:0*/ __Vdlyvset__cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__tag__v32; + CData/*0:0*/ __Vdlyvset__cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__data__v0; + CData/*4:0*/ __Vdlyvdim0__cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__data__v32; + CData/*6:0*/ __Vdlyvlsb__cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__data__v32; + CData/*7:0*/ __Vdlyvval__cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__data__v32; 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+ } + } else { + if (vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__genblk2__BRA__1__KET____DOT__shm_write) { + VL_ASSIGNSEL_WIII(32,(0x60U & ((IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__block_we) + << 3U)), + vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__genblk2__BRA__1__KET____DOT__vx_shared_memory_block__DOT__shared_memory + [(0x7fU & (vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__block_addr + >> 7U))], + (((0U == (0x1fU & ((IData)(0x80U) + + + (0x60U + & ((IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__block_we) + << 3U))))) + ? 0U : (vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__block_wdata[ + ((IData)(1U) + + (0xfU & + (((IData)(0x80U) + + (0x60U + & ((IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__block_we) + << 3U))) + >> 5U)))] + << ((IData)(0x20U) + - (0x1fU + & ((IData)(0x80U) + + + (0x60U + & ((IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__block_we) + << 3U))))))) + | (vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__block_wdata[ + (0xfU & (((IData)(0x80U) + + (0x60U + & ((IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__block_we) + << 3U))) + >> 5U))] + >> (0x1fU & ((IData)(0x80U) + + (0x60U + & ((IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__block_we) + << 3U))))))); + } + } + if (vlTOPp->reset) { + vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__genblk2__BRA__2__KET____DOT__vx_shared_memory_block__DOT__curr_ind = 0U; + while (VL_GTS_III(1,32,32, 0x80U, vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__genblk2__BRA__2__KET____DOT__vx_shared_memory_block__DOT__curr_ind)) { + vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__genblk2__BRA__2__KET____DOT__vx_shared_memory_block__DOT__shared_memory[(0x7fU + & vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__genblk2__BRA__2__KET____DOT__vx_shared_memory_block__DOT__curr_ind)][0U] = 0U; + vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__genblk2__BRA__2__KET____DOT__vx_shared_memory_block__DOT__shared_memory[(0x7fU + & vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__genblk2__BRA__2__KET____DOT__vx_shared_memory_block__DOT__curr_ind)][1U] = 0U; + vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__genblk2__BRA__2__KET____DOT__vx_shared_memory_block__DOT__shared_memory[(0x7fU + & vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__genblk2__BRA__2__KET____DOT__vx_shared_memory_block__DOT__curr_ind)][2U] = 0U; + vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__genblk2__BRA__2__KET____DOT__vx_shared_memory_block__DOT__shared_memory[(0x7fU + & vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__genblk2__BRA__2__KET____DOT__vx_shared_memory_block__DOT__curr_ind)][3U] = 0U; + vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__genblk2__BRA__2__KET____DOT__vx_shared_memory_block__DOT__curr_ind + = ((IData)(1U) + vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__genblk2__BRA__2__KET____DOT__vx_shared_memory_block__DOT__curr_ind); + } + } else { + if (vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__genblk2__BRA__2__KET____DOT__shm_write) { + VL_ASSIGNSEL_WIII(32,(0x60U & ((IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__block_we) + << 1U)), + vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__genblk2__BRA__2__KET____DOT__vx_shared_memory_block__DOT__shared_memory + [(0x7fU & (vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__block_addr + >> 0xeU))], + (((0U == (0x1fU & ((IData)(0x100U) + + + (0x60U + & ((IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__block_we) + << 1U))))) + ? 0U : (vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__block_wdata[ + ((IData)(1U) + + (0xfU & + (((IData)(0x100U) + + (0x60U + & ((IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__block_we) + << 1U))) + >> 5U)))] + << ((IData)(0x20U) + - (0x1fU + & ((IData)(0x100U) + + + (0x60U + & ((IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__block_we) + << 1U))))))) + | (vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__block_wdata[ + (0xfU & (((IData)(0x100U) + + (0x60U + & ((IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__block_we) + << 1U))) + >> 5U))] + >> (0x1fU & ((IData)(0x100U) + + (0x60U + & ((IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__block_we) + << 1U))))))); + } + } + if (vlTOPp->reset) { + vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__genblk2__BRA__3__KET____DOT__vx_shared_memory_block__DOT__curr_ind = 0U; + while (VL_GTS_III(1,32,32, 0x80U, vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__genblk2__BRA__3__KET____DOT__vx_shared_memory_block__DOT__curr_ind)) { + vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__genblk2__BRA__3__KET____DOT__vx_shared_memory_block__DOT__shared_memory[(0x7fU + & vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__genblk2__BRA__3__KET____DOT__vx_shared_memory_block__DOT__curr_ind)][0U] = 0U; + vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__genblk2__BRA__3__KET____DOT__vx_shared_memory_block__DOT__shared_memory[(0x7fU + & vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__genblk2__BRA__3__KET____DOT__vx_shared_memory_block__DOT__curr_ind)][1U] = 0U; + vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__genblk2__BRA__3__KET____DOT__vx_shared_memory_block__DOT__shared_memory[(0x7fU + & vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__genblk2__BRA__3__KET____DOT__vx_shared_memory_block__DOT__curr_ind)][2U] = 0U; + vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__genblk2__BRA__3__KET____DOT__vx_shared_memory_block__DOT__shared_memory[(0x7fU + & vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__genblk2__BRA__3__KET____DOT__vx_shared_memory_block__DOT__curr_ind)][3U] = 0U; + vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__genblk2__BRA__3__KET____DOT__vx_shared_memory_block__DOT__curr_ind + = ((IData)(1U) + vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__genblk2__BRA__3__KET____DOT__vx_shared_memory_block__DOT__curr_ind); + } + } else { + if (vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__genblk2__BRA__3__KET____DOT__shm_write) { + VL_ASSIGNSEL_WIII(32,(0x60U & ((IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__block_we) + >> 1U)), + vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__genblk2__BRA__3__KET____DOT__vx_shared_memory_block__DOT__shared_memory + [(0x7fU & (vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__block_addr + >> 0x15U))], + (((0U == (0x1fU & ((IData)(0x180U) + + + (0x60U + & ((IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__block_we) + >> 1U))))) + ? 0U : (vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__block_wdata[ + ((IData)(1U) + + (0xfU & + (((IData)(0x180U) + + (0x60U + & ((IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__block_we) + >> 1U))) + >> 5U)))] + << ((IData)(0x20U) + - (0x1fU + & ((IData)(0x180U) + + + (0x60U + & ((IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__block_we) + >> 1U))))))) + | (vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__block_wdata[ + (0xfU & (((IData)(0x180U) + + (0x60U + & ((IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__block_we) + >> 1U))) + >> 5U))] + >> (0x1fU & ((IData)(0x180U) + + (0x60U + & ((IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__block_we) + >> 1U))))))); + } + } + vlTOPp->cache_simX__DOT__icache_i_m_ready = ((~ (IData)(vlTOPp->reset)) + & (1U + == (IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__state))); + vlTOPp->cache_simX__DOT__dcache_i_m_ready = ((~ (IData)(vlTOPp->reset)) + & (1U + == (IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT__state))); + vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__final_data_read + = ((IData)(vlTOPp->reset) ? 0U : vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__new_final_data_read_Qual); + vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT__final_data_read[0U] + = ((IData)(vlTOPp->reset) ? 0U : vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT__new_final_data_read_Qual[0U]); + vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT__final_data_read[1U] + = ((IData)(vlTOPp->reset) ? 0U : vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT__new_final_data_read_Qual[1U]); + vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT__final_data_read[2U] + = ((IData)(vlTOPp->reset) ? 0U : vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT__new_final_data_read_Qual[2U]); + vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT__final_data_read[3U] + = ((IData)(vlTOPp->reset) ? 0U : vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT__new_final_data_read_Qual[3U]); + if (vlTOPp->reset) { + __Vdlyvset__cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__data_structures__DOT__each_way__BRA__1__KET____DOT__data_structures__DOT__dirty__v0 = 1U; + } else { + if ((1U & (((~ (IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__data_structures__DOT____Vcellout__each_way__BRA__1__KET____DOT__data_structures__dirty_use)) + & (0U != (0xffffU & (vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__data_structures__DOT__we_per_way + >> 0x10U)))) + | ((IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__data_structures__DOT__write_from_mem_per_way) + >> 1U)))) { + __Vdlyvval__cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__data_structures__DOT__each_way__BRA__1__KET____DOT__data_structures__DOT__dirty__v32 + = ((2U & (IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__data_structures__DOT__write_from_mem_per_way)) + ? 0U : (1U & (0U != (0xffffU & + (vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__data_structures__DOT__we_per_way + >> 0x10U))))); + __Vdlyvset__cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__data_structures__DOT__each_way__BRA__1__KET____DOT__data_structures__DOT__dirty__v32 = 1U; + __Vdlyvdim0__cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__data_structures__DOT__each_way__BRA__1__KET____DOT__data_structures__DOT__dirty__v32 + = (0x1fU & (vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_addr + >> 4U)); + } + } + if (vlTOPp->reset) { + __Vdlyvset__cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__dirty__v0 = 1U; + } else { + if ((1U & (((~ (IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__data_structures__DOT____Vcellout__each_way__BRA__0__KET____DOT__data_structures__dirty_use)) + & (0U != (0xffffU & vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__data_structures__DOT__we_per_way))) + | (IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__data_structures__DOT__write_from_mem_per_way)))) { + __Vdlyvval__cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__dirty__v32 + = ((1U & (IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__data_structures__DOT__write_from_mem_per_way)) + ? 0U : (1U & (0U != (0xffffU & vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__data_structures__DOT__we_per_way)))); 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(IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__vx_priority_encoder_sm__DOT__new_left_requests) + : 0U)); + if (vlTOPp->reset) { + __Vdlyvset__cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__data_structures__DOT__each_way__BRA__1__KET____DOT__data_structures__DOT__valid__v0 = 1U; + } else { + if ((2U & (IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__data_structures__DOT__write_from_mem_per_way))) { + __Vdlyvset__cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__data_structures__DOT__each_way__BRA__1__KET____DOT__data_structures__DOT__valid__v32 = 1U; + __Vdlyvdim0__cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__data_structures__DOT__each_way__BRA__1__KET____DOT__data_structures__DOT__valid__v32 + = (0x1fU & (vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_addr + >> 4U)); + } + } + if (vlTOPp->reset) { + __Vdlyvset__cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__valid__v0 = 1U; + } else { + if ((1U & (IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__data_structures__DOT__write_from_mem_per_way))) { + __Vdlyvset__cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__valid__v32 = 1U; + __Vdlyvdim0__cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__valid__v32 + = (0x1fU & (vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_addr + >> 4U)); + } + } + if (vlTOPp->reset) { + __Vdlyvset__cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__data_structures__DOT__each_way__BRA__1__KET____DOT__data_structures__DOT__tag__v0 = 1U; + } else { + if ((2U & (IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__data_structures__DOT__write_from_mem_per_way))) { + __Vdlyvval__cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__data_structures__DOT__each_way__BRA__1__KET____DOT__data_structures__DOT__tag__v32 + = (0x7fffffU & (vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_addr + >> 9U)); + __Vdlyvset__cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__data_structures__DOT__each_way__BRA__1__KET____DOT__data_structures__DOT__tag__v32 = 1U; + __Vdlyvdim0__cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__data_structures__DOT__each_way__BRA__1__KET____DOT__data_structures__DOT__tag__v32 + = (0x1fU & (vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_addr + >> 4U)); + } + } + if (vlTOPp->reset) { + __Vdlyvset__cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__tag__v0 = 1U; + } else { + if ((1U & (IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__data_structures__DOT__write_from_mem_per_way))) { + __Vdlyvval__cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__tag__v32 + = (0x7fffffU & (vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_addr + >> 9U)); + __Vdlyvset__cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__tag__v32 = 1U; + __Vdlyvdim0__cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__tag__v32 + = (0x1fU & (vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_addr + >> 4U)); + } + } + vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__global_way_to_evict + = (1U & ((~ (IData)(vlTOPp->reset)) & (((2U + == (IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__state)) + & (0U + == (IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__new_state))) + ? ((IData)(1U) + + (IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__global_way_to_evict)) + : (IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__global_way_to_evict)))); + if (vlTOPp->reset) { + vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__miss_addr = 0U; + } else { + if ((0U == (IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__state))) { + vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__miss_addr + = ((IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__miss_found) + ? (vlTOPp->in_icache_pc_addr >> + (0x1fU & (((0U >= (IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__miss_bank_index)) + & ((IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT____Vcellout__genblk1__BRA__0__KET____DOT__choose_thread__index) + >> (IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__miss_bank_index))) + << 5U))) : 0U); + } + } + if (vlTOPp->reset) { + __Vdlyvset__cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__data_structures__DOT__each_way__BRA__1__KET____DOT__data_structures__DOT__data__v0 = 1U; + } else { + if ((0x10000U & vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__data_structures__DOT__we_per_way)) { + __Vdlyvval__cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__data_structures__DOT__each_way__BRA__1__KET____DOT__data_structures__DOT__data__v32 + = (0xffU & vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__data_structures__DOT__data_write_per_way[4U]); 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+ } + if (__Vdlyvset__cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__data__v39) { + VL_ASSIGNSEL_WIII(8,(IData)(__Vdlyvlsb__cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__data__v39), + vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__data + [__Vdlyvdim0__cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__data__v39], __Vdlyvval__cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__data__v39); + } + if (__Vdlyvset__cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__data__v40) { + VL_ASSIGNSEL_WIII(8,(IData)(__Vdlyvlsb__cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__data__v40), + vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__data + [__Vdlyvdim0__cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__data__v40], __Vdlyvval__cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__data__v40); + } + if (__Vdlyvset__cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__data__v41) { + VL_ASSIGNSEL_WIII(8,(IData)(__Vdlyvlsb__cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__data__v41), + vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__data + [__Vdlyvdim0__cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__data__v41], __Vdlyvval__cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__data__v41); + } + if (__Vdlyvset__cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__data__v42) { + VL_ASSIGNSEL_WIII(8,(IData)(__Vdlyvlsb__cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__data__v42), + vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__data + [__Vdlyvdim0__cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__data__v42], __Vdlyvval__cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__data__v42); + } + if (__Vdlyvset__cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__data__v43) { + VL_ASSIGNSEL_WIII(8,(IData)(__Vdlyvlsb__cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__data__v43), + vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__data + [__Vdlyvdim0__cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__data__v43], __Vdlyvval__cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__data__v43); + } + if (__Vdlyvset__cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__data__v44) { + VL_ASSIGNSEL_WIII(8,(IData)(__Vdlyvlsb__cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__data__v44), + vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__data + [__Vdlyvdim0__cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__data__v44], __Vdlyvval__cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__data__v44); + } + if (__Vdlyvset__cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__data__v45) { + VL_ASSIGNSEL_WIII(8,(IData)(__Vdlyvlsb__cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__data__v45), + vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__data + [__Vdlyvdim0__cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__data__v45], __Vdlyvval__cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__data__v45); + } + if (__Vdlyvset__cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__data__v46) { + VL_ASSIGNSEL_WIII(8,(IData)(__Vdlyvlsb__cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__data__v46), + vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__data + [__Vdlyvdim0__cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__data__v46], __Vdlyvval__cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__data__v46); + } + if (__Vdlyvset__cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__data__v47) { + VL_ASSIGNSEL_WIII(8,(IData)(__Vdlyvlsb__cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__data__v47), + vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__data + [__Vdlyvdim0__cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__data__v47], __Vdlyvval__cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__data__v47); + } + vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__way_to_update + = vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__global_way_to_evict; + vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__state + = ((IData)(vlTOPp->reset) ? 0U : (IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__new_state)); + vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT__state + = ((IData)(vlTOPp->reset) ? 0U : (IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT__new_state)); +} + +VL_INLINE_OPT void Vcache_simX::_combo__TOP__5(Vcache_simX__Syms* __restrict vlSymsp) { + VL_DEBUG_IF(VL_DBG_MSGF("+ Vcache_simX::_combo__TOP__5\n"); ); + Vcache_simX* __restrict vlTOPp VL_ATTR_UNUSED = vlSymsp->TOPp; + // Variables + WData/*31:0*/ __Vtemp132[4]; + WData/*31:0*/ __Vtemp133[4]; + WData/*31:0*/ __Vtemp134[4]; + WData/*31:0*/ __Vtemp135[4]; + // Body + vlSymsp->TOP__cache_simX__DOT__VX_dcache_req.out_cache_driver_in_address[0U] + = vlTOPp->in_dcache_in_address[0U]; + vlSymsp->TOP__cache_simX__DOT__VX_dcache_req.out_cache_driver_in_address[1U] + = vlTOPp->in_dcache_in_address[1U]; + vlSymsp->TOP__cache_simX__DOT__VX_dcache_req.out_cache_driver_in_address[2U] + = vlTOPp->in_dcache_in_address[2U]; + vlSymsp->TOP__cache_simX__DOT__VX_dcache_req.out_cache_driver_in_address[3U] + = vlTOPp->in_dcache_in_address[3U]; + vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__use_valid + = ((IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__stored_valid) + ? (IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__stored_valid) + : (IData)(vlTOPp->in_icache_valid_pc_addr)); + vlTOPp->cache_simX__DOT__dmem_controller__DOT__sm_driver_in_valid + = ((IData)(vlSymsp->TOP__cache_simX__DOT__VX_dcache_req.out_cache_driver_in_valid) + & VL_NEGATE_I((IData)((0xffU == (0xffU & + ((vlSymsp->TOP__cache_simX__DOT__VX_dcache_req.out_cache_driver_in_address[1U] + << 8U) + | (vlSymsp->TOP__cache_simX__DOT__VX_dcache_req.out_cache_driver_in_address[0U] + >> 0x18U))))))); + vlTOPp->cache_simX__DOT__dmem_controller__DOT__cache_driver_in_valid + = ((IData)(vlSymsp->TOP__cache_simX__DOT__VX_dcache_req.out_cache_driver_in_valid) + & VL_NEGATE_I((IData)((0xffU != (0xffU & + ((vlSymsp->TOP__cache_simX__DOT__VX_dcache_req.out_cache_driver_in_address[1U] + << 8U) + | (vlSymsp->TOP__cache_simX__DOT__VX_dcache_req.out_cache_driver_in_address[0U] + >> 0x18U))))))); + vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__multip_banks__DOT____Vlvbound1 + = vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__use_valid; + vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT____Vcellout__multip_banks__thread_track_banks + = vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__multip_banks__DOT____Vlvbound1; + vlTOPp->cache_simX__DOT__dmem_controller__DOT__sm_driver_in_mem_read + = ((0U != (IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__sm_driver_in_valid)) + ? (IData)(vlTOPp->in_dcache_mem_read) : 7U); + vlTOPp->cache_simX__DOT__dmem_controller__DOT__sm_driver_in_mem_write + = ((0U != (IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__sm_driver_in_valid)) + ? (IData)(vlTOPp->in_dcache_mem_write) : 7U); + vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__orig_in_valid + = ((0xeU & (IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__orig_in_valid)) + | (1U & (IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__sm_driver_in_valid))); + vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__orig_in_valid + = ((0xdU & (IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__orig_in_valid)) + | (2U & (IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__sm_driver_in_valid))); + vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__orig_in_valid + = ((0xbU & (IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__orig_in_valid)) + | (4U & (IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__sm_driver_in_valid))); + vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__orig_in_valid + = ((7U & (IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__orig_in_valid)) + | (8U & (IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__sm_driver_in_valid))); + vlTOPp->cache_simX__DOT__dmem_controller__DOT__read_or_write + = ((7U != (IData)(vlTOPp->in_dcache_mem_write)) + & (0U != (IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__cache_driver_in_valid))); + vlTOPp->cache_simX__DOT__dmem_controller__DOT__cache_driver_in_mem_write + = ((0U != (IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__cache_driver_in_valid)) + ? (IData)(vlTOPp->in_dcache_mem_write) : 7U); + vlTOPp->cache_simX__DOT__dmem_controller__DOT__cache_driver_in_mem_read + = ((0U != (IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__cache_driver_in_valid)) + ? (IData)(vlTOPp->in_dcache_mem_read) : 7U); + vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT__use_valid + = ((0U == (IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT__stored_valid)) + ? (IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__cache_driver_in_valid) + : (IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT__stored_valid)); + vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__valid_per_bank = 0U; + if (vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT____Vcellout__multip_banks__thread_track_banks) { + vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__valid_per_bank = 1U; + } + vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT____Vcellout__genblk1__BRA__0__KET____DOT__choose_thread__index = 0U; + if (vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT____Vcellout__multip_banks__thread_track_banks) { + vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT____Vcellout__genblk1__BRA__0__KET____DOT__choose_thread__index = 0U; + } + vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__vx_priority_encoder_sm__DOT__use_valid + = ((0U != (IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__vx_priority_encoder_sm__DOT__left_requests)) + ? (IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__vx_priority_encoder_sm__DOT__left_requests) + : (IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__orig_in_valid)); + vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT____Vcellout__multip_banks__thread_track_banks = 0U; + vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT____Vcellout__multip_banks__thread_track_banks + = (((~ ((IData)(1U) << (0xcU & vlSymsp->TOP__cache_simX__DOT__VX_dcache_req.out_cache_driver_in_address[0U]))) + & (IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT____Vcellout__multip_banks__thread_track_banks)) + | ((1U & (IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT__use_valid)) + << (0xcU & vlSymsp->TOP__cache_simX__DOT__VX_dcache_req.out_cache_driver_in_address[0U]))); + vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT____Vcellout__multip_banks__thread_track_banks + = (((~ ((IData)(1U) << (0xfU & ((IData)(1U) + + (0xcU & vlSymsp->TOP__cache_simX__DOT__VX_dcache_req.out_cache_driver_in_address[1U]))))) + & (IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT____Vcellout__multip_banks__thread_track_banks)) + | ((1U & ((IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT__use_valid) + >> 1U)) << (0xfU & ((IData)(1U) + + (0xcU & + vlSymsp->TOP__cache_simX__DOT__VX_dcache_req.out_cache_driver_in_address[1U]))))); + vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT____Vcellout__multip_banks__thread_track_banks + = (((~ ((IData)(1U) << (0xfU & ((IData)(2U) + + (0xcU & vlSymsp->TOP__cache_simX__DOT__VX_dcache_req.out_cache_driver_in_address[2U]))))) + & (IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT____Vcellout__multip_banks__thread_track_banks)) + | ((1U & ((IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT__use_valid) + >> 2U)) << (0xfU & ((IData)(2U) + + (0xcU & + vlSymsp->TOP__cache_simX__DOT__VX_dcache_req.out_cache_driver_in_address[2U]))))); + vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT____Vcellout__multip_banks__thread_track_banks + = (((~ ((IData)(1U) << (0xfU & ((IData)(3U) + + (0xcU & vlSymsp->TOP__cache_simX__DOT__VX_dcache_req.out_cache_driver_in_address[3U]))))) + & (IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT____Vcellout__multip_banks__thread_track_banks)) + | ((1U & ((IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT__use_valid) + >> 3U)) << (0xfU & ((IData)(3U) + + (0xcU & + vlSymsp->TOP__cache_simX__DOT__VX_dcache_req.out_cache_driver_in_address[3U]))))); + vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__use_valid_in + = (((2U == (IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__state)) + & (IData)(vlTOPp->cache_simX__DOT__icache_i_m_ready)) + | ((~ ((2U == (IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__state)) + & (~ (IData)(vlTOPp->cache_simX__DOT__icache_i_m_ready)))) + & ((1U != (IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__state)) + & (IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__valid_per_bank)))); + vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_addr + = ((1U == (IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__state)) + ? vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__miss_addr + : ((2U == (IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__state)) + ? vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__miss_addr + : (vlTOPp->in_icache_pc_addr >> (0x1fU + & ((IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT____Vcellout__genblk1__BRA__0__KET____DOT__choose_thread__index) + << 5U))))); + vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__vx_priority_encoder_sm__DOT____Vcellout__vx_bank_valid__bank_valids + = ((0xfffeU & (IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__vx_priority_encoder_sm__DOT____Vcellout__vx_bank_valid__bank_valids)) + | ((IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__vx_priority_encoder_sm__DOT__use_valid) + & (0U == (3U & ((vlSymsp->TOP__cache_simX__DOT__VX_dcache_req.out_cache_driver_in_address[1U] + << 0x1eU) | (vlSymsp->TOP__cache_simX__DOT__VX_dcache_req.out_cache_driver_in_address[0U] + >> 2U)))))); + vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__vx_priority_encoder_sm__DOT____Vcellout__vx_bank_valid__bank_valids + = ((0xfffdU & (IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__vx_priority_encoder_sm__DOT____Vcellout__vx_bank_valid__bank_valids)) + | (0xfffffffeU & ((IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__vx_priority_encoder_sm__DOT__use_valid) + & ((0U == (3U & ((vlSymsp->TOP__cache_simX__DOT__VX_dcache_req.out_cache_driver_in_address[2U] + << 0x1eU) + | (vlSymsp->TOP__cache_simX__DOT__VX_dcache_req.out_cache_driver_in_address[1U] + >> 2U)))) + << 1U)))); + vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__vx_priority_encoder_sm__DOT____Vcellout__vx_bank_valid__bank_valids + = ((0xfffbU & (IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__vx_priority_encoder_sm__DOT____Vcellout__vx_bank_valid__bank_valids)) + | (0xfffffffcU & ((IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__vx_priority_encoder_sm__DOT__use_valid) + & ((0U == (3U & ((vlSymsp->TOP__cache_simX__DOT__VX_dcache_req.out_cache_driver_in_address[3U] + << 0x1eU) + | (vlSymsp->TOP__cache_simX__DOT__VX_dcache_req.out_cache_driver_in_address[2U] + >> 2U)))) + << 2U)))); + vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__vx_priority_encoder_sm__DOT____Vcellout__vx_bank_valid__bank_valids + = ((0xfff7U & (IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__vx_priority_encoder_sm__DOT____Vcellout__vx_bank_valid__bank_valids)) + | (0xfffffff8U & ((IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__vx_priority_encoder_sm__DOT__use_valid) + & ((0U == (3U & (vlSymsp->TOP__cache_simX__DOT__VX_dcache_req.out_cache_driver_in_address[3U] + >> 2U))) + << 3U)))); + vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__vx_priority_encoder_sm__DOT____Vcellout__vx_bank_valid__bank_valids + = ((0xffefU & (IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__vx_priority_encoder_sm__DOT____Vcellout__vx_bank_valid__bank_valids)) + | (((IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__vx_priority_encoder_sm__DOT__use_valid) + & (1U == (3U & ((vlSymsp->TOP__cache_simX__DOT__VX_dcache_req.out_cache_driver_in_address[1U] + << 0x1eU) | (vlSymsp->TOP__cache_simX__DOT__VX_dcache_req.out_cache_driver_in_address[0U] + >> 2U))))) + << 4U)); + vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__vx_priority_encoder_sm__DOT____Vcellout__vx_bank_valid__bank_valids + = ((0xffdfU & (IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__vx_priority_encoder_sm__DOT____Vcellout__vx_bank_valid__bank_valids)) + | (0xffffffe0U & (((IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__vx_priority_encoder_sm__DOT__use_valid) + << 4U) & ((1U == (3U + & ((vlSymsp->TOP__cache_simX__DOT__VX_dcache_req.out_cache_driver_in_address[2U] + << 0x1eU) + | (vlSymsp->TOP__cache_simX__DOT__VX_dcache_req.out_cache_driver_in_address[1U] + >> 2U)))) + << 5U)))); + vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__vx_priority_encoder_sm__DOT____Vcellout__vx_bank_valid__bank_valids + = ((0xffbfU & (IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__vx_priority_encoder_sm__DOT____Vcellout__vx_bank_valid__bank_valids)) + | (0xffffffc0U & (((IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__vx_priority_encoder_sm__DOT__use_valid) + << 4U) & ((1U == (3U + & ((vlSymsp->TOP__cache_simX__DOT__VX_dcache_req.out_cache_driver_in_address[3U] + << 0x1eU) + | (vlSymsp->TOP__cache_simX__DOT__VX_dcache_req.out_cache_driver_in_address[2U] + >> 2U)))) + << 6U)))); + vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__vx_priority_encoder_sm__DOT____Vcellout__vx_bank_valid__bank_valids + = ((0xff7fU & (IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__vx_priority_encoder_sm__DOT____Vcellout__vx_bank_valid__bank_valids)) + | (0xffffff80U & (((IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__vx_priority_encoder_sm__DOT__use_valid) + << 4U) & ((1U == (3U + & (vlSymsp->TOP__cache_simX__DOT__VX_dcache_req.out_cache_driver_in_address[3U] + >> 2U))) + << 7U)))); + vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__vx_priority_encoder_sm__DOT____Vcellout__vx_bank_valid__bank_valids + = ((0xfeffU & (IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__vx_priority_encoder_sm__DOT____Vcellout__vx_bank_valid__bank_valids)) + | (((IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__vx_priority_encoder_sm__DOT__use_valid) + & (2U == (3U & ((vlSymsp->TOP__cache_simX__DOT__VX_dcache_req.out_cache_driver_in_address[1U] + << 0x1eU) | (vlSymsp->TOP__cache_simX__DOT__VX_dcache_req.out_cache_driver_in_address[0U] + >> 2U))))) + << 8U)); + vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__vx_priority_encoder_sm__DOT____Vcellout__vx_bank_valid__bank_valids + = ((0xfdffU & (IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__vx_priority_encoder_sm__DOT____Vcellout__vx_bank_valid__bank_valids)) + | (0xfffffe00U & (((IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__vx_priority_encoder_sm__DOT__use_valid) + << 8U) & ((2U == (3U + & ((vlSymsp->TOP__cache_simX__DOT__VX_dcache_req.out_cache_driver_in_address[2U] + << 0x1eU) + | (vlSymsp->TOP__cache_simX__DOT__VX_dcache_req.out_cache_driver_in_address[1U] + >> 2U)))) + << 9U)))); + vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__vx_priority_encoder_sm__DOT____Vcellout__vx_bank_valid__bank_valids + = ((0xfbffU & (IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__vx_priority_encoder_sm__DOT____Vcellout__vx_bank_valid__bank_valids)) + | (0xfffffc00U & (((IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__vx_priority_encoder_sm__DOT__use_valid) + << 8U) & ((2U == (3U + & ((vlSymsp->TOP__cache_simX__DOT__VX_dcache_req.out_cache_driver_in_address[3U] + << 0x1eU) + | (vlSymsp->TOP__cache_simX__DOT__VX_dcache_req.out_cache_driver_in_address[2U] + >> 2U)))) + << 0xaU)))); + vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__vx_priority_encoder_sm__DOT____Vcellout__vx_bank_valid__bank_valids + = ((0xf7ffU & (IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__vx_priority_encoder_sm__DOT____Vcellout__vx_bank_valid__bank_valids)) + | (0xfffff800U & (((IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__vx_priority_encoder_sm__DOT__use_valid) + << 8U) & ((2U == (3U + & (vlSymsp->TOP__cache_simX__DOT__VX_dcache_req.out_cache_driver_in_address[3U] + >> 2U))) + << 0xbU)))); + vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__vx_priority_encoder_sm__DOT____Vcellout__vx_bank_valid__bank_valids + = ((0xefffU & (IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__vx_priority_encoder_sm__DOT____Vcellout__vx_bank_valid__bank_valids)) + | (((IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__vx_priority_encoder_sm__DOT__use_valid) + & (3U == (3U & ((vlSymsp->TOP__cache_simX__DOT__VX_dcache_req.out_cache_driver_in_address[1U] + << 0x1eU) | (vlSymsp->TOP__cache_simX__DOT__VX_dcache_req.out_cache_driver_in_address[0U] + >> 2U))))) + << 0xcU)); + vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__vx_priority_encoder_sm__DOT____Vcellout__vx_bank_valid__bank_valids + = ((0xdfffU & (IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__vx_priority_encoder_sm__DOT____Vcellout__vx_bank_valid__bank_valids)) + | (0xffffe000U & (((IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__vx_priority_encoder_sm__DOT__use_valid) + << 0xcU) & ((3U == (3U + & ((vlSymsp->TOP__cache_simX__DOT__VX_dcache_req.out_cache_driver_in_address[2U] + << 0x1eU) + | (vlSymsp->TOP__cache_simX__DOT__VX_dcache_req.out_cache_driver_in_address[1U] + >> 2U)))) + << 0xdU)))); + vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__vx_priority_encoder_sm__DOT____Vcellout__vx_bank_valid__bank_valids + = ((0xbfffU & (IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__vx_priority_encoder_sm__DOT____Vcellout__vx_bank_valid__bank_valids)) + | (0xffffc000U & (((IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__vx_priority_encoder_sm__DOT__use_valid) + << 0xcU) & ((3U == (3U + & ((vlSymsp->TOP__cache_simX__DOT__VX_dcache_req.out_cache_driver_in_address[3U] + << 0x1eU) + | (vlSymsp->TOP__cache_simX__DOT__VX_dcache_req.out_cache_driver_in_address[2U] + >> 2U)))) + << 0xeU)))); + vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__vx_priority_encoder_sm__DOT____Vcellout__vx_bank_valid__bank_valids + = ((0x7fffU & (IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__vx_priority_encoder_sm__DOT____Vcellout__vx_bank_valid__bank_valids)) + | (0xffff8000U & (((IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__vx_priority_encoder_sm__DOT__use_valid) + << 0xcU) & ((3U == (3U + & (vlSymsp->TOP__cache_simX__DOT__VX_dcache_req.out_cache_driver_in_address[3U] + >> 2U))) + << 0xfU)))); + vlTOPp->__Vtableidx6 = (0xfU & (IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT____Vcellout__multip_banks__thread_track_banks)); + vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT____Vcellout__genblk1__BRA__0__KET____DOT__choose_thread__index + = vlTOPp->__Vtable6_cache_simX__DOT__dmem_controller__DOT__dcache__DOT____Vcellout__genblk1__BRA__0__KET____DOT__choose_thread__index + [vlTOPp->__Vtableidx6]; + vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT____Vcellout__genblk1__BRA__0__KET____DOT__choose_thread__found + = vlTOPp->__Vtable6_cache_simX__DOT__dmem_controller__DOT__dcache__DOT____Vcellout__genblk1__BRA__0__KET____DOT__choose_thread__found + [vlTOPp->__Vtableidx6]; + vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk1__BRA__0__KET____DOT__choose_thread__DOT__i + = vlTOPp->__Vtable6_cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk1__BRA__0__KET____DOT__choose_thread__DOT__i + [vlTOPp->__Vtableidx6]; + vlTOPp->__Vtableidx7 = (0xfU & ((IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT____Vcellout__multip_banks__thread_track_banks) + >> 4U)); + vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT____Vcellout__genblk1__BRA__1__KET____DOT__choose_thread__index + = vlTOPp->__Vtable7_cache_simX__DOT__dmem_controller__DOT__dcache__DOT____Vcellout__genblk1__BRA__1__KET____DOT__choose_thread__index + [vlTOPp->__Vtableidx7]; + vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT____Vcellout__genblk1__BRA__1__KET____DOT__choose_thread__found + = vlTOPp->__Vtable7_cache_simX__DOT__dmem_controller__DOT__dcache__DOT____Vcellout__genblk1__BRA__1__KET____DOT__choose_thread__found + [vlTOPp->__Vtableidx7]; + vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk1__BRA__1__KET____DOT__choose_thread__DOT__i + = vlTOPp->__Vtable7_cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk1__BRA__1__KET____DOT__choose_thread__DOT__i + [vlTOPp->__Vtableidx7]; + vlTOPp->__Vtableidx8 = (0xfU & ((IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT____Vcellout__multip_banks__thread_track_banks) + >> 8U)); + vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT____Vcellout__genblk1__BRA__2__KET____DOT__choose_thread__index + = vlTOPp->__Vtable8_cache_simX__DOT__dmem_controller__DOT__dcache__DOT____Vcellout__genblk1__BRA__2__KET____DOT__choose_thread__index + [vlTOPp->__Vtableidx8]; + vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT____Vcellout__genblk1__BRA__2__KET____DOT__choose_thread__found + = vlTOPp->__Vtable8_cache_simX__DOT__dmem_controller__DOT__dcache__DOT____Vcellout__genblk1__BRA__2__KET____DOT__choose_thread__found + [vlTOPp->__Vtableidx8]; + vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk1__BRA__2__KET____DOT__choose_thread__DOT__i + = vlTOPp->__Vtable8_cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk1__BRA__2__KET____DOT__choose_thread__DOT__i + [vlTOPp->__Vtableidx8]; + vlTOPp->__Vtableidx9 = (0xfU & ((IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT____Vcellout__multip_banks__thread_track_banks) + >> 0xcU)); + vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT____Vcellout__genblk1__BRA__3__KET____DOT__choose_thread__index + = vlTOPp->__Vtable9_cache_simX__DOT__dmem_controller__DOT__dcache__DOT____Vcellout__genblk1__BRA__3__KET____DOT__choose_thread__index + [vlTOPp->__Vtableidx9]; + vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT____Vcellout__genblk1__BRA__3__KET____DOT__choose_thread__found + = vlTOPp->__Vtable9_cache_simX__DOT__dmem_controller__DOT__dcache__DOT____Vcellout__genblk1__BRA__3__KET____DOT__choose_thread__found + [vlTOPp->__Vtableidx9]; + vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk1__BRA__3__KET____DOT__choose_thread__DOT__i + = vlTOPp->__Vtable9_cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk1__BRA__3__KET____DOT__choose_thread__DOT__i + [vlTOPp->__Vtableidx9]; + vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__write_from_mem + = ((2U == (IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__state)) + & (IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__use_valid_in)); + vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__access + = ((0U == (IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__state)) + & (IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__use_valid_in)); + vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__sb_mask + = ((0U == (3U & vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_addr)) + ? 1U : ((1U == (3U & vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_addr)) + ? 2U : ((2U == (3U & vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_addr)) + ? 4U : 8U))); + vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__data_structures__DOT____Vcellout__each_way__BRA__0__KET____DOT__data_structures__dirty_use + = vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__dirty + [(0x1fU & (vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_addr + >> 4U))]; + vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__data_structures__DOT____Vcellout__each_way__BRA__1__KET____DOT__data_structures__dirty_use + = vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__data_structures__DOT__each_way__BRA__1__KET____DOT__data_structures__DOT__dirty + [(0x1fU & (vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_addr + >> 4U))]; + vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__data_structures__DOT__data_use_per_way[0U] + = vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__data + [(0x1fU & (vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_addr + >> 4U))][0U]; + vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__data_structures__DOT__data_use_per_way[1U] + = vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__data + [(0x1fU & (vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_addr + >> 4U))][1U]; + vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__data_structures__DOT__data_use_per_way[2U] + = vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__data + [(0x1fU & (vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_addr + >> 4U))][2U]; + vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__data_structures__DOT__data_use_per_way[3U] + = vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__data + [(0x1fU & (vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_addr + >> 4U))][3U]; + vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__data_structures__DOT__data_use_per_way[4U] + = vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__data_structures__DOT__each_way__BRA__1__KET____DOT__data_structures__DOT__data + [(0x1fU & (vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_addr + >> 4U))][0U]; + vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__data_structures__DOT__data_use_per_way[5U] + = vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__data_structures__DOT__each_way__BRA__1__KET____DOT__data_structures__DOT__data + [(0x1fU & (vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_addr + >> 4U))][1U]; + vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__data_structures__DOT__data_use_per_way[6U] + = vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__data_structures__DOT__each_way__BRA__1__KET____DOT__data_structures__DOT__data + [(0x1fU & (vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_addr + >> 4U))][2U]; + vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__data_structures__DOT__data_use_per_way[7U] + = vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__data_structures__DOT__each_way__BRA__1__KET____DOT__data_structures__DOT__data + [(0x1fU & (vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_addr + >> 4U))][3U]; + vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__data_structures__DOT__tag_use_per_way + = ((VL_ULL(0x3fffff800000) & vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__data_structures__DOT__tag_use_per_way) + | (IData)((IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__tag + [(0x1fU & (vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_addr + >> 4U))]))); + vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__data_structures__DOT__tag_use_per_way + = ((VL_ULL(0x7fffff) & vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__data_structures__DOT__tag_use_per_way) + | ((QData)((IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__data_structures__DOT__each_way__BRA__1__KET____DOT__data_structures__DOT__tag + [(0x1fU & (vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_addr + >> 4U))])) + << 0x17U)); + vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__data_structures__DOT__valid_use_per_way + = ((2U & (IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__data_structures__DOT__valid_use_per_way)) + | vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__valid + [(0x1fU & (vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_addr + >> 4U))]); + vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__data_structures__DOT__valid_use_per_way + = ((1U & (IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__data_structures__DOT__valid_use_per_way)) + | (vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__data_structures__DOT__each_way__BRA__1__KET____DOT__data_structures__DOT__valid + [(0x1fU & (vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_addr + >> 4U))] << 1U)); + vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__vx_priority_encoder_sm__DOT__genblk1__BRA__0__KET____DOT__num_valids = 0U; + if ((8U & (IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__vx_priority_encoder_sm__DOT____Vcellout__vx_bank_valid__bank_valids))) { + vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__vx_priority_encoder_sm__DOT__genblk1__BRA__0__KET____DOT__num_valids + = (7U & ((IData)(1U) + (IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__vx_priority_encoder_sm__DOT__genblk1__BRA__0__KET____DOT__num_valids))); + } + if ((4U & (IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__vx_priority_encoder_sm__DOT____Vcellout__vx_bank_valid__bank_valids))) { + vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__vx_priority_encoder_sm__DOT__genblk1__BRA__0__KET____DOT__num_valids + = (7U & ((IData)(1U) + (IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__vx_priority_encoder_sm__DOT__genblk1__BRA__0__KET____DOT__num_valids))); + } + if ((2U & (IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__vx_priority_encoder_sm__DOT____Vcellout__vx_bank_valid__bank_valids))) { + vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__vx_priority_encoder_sm__DOT__genblk1__BRA__0__KET____DOT__num_valids + = (7U & ((IData)(1U) + (IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__vx_priority_encoder_sm__DOT__genblk1__BRA__0__KET____DOT__num_valids))); + } + if ((1U & (IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__vx_priority_encoder_sm__DOT____Vcellout__vx_bank_valid__bank_valids))) { + vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__vx_priority_encoder_sm__DOT__genblk1__BRA__0__KET____DOT__num_valids + = (7U & ((IData)(1U) + (IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__vx_priority_encoder_sm__DOT__genblk1__BRA__0__KET____DOT__num_valids))); + } + vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__vx_priority_encoder_sm__DOT__genblk1__BRA__1__KET____DOT__num_valids = 0U; + if ((0x80U & (IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__vx_priority_encoder_sm__DOT____Vcellout__vx_bank_valid__bank_valids))) { + vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__vx_priority_encoder_sm__DOT__genblk1__BRA__1__KET____DOT__num_valids + = (7U & ((IData)(1U) + (IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__vx_priority_encoder_sm__DOT__genblk1__BRA__1__KET____DOT__num_valids))); + } + if ((0x40U & (IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__vx_priority_encoder_sm__DOT____Vcellout__vx_bank_valid__bank_valids))) { + vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__vx_priority_encoder_sm__DOT__genblk1__BRA__1__KET____DOT__num_valids + = (7U & ((IData)(1U) + (IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__vx_priority_encoder_sm__DOT__genblk1__BRA__1__KET____DOT__num_valids))); + } + if ((0x20U & (IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__vx_priority_encoder_sm__DOT____Vcellout__vx_bank_valid__bank_valids))) { + vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__vx_priority_encoder_sm__DOT__genblk1__BRA__1__KET____DOT__num_valids + = (7U & ((IData)(1U) + (IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__vx_priority_encoder_sm__DOT__genblk1__BRA__1__KET____DOT__num_valids))); + } + if ((0x10U & (IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__vx_priority_encoder_sm__DOT____Vcellout__vx_bank_valid__bank_valids))) { + vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__vx_priority_encoder_sm__DOT__genblk1__BRA__1__KET____DOT__num_valids + = (7U & ((IData)(1U) + (IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__vx_priority_encoder_sm__DOT__genblk1__BRA__1__KET____DOT__num_valids))); + } + vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__vx_priority_encoder_sm__DOT__genblk1__BRA__2__KET____DOT__num_valids = 0U; + if ((0x800U & (IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__vx_priority_encoder_sm__DOT____Vcellout__vx_bank_valid__bank_valids))) { + vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__vx_priority_encoder_sm__DOT__genblk1__BRA__2__KET____DOT__num_valids + = (7U & ((IData)(1U) + (IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__vx_priority_encoder_sm__DOT__genblk1__BRA__2__KET____DOT__num_valids))); + } + if ((0x400U & (IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__vx_priority_encoder_sm__DOT____Vcellout__vx_bank_valid__bank_valids))) { + vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__vx_priority_encoder_sm__DOT__genblk1__BRA__2__KET____DOT__num_valids + = (7U & ((IData)(1U) + (IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__vx_priority_encoder_sm__DOT__genblk1__BRA__2__KET____DOT__num_valids))); + } + if ((0x200U & (IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__vx_priority_encoder_sm__DOT____Vcellout__vx_bank_valid__bank_valids))) { + vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__vx_priority_encoder_sm__DOT__genblk1__BRA__2__KET____DOT__num_valids + = (7U & ((IData)(1U) + (IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__vx_priority_encoder_sm__DOT__genblk1__BRA__2__KET____DOT__num_valids))); + } + if ((0x100U & (IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__vx_priority_encoder_sm__DOT____Vcellout__vx_bank_valid__bank_valids))) { + vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__vx_priority_encoder_sm__DOT__genblk1__BRA__2__KET____DOT__num_valids + = (7U & ((IData)(1U) + (IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__vx_priority_encoder_sm__DOT__genblk1__BRA__2__KET____DOT__num_valids))); + } + vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__vx_priority_encoder_sm__DOT__genblk1__BRA__3__KET____DOT__num_valids = 0U; + if ((0x8000U & (IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__vx_priority_encoder_sm__DOT____Vcellout__vx_bank_valid__bank_valids))) { + vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__vx_priority_encoder_sm__DOT__genblk1__BRA__3__KET____DOT__num_valids + = (7U & ((IData)(1U) + (IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__vx_priority_encoder_sm__DOT__genblk1__BRA__3__KET____DOT__num_valids))); + } + if ((0x4000U & (IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__vx_priority_encoder_sm__DOT____Vcellout__vx_bank_valid__bank_valids))) { + vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__vx_priority_encoder_sm__DOT__genblk1__BRA__3__KET____DOT__num_valids + = (7U & ((IData)(1U) + (IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__vx_priority_encoder_sm__DOT__genblk1__BRA__3__KET____DOT__num_valids))); + } + if ((0x2000U & (IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__vx_priority_encoder_sm__DOT____Vcellout__vx_bank_valid__bank_valids))) { + vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__vx_priority_encoder_sm__DOT__genblk1__BRA__3__KET____DOT__num_valids + = (7U & ((IData)(1U) + (IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__vx_priority_encoder_sm__DOT__genblk1__BRA__3__KET____DOT__num_valids))); + } + if ((0x1000U & (IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__vx_priority_encoder_sm__DOT____Vcellout__vx_bank_valid__bank_valids))) { + vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__vx_priority_encoder_sm__DOT__genblk1__BRA__3__KET____DOT__num_valids + = (7U & ((IData)(1U) + (IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__vx_priority_encoder_sm__DOT__genblk1__BRA__3__KET____DOT__num_valids))); + } + vlTOPp->__Vtableidx1 = (0xfU & (IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__vx_priority_encoder_sm__DOT____Vcellout__vx_bank_valid__bank_valids)); + vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__vx_priority_encoder_sm__DOT____Vcellout__genblk2__BRA__0__KET____DOT__vx_priority_encoder__index + = vlTOPp->__Vtable1_cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__vx_priority_encoder_sm__DOT____Vcellout__genblk2__BRA__0__KET____DOT__vx_priority_encoder__index + [vlTOPp->__Vtableidx1]; + vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__vx_priority_encoder_sm__DOT____Vcellout__genblk2__BRA__0__KET____DOT__vx_priority_encoder__found + = vlTOPp->__Vtable1_cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__vx_priority_encoder_sm__DOT____Vcellout__genblk2__BRA__0__KET____DOT__vx_priority_encoder__found + [vlTOPp->__Vtableidx1]; + vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__vx_priority_encoder_sm__DOT__genblk2__BRA__0__KET____DOT__vx_priority_encoder__DOT__i + = vlTOPp->__Vtable1_cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__vx_priority_encoder_sm__DOT__genblk2__BRA__0__KET____DOT__vx_priority_encoder__DOT__i + [vlTOPp->__Vtableidx1]; + vlTOPp->__Vtableidx2 = (0xfU & ((IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__vx_priority_encoder_sm__DOT____Vcellout__vx_bank_valid__bank_valids) + >> 4U)); + vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__vx_priority_encoder_sm__DOT____Vcellout__genblk2__BRA__1__KET____DOT__vx_priority_encoder__index + = vlTOPp->__Vtable2_cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__vx_priority_encoder_sm__DOT____Vcellout__genblk2__BRA__1__KET____DOT__vx_priority_encoder__index + [vlTOPp->__Vtableidx2]; + vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__vx_priority_encoder_sm__DOT____Vcellout__genblk2__BRA__1__KET____DOT__vx_priority_encoder__found + = vlTOPp->__Vtable2_cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__vx_priority_encoder_sm__DOT____Vcellout__genblk2__BRA__1__KET____DOT__vx_priority_encoder__found + [vlTOPp->__Vtableidx2]; + vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__vx_priority_encoder_sm__DOT__genblk2__BRA__1__KET____DOT__vx_priority_encoder__DOT__i + = vlTOPp->__Vtable2_cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__vx_priority_encoder_sm__DOT__genblk2__BRA__1__KET____DOT__vx_priority_encoder__DOT__i + [vlTOPp->__Vtableidx2]; + vlTOPp->__Vtableidx3 = (0xfU & ((IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__vx_priority_encoder_sm__DOT____Vcellout__vx_bank_valid__bank_valids) + >> 8U)); + vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__vx_priority_encoder_sm__DOT____Vcellout__genblk2__BRA__2__KET____DOT__vx_priority_encoder__index + = vlTOPp->__Vtable3_cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__vx_priority_encoder_sm__DOT____Vcellout__genblk2__BRA__2__KET____DOT__vx_priority_encoder__index + [vlTOPp->__Vtableidx3]; + vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__vx_priority_encoder_sm__DOT____Vcellout__genblk2__BRA__2__KET____DOT__vx_priority_encoder__found + = vlTOPp->__Vtable3_cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__vx_priority_encoder_sm__DOT____Vcellout__genblk2__BRA__2__KET____DOT__vx_priority_encoder__found + [vlTOPp->__Vtableidx3]; + vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__vx_priority_encoder_sm__DOT__genblk2__BRA__2__KET____DOT__vx_priority_encoder__DOT__i + = vlTOPp->__Vtable3_cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__vx_priority_encoder_sm__DOT__genblk2__BRA__2__KET____DOT__vx_priority_encoder__DOT__i + [vlTOPp->__Vtableidx3]; + vlTOPp->__Vtableidx4 = (0xfU & ((IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__vx_priority_encoder_sm__DOT____Vcellout__vx_bank_valid__bank_valids) + >> 0xcU)); + vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__vx_priority_encoder_sm__DOT____Vcellout__genblk2__BRA__3__KET____DOT__vx_priority_encoder__index + = vlTOPp->__Vtable4_cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__vx_priority_encoder_sm__DOT____Vcellout__genblk2__BRA__3__KET____DOT__vx_priority_encoder__index + [vlTOPp->__Vtableidx4]; + vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__vx_priority_encoder_sm__DOT____Vcellout__genblk2__BRA__3__KET____DOT__vx_priority_encoder__found + = vlTOPp->__Vtable4_cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__vx_priority_encoder_sm__DOT____Vcellout__genblk2__BRA__3__KET____DOT__vx_priority_encoder__found + [vlTOPp->__Vtableidx4]; + vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__vx_priority_encoder_sm__DOT__genblk2__BRA__3__KET____DOT__vx_priority_encoder__DOT__i + = vlTOPp->__Vtable4_cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__vx_priority_encoder_sm__DOT__genblk2__BRA__3__KET____DOT__vx_priority_encoder__DOT__i + [vlTOPp->__Vtableidx4]; + vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT__valid_per_bank + = ((0xeU & (IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT__valid_per_bank)) + | (IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT____Vcellout__genblk1__BRA__0__KET____DOT__choose_thread__found)); + vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT__use_mask_per_bank + = ((0xfff0U & (IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT__use_mask_per_bank)) + | ((IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT____Vcellout__genblk1__BRA__0__KET____DOT__choose_thread__found) + ? (0xfU & ((IData)(1U) << (IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT____Vcellout__genblk1__BRA__0__KET____DOT__choose_thread__index))) + : 0U)); + vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT__index_per_bank + = ((0xfcU & (IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT__index_per_bank)) + | (IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT____Vcellout__genblk1__BRA__0__KET____DOT__choose_thread__index)); + vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT__valid_per_bank + = ((0xdU & (IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT__valid_per_bank)) + | ((IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT____Vcellout__genblk1__BRA__1__KET____DOT__choose_thread__found) + << 1U)); + vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT__use_mask_per_bank + = ((0xff0fU & (IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT__use_mask_per_bank)) + | (((IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT____Vcellout__genblk1__BRA__1__KET____DOT__choose_thread__found) + ? (0xfU & ((IData)(1U) << (IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT____Vcellout__genblk1__BRA__1__KET____DOT__choose_thread__index))) + : 0U) << 4U)); + vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT__index_per_bank + = ((0xf3U & (IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT__index_per_bank)) + | ((IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT____Vcellout__genblk1__BRA__1__KET____DOT__choose_thread__index) + << 2U)); + vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT__valid_per_bank + = ((0xbU & (IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT__valid_per_bank)) + | ((IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT____Vcellout__genblk1__BRA__2__KET____DOT__choose_thread__found) + << 2U)); + vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT__use_mask_per_bank + = ((0xf0ffU & (IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT__use_mask_per_bank)) + | (((IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT____Vcellout__genblk1__BRA__2__KET____DOT__choose_thread__found) + ? (0xfU & ((IData)(1U) << (IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT____Vcellout__genblk1__BRA__2__KET____DOT__choose_thread__index))) + : 0U) << 8U)); + vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT__index_per_bank + = ((0xcfU & (IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT__index_per_bank)) + | ((IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT____Vcellout__genblk1__BRA__2__KET____DOT__choose_thread__index) + << 4U)); + vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT__valid_per_bank + = ((7U & (IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT__valid_per_bank)) + | ((IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT____Vcellout__genblk1__BRA__3__KET____DOT__choose_thread__found) + << 3U)); + vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT__use_mask_per_bank + = ((0xfffU & (IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT__use_mask_per_bank)) + | (((IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT____Vcellout__genblk1__BRA__3__KET____DOT__choose_thread__found) + ? (0xfU & ((IData)(1U) << (IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT____Vcellout__genblk1__BRA__3__KET____DOT__choose_thread__index))) + : 0U) << 0xcU)); + vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT__index_per_bank + = ((0x3fU & (IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT__index_per_bank)) + | ((IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT____Vcellout__genblk1__BRA__3__KET____DOT__choose_thread__index) + << 6U)); + vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__data_write[0U] + = ((IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__write_from_mem) + ? vlSymsp->TOP__cache_simX__DOT__VX_dram_req_rsp_icache.i_m_readdata[0U] + : 0U); + vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__data_write[1U] + = ((IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__write_from_mem) + ? vlSymsp->TOP__cache_simX__DOT__VX_dram_req_rsp_icache.i_m_readdata[1U] + : 0U); + vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__data_write[2U] + = ((IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__write_from_mem) + ? vlSymsp->TOP__cache_simX__DOT__VX_dram_req_rsp_icache.i_m_readdata[2U] + : 0U); + vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__data_write[3U] + = ((IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__write_from_mem) + ? vlSymsp->TOP__cache_simX__DOT__VX_dram_req_rsp_icache.i_m_readdata[3U] + : 0U); + vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__we + = ((0xfff0U & (IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__we)) + | ((IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__write_from_mem) + ? 0xfU : 0U)); + vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__we + = ((0xff0fU & (IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__we)) + | (((IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__write_from_mem) + ? 0xfU : 0U) << 4U)); + vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__we + = ((0xf0ffU & (IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__we)) + | (((IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__write_from_mem) + ? 0xfU : 0U) << 8U)); + vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__we + = ((0xfffU & (IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__we)) + | (((IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__write_from_mem) + ? 0xfU : 0U) << 0xcU)); + vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__data_structures__DOT__dirty_use_per_way + = ((2U & (IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__data_structures__DOT__dirty_use_per_way)) + | (IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__data_structures__DOT____Vcellout__each_way__BRA__0__KET____DOT__data_structures__dirty_use)); + vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__data_structures__DOT__dirty_use_per_way + = ((1U & (IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__data_structures__DOT__dirty_use_per_way)) + | ((IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__data_structures__DOT____Vcellout__each_way__BRA__1__KET____DOT__data_structures__dirty_use) + << 1U)); + vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__data_structures__DOT__invalid_found = 0U; + if ((1U & (~ ((IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__data_structures__DOT__valid_use_per_way) + >> 1U)))) { + vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__data_structures__DOT__invalid_found = 1U; + } + if ((1U & (~ (IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__data_structures__DOT__valid_use_per_way)))) { + vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__data_structures__DOT__invalid_found = 1U; + } + vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__data_structures__DOT__invalid_index = 0U; + if ((1U & (~ ((IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__data_structures__DOT__valid_use_per_way) + >> 1U)))) { + vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__data_structures__DOT__invalid_index = 1U; + } + if ((1U & (~ (IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__data_structures__DOT__valid_use_per_way)))) { + vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__data_structures__DOT__invalid_index = 0U; + } + vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__data_structures__DOT__hit_per_way + = ((2U & (IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__data_structures__DOT__hit_per_way)) + | (((IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__data_structures__DOT__valid_use_per_way) + & ((0x7fffffU & (IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__data_structures__DOT__tag_use_per_way)) + == (0x7fffffU & (vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_addr + >> 9U)))) ? 1U : 0U)); + vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__data_structures__DOT__hit_per_way + = ((1U & (IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__data_structures__DOT__hit_per_way)) + | (((((IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__data_structures__DOT__valid_use_per_way) + >> 1U) & ((0x7fffffU & (IData)((vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__data_structures__DOT__tag_use_per_way + >> 0x17U))) + == (0x7fffffU & (vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_addr + >> 9U)))) + ? 1U : 0U) << 1U)); + vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__vx_priority_encoder_sm__DOT__more_than_one_valid + = ((0xeU & (IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__vx_priority_encoder_sm__DOT__more_than_one_valid)) + | (1U < (IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__vx_priority_encoder_sm__DOT__genblk1__BRA__0__KET____DOT__num_valids))); + vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__vx_priority_encoder_sm__DOT__more_than_one_valid + = ((0xdU & (IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__vx_priority_encoder_sm__DOT__more_than_one_valid)) + | ((1U < (IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__vx_priority_encoder_sm__DOT__genblk1__BRA__1__KET____DOT__num_valids)) + << 1U)); + vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__vx_priority_encoder_sm__DOT__more_than_one_valid + = ((0xbU & (IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__vx_priority_encoder_sm__DOT__more_than_one_valid)) + | ((1U < (IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__vx_priority_encoder_sm__DOT__genblk1__BRA__2__KET____DOT__num_valids)) + << 2U)); + vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__vx_priority_encoder_sm__DOT__more_than_one_valid + = ((7U & (IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__vx_priority_encoder_sm__DOT__more_than_one_valid)) + | ((1U < (IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__vx_priority_encoder_sm__DOT__genblk1__BRA__3__KET____DOT__num_valids)) + << 3U)); + vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__vx_priority_encoder_sm__DOT__internal_req_num + = ((0xfcU & (IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__vx_priority_encoder_sm__DOT__internal_req_num)) + | (IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__vx_priority_encoder_sm__DOT____Vcellout__genblk2__BRA__0__KET____DOT__vx_priority_encoder__index)); + vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__vx_priority_encoder_sm__DOT__internal_out_valid + = ((0xeU & (IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__vx_priority_encoder_sm__DOT__internal_out_valid)) + | (IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__vx_priority_encoder_sm__DOT____Vcellout__genblk2__BRA__0__KET____DOT__vx_priority_encoder__found)); + vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__vx_priority_encoder_sm__DOT__internal_req_num + = ((0xf3U & (IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__vx_priority_encoder_sm__DOT__internal_req_num)) + | ((IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__vx_priority_encoder_sm__DOT____Vcellout__genblk2__BRA__1__KET____DOT__vx_priority_encoder__index) + << 2U)); + vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__vx_priority_encoder_sm__DOT__internal_out_valid + = ((0xdU & (IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__vx_priority_encoder_sm__DOT__internal_out_valid)) + | ((IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__vx_priority_encoder_sm__DOT____Vcellout__genblk2__BRA__1__KET____DOT__vx_priority_encoder__found) + << 1U)); + vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__vx_priority_encoder_sm__DOT__internal_req_num + = ((0xcfU & (IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__vx_priority_encoder_sm__DOT__internal_req_num)) + | ((IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__vx_priority_encoder_sm__DOT____Vcellout__genblk2__BRA__2__KET____DOT__vx_priority_encoder__index) + << 4U)); + vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__vx_priority_encoder_sm__DOT__internal_out_valid + = ((0xbU & (IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__vx_priority_encoder_sm__DOT__internal_out_valid)) + | ((IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__vx_priority_encoder_sm__DOT____Vcellout__genblk2__BRA__2__KET____DOT__vx_priority_encoder__found) + << 2U)); + vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__vx_priority_encoder_sm__DOT__internal_req_num + = ((0x3fU & (IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__vx_priority_encoder_sm__DOT__internal_req_num)) + | ((IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__vx_priority_encoder_sm__DOT____Vcellout__genblk2__BRA__3__KET____DOT__vx_priority_encoder__index) + << 6U)); + vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__vx_priority_encoder_sm__DOT__internal_out_valid + = ((7U & (IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__vx_priority_encoder_sm__DOT__internal_out_valid)) + | ((IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__vx_priority_encoder_sm__DOT____Vcellout__genblk2__BRA__3__KET____DOT__vx_priority_encoder__found) + << 3U)); + vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__0__KET____DOT__use_valid_in + = (((2U == (IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT__state)) + & (IData)(vlTOPp->cache_simX__DOT__dcache_i_m_ready)) + | ((~ ((2U == (IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT__state)) + & (~ (IData)(vlTOPp->cache_simX__DOT__dcache_i_m_ready)))) + & ((1U != (IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT__state)) + & (IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT__valid_per_bank)))); + vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__1__KET____DOT__use_valid_in + = (((2U == (IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT__state)) + & (IData)(vlTOPp->cache_simX__DOT__dcache_i_m_ready)) + | ((~ ((2U == (IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT__state)) + & (~ (IData)(vlTOPp->cache_simX__DOT__dcache_i_m_ready)))) + & ((1U != (IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT__state)) + & ((IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT__valid_per_bank) + >> 1U)))); + vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__2__KET____DOT__use_valid_in + = (((2U == (IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT__state)) + & (IData)(vlTOPp->cache_simX__DOT__dcache_i_m_ready)) + | ((~ ((2U == (IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT__state)) + & (~ (IData)(vlTOPp->cache_simX__DOT__dcache_i_m_ready)))) + & ((1U != (IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT__state)) + & ((IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT__valid_per_bank) + >> 2U)))); + vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__3__KET____DOT__use_valid_in + = (((2U == (IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT__state)) + & (IData)(vlTOPp->cache_simX__DOT__dcache_i_m_ready)) + | ((~ ((2U == (IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT__state)) + & (~ (IData)(vlTOPp->cache_simX__DOT__dcache_i_m_ready)))) + & ((1U != (IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT__state)) + & ((IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT__valid_per_bank) + >> 3U)))); + vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__0__KET____DOT__bank_addr + = ((1U == (IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT__state)) + ? vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT__miss_addr + : ((2U == (IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT__state)) + ? vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT__miss_addr + : vlSymsp->TOP__cache_simX__DOT__VX_dcache_req.out_cache_driver_in_address[ + (3U & (IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT__index_per_bank))])); + vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__1__KET____DOT__bank_addr + = ((1U == (IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT__state)) + ? vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT__miss_addr + : ((2U == (IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT__state)) + ? vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT__miss_addr + : vlSymsp->TOP__cache_simX__DOT__VX_dcache_req.out_cache_driver_in_address[ + (3U & ((IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT__index_per_bank) + >> 2U))])); + vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__2__KET____DOT__bank_addr + = ((1U == (IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT__state)) + ? vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT__miss_addr + : ((2U == (IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT__state)) + ? vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT__miss_addr + : vlSymsp->TOP__cache_simX__DOT__VX_dcache_req.out_cache_driver_in_address[ + (3U & ((IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT__index_per_bank) + >> 4U))])); + vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__3__KET____DOT__bank_addr + = ((1U == (IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT__state)) + ? vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT__miss_addr + : ((2U == (IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT__state)) + ? vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT__miss_addr + : vlSymsp->TOP__cache_simX__DOT__VX_dcache_req.out_cache_driver_in_address[ + (3U & ((IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT__index_per_bank) + >> 6U))])); + vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__data_structures__DOT__data_write_per_way[0U] + = vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__data_write[0U]; + vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__data_structures__DOT__data_write_per_way[1U] + = vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__data_write[1U]; + vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__data_structures__DOT__data_write_per_way[2U] + = vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__data_write[2U]; + vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__data_structures__DOT__data_write_per_way[3U] + = vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__data_write[3U]; + vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__data_structures__DOT__data_write_per_way[4U] + = vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__data_write[0U]; + vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__data_structures__DOT__data_write_per_way[5U] + = vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__data_write[1U]; + vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__data_structures__DOT__data_write_per_way[6U] + = vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__data_write[2U]; + vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__data_structures__DOT__data_write_per_way[7U] + = vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__data_write[3U]; + vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__data_structures__DOT__genblk1__DOT__way_indexing__DOT__found = 0U; + if ((2U & (IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__data_structures__DOT__hit_per_way))) { + vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__data_structures__DOT__genblk1__DOT__way_indexing__DOT__found = 1U; + } + if ((1U & (IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__data_structures__DOT__hit_per_way))) { + vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__data_structures__DOT__genblk1__DOT__way_indexing__DOT__found = 1U; + } + vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__data_structures__DOT__way_index = 0U; + if ((2U & (IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__data_structures__DOT__hit_per_way))) { + vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__data_structures__DOT__way_index = 1U; + } + if ((1U & (IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__data_structures__DOT__hit_per_way))) { + vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__data_structures__DOT__way_index = 0U; + } + vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__vx_priority_encoder_sm__DOT__serviced = 0U; + vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__vx_priority_encoder_sm__DOT__serviced + = ((IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__vx_priority_encoder_sm__DOT__serviced) + | ((IData)(1U) << (3U & (IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__vx_priority_encoder_sm__DOT__internal_req_num)))); + vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__vx_priority_encoder_sm__DOT__serviced + = ((IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__vx_priority_encoder_sm__DOT__serviced) + | ((IData)(1U) << (3U & ((IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__vx_priority_encoder_sm__DOT__internal_req_num) + >> 2U)))); + vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__vx_priority_encoder_sm__DOT__serviced + = ((IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__vx_priority_encoder_sm__DOT__serviced) + | ((IData)(1U) << (3U & ((IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__vx_priority_encoder_sm__DOT__internal_req_num) + >> 4U)))); + vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__vx_priority_encoder_sm__DOT__serviced + = ((IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__vx_priority_encoder_sm__DOT__serviced) + | ((IData)(1U) << (3U & ((IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__vx_priority_encoder_sm__DOT__internal_req_num) + >> 6U)))); + __Vtemp132[0U] = 0U; + __Vtemp132[1U] = 0U; + __Vtemp132[2U] = 0U; + __Vtemp132[3U] = 0U; + vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT____Vcellout__vx_priority_encoder_sm__out_data[0U] + = ((1U & (IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__vx_priority_encoder_sm__DOT__internal_out_valid)) + ? __Vtemp132[(3U & (IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__vx_priority_encoder_sm__DOT__internal_req_num))] + : 0U); + __Vtemp133[0U] = 0U; + __Vtemp133[1U] = 0U; + __Vtemp133[2U] = 0U; + __Vtemp133[3U] = 0U; + vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT____Vcellout__vx_priority_encoder_sm__out_data[1U] + = ((2U & (IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__vx_priority_encoder_sm__DOT__internal_out_valid)) + ? __Vtemp133[(3U & ((IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__vx_priority_encoder_sm__DOT__internal_req_num) + >> 2U))] : 0U); + __Vtemp134[0U] = 0U; + __Vtemp134[1U] = 0U; + __Vtemp134[2U] = 0U; + __Vtemp134[3U] = 0U; + vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT____Vcellout__vx_priority_encoder_sm__out_data[2U] + = ((4U & (IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__vx_priority_encoder_sm__DOT__internal_out_valid)) + ? __Vtemp134[(3U & ((IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__vx_priority_encoder_sm__DOT__internal_req_num) + >> 4U))] : 0U); + __Vtemp135[0U] = 0U; + __Vtemp135[1U] = 0U; + __Vtemp135[2U] = 0U; + __Vtemp135[3U] = 0U; + vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT____Vcellout__vx_priority_encoder_sm__out_data[3U] + = ((8U & (IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__vx_priority_encoder_sm__DOT__internal_out_valid)) + ? __Vtemp135[(3U & ((IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__vx_priority_encoder_sm__DOT__internal_req_num) + >> 6U))] : 0U); + vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__genblk2__BRA__0__KET____DOT__shm_write + = ((7U != (IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__sm_driver_in_mem_write)) + & (IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__vx_priority_encoder_sm__DOT__internal_out_valid)); + vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__genblk2__BRA__1__KET____DOT__shm_write + = ((7U != (IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__sm_driver_in_mem_write)) + & ((IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__vx_priority_encoder_sm__DOT__internal_out_valid) + >> 1U)); + vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__genblk2__BRA__2__KET____DOT__shm_write + = ((7U != (IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__sm_driver_in_mem_write)) + & ((IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__vx_priority_encoder_sm__DOT__internal_out_valid) + >> 2U)); + vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__genblk2__BRA__3__KET____DOT__shm_write + = ((7U != (IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__sm_driver_in_mem_write)) + & ((IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__vx_priority_encoder_sm__DOT__internal_out_valid) + >> 3U)); + vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT____Vcellout__vx_priority_encoder_sm__out_address[0U] + = ((1U & (IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__vx_priority_encoder_sm__DOT__internal_out_valid)) + ? vlSymsp->TOP__cache_simX__DOT__VX_dcache_req.out_cache_driver_in_address[ + (3U & (IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__vx_priority_encoder_sm__DOT__internal_req_num))] + : 0U); + vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT____Vcellout__vx_priority_encoder_sm__out_address[1U] + = ((2U & (IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__vx_priority_encoder_sm__DOT__internal_out_valid)) + ? vlSymsp->TOP__cache_simX__DOT__VX_dcache_req.out_cache_driver_in_address[ + (3U & ((IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__vx_priority_encoder_sm__DOT__internal_req_num) + >> 2U))] : 0U); + vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT____Vcellout__vx_priority_encoder_sm__out_address[2U] + = ((4U & (IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__vx_priority_encoder_sm__DOT__internal_out_valid)) + ? vlSymsp->TOP__cache_simX__DOT__VX_dcache_req.out_cache_driver_in_address[ + (3U & ((IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__vx_priority_encoder_sm__DOT__internal_req_num) + >> 4U))] : 0U); + vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT____Vcellout__vx_priority_encoder_sm__out_address[3U] + = ((8U & (IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__vx_priority_encoder_sm__DOT__internal_out_valid)) + ? vlSymsp->TOP__cache_simX__DOT__VX_dcache_req.out_cache_driver_in_address[ + (3U & ((IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__vx_priority_encoder_sm__DOT__internal_req_num) + >> 6U))] : 0U); + vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__data_structures__DOT__way_use_Qual + = ((0U != (IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__state)) + ? (IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__way_to_update) + : (IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__data_structures__DOT__way_index)); + vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__vx_priority_encoder_sm__DOT__serviced_qual + = ((IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__orig_in_valid) + & (IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__vx_priority_encoder_sm__DOT__serviced)); + vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__block_we = 0U; + if ((1U & (IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__vx_priority_encoder_sm__DOT__internal_out_valid))) { + if ((0xffU == (0xffU & ((vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT____Vcellout__vx_priority_encoder_sm__out_address[1U] + << 8U) | (vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT____Vcellout__vx_priority_encoder_sm__out_address[0U] + >> 0x18U))))) { + if ((7U != (IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__sm_driver_in_mem_write))) { + if ((0U != (IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__sm_driver_in_mem_write))) { + if ((1U != (IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__sm_driver_in_mem_write))) { + if ((2U == (IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__sm_driver_in_mem_write))) { + vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__block_we + = ((0xfcU & (IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__block_we)) + | (3U & ((vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT____Vcellout__vx_priority_encoder_sm__out_address[1U] + << 0x1cU) + | (vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT____Vcellout__vx_priority_encoder_sm__out_address[0U] + >> 4U)))); + } + } + } + } + } + } + if ((2U & (IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__vx_priority_encoder_sm__DOT__internal_out_valid))) { + if ((0xffU == (0xffU & ((vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT____Vcellout__vx_priority_encoder_sm__out_address[2U] + << 8U) | (vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT____Vcellout__vx_priority_encoder_sm__out_address[1U] + >> 0x18U))))) { + if ((7U != (IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__sm_driver_in_mem_write))) { + if ((0U != (IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__sm_driver_in_mem_write))) { + if ((1U != (IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__sm_driver_in_mem_write))) { + if ((2U == (IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__sm_driver_in_mem_write))) { + vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__block_we + = ((0xf3U & (IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__block_we)) + | (0xcU & ((vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT____Vcellout__vx_priority_encoder_sm__out_address[2U] + << 0x1eU) + | (0x3ffffffcU + & (vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT____Vcellout__vx_priority_encoder_sm__out_address[1U] + >> 2U))))); + } + } + } + } + } + } + if ((4U & (IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__vx_priority_encoder_sm__DOT__internal_out_valid))) { + if ((0xffU == (0xffU & ((vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT____Vcellout__vx_priority_encoder_sm__out_address[3U] + << 8U) | (vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT____Vcellout__vx_priority_encoder_sm__out_address[2U] + >> 0x18U))))) { + if ((7U != (IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__sm_driver_in_mem_write))) { + if ((0U != (IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__sm_driver_in_mem_write))) { + if ((1U != (IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__sm_driver_in_mem_write))) { + if ((2U == (IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__sm_driver_in_mem_write))) { + vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__block_we + = ((0xcfU & (IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__block_we)) + | (0x30U & vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT____Vcellout__vx_priority_encoder_sm__out_address[2U])); + } + } + } + } + } + } + if ((8U & (IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__vx_priority_encoder_sm__DOT__internal_out_valid))) { + if ((0xffU == (0xffU & (vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT____Vcellout__vx_priority_encoder_sm__out_address[3U] + >> 0x18U)))) { + if ((7U != (IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__sm_driver_in_mem_write))) { + if ((0U != (IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__sm_driver_in_mem_write))) { + if ((1U != (IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__sm_driver_in_mem_write))) { + if ((2U == (IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__sm_driver_in_mem_write))) { + vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__block_we + = ((0x3fU & (IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__block_we)) + | (0xc0U & (vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT____Vcellout__vx_priority_encoder_sm__out_address[3U] + << 2U))); + } + } + } + } + } + } + vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__block_wdata[0U] = 0U; + vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__block_wdata[1U] = 0U; + vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__block_wdata[2U] = 0U; + vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__block_wdata[3U] = 0U; + vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__block_wdata[4U] = 0U; + vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__block_wdata[5U] = 0U; + vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__block_wdata[6U] = 0U; + vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__block_wdata[7U] = 0U; + vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__block_wdata[8U] = 0U; + vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__block_wdata[9U] = 0U; + vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__block_wdata[0xaU] = 0U; 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+ } + } + } + } + } + } + if ((8U & (IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__vx_priority_encoder_sm__DOT__internal_out_valid))) { + if ((0xffU == (0xffU & (vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT____Vcellout__vx_priority_encoder_sm__out_address[3U] + >> 0x18U)))) { + if ((7U != (IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__sm_driver_in_mem_write))) { + if ((0U != (IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__sm_driver_in_mem_write))) { + if ((1U != (IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__sm_driver_in_mem_write))) { + if ((2U == (IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__sm_driver_in_mem_write))) { + VL_ASSIGNSEL_WIII(32,(0x1ffU + & ((IData)(0x180U) + + + (0x60U + & (vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT____Vcellout__vx_priority_encoder_sm__out_address[3U] + << 1U)))), vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__block_wdata, + vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT____Vcellout__vx_priority_encoder_sm__out_data[3U]); + } + } + } + } + } + } + if ((1U & (IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__vx_priority_encoder_sm__DOT__internal_out_valid))) { + if ((0xffU == (0xffU & ((vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT____Vcellout__vx_priority_encoder_sm__out_address[1U] + << 8U) | (vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT____Vcellout__vx_priority_encoder_sm__out_address[0U] + >> 0x18U))))) { + if ((7U == (IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__sm_driver_in_mem_write))) { + if ((7U != (IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__sm_driver_in_mem_read))) { + if ((0U != (IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__sm_driver_in_mem_read))) { + if ((1U != (IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__sm_driver_in_mem_read))) { + if ((2U == (IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__sm_driver_in_mem_read))) { + vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__temp_out_valid + = ((IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__temp_out_valid) + | ((IData)(1U) + << (3U & (IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__vx_priority_encoder_sm__DOT__internal_req_num)))); + } + } + } + } + } + } + } + if ((2U & (IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__vx_priority_encoder_sm__DOT__internal_out_valid))) { + if ((0xffU == (0xffU & ((vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT____Vcellout__vx_priority_encoder_sm__out_address[2U] + << 8U) | (vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT____Vcellout__vx_priority_encoder_sm__out_address[1U] + >> 0x18U))))) { + if ((7U == (IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__sm_driver_in_mem_write))) { + if ((7U != (IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__sm_driver_in_mem_read))) { + if ((0U != (IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__sm_driver_in_mem_read))) { + if ((1U != (IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__sm_driver_in_mem_read))) { + if ((2U == (IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__sm_driver_in_mem_read))) { + vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__temp_out_valid + = ((IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__temp_out_valid) + | ((IData)(1U) + << (3U & + ((IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__vx_priority_encoder_sm__DOT__internal_req_num) + >> 3U)))); + } + } + } + } + } + } + } + if ((4U & (IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__vx_priority_encoder_sm__DOT__internal_out_valid))) { + if ((0xffU == (0xffU & ((vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT____Vcellout__vx_priority_encoder_sm__out_address[3U] + << 8U) | (vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT____Vcellout__vx_priority_encoder_sm__out_address[2U] + >> 0x18U))))) { + if ((7U == (IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__sm_driver_in_mem_write))) { + if ((7U != (IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__sm_driver_in_mem_read))) { + if ((0U != (IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__sm_driver_in_mem_read))) { + if ((1U != (IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__sm_driver_in_mem_read))) { + if ((2U == (IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__sm_driver_in_mem_read))) { + vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__temp_out_valid + = ((IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__temp_out_valid) + | ((IData)(1U) + << (3U & + ((IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__vx_priority_encoder_sm__DOT__internal_req_num) + >> 6U)))); + } + } + } + } + } + } + } + if ((8U & (IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__vx_priority_encoder_sm__DOT__internal_out_valid))) { + if ((0xffU == (0xffU & (vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT____Vcellout__vx_priority_encoder_sm__out_address[3U] + >> 0x18U)))) { + if ((7U == (IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__sm_driver_in_mem_write))) { + if ((7U != (IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__sm_driver_in_mem_read))) { + if ((0U != (IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__sm_driver_in_mem_read))) { + if ((1U != (IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__sm_driver_in_mem_read))) { + if ((2U == (IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__sm_driver_in_mem_read))) { + vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__temp_out_valid + = ((IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__temp_out_valid) + | ((IData)(1U) + << (3U & + ((IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__vx_priority_encoder_sm__DOT__internal_req_num) + >> 9U)))); + } + } + } + } + } + } + } + vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__block_addr = 0U; + if ((1U & (IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__vx_priority_encoder_sm__DOT__internal_out_valid))) { + if ((0xffU == (0xffU & ((vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT____Vcellout__vx_priority_encoder_sm__out_address[1U] + << 8U) | (vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT____Vcellout__vx_priority_encoder_sm__out_address[0U] + >> 0x18U))))) { + if ((7U != (IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__sm_driver_in_mem_write))) { + if ((0U != (IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__sm_driver_in_mem_write))) { + if ((1U != (IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__sm_driver_in_mem_write))) { + if ((2U == (IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__sm_driver_in_mem_write))) { + vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT____Vlvbound1 + = (0x7fU & ((vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT____Vcellout__vx_priority_encoder_sm__out_address[1U] + << 0x1aU) + | (vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT____Vcellout__vx_priority_encoder_sm__out_address[0U] + >> 6U))); + vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__block_addr + = ((0xfffff80U & vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__block_addr) + | (IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT____Vlvbound1)); + } + } + } + } else { + if ((7U != (IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__sm_driver_in_mem_read))) { + if ((0U != (IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__sm_driver_in_mem_read))) { + if ((1U != (IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__sm_driver_in_mem_read))) { + if ((2U == (IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__sm_driver_in_mem_read))) { + vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT____Vlvbound2 + = (0x7fU & ((vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT____Vcellout__vx_priority_encoder_sm__out_address[1U] + << 0x1aU) + | (vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT____Vcellout__vx_priority_encoder_sm__out_address[0U] + >> 6U))); + vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__block_addr + = ((0xfffff80U + & vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__block_addr) + | (IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT____Vlvbound2)); + } + } + } + } + } + } + } + if ((2U & (IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__vx_priority_encoder_sm__DOT__internal_out_valid))) { + if ((0xffU == (0xffU & ((vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT____Vcellout__vx_priority_encoder_sm__out_address[2U] + << 8U) | (vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT____Vcellout__vx_priority_encoder_sm__out_address[1U] + >> 0x18U))))) { + if ((7U != (IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__sm_driver_in_mem_write))) { + if ((0U != (IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__sm_driver_in_mem_write))) { + if ((1U != (IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__sm_driver_in_mem_write))) { + if ((2U == (IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__sm_driver_in_mem_write))) { + vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT____Vlvbound1 + = (0x7fU & ((vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT____Vcellout__vx_priority_encoder_sm__out_address[2U] + << 0x1aU) + | (vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT____Vcellout__vx_priority_encoder_sm__out_address[1U] + >> 6U))); + vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__block_addr + = ((0xfffc07fU & vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__block_addr) + | ((IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT____Vlvbound1) + << 7U)); + } + } + } + } else { + if ((7U != (IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__sm_driver_in_mem_read))) { + if ((0U != (IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__sm_driver_in_mem_read))) { + if ((1U != (IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__sm_driver_in_mem_read))) { + if ((2U == (IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__sm_driver_in_mem_read))) { + vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT____Vlvbound2 + = (0x7fU & ((vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT____Vcellout__vx_priority_encoder_sm__out_address[2U] + << 0x1aU) + | (vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT____Vcellout__vx_priority_encoder_sm__out_address[1U] + >> 6U))); + vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__block_addr + = ((0xfffc07fU + & vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__block_addr) + | ((IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT____Vlvbound2) + << 7U)); + } + } + } + } + } + } + } + if ((4U & (IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__vx_priority_encoder_sm__DOT__internal_out_valid))) { + if ((0xffU == (0xffU & ((vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT____Vcellout__vx_priority_encoder_sm__out_address[3U] + << 8U) | (vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT____Vcellout__vx_priority_encoder_sm__out_address[2U] + >> 0x18U))))) { + if ((7U != (IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__sm_driver_in_mem_write))) { + if ((0U != (IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__sm_driver_in_mem_write))) { + if ((1U != (IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__sm_driver_in_mem_write))) { + if ((2U == (IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__sm_driver_in_mem_write))) { + vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT____Vlvbound1 + = (0x7fU & ((vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT____Vcellout__vx_priority_encoder_sm__out_address[3U] + << 0x1aU) + | (vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT____Vcellout__vx_priority_encoder_sm__out_address[2U] + >> 6U))); + vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__block_addr + = ((0xfe03fffU & vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__block_addr) + | ((IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT____Vlvbound1) + << 0xeU)); + } + } + } + } else { + if ((7U != (IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__sm_driver_in_mem_read))) { + if ((0U != (IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__sm_driver_in_mem_read))) { + if ((1U != (IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__sm_driver_in_mem_read))) { + if ((2U == (IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__sm_driver_in_mem_read))) { + vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT____Vlvbound2 + = (0x7fU & ((vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT____Vcellout__vx_priority_encoder_sm__out_address[3U] + << 0x1aU) + | (vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT____Vcellout__vx_priority_encoder_sm__out_address[2U] + >> 6U))); + vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__block_addr + = ((0xfe03fffU + & vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__block_addr) + | ((IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT____Vlvbound2) + << 0xeU)); + } + } + } + } + } + } + } + if ((8U & (IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__vx_priority_encoder_sm__DOT__internal_out_valid))) { + if ((0xffU == (0xffU & (vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT____Vcellout__vx_priority_encoder_sm__out_address[3U] + >> 0x18U)))) { + if ((7U != (IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__sm_driver_in_mem_write))) { + if ((0U != (IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__sm_driver_in_mem_write))) { + if ((1U != (IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__sm_driver_in_mem_write))) { + if ((2U == (IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__sm_driver_in_mem_write))) { + vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT____Vlvbound1 + = (0x7fU & (vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT____Vcellout__vx_priority_encoder_sm__out_address[3U] + >> 6U)); + vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__block_addr + = ((0x1fffffU & vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__block_addr) + | ((IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT____Vlvbound1) + << 0x15U)); + } + } + } + } else { + if ((7U != (IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__sm_driver_in_mem_read))) { + if ((0U != (IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__sm_driver_in_mem_read))) { + if ((1U != (IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__sm_driver_in_mem_read))) { + if ((2U == (IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__sm_driver_in_mem_read))) { + vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT____Vlvbound2 + = (0x7fU & (vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT____Vcellout__vx_priority_encoder_sm__out_address[3U] + >> 6U)); + vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__block_addr + = ((0x1fffffU & vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__block_addr) + | ((IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT____Vlvbound2) + << 0x15U)); + } + } + } + } + } + } + } + vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__data_structures__DOT__write_from_mem_per_way + = ((2U & (IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__data_structures__DOT__write_from_mem_per_way)) + | ((IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__write_from_mem) + & (~ (IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__data_structures__DOT__way_use_Qual)))); + vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__data_structures__DOT__we_per_way + = ((0xffff0000U & vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__data_structures__DOT__we_per_way) + | ((IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__data_structures__DOT__way_use_Qual) + ? 0U : (0xffffU & (IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__we)))); + vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__data_structures__DOT__write_from_mem_per_way + = ((1U & (IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__data_structures__DOT__write_from_mem_per_way)) + | (((IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__write_from_mem) + & (IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__data_structures__DOT__way_use_Qual)) + << 1U)); + vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__data_structures__DOT__we_per_way + = ((0xffffU & vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__data_structures__DOT__we_per_way) + | (((IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__data_structures__DOT__way_use_Qual) + ? (0xffffU & (IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__we)) + : 0U) << 0x10U)); + vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__data_unQual + = (((0U == (3U & vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_addr)) + | (2U == (IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache_driver_in_mem_read))) + ? (((0U == (0x1fU & (((IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__data_structures__DOT__way_use_Qual) + << 7U) + (0x60U & + (vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_addr + << 3U))))) + ? 0U : (vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__data_structures__DOT__data_use_per_way[ + ((IData)(1U) + (7U & ((((IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__data_structures__DOT__way_use_Qual) + << 7U) + + (0x60U + & (vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_addr + << 3U))) + >> 5U)))] + << ((IData)(0x20U) - (0x1fU + & (((IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__data_structures__DOT__way_use_Qual) + << 7U) + + + (0x60U + & (vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_addr + << 3U))))))) + | (vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__data_structures__DOT__data_use_per_way[ + (7U & ((((IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__data_structures__DOT__way_use_Qual) + << 7U) + (0x60U & (vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_addr + << 3U))) + >> 5U))] >> (0x1fU & (((IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__data_structures__DOT__way_use_Qual) + << 7U) + + (0x60U + & (vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_addr + << 3U)))))) + : ((1U == (3U & vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_addr)) + ? ((((0U == (0x1fU & (((IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__data_structures__DOT__way_use_Qual) + << 7U) + (0x60U + & (vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_addr + << 3U))))) + ? 0U : (vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__data_structures__DOT__data_use_per_way[ + ((IData)(1U) + (7U & + ((((IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__data_structures__DOT__way_use_Qual) + << 7U) + + (0x60U + & (vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_addr + << 3U))) + >> 5U)))] + << ((IData)(0x20U) - + (0x1fU & (((IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__data_structures__DOT__way_use_Qual) + << 7U) + + (0x60U + & (vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_addr + << 3U))))))) + | (vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__data_structures__DOT__data_use_per_way[ + (7U & ((((IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__data_structures__DOT__way_use_Qual) + << 7U) + (0x60U & (vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_addr + << 3U))) + >> 5U))] >> (0x1fU & + (((IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__data_structures__DOT__way_use_Qual) + << 7U) + + (0x60U + & (vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_addr + << 3U)))))) + >> 8U) : ((2U == (3U & vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_addr)) + ? ((((0U == (0x1fU & + (((IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__data_structures__DOT__way_use_Qual) + << 7U) + + (0x60U + & (vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_addr + << 3U))))) + ? 0U : (vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__data_structures__DOT__data_use_per_way[ + ((IData)(1U) + + (7U + & ((((IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__data_structures__DOT__way_use_Qual) + << 7U) + + + (0x60U + & (vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_addr + << 3U))) + >> 5U)))] + << ((IData)(0x20U) + - (0x1fU + & (((IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__data_structures__DOT__way_use_Qual) + << 7U) + + + (0x60U + & (vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_addr + << 3U))))))) + | (vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__data_structures__DOT__data_use_per_way[ + (7U & ((((IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__data_structures__DOT__way_use_Qual) + << 7U) + + (0x60U + & (vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_addr + << 3U))) + >> 5U))] + >> (0x1fU & (((IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__data_structures__DOT__way_use_Qual) + << 7U) + + + (0x60U + & (vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_addr + << 3U)))))) + >> 0x10U) : ((((0U + == + (0x1fU + & (((IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__data_structures__DOT__way_use_Qual) + << 7U) + + + (0x60U + & (vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_addr + << 3U))))) + ? 0U + : + (vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__data_structures__DOT__data_use_per_way[ + ((IData)(1U) + + + (7U + & ((((IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__data_structures__DOT__way_use_Qual) + << 7U) + + + (0x60U + & (vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_addr + << 3U))) + >> 5U)))] + << + ((IData)(0x20U) + - + (0x1fU + & (((IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__data_structures__DOT__way_use_Qual) + << 7U) + + + (0x60U + & (vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_addr + << 3U))))))) + | (vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__data_structures__DOT__data_use_per_way[ + (7U + & ((((IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__data_structures__DOT__way_use_Qual) + << 7U) + + + (0x60U + & (vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_addr + << 3U))) + >> 5U))] + >> + (0x1fU + & (((IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__data_structures__DOT__way_use_Qual) + << 7U) + + + (0x60U + & (vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_addr + << 3U)))))) + >> 0x18U)))); + vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__tag_use + = ((0x2dU >= (0x3fU & ((IData)(0x17U) * (IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__data_structures__DOT__way_use_Qual)))) + ? (0x7fffffU & (IData)((vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__data_structures__DOT__tag_use_per_way + >> (0x3fU & ((IData)(0x17U) + * (IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__data_structures__DOT__way_use_Qual)))))) + : 0U); + vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__valid_use + = (1U & ((IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__data_structures__DOT__valid_use_per_way) + >> (IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__data_structures__DOT__way_use_Qual))); + vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__vx_priority_encoder_sm__DOT__new_left_requests + = ((0U == (IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__vx_priority_encoder_sm__DOT__left_requests)) + ? ((IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__orig_in_valid) + & (~ (IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__vx_priority_encoder_sm__DOT__serviced_qual))) + : ((IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__vx_priority_encoder_sm__DOT__left_requests) + & (~ (IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__vx_priority_encoder_sm__DOT__serviced_qual)))); + vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__block_rdata[0U] + = ((IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__genblk2__BRA__0__KET____DOT__shm_write) + ? 0U : vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__genblk2__BRA__0__KET____DOT__vx_shared_memory_block__DOT__shared_memory + [(0x7fU & vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__block_addr)][0U]); + vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__block_rdata[1U] + = ((IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__genblk2__BRA__0__KET____DOT__shm_write) + ? 0U : vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__genblk2__BRA__0__KET____DOT__vx_shared_memory_block__DOT__shared_memory + [(0x7fU & vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__block_addr)][1U]); + vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__block_rdata[2U] + = ((IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__genblk2__BRA__0__KET____DOT__shm_write) + ? 0U : vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__genblk2__BRA__0__KET____DOT__vx_shared_memory_block__DOT__shared_memory + [(0x7fU & vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__block_addr)][2U]); + vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__block_rdata[3U] + = ((IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__genblk2__BRA__0__KET____DOT__shm_write) + ? 0U : vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__genblk2__BRA__0__KET____DOT__vx_shared_memory_block__DOT__shared_memory + [(0x7fU & vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__block_addr)][3U]); + vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__block_rdata[4U] + = ((IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__genblk2__BRA__1__KET____DOT__shm_write) + ? 0U : vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__genblk2__BRA__1__KET____DOT__vx_shared_memory_block__DOT__shared_memory + [(0x7fU & (vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__block_addr + >> 7U))][0U]); + vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__block_rdata[5U] + = ((IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__genblk2__BRA__1__KET____DOT__shm_write) + ? 0U : vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__genblk2__BRA__1__KET____DOT__vx_shared_memory_block__DOT__shared_memory + [(0x7fU & (vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__block_addr + >> 7U))][1U]); + vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__block_rdata[6U] + = ((IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__genblk2__BRA__1__KET____DOT__shm_write) + ? 0U : vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__genblk2__BRA__1__KET____DOT__vx_shared_memory_block__DOT__shared_memory + [(0x7fU & (vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__block_addr + >> 7U))][2U]); + vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__block_rdata[7U] + = ((IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__genblk2__BRA__1__KET____DOT__shm_write) + ? 0U : vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__genblk2__BRA__1__KET____DOT__vx_shared_memory_block__DOT__shared_memory + [(0x7fU & (vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__block_addr + >> 7U))][3U]); + vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__block_rdata[8U] + = ((IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__genblk2__BRA__2__KET____DOT__shm_write) + ? 0U : vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__genblk2__BRA__2__KET____DOT__vx_shared_memory_block__DOT__shared_memory + [(0x7fU & (vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__block_addr + >> 0xeU))][0U]); + vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__block_rdata[9U] + = ((IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__genblk2__BRA__2__KET____DOT__shm_write) + ? 0U : vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__genblk2__BRA__2__KET____DOT__vx_shared_memory_block__DOT__shared_memory + [(0x7fU & (vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__block_addr + >> 0xeU))][1U]); + vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__block_rdata[0xaU] + = ((IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__genblk2__BRA__2__KET____DOT__shm_write) + ? 0U : vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__genblk2__BRA__2__KET____DOT__vx_shared_memory_block__DOT__shared_memory + [(0x7fU & (vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__block_addr + >> 0xeU))][2U]); + vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__block_rdata[0xbU] + = ((IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__genblk2__BRA__2__KET____DOT__shm_write) + ? 0U : vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__genblk2__BRA__2__KET____DOT__vx_shared_memory_block__DOT__shared_memory + [(0x7fU & (vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__block_addr + >> 0xeU))][3U]); + vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__block_rdata[0xcU] + = ((IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__genblk2__BRA__3__KET____DOT__shm_write) + ? 0U : vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__genblk2__BRA__3__KET____DOT__vx_shared_memory_block__DOT__shared_memory + [(0x7fU & (vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__block_addr + >> 0x15U))][0U]); + vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__block_rdata[0xdU] + = ((IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__genblk2__BRA__3__KET____DOT__shm_write) + ? 0U : vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__genblk2__BRA__3__KET____DOT__vx_shared_memory_block__DOT__shared_memory + [(0x7fU & (vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__block_addr + >> 0x15U))][1U]); + vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__block_rdata[0xeU] + = ((IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__genblk2__BRA__3__KET____DOT__shm_write) + ? 0U : vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__genblk2__BRA__3__KET____DOT__vx_shared_memory_block__DOT__shared_memory + [(0x7fU & (vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__block_addr + >> 0x15U))][2U]); + vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__block_rdata[0xfU] + = ((IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__genblk2__BRA__3__KET____DOT__shm_write) + ? 0U : vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__genblk2__BRA__3__KET____DOT__vx_shared_memory_block__DOT__shared_memory + [(0x7fU & (vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__block_addr + >> 0x15U))][3U]); + vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__hit_per_bank + = (((IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__access) + & (vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__tag_use + == (0x7fffffU & (vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_addr + >> 9U)))) & (IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__valid_use)); + if ((1U & (IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__vx_priority_encoder_sm__DOT__internal_out_valid))) { + if ((0xffU == (0xffU & ((vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT____Vcellout__vx_priority_encoder_sm__out_address[1U] + << 8U) | (vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT____Vcellout__vx_priority_encoder_sm__out_address[0U] + >> 0x18U))))) { + if ((7U == (IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__sm_driver_in_mem_write))) { + if ((7U != (IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__sm_driver_in_mem_read))) { + if ((0U != (IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__sm_driver_in_mem_read))) { + if ((1U != (IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__sm_driver_in_mem_read))) { + if ((2U == (IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__sm_driver_in_mem_read))) { + VL_ASSIGNSEL_WIII(32, + (0x60U + & ((IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__vx_priority_encoder_sm__DOT__internal_req_num) + << 5U)), vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__temp_out_data, + vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__block_rdata[ + (3U + & (vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT____Vcellout__vx_priority_encoder_sm__out_address[0U] + >> 4U))]); + } + } + } + } + } + } + } + if ((2U & (IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__vx_priority_encoder_sm__DOT__internal_out_valid))) { + if ((0xffU == (0xffU & ((vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT____Vcellout__vx_priority_encoder_sm__out_address[2U] + << 8U) | (vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT____Vcellout__vx_priority_encoder_sm__out_address[1U] + >> 0x18U))))) { + if ((7U == (IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__sm_driver_in_mem_write))) { + if ((7U != (IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__sm_driver_in_mem_read))) { + if ((0U != (IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__sm_driver_in_mem_read))) { + if ((1U != (IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__sm_driver_in_mem_read))) { + if ((2U == (IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__sm_driver_in_mem_read))) { + VL_ASSIGNSEL_WIII(32, + (0x60U + & ((IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__vx_priority_encoder_sm__DOT__internal_req_num) + << 2U)), vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__temp_out_data, + (((0U + == + (0x1fU + & ((IData)(0x80U) + + + (0x60U + & (vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT____Vcellout__vx_priority_encoder_sm__out_address[1U] + << 1U))))) + ? 0U + : + (vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__block_rdata[ + ((IData)(1U) + + + (0xfU + & (((IData)(0x80U) + + + (0x60U + & (vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT____Vcellout__vx_priority_encoder_sm__out_address[1U] + << 1U))) + >> 5U)))] + << + ((IData)(0x20U) + - + (0x1fU + & ((IData)(0x80U) + + + (0x60U + & (vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT____Vcellout__vx_priority_encoder_sm__out_address[1U] + << 1U))))))) + | (vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__block_rdata[ + (0xfU + & (((IData)(0x80U) + + + (0x60U + & (vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT____Vcellout__vx_priority_encoder_sm__out_address[1U] + << 1U))) + >> 5U))] + >> + (0x1fU + & ((IData)(0x80U) + + + (0x60U + & (vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT____Vcellout__vx_priority_encoder_sm__out_address[1U] + << 1U))))))); + } + } + } + } + } + } + } + if ((4U & (IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__vx_priority_encoder_sm__DOT__internal_out_valid))) { + if ((0xffU == (0xffU & ((vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT____Vcellout__vx_priority_encoder_sm__out_address[3U] + << 8U) | (vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT____Vcellout__vx_priority_encoder_sm__out_address[2U] + >> 0x18U))))) { + if ((7U == (IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__sm_driver_in_mem_write))) { + if ((7U != (IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__sm_driver_in_mem_read))) { + if ((0U != (IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__sm_driver_in_mem_read))) { + if ((1U != (IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__sm_driver_in_mem_read))) { + if ((2U == (IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__sm_driver_in_mem_read))) { + VL_ASSIGNSEL_WIII(32, + (0x60U + & ((IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__vx_priority_encoder_sm__DOT__internal_req_num) + >> 1U)), vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__temp_out_data, + (((0U + == + (0x1fU + & ((IData)(0x100U) + + + (0x60U + & (vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT____Vcellout__vx_priority_encoder_sm__out_address[2U] + << 1U))))) + ? 0U + : + (vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__block_rdata[ + ((IData)(1U) + + + (0xfU + & (((IData)(0x100U) + + + (0x60U + & (vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT____Vcellout__vx_priority_encoder_sm__out_address[2U] + << 1U))) + >> 5U)))] + << + ((IData)(0x20U) + - + (0x1fU + & ((IData)(0x100U) + + + (0x60U + & (vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT____Vcellout__vx_priority_encoder_sm__out_address[2U] + << 1U))))))) + | (vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__block_rdata[ + (0xfU + & (((IData)(0x100U) + + + (0x60U + & (vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT____Vcellout__vx_priority_encoder_sm__out_address[2U] + << 1U))) + >> 5U))] + >> + (0x1fU + & ((IData)(0x100U) + + + (0x60U + & (vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT____Vcellout__vx_priority_encoder_sm__out_address[2U] + << 1U))))))); + } + } + } + } + } + } + } + if ((8U & (IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__vx_priority_encoder_sm__DOT__internal_out_valid))) { + if ((0xffU == (0xffU & (vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT____Vcellout__vx_priority_encoder_sm__out_address[3U] + >> 0x18U)))) { + if ((7U == (IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__sm_driver_in_mem_write))) { + if ((7U != (IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__sm_driver_in_mem_read))) { + if ((0U != (IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__sm_driver_in_mem_read))) { + if ((1U != (IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__sm_driver_in_mem_read))) { + if ((2U == (IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__sm_driver_in_mem_read))) { + VL_ASSIGNSEL_WIII(32, + (0x60U + & ((IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__vx_priority_encoder_sm__DOT__internal_req_num) + >> 4U)), vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__temp_out_data, + (((0U + == + (0x1fU + & ((IData)(0x180U) + + + (0x60U + & (vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT____Vcellout__vx_priority_encoder_sm__out_address[3U] + << 1U))))) + ? 0U + : + (vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__block_rdata[ + ((IData)(1U) + + + (0xfU + & (((IData)(0x180U) + + + (0x60U + & (vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT____Vcellout__vx_priority_encoder_sm__out_address[3U] + << 1U))) + >> 5U)))] + << + ((IData)(0x20U) + - + (0x1fU + & ((IData)(0x180U) + + + (0x60U + & (vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT____Vcellout__vx_priority_encoder_sm__out_address[3U] + << 1U))))))) + | (vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__block_rdata[ + (0xfU + & (((IData)(0x180U) + + + (0x60U + & (vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT____Vcellout__vx_priority_encoder_sm__out_address[3U] + << 1U))) + >> 5U))] + >> + (0x1fU + & ((IData)(0x180U) + + + (0x60U + & (vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT____Vcellout__vx_priority_encoder_sm__out_address[3U] + << 1U))))))); + } + } + } + } + } + } + } + vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__new_final_data_read = 0U; + if (vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__hit_per_bank) { + vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__new_final_data_read + = (((~ ((IData)(0xffffffffU) << (0x1fU + & ((IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT____Vcellout__genblk1__BRA__0__KET____DOT__choose_thread__index) + << 5U)))) + & vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__new_final_data_read) + | (((IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__access) + ? ((0U == (IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache_driver_in_mem_read)) + ? ((0x80U & vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__data_unQual) + ? (0xffffff00U | vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__data_unQual) + : (0xffU & vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__data_unQual)) + : ((1U == (IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache_driver_in_mem_read)) + ? ((0x8000U & vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__data_unQual) + ? (0xffff0000U | vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__data_unQual) + : (0xffffU & vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__data_unQual)) + : ((5U == (IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache_driver_in_mem_read)) + ? (0xffffU & vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__data_unQual) + : ((4U == (IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache_driver_in_mem_read)) + ? (0xffU & vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__data_unQual) + : vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__data_unQual)))) + : 0U) << (0x1fU & ((IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT____Vcellout__genblk1__BRA__0__KET____DOT__choose_thread__index) + << 5U)))); + } + vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__detect_bank_miss + = ((IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__valid_per_bank) + & (~ (IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__hit_per_bank))); + vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__debug_hit_per_bank_mask[0U] + = vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__hit_per_bank; + vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__miss_found = 0U; + if (vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__detect_bank_miss) { + vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__miss_found = 1U; + } + vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__miss_bank_index = 0U; + if (vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__detect_bank_miss) { + vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__miss_bank_index = 0U; + } + vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__new_state + = (((0U == (IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__state)) + & (IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__detect_bank_miss)) + ? 1U : ((1U == (IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__state)) + ? 2U : (((2U == (IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__state)) + & (~ (IData)(vlTOPp->cache_simX__DOT__icache_i_m_ready))) + ? 2U : 0U))); + vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__threads_serviced_per_bank + = (((IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__valid_per_bank) + ? ((IData)(1U) << (IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT____Vcellout__genblk1__BRA__0__KET____DOT__choose_thread__index)) + : 0U) & vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__debug_hit_per_bank_mask + [0U]); + vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__new_final_data_read_Qual + = ((IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__threads_serviced_per_bank) + ? vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__new_final_data_read + : vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__final_data_read); + vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__new_stored_valid + = ((IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__use_valid) + & (~ (IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__threads_serviced_per_bank))); + vlTOPp->out_icache_stall = ((IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__new_stored_valid) + | (0U != (IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__state))); +} + +void Vcache_simX::_eval(Vcache_simX__Syms* __restrict vlSymsp) { + VL_DEBUG_IF(VL_DBG_MSGF("+ Vcache_simX::_eval\n"); ); + Vcache_simX* __restrict vlTOPp VL_ATTR_UNUSED = vlSymsp->TOPp; + // Body + vlTOPp->_combo__TOP__1(vlSymsp); + vlTOPp->__Vm_traceActivity = (2U | vlTOPp->__Vm_traceActivity); + if ((((IData)(vlTOPp->clk) & (~ (IData)(vlTOPp->__Vclklast__TOP__clk))) + | ((IData)(vlTOPp->reset) & (~ (IData)(vlTOPp->__Vclklast__TOP__reset))))) { + vlTOPp->_sequent__TOP__4(vlSymsp); + vlTOPp->__Vm_traceActivity = (4U | vlTOPp->__Vm_traceActivity); + vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__0__KET____DOT__bank_structure._sequent__TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__5(vlSymsp); + vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__1__KET____DOT__bank_structure._sequent__TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__1__KET____DOT__bank_structure__6(vlSymsp); + vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__2__KET____DOT__bank_structure._sequent__TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__2__KET____DOT__bank_structure__7(vlSymsp); + vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__3__KET____DOT__bank_structure._sequent__TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__3__KET____DOT__bank_structure__8(vlSymsp); + } + vlTOPp->_combo__TOP__5(vlSymsp); + vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__0__KET____DOT__bank_structure._combo__TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__9(vlSymsp); + vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__1__KET____DOT__bank_structure._combo__TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__1__KET____DOT__bank_structure__10(vlSymsp); + vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__2__KET____DOT__bank_structure._combo__TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__2__KET____DOT__bank_structure__11(vlSymsp); + vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__3__KET____DOT__bank_structure._combo__TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__3__KET____DOT__bank_structure__12(vlSymsp); + vlTOPp->_settle__TOP__3(vlSymsp); + // Final + vlTOPp->__Vclklast__TOP__clk = vlTOPp->clk; + vlTOPp->__Vclklast__TOP__reset = vlTOPp->reset; +} + +void Vcache_simX::_eval_initial(Vcache_simX__Syms* __restrict vlSymsp) { + VL_DEBUG_IF(VL_DBG_MSGF("+ Vcache_simX::_eval_initial\n"); ); + Vcache_simX* __restrict vlTOPp VL_ATTR_UNUSED = vlSymsp->TOPp; + // Body + vlTOPp->__Vclklast__TOP__clk = vlTOPp->clk; + vlTOPp->__Vclklast__TOP__reset = vlTOPp->reset; +} + +void Vcache_simX::final() { + VL_DEBUG_IF(VL_DBG_MSGF("+ Vcache_simX::final\n"); ); + // Variables + Vcache_simX__Syms* __restrict vlSymsp = this->__VlSymsp; + Vcache_simX* __restrict vlTOPp VL_ATTR_UNUSED = vlSymsp->TOPp; +} + +void Vcache_simX::_eval_settle(Vcache_simX__Syms* __restrict vlSymsp) { + VL_DEBUG_IF(VL_DBG_MSGF("+ Vcache_simX::_eval_settle\n"); ); + Vcache_simX* __restrict vlTOPp VL_ATTR_UNUSED = vlSymsp->TOPp; + // Body + vlTOPp->_settle__TOP__2(vlSymsp); + vlTOPp->__Vm_traceActivity = (1U | vlTOPp->__Vm_traceActivity); + vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__0__KET____DOT__bank_structure._settle__TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__1(vlSymsp); + vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__1__KET____DOT__bank_structure._settle__TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__1__KET____DOT__bank_structure__2(vlSymsp); + vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__2__KET____DOT__bank_structure._settle__TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__2__KET____DOT__bank_structure__3(vlSymsp); + vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__3__KET____DOT__bank_structure._settle__TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__3__KET____DOT__bank_structure__4(vlSymsp); + vlTOPp->_settle__TOP__3(vlSymsp); +} + +VL_INLINE_OPT QData Vcache_simX::_change_request(Vcache_simX__Syms* __restrict vlSymsp) { + VL_DEBUG_IF(VL_DBG_MSGF("+ Vcache_simX::_change_request\n"); ); + Vcache_simX* __restrict vlTOPp VL_ATTR_UNUSED = vlSymsp->TOPp; + // Body + // Change detection + QData __req = false; // Logically a bool + return __req; +} + +#ifdef VL_DEBUG +void Vcache_simX::_eval_debug_assertions() { + VL_DEBUG_IF(VL_DBG_MSGF("+ Vcache_simX::_eval_debug_assertions\n"); ); + // Body + if (VL_UNLIKELY((clk & 0xfeU))) { + Verilated::overWidthError("clk");} + if (VL_UNLIKELY((reset & 0xfeU))) { + Verilated::overWidthError("reset");} + if (VL_UNLIKELY((in_icache_valid_pc_addr & 0xfeU))) { + Verilated::overWidthError("in_icache_valid_pc_addr");} + if (VL_UNLIKELY((in_dcache_mem_read & 0xf8U))) { + Verilated::overWidthError("in_dcache_mem_read");} + if (VL_UNLIKELY((in_dcache_mem_write & 0xf8U))) { + Verilated::overWidthError("in_dcache_mem_write");} +} +#endif // VL_DEBUG + +void Vcache_simX::_ctor_var_reset() { + VL_DEBUG_IF(VL_DBG_MSGF("+ Vcache_simX::_ctor_var_reset\n"); ); + // Body + clk = VL_RAND_RESET_I(1); + reset = VL_RAND_RESET_I(1); + in_icache_pc_addr = VL_RAND_RESET_I(32); + in_icache_valid_pc_addr = VL_RAND_RESET_I(1); + out_icache_stall = VL_RAND_RESET_I(1); + in_dcache_mem_read = VL_RAND_RESET_I(3); + in_dcache_mem_write = VL_RAND_RESET_I(3); + { int __Vi0=0; for (; __Vi0<4; ++__Vi0) { + in_dcache_in_valid[__Vi0] = VL_RAND_RESET_I(1); + }} + { int __Vi0=0; for (; __Vi0<4; ++__Vi0) { + in_dcache_in_address[__Vi0] = VL_RAND_RESET_I(32); + }} + out_dcache_stall = VL_RAND_RESET_I(1); + cache_simX__DOT__icache_i_m_ready = VL_RAND_RESET_I(1); + cache_simX__DOT__dcache_i_m_ready = VL_RAND_RESET_I(1); + cache_simX__DOT__dmem_controller__DOT__sm_driver_in_valid = VL_RAND_RESET_I(4); + cache_simX__DOT__dmem_controller__DOT__cache_driver_in_valid = VL_RAND_RESET_I(4); + cache_simX__DOT__dmem_controller__DOT__read_or_write = VL_RAND_RESET_I(1); + cache_simX__DOT__dmem_controller__DOT__cache_driver_in_mem_read = VL_RAND_RESET_I(3); + cache_simX__DOT__dmem_controller__DOT__cache_driver_in_mem_write = VL_RAND_RESET_I(3); + cache_simX__DOT__dmem_controller__DOT__sm_driver_in_mem_read = VL_RAND_RESET_I(3); + cache_simX__DOT__dmem_controller__DOT__sm_driver_in_mem_write = VL_RAND_RESET_I(3); + cache_simX__DOT__dmem_controller__DOT__icache_driver_in_mem_read = VL_RAND_RESET_I(3); + VL_RAND_RESET_W(512,cache_simX__DOT__dmem_controller__DOT____Vcellout__dcache__o_m_writedata); + cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__temp_out_valid = VL_RAND_RESET_I(4); + VL_RAND_RESET_W(128,cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__temp_out_data); + cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__block_addr = VL_RAND_RESET_I(28); + VL_RAND_RESET_W(512,cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__block_wdata); + VL_RAND_RESET_W(512,cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__block_rdata); + cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__block_we = VL_RAND_RESET_I(8); + cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__orig_in_valid = VL_RAND_RESET_I(4); + VL_RAND_RESET_W(128,cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT____Vcellout__vx_priority_encoder_sm__out_data); + VL_RAND_RESET_W(128,cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT____Vcellout__vx_priority_encoder_sm__out_address); + cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__genblk2__BRA__0__KET____DOT__shm_write = VL_RAND_RESET_I(1); + cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__genblk2__BRA__1__KET____DOT__shm_write = VL_RAND_RESET_I(1); + cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__genblk2__BRA__2__KET____DOT__shm_write = VL_RAND_RESET_I(1); + cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__genblk2__BRA__3__KET____DOT__shm_write = VL_RAND_RESET_I(1); + cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT____Vlvbound1 = VL_RAND_RESET_I(7); + cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT____Vlvbound2 = VL_RAND_RESET_I(7); + cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__vx_priority_encoder_sm__DOT__left_requests = VL_RAND_RESET_I(4); + cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__vx_priority_encoder_sm__DOT__serviced = VL_RAND_RESET_I(4); + cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__vx_priority_encoder_sm__DOT__use_valid = VL_RAND_RESET_I(4); + cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__vx_priority_encoder_sm__DOT____Vcellout__vx_bank_valid__bank_valids = VL_RAND_RESET_I(16); + cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__vx_priority_encoder_sm__DOT__more_than_one_valid = VL_RAND_RESET_I(4); + cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__vx_priority_encoder_sm__DOT__internal_req_num = VL_RAND_RESET_I(8); + cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__vx_priority_encoder_sm__DOT__internal_out_valid = VL_RAND_RESET_I(4); + cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__vx_priority_encoder_sm__DOT__serviced_qual = VL_RAND_RESET_I(4); + cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__vx_priority_encoder_sm__DOT__new_left_requests = VL_RAND_RESET_I(4); + cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__vx_priority_encoder_sm__DOT__genblk1__BRA__0__KET____DOT__num_valids = VL_RAND_RESET_I(3); + cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__vx_priority_encoder_sm__DOT__genblk1__BRA__1__KET____DOT__num_valids = VL_RAND_RESET_I(3); + cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__vx_priority_encoder_sm__DOT__genblk1__BRA__2__KET____DOT__num_valids = VL_RAND_RESET_I(3); + cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__vx_priority_encoder_sm__DOT__genblk1__BRA__3__KET____DOT__num_valids = VL_RAND_RESET_I(3); + cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__vx_priority_encoder_sm__DOT____Vcellout__genblk2__BRA__0__KET____DOT__vx_priority_encoder__found = VL_RAND_RESET_I(1); + cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__vx_priority_encoder_sm__DOT____Vcellout__genblk2__BRA__0__KET____DOT__vx_priority_encoder__index = VL_RAND_RESET_I(2); + cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__vx_priority_encoder_sm__DOT____Vcellout__genblk2__BRA__1__KET____DOT__vx_priority_encoder__found = VL_RAND_RESET_I(1); + cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__vx_priority_encoder_sm__DOT____Vcellout__genblk2__BRA__1__KET____DOT__vx_priority_encoder__index = VL_RAND_RESET_I(2); + cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__vx_priority_encoder_sm__DOT____Vcellout__genblk2__BRA__2__KET____DOT__vx_priority_encoder__found = VL_RAND_RESET_I(1); + cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__vx_priority_encoder_sm__DOT____Vcellout__genblk2__BRA__2__KET____DOT__vx_priority_encoder__index = VL_RAND_RESET_I(2); + cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__vx_priority_encoder_sm__DOT____Vcellout__genblk2__BRA__3__KET____DOT__vx_priority_encoder__found = VL_RAND_RESET_I(1); + cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__vx_priority_encoder_sm__DOT____Vcellout__genblk2__BRA__3__KET____DOT__vx_priority_encoder__index = VL_RAND_RESET_I(2); + cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__vx_priority_encoder_sm__DOT__genblk2__BRA__0__KET____DOT__vx_priority_encoder__DOT__i = VL_RAND_RESET_I(32); + cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__vx_priority_encoder_sm__DOT__genblk2__BRA__1__KET____DOT__vx_priority_encoder__DOT__i = VL_RAND_RESET_I(32); + cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__vx_priority_encoder_sm__DOT__genblk2__BRA__2__KET____DOT__vx_priority_encoder__DOT__i = VL_RAND_RESET_I(32); + cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__vx_priority_encoder_sm__DOT__genblk2__BRA__3__KET____DOT__vx_priority_encoder__DOT__i = VL_RAND_RESET_I(32); + { int __Vi0=0; for (; __Vi0<128; ++__Vi0) { + VL_RAND_RESET_W(128,cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__genblk2__BRA__0__KET____DOT__vx_shared_memory_block__DOT__shared_memory[__Vi0]); + }} + cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__genblk2__BRA__0__KET____DOT__vx_shared_memory_block__DOT__curr_ind = VL_RAND_RESET_I(32); + { int __Vi0=0; for (; __Vi0<128; ++__Vi0) { + VL_RAND_RESET_W(128,cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__genblk2__BRA__1__KET____DOT__vx_shared_memory_block__DOT__shared_memory[__Vi0]); + }} + cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__genblk2__BRA__1__KET____DOT__vx_shared_memory_block__DOT__curr_ind = VL_RAND_RESET_I(32); + { int __Vi0=0; for (; __Vi0<128; ++__Vi0) { + VL_RAND_RESET_W(128,cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__genblk2__BRA__2__KET____DOT__vx_shared_memory_block__DOT__shared_memory[__Vi0]); + }} + cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__genblk2__BRA__2__KET____DOT__vx_shared_memory_block__DOT__curr_ind = VL_RAND_RESET_I(32); + { int __Vi0=0; for (; __Vi0<128; ++__Vi0) { + VL_RAND_RESET_W(128,cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__genblk2__BRA__3__KET____DOT__vx_shared_memory_block__DOT__shared_memory[__Vi0]); + }} + cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__genblk2__BRA__3__KET____DOT__vx_shared_memory_block__DOT__curr_ind = VL_RAND_RESET_I(32); + VL_RAND_RESET_W(128,cache_simX__DOT__dmem_controller__DOT__dcache__DOT__final_data_read); + VL_RAND_RESET_W(128,cache_simX__DOT__dmem_controller__DOT__dcache__DOT__new_final_data_read); + VL_RAND_RESET_W(128,cache_simX__DOT__dmem_controller__DOT__dcache__DOT__new_final_data_read_Qual); + cache_simX__DOT__dmem_controller__DOT__dcache__DOT__global_way_to_evict = VL_RAND_RESET_I(1); + cache_simX__DOT__dmem_controller__DOT__dcache__DOT__index_per_bank = VL_RAND_RESET_I(8); + cache_simX__DOT__dmem_controller__DOT__dcache__DOT__use_mask_per_bank = VL_RAND_RESET_I(16); + cache_simX__DOT__dmem_controller__DOT__dcache__DOT__valid_per_bank = VL_RAND_RESET_I(4); + cache_simX__DOT__dmem_controller__DOT__dcache__DOT__threads_serviced_per_bank = VL_RAND_RESET_I(16); + VL_RAND_RESET_W(128,cache_simX__DOT__dmem_controller__DOT__dcache__DOT__readdata_per_bank); + cache_simX__DOT__dmem_controller__DOT__dcache__DOT__hit_per_bank = VL_RAND_RESET_I(4); + cache_simX__DOT__dmem_controller__DOT__dcache__DOT__eviction_wb = VL_RAND_RESET_I(4); + cache_simX__DOT__dmem_controller__DOT__dcache__DOT__eviction_wb_old = VL_RAND_RESET_I(4); + cache_simX__DOT__dmem_controller__DOT__dcache__DOT__state = VL_RAND_RESET_I(4); + cache_simX__DOT__dmem_controller__DOT__dcache__DOT__new_state = VL_RAND_RESET_I(4); + cache_simX__DOT__dmem_controller__DOT__dcache__DOT__use_valid = VL_RAND_RESET_I(4); + cache_simX__DOT__dmem_controller__DOT__dcache__DOT__stored_valid = VL_RAND_RESET_I(4); + cache_simX__DOT__dmem_controller__DOT__dcache__DOT__new_stored_valid = VL_RAND_RESET_I(4); + VL_RAND_RESET_W(128,cache_simX__DOT__dmem_controller__DOT__dcache__DOT__eviction_addr_per_bank); + cache_simX__DOT__dmem_controller__DOT__dcache__DOT__miss_addr = VL_RAND_RESET_I(32); + cache_simX__DOT__dmem_controller__DOT__dcache__DOT____Vcellout__multip_banks__thread_track_banks = VL_RAND_RESET_I(16); + cache_simX__DOT__dmem_controller__DOT__dcache__DOT__threads_serviced_Qual = VL_RAND_RESET_I(4); + { int __Vi0=0; for (; __Vi0<4; ++__Vi0) { + cache_simX__DOT__dmem_controller__DOT__dcache__DOT__debug_hit_per_bank_mask[__Vi0] = VL_RAND_RESET_I(4); + }} + cache_simX__DOT__dmem_controller__DOT__dcache__DOT__detect_bank_miss = VL_RAND_RESET_I(4); + cache_simX__DOT__dmem_controller__DOT__dcache__DOT__miss_bank_index = VL_RAND_RESET_I(2); + cache_simX__DOT__dmem_controller__DOT__dcache__DOT__miss_found = VL_RAND_RESET_I(1); + cache_simX__DOT__dmem_controller__DOT__dcache__DOT__init_b = VL_RAND_RESET_I(32); + cache_simX__DOT__dmem_controller__DOT__dcache__DOT____Vcellout__genblk1__BRA__0__KET____DOT__choose_thread__found = VL_RAND_RESET_I(1); + cache_simX__DOT__dmem_controller__DOT__dcache__DOT____Vcellout__genblk1__BRA__0__KET____DOT__choose_thread__index = VL_RAND_RESET_I(2); + cache_simX__DOT__dmem_controller__DOT__dcache__DOT____Vcellout__genblk1__BRA__1__KET____DOT__choose_thread__found = VL_RAND_RESET_I(1); + cache_simX__DOT__dmem_controller__DOT__dcache__DOT____Vcellout__genblk1__BRA__1__KET____DOT__choose_thread__index = VL_RAND_RESET_I(2); + cache_simX__DOT__dmem_controller__DOT__dcache__DOT____Vcellout__genblk1__BRA__2__KET____DOT__choose_thread__found = VL_RAND_RESET_I(1); + cache_simX__DOT__dmem_controller__DOT__dcache__DOT____Vcellout__genblk1__BRA__2__KET____DOT__choose_thread__index = VL_RAND_RESET_I(2); + cache_simX__DOT__dmem_controller__DOT__dcache__DOT____Vcellout__genblk1__BRA__3__KET____DOT__choose_thread__found = VL_RAND_RESET_I(1); + cache_simX__DOT__dmem_controller__DOT__dcache__DOT____Vcellout__genblk1__BRA__3__KET____DOT__choose_thread__index = VL_RAND_RESET_I(2); + cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__0__KET____DOT__bank_addr = VL_RAND_RESET_I(32); + cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__0__KET____DOT__use_valid_in = VL_RAND_RESET_I(1); + cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__1__KET____DOT__bank_addr = VL_RAND_RESET_I(32); + cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__1__KET____DOT__use_valid_in = VL_RAND_RESET_I(1); + cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__2__KET____DOT__bank_addr = VL_RAND_RESET_I(32); + cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__2__KET____DOT__use_valid_in = VL_RAND_RESET_I(1); + cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__3__KET____DOT__bank_addr = VL_RAND_RESET_I(32); + cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__3__KET____DOT__use_valid_in = VL_RAND_RESET_I(1); + cache_simX__DOT__dmem_controller__DOT__dcache__DOT__get_miss_index__DOT__i = VL_RAND_RESET_I(32); + cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk1__BRA__0__KET____DOT__choose_thread__DOT__i = VL_RAND_RESET_I(32); + cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk1__BRA__1__KET____DOT__choose_thread__DOT__i = VL_RAND_RESET_I(32); + cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk1__BRA__2__KET____DOT__choose_thread__DOT__i = VL_RAND_RESET_I(32); + cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk1__BRA__3__KET____DOT__choose_thread__DOT__i = VL_RAND_RESET_I(32); + cache_simX__DOT__dmem_controller__DOT__icache__DOT__final_data_read = VL_RAND_RESET_I(32); + cache_simX__DOT__dmem_controller__DOT__icache__DOT__new_final_data_read = VL_RAND_RESET_I(32); + cache_simX__DOT__dmem_controller__DOT__icache__DOT__new_final_data_read_Qual = VL_RAND_RESET_I(32); + cache_simX__DOT__dmem_controller__DOT__icache__DOT__global_way_to_evict = VL_RAND_RESET_I(1); + cache_simX__DOT__dmem_controller__DOT__icache__DOT__valid_per_bank = VL_RAND_RESET_I(1); + cache_simX__DOT__dmem_controller__DOT__icache__DOT__threads_serviced_per_bank = VL_RAND_RESET_I(1); + cache_simX__DOT__dmem_controller__DOT__icache__DOT__hit_per_bank = VL_RAND_RESET_I(1); + cache_simX__DOT__dmem_controller__DOT__icache__DOT__eviction_wb_old = VL_RAND_RESET_I(1); + cache_simX__DOT__dmem_controller__DOT__icache__DOT__state = VL_RAND_RESET_I(4); + cache_simX__DOT__dmem_controller__DOT__icache__DOT__new_state = VL_RAND_RESET_I(4); + cache_simX__DOT__dmem_controller__DOT__icache__DOT__use_valid = VL_RAND_RESET_I(1); + cache_simX__DOT__dmem_controller__DOT__icache__DOT__stored_valid = VL_RAND_RESET_I(1); + cache_simX__DOT__dmem_controller__DOT__icache__DOT__new_stored_valid = VL_RAND_RESET_I(1); + cache_simX__DOT__dmem_controller__DOT__icache__DOT__miss_addr = VL_RAND_RESET_I(32); + cache_simX__DOT__dmem_controller__DOT__icache__DOT____Vcellout__multip_banks__thread_track_banks = VL_RAND_RESET_I(1); + { int __Vi0=0; for (; __Vi0<1; ++__Vi0) { + cache_simX__DOT__dmem_controller__DOT__icache__DOT__debug_hit_per_bank_mask[__Vi0] = VL_RAND_RESET_I(1); + }} + cache_simX__DOT__dmem_controller__DOT__icache__DOT__detect_bank_miss = VL_RAND_RESET_I(1); + cache_simX__DOT__dmem_controller__DOT__icache__DOT__miss_bank_index = VL_RAND_RESET_I(1); + cache_simX__DOT__dmem_controller__DOT__icache__DOT__miss_found = VL_RAND_RESET_I(1); + cache_simX__DOT__dmem_controller__DOT__icache__DOT__init_b = VL_RAND_RESET_I(32); + cache_simX__DOT__dmem_controller__DOT__icache__DOT____Vcellout__genblk1__BRA__0__KET____DOT__choose_thread__index = VL_RAND_RESET_I(1); + cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_addr = VL_RAND_RESET_I(32); + cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__use_valid_in = VL_RAND_RESET_I(1); + cache_simX__DOT__dmem_controller__DOT__icache__DOT__multip_banks__DOT____Vlvbound1 = VL_RAND_RESET_I(1); + cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__tag_use = VL_RAND_RESET_I(23); + cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__valid_use = VL_RAND_RESET_I(1); + cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__access = VL_RAND_RESET_I(1); + cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__write_from_mem = VL_RAND_RESET_I(1); + cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__way_to_update = VL_RAND_RESET_I(1); + cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__data_unQual = VL_RAND_RESET_I(32); + cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__sb_mask = VL_RAND_RESET_I(4); + cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__we = VL_RAND_RESET_I(16); + VL_RAND_RESET_W(128,cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__data_write); + cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__data_structures__DOT__tag_use_per_way = VL_RAND_RESET_Q(46); + VL_RAND_RESET_W(256,cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__data_structures__DOT__data_use_per_way); + cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__data_structures__DOT__valid_use_per_way = VL_RAND_RESET_I(2); + cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__data_structures__DOT__dirty_use_per_way = VL_RAND_RESET_I(2); + cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__data_structures__DOT__hit_per_way = VL_RAND_RESET_I(2); + cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__data_structures__DOT__we_per_way = VL_RAND_RESET_I(32); + VL_RAND_RESET_W(256,cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__data_structures__DOT__data_write_per_way); + cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__data_structures__DOT__write_from_mem_per_way = VL_RAND_RESET_I(2); + cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__data_structures__DOT__invalid_found = VL_RAND_RESET_I(1); + cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__data_structures__DOT__way_index = VL_RAND_RESET_I(1); + cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__data_structures__DOT__invalid_index = VL_RAND_RESET_I(1); + cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__data_structures__DOT__way_use_Qual = VL_RAND_RESET_I(1); + cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__data_structures__DOT____Vcellout__each_way__BRA__0__KET____DOT__data_structures__dirty_use = VL_RAND_RESET_I(1); + cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__data_structures__DOT____Vcellout__each_way__BRA__1__KET____DOT__data_structures__dirty_use = VL_RAND_RESET_I(1); + cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__data_structures__DOT__genblk1__DOT__way_indexing__DOT__found = VL_RAND_RESET_I(1); + { int __Vi0=0; for (; __Vi0<32; ++__Vi0) { + VL_RAND_RESET_W(128,cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__data[__Vi0]); + }} + { int __Vi0=0; for (; __Vi0<32; ++__Vi0) { + cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__tag[__Vi0] = VL_RAND_RESET_I(23); + }} + { int __Vi0=0; for (; __Vi0<32; ++__Vi0) { + cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__valid[__Vi0] = VL_RAND_RESET_I(1); + }} + { int __Vi0=0; for (; __Vi0<32; ++__Vi0) { + cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__dirty[__Vi0] = VL_RAND_RESET_I(1); + }} + cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__f = VL_RAND_RESET_I(32); + cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__ini_ind = VL_RAND_RESET_I(32); + { int __Vi0=0; for (; __Vi0<32; ++__Vi0) { + VL_RAND_RESET_W(128,cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__data_structures__DOT__each_way__BRA__1__KET____DOT__data_structures__DOT__data[__Vi0]); + }} + { int __Vi0=0; for (; __Vi0<32; ++__Vi0) { + cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__data_structures__DOT__each_way__BRA__1__KET____DOT__data_structures__DOT__tag[__Vi0] = VL_RAND_RESET_I(23); + }} + { int __Vi0=0; for (; __Vi0<32; ++__Vi0) { + cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__data_structures__DOT__each_way__BRA__1__KET____DOT__data_structures__DOT__valid[__Vi0] = VL_RAND_RESET_I(1); + }} + { int __Vi0=0; for (; __Vi0<32; ++__Vi0) { + cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__data_structures__DOT__each_way__BRA__1__KET____DOT__data_structures__DOT__dirty[__Vi0] = VL_RAND_RESET_I(1); + }} + cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__data_structures__DOT__each_way__BRA__1__KET____DOT__data_structures__DOT__f = VL_RAND_RESET_I(32); + cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__data_structures__DOT__each_way__BRA__1__KET____DOT__data_structures__DOT__ini_ind = VL_RAND_RESET_I(32); + __Vtableidx1 = 0; + __Vtable1_cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__vx_priority_encoder_sm__DOT____Vcellout__genblk2__BRA__0__KET____DOT__vx_priority_encoder__index[0] = 0U; + __Vtable1_cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__vx_priority_encoder_sm__DOT____Vcellout__genblk2__BRA__0__KET____DOT__vx_priority_encoder__index[1] = 0U; + __Vtable1_cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__vx_priority_encoder_sm__DOT____Vcellout__genblk2__BRA__0__KET____DOT__vx_priority_encoder__index[2] = 1U; + __Vtable1_cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__vx_priority_encoder_sm__DOT____Vcellout__genblk2__BRA__0__KET____DOT__vx_priority_encoder__index[3] = 0U; + __Vtable1_cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__vx_priority_encoder_sm__DOT____Vcellout__genblk2__BRA__0__KET____DOT__vx_priority_encoder__index[4] = 2U; + __Vtable1_cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__vx_priority_encoder_sm__DOT____Vcellout__genblk2__BRA__0__KET____DOT__vx_priority_encoder__index[5] = 0U; + __Vtable1_cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__vx_priority_encoder_sm__DOT____Vcellout__genblk2__BRA__0__KET____DOT__vx_priority_encoder__index[6] = 1U; + __Vtable1_cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__vx_priority_encoder_sm__DOT____Vcellout__genblk2__BRA__0__KET____DOT__vx_priority_encoder__index[7] = 0U; + __Vtable1_cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__vx_priority_encoder_sm__DOT____Vcellout__genblk2__BRA__0__KET____DOT__vx_priority_encoder__index[8] = 3U; + __Vtable1_cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__vx_priority_encoder_sm__DOT____Vcellout__genblk2__BRA__0__KET____DOT__vx_priority_encoder__index[9] = 0U; + __Vtable1_cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__vx_priority_encoder_sm__DOT____Vcellout__genblk2__BRA__0__KET____DOT__vx_priority_encoder__index[10] = 1U; + __Vtable1_cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__vx_priority_encoder_sm__DOT____Vcellout__genblk2__BRA__0__KET____DOT__vx_priority_encoder__index[11] = 0U; + __Vtable1_cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__vx_priority_encoder_sm__DOT____Vcellout__genblk2__BRA__0__KET____DOT__vx_priority_encoder__index[12] = 2U; + __Vtable1_cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__vx_priority_encoder_sm__DOT____Vcellout__genblk2__BRA__0__KET____DOT__vx_priority_encoder__index[13] = 0U; + __Vtable1_cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__vx_priority_encoder_sm__DOT____Vcellout__genblk2__BRA__0__KET____DOT__vx_priority_encoder__index[14] = 1U; + __Vtable1_cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__vx_priority_encoder_sm__DOT____Vcellout__genblk2__BRA__0__KET____DOT__vx_priority_encoder__index[15] = 0U; + __Vtable1_cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__vx_priority_encoder_sm__DOT____Vcellout__genblk2__BRA__0__KET____DOT__vx_priority_encoder__found[0] = 0U; + __Vtable1_cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__vx_priority_encoder_sm__DOT____Vcellout__genblk2__BRA__0__KET____DOT__vx_priority_encoder__found[1] = 1U; + __Vtable1_cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__vx_priority_encoder_sm__DOT____Vcellout__genblk2__BRA__0__KET____DOT__vx_priority_encoder__found[2] = 1U; + __Vtable1_cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__vx_priority_encoder_sm__DOT____Vcellout__genblk2__BRA__0__KET____DOT__vx_priority_encoder__found[3] = 1U; + __Vtable1_cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__vx_priority_encoder_sm__DOT____Vcellout__genblk2__BRA__0__KET____DOT__vx_priority_encoder__found[4] = 1U; + __Vtable1_cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__vx_priority_encoder_sm__DOT____Vcellout__genblk2__BRA__0__KET____DOT__vx_priority_encoder__found[5] = 1U; + __Vtable1_cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__vx_priority_encoder_sm__DOT____Vcellout__genblk2__BRA__0__KET____DOT__vx_priority_encoder__found[6] = 1U; + __Vtable1_cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__vx_priority_encoder_sm__DOT____Vcellout__genblk2__BRA__0__KET____DOT__vx_priority_encoder__found[7] = 1U; + __Vtable1_cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__vx_priority_encoder_sm__DOT____Vcellout__genblk2__BRA__0__KET____DOT__vx_priority_encoder__found[8] = 1U; + __Vtable1_cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__vx_priority_encoder_sm__DOT____Vcellout__genblk2__BRA__0__KET____DOT__vx_priority_encoder__found[9] = 1U; + __Vtable1_cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__vx_priority_encoder_sm__DOT____Vcellout__genblk2__BRA__0__KET____DOT__vx_priority_encoder__found[10] = 1U; + __Vtable1_cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__vx_priority_encoder_sm__DOT____Vcellout__genblk2__BRA__0__KET____DOT__vx_priority_encoder__found[11] = 1U; + __Vtable1_cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__vx_priority_encoder_sm__DOT____Vcellout__genblk2__BRA__0__KET____DOT__vx_priority_encoder__found[12] = 1U; + __Vtable1_cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__vx_priority_encoder_sm__DOT____Vcellout__genblk2__BRA__0__KET____DOT__vx_priority_encoder__found[13] = 1U; + __Vtable1_cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__vx_priority_encoder_sm__DOT____Vcellout__genblk2__BRA__0__KET____DOT__vx_priority_encoder__found[14] = 1U; + __Vtable1_cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__vx_priority_encoder_sm__DOT____Vcellout__genblk2__BRA__0__KET____DOT__vx_priority_encoder__found[15] = 1U; + __Vtable1_cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__vx_priority_encoder_sm__DOT__genblk2__BRA__0__KET____DOT__vx_priority_encoder__DOT__i[0] = 0xffffffffU; + __Vtable1_cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__vx_priority_encoder_sm__DOT__genblk2__BRA__0__KET____DOT__vx_priority_encoder__DOT__i[1] = 0xffffffffU; + __Vtable1_cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__vx_priority_encoder_sm__DOT__genblk2__BRA__0__KET____DOT__vx_priority_encoder__DOT__i[2] = 0xffffffffU; + __Vtable1_cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__vx_priority_encoder_sm__DOT__genblk2__BRA__0__KET____DOT__vx_priority_encoder__DOT__i[3] = 0xffffffffU; + __Vtable1_cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__vx_priority_encoder_sm__DOT__genblk2__BRA__0__KET____DOT__vx_priority_encoder__DOT__i[4] = 0xffffffffU; + __Vtable1_cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__vx_priority_encoder_sm__DOT__genblk2__BRA__0__KET____DOT__vx_priority_encoder__DOT__i[5] = 0xffffffffU; + __Vtable1_cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__vx_priority_encoder_sm__DOT__genblk2__BRA__0__KET____DOT__vx_priority_encoder__DOT__i[6] = 0xffffffffU; + __Vtable1_cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__vx_priority_encoder_sm__DOT__genblk2__BRA__0__KET____DOT__vx_priority_encoder__DOT__i[7] = 0xffffffffU; + __Vtable1_cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__vx_priority_encoder_sm__DOT__genblk2__BRA__0__KET____DOT__vx_priority_encoder__DOT__i[8] = 0xffffffffU; + __Vtable1_cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__vx_priority_encoder_sm__DOT__genblk2__BRA__0__KET____DOT__vx_priority_encoder__DOT__i[9] = 0xffffffffU; + __Vtable1_cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__vx_priority_encoder_sm__DOT__genblk2__BRA__0__KET____DOT__vx_priority_encoder__DOT__i[10] = 0xffffffffU; + __Vtable1_cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__vx_priority_encoder_sm__DOT__genblk2__BRA__0__KET____DOT__vx_priority_encoder__DOT__i[11] = 0xffffffffU; + __Vtable1_cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__vx_priority_encoder_sm__DOT__genblk2__BRA__0__KET____DOT__vx_priority_encoder__DOT__i[12] = 0xffffffffU; + __Vtable1_cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__vx_priority_encoder_sm__DOT__genblk2__BRA__0__KET____DOT__vx_priority_encoder__DOT__i[13] = 0xffffffffU; + __Vtable1_cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__vx_priority_encoder_sm__DOT__genblk2__BRA__0__KET____DOT__vx_priority_encoder__DOT__i[14] = 0xffffffffU; + __Vtable1_cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__vx_priority_encoder_sm__DOT__genblk2__BRA__0__KET____DOT__vx_priority_encoder__DOT__i[15] = 0xffffffffU; + __Vtableidx2 = 0; + __Vtable2_cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__vx_priority_encoder_sm__DOT____Vcellout__genblk2__BRA__1__KET____DOT__vx_priority_encoder__index[0] = 0U; + __Vtable2_cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__vx_priority_encoder_sm__DOT____Vcellout__genblk2__BRA__1__KET____DOT__vx_priority_encoder__index[1] = 0U; + __Vtable2_cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__vx_priority_encoder_sm__DOT____Vcellout__genblk2__BRA__1__KET____DOT__vx_priority_encoder__index[2] = 1U; + __Vtable2_cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__vx_priority_encoder_sm__DOT____Vcellout__genblk2__BRA__1__KET____DOT__vx_priority_encoder__index[3] = 0U; + __Vtable2_cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__vx_priority_encoder_sm__DOT____Vcellout__genblk2__BRA__1__KET____DOT__vx_priority_encoder__index[4] = 2U; + __Vtable2_cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__vx_priority_encoder_sm__DOT____Vcellout__genblk2__BRA__1__KET____DOT__vx_priority_encoder__index[5] = 0U; + __Vtable2_cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__vx_priority_encoder_sm__DOT____Vcellout__genblk2__BRA__1__KET____DOT__vx_priority_encoder__index[6] = 1U; + __Vtable2_cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__vx_priority_encoder_sm__DOT____Vcellout__genblk2__BRA__1__KET____DOT__vx_priority_encoder__index[7] = 0U; + __Vtable2_cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__vx_priority_encoder_sm__DOT____Vcellout__genblk2__BRA__1__KET____DOT__vx_priority_encoder__index[8] = 3U; + __Vtable2_cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__vx_priority_encoder_sm__DOT____Vcellout__genblk2__BRA__1__KET____DOT__vx_priority_encoder__index[9] = 0U; + __Vtable2_cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__vx_priority_encoder_sm__DOT____Vcellout__genblk2__BRA__1__KET____DOT__vx_priority_encoder__index[10] = 1U; + __Vtable2_cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__vx_priority_encoder_sm__DOT____Vcellout__genblk2__BRA__1__KET____DOT__vx_priority_encoder__index[11] = 0U; + __Vtable2_cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__vx_priority_encoder_sm__DOT____Vcellout__genblk2__BRA__1__KET____DOT__vx_priority_encoder__index[12] = 2U; + __Vtable2_cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__vx_priority_encoder_sm__DOT____Vcellout__genblk2__BRA__1__KET____DOT__vx_priority_encoder__index[13] = 0U; + __Vtable2_cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__vx_priority_encoder_sm__DOT____Vcellout__genblk2__BRA__1__KET____DOT__vx_priority_encoder__index[14] = 1U; + __Vtable2_cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__vx_priority_encoder_sm__DOT____Vcellout__genblk2__BRA__1__KET____DOT__vx_priority_encoder__index[15] = 0U; + __Vtable2_cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__vx_priority_encoder_sm__DOT____Vcellout__genblk2__BRA__1__KET____DOT__vx_priority_encoder__found[0] = 0U; + __Vtable2_cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__vx_priority_encoder_sm__DOT____Vcellout__genblk2__BRA__1__KET____DOT__vx_priority_encoder__found[1] = 1U; + __Vtable2_cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__vx_priority_encoder_sm__DOT____Vcellout__genblk2__BRA__1__KET____DOT__vx_priority_encoder__found[2] = 1U; + __Vtable2_cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__vx_priority_encoder_sm__DOT____Vcellout__genblk2__BRA__1__KET____DOT__vx_priority_encoder__found[3] = 1U; + __Vtable2_cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__vx_priority_encoder_sm__DOT____Vcellout__genblk2__BRA__1__KET____DOT__vx_priority_encoder__found[4] = 1U; + __Vtable2_cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__vx_priority_encoder_sm__DOT____Vcellout__genblk2__BRA__1__KET____DOT__vx_priority_encoder__found[5] = 1U; + __Vtable2_cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__vx_priority_encoder_sm__DOT____Vcellout__genblk2__BRA__1__KET____DOT__vx_priority_encoder__found[6] = 1U; + __Vtable2_cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__vx_priority_encoder_sm__DOT____Vcellout__genblk2__BRA__1__KET____DOT__vx_priority_encoder__found[7] = 1U; + __Vtable2_cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__vx_priority_encoder_sm__DOT____Vcellout__genblk2__BRA__1__KET____DOT__vx_priority_encoder__found[8] = 1U; + __Vtable2_cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__vx_priority_encoder_sm__DOT____Vcellout__genblk2__BRA__1__KET____DOT__vx_priority_encoder__found[9] = 1U; + __Vtable2_cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__vx_priority_encoder_sm__DOT____Vcellout__genblk2__BRA__1__KET____DOT__vx_priority_encoder__found[10] = 1U; + __Vtable2_cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__vx_priority_encoder_sm__DOT____Vcellout__genblk2__BRA__1__KET____DOT__vx_priority_encoder__found[11] = 1U; + __Vtable2_cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__vx_priority_encoder_sm__DOT____Vcellout__genblk2__BRA__1__KET____DOT__vx_priority_encoder__found[12] = 1U; + __Vtable2_cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__vx_priority_encoder_sm__DOT____Vcellout__genblk2__BRA__1__KET____DOT__vx_priority_encoder__found[13] = 1U; + __Vtable2_cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__vx_priority_encoder_sm__DOT____Vcellout__genblk2__BRA__1__KET____DOT__vx_priority_encoder__found[14] = 1U; + __Vtable2_cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__vx_priority_encoder_sm__DOT____Vcellout__genblk2__BRA__1__KET____DOT__vx_priority_encoder__found[15] = 1U; + __Vtable2_cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__vx_priority_encoder_sm__DOT__genblk2__BRA__1__KET____DOT__vx_priority_encoder__DOT__i[0] = 0xffffffffU; + __Vtable2_cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__vx_priority_encoder_sm__DOT__genblk2__BRA__1__KET____DOT__vx_priority_encoder__DOT__i[1] = 0xffffffffU; + __Vtable2_cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__vx_priority_encoder_sm__DOT__genblk2__BRA__1__KET____DOT__vx_priority_encoder__DOT__i[2] = 0xffffffffU; + __Vtable2_cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__vx_priority_encoder_sm__DOT__genblk2__BRA__1__KET____DOT__vx_priority_encoder__DOT__i[3] = 0xffffffffU; + __Vtable2_cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__vx_priority_encoder_sm__DOT__genblk2__BRA__1__KET____DOT__vx_priority_encoder__DOT__i[4] = 0xffffffffU; + __Vtable2_cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__vx_priority_encoder_sm__DOT__genblk2__BRA__1__KET____DOT__vx_priority_encoder__DOT__i[5] = 0xffffffffU; + __Vtable2_cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__vx_priority_encoder_sm__DOT__genblk2__BRA__1__KET____DOT__vx_priority_encoder__DOT__i[6] = 0xffffffffU; + __Vtable2_cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__vx_priority_encoder_sm__DOT__genblk2__BRA__1__KET____DOT__vx_priority_encoder__DOT__i[7] = 0xffffffffU; + __Vtable2_cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__vx_priority_encoder_sm__DOT__genblk2__BRA__1__KET____DOT__vx_priority_encoder__DOT__i[8] = 0xffffffffU; + __Vtable2_cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__vx_priority_encoder_sm__DOT__genblk2__BRA__1__KET____DOT__vx_priority_encoder__DOT__i[9] = 0xffffffffU; + __Vtable2_cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__vx_priority_encoder_sm__DOT__genblk2__BRA__1__KET____DOT__vx_priority_encoder__DOT__i[10] = 0xffffffffU; + __Vtable2_cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__vx_priority_encoder_sm__DOT__genblk2__BRA__1__KET____DOT__vx_priority_encoder__DOT__i[11] = 0xffffffffU; + __Vtable2_cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__vx_priority_encoder_sm__DOT__genblk2__BRA__1__KET____DOT__vx_priority_encoder__DOT__i[12] = 0xffffffffU; + __Vtable2_cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__vx_priority_encoder_sm__DOT__genblk2__BRA__1__KET____DOT__vx_priority_encoder__DOT__i[13] = 0xffffffffU; + __Vtable2_cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__vx_priority_encoder_sm__DOT__genblk2__BRA__1__KET____DOT__vx_priority_encoder__DOT__i[14] = 0xffffffffU; + __Vtable2_cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__vx_priority_encoder_sm__DOT__genblk2__BRA__1__KET____DOT__vx_priority_encoder__DOT__i[15] = 0xffffffffU; + __Vtableidx3 = 0; + __Vtable3_cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__vx_priority_encoder_sm__DOT____Vcellout__genblk2__BRA__2__KET____DOT__vx_priority_encoder__index[0] = 0U; + __Vtable3_cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__vx_priority_encoder_sm__DOT____Vcellout__genblk2__BRA__2__KET____DOT__vx_priority_encoder__index[1] = 0U; + __Vtable3_cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__vx_priority_encoder_sm__DOT____Vcellout__genblk2__BRA__2__KET____DOT__vx_priority_encoder__index[2] = 1U; + __Vtable3_cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__vx_priority_encoder_sm__DOT____Vcellout__genblk2__BRA__2__KET____DOT__vx_priority_encoder__index[3] = 0U; + __Vtable3_cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__vx_priority_encoder_sm__DOT____Vcellout__genblk2__BRA__2__KET____DOT__vx_priority_encoder__index[4] = 2U; + __Vtable3_cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__vx_priority_encoder_sm__DOT____Vcellout__genblk2__BRA__2__KET____DOT__vx_priority_encoder__index[5] = 0U; + __Vtable3_cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__vx_priority_encoder_sm__DOT____Vcellout__genblk2__BRA__2__KET____DOT__vx_priority_encoder__index[6] = 1U; + __Vtable3_cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__vx_priority_encoder_sm__DOT____Vcellout__genblk2__BRA__2__KET____DOT__vx_priority_encoder__index[7] = 0U; + __Vtable3_cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__vx_priority_encoder_sm__DOT____Vcellout__genblk2__BRA__2__KET____DOT__vx_priority_encoder__index[8] = 3U; + __Vtable3_cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__vx_priority_encoder_sm__DOT____Vcellout__genblk2__BRA__2__KET____DOT__vx_priority_encoder__index[9] = 0U; + __Vtable3_cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__vx_priority_encoder_sm__DOT____Vcellout__genblk2__BRA__2__KET____DOT__vx_priority_encoder__index[10] = 1U; + __Vtable3_cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__vx_priority_encoder_sm__DOT____Vcellout__genblk2__BRA__2__KET____DOT__vx_priority_encoder__index[11] = 0U; + __Vtable3_cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__vx_priority_encoder_sm__DOT____Vcellout__genblk2__BRA__2__KET____DOT__vx_priority_encoder__index[12] = 2U; + __Vtable3_cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__vx_priority_encoder_sm__DOT____Vcellout__genblk2__BRA__2__KET____DOT__vx_priority_encoder__index[13] = 0U; + __Vtable3_cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__vx_priority_encoder_sm__DOT____Vcellout__genblk2__BRA__2__KET____DOT__vx_priority_encoder__index[14] = 1U; + __Vtable3_cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__vx_priority_encoder_sm__DOT____Vcellout__genblk2__BRA__2__KET____DOT__vx_priority_encoder__index[15] = 0U; + __Vtable3_cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__vx_priority_encoder_sm__DOT____Vcellout__genblk2__BRA__2__KET____DOT__vx_priority_encoder__found[0] = 0U; + __Vtable3_cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__vx_priority_encoder_sm__DOT____Vcellout__genblk2__BRA__2__KET____DOT__vx_priority_encoder__found[1] = 1U; + __Vtable3_cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__vx_priority_encoder_sm__DOT____Vcellout__genblk2__BRA__2__KET____DOT__vx_priority_encoder__found[2] = 1U; + __Vtable3_cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__vx_priority_encoder_sm__DOT____Vcellout__genblk2__BRA__2__KET____DOT__vx_priority_encoder__found[3] = 1U; + __Vtable3_cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__vx_priority_encoder_sm__DOT____Vcellout__genblk2__BRA__2__KET____DOT__vx_priority_encoder__found[4] = 1U; + __Vtable3_cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__vx_priority_encoder_sm__DOT____Vcellout__genblk2__BRA__2__KET____DOT__vx_priority_encoder__found[5] = 1U; + __Vtable3_cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__vx_priority_encoder_sm__DOT____Vcellout__genblk2__BRA__2__KET____DOT__vx_priority_encoder__found[6] = 1U; + __Vtable3_cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__vx_priority_encoder_sm__DOT____Vcellout__genblk2__BRA__2__KET____DOT__vx_priority_encoder__found[7] = 1U; + __Vtable3_cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__vx_priority_encoder_sm__DOT____Vcellout__genblk2__BRA__2__KET____DOT__vx_priority_encoder__found[8] = 1U; + __Vtable3_cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__vx_priority_encoder_sm__DOT____Vcellout__genblk2__BRA__2__KET____DOT__vx_priority_encoder__found[9] = 1U; + __Vtable3_cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__vx_priority_encoder_sm__DOT____Vcellout__genblk2__BRA__2__KET____DOT__vx_priority_encoder__found[10] = 1U; + __Vtable3_cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__vx_priority_encoder_sm__DOT____Vcellout__genblk2__BRA__2__KET____DOT__vx_priority_encoder__found[11] = 1U; + __Vtable3_cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__vx_priority_encoder_sm__DOT____Vcellout__genblk2__BRA__2__KET____DOT__vx_priority_encoder__found[12] = 1U; + __Vtable3_cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__vx_priority_encoder_sm__DOT____Vcellout__genblk2__BRA__2__KET____DOT__vx_priority_encoder__found[13] = 1U; + __Vtable3_cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__vx_priority_encoder_sm__DOT____Vcellout__genblk2__BRA__2__KET____DOT__vx_priority_encoder__found[14] = 1U; + __Vtable3_cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__vx_priority_encoder_sm__DOT____Vcellout__genblk2__BRA__2__KET____DOT__vx_priority_encoder__found[15] = 1U; + __Vtable3_cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__vx_priority_encoder_sm__DOT__genblk2__BRA__2__KET____DOT__vx_priority_encoder__DOT__i[0] = 0xffffffffU; + __Vtable3_cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__vx_priority_encoder_sm__DOT__genblk2__BRA__2__KET____DOT__vx_priority_encoder__DOT__i[1] = 0xffffffffU; + __Vtable3_cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__vx_priority_encoder_sm__DOT__genblk2__BRA__2__KET____DOT__vx_priority_encoder__DOT__i[2] = 0xffffffffU; + __Vtable3_cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__vx_priority_encoder_sm__DOT__genblk2__BRA__2__KET____DOT__vx_priority_encoder__DOT__i[3] = 0xffffffffU; + __Vtable3_cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__vx_priority_encoder_sm__DOT__genblk2__BRA__2__KET____DOT__vx_priority_encoder__DOT__i[4] = 0xffffffffU; + __Vtable3_cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__vx_priority_encoder_sm__DOT__genblk2__BRA__2__KET____DOT__vx_priority_encoder__DOT__i[5] = 0xffffffffU; + __Vtable3_cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__vx_priority_encoder_sm__DOT__genblk2__BRA__2__KET____DOT__vx_priority_encoder__DOT__i[6] = 0xffffffffU; + __Vtable3_cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__vx_priority_encoder_sm__DOT__genblk2__BRA__2__KET____DOT__vx_priority_encoder__DOT__i[7] = 0xffffffffU; + __Vtable3_cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__vx_priority_encoder_sm__DOT__genblk2__BRA__2__KET____DOT__vx_priority_encoder__DOT__i[8] = 0xffffffffU; + __Vtable3_cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__vx_priority_encoder_sm__DOT__genblk2__BRA__2__KET____DOT__vx_priority_encoder__DOT__i[9] = 0xffffffffU; + __Vtable3_cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__vx_priority_encoder_sm__DOT__genblk2__BRA__2__KET____DOT__vx_priority_encoder__DOT__i[10] = 0xffffffffU; + __Vtable3_cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__vx_priority_encoder_sm__DOT__genblk2__BRA__2__KET____DOT__vx_priority_encoder__DOT__i[11] = 0xffffffffU; + __Vtable3_cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__vx_priority_encoder_sm__DOT__genblk2__BRA__2__KET____DOT__vx_priority_encoder__DOT__i[12] = 0xffffffffU; + __Vtable3_cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__vx_priority_encoder_sm__DOT__genblk2__BRA__2__KET____DOT__vx_priority_encoder__DOT__i[13] = 0xffffffffU; + __Vtable3_cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__vx_priority_encoder_sm__DOT__genblk2__BRA__2__KET____DOT__vx_priority_encoder__DOT__i[14] = 0xffffffffU; + __Vtable3_cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__vx_priority_encoder_sm__DOT__genblk2__BRA__2__KET____DOT__vx_priority_encoder__DOT__i[15] = 0xffffffffU; + __Vtableidx4 = 0; + __Vtable4_cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__vx_priority_encoder_sm__DOT____Vcellout__genblk2__BRA__3__KET____DOT__vx_priority_encoder__index[0] = 0U; + __Vtable4_cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__vx_priority_encoder_sm__DOT____Vcellout__genblk2__BRA__3__KET____DOT__vx_priority_encoder__index[1] = 0U; + __Vtable4_cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__vx_priority_encoder_sm__DOT____Vcellout__genblk2__BRA__3__KET____DOT__vx_priority_encoder__index[2] = 1U; + __Vtable4_cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__vx_priority_encoder_sm__DOT____Vcellout__genblk2__BRA__3__KET____DOT__vx_priority_encoder__index[3] = 0U; + __Vtable4_cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__vx_priority_encoder_sm__DOT____Vcellout__genblk2__BRA__3__KET____DOT__vx_priority_encoder__index[4] = 2U; + __Vtable4_cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__vx_priority_encoder_sm__DOT____Vcellout__genblk2__BRA__3__KET____DOT__vx_priority_encoder__index[5] = 0U; + __Vtable4_cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__vx_priority_encoder_sm__DOT____Vcellout__genblk2__BRA__3__KET____DOT__vx_priority_encoder__index[6] = 1U; + __Vtable4_cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__vx_priority_encoder_sm__DOT____Vcellout__genblk2__BRA__3__KET____DOT__vx_priority_encoder__index[7] = 0U; + __Vtable4_cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__vx_priority_encoder_sm__DOT____Vcellout__genblk2__BRA__3__KET____DOT__vx_priority_encoder__index[8] = 3U; + __Vtable4_cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__vx_priority_encoder_sm__DOT____Vcellout__genblk2__BRA__3__KET____DOT__vx_priority_encoder__index[9] = 0U; + __Vtable4_cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__vx_priority_encoder_sm__DOT____Vcellout__genblk2__BRA__3__KET____DOT__vx_priority_encoder__index[10] = 1U; + __Vtable4_cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__vx_priority_encoder_sm__DOT____Vcellout__genblk2__BRA__3__KET____DOT__vx_priority_encoder__index[11] = 0U; + __Vtable4_cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__vx_priority_encoder_sm__DOT____Vcellout__genblk2__BRA__3__KET____DOT__vx_priority_encoder__index[12] = 2U; + __Vtable4_cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__vx_priority_encoder_sm__DOT____Vcellout__genblk2__BRA__3__KET____DOT__vx_priority_encoder__index[13] = 0U; + __Vtable4_cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__vx_priority_encoder_sm__DOT____Vcellout__genblk2__BRA__3__KET____DOT__vx_priority_encoder__index[14] = 1U; + __Vtable4_cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__vx_priority_encoder_sm__DOT____Vcellout__genblk2__BRA__3__KET____DOT__vx_priority_encoder__index[15] = 0U; + __Vtable4_cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__vx_priority_encoder_sm__DOT____Vcellout__genblk2__BRA__3__KET____DOT__vx_priority_encoder__found[0] = 0U; + __Vtable4_cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__vx_priority_encoder_sm__DOT____Vcellout__genblk2__BRA__3__KET____DOT__vx_priority_encoder__found[1] = 1U; + __Vtable4_cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__vx_priority_encoder_sm__DOT____Vcellout__genblk2__BRA__3__KET____DOT__vx_priority_encoder__found[2] = 1U; + __Vtable4_cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__vx_priority_encoder_sm__DOT____Vcellout__genblk2__BRA__3__KET____DOT__vx_priority_encoder__found[3] = 1U; + __Vtable4_cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__vx_priority_encoder_sm__DOT____Vcellout__genblk2__BRA__3__KET____DOT__vx_priority_encoder__found[4] = 1U; + __Vtable4_cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__vx_priority_encoder_sm__DOT____Vcellout__genblk2__BRA__3__KET____DOT__vx_priority_encoder__found[5] = 1U; + __Vtable4_cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__vx_priority_encoder_sm__DOT____Vcellout__genblk2__BRA__3__KET____DOT__vx_priority_encoder__found[6] = 1U; + __Vtable4_cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__vx_priority_encoder_sm__DOT____Vcellout__genblk2__BRA__3__KET____DOT__vx_priority_encoder__found[7] = 1U; + __Vtable4_cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__vx_priority_encoder_sm__DOT____Vcellout__genblk2__BRA__3__KET____DOT__vx_priority_encoder__found[8] = 1U; + __Vtable4_cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__vx_priority_encoder_sm__DOT____Vcellout__genblk2__BRA__3__KET____DOT__vx_priority_encoder__found[9] = 1U; + __Vtable4_cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__vx_priority_encoder_sm__DOT____Vcellout__genblk2__BRA__3__KET____DOT__vx_priority_encoder__found[10] = 1U; + __Vtable4_cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__vx_priority_encoder_sm__DOT____Vcellout__genblk2__BRA__3__KET____DOT__vx_priority_encoder__found[11] = 1U; + __Vtable4_cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__vx_priority_encoder_sm__DOT____Vcellout__genblk2__BRA__3__KET____DOT__vx_priority_encoder__found[12] = 1U; + __Vtable4_cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__vx_priority_encoder_sm__DOT____Vcellout__genblk2__BRA__3__KET____DOT__vx_priority_encoder__found[13] = 1U; + __Vtable4_cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__vx_priority_encoder_sm__DOT____Vcellout__genblk2__BRA__3__KET____DOT__vx_priority_encoder__found[14] = 1U; + __Vtable4_cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__vx_priority_encoder_sm__DOT____Vcellout__genblk2__BRA__3__KET____DOT__vx_priority_encoder__found[15] = 1U; + __Vtable4_cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__vx_priority_encoder_sm__DOT__genblk2__BRA__3__KET____DOT__vx_priority_encoder__DOT__i[0] = 0xffffffffU; + __Vtable4_cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__vx_priority_encoder_sm__DOT__genblk2__BRA__3__KET____DOT__vx_priority_encoder__DOT__i[1] = 0xffffffffU; + __Vtable4_cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__vx_priority_encoder_sm__DOT__genblk2__BRA__3__KET____DOT__vx_priority_encoder__DOT__i[2] = 0xffffffffU; + __Vtable4_cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__vx_priority_encoder_sm__DOT__genblk2__BRA__3__KET____DOT__vx_priority_encoder__DOT__i[3] = 0xffffffffU; + __Vtable4_cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__vx_priority_encoder_sm__DOT__genblk2__BRA__3__KET____DOT__vx_priority_encoder__DOT__i[4] = 0xffffffffU; + __Vtable4_cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__vx_priority_encoder_sm__DOT__genblk2__BRA__3__KET____DOT__vx_priority_encoder__DOT__i[5] = 0xffffffffU; + __Vtable4_cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__vx_priority_encoder_sm__DOT__genblk2__BRA__3__KET____DOT__vx_priority_encoder__DOT__i[6] = 0xffffffffU; + __Vtable4_cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__vx_priority_encoder_sm__DOT__genblk2__BRA__3__KET____DOT__vx_priority_encoder__DOT__i[7] = 0xffffffffU; + __Vtable4_cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__vx_priority_encoder_sm__DOT__genblk2__BRA__3__KET____DOT__vx_priority_encoder__DOT__i[8] = 0xffffffffU; + __Vtable4_cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__vx_priority_encoder_sm__DOT__genblk2__BRA__3__KET____DOT__vx_priority_encoder__DOT__i[9] = 0xffffffffU; + __Vtable4_cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__vx_priority_encoder_sm__DOT__genblk2__BRA__3__KET____DOT__vx_priority_encoder__DOT__i[10] = 0xffffffffU; + __Vtable4_cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__vx_priority_encoder_sm__DOT__genblk2__BRA__3__KET____DOT__vx_priority_encoder__DOT__i[11] = 0xffffffffU; + __Vtable4_cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__vx_priority_encoder_sm__DOT__genblk2__BRA__3__KET____DOT__vx_priority_encoder__DOT__i[12] = 0xffffffffU; + __Vtable4_cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__vx_priority_encoder_sm__DOT__genblk2__BRA__3__KET____DOT__vx_priority_encoder__DOT__i[13] = 0xffffffffU; + __Vtable4_cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__vx_priority_encoder_sm__DOT__genblk2__BRA__3__KET____DOT__vx_priority_encoder__DOT__i[14] = 0xffffffffU; + __Vtable4_cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__vx_priority_encoder_sm__DOT__genblk2__BRA__3__KET____DOT__vx_priority_encoder__DOT__i[15] = 0xffffffffU; + __Vtableidx5 = 0; + __Vtable5_cache_simX__DOT__dmem_controller__DOT__dcache__DOT__miss_bank_index[0] = 0U; + __Vtable5_cache_simX__DOT__dmem_controller__DOT__dcache__DOT__miss_bank_index[1] = 0U; + __Vtable5_cache_simX__DOT__dmem_controller__DOT__dcache__DOT__miss_bank_index[2] = 1U; + __Vtable5_cache_simX__DOT__dmem_controller__DOT__dcache__DOT__miss_bank_index[3] = 0U; + __Vtable5_cache_simX__DOT__dmem_controller__DOT__dcache__DOT__miss_bank_index[4] = 2U; + __Vtable5_cache_simX__DOT__dmem_controller__DOT__dcache__DOT__miss_bank_index[5] = 0U; + __Vtable5_cache_simX__DOT__dmem_controller__DOT__dcache__DOT__miss_bank_index[6] = 1U; + __Vtable5_cache_simX__DOT__dmem_controller__DOT__dcache__DOT__miss_bank_index[7] = 0U; + __Vtable5_cache_simX__DOT__dmem_controller__DOT__dcache__DOT__miss_bank_index[8] = 3U; + __Vtable5_cache_simX__DOT__dmem_controller__DOT__dcache__DOT__miss_bank_index[9] = 0U; + __Vtable5_cache_simX__DOT__dmem_controller__DOT__dcache__DOT__miss_bank_index[10] = 1U; + __Vtable5_cache_simX__DOT__dmem_controller__DOT__dcache__DOT__miss_bank_index[11] = 0U; + __Vtable5_cache_simX__DOT__dmem_controller__DOT__dcache__DOT__miss_bank_index[12] = 2U; + __Vtable5_cache_simX__DOT__dmem_controller__DOT__dcache__DOT__miss_bank_index[13] = 0U; + __Vtable5_cache_simX__DOT__dmem_controller__DOT__dcache__DOT__miss_bank_index[14] = 1U; + __Vtable5_cache_simX__DOT__dmem_controller__DOT__dcache__DOT__miss_bank_index[15] = 0U; + __Vtable5_cache_simX__DOT__dmem_controller__DOT__dcache__DOT__miss_found[0] = 0U; + __Vtable5_cache_simX__DOT__dmem_controller__DOT__dcache__DOT__miss_found[1] = 1U; + __Vtable5_cache_simX__DOT__dmem_controller__DOT__dcache__DOT__miss_found[2] = 1U; + __Vtable5_cache_simX__DOT__dmem_controller__DOT__dcache__DOT__miss_found[3] = 1U; + __Vtable5_cache_simX__DOT__dmem_controller__DOT__dcache__DOT__miss_found[4] = 1U; + __Vtable5_cache_simX__DOT__dmem_controller__DOT__dcache__DOT__miss_found[5] = 1U; + __Vtable5_cache_simX__DOT__dmem_controller__DOT__dcache__DOT__miss_found[6] = 1U; + __Vtable5_cache_simX__DOT__dmem_controller__DOT__dcache__DOT__miss_found[7] = 1U; + __Vtable5_cache_simX__DOT__dmem_controller__DOT__dcache__DOT__miss_found[8] = 1U; + __Vtable5_cache_simX__DOT__dmem_controller__DOT__dcache__DOT__miss_found[9] = 1U; + __Vtable5_cache_simX__DOT__dmem_controller__DOT__dcache__DOT__miss_found[10] = 1U; + __Vtable5_cache_simX__DOT__dmem_controller__DOT__dcache__DOT__miss_found[11] = 1U; + __Vtable5_cache_simX__DOT__dmem_controller__DOT__dcache__DOT__miss_found[12] = 1U; + __Vtable5_cache_simX__DOT__dmem_controller__DOT__dcache__DOT__miss_found[13] = 1U; + __Vtable5_cache_simX__DOT__dmem_controller__DOT__dcache__DOT__miss_found[14] = 1U; + __Vtable5_cache_simX__DOT__dmem_controller__DOT__dcache__DOT__miss_found[15] = 1U; + __Vtable5_cache_simX__DOT__dmem_controller__DOT__dcache__DOT__get_miss_index__DOT__i[0] = 0xffffffffU; + __Vtable5_cache_simX__DOT__dmem_controller__DOT__dcache__DOT__get_miss_index__DOT__i[1] = 0xffffffffU; + __Vtable5_cache_simX__DOT__dmem_controller__DOT__dcache__DOT__get_miss_index__DOT__i[2] = 0xffffffffU; + __Vtable5_cache_simX__DOT__dmem_controller__DOT__dcache__DOT__get_miss_index__DOT__i[3] = 0xffffffffU; + __Vtable5_cache_simX__DOT__dmem_controller__DOT__dcache__DOT__get_miss_index__DOT__i[4] = 0xffffffffU; + __Vtable5_cache_simX__DOT__dmem_controller__DOT__dcache__DOT__get_miss_index__DOT__i[5] = 0xffffffffU; + __Vtable5_cache_simX__DOT__dmem_controller__DOT__dcache__DOT__get_miss_index__DOT__i[6] = 0xffffffffU; + __Vtable5_cache_simX__DOT__dmem_controller__DOT__dcache__DOT__get_miss_index__DOT__i[7] = 0xffffffffU; + __Vtable5_cache_simX__DOT__dmem_controller__DOT__dcache__DOT__get_miss_index__DOT__i[8] = 0xffffffffU; + __Vtable5_cache_simX__DOT__dmem_controller__DOT__dcache__DOT__get_miss_index__DOT__i[9] = 0xffffffffU; + __Vtable5_cache_simX__DOT__dmem_controller__DOT__dcache__DOT__get_miss_index__DOT__i[10] = 0xffffffffU; + __Vtable5_cache_simX__DOT__dmem_controller__DOT__dcache__DOT__get_miss_index__DOT__i[11] = 0xffffffffU; + __Vtable5_cache_simX__DOT__dmem_controller__DOT__dcache__DOT__get_miss_index__DOT__i[12] = 0xffffffffU; + __Vtable5_cache_simX__DOT__dmem_controller__DOT__dcache__DOT__get_miss_index__DOT__i[13] = 0xffffffffU; + __Vtable5_cache_simX__DOT__dmem_controller__DOT__dcache__DOT__get_miss_index__DOT__i[14] = 0xffffffffU; + __Vtable5_cache_simX__DOT__dmem_controller__DOT__dcache__DOT__get_miss_index__DOT__i[15] = 0xffffffffU; + __Vtableidx6 = 0; + __Vtable6_cache_simX__DOT__dmem_controller__DOT__dcache__DOT____Vcellout__genblk1__BRA__0__KET____DOT__choose_thread__index[0] = 0U; + __Vtable6_cache_simX__DOT__dmem_controller__DOT__dcache__DOT____Vcellout__genblk1__BRA__0__KET____DOT__choose_thread__index[1] = 0U; + __Vtable6_cache_simX__DOT__dmem_controller__DOT__dcache__DOT____Vcellout__genblk1__BRA__0__KET____DOT__choose_thread__index[2] = 1U; + __Vtable6_cache_simX__DOT__dmem_controller__DOT__dcache__DOT____Vcellout__genblk1__BRA__0__KET____DOT__choose_thread__index[3] = 1U; + __Vtable6_cache_simX__DOT__dmem_controller__DOT__dcache__DOT____Vcellout__genblk1__BRA__0__KET____DOT__choose_thread__index[4] = 2U; + __Vtable6_cache_simX__DOT__dmem_controller__DOT__dcache__DOT____Vcellout__genblk1__BRA__0__KET____DOT__choose_thread__index[5] = 2U; + __Vtable6_cache_simX__DOT__dmem_controller__DOT__dcache__DOT____Vcellout__genblk1__BRA__0__KET____DOT__choose_thread__index[6] = 2U; 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+ __Vtable8_cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk1__BRA__2__KET____DOT__choose_thread__DOT__i[1] = 4U; + __Vtable8_cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk1__BRA__2__KET____DOT__choose_thread__DOT__i[2] = 4U; + __Vtable8_cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk1__BRA__2__KET____DOT__choose_thread__DOT__i[3] = 4U; + __Vtable8_cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk1__BRA__2__KET____DOT__choose_thread__DOT__i[4] = 4U; + __Vtable8_cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk1__BRA__2__KET____DOT__choose_thread__DOT__i[5] = 4U; + __Vtable8_cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk1__BRA__2__KET____DOT__choose_thread__DOT__i[6] = 4U; + __Vtable8_cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk1__BRA__2__KET____DOT__choose_thread__DOT__i[7] = 4U; + __Vtable8_cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk1__BRA__2__KET____DOT__choose_thread__DOT__i[8] = 4U; + __Vtable8_cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk1__BRA__2__KET____DOT__choose_thread__DOT__i[9] = 4U; + __Vtable8_cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk1__BRA__2__KET____DOT__choose_thread__DOT__i[10] = 4U; + __Vtable8_cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk1__BRA__2__KET____DOT__choose_thread__DOT__i[11] = 4U; + __Vtable8_cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk1__BRA__2__KET____DOT__choose_thread__DOT__i[12] = 4U; + __Vtable8_cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk1__BRA__2__KET____DOT__choose_thread__DOT__i[13] = 4U; + __Vtable8_cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk1__BRA__2__KET____DOT__choose_thread__DOT__i[14] = 4U; + __Vtable8_cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk1__BRA__2__KET____DOT__choose_thread__DOT__i[15] = 4U; + __Vtableidx9 = 0; + __Vtable9_cache_simX__DOT__dmem_controller__DOT__dcache__DOT____Vcellout__genblk1__BRA__3__KET____DOT__choose_thread__index[0] = 0U; + __Vtable9_cache_simX__DOT__dmem_controller__DOT__dcache__DOT____Vcellout__genblk1__BRA__3__KET____DOT__choose_thread__index[1] = 0U; + __Vtable9_cache_simX__DOT__dmem_controller__DOT__dcache__DOT____Vcellout__genblk1__BRA__3__KET____DOT__choose_thread__index[2] = 1U; + __Vtable9_cache_simX__DOT__dmem_controller__DOT__dcache__DOT____Vcellout__genblk1__BRA__3__KET____DOT__choose_thread__index[3] = 1U; + __Vtable9_cache_simX__DOT__dmem_controller__DOT__dcache__DOT____Vcellout__genblk1__BRA__3__KET____DOT__choose_thread__index[4] = 2U; + __Vtable9_cache_simX__DOT__dmem_controller__DOT__dcache__DOT____Vcellout__genblk1__BRA__3__KET____DOT__choose_thread__index[5] = 2U; + __Vtable9_cache_simX__DOT__dmem_controller__DOT__dcache__DOT____Vcellout__genblk1__BRA__3__KET____DOT__choose_thread__index[6] = 2U; + __Vtable9_cache_simX__DOT__dmem_controller__DOT__dcache__DOT____Vcellout__genblk1__BRA__3__KET____DOT__choose_thread__index[7] = 2U; + __Vtable9_cache_simX__DOT__dmem_controller__DOT__dcache__DOT____Vcellout__genblk1__BRA__3__KET____DOT__choose_thread__index[8] = 3U; + __Vtable9_cache_simX__DOT__dmem_controller__DOT__dcache__DOT____Vcellout__genblk1__BRA__3__KET____DOT__choose_thread__index[9] = 3U; + __Vtable9_cache_simX__DOT__dmem_controller__DOT__dcache__DOT____Vcellout__genblk1__BRA__3__KET____DOT__choose_thread__index[10] = 3U; + __Vtable9_cache_simX__DOT__dmem_controller__DOT__dcache__DOT____Vcellout__genblk1__BRA__3__KET____DOT__choose_thread__index[11] = 3U; + __Vtable9_cache_simX__DOT__dmem_controller__DOT__dcache__DOT____Vcellout__genblk1__BRA__3__KET____DOT__choose_thread__index[12] = 3U; + __Vtable9_cache_simX__DOT__dmem_controller__DOT__dcache__DOT____Vcellout__genblk1__BRA__3__KET____DOT__choose_thread__index[13] = 3U; + __Vtable9_cache_simX__DOT__dmem_controller__DOT__dcache__DOT____Vcellout__genblk1__BRA__3__KET____DOT__choose_thread__index[14] = 3U; + __Vtable9_cache_simX__DOT__dmem_controller__DOT__dcache__DOT____Vcellout__genblk1__BRA__3__KET____DOT__choose_thread__index[15] = 3U; + __Vtable9_cache_simX__DOT__dmem_controller__DOT__dcache__DOT____Vcellout__genblk1__BRA__3__KET____DOT__choose_thread__found[0] = 0U; + __Vtable9_cache_simX__DOT__dmem_controller__DOT__dcache__DOT____Vcellout__genblk1__BRA__3__KET____DOT__choose_thread__found[1] = 1U; + __Vtable9_cache_simX__DOT__dmem_controller__DOT__dcache__DOT____Vcellout__genblk1__BRA__3__KET____DOT__choose_thread__found[2] = 1U; + __Vtable9_cache_simX__DOT__dmem_controller__DOT__dcache__DOT____Vcellout__genblk1__BRA__3__KET____DOT__choose_thread__found[3] = 1U; + __Vtable9_cache_simX__DOT__dmem_controller__DOT__dcache__DOT____Vcellout__genblk1__BRA__3__KET____DOT__choose_thread__found[4] = 1U; + __Vtable9_cache_simX__DOT__dmem_controller__DOT__dcache__DOT____Vcellout__genblk1__BRA__3__KET____DOT__choose_thread__found[5] = 1U; + __Vtable9_cache_simX__DOT__dmem_controller__DOT__dcache__DOT____Vcellout__genblk1__BRA__3__KET____DOT__choose_thread__found[6] = 1U; + __Vtable9_cache_simX__DOT__dmem_controller__DOT__dcache__DOT____Vcellout__genblk1__BRA__3__KET____DOT__choose_thread__found[7] = 1U; + __Vtable9_cache_simX__DOT__dmem_controller__DOT__dcache__DOT____Vcellout__genblk1__BRA__3__KET____DOT__choose_thread__found[8] = 1U; + __Vtable9_cache_simX__DOT__dmem_controller__DOT__dcache__DOT____Vcellout__genblk1__BRA__3__KET____DOT__choose_thread__found[9] = 1U; + __Vtable9_cache_simX__DOT__dmem_controller__DOT__dcache__DOT____Vcellout__genblk1__BRA__3__KET____DOT__choose_thread__found[10] = 1U; + __Vtable9_cache_simX__DOT__dmem_controller__DOT__dcache__DOT____Vcellout__genblk1__BRA__3__KET____DOT__choose_thread__found[11] = 1U; + __Vtable9_cache_simX__DOT__dmem_controller__DOT__dcache__DOT____Vcellout__genblk1__BRA__3__KET____DOT__choose_thread__found[12] = 1U; + __Vtable9_cache_simX__DOT__dmem_controller__DOT__dcache__DOT____Vcellout__genblk1__BRA__3__KET____DOT__choose_thread__found[13] = 1U; + __Vtable9_cache_simX__DOT__dmem_controller__DOT__dcache__DOT____Vcellout__genblk1__BRA__3__KET____DOT__choose_thread__found[14] = 1U; + __Vtable9_cache_simX__DOT__dmem_controller__DOT__dcache__DOT____Vcellout__genblk1__BRA__3__KET____DOT__choose_thread__found[15] = 1U; + __Vtable9_cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk1__BRA__3__KET____DOT__choose_thread__DOT__i[0] = 4U; + __Vtable9_cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk1__BRA__3__KET____DOT__choose_thread__DOT__i[1] = 4U; + __Vtable9_cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk1__BRA__3__KET____DOT__choose_thread__DOT__i[2] = 4U; + __Vtable9_cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk1__BRA__3__KET____DOT__choose_thread__DOT__i[3] = 4U; + __Vtable9_cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk1__BRA__3__KET____DOT__choose_thread__DOT__i[4] = 4U; + __Vtable9_cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk1__BRA__3__KET____DOT__choose_thread__DOT__i[5] = 4U; + __Vtable9_cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk1__BRA__3__KET____DOT__choose_thread__DOT__i[6] = 4U; + __Vtable9_cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk1__BRA__3__KET____DOT__choose_thread__DOT__i[7] = 4U; + __Vtable9_cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk1__BRA__3__KET____DOT__choose_thread__DOT__i[8] = 4U; + __Vtable9_cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk1__BRA__3__KET____DOT__choose_thread__DOT__i[9] = 4U; + __Vtable9_cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk1__BRA__3__KET____DOT__choose_thread__DOT__i[10] = 4U; + __Vtable9_cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk1__BRA__3__KET____DOT__choose_thread__DOT__i[11] = 4U; + __Vtable9_cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk1__BRA__3__KET____DOT__choose_thread__DOT__i[12] = 4U; + __Vtable9_cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk1__BRA__3__KET____DOT__choose_thread__DOT__i[13] = 4U; + __Vtable9_cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk1__BRA__3__KET____DOT__choose_thread__DOT__i[14] = 4U; + __Vtable9_cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk1__BRA__3__KET____DOT__choose_thread__DOT__i[15] = 4U; + __Vm_traceActivity = 0; +} diff --git a/simX/obj_dir/Vcache_simX.h b/simX/obj_dir/Vcache_simX.h new file mode 100644 index 00000000..813fdee5 --- /dev/null +++ b/simX/obj_dir/Vcache_simX.h @@ -0,0 +1,332 @@ +// Verilated -*- C++ -*- +// DESCRIPTION: Verilator output: Primary design header +// +// This header should be included by all source files instantiating the design. +// The class here is then constructed to instantiate the design. +// See the Verilator manual for examples. + +#ifndef _Vcache_simX_H_ +#define _Vcache_simX_H_ + +#include "verilated.h" + +class Vcache_simX__Syms; +class Vcache_simX_VX_dram_req_rsp_inter__N1_NB4; +class Vcache_simX_VX_dcache_request_inter; +class Vcache_simX_VX_dram_req_rsp_inter__N4_NB4; +class Vcache_simX_VX_Cache_Bank__pi7; +class VerilatedVcd; + +//---------- + +VL_MODULE(Vcache_simX) { + public: + // CELLS + // Public to allow access to /*verilator_public*/ items; + // otherwise the application code can consider these internals. + Vcache_simX_VX_dram_req_rsp_inter__N1_NB4* __PVT__cache_simX__DOT__VX_dram_req_rsp_icache; + Vcache_simX_VX_dcache_request_inter* __PVT__cache_simX__DOT__VX_dcache_req; + Vcache_simX_VX_dram_req_rsp_inter__N4_NB4* __PVT__cache_simX__DOT__VX_dram_req_rsp; + Vcache_simX_VX_Cache_Bank__pi7* __PVT__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__0__KET____DOT__bank_structure; + Vcache_simX_VX_Cache_Bank__pi7* __PVT__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__1__KET____DOT__bank_structure; + Vcache_simX_VX_Cache_Bank__pi7* __PVT__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__2__KET____DOT__bank_structure; + Vcache_simX_VX_Cache_Bank__pi7* __PVT__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__3__KET____DOT__bank_structure; + + // PORTS + // The application code writes and reads these signals to + // propagate new values into/out from the Verilated model. + VL_IN8(clk,0,0); + VL_IN8(reset,0,0); + VL_IN8(in_icache_valid_pc_addr,0,0); + VL_OUT8(out_icache_stall,0,0); + VL_IN8(in_dcache_mem_read,2,0); + VL_IN8(in_dcache_mem_write,2,0); + VL_OUT8(out_dcache_stall,0,0); + VL_IN(in_icache_pc_addr,31,0); + VL_IN8(in_dcache_in_valid[4],0,0); + VL_IN(in_dcache_in_address[4],31,0); + + // LOCAL SIGNALS + // Internals; generally not touched by application code + // Anonymous structures to workaround compiler member-count bugs + struct { + CData/*0:0*/ cache_simX__DOT__icache_i_m_ready; + CData/*0:0*/ cache_simX__DOT__dcache_i_m_ready; + CData/*3:0*/ cache_simX__DOT__dmem_controller__DOT__sm_driver_in_valid; + CData/*3:0*/ cache_simX__DOT__dmem_controller__DOT__cache_driver_in_valid; + CData/*0:0*/ cache_simX__DOT__dmem_controller__DOT__read_or_write; + CData/*2:0*/ cache_simX__DOT__dmem_controller__DOT__cache_driver_in_mem_read; + CData/*2:0*/ cache_simX__DOT__dmem_controller__DOT__cache_driver_in_mem_write; + CData/*2:0*/ cache_simX__DOT__dmem_controller__DOT__sm_driver_in_mem_read; + CData/*2:0*/ cache_simX__DOT__dmem_controller__DOT__sm_driver_in_mem_write; + CData/*2:0*/ cache_simX__DOT__dmem_controller__DOT__icache_driver_in_mem_read; + CData/*3:0*/ cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__temp_out_valid; + IData/*6:0*/ cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__block_addr; + CData/*1:0*/ cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__block_we; + CData/*3:0*/ cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__orig_in_valid; + CData/*0:0*/ cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__genblk2__BRA__0__KET____DOT__shm_write; + CData/*0:0*/ cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__genblk2__BRA__1__KET____DOT__shm_write; + CData/*0:0*/ cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__genblk2__BRA__2__KET____DOT__shm_write; + CData/*0:0*/ cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__genblk2__BRA__3__KET____DOT__shm_write; + CData/*3:0*/ cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__vx_priority_encoder_sm__DOT__left_requests; + CData/*3:0*/ cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__vx_priority_encoder_sm__DOT__serviced; + CData/*3:0*/ cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__vx_priority_encoder_sm__DOT__use_valid; + CData/*3:0*/ cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__vx_priority_encoder_sm__DOT__more_than_one_valid; + CData/*1:0*/ cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__vx_priority_encoder_sm__DOT__internal_req_num; + CData/*3:0*/ cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__vx_priority_encoder_sm__DOT__internal_out_valid; + CData/*3:0*/ cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__vx_priority_encoder_sm__DOT__serviced_qual; + CData/*3:0*/ cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__vx_priority_encoder_sm__DOT__new_left_requests; + CData/*2:0*/ cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__vx_priority_encoder_sm__DOT__genblk1__BRA__0__KET____DOT__num_valids; + CData/*2:0*/ cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__vx_priority_encoder_sm__DOT__genblk1__BRA__1__KET____DOT__num_valids; + CData/*2:0*/ cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__vx_priority_encoder_sm__DOT__genblk1__BRA__2__KET____DOT__num_valids; + CData/*2:0*/ cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__vx_priority_encoder_sm__DOT__genblk1__BRA__3__KET____DOT__num_valids; + CData/*0:0*/ cache_simX__DOT__dmem_controller__DOT__dcache__DOT__global_way_to_evict; + CData/*1:0*/ cache_simX__DOT__dmem_controller__DOT__dcache__DOT__index_per_bank; + SData/*3:0*/ cache_simX__DOT__dmem_controller__DOT__dcache__DOT__use_mask_per_bank; + CData/*3:0*/ cache_simX__DOT__dmem_controller__DOT__dcache__DOT__valid_per_bank; + SData/*3:0*/ cache_simX__DOT__dmem_controller__DOT__dcache__DOT__threads_serviced_per_bank; + CData/*3:0*/ cache_simX__DOT__dmem_controller__DOT__dcache__DOT__hit_per_bank; + CData/*3:0*/ cache_simX__DOT__dmem_controller__DOT__dcache__DOT__eviction_wb; + CData/*3:0*/ cache_simX__DOT__dmem_controller__DOT__dcache__DOT__eviction_wb_old; + CData/*3:0*/ cache_simX__DOT__dmem_controller__DOT__dcache__DOT__state; + CData/*3:0*/ cache_simX__DOT__dmem_controller__DOT__dcache__DOT__new_state; + CData/*3:0*/ cache_simX__DOT__dmem_controller__DOT__dcache__DOT__use_valid; + CData/*3:0*/ cache_simX__DOT__dmem_controller__DOT__dcache__DOT__stored_valid; + CData/*3:0*/ cache_simX__DOT__dmem_controller__DOT__dcache__DOT__new_stored_valid; + CData/*3:0*/ cache_simX__DOT__dmem_controller__DOT__dcache__DOT__threads_serviced_Qual; + CData/*3:0*/ cache_simX__DOT__dmem_controller__DOT__dcache__DOT__detect_bank_miss; + CData/*1:0*/ cache_simX__DOT__dmem_controller__DOT__dcache__DOT__miss_bank_index; + CData/*0:0*/ cache_simX__DOT__dmem_controller__DOT__dcache__DOT__miss_found; + CData/*0:0*/ cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__0__KET____DOT__use_valid_in; + CData/*0:0*/ cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__1__KET____DOT__use_valid_in; + CData/*0:0*/ cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__2__KET____DOT__use_valid_in; + CData/*0:0*/ cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__3__KET____DOT__use_valid_in; + CData/*0:0*/ cache_simX__DOT__dmem_controller__DOT__icache__DOT__global_way_to_evict; + CData/*0:0*/ cache_simX__DOT__dmem_controller__DOT__icache__DOT__valid_per_bank; + CData/*0:0*/ cache_simX__DOT__dmem_controller__DOT__icache__DOT__threads_serviced_per_bank; + CData/*0:0*/ cache_simX__DOT__dmem_controller__DOT__icache__DOT__hit_per_bank; + CData/*0:0*/ cache_simX__DOT__dmem_controller__DOT__icache__DOT__eviction_wb_old; + CData/*3:0*/ cache_simX__DOT__dmem_controller__DOT__icache__DOT__state; + CData/*3:0*/ cache_simX__DOT__dmem_controller__DOT__icache__DOT__new_state; + CData/*0:0*/ cache_simX__DOT__dmem_controller__DOT__icache__DOT__use_valid; + CData/*0:0*/ cache_simX__DOT__dmem_controller__DOT__icache__DOT__stored_valid; + CData/*0:0*/ cache_simX__DOT__dmem_controller__DOT__icache__DOT__new_stored_valid; + CData/*0:0*/ cache_simX__DOT__dmem_controller__DOT__icache__DOT__detect_bank_miss; + CData/*0:0*/ cache_simX__DOT__dmem_controller__DOT__icache__DOT__miss_bank_index; + CData/*0:0*/ cache_simX__DOT__dmem_controller__DOT__icache__DOT__miss_found; + }; + struct { + CData/*0:0*/ cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__use_valid_in; + CData/*0:0*/ cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__valid_use; + CData/*0:0*/ cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__access; + CData/*0:0*/ cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__write_from_mem; + CData/*0:0*/ cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__way_to_update; + CData/*3:0*/ cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__sb_mask; + SData/*3:0*/ cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__we; + CData/*1:0*/ cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__data_structures__DOT__valid_use_per_way; + CData/*1:0*/ cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__data_structures__DOT__dirty_use_per_way; + CData/*1:0*/ cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__data_structures__DOT__hit_per_way; + IData/*3:0*/ cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__data_structures__DOT__we_per_way; + CData/*1:0*/ cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__data_structures__DOT__write_from_mem_per_way; + CData/*0:0*/ cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__data_structures__DOT__invalid_found; + CData/*0:0*/ cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__data_structures__DOT__way_index; + CData/*0:0*/ cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__data_structures__DOT__invalid_index; + CData/*0:0*/ cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__data_structures__DOT__way_use_Qual; + CData/*0:0*/ cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__data_structures__DOT__genblk1__DOT__way_indexing__DOT__found; + WData/*31:0*/ cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__temp_out_data[4]; + WData/*31:0*/ cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__block_wdata[16]; + WData/*31:0*/ cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__block_rdata[16]; + IData/*31:0*/ cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__vx_priority_encoder_sm__DOT__genblk2__BRA__0__KET____DOT__vx_priority_encoder__DOT__i; + IData/*31:0*/ cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__vx_priority_encoder_sm__DOT__genblk2__BRA__1__KET____DOT__vx_priority_encoder__DOT__i; + IData/*31:0*/ cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__vx_priority_encoder_sm__DOT__genblk2__BRA__2__KET____DOT__vx_priority_encoder__DOT__i; + IData/*31:0*/ cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__vx_priority_encoder_sm__DOT__genblk2__BRA__3__KET____DOT__vx_priority_encoder__DOT__i; + IData/*31:0*/ cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__genblk2__BRA__0__KET____DOT__vx_shared_memory_block__DOT__curr_ind; + IData/*31:0*/ cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__genblk2__BRA__1__KET____DOT__vx_shared_memory_block__DOT__curr_ind; + IData/*31:0*/ cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__genblk2__BRA__2__KET____DOT__vx_shared_memory_block__DOT__curr_ind; + IData/*31:0*/ cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__genblk2__BRA__3__KET____DOT__vx_shared_memory_block__DOT__curr_ind; + WData/*31:0*/ cache_simX__DOT__dmem_controller__DOT__dcache__DOT__final_data_read[4]; + WData/*31:0*/ cache_simX__DOT__dmem_controller__DOT__dcache__DOT__new_final_data_read[4]; + WData/*31:0*/ cache_simX__DOT__dmem_controller__DOT__dcache__DOT__new_final_data_read_Qual[4]; + WData/*31:0*/ cache_simX__DOT__dmem_controller__DOT__dcache__DOT__readdata_per_bank[4]; + WData/*31:0*/ cache_simX__DOT__dmem_controller__DOT__dcache__DOT__eviction_addr_per_bank[4]; + IData/*31:0*/ cache_simX__DOT__dmem_controller__DOT__dcache__DOT__miss_addr; + IData/*31:0*/ cache_simX__DOT__dmem_controller__DOT__dcache__DOT__init_b; + IData/*31:0*/ cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__0__KET____DOT__bank_addr; + IData/*31:0*/ cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__1__KET____DOT__bank_addr; + IData/*31:0*/ cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__2__KET____DOT__bank_addr; + IData/*31:0*/ cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__3__KET____DOT__bank_addr; + IData/*31:0*/ cache_simX__DOT__dmem_controller__DOT__dcache__DOT__get_miss_index__DOT__i; + IData/*31:0*/ cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk1__BRA__0__KET____DOT__choose_thread__DOT__i; + IData/*31:0*/ cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk1__BRA__1__KET____DOT__choose_thread__DOT__i; + IData/*31:0*/ cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk1__BRA__2__KET____DOT__choose_thread__DOT__i; + IData/*31:0*/ cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk1__BRA__3__KET____DOT__choose_thread__DOT__i; + IData/*31:0*/ cache_simX__DOT__dmem_controller__DOT__icache__DOT__final_data_read; + IData/*31:0*/ cache_simX__DOT__dmem_controller__DOT__icache__DOT__new_final_data_read; + IData/*31:0*/ cache_simX__DOT__dmem_controller__DOT__icache__DOT__new_final_data_read_Qual; + IData/*31:0*/ cache_simX__DOT__dmem_controller__DOT__icache__DOT__miss_addr; + IData/*31:0*/ cache_simX__DOT__dmem_controller__DOT__icache__DOT__init_b; + IData/*31:0*/ cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_addr; + IData/*22:0*/ cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__tag_use; + IData/*31:0*/ cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__data_unQual; + WData/*31:0*/ cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__data_write[4]; + QData/*22:0*/ cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__data_structures__DOT__tag_use_per_way; + WData/*31:0*/ cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__data_structures__DOT__data_use_per_way[8]; + WData/*31:0*/ cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__data_structures__DOT__data_write_per_way[8]; + IData/*31:0*/ cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__f; + IData/*31:0*/ cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__ini_ind; + IData/*31:0*/ cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__data_structures__DOT__each_way__BRA__1__KET____DOT__data_structures__DOT__f; + IData/*31:0*/ cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__data_structures__DOT__each_way__BRA__1__KET____DOT__data_structures__DOT__ini_ind; + WData/*31:0*/ cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__genblk2__BRA__0__KET____DOT__vx_shared_memory_block__DOT__shared_memory[128][4]; + WData/*31:0*/ cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__genblk2__BRA__1__KET____DOT__vx_shared_memory_block__DOT__shared_memory[128][4]; + WData/*31:0*/ cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__genblk2__BRA__2__KET____DOT__vx_shared_memory_block__DOT__shared_memory[128][4]; + WData/*31:0*/ cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__genblk2__BRA__3__KET____DOT__vx_shared_memory_block__DOT__shared_memory[128][4]; + }; + struct { + CData/*3:0*/ cache_simX__DOT__dmem_controller__DOT__dcache__DOT__debug_hit_per_bank_mask[4]; + CData/*0:0*/ cache_simX__DOT__dmem_controller__DOT__icache__DOT__debug_hit_per_bank_mask[1]; + WData/*7:0*/ cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__data[32][4]; + IData/*22:0*/ cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__tag[32]; + CData/*0:0*/ cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__valid[32]; + CData/*0:0*/ cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__dirty[32]; + WData/*7:0*/ cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__data_structures__DOT__each_way__BRA__1__KET____DOT__data_structures__DOT__data[32][4]; + IData/*22:0*/ cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__data_structures__DOT__each_way__BRA__1__KET____DOT__data_structures__DOT__tag[32]; + CData/*0:0*/ cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__data_structures__DOT__each_way__BRA__1__KET____DOT__data_structures__DOT__valid[32]; + CData/*0:0*/ cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__data_structures__DOT__each_way__BRA__1__KET____DOT__data_structures__DOT__dirty[32]; + }; + + // LOCAL VARIABLES + // Internals; generally not touched by application code + CData/*6:0*/ cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT____Vlvbound1; + CData/*6:0*/ cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT____Vlvbound2; + SData/*3:0*/ cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__vx_priority_encoder_sm__DOT____Vcellout__vx_bank_valid__bank_valids; + CData/*0:0*/ cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__vx_priority_encoder_sm__DOT____Vcellout__genblk2__BRA__0__KET____DOT__vx_priority_encoder__found; + CData/*1:0*/ cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__vx_priority_encoder_sm__DOT____Vcellout__genblk2__BRA__0__KET____DOT__vx_priority_encoder__index; + CData/*0:0*/ cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__vx_priority_encoder_sm__DOT____Vcellout__genblk2__BRA__1__KET____DOT__vx_priority_encoder__found; + CData/*1:0*/ cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__vx_priority_encoder_sm__DOT____Vcellout__genblk2__BRA__1__KET____DOT__vx_priority_encoder__index; + CData/*0:0*/ cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__vx_priority_encoder_sm__DOT____Vcellout__genblk2__BRA__2__KET____DOT__vx_priority_encoder__found; + CData/*1:0*/ cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__vx_priority_encoder_sm__DOT____Vcellout__genblk2__BRA__2__KET____DOT__vx_priority_encoder__index; + CData/*0:0*/ cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__vx_priority_encoder_sm__DOT____Vcellout__genblk2__BRA__3__KET____DOT__vx_priority_encoder__found; + CData/*1:0*/ cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__vx_priority_encoder_sm__DOT____Vcellout__genblk2__BRA__3__KET____DOT__vx_priority_encoder__index; + SData/*3:0*/ cache_simX__DOT__dmem_controller__DOT__dcache__DOT____Vcellout__multip_banks__thread_track_banks; + CData/*0:0*/ cache_simX__DOT__dmem_controller__DOT__dcache__DOT____Vcellout__genblk1__BRA__0__KET____DOT__choose_thread__found; + CData/*1:0*/ cache_simX__DOT__dmem_controller__DOT__dcache__DOT____Vcellout__genblk1__BRA__0__KET____DOT__choose_thread__index; + CData/*0:0*/ cache_simX__DOT__dmem_controller__DOT__dcache__DOT____Vcellout__genblk1__BRA__1__KET____DOT__choose_thread__found; + CData/*1:0*/ cache_simX__DOT__dmem_controller__DOT__dcache__DOT____Vcellout__genblk1__BRA__1__KET____DOT__choose_thread__index; + CData/*0:0*/ cache_simX__DOT__dmem_controller__DOT__dcache__DOT____Vcellout__genblk1__BRA__2__KET____DOT__choose_thread__found; + CData/*1:0*/ cache_simX__DOT__dmem_controller__DOT__dcache__DOT____Vcellout__genblk1__BRA__2__KET____DOT__choose_thread__index; + CData/*0:0*/ cache_simX__DOT__dmem_controller__DOT__dcache__DOT____Vcellout__genblk1__BRA__3__KET____DOT__choose_thread__found; + CData/*1:0*/ cache_simX__DOT__dmem_controller__DOT__dcache__DOT____Vcellout__genblk1__BRA__3__KET____DOT__choose_thread__index; + CData/*0:0*/ cache_simX__DOT__dmem_controller__DOT__icache__DOT____Vcellout__multip_banks__thread_track_banks; + CData/*0:0*/ cache_simX__DOT__dmem_controller__DOT__icache__DOT____Vcellout__genblk1__BRA__0__KET____DOT__choose_thread__index; + CData/*0:0*/ cache_simX__DOT__dmem_controller__DOT__icache__DOT__multip_banks__DOT____Vlvbound1; + CData/*0:0*/ cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__data_structures__DOT____Vcellout__each_way__BRA__0__KET____DOT__data_structures__dirty_use; + CData/*0:0*/ cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__data_structures__DOT____Vcellout__each_way__BRA__1__KET____DOT__data_structures__dirty_use; + CData/*3:0*/ __Vtableidx1; + CData/*3:0*/ __Vtableidx2; + CData/*3:0*/ __Vtableidx3; + CData/*3:0*/ __Vtableidx4; + CData/*3:0*/ __Vtableidx5; + CData/*3:0*/ __Vtableidx6; + CData/*3:0*/ __Vtableidx7; + CData/*3:0*/ __Vtableidx8; + CData/*3:0*/ __Vtableidx9; + CData/*0:0*/ __Vclklast__TOP__clk; + CData/*0:0*/ __Vclklast__TOP__reset; + WData/*31:0*/ cache_simX__DOT__dmem_controller__DOT____Vcellout__dcache__o_m_writedata[16]; + WData/*31:0*/ cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT____Vcellout__vx_priority_encoder_sm__out_data[4]; + WData/*31:0*/ cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT____Vcellout__vx_priority_encoder_sm__out_address[4]; + IData/*31:0*/ __Vm_traceActivity; + static CData/*1:0*/ __Vtable1_cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__vx_priority_encoder_sm__DOT____Vcellout__genblk2__BRA__0__KET____DOT__vx_priority_encoder__index[16]; + static CData/*0:0*/ __Vtable1_cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__vx_priority_encoder_sm__DOT____Vcellout__genblk2__BRA__0__KET____DOT__vx_priority_encoder__found[16]; + static IData/*31:0*/ __Vtable1_cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__vx_priority_encoder_sm__DOT__genblk2__BRA__0__KET____DOT__vx_priority_encoder__DOT__i[16]; + static CData/*1:0*/ __Vtable2_cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__vx_priority_encoder_sm__DOT____Vcellout__genblk2__BRA__1__KET____DOT__vx_priority_encoder__index[16]; + static CData/*0:0*/ __Vtable2_cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__vx_priority_encoder_sm__DOT____Vcellout__genblk2__BRA__1__KET____DOT__vx_priority_encoder__found[16]; + static IData/*31:0*/ __Vtable2_cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__vx_priority_encoder_sm__DOT__genblk2__BRA__1__KET____DOT__vx_priority_encoder__DOT__i[16]; + static CData/*1:0*/ __Vtable3_cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__vx_priority_encoder_sm__DOT____Vcellout__genblk2__BRA__2__KET____DOT__vx_priority_encoder__index[16]; + static CData/*0:0*/ __Vtable3_cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__vx_priority_encoder_sm__DOT____Vcellout__genblk2__BRA__2__KET____DOT__vx_priority_encoder__found[16]; + static IData/*31:0*/ __Vtable3_cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__vx_priority_encoder_sm__DOT__genblk2__BRA__2__KET____DOT__vx_priority_encoder__DOT__i[16]; + static CData/*1:0*/ __Vtable4_cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__vx_priority_encoder_sm__DOT____Vcellout__genblk2__BRA__3__KET____DOT__vx_priority_encoder__index[16]; + static CData/*0:0*/ __Vtable4_cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__vx_priority_encoder_sm__DOT____Vcellout__genblk2__BRA__3__KET____DOT__vx_priority_encoder__found[16]; + static IData/*31:0*/ __Vtable4_cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__vx_priority_encoder_sm__DOT__genblk2__BRA__3__KET____DOT__vx_priority_encoder__DOT__i[16]; + static CData/*1:0*/ __Vtable5_cache_simX__DOT__dmem_controller__DOT__dcache__DOT__miss_bank_index[16]; + static CData/*0:0*/ __Vtable5_cache_simX__DOT__dmem_controller__DOT__dcache__DOT__miss_found[16]; + static IData/*31:0*/ __Vtable5_cache_simX__DOT__dmem_controller__DOT__dcache__DOT__get_miss_index__DOT__i[16]; + static CData/*1:0*/ __Vtable6_cache_simX__DOT__dmem_controller__DOT__dcache__DOT____Vcellout__genblk1__BRA__0__KET____DOT__choose_thread__index[16]; + static CData/*0:0*/ __Vtable6_cache_simX__DOT__dmem_controller__DOT__dcache__DOT____Vcellout__genblk1__BRA__0__KET____DOT__choose_thread__found[16]; + static IData/*31:0*/ __Vtable6_cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk1__BRA__0__KET____DOT__choose_thread__DOT__i[16]; + static CData/*1:0*/ __Vtable7_cache_simX__DOT__dmem_controller__DOT__dcache__DOT____Vcellout__genblk1__BRA__1__KET____DOT__choose_thread__index[16]; + static CData/*0:0*/ __Vtable7_cache_simX__DOT__dmem_controller__DOT__dcache__DOT____Vcellout__genblk1__BRA__1__KET____DOT__choose_thread__found[16]; + static IData/*31:0*/ __Vtable7_cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk1__BRA__1__KET____DOT__choose_thread__DOT__i[16]; + static CData/*1:0*/ __Vtable8_cache_simX__DOT__dmem_controller__DOT__dcache__DOT____Vcellout__genblk1__BRA__2__KET____DOT__choose_thread__index[16]; + static CData/*0:0*/ __Vtable8_cache_simX__DOT__dmem_controller__DOT__dcache__DOT____Vcellout__genblk1__BRA__2__KET____DOT__choose_thread__found[16]; + static IData/*31:0*/ __Vtable8_cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk1__BRA__2__KET____DOT__choose_thread__DOT__i[16]; + static CData/*1:0*/ __Vtable9_cache_simX__DOT__dmem_controller__DOT__dcache__DOT____Vcellout__genblk1__BRA__3__KET____DOT__choose_thread__index[16]; + static CData/*0:0*/ __Vtable9_cache_simX__DOT__dmem_controller__DOT__dcache__DOT____Vcellout__genblk1__BRA__3__KET____DOT__choose_thread__found[16]; + static IData/*31:0*/ __Vtable9_cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk1__BRA__3__KET____DOT__choose_thread__DOT__i[16]; + + // INTERNAL VARIABLES + // Internals; generally not touched by application code + Vcache_simX__Syms* __VlSymsp; // Symbol table + + // PARAMETERS + // Parameters marked /*verilator public*/ for use by application code + + // CONSTRUCTORS + private: + VL_UNCOPYABLE(Vcache_simX); ///< Copying not allowed + public: + /// Construct the model; called by application code + /// The special name may be used to make a wrapper with a + /// single model invisible with respect to DPI scope names. + Vcache_simX(const char* name = "TOP"); + /// Destroy the model; called (often implicitly) by application code + ~Vcache_simX(); + /// Trace signals in the model; called by application code + void trace(VerilatedVcdC* tfp, int levels, int options = 0); + + // API METHODS + /// Evaluate the model. Application must call when inputs change. + void eval(); + /// Simulation complete, run final blocks. Application must call on completion. + void final(); + + // INTERNAL METHODS + private: + static void _eval_initial_loop(Vcache_simX__Syms* __restrict vlSymsp); + public: + void __Vconfigure(Vcache_simX__Syms* symsp, bool first); + private: + static QData _change_request(Vcache_simX__Syms* __restrict vlSymsp); + public: + static void _combo__TOP__1(Vcache_simX__Syms* __restrict vlSymsp); + static void _combo__TOP__5(Vcache_simX__Syms* __restrict vlSymsp); + private: + void _ctor_var_reset() VL_ATTR_COLD; + public: + static void _eval(Vcache_simX__Syms* __restrict vlSymsp); + private: +#ifdef VL_DEBUG + void _eval_debug_assertions(); +#endif // VL_DEBUG + public: + static void _eval_initial(Vcache_simX__Syms* __restrict vlSymsp) VL_ATTR_COLD; + static void _eval_settle(Vcache_simX__Syms* __restrict vlSymsp) VL_ATTR_COLD; + static void _sequent__TOP__4(Vcache_simX__Syms* __restrict vlSymsp); + static void _settle__TOP__2(Vcache_simX__Syms* __restrict vlSymsp) VL_ATTR_COLD; + static void _settle__TOP__3(Vcache_simX__Syms* __restrict vlSymsp); + static void traceChgThis(Vcache_simX__Syms* __restrict vlSymsp, VerilatedVcd* vcdp, uint32_t code); + static void traceChgThis__2(Vcache_simX__Syms* __restrict vlSymsp, VerilatedVcd* vcdp, uint32_t code); + static void traceChgThis__3(Vcache_simX__Syms* __restrict vlSymsp, VerilatedVcd* vcdp, uint32_t code); + static void traceChgThis__4(Vcache_simX__Syms* __restrict vlSymsp, VerilatedVcd* vcdp, uint32_t code); + static void traceChgThis__5(Vcache_simX__Syms* __restrict vlSymsp, VerilatedVcd* vcdp, uint32_t code); + static void traceChgThis__6(Vcache_simX__Syms* __restrict vlSymsp, VerilatedVcd* vcdp, uint32_t code); + static void traceFullThis(Vcache_simX__Syms* __restrict vlSymsp, VerilatedVcd* vcdp, uint32_t code) VL_ATTR_COLD; + static void traceFullThis__1(Vcache_simX__Syms* __restrict vlSymsp, VerilatedVcd* vcdp, uint32_t code) VL_ATTR_COLD; + static void traceInitThis(Vcache_simX__Syms* __restrict vlSymsp, VerilatedVcd* vcdp, uint32_t code) VL_ATTR_COLD; + static void traceInitThis__1(Vcache_simX__Syms* __restrict vlSymsp, VerilatedVcd* vcdp, uint32_t code) VL_ATTR_COLD; + static void traceInit(VerilatedVcd* vcdp, void* userthis, uint32_t code); + static void traceFull(VerilatedVcd* vcdp, void* userthis, uint32_t code); + static void traceChg(VerilatedVcd* vcdp, void* userthis, uint32_t code); +} VL_ATTR_ALIGNED(128); + +#endif // guard diff --git a/simX/obj_dir/Vcache_simX.mk b/simX/obj_dir/Vcache_simX.mk new file mode 100644 index 00000000..644e2052 --- /dev/null +++ b/simX/obj_dir/Vcache_simX.mk @@ -0,0 +1,85 @@ +# Verilated -*- Makefile -*- +# DESCRIPTION: Verilator output: Makefile for building Verilated archive or executable +# +# Execute this makefile from the object directory: +# make -f Vcache_simX.mk + +default: Vcache_simX + +### Constants... +# Perl executable (from $PERL) +PERL = perl +# Path to Verilator kit (from $VERILATOR_ROOT) +VERILATOR_ROOT = /usr/local/share/verilator +# SystemC include directory with systemc.h (from $SYSTEMC_INCLUDE) +SYSTEMC_INCLUDE ?= +# SystemC library directory with libsystemc.a (from $SYSTEMC_LIBDIR) +SYSTEMC_LIBDIR ?= + +### Switches... +# SystemC output mode? 0/1 (from --sc) +VM_SC = 0 +# Legacy or SystemC output mode? 0/1 (from --sc) +VM_SP_OR_SC = $(VM_SC) +# Deprecated +VM_PCLI = 1 +# Deprecated: SystemC architecture to find link library path (from $SYSTEMC_ARCH) +VM_SC_TARGET_ARCH = linux + +### Vars... +# Design prefix (from --prefix) +VM_PREFIX = Vcache_simX +# Module prefix (from --prefix) +VM_MODPREFIX = Vcache_simX +# User CFLAGS (from -CFLAGS on Verilator command line) +VM_USER_CFLAGS = \ + -std=c++11 -fPIC -O3 \ + +# User LDLIBS (from -LDFLAGS on Verilator command line) +VM_USER_LDLIBS = \ + +# User .cpp files (from .cpp's on Verilator command line) +VM_USER_CLASSES = \ + args \ + core \ + enc \ + instruction \ + mem \ + simX \ + util \ + +# User .cpp directories (from .cpp's on Verilator command line) +VM_USER_DIR = \ + . \ + + +### Default rules... +# Include list of all generated classes +include Vcache_simX_classes.mk +# Include global rules +include $(VERILATOR_ROOT)/include/verilated.mk + +### Executable rules... (from --exe) +VPATH += $(VM_USER_DIR) + +args.o: args.cpp + $(OBJCACHE) $(CXX) $(CXXFLAGS) $(CPPFLAGS) $(OPT_FAST) -c -o $@ $< +core.o: core.cpp + $(OBJCACHE) $(CXX) $(CXXFLAGS) $(CPPFLAGS) $(OPT_FAST) -c -o $@ $< +enc.o: enc.cpp + $(OBJCACHE) $(CXX) $(CXXFLAGS) $(CPPFLAGS) $(OPT_FAST) -c -o $@ $< +instruction.o: instruction.cpp + $(OBJCACHE) $(CXX) $(CXXFLAGS) $(CPPFLAGS) $(OPT_FAST) -c -o $@ $< +mem.o: mem.cpp + $(OBJCACHE) $(CXX) $(CXXFLAGS) $(CPPFLAGS) $(OPT_FAST) -c -o $@ $< +simX.o: simX.cpp + $(OBJCACHE) $(CXX) $(CXXFLAGS) $(CPPFLAGS) $(OPT_FAST) -c -o $@ $< +util.o: util.cpp + $(OBJCACHE) $(CXX) $(CXXFLAGS) $(CPPFLAGS) $(OPT_FAST) -c -o $@ $< + +### Link rules... (from --exe) +Vcache_simX: $(VK_USER_OBJS) $(VK_GLOBAL_OBJS) $(VM_PREFIX)__ALL.a + $(LINK) $(LDFLAGS) $^ $(LOADLIBES) $(LDLIBS) -o $@ $(LIBS) $(SC_LIBS) + + +# Verilated -*- Makefile -*- diff --git a/simX/obj_dir/Vcache_simX_VX_Cache_Bank__pi7.cpp b/simX/obj_dir/Vcache_simX_VX_Cache_Bank__pi7.cpp new file mode 100644 index 00000000..d214a4a8 --- /dev/null +++ b/simX/obj_dir/Vcache_simX_VX_Cache_Bank__pi7.cpp @@ -0,0 +1,8669 @@ +// Verilated -*- C++ -*- +// DESCRIPTION: Verilator output: Design implementation internals +// See Vcache_simX.h for the primary calling header + +#include "Vcache_simX_VX_Cache_Bank__pi7.h" +#include "Vcache_simX__Syms.h" + + +//-------------------- +// STATIC VARIABLES + + +//-------------------- + +VL_CTOR_IMP(Vcache_simX_VX_Cache_Bank__pi7) { + // Reset internal values + // Reset structure values + _ctor_var_reset(); +} + +void Vcache_simX_VX_Cache_Bank__pi7::__Vconfigure(Vcache_simX__Syms* vlSymsp, bool first) { + if (0 && first) {} // Prevent unused + this->__VlSymsp = vlSymsp; +} + +Vcache_simX_VX_Cache_Bank__pi7::~Vcache_simX_VX_Cache_Bank__pi7() { +} + +//-------------------- +// Internal Methods + +void Vcache_simX_VX_Cache_Bank__pi7::_settle__TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__1(Vcache_simX__Syms* __restrict vlSymsp) { + VL_DEBUG_IF(VL_DBG_MSGF("+ Vcache_simX_VX_Cache_Bank__pi7::_settle__TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__1\n"); ); + Vcache_simX* __restrict vlTOPp VL_ATTR_UNUSED = vlSymsp->TOPp; + // Variables + WData/*31:0*/ __Vtemp1[4]; + WData/*31:0*/ __Vtemp2[4]; + WData/*31:0*/ __Vtemp3[4]; + WData/*31:0*/ __Vtemp4[4]; + WData/*31:0*/ __Vtemp5[4]; + WData/*31:0*/ __Vtemp6[4]; + WData/*31:0*/ __Vtemp7[4]; + // Body + this->__PVT__way_to_update = vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT__global_way_to_evict; + this->__PVT__write_from_mem = ((2U == (IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT__state)) + & (IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__0__KET____DOT__use_valid_in)); + this->__PVT__access = ((0U == (IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT__state)) + & (IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__0__KET____DOT__use_valid_in)); + this->data_structures__DOT____Vcellout__each_way__BRA__0__KET____DOT__data_structures__dirty_use + = this->__PVT__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__dirty + [(0x1fU & (vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__0__KET____DOT__bank_addr + >> 6U))]; + this->data_structures__DOT____Vcellout__each_way__BRA__1__KET____DOT__data_structures__dirty_use + = this->__PVT__data_structures__DOT__each_way__BRA__1__KET____DOT__data_structures__DOT__dirty + [(0x1fU & (vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__0__KET____DOT__bank_addr + >> 6U))]; + __Vtemp1[0U] = 0U; + __Vtemp1[1U] = 0U; + __Vtemp1[2U] = 0U; + __Vtemp1[3U] = 0U; + __Vtemp2[0U] = 0U; + __Vtemp2[1U] = 0U; + __Vtemp2[2U] = 0U; + __Vtemp2[3U] = 0U; + __Vtemp3[0U] = 0U; + __Vtemp3[1U] = 0U; + __Vtemp3[2U] = 0U; + __Vtemp3[3U] = 0U; + __Vtemp4[0U] = 0U; + __Vtemp4[1U] = 0U; + __Vtemp4[2U] = 0U; + __Vtemp4[3U] = 0U; + __Vtemp5[0U] = 0U; + __Vtemp5[1U] = 0U; + __Vtemp5[2U] = 0U; + __Vtemp5[3U] = 0U; + __Vtemp6[0U] = 0U; + __Vtemp6[1U] = 0U; + __Vtemp6[2U] = 0U; + __Vtemp6[3U] = 0U; + __Vtemp7[0U] = 0U; + __Vtemp7[1U] = 0U; + __Vtemp7[2U] = 0U; + __Vtemp7[3U] = 0U; + this->__PVT__use_write_data = ((0U == (IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__cache_driver_in_mem_write)) + ? ((1U == (3U & vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__0__KET____DOT__bank_addr)) + ? (0xff00U + & (__Vtemp1[ + (3U & (IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT__index_per_bank))] + << 8U)) + : ((2U == (3U + & vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__0__KET____DOT__bank_addr)) + ? (0xff0000U + & (__Vtemp2[ + (3U + & (IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT__index_per_bank))] + << 0x10U)) + : ((3U + == + (3U + & vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__0__KET____DOT__bank_addr)) + ? (0xff000000U + & (__Vtemp3[ + (3U + & (IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT__index_per_bank))] + << 0x18U)) + : __Vtemp4[ + (3U + & (IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT__index_per_bank))]))) + : ((1U == (IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__cache_driver_in_mem_write)) + ? ((2U == (3U + & vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__0__KET____DOT__bank_addr)) + ? (0xffff0000U + & (__Vtemp5[ + (3U + & (IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT__index_per_bank))] + << 0x10U)) + : __Vtemp6[ + (3U & (IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT__index_per_bank))]) + : __Vtemp7[ + (3U & (IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT__index_per_bank))])); + this->__PVT__sb_mask = ((0U == (3U & vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__0__KET____DOT__bank_addr)) + ? 1U : ((1U == (3U & vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__0__KET____DOT__bank_addr)) + ? 2U : ((2U == + (3U + & vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__0__KET____DOT__bank_addr)) + ? 4U + : 8U))); + this->__PVT__data_structures__DOT__data_use_per_way[0U] + = this->__PVT__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__data + [(0x1fU & (vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__0__KET____DOT__bank_addr + >> 6U))][0U]; + this->__PVT__data_structures__DOT__data_use_per_way[1U] + = this->__PVT__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__data + [(0x1fU & (vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__0__KET____DOT__bank_addr + >> 6U))][1U]; + this->__PVT__data_structures__DOT__data_use_per_way[2U] + = this->__PVT__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__data + [(0x1fU & (vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__0__KET____DOT__bank_addr + >> 6U))][2U]; + this->__PVT__data_structures__DOT__data_use_per_way[3U] + = this->__PVT__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__data + [(0x1fU & (vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__0__KET____DOT__bank_addr + >> 6U))][3U]; + this->__PVT__data_structures__DOT__data_use_per_way[4U] + = this->__PVT__data_structures__DOT__each_way__BRA__1__KET____DOT__data_structures__DOT__data + [(0x1fU & (vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__0__KET____DOT__bank_addr + >> 6U))][0U]; + this->__PVT__data_structures__DOT__data_use_per_way[5U] + = this->__PVT__data_structures__DOT__each_way__BRA__1__KET____DOT__data_structures__DOT__data + [(0x1fU & (vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__0__KET____DOT__bank_addr + >> 6U))][1U]; + this->__PVT__data_structures__DOT__data_use_per_way[6U] + = this->__PVT__data_structures__DOT__each_way__BRA__1__KET____DOT__data_structures__DOT__data + [(0x1fU & (vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__0__KET____DOT__bank_addr + >> 6U))][2U]; + this->__PVT__data_structures__DOT__data_use_per_way[7U] + = this->__PVT__data_structures__DOT__each_way__BRA__1__KET____DOT__data_structures__DOT__data + [(0x1fU & (vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__0__KET____DOT__bank_addr + >> 6U))][3U]; + this->__PVT__data_structures__DOT__valid_use_per_way + = ((2U & (IData)(this->__PVT__data_structures__DOT__valid_use_per_way)) + | this->__PVT__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__valid + [(0x1fU & (vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__0__KET____DOT__bank_addr + >> 6U))]); + this->__PVT__data_structures__DOT__valid_use_per_way + = ((1U & (IData)(this->__PVT__data_structures__DOT__valid_use_per_way)) + | (this->__PVT__data_structures__DOT__each_way__BRA__1__KET____DOT__data_structures__DOT__valid + [(0x1fU & (vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__0__KET____DOT__bank_addr + >> 6U))] << 1U)); + this->__PVT__data_structures__DOT__tag_use_per_way + = ((VL_ULL(0x3ffffe00000) & this->__PVT__data_structures__DOT__tag_use_per_way) + | (IData)((IData)(this->__PVT__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__tag + [(0x1fU & (vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__0__KET____DOT__bank_addr + >> 6U))]))); + this->__PVT__data_structures__DOT__tag_use_per_way + = ((VL_ULL(0x1fffff) & this->__PVT__data_structures__DOT__tag_use_per_way) + | ((QData)((IData)(this->__PVT__data_structures__DOT__each_way__BRA__1__KET____DOT__data_structures__DOT__tag + [(0x1fU & (vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__0__KET____DOT__bank_addr + >> 6U))])) + << 0x15U)); + this->__PVT__data_structures__DOT__dirty_use_per_way + = ((2U & (IData)(this->__PVT__data_structures__DOT__dirty_use_per_way)) + | (IData)(this->data_structures__DOT____Vcellout__each_way__BRA__0__KET____DOT__data_structures__dirty_use)); + this->__PVT__data_structures__DOT__dirty_use_per_way + = ((1U & (IData)(this->__PVT__data_structures__DOT__dirty_use_per_way)) + | ((IData)(this->data_structures__DOT____Vcellout__each_way__BRA__1__KET____DOT__data_structures__dirty_use) + << 1U)); + this->__PVT__data_write[0U] = ((IData)(this->__PVT__write_from_mem) + ? vlSymsp->TOP__cache_simX__DOT__VX_dram_req_rsp.i_m_readdata[0U] + : this->__PVT__use_write_data); + this->__PVT__data_write[1U] = ((IData)(this->__PVT__write_from_mem) + ? vlSymsp->TOP__cache_simX__DOT__VX_dram_req_rsp.i_m_readdata[1U] + : this->__PVT__use_write_data); + this->__PVT__data_write[2U] = ((IData)(this->__PVT__write_from_mem) + ? vlSymsp->TOP__cache_simX__DOT__VX_dram_req_rsp.i_m_readdata[2U] + : this->__PVT__use_write_data); + this->__PVT__data_write[3U] = ((IData)(this->__PVT__write_from_mem) + ? vlSymsp->TOP__cache_simX__DOT__VX_dram_req_rsp.i_m_readdata[3U] + : this->__PVT__use_write_data); + this->__PVT__data_structures__DOT__invalid_found = 0U; + if ((1U & (~ ((IData)(this->__PVT__data_structures__DOT__valid_use_per_way) + >> 1U)))) { + this->__PVT__data_structures__DOT__invalid_found = 1U; + } + if ((1U & (~ (IData)(this->__PVT__data_structures__DOT__valid_use_per_way)))) { + this->__PVT__data_structures__DOT__invalid_found = 1U; + } + this->__PVT__data_structures__DOT__invalid_index = 0U; + if ((1U & (~ ((IData)(this->__PVT__data_structures__DOT__valid_use_per_way) + >> 1U)))) { + this->__PVT__data_structures__DOT__invalid_index = 1U; + } + if ((1U & (~ (IData)(this->__PVT__data_structures__DOT__valid_use_per_way)))) { + this->__PVT__data_structures__DOT__invalid_index = 0U; + } + this->__PVT__data_structures__DOT__hit_per_way + = ((2U & (IData)(this->__PVT__data_structures__DOT__hit_per_way)) + | (((IData)(this->__PVT__data_structures__DOT__valid_use_per_way) + & ((0x1fffffU & (IData)(this->__PVT__data_structures__DOT__tag_use_per_way)) + == (0x1fffffU & (vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__0__KET____DOT__bank_addr + >> 0xbU)))) ? 1U + : 0U)); + this->__PVT__data_structures__DOT__hit_per_way + = ((1U & (IData)(this->__PVT__data_structures__DOT__hit_per_way)) + | (((((IData)(this->__PVT__data_structures__DOT__valid_use_per_way) + >> 1U) & ((0x1fffffU & (IData)((this->__PVT__data_structures__DOT__tag_use_per_way + >> 0x15U))) + == (0x1fffffU & (vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__0__KET____DOT__bank_addr + >> 0xbU)))) + ? 1U : 0U) << 1U)); + this->__PVT__data_structures__DOT__data_write_per_way[0U] + = this->__PVT__data_write[0U]; + this->__PVT__data_structures__DOT__data_write_per_way[1U] + = this->__PVT__data_write[1U]; + this->__PVT__data_structures__DOT__data_write_per_way[2U] + = this->__PVT__data_write[2U]; + this->__PVT__data_structures__DOT__data_write_per_way[3U] + = this->__PVT__data_write[3U]; + this->__PVT__data_structures__DOT__data_write_per_way[4U] + = this->__PVT__data_write[0U]; + this->__PVT__data_structures__DOT__data_write_per_way[5U] + = this->__PVT__data_write[1U]; + this->__PVT__data_structures__DOT__data_write_per_way[6U] + = this->__PVT__data_write[2U]; + this->__PVT__data_structures__DOT__data_write_per_way[7U] + = this->__PVT__data_write[3U]; + this->__PVT__data_structures__DOT__genblk1__DOT__way_indexing__DOT__found = 0U; + if ((2U & (IData)(this->__PVT__data_structures__DOT__hit_per_way))) { + this->__PVT__data_structures__DOT__genblk1__DOT__way_indexing__DOT__found = 1U; + } + if ((1U & (IData)(this->__PVT__data_structures__DOT__hit_per_way))) { + this->__PVT__data_structures__DOT__genblk1__DOT__way_indexing__DOT__found = 1U; + } + this->__PVT__data_structures__DOT__way_index = 0U; + if ((2U & (IData)(this->__PVT__data_structures__DOT__hit_per_way))) { + this->__PVT__data_structures__DOT__way_index = 1U; + } + if ((1U & (IData)(this->__PVT__data_structures__DOT__hit_per_way))) { + this->__PVT__data_structures__DOT__way_index = 0U; + } + this->__PVT__data_structures__DOT__way_use_Qual + = ((0U != (IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT__state)) + ? (IData)(this->__PVT__way_to_update) : (IData)(this->__PVT__data_structures__DOT__way_index)); + this->__PVT__data_structures__DOT__write_from_mem_per_way + = ((2U & (IData)(this->__PVT__data_structures__DOT__write_from_mem_per_way)) + | ((IData)(this->__PVT__write_from_mem) + & (~ (IData)(this->__PVT__data_structures__DOT__way_use_Qual)))); + this->__PVT__data_structures__DOT__write_from_mem_per_way + = ((1U & (IData)(this->__PVT__data_structures__DOT__write_from_mem_per_way)) + | (((IData)(this->__PVT__write_from_mem) + & (IData)(this->__PVT__data_structures__DOT__way_use_Qual)) + << 1U)); + this->__Vcellout__data_structures__data_use[0U] + = (((0U == (0x1fU & ((IData)(this->__PVT__data_structures__DOT__way_use_Qual) + << 7U))) ? 0U : (this->__PVT__data_structures__DOT__data_use_per_way[ + ((IData)(1U) + + (4U + & ((IData)(this->__PVT__data_structures__DOT__way_use_Qual) + << 2U)))] + << ((IData)(0x20U) + - + (0x1fU + & ((IData)(this->__PVT__data_structures__DOT__way_use_Qual) + << 7U))))) + | (this->__PVT__data_structures__DOT__data_use_per_way[ + (4U & ((IData)(this->__PVT__data_structures__DOT__way_use_Qual) + << 2U))] >> (0x1fU & ((IData)(this->__PVT__data_structures__DOT__way_use_Qual) + << 7U)))); + this->__Vcellout__data_structures__data_use[1U] + = (((0U == (0x1fU & ((IData)(this->__PVT__data_structures__DOT__way_use_Qual) + << 7U))) ? 0U : (this->__PVT__data_structures__DOT__data_use_per_way[ + ((IData)(2U) + + (4U + & ((IData)(this->__PVT__data_structures__DOT__way_use_Qual) + << 2U)))] + << ((IData)(0x20U) + - + (0x1fU + & ((IData)(this->__PVT__data_structures__DOT__way_use_Qual) + << 7U))))) + | (this->__PVT__data_structures__DOT__data_use_per_way[ + ((IData)(1U) + (4U & ((IData)(this->__PVT__data_structures__DOT__way_use_Qual) + << 2U)))] >> (0x1fU + & ((IData)(this->__PVT__data_structures__DOT__way_use_Qual) + << 7U)))); + this->__Vcellout__data_structures__data_use[2U] + = (((0U == (0x1fU & ((IData)(this->__PVT__data_structures__DOT__way_use_Qual) + << 7U))) ? 0U : (this->__PVT__data_structures__DOT__data_use_per_way[ + ((IData)(3U) + + (4U + & ((IData)(this->__PVT__data_structures__DOT__way_use_Qual) + << 2U)))] + << ((IData)(0x20U) + - + (0x1fU + & ((IData)(this->__PVT__data_structures__DOT__way_use_Qual) + << 7U))))) + | (this->__PVT__data_structures__DOT__data_use_per_way[ + ((IData)(2U) + (4U & ((IData)(this->__PVT__data_structures__DOT__way_use_Qual) + << 2U)))] >> (0x1fU + & ((IData)(this->__PVT__data_structures__DOT__way_use_Qual) + << 7U)))); + this->__Vcellout__data_structures__data_use[3U] + = (((0U == (0x1fU & ((IData)(this->__PVT__data_structures__DOT__way_use_Qual) + << 7U))) ? 0U : (this->__PVT__data_structures__DOT__data_use_per_way[ + ((IData)(4U) + + (4U + & ((IData)(this->__PVT__data_structures__DOT__way_use_Qual) + << 2U)))] + << ((IData)(0x20U) + - + (0x1fU + & ((IData)(this->__PVT__data_structures__DOT__way_use_Qual) + << 7U))))) + | (this->__PVT__data_structures__DOT__data_use_per_way[ + ((IData)(3U) + (4U & ((IData)(this->__PVT__data_structures__DOT__way_use_Qual) + << 2U)))] >> (0x1fU + & ((IData)(this->__PVT__data_structures__DOT__way_use_Qual) + << 7U)))); + this->__PVT__valid_use = (1U & ((IData)(this->__PVT__data_structures__DOT__valid_use_per_way) + >> (IData)(this->__PVT__data_structures__DOT__way_use_Qual))); + this->__PVT__tag_use = ((0x29U >= (0x3fU & ((IData)(0x15U) + * (IData)(this->__PVT__data_structures__DOT__way_use_Qual)))) + ? (0x1fffffU & (IData)( + (this->__PVT__data_structures__DOT__tag_use_per_way + >> + (0x3fU + & ((IData)(0x15U) + * (IData)(this->__PVT__data_structures__DOT__way_use_Qual)))))) + : 0U); + this->__PVT__data_unQual = (((0U == (3U & vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__0__KET____DOT__bank_addr)) + | (2U == (IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__cache_driver_in_mem_read))) + ? this->__Vcellout__data_structures__data_use[ + (3U & (vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__0__KET____DOT__bank_addr + >> 4U))] : ( + (1U + == + (3U + & vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__0__KET____DOT__bank_addr)) + ? + (this->__Vcellout__data_structures__data_use[ + (3U + & (vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__0__KET____DOT__bank_addr + >> 4U))] + >> 8U) + : + ((2U + == + (3U + & vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__0__KET____DOT__bank_addr)) + ? + (this->__Vcellout__data_structures__data_use[ + (3U + & (vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__0__KET____DOT__bank_addr + >> 4U))] + >> 0x10U) + : + (this->__Vcellout__data_structures__data_use[ + (3U + & (vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__0__KET____DOT__bank_addr + >> 4U))] + >> 0x18U)))); + this->__PVT__miss = (((this->__PVT__tag_use != + (0x1fffffU & (vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__0__KET____DOT__bank_addr + >> 0xbU))) + & (IData)(this->__PVT__valid_use)) + & (IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__0__KET____DOT__use_valid_in)); + this->__PVT__genblk1__BRA__0__KET____DOT__normal_write + = (((IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__read_or_write) + & ((IData)(this->__PVT__access) & (0U == + (3U + & (vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__0__KET____DOT__bank_addr + >> 4U))))) + & (~ (IData)(this->__PVT__miss))); + this->__PVT__genblk1__BRA__1__KET____DOT__normal_write + = (((IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__read_or_write) + & ((IData)(this->__PVT__access) & (1U == + (3U + & (vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__0__KET____DOT__bank_addr + >> 4U))))) + & (~ (IData)(this->__PVT__miss))); + this->__PVT__genblk1__BRA__2__KET____DOT__normal_write + = (((IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__read_or_write) + & ((IData)(this->__PVT__access) & (2U == + (3U + & (vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__0__KET____DOT__bank_addr + >> 4U))))) + & (~ (IData)(this->__PVT__miss))); + this->__PVT__genblk1__BRA__3__KET____DOT__normal_write + = (((IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__read_or_write) + & ((IData)(this->__PVT__access) & (3U == + (3U + & (vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__0__KET____DOT__bank_addr + >> 4U))))) + & (~ (IData)(this->__PVT__miss))); + this->__PVT__we = ((0xfff0U & (IData)(this->__PVT__we)) + | ((IData)(this->__PVT__write_from_mem) + ? 0xfU : (((IData)(this->__PVT__genblk1__BRA__0__KET____DOT__normal_write) + & (2U == (IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__cache_driver_in_mem_write))) + ? 0xfU : (((IData)(this->__PVT__genblk1__BRA__0__KET____DOT__normal_write) + & (0U + == (IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__cache_driver_in_mem_write))) + ? (IData)(this->__PVT__sb_mask) + : + (((IData)(this->__PVT__genblk1__BRA__0__KET____DOT__normal_write) + & (1U + == (IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__cache_driver_in_mem_write))) + ? + ((0U + == + (3U + & vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__0__KET____DOT__bank_addr)) + ? 3U + : 0xcU) + : 0U))))); + this->__PVT__we = ((0xff0fU & (IData)(this->__PVT__we)) + | (((IData)(this->__PVT__write_from_mem) + ? 0xfU : (((IData)(this->__PVT__genblk1__BRA__1__KET____DOT__normal_write) + & (2U == (IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__cache_driver_in_mem_write))) + ? 0xfU : (((IData)(this->__PVT__genblk1__BRA__1__KET____DOT__normal_write) + & (0U + == (IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__cache_driver_in_mem_write))) + ? (IData)(this->__PVT__sb_mask) + : + (((IData)(this->__PVT__genblk1__BRA__1__KET____DOT__normal_write) + & (1U + == (IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__cache_driver_in_mem_write))) + ? + ((0U + == + (3U + & vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__0__KET____DOT__bank_addr)) + ? 3U + : 0xcU) + : 0U)))) + << 4U)); + this->__PVT__we = ((0xf0ffU & (IData)(this->__PVT__we)) + | (((IData)(this->__PVT__write_from_mem) + ? 0xfU : (((IData)(this->__PVT__genblk1__BRA__2__KET____DOT__normal_write) + & (2U == (IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__cache_driver_in_mem_write))) + ? 0xfU : (((IData)(this->__PVT__genblk1__BRA__2__KET____DOT__normal_write) + & (0U + == (IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__cache_driver_in_mem_write))) + ? (IData)(this->__PVT__sb_mask) + : + (((IData)(this->__PVT__genblk1__BRA__2__KET____DOT__normal_write) + & (1U + == (IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__cache_driver_in_mem_write))) + ? + ((0U + == + (3U + & vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__0__KET____DOT__bank_addr)) + ? 3U + : 0xcU) + : 0U)))) + << 8U)); + this->__PVT__we = ((0xfffU & (IData)(this->__PVT__we)) + | (((IData)(this->__PVT__write_from_mem) + ? 0xfU : (((IData)(this->__PVT__genblk1__BRA__3__KET____DOT__normal_write) + & (2U == (IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__cache_driver_in_mem_write))) + ? 0xfU : (((IData)(this->__PVT__genblk1__BRA__3__KET____DOT__normal_write) + & (0U + == (IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__cache_driver_in_mem_write))) + ? (IData)(this->__PVT__sb_mask) + : + (((IData)(this->__PVT__genblk1__BRA__3__KET____DOT__normal_write) + & (1U + == (IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__cache_driver_in_mem_write))) + ? + ((0U + == + (3U + & vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__0__KET____DOT__bank_addr)) + ? 3U + : 0xcU) + : 0U)))) + << 0xcU)); + this->__PVT__data_structures__DOT__we_per_way = + ((0xffff0000U & this->__PVT__data_structures__DOT__we_per_way) + | ((IData)(this->__PVT__data_structures__DOT__way_use_Qual) + ? 0U : (0xffffU & (IData)(this->__PVT__we)))); + this->__PVT__data_structures__DOT__we_per_way = + ((0xffffU & this->__PVT__data_structures__DOT__we_per_way) + | (((IData)(this->__PVT__data_structures__DOT__way_use_Qual) + ? (0xffffU & (IData)(this->__PVT__we)) + : 0U) << 0x10U)); +} + +VL_INLINE_OPT void Vcache_simX_VX_Cache_Bank__pi7::_sequent__TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__5(Vcache_simX__Syms* __restrict vlSymsp) { + VL_DEBUG_IF(VL_DBG_MSGF("+ Vcache_simX_VX_Cache_Bank__pi7::_sequent__TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__5\n"); ); + Vcache_simX* __restrict vlTOPp VL_ATTR_UNUSED = vlSymsp->TOPp; + // Body + this->__PVT__way_to_update = vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT__global_way_to_evict; + this->__Vdlyvset__data_structures__DOT__each_way__BRA__1__KET____DOT__data_structures__DOT__dirty__v0 = 0U; + this->__Vdlyvset__data_structures__DOT__each_way__BRA__1__KET____DOT__data_structures__DOT__dirty__v32 = 0U; + this->__Vdlyvset__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__dirty__v0 = 0U; + this->__Vdlyvset__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__dirty__v32 = 0U; + this->__Vdlyvset__data_structures__DOT__each_way__BRA__1__KET____DOT__data_structures__DOT__valid__v0 = 0U; + this->__Vdlyvset__data_structures__DOT__each_way__BRA__1__KET____DOT__data_structures__DOT__valid__v32 = 0U; + this->__Vdlyvset__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__valid__v0 = 0U; + this->__Vdlyvset__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__valid__v32 = 0U; + this->__Vdlyvset__data_structures__DOT__each_way__BRA__1__KET____DOT__data_structures__DOT__tag__v0 = 0U; + this->__Vdlyvset__data_structures__DOT__each_way__BRA__1__KET____DOT__data_structures__DOT__tag__v32 = 0U; + this->__Vdlyvset__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__tag__v0 = 0U; + this->__Vdlyvset__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__tag__v32 = 0U; + if (vlTOPp->reset) { + this->__PVT__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__ini_ind = 0x20U; + } + if ((1U & (~ (IData)(vlTOPp->reset)))) { + this->__PVT__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__f = 4U; + } + if (vlTOPp->reset) { + this->__PVT__data_structures__DOT__each_way__BRA__1__KET____DOT__data_structures__DOT__ini_ind = 0x20U; + } + if ((1U & (~ (IData)(vlTOPp->reset)))) { + this->__PVT__data_structures__DOT__each_way__BRA__1__KET____DOT__data_structures__DOT__f = 4U; + } + this->__Vdlyvset__data_structures__DOT__each_way__BRA__1__KET____DOT__data_structures__DOT__data__v0 = 0U; + this->__Vdlyvset__data_structures__DOT__each_way__BRA__1__KET____DOT__data_structures__DOT__data__v32 = 0U; + this->__Vdlyvset__data_structures__DOT__each_way__BRA__1__KET____DOT__data_structures__DOT__data__v33 = 0U; + this->__Vdlyvset__data_structures__DOT__each_way__BRA__1__KET____DOT__data_structures__DOT__data__v34 = 0U; + this->__Vdlyvset__data_structures__DOT__each_way__BRA__1__KET____DOT__data_structures__DOT__data__v35 = 0U; + this->__Vdlyvset__data_structures__DOT__each_way__BRA__1__KET____DOT__data_structures__DOT__data__v36 = 0U; + this->__Vdlyvset__data_structures__DOT__each_way__BRA__1__KET____DOT__data_structures__DOT__data__v37 = 0U; + this->__Vdlyvset__data_structures__DOT__each_way__BRA__1__KET____DOT__data_structures__DOT__data__v38 = 0U; + this->__Vdlyvset__data_structures__DOT__each_way__BRA__1__KET____DOT__data_structures__DOT__data__v39 = 0U; + this->__Vdlyvset__data_structures__DOT__each_way__BRA__1__KET____DOT__data_structures__DOT__data__v40 = 0U; + this->__Vdlyvset__data_structures__DOT__each_way__BRA__1__KET____DOT__data_structures__DOT__data__v41 = 0U; + this->__Vdlyvset__data_structures__DOT__each_way__BRA__1__KET____DOT__data_structures__DOT__data__v42 = 0U; + this->__Vdlyvset__data_structures__DOT__each_way__BRA__1__KET____DOT__data_structures__DOT__data__v43 = 0U; + this->__Vdlyvset__data_structures__DOT__each_way__BRA__1__KET____DOT__data_structures__DOT__data__v44 = 0U; + this->__Vdlyvset__data_structures__DOT__each_way__BRA__1__KET____DOT__data_structures__DOT__data__v45 = 0U; + this->__Vdlyvset__data_structures__DOT__each_way__BRA__1__KET____DOT__data_structures__DOT__data__v46 = 0U; + this->__Vdlyvset__data_structures__DOT__each_way__BRA__1__KET____DOT__data_structures__DOT__data__v47 = 0U; + this->__Vdlyvset__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__data__v0 = 0U; + this->__Vdlyvset__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__data__v32 = 0U; + this->__Vdlyvset__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__data__v33 = 0U; + this->__Vdlyvset__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__data__v34 = 0U; + this->__Vdlyvset__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__data__v35 = 0U; + this->__Vdlyvset__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__data__v36 = 0U; + this->__Vdlyvset__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__data__v37 = 0U; + this->__Vdlyvset__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__data__v38 = 0U; + this->__Vdlyvset__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__data__v39 = 0U; + this->__Vdlyvset__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__data__v40 = 0U; + this->__Vdlyvset__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__data__v41 = 0U; + this->__Vdlyvset__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__data__v42 = 0U; + this->__Vdlyvset__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__data__v43 = 0U; + this->__Vdlyvset__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__data__v44 = 0U; + this->__Vdlyvset__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__data__v45 = 0U; + this->__Vdlyvset__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__data__v46 = 0U; + this->__Vdlyvset__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__data__v47 = 0U; + if (vlTOPp->reset) { + this->__Vdlyvset__data_structures__DOT__each_way__BRA__1__KET____DOT__data_structures__DOT__dirty__v0 = 1U; + } else { + if ((1U & (((~ (IData)(this->data_structures__DOT____Vcellout__each_way__BRA__1__KET____DOT__data_structures__dirty_use)) + & (0U != (0xffffU & (this->__PVT__data_structures__DOT__we_per_way + >> 0x10U)))) + | ((IData)(this->__PVT__data_structures__DOT__write_from_mem_per_way) + >> 1U)))) { + this->__Vdlyvval__data_structures__DOT__each_way__BRA__1__KET____DOT__data_structures__DOT__dirty__v32 + = ((2U & (IData)(this->__PVT__data_structures__DOT__write_from_mem_per_way)) + ? 0U : (1U & (0U != (0xffffU & + (this->__PVT__data_structures__DOT__we_per_way + >> 0x10U))))); + this->__Vdlyvset__data_structures__DOT__each_way__BRA__1__KET____DOT__data_structures__DOT__dirty__v32 = 1U; + this->__Vdlyvdim0__data_structures__DOT__each_way__BRA__1__KET____DOT__data_structures__DOT__dirty__v32 + = (0x1fU & (vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__0__KET____DOT__bank_addr + >> 6U)); + } + } + if (vlTOPp->reset) { + this->__Vdlyvset__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__dirty__v0 = 1U; + } else { + if ((1U & (((~ (IData)(this->data_structures__DOT____Vcellout__each_way__BRA__0__KET____DOT__data_structures__dirty_use)) + & (0U != (0xffffU & this->__PVT__data_structures__DOT__we_per_way))) + | (IData)(this->__PVT__data_structures__DOT__write_from_mem_per_way)))) { + this->__Vdlyvval__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__dirty__v32 + = ((1U & (IData)(this->__PVT__data_structures__DOT__write_from_mem_per_way)) + ? 0U : (1U & (0U != (0xffffU & this->__PVT__data_structures__DOT__we_per_way)))); + this->__Vdlyvset__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__dirty__v32 = 1U; + this->__Vdlyvdim0__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__dirty__v32 + = (0x1fU & (vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__0__KET____DOT__bank_addr + >> 6U)); + } + } + if (vlTOPp->reset) { + this->__Vdlyvset__data_structures__DOT__each_way__BRA__1__KET____DOT__data_structures__DOT__valid__v0 = 1U; + } else { + if ((2U & (IData)(this->__PVT__data_structures__DOT__write_from_mem_per_way))) { + this->__Vdlyvset__data_structures__DOT__each_way__BRA__1__KET____DOT__data_structures__DOT__valid__v32 = 1U; + this->__Vdlyvdim0__data_structures__DOT__each_way__BRA__1__KET____DOT__data_structures__DOT__valid__v32 + = (0x1fU & (vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__0__KET____DOT__bank_addr + >> 6U)); + } + } + if (vlTOPp->reset) { + this->__Vdlyvset__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__valid__v0 = 1U; + } else { + if ((1U & (IData)(this->__PVT__data_structures__DOT__write_from_mem_per_way))) { + this->__Vdlyvset__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__valid__v32 = 1U; + this->__Vdlyvdim0__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__valid__v32 + = (0x1fU & (vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__0__KET____DOT__bank_addr + >> 6U)); + } + } + if (vlTOPp->reset) { + this->__Vdlyvset__data_structures__DOT__each_way__BRA__1__KET____DOT__data_structures__DOT__tag__v0 = 1U; + } else { + if ((2U & (IData)(this->__PVT__data_structures__DOT__write_from_mem_per_way))) { + this->__Vdlyvval__data_structures__DOT__each_way__BRA__1__KET____DOT__data_structures__DOT__tag__v32 + = (0x1fffffU & (vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__0__KET____DOT__bank_addr + >> 0xbU)); + this->__Vdlyvset__data_structures__DOT__each_way__BRA__1__KET____DOT__data_structures__DOT__tag__v32 = 1U; + this->__Vdlyvdim0__data_structures__DOT__each_way__BRA__1__KET____DOT__data_structures__DOT__tag__v32 + = (0x1fU & (vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__0__KET____DOT__bank_addr + >> 6U)); + } + } + if (vlTOPp->reset) { + this->__Vdlyvset__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__tag__v0 = 1U; + } else { + if ((1U & (IData)(this->__PVT__data_structures__DOT__write_from_mem_per_way))) { + this->__Vdlyvval__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__tag__v32 + = (0x1fffffU & (vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__0__KET____DOT__bank_addr + >> 0xbU)); + this->__Vdlyvset__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__tag__v32 = 1U; + this->__Vdlyvdim0__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__tag__v32 + = (0x1fU & (vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__0__KET____DOT__bank_addr + >> 6U)); + } + } + if (vlTOPp->reset) { + this->__Vdlyvset__data_structures__DOT__each_way__BRA__1__KET____DOT__data_structures__DOT__data__v0 = 1U; + } else { + if ((0x10000U & this->__PVT__data_structures__DOT__we_per_way)) { + this->__Vdlyvval__data_structures__DOT__each_way__BRA__1__KET____DOT__data_structures__DOT__data__v32 + = (0xffU & this->__PVT__data_structures__DOT__data_write_per_way[4U]); + this->__Vdlyvset__data_structures__DOT__each_way__BRA__1__KET____DOT__data_structures__DOT__data__v32 = 1U; + this->__Vdlyvlsb__data_structures__DOT__each_way__BRA__1__KET____DOT__data_structures__DOT__data__v32 = 0U; + this->__Vdlyvdim0__data_structures__DOT__each_way__BRA__1__KET____DOT__data_structures__DOT__data__v32 + = (0x1fU & (vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__0__KET____DOT__bank_addr + >> 6U)); + } + if ((0x20000U & this->__PVT__data_structures__DOT__we_per_way)) { + this->__Vdlyvval__data_structures__DOT__each_way__BRA__1__KET____DOT__data_structures__DOT__data__v33 + = (0xffU & ((this->__PVT__data_structures__DOT__data_write_per_way[5U] + << 0x18U) | (this->__PVT__data_structures__DOT__data_write_per_way[4U] + >> 8U))); + this->__Vdlyvset__data_structures__DOT__each_way__BRA__1__KET____DOT__data_structures__DOT__data__v33 = 1U; + this->__Vdlyvlsb__data_structures__DOT__each_way__BRA__1__KET____DOT__data_structures__DOT__data__v33 = 8U; + this->__Vdlyvdim0__data_structures__DOT__each_way__BRA__1__KET____DOT__data_structures__DOT__data__v33 + = (0x1fU & (vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__0__KET____DOT__bank_addr + >> 6U)); + } + if ((0x40000U & this->__PVT__data_structures__DOT__we_per_way)) { + this->__Vdlyvval__data_structures__DOT__each_way__BRA__1__KET____DOT__data_structures__DOT__data__v34 + = (0xffU & ((this->__PVT__data_structures__DOT__data_write_per_way[5U] + << 0x10U) | (this->__PVT__data_structures__DOT__data_write_per_way[4U] + >> 0x10U))); + this->__Vdlyvset__data_structures__DOT__each_way__BRA__1__KET____DOT__data_structures__DOT__data__v34 = 1U; + this->__Vdlyvlsb__data_structures__DOT__each_way__BRA__1__KET____DOT__data_structures__DOT__data__v34 = 0x10U; + this->__Vdlyvdim0__data_structures__DOT__each_way__BRA__1__KET____DOT__data_structures__DOT__data__v34 + = (0x1fU & (vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__0__KET____DOT__bank_addr + >> 6U)); + } + if ((0x80000U & this->__PVT__data_structures__DOT__we_per_way)) { + this->__Vdlyvval__data_structures__DOT__each_way__BRA__1__KET____DOT__data_structures__DOT__data__v35 + = (0xffU & ((this->__PVT__data_structures__DOT__data_write_per_way[5U] + << 8U) | (this->__PVT__data_structures__DOT__data_write_per_way[4U] + >> 0x18U))); + this->__Vdlyvset__data_structures__DOT__each_way__BRA__1__KET____DOT__data_structures__DOT__data__v35 = 1U; + this->__Vdlyvlsb__data_structures__DOT__each_way__BRA__1__KET____DOT__data_structures__DOT__data__v35 = 0x18U; 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+ this->__PVT__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__data[0x1fU][0U] = 0U; + this->__PVT__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__data[0x1fU][1U] = 0U; + this->__PVT__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__data[0x1fU][2U] = 0U; + this->__PVT__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__data[0x1fU][3U] = 0U; + } + if (this->__Vdlyvset__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__data__v32) { + VL_ASSIGNSEL_WIII(8,(IData)(this->__Vdlyvlsb__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__data__v32), + this->__PVT__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__data + [this->__Vdlyvdim0__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__data__v32], this->__Vdlyvval__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__data__v32); + } + if (this->__Vdlyvset__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__data__v33) { + VL_ASSIGNSEL_WIII(8,(IData)(this->__Vdlyvlsb__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__data__v33), + this->__PVT__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__data + [this->__Vdlyvdim0__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__data__v33], this->__Vdlyvval__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__data__v33); + } + if (this->__Vdlyvset__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__data__v34) { + VL_ASSIGNSEL_WIII(8,(IData)(this->__Vdlyvlsb__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__data__v34), + this->__PVT__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__data + [this->__Vdlyvdim0__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__data__v34], this->__Vdlyvval__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__data__v34); + } + if (this->__Vdlyvset__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__data__v35) { + VL_ASSIGNSEL_WIII(8,(IData)(this->__Vdlyvlsb__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__data__v35), + this->__PVT__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__data + [this->__Vdlyvdim0__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__data__v35], this->__Vdlyvval__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__data__v35); + } + if (this->__Vdlyvset__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__data__v36) { + VL_ASSIGNSEL_WIII(8,(IData)(this->__Vdlyvlsb__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__data__v36), + this->__PVT__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__data + [this->__Vdlyvdim0__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__data__v36], this->__Vdlyvval__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__data__v36); + } + if (this->__Vdlyvset__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__data__v37) { + VL_ASSIGNSEL_WIII(8,(IData)(this->__Vdlyvlsb__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__data__v37), + this->__PVT__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__data + [this->__Vdlyvdim0__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__data__v37], this->__Vdlyvval__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__data__v37); + } + if (this->__Vdlyvset__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__data__v38) { + VL_ASSIGNSEL_WIII(8,(IData)(this->__Vdlyvlsb__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__data__v38), + this->__PVT__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__data + [this->__Vdlyvdim0__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__data__v38], this->__Vdlyvval__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__data__v38); + } + if (this->__Vdlyvset__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__data__v39) { + VL_ASSIGNSEL_WIII(8,(IData)(this->__Vdlyvlsb__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__data__v39), + this->__PVT__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__data + [this->__Vdlyvdim0__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__data__v39], this->__Vdlyvval__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__data__v39); + } + if (this->__Vdlyvset__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__data__v40) { + VL_ASSIGNSEL_WIII(8,(IData)(this->__Vdlyvlsb__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__data__v40), + this->__PVT__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__data + [this->__Vdlyvdim0__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__data__v40], this->__Vdlyvval__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__data__v40); + } + if (this->__Vdlyvset__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__data__v41) { + VL_ASSIGNSEL_WIII(8,(IData)(this->__Vdlyvlsb__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__data__v41), + this->__PVT__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__data + [this->__Vdlyvdim0__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__data__v41], this->__Vdlyvval__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__data__v41); + } + if (this->__Vdlyvset__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__data__v42) { + VL_ASSIGNSEL_WIII(8,(IData)(this->__Vdlyvlsb__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__data__v42), + this->__PVT__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__data + [this->__Vdlyvdim0__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__data__v42], this->__Vdlyvval__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__data__v42); + } + if (this->__Vdlyvset__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__data__v43) { + VL_ASSIGNSEL_WIII(8,(IData)(this->__Vdlyvlsb__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__data__v43), + this->__PVT__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__data + [this->__Vdlyvdim0__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__data__v43], this->__Vdlyvval__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__data__v43); + } + if (this->__Vdlyvset__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__data__v44) { + VL_ASSIGNSEL_WIII(8,(IData)(this->__Vdlyvlsb__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__data__v44), + this->__PVT__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__data + [this->__Vdlyvdim0__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__data__v44], this->__Vdlyvval__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__data__v44); + } + if (this->__Vdlyvset__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__data__v45) { + VL_ASSIGNSEL_WIII(8,(IData)(this->__Vdlyvlsb__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__data__v45), + this->__PVT__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__data + [this->__Vdlyvdim0__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__data__v45], this->__Vdlyvval__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__data__v45); + } + if (this->__Vdlyvset__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__data__v46) { + VL_ASSIGNSEL_WIII(8,(IData)(this->__Vdlyvlsb__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__data__v46), + this->__PVT__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__data + [this->__Vdlyvdim0__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__data__v46], this->__Vdlyvval__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__data__v46); + } + if (this->__Vdlyvset__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__data__v47) { + VL_ASSIGNSEL_WIII(8,(IData)(this->__Vdlyvlsb__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__data__v47), + this->__PVT__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__data + [this->__Vdlyvdim0__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__data__v47], this->__Vdlyvval__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__data__v47); + } +} + +VL_INLINE_OPT void Vcache_simX_VX_Cache_Bank__pi7::_combo__TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__9(Vcache_simX__Syms* __restrict vlSymsp) { + VL_DEBUG_IF(VL_DBG_MSGF("+ Vcache_simX_VX_Cache_Bank__pi7::_combo__TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__9\n"); ); + Vcache_simX* __restrict vlTOPp VL_ATTR_UNUSED = vlSymsp->TOPp; + // Variables + WData/*31:0*/ __Vtemp75[4]; + WData/*31:0*/ __Vtemp76[4]; + WData/*31:0*/ __Vtemp77[4]; + WData/*31:0*/ __Vtemp78[4]; + WData/*31:0*/ __Vtemp79[4]; + WData/*31:0*/ __Vtemp80[4]; + WData/*31:0*/ __Vtemp81[4]; + // Body + this->__PVT__write_from_mem = ((2U == (IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT__state)) + & (IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__0__KET____DOT__use_valid_in)); + this->__PVT__access = ((0U == (IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT__state)) + & (IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__0__KET____DOT__use_valid_in)); + this->data_structures__DOT____Vcellout__each_way__BRA__0__KET____DOT__data_structures__dirty_use + = this->__PVT__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__dirty + [(0x1fU & (vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__0__KET____DOT__bank_addr + >> 6U))]; + this->data_structures__DOT____Vcellout__each_way__BRA__1__KET____DOT__data_structures__dirty_use + = this->__PVT__data_structures__DOT__each_way__BRA__1__KET____DOT__data_structures__DOT__dirty + [(0x1fU & (vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__0__KET____DOT__bank_addr + >> 6U))]; + __Vtemp75[0U] = 0U; + __Vtemp75[1U] = 0U; + __Vtemp75[2U] = 0U; + __Vtemp75[3U] = 0U; + __Vtemp76[0U] = 0U; + __Vtemp76[1U] = 0U; + __Vtemp76[2U] = 0U; + __Vtemp76[3U] = 0U; + __Vtemp77[0U] = 0U; + __Vtemp77[1U] = 0U; + __Vtemp77[2U] = 0U; + __Vtemp77[3U] = 0U; + __Vtemp78[0U] = 0U; + __Vtemp78[1U] = 0U; + __Vtemp78[2U] = 0U; + __Vtemp78[3U] = 0U; + __Vtemp79[0U] = 0U; + __Vtemp79[1U] = 0U; + __Vtemp79[2U] = 0U; + __Vtemp79[3U] = 0U; + __Vtemp80[0U] = 0U; + __Vtemp80[1U] = 0U; + __Vtemp80[2U] = 0U; + __Vtemp80[3U] = 0U; + __Vtemp81[0U] = 0U; + __Vtemp81[1U] = 0U; + __Vtemp81[2U] = 0U; + __Vtemp81[3U] = 0U; + this->__PVT__use_write_data = ((0U == (IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__cache_driver_in_mem_write)) + ? ((1U == (3U & vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__0__KET____DOT__bank_addr)) + ? (0xff00U + & (__Vtemp75[ + (3U & (IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT__index_per_bank))] + << 8U)) + : ((2U == (3U + & vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__0__KET____DOT__bank_addr)) + ? (0xff0000U + & (__Vtemp76[ + (3U + & (IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT__index_per_bank))] + << 0x10U)) + : ((3U + == + (3U + & vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__0__KET____DOT__bank_addr)) + ? (0xff000000U + & (__Vtemp77[ + (3U + & (IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT__index_per_bank))] + << 0x18U)) + : __Vtemp78[ + (3U + & (IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT__index_per_bank))]))) + : ((1U == (IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__cache_driver_in_mem_write)) + ? ((2U == (3U + & vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__0__KET____DOT__bank_addr)) + ? (0xffff0000U + & (__Vtemp79[ + (3U + & (IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT__index_per_bank))] + << 0x10U)) + : __Vtemp80[ + (3U & (IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT__index_per_bank))]) + : __Vtemp81[ + (3U & (IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT__index_per_bank))])); + this->__PVT__sb_mask = ((0U == (3U & vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__0__KET____DOT__bank_addr)) + ? 1U : ((1U == (3U & vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__0__KET____DOT__bank_addr)) + ? 2U : ((2U == + (3U + & vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__0__KET____DOT__bank_addr)) + ? 4U + : 8U))); + this->__PVT__data_structures__DOT__data_use_per_way[0U] + = this->__PVT__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__data + [(0x1fU & (vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__0__KET____DOT__bank_addr + >> 6U))][0U]; + this->__PVT__data_structures__DOT__data_use_per_way[1U] + = this->__PVT__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__data + [(0x1fU & (vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__0__KET____DOT__bank_addr + >> 6U))][1U]; + this->__PVT__data_structures__DOT__data_use_per_way[2U] + = this->__PVT__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__data + [(0x1fU & (vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__0__KET____DOT__bank_addr + >> 6U))][2U]; + this->__PVT__data_structures__DOT__data_use_per_way[3U] + = this->__PVT__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__data + [(0x1fU & (vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__0__KET____DOT__bank_addr + >> 6U))][3U]; + this->__PVT__data_structures__DOT__data_use_per_way[4U] + = this->__PVT__data_structures__DOT__each_way__BRA__1__KET____DOT__data_structures__DOT__data + [(0x1fU & (vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__0__KET____DOT__bank_addr + >> 6U))][0U]; + this->__PVT__data_structures__DOT__data_use_per_way[5U] + = this->__PVT__data_structures__DOT__each_way__BRA__1__KET____DOT__data_structures__DOT__data + [(0x1fU & (vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__0__KET____DOT__bank_addr + >> 6U))][1U]; + this->__PVT__data_structures__DOT__data_use_per_way[6U] + = this->__PVT__data_structures__DOT__each_way__BRA__1__KET____DOT__data_structures__DOT__data + [(0x1fU & (vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__0__KET____DOT__bank_addr + >> 6U))][2U]; + this->__PVT__data_structures__DOT__data_use_per_way[7U] + = this->__PVT__data_structures__DOT__each_way__BRA__1__KET____DOT__data_structures__DOT__data + [(0x1fU & (vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__0__KET____DOT__bank_addr + >> 6U))][3U]; + this->__PVT__data_structures__DOT__valid_use_per_way + = ((2U & (IData)(this->__PVT__data_structures__DOT__valid_use_per_way)) + | this->__PVT__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__valid + [(0x1fU & (vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__0__KET____DOT__bank_addr + >> 6U))]); + this->__PVT__data_structures__DOT__valid_use_per_way + = ((1U & (IData)(this->__PVT__data_structures__DOT__valid_use_per_way)) + | (this->__PVT__data_structures__DOT__each_way__BRA__1__KET____DOT__data_structures__DOT__valid + [(0x1fU & (vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__0__KET____DOT__bank_addr + >> 6U))] << 1U)); + this->__PVT__data_structures__DOT__tag_use_per_way + = ((VL_ULL(0x3ffffe00000) & this->__PVT__data_structures__DOT__tag_use_per_way) + | (IData)((IData)(this->__PVT__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__tag + [(0x1fU & (vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__0__KET____DOT__bank_addr + >> 6U))]))); + this->__PVT__data_structures__DOT__tag_use_per_way + = ((VL_ULL(0x1fffff) & this->__PVT__data_structures__DOT__tag_use_per_way) + | ((QData)((IData)(this->__PVT__data_structures__DOT__each_way__BRA__1__KET____DOT__data_structures__DOT__tag + [(0x1fU & (vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__0__KET____DOT__bank_addr + >> 6U))])) + << 0x15U)); + this->__PVT__data_structures__DOT__dirty_use_per_way + = ((2U & (IData)(this->__PVT__data_structures__DOT__dirty_use_per_way)) + | (IData)(this->data_structures__DOT____Vcellout__each_way__BRA__0__KET____DOT__data_structures__dirty_use)); + this->__PVT__data_structures__DOT__dirty_use_per_way + = ((1U & (IData)(this->__PVT__data_structures__DOT__dirty_use_per_way)) + | ((IData)(this->data_structures__DOT____Vcellout__each_way__BRA__1__KET____DOT__data_structures__dirty_use) + << 1U)); + this->__PVT__data_write[0U] = ((IData)(this->__PVT__write_from_mem) + ? vlSymsp->TOP__cache_simX__DOT__VX_dram_req_rsp.i_m_readdata[0U] + : this->__PVT__use_write_data); + this->__PVT__data_write[1U] = ((IData)(this->__PVT__write_from_mem) + ? vlSymsp->TOP__cache_simX__DOT__VX_dram_req_rsp.i_m_readdata[1U] + : this->__PVT__use_write_data); + this->__PVT__data_write[2U] = ((IData)(this->__PVT__write_from_mem) + ? vlSymsp->TOP__cache_simX__DOT__VX_dram_req_rsp.i_m_readdata[2U] + : this->__PVT__use_write_data); + this->__PVT__data_write[3U] = ((IData)(this->__PVT__write_from_mem) + ? vlSymsp->TOP__cache_simX__DOT__VX_dram_req_rsp.i_m_readdata[3U] + : this->__PVT__use_write_data); + this->__PVT__data_structures__DOT__invalid_found = 0U; + if ((1U & (~ ((IData)(this->__PVT__data_structures__DOT__valid_use_per_way) + >> 1U)))) { + this->__PVT__data_structures__DOT__invalid_found = 1U; + } + if ((1U & (~ (IData)(this->__PVT__data_structures__DOT__valid_use_per_way)))) { + this->__PVT__data_structures__DOT__invalid_found = 1U; + } + this->__PVT__data_structures__DOT__invalid_index = 0U; + if ((1U & (~ ((IData)(this->__PVT__data_structures__DOT__valid_use_per_way) + >> 1U)))) { + this->__PVT__data_structures__DOT__invalid_index = 1U; + } + if ((1U & (~ (IData)(this->__PVT__data_structures__DOT__valid_use_per_way)))) { + this->__PVT__data_structures__DOT__invalid_index = 0U; + } + this->__PVT__data_structures__DOT__hit_per_way + = ((2U & (IData)(this->__PVT__data_structures__DOT__hit_per_way)) + | (((IData)(this->__PVT__data_structures__DOT__valid_use_per_way) + & ((0x1fffffU & (IData)(this->__PVT__data_structures__DOT__tag_use_per_way)) + == (0x1fffffU & (vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__0__KET____DOT__bank_addr + >> 0xbU)))) ? 1U + : 0U)); + this->__PVT__data_structures__DOT__hit_per_way + = ((1U & (IData)(this->__PVT__data_structures__DOT__hit_per_way)) + | (((((IData)(this->__PVT__data_structures__DOT__valid_use_per_way) + >> 1U) & ((0x1fffffU & (IData)((this->__PVT__data_structures__DOT__tag_use_per_way + >> 0x15U))) + == (0x1fffffU & (vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__0__KET____DOT__bank_addr + >> 0xbU)))) + ? 1U : 0U) << 1U)); + this->__PVT__data_structures__DOT__data_write_per_way[0U] + = this->__PVT__data_write[0U]; + this->__PVT__data_structures__DOT__data_write_per_way[1U] + = this->__PVT__data_write[1U]; + this->__PVT__data_structures__DOT__data_write_per_way[2U] + = this->__PVT__data_write[2U]; + this->__PVT__data_structures__DOT__data_write_per_way[3U] + = this->__PVT__data_write[3U]; + this->__PVT__data_structures__DOT__data_write_per_way[4U] + = this->__PVT__data_write[0U]; + this->__PVT__data_structures__DOT__data_write_per_way[5U] + = this->__PVT__data_write[1U]; + this->__PVT__data_structures__DOT__data_write_per_way[6U] + = this->__PVT__data_write[2U]; + this->__PVT__data_structures__DOT__data_write_per_way[7U] + = this->__PVT__data_write[3U]; + this->__PVT__data_structures__DOT__genblk1__DOT__way_indexing__DOT__found = 0U; + if ((2U & (IData)(this->__PVT__data_structures__DOT__hit_per_way))) { + this->__PVT__data_structures__DOT__genblk1__DOT__way_indexing__DOT__found = 1U; + } + if ((1U & (IData)(this->__PVT__data_structures__DOT__hit_per_way))) { + this->__PVT__data_structures__DOT__genblk1__DOT__way_indexing__DOT__found = 1U; + } + this->__PVT__data_structures__DOT__way_index = 0U; + if ((2U & (IData)(this->__PVT__data_structures__DOT__hit_per_way))) { + this->__PVT__data_structures__DOT__way_index = 1U; + } + if ((1U & (IData)(this->__PVT__data_structures__DOT__hit_per_way))) { + this->__PVT__data_structures__DOT__way_index = 0U; + } + this->__PVT__data_structures__DOT__way_use_Qual + = ((0U != (IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT__state)) + ? (IData)(this->__PVT__way_to_update) : (IData)(this->__PVT__data_structures__DOT__way_index)); + this->__PVT__data_structures__DOT__write_from_mem_per_way + = ((2U & (IData)(this->__PVT__data_structures__DOT__write_from_mem_per_way)) + | ((IData)(this->__PVT__write_from_mem) + & (~ (IData)(this->__PVT__data_structures__DOT__way_use_Qual)))); + this->__PVT__data_structures__DOT__write_from_mem_per_way + = ((1U & (IData)(this->__PVT__data_structures__DOT__write_from_mem_per_way)) + | (((IData)(this->__PVT__write_from_mem) + & (IData)(this->__PVT__data_structures__DOT__way_use_Qual)) + << 1U)); + this->__Vcellout__data_structures__data_use[0U] + = (((0U == (0x1fU & ((IData)(this->__PVT__data_structures__DOT__way_use_Qual) + << 7U))) ? 0U : (this->__PVT__data_structures__DOT__data_use_per_way[ + ((IData)(1U) + + (4U + & ((IData)(this->__PVT__data_structures__DOT__way_use_Qual) + << 2U)))] + << ((IData)(0x20U) + - + (0x1fU + & ((IData)(this->__PVT__data_structures__DOT__way_use_Qual) + << 7U))))) + | (this->__PVT__data_structures__DOT__data_use_per_way[ + (4U & ((IData)(this->__PVT__data_structures__DOT__way_use_Qual) + << 2U))] >> (0x1fU & ((IData)(this->__PVT__data_structures__DOT__way_use_Qual) + << 7U)))); + this->__Vcellout__data_structures__data_use[1U] + = (((0U == (0x1fU & ((IData)(this->__PVT__data_structures__DOT__way_use_Qual) + << 7U))) ? 0U : (this->__PVT__data_structures__DOT__data_use_per_way[ + ((IData)(2U) + + (4U + & ((IData)(this->__PVT__data_structures__DOT__way_use_Qual) + << 2U)))] + << ((IData)(0x20U) + - + (0x1fU + & ((IData)(this->__PVT__data_structures__DOT__way_use_Qual) + << 7U))))) + | (this->__PVT__data_structures__DOT__data_use_per_way[ + ((IData)(1U) + (4U & ((IData)(this->__PVT__data_structures__DOT__way_use_Qual) + << 2U)))] >> (0x1fU + & ((IData)(this->__PVT__data_structures__DOT__way_use_Qual) + << 7U)))); + this->__Vcellout__data_structures__data_use[2U] + = (((0U == (0x1fU & ((IData)(this->__PVT__data_structures__DOT__way_use_Qual) + << 7U))) ? 0U : (this->__PVT__data_structures__DOT__data_use_per_way[ + ((IData)(3U) + + (4U + & ((IData)(this->__PVT__data_structures__DOT__way_use_Qual) + << 2U)))] + << ((IData)(0x20U) + - + (0x1fU + & ((IData)(this->__PVT__data_structures__DOT__way_use_Qual) + << 7U))))) + | (this->__PVT__data_structures__DOT__data_use_per_way[ + ((IData)(2U) + (4U & ((IData)(this->__PVT__data_structures__DOT__way_use_Qual) + << 2U)))] >> (0x1fU + & ((IData)(this->__PVT__data_structures__DOT__way_use_Qual) + << 7U)))); + this->__Vcellout__data_structures__data_use[3U] + = (((0U == (0x1fU & ((IData)(this->__PVT__data_structures__DOT__way_use_Qual) + << 7U))) ? 0U : (this->__PVT__data_structures__DOT__data_use_per_way[ + ((IData)(4U) + + (4U + & ((IData)(this->__PVT__data_structures__DOT__way_use_Qual) + << 2U)))] + << ((IData)(0x20U) + - + (0x1fU + & ((IData)(this->__PVT__data_structures__DOT__way_use_Qual) + << 7U))))) + | (this->__PVT__data_structures__DOT__data_use_per_way[ + ((IData)(3U) + (4U & ((IData)(this->__PVT__data_structures__DOT__way_use_Qual) + << 2U)))] >> (0x1fU + & ((IData)(this->__PVT__data_structures__DOT__way_use_Qual) + << 7U)))); + this->__PVT__valid_use = (1U & ((IData)(this->__PVT__data_structures__DOT__valid_use_per_way) + >> (IData)(this->__PVT__data_structures__DOT__way_use_Qual))); + this->__PVT__tag_use = ((0x29U >= (0x3fU & ((IData)(0x15U) + * (IData)(this->__PVT__data_structures__DOT__way_use_Qual)))) + ? (0x1fffffU & (IData)( + (this->__PVT__data_structures__DOT__tag_use_per_way + >> + (0x3fU + & ((IData)(0x15U) + * (IData)(this->__PVT__data_structures__DOT__way_use_Qual)))))) + : 0U); + this->__PVT__data_unQual = (((0U == (3U & vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__0__KET____DOT__bank_addr)) + | (2U == (IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__cache_driver_in_mem_read))) + ? this->__Vcellout__data_structures__data_use[ + (3U & (vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__0__KET____DOT__bank_addr + >> 4U))] : ( + (1U + == + (3U + & vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__0__KET____DOT__bank_addr)) + ? + (this->__Vcellout__data_structures__data_use[ + (3U + & (vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__0__KET____DOT__bank_addr + >> 4U))] + >> 8U) + : + ((2U + == + (3U + & vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__0__KET____DOT__bank_addr)) + ? + (this->__Vcellout__data_structures__data_use[ + (3U + & (vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__0__KET____DOT__bank_addr + >> 4U))] + >> 0x10U) + : + (this->__Vcellout__data_structures__data_use[ + (3U + & (vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__0__KET____DOT__bank_addr + >> 4U))] + >> 0x18U)))); + this->__PVT__miss = (((this->__PVT__tag_use != + (0x1fffffU & (vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__0__KET____DOT__bank_addr + >> 0xbU))) + & (IData)(this->__PVT__valid_use)) + & (IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__0__KET____DOT__use_valid_in)); + this->__PVT__genblk1__BRA__0__KET____DOT__normal_write + = (((IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__read_or_write) + & ((IData)(this->__PVT__access) & (0U == + (3U + & (vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__0__KET____DOT__bank_addr + >> 4U))))) + & (~ (IData)(this->__PVT__miss))); + this->__PVT__genblk1__BRA__1__KET____DOT__normal_write + = (((IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__read_or_write) + & ((IData)(this->__PVT__access) & (1U == + (3U + & (vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__0__KET____DOT__bank_addr + >> 4U))))) + & (~ (IData)(this->__PVT__miss))); + this->__PVT__genblk1__BRA__2__KET____DOT__normal_write + = (((IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__read_or_write) + & ((IData)(this->__PVT__access) & (2U == + (3U + & (vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__0__KET____DOT__bank_addr + >> 4U))))) + & (~ (IData)(this->__PVT__miss))); + this->__PVT__genblk1__BRA__3__KET____DOT__normal_write + = (((IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__read_or_write) + & ((IData)(this->__PVT__access) & (3U == + (3U + & (vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__0__KET____DOT__bank_addr + >> 4U))))) + & (~ (IData)(this->__PVT__miss))); + this->__PVT__we = ((0xfff0U & (IData)(this->__PVT__we)) + | ((IData)(this->__PVT__write_from_mem) + ? 0xfU : (((IData)(this->__PVT__genblk1__BRA__0__KET____DOT__normal_write) + & (2U == (IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__cache_driver_in_mem_write))) + ? 0xfU : (((IData)(this->__PVT__genblk1__BRA__0__KET____DOT__normal_write) + & (0U + == (IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__cache_driver_in_mem_write))) + ? (IData)(this->__PVT__sb_mask) + : + (((IData)(this->__PVT__genblk1__BRA__0__KET____DOT__normal_write) + & (1U + == (IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__cache_driver_in_mem_write))) + ? + ((0U + == + (3U + & vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__0__KET____DOT__bank_addr)) + ? 3U + : 0xcU) + : 0U))))); + this->__PVT__we = ((0xff0fU & (IData)(this->__PVT__we)) + | (((IData)(this->__PVT__write_from_mem) + ? 0xfU : (((IData)(this->__PVT__genblk1__BRA__1__KET____DOT__normal_write) + & (2U == (IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__cache_driver_in_mem_write))) + ? 0xfU : (((IData)(this->__PVT__genblk1__BRA__1__KET____DOT__normal_write) + & (0U + == (IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__cache_driver_in_mem_write))) + ? (IData)(this->__PVT__sb_mask) + : + (((IData)(this->__PVT__genblk1__BRA__1__KET____DOT__normal_write) + & (1U + == (IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__cache_driver_in_mem_write))) + ? + ((0U + == + (3U + & vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__0__KET____DOT__bank_addr)) + ? 3U + : 0xcU) + : 0U)))) + << 4U)); + this->__PVT__we = ((0xf0ffU & (IData)(this->__PVT__we)) + | (((IData)(this->__PVT__write_from_mem) + ? 0xfU : (((IData)(this->__PVT__genblk1__BRA__2__KET____DOT__normal_write) + & (2U == (IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__cache_driver_in_mem_write))) + ? 0xfU : (((IData)(this->__PVT__genblk1__BRA__2__KET____DOT__normal_write) + & (0U + == (IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__cache_driver_in_mem_write))) + ? (IData)(this->__PVT__sb_mask) + : + (((IData)(this->__PVT__genblk1__BRA__2__KET____DOT__normal_write) + & (1U + == (IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__cache_driver_in_mem_write))) + ? + ((0U + == + (3U + & vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__0__KET____DOT__bank_addr)) + ? 3U + : 0xcU) + : 0U)))) + << 8U)); + this->__PVT__we = ((0xfffU & (IData)(this->__PVT__we)) + | (((IData)(this->__PVT__write_from_mem) + ? 0xfU : (((IData)(this->__PVT__genblk1__BRA__3__KET____DOT__normal_write) + & (2U == (IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__cache_driver_in_mem_write))) + ? 0xfU : (((IData)(this->__PVT__genblk1__BRA__3__KET____DOT__normal_write) + & (0U + == (IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__cache_driver_in_mem_write))) + ? (IData)(this->__PVT__sb_mask) + : + (((IData)(this->__PVT__genblk1__BRA__3__KET____DOT__normal_write) + & (1U + == (IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__cache_driver_in_mem_write))) + ? + ((0U + == + (3U + & vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__0__KET____DOT__bank_addr)) + ? 3U + : 0xcU) + : 0U)))) + << 0xcU)); + this->__PVT__data_structures__DOT__we_per_way = + ((0xffff0000U & this->__PVT__data_structures__DOT__we_per_way) + | ((IData)(this->__PVT__data_structures__DOT__way_use_Qual) + ? 0U : (0xffffU & (IData)(this->__PVT__we)))); + this->__PVT__data_structures__DOT__we_per_way = + ((0xffffU & this->__PVT__data_structures__DOT__we_per_way) + | (((IData)(this->__PVT__data_structures__DOT__way_use_Qual) + ? (0xffffU & (IData)(this->__PVT__we)) + : 0U) << 0x10U)); +} + +void Vcache_simX_VX_Cache_Bank__pi7::_settle__TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__1__KET____DOT__bank_structure__2(Vcache_simX__Syms* __restrict vlSymsp) { + VL_DEBUG_IF(VL_DBG_MSGF("+ Vcache_simX_VX_Cache_Bank__pi7::_settle__TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__1__KET____DOT__bank_structure__2\n"); ); + Vcache_simX* __restrict vlTOPp VL_ATTR_UNUSED = vlSymsp->TOPp; + // Variables + WData/*31:0*/ __Vtemp85[4]; + WData/*31:0*/ __Vtemp86[4]; + WData/*31:0*/ __Vtemp87[4]; + WData/*31:0*/ __Vtemp88[4]; + WData/*31:0*/ __Vtemp89[4]; + WData/*31:0*/ __Vtemp90[4]; + WData/*31:0*/ __Vtemp91[4]; + // Body + this->__PVT__way_to_update = vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT__global_way_to_evict; + this->__PVT__write_from_mem = ((2U == (IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT__state)) + & (IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__1__KET____DOT__use_valid_in)); + this->__PVT__access = ((0U == (IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT__state)) + & (IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__1__KET____DOT__use_valid_in)); + this->data_structures__DOT____Vcellout__each_way__BRA__0__KET____DOT__data_structures__dirty_use + = this->__PVT__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__dirty + [(0x1fU & (vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__1__KET____DOT__bank_addr + >> 6U))]; + this->data_structures__DOT____Vcellout__each_way__BRA__1__KET____DOT__data_structures__dirty_use + = this->__PVT__data_structures__DOT__each_way__BRA__1__KET____DOT__data_structures__DOT__dirty + [(0x1fU & (vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__1__KET____DOT__bank_addr + >> 6U))]; + __Vtemp85[0U] = 0U; + __Vtemp85[1U] = 0U; + __Vtemp85[2U] = 0U; + __Vtemp85[3U] = 0U; + __Vtemp86[0U] = 0U; + __Vtemp86[1U] = 0U; + __Vtemp86[2U] = 0U; + __Vtemp86[3U] = 0U; + __Vtemp87[0U] = 0U; + __Vtemp87[1U] = 0U; + __Vtemp87[2U] = 0U; + __Vtemp87[3U] = 0U; + __Vtemp88[0U] = 0U; + __Vtemp88[1U] = 0U; + __Vtemp88[2U] = 0U; + __Vtemp88[3U] = 0U; + __Vtemp89[0U] = 0U; + __Vtemp89[1U] = 0U; + __Vtemp89[2U] = 0U; + __Vtemp89[3U] = 0U; + __Vtemp90[0U] = 0U; + __Vtemp90[1U] = 0U; + __Vtemp90[2U] = 0U; + __Vtemp90[3U] = 0U; + __Vtemp91[0U] = 0U; + __Vtemp91[1U] = 0U; + __Vtemp91[2U] = 0U; + __Vtemp91[3U] = 0U; + this->__PVT__use_write_data = ((0U == (IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__cache_driver_in_mem_write)) + ? ((1U == (3U & vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__1__KET____DOT__bank_addr)) + ? (0xff00U + & (__Vtemp85[ + (3U & + ((IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT__index_per_bank) + >> 2U))] + << 8U)) + : ((2U == (3U + & vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__1__KET____DOT__bank_addr)) + ? (0xff0000U + & (__Vtemp86[ + (3U + & ((IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT__index_per_bank) + >> 2U))] + << 0x10U)) + : ((3U + == + (3U + & vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__1__KET____DOT__bank_addr)) + ? (0xff000000U + & (__Vtemp87[ + (3U + & ((IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT__index_per_bank) + >> 2U))] + << 0x18U)) + : __Vtemp88[ + (3U + & ((IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT__index_per_bank) + >> 2U))]))) + : ((1U == (IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__cache_driver_in_mem_write)) + ? ((2U == (3U + & vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__1__KET____DOT__bank_addr)) + ? (0xffff0000U + & (__Vtemp89[ + (3U + & ((IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT__index_per_bank) + >> 2U))] + << 0x10U)) + : __Vtemp90[ + (3U & ((IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT__index_per_bank) + >> 2U))]) + : __Vtemp91[ + (3U & ((IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT__index_per_bank) + >> 2U))])); + this->__PVT__sb_mask = ((0U == (3U & vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__1__KET____DOT__bank_addr)) + ? 1U : ((1U == (3U & vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__1__KET____DOT__bank_addr)) + ? 2U : ((2U == + (3U + & vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__1__KET____DOT__bank_addr)) + ? 4U + : 8U))); + this->__PVT__data_structures__DOT__data_use_per_way[0U] + = this->__PVT__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__data + [(0x1fU & (vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__1__KET____DOT__bank_addr + >> 6U))][0U]; + this->__PVT__data_structures__DOT__data_use_per_way[1U] + = this->__PVT__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__data + [(0x1fU & (vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__1__KET____DOT__bank_addr + >> 6U))][1U]; + this->__PVT__data_structures__DOT__data_use_per_way[2U] + = this->__PVT__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__data + [(0x1fU & (vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__1__KET____DOT__bank_addr + >> 6U))][2U]; + this->__PVT__data_structures__DOT__data_use_per_way[3U] + = this->__PVT__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__data + [(0x1fU & (vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__1__KET____DOT__bank_addr + >> 6U))][3U]; + this->__PVT__data_structures__DOT__data_use_per_way[4U] + = this->__PVT__data_structures__DOT__each_way__BRA__1__KET____DOT__data_structures__DOT__data + [(0x1fU & (vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__1__KET____DOT__bank_addr + >> 6U))][0U]; + this->__PVT__data_structures__DOT__data_use_per_way[5U] + = this->__PVT__data_structures__DOT__each_way__BRA__1__KET____DOT__data_structures__DOT__data + [(0x1fU & (vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__1__KET____DOT__bank_addr + >> 6U))][1U]; + this->__PVT__data_structures__DOT__data_use_per_way[6U] + = this->__PVT__data_structures__DOT__each_way__BRA__1__KET____DOT__data_structures__DOT__data + [(0x1fU & (vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__1__KET____DOT__bank_addr + >> 6U))][2U]; + this->__PVT__data_structures__DOT__data_use_per_way[7U] + = this->__PVT__data_structures__DOT__each_way__BRA__1__KET____DOT__data_structures__DOT__data + [(0x1fU & (vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__1__KET____DOT__bank_addr + >> 6U))][3U]; + this->__PVT__data_structures__DOT__valid_use_per_way + = ((2U & (IData)(this->__PVT__data_structures__DOT__valid_use_per_way)) + | this->__PVT__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__valid + [(0x1fU & (vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__1__KET____DOT__bank_addr + >> 6U))]); + this->__PVT__data_structures__DOT__valid_use_per_way + = ((1U & (IData)(this->__PVT__data_structures__DOT__valid_use_per_way)) + | (this->__PVT__data_structures__DOT__each_way__BRA__1__KET____DOT__data_structures__DOT__valid + [(0x1fU & (vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__1__KET____DOT__bank_addr + >> 6U))] << 1U)); + this->__PVT__data_structures__DOT__tag_use_per_way + = ((VL_ULL(0x3ffffe00000) & this->__PVT__data_structures__DOT__tag_use_per_way) + | (IData)((IData)(this->__PVT__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__tag + [(0x1fU & (vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__1__KET____DOT__bank_addr + >> 6U))]))); + this->__PVT__data_structures__DOT__tag_use_per_way + = ((VL_ULL(0x1fffff) & this->__PVT__data_structures__DOT__tag_use_per_way) + | ((QData)((IData)(this->__PVT__data_structures__DOT__each_way__BRA__1__KET____DOT__data_structures__DOT__tag + [(0x1fU & (vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__1__KET____DOT__bank_addr + >> 6U))])) + << 0x15U)); + this->__PVT__data_structures__DOT__dirty_use_per_way + = ((2U & (IData)(this->__PVT__data_structures__DOT__dirty_use_per_way)) + | (IData)(this->data_structures__DOT____Vcellout__each_way__BRA__0__KET____DOT__data_structures__dirty_use)); + this->__PVT__data_structures__DOT__dirty_use_per_way + = ((1U & (IData)(this->__PVT__data_structures__DOT__dirty_use_per_way)) + | ((IData)(this->data_structures__DOT____Vcellout__each_way__BRA__1__KET____DOT__data_structures__dirty_use) + << 1U)); + this->__PVT__data_write[0U] = ((IData)(this->__PVT__write_from_mem) + ? vlSymsp->TOP__cache_simX__DOT__VX_dram_req_rsp.i_m_readdata[4U] + : this->__PVT__use_write_data); + this->__PVT__data_write[1U] = ((IData)(this->__PVT__write_from_mem) + ? vlSymsp->TOP__cache_simX__DOT__VX_dram_req_rsp.i_m_readdata[5U] + : this->__PVT__use_write_data); + this->__PVT__data_write[2U] = ((IData)(this->__PVT__write_from_mem) + ? vlSymsp->TOP__cache_simX__DOT__VX_dram_req_rsp.i_m_readdata[6U] + : this->__PVT__use_write_data); + this->__PVT__data_write[3U] = ((IData)(this->__PVT__write_from_mem) + ? vlSymsp->TOP__cache_simX__DOT__VX_dram_req_rsp.i_m_readdata[7U] + : this->__PVT__use_write_data); + this->__PVT__data_structures__DOT__invalid_found = 0U; + if ((1U & (~ ((IData)(this->__PVT__data_structures__DOT__valid_use_per_way) + >> 1U)))) { + this->__PVT__data_structures__DOT__invalid_found = 1U; + } + if ((1U & (~ (IData)(this->__PVT__data_structures__DOT__valid_use_per_way)))) { + this->__PVT__data_structures__DOT__invalid_found = 1U; + } + this->__PVT__data_structures__DOT__invalid_index = 0U; + if ((1U & (~ ((IData)(this->__PVT__data_structures__DOT__valid_use_per_way) + >> 1U)))) { + this->__PVT__data_structures__DOT__invalid_index = 1U; + } + if ((1U & (~ (IData)(this->__PVT__data_structures__DOT__valid_use_per_way)))) { + this->__PVT__data_structures__DOT__invalid_index = 0U; + } + this->__PVT__data_structures__DOT__hit_per_way + = ((2U & (IData)(this->__PVT__data_structures__DOT__hit_per_way)) + | (((IData)(this->__PVT__data_structures__DOT__valid_use_per_way) + & ((0x1fffffU & (IData)(this->__PVT__data_structures__DOT__tag_use_per_way)) + == (0x1fffffU & (vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__1__KET____DOT__bank_addr + >> 0xbU)))) ? 1U + : 0U)); + this->__PVT__data_structures__DOT__hit_per_way + = ((1U & (IData)(this->__PVT__data_structures__DOT__hit_per_way)) + | (((((IData)(this->__PVT__data_structures__DOT__valid_use_per_way) + >> 1U) & ((0x1fffffU & (IData)((this->__PVT__data_structures__DOT__tag_use_per_way + >> 0x15U))) + == (0x1fffffU & (vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__1__KET____DOT__bank_addr + >> 0xbU)))) + ? 1U : 0U) << 1U)); + this->__PVT__data_structures__DOT__data_write_per_way[0U] + = this->__PVT__data_write[0U]; + this->__PVT__data_structures__DOT__data_write_per_way[1U] + = this->__PVT__data_write[1U]; + this->__PVT__data_structures__DOT__data_write_per_way[2U] + = this->__PVT__data_write[2U]; + this->__PVT__data_structures__DOT__data_write_per_way[3U] + = this->__PVT__data_write[3U]; + this->__PVT__data_structures__DOT__data_write_per_way[4U] + = this->__PVT__data_write[0U]; + this->__PVT__data_structures__DOT__data_write_per_way[5U] + = this->__PVT__data_write[1U]; + this->__PVT__data_structures__DOT__data_write_per_way[6U] + = this->__PVT__data_write[2U]; + this->__PVT__data_structures__DOT__data_write_per_way[7U] + = this->__PVT__data_write[3U]; + this->__PVT__data_structures__DOT__genblk1__DOT__way_indexing__DOT__found = 0U; + if ((2U & (IData)(this->__PVT__data_structures__DOT__hit_per_way))) { + this->__PVT__data_structures__DOT__genblk1__DOT__way_indexing__DOT__found = 1U; + } + if ((1U & (IData)(this->__PVT__data_structures__DOT__hit_per_way))) { + this->__PVT__data_structures__DOT__genblk1__DOT__way_indexing__DOT__found = 1U; + } + this->__PVT__data_structures__DOT__way_index = 0U; + if ((2U & (IData)(this->__PVT__data_structures__DOT__hit_per_way))) { + this->__PVT__data_structures__DOT__way_index = 1U; + } + if ((1U & (IData)(this->__PVT__data_structures__DOT__hit_per_way))) { + this->__PVT__data_structures__DOT__way_index = 0U; + } + this->__PVT__data_structures__DOT__way_use_Qual + = ((0U != (IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT__state)) + ? (IData)(this->__PVT__way_to_update) : (IData)(this->__PVT__data_structures__DOT__way_index)); + this->__PVT__data_structures__DOT__write_from_mem_per_way + = ((2U & (IData)(this->__PVT__data_structures__DOT__write_from_mem_per_way)) + | ((IData)(this->__PVT__write_from_mem) + & (~ (IData)(this->__PVT__data_structures__DOT__way_use_Qual)))); + this->__PVT__data_structures__DOT__write_from_mem_per_way + = ((1U & (IData)(this->__PVT__data_structures__DOT__write_from_mem_per_way)) + | (((IData)(this->__PVT__write_from_mem) + & (IData)(this->__PVT__data_structures__DOT__way_use_Qual)) + << 1U)); + this->__Vcellout__data_structures__data_use[0U] + = (((0U == (0x1fU & ((IData)(this->__PVT__data_structures__DOT__way_use_Qual) + << 7U))) ? 0U : (this->__PVT__data_structures__DOT__data_use_per_way[ + ((IData)(1U) + + (4U + & ((IData)(this->__PVT__data_structures__DOT__way_use_Qual) + << 2U)))] + << ((IData)(0x20U) + - + (0x1fU + & ((IData)(this->__PVT__data_structures__DOT__way_use_Qual) + << 7U))))) + | (this->__PVT__data_structures__DOT__data_use_per_way[ + (4U & ((IData)(this->__PVT__data_structures__DOT__way_use_Qual) + << 2U))] >> (0x1fU & ((IData)(this->__PVT__data_structures__DOT__way_use_Qual) + << 7U)))); + this->__Vcellout__data_structures__data_use[1U] + = (((0U == (0x1fU & ((IData)(this->__PVT__data_structures__DOT__way_use_Qual) + << 7U))) ? 0U : (this->__PVT__data_structures__DOT__data_use_per_way[ + ((IData)(2U) + + (4U + & ((IData)(this->__PVT__data_structures__DOT__way_use_Qual) + << 2U)))] + << ((IData)(0x20U) + - + (0x1fU + & ((IData)(this->__PVT__data_structures__DOT__way_use_Qual) + << 7U))))) + | (this->__PVT__data_structures__DOT__data_use_per_way[ + ((IData)(1U) + (4U & ((IData)(this->__PVT__data_structures__DOT__way_use_Qual) + << 2U)))] >> (0x1fU + & ((IData)(this->__PVT__data_structures__DOT__way_use_Qual) + << 7U)))); + this->__Vcellout__data_structures__data_use[2U] + = (((0U == (0x1fU & ((IData)(this->__PVT__data_structures__DOT__way_use_Qual) + << 7U))) ? 0U : (this->__PVT__data_structures__DOT__data_use_per_way[ + ((IData)(3U) + + (4U + & ((IData)(this->__PVT__data_structures__DOT__way_use_Qual) + << 2U)))] + << ((IData)(0x20U) + - + (0x1fU + & ((IData)(this->__PVT__data_structures__DOT__way_use_Qual) + << 7U))))) + | (this->__PVT__data_structures__DOT__data_use_per_way[ + ((IData)(2U) + (4U & ((IData)(this->__PVT__data_structures__DOT__way_use_Qual) + << 2U)))] >> (0x1fU + & ((IData)(this->__PVT__data_structures__DOT__way_use_Qual) + << 7U)))); + this->__Vcellout__data_structures__data_use[3U] + = (((0U == (0x1fU & ((IData)(this->__PVT__data_structures__DOT__way_use_Qual) + << 7U))) ? 0U : (this->__PVT__data_structures__DOT__data_use_per_way[ + ((IData)(4U) + + (4U + & ((IData)(this->__PVT__data_structures__DOT__way_use_Qual) + << 2U)))] + << ((IData)(0x20U) + - + (0x1fU + & ((IData)(this->__PVT__data_structures__DOT__way_use_Qual) + << 7U))))) + | (this->__PVT__data_structures__DOT__data_use_per_way[ + ((IData)(3U) + (4U & ((IData)(this->__PVT__data_structures__DOT__way_use_Qual) + << 2U)))] >> (0x1fU + & ((IData)(this->__PVT__data_structures__DOT__way_use_Qual) + << 7U)))); + this->__PVT__valid_use = (1U & ((IData)(this->__PVT__data_structures__DOT__valid_use_per_way) + >> (IData)(this->__PVT__data_structures__DOT__way_use_Qual))); + this->__PVT__tag_use = ((0x29U >= (0x3fU & ((IData)(0x15U) + * (IData)(this->__PVT__data_structures__DOT__way_use_Qual)))) + ? (0x1fffffU & (IData)( + (this->__PVT__data_structures__DOT__tag_use_per_way + >> + (0x3fU + & ((IData)(0x15U) + * (IData)(this->__PVT__data_structures__DOT__way_use_Qual)))))) + : 0U); + this->__PVT__data_unQual = (((0U == (3U & vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__1__KET____DOT__bank_addr)) + | (2U == (IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__cache_driver_in_mem_read))) + ? this->__Vcellout__data_structures__data_use[ + (3U & (vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__1__KET____DOT__bank_addr + >> 4U))] : ( + (1U + == + (3U + & vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__1__KET____DOT__bank_addr)) + ? + (this->__Vcellout__data_structures__data_use[ + (3U + & (vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__1__KET____DOT__bank_addr + >> 4U))] + >> 8U) + : + ((2U + == + (3U + & vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__1__KET____DOT__bank_addr)) + ? + (this->__Vcellout__data_structures__data_use[ + (3U + & (vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__1__KET____DOT__bank_addr + >> 4U))] + >> 0x10U) + : + (this->__Vcellout__data_structures__data_use[ + (3U + & (vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__1__KET____DOT__bank_addr + >> 4U))] + >> 0x18U)))); + this->__PVT__miss = (((this->__PVT__tag_use != + (0x1fffffU & (vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__1__KET____DOT__bank_addr + >> 0xbU))) + & (IData)(this->__PVT__valid_use)) + & (IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__1__KET____DOT__use_valid_in)); + this->__PVT__genblk1__BRA__0__KET____DOT__normal_write + = (((IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__read_or_write) + & ((IData)(this->__PVT__access) & (0U == + (3U + & (vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__1__KET____DOT__bank_addr + >> 4U))))) + & (~ (IData)(this->__PVT__miss))); + this->__PVT__genblk1__BRA__1__KET____DOT__normal_write + = (((IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__read_or_write) + & ((IData)(this->__PVT__access) & (1U == + (3U + & (vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__1__KET____DOT__bank_addr + >> 4U))))) + & (~ (IData)(this->__PVT__miss))); + this->__PVT__genblk1__BRA__2__KET____DOT__normal_write + = (((IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__read_or_write) + & ((IData)(this->__PVT__access) & (2U == + (3U + & (vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__1__KET____DOT__bank_addr + >> 4U))))) + & (~ (IData)(this->__PVT__miss))); + this->__PVT__genblk1__BRA__3__KET____DOT__normal_write + = (((IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__read_or_write) + & ((IData)(this->__PVT__access) & (3U == + (3U + & (vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__1__KET____DOT__bank_addr + >> 4U))))) + & (~ (IData)(this->__PVT__miss))); + this->__PVT__we = ((0xfff0U & (IData)(this->__PVT__we)) + | ((IData)(this->__PVT__write_from_mem) + ? 0xfU : (((IData)(this->__PVT__genblk1__BRA__0__KET____DOT__normal_write) + & (2U == (IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__cache_driver_in_mem_write))) + ? 0xfU : (((IData)(this->__PVT__genblk1__BRA__0__KET____DOT__normal_write) + & (0U + == (IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__cache_driver_in_mem_write))) + ? (IData)(this->__PVT__sb_mask) + : + (((IData)(this->__PVT__genblk1__BRA__0__KET____DOT__normal_write) + & (1U + == (IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__cache_driver_in_mem_write))) + ? + ((0U + == + (3U + & vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__1__KET____DOT__bank_addr)) + ? 3U + : 0xcU) + : 0U))))); + this->__PVT__we = ((0xff0fU & (IData)(this->__PVT__we)) + | (((IData)(this->__PVT__write_from_mem) + ? 0xfU : (((IData)(this->__PVT__genblk1__BRA__1__KET____DOT__normal_write) + & (2U == (IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__cache_driver_in_mem_write))) + ? 0xfU : (((IData)(this->__PVT__genblk1__BRA__1__KET____DOT__normal_write) + & (0U + == (IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__cache_driver_in_mem_write))) + ? (IData)(this->__PVT__sb_mask) + : + (((IData)(this->__PVT__genblk1__BRA__1__KET____DOT__normal_write) + & (1U + == (IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__cache_driver_in_mem_write))) + ? + ((0U + == + (3U + & vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__1__KET____DOT__bank_addr)) + ? 3U + : 0xcU) + : 0U)))) + << 4U)); + this->__PVT__we = ((0xf0ffU & (IData)(this->__PVT__we)) + | (((IData)(this->__PVT__write_from_mem) + ? 0xfU : (((IData)(this->__PVT__genblk1__BRA__2__KET____DOT__normal_write) + & (2U == (IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__cache_driver_in_mem_write))) + ? 0xfU : (((IData)(this->__PVT__genblk1__BRA__2__KET____DOT__normal_write) + & (0U + == (IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__cache_driver_in_mem_write))) + ? (IData)(this->__PVT__sb_mask) + : + (((IData)(this->__PVT__genblk1__BRA__2__KET____DOT__normal_write) + & (1U + == (IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__cache_driver_in_mem_write))) + ? + ((0U + == + (3U + & vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__1__KET____DOT__bank_addr)) + ? 3U + : 0xcU) + : 0U)))) + << 8U)); + this->__PVT__we = ((0xfffU & (IData)(this->__PVT__we)) + | (((IData)(this->__PVT__write_from_mem) + ? 0xfU : (((IData)(this->__PVT__genblk1__BRA__3__KET____DOT__normal_write) + & (2U == (IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__cache_driver_in_mem_write))) + ? 0xfU : (((IData)(this->__PVT__genblk1__BRA__3__KET____DOT__normal_write) + & (0U + == (IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__cache_driver_in_mem_write))) + ? (IData)(this->__PVT__sb_mask) + : + (((IData)(this->__PVT__genblk1__BRA__3__KET____DOT__normal_write) + & (1U + == (IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__cache_driver_in_mem_write))) + ? + ((0U + == + (3U + & vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__1__KET____DOT__bank_addr)) + ? 3U + : 0xcU) + : 0U)))) + << 0xcU)); + this->__PVT__data_structures__DOT__we_per_way = + ((0xffff0000U & this->__PVT__data_structures__DOT__we_per_way) + | ((IData)(this->__PVT__data_structures__DOT__way_use_Qual) + ? 0U : (0xffffU & (IData)(this->__PVT__we)))); + this->__PVT__data_structures__DOT__we_per_way = + ((0xffffU & this->__PVT__data_structures__DOT__we_per_way) + | (((IData)(this->__PVT__data_structures__DOT__way_use_Qual) + ? (0xffffU & (IData)(this->__PVT__we)) + : 0U) << 0x10U)); +} + +VL_INLINE_OPT void Vcache_simX_VX_Cache_Bank__pi7::_sequent__TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__1__KET____DOT__bank_structure__6(Vcache_simX__Syms* __restrict vlSymsp) { + VL_DEBUG_IF(VL_DBG_MSGF("+ Vcache_simX_VX_Cache_Bank__pi7::_sequent__TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__1__KET____DOT__bank_structure__6\n"); ); + Vcache_simX* __restrict vlTOPp VL_ATTR_UNUSED = vlSymsp->TOPp; + // Body + this->__PVT__way_to_update = vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT__global_way_to_evict; + this->__Vdlyvset__data_structures__DOT__each_way__BRA__1__KET____DOT__data_structures__DOT__dirty__v0 = 0U; + this->__Vdlyvset__data_structures__DOT__each_way__BRA__1__KET____DOT__data_structures__DOT__dirty__v32 = 0U; + this->__Vdlyvset__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__dirty__v0 = 0U; + this->__Vdlyvset__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__dirty__v32 = 0U; + this->__Vdlyvset__data_structures__DOT__each_way__BRA__1__KET____DOT__data_structures__DOT__valid__v0 = 0U; + this->__Vdlyvset__data_structures__DOT__each_way__BRA__1__KET____DOT__data_structures__DOT__valid__v32 = 0U; + this->__Vdlyvset__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__valid__v0 = 0U; + this->__Vdlyvset__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__valid__v32 = 0U; + this->__Vdlyvset__data_structures__DOT__each_way__BRA__1__KET____DOT__data_structures__DOT__tag__v0 = 0U; + this->__Vdlyvset__data_structures__DOT__each_way__BRA__1__KET____DOT__data_structures__DOT__tag__v32 = 0U; + this->__Vdlyvset__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__tag__v0 = 0U; + this->__Vdlyvset__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__tag__v32 = 0U; + if (vlTOPp->reset) { + this->__PVT__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__ini_ind = 0x20U; + } + if ((1U & (~ (IData)(vlTOPp->reset)))) { + this->__PVT__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__f = 4U; + } + if (vlTOPp->reset) { + this->__PVT__data_structures__DOT__each_way__BRA__1__KET____DOT__data_structures__DOT__ini_ind = 0x20U; + } + if ((1U & (~ (IData)(vlTOPp->reset)))) { + this->__PVT__data_structures__DOT__each_way__BRA__1__KET____DOT__data_structures__DOT__f = 4U; + } + this->__Vdlyvset__data_structures__DOT__each_way__BRA__1__KET____DOT__data_structures__DOT__data__v0 = 0U; + this->__Vdlyvset__data_structures__DOT__each_way__BRA__1__KET____DOT__data_structures__DOT__data__v32 = 0U; + this->__Vdlyvset__data_structures__DOT__each_way__BRA__1__KET____DOT__data_structures__DOT__data__v33 = 0U; + this->__Vdlyvset__data_structures__DOT__each_way__BRA__1__KET____DOT__data_structures__DOT__data__v34 = 0U; + this->__Vdlyvset__data_structures__DOT__each_way__BRA__1__KET____DOT__data_structures__DOT__data__v35 = 0U; + this->__Vdlyvset__data_structures__DOT__each_way__BRA__1__KET____DOT__data_structures__DOT__data__v36 = 0U; + this->__Vdlyvset__data_structures__DOT__each_way__BRA__1__KET____DOT__data_structures__DOT__data__v37 = 0U; + this->__Vdlyvset__data_structures__DOT__each_way__BRA__1__KET____DOT__data_structures__DOT__data__v38 = 0U; + this->__Vdlyvset__data_structures__DOT__each_way__BRA__1__KET____DOT__data_structures__DOT__data__v39 = 0U; + this->__Vdlyvset__data_structures__DOT__each_way__BRA__1__KET____DOT__data_structures__DOT__data__v40 = 0U; + this->__Vdlyvset__data_structures__DOT__each_way__BRA__1__KET____DOT__data_structures__DOT__data__v41 = 0U; + this->__Vdlyvset__data_structures__DOT__each_way__BRA__1__KET____DOT__data_structures__DOT__data__v42 = 0U; + this->__Vdlyvset__data_structures__DOT__each_way__BRA__1__KET____DOT__data_structures__DOT__data__v43 = 0U; + this->__Vdlyvset__data_structures__DOT__each_way__BRA__1__KET____DOT__data_structures__DOT__data__v44 = 0U; + this->__Vdlyvset__data_structures__DOT__each_way__BRA__1__KET____DOT__data_structures__DOT__data__v45 = 0U; + this->__Vdlyvset__data_structures__DOT__each_way__BRA__1__KET____DOT__data_structures__DOT__data__v46 = 0U; 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+ } + if (this->__Vdlyvset__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__data__v42) { + VL_ASSIGNSEL_WIII(8,(IData)(this->__Vdlyvlsb__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__data__v42), + this->__PVT__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__data + [this->__Vdlyvdim0__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__data__v42], this->__Vdlyvval__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__data__v42); + } + if (this->__Vdlyvset__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__data__v43) { + VL_ASSIGNSEL_WIII(8,(IData)(this->__Vdlyvlsb__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__data__v43), + this->__PVT__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__data + [this->__Vdlyvdim0__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__data__v43], this->__Vdlyvval__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__data__v43); + } + if (this->__Vdlyvset__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__data__v44) { + VL_ASSIGNSEL_WIII(8,(IData)(this->__Vdlyvlsb__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__data__v44), + this->__PVT__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__data + [this->__Vdlyvdim0__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__data__v44], this->__Vdlyvval__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__data__v44); + } + if (this->__Vdlyvset__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__data__v45) { + VL_ASSIGNSEL_WIII(8,(IData)(this->__Vdlyvlsb__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__data__v45), + this->__PVT__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__data + [this->__Vdlyvdim0__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__data__v45], this->__Vdlyvval__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__data__v45); + } + if (this->__Vdlyvset__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__data__v46) { + VL_ASSIGNSEL_WIII(8,(IData)(this->__Vdlyvlsb__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__data__v46), + this->__PVT__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__data + [this->__Vdlyvdim0__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__data__v46], this->__Vdlyvval__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__data__v46); + } + if (this->__Vdlyvset__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__data__v47) { + VL_ASSIGNSEL_WIII(8,(IData)(this->__Vdlyvlsb__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__data__v47), + this->__PVT__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__data + [this->__Vdlyvdim0__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__data__v47], this->__Vdlyvval__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__data__v47); + } +} + +VL_INLINE_OPT void Vcache_simX_VX_Cache_Bank__pi7::_combo__TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__1__KET____DOT__bank_structure__10(Vcache_simX__Syms* __restrict vlSymsp) { + VL_DEBUG_IF(VL_DBG_MSGF("+ Vcache_simX_VX_Cache_Bank__pi7::_combo__TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__1__KET____DOT__bank_structure__10\n"); ); + Vcache_simX* __restrict vlTOPp VL_ATTR_UNUSED = vlSymsp->TOPp; + // Variables + WData/*31:0*/ __Vtemp159[4]; + WData/*31:0*/ __Vtemp160[4]; + WData/*31:0*/ __Vtemp161[4]; + WData/*31:0*/ __Vtemp162[4]; + WData/*31:0*/ __Vtemp163[4]; + WData/*31:0*/ __Vtemp164[4]; + WData/*31:0*/ __Vtemp165[4]; + // Body + this->__PVT__write_from_mem = ((2U == (IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT__state)) + & (IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__1__KET____DOT__use_valid_in)); + this->__PVT__access = ((0U == (IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT__state)) + & (IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__1__KET____DOT__use_valid_in)); + this->data_structures__DOT____Vcellout__each_way__BRA__0__KET____DOT__data_structures__dirty_use + = this->__PVT__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__dirty + [(0x1fU & (vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__1__KET____DOT__bank_addr + >> 6U))]; + this->data_structures__DOT____Vcellout__each_way__BRA__1__KET____DOT__data_structures__dirty_use + = this->__PVT__data_structures__DOT__each_way__BRA__1__KET____DOT__data_structures__DOT__dirty + [(0x1fU & (vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__1__KET____DOT__bank_addr + >> 6U))]; + __Vtemp159[0U] = 0U; + __Vtemp159[1U] = 0U; + __Vtemp159[2U] = 0U; + __Vtemp159[3U] = 0U; + __Vtemp160[0U] = 0U; + __Vtemp160[1U] = 0U; + __Vtemp160[2U] = 0U; + __Vtemp160[3U] = 0U; + __Vtemp161[0U] = 0U; + __Vtemp161[1U] = 0U; + __Vtemp161[2U] = 0U; + __Vtemp161[3U] = 0U; + __Vtemp162[0U] = 0U; + __Vtemp162[1U] = 0U; + __Vtemp162[2U] = 0U; + __Vtemp162[3U] = 0U; + __Vtemp163[0U] = 0U; + __Vtemp163[1U] = 0U; + __Vtemp163[2U] = 0U; + __Vtemp163[3U] = 0U; + __Vtemp164[0U] = 0U; + __Vtemp164[1U] = 0U; + __Vtemp164[2U] = 0U; + __Vtemp164[3U] = 0U; + __Vtemp165[0U] = 0U; + __Vtemp165[1U] = 0U; + __Vtemp165[2U] = 0U; + __Vtemp165[3U] = 0U; + this->__PVT__use_write_data = ((0U == (IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__cache_driver_in_mem_write)) + ? ((1U == (3U & vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__1__KET____DOT__bank_addr)) + ? (0xff00U + & (__Vtemp159[ + (3U & + ((IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT__index_per_bank) + >> 2U))] + << 8U)) + : ((2U == (3U + & vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__1__KET____DOT__bank_addr)) + ? (0xff0000U + & (__Vtemp160[ + (3U + & ((IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT__index_per_bank) + >> 2U))] + << 0x10U)) + : ((3U + == + (3U + & vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__1__KET____DOT__bank_addr)) + ? (0xff000000U + & (__Vtemp161[ + (3U + & ((IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT__index_per_bank) + >> 2U))] + << 0x18U)) + : __Vtemp162[ + (3U + & ((IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT__index_per_bank) + >> 2U))]))) + : ((1U == (IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__cache_driver_in_mem_write)) + ? ((2U == (3U + & vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__1__KET____DOT__bank_addr)) + ? (0xffff0000U + & (__Vtemp163[ + (3U + & ((IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT__index_per_bank) + >> 2U))] + << 0x10U)) + : __Vtemp164[ + (3U & ((IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT__index_per_bank) + >> 2U))]) + : __Vtemp165[ + (3U & ((IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT__index_per_bank) + >> 2U))])); + this->__PVT__sb_mask = ((0U == (3U & vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__1__KET____DOT__bank_addr)) + ? 1U : ((1U == (3U & vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__1__KET____DOT__bank_addr)) + ? 2U : ((2U == + (3U + & vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__1__KET____DOT__bank_addr)) + ? 4U + : 8U))); + this->__PVT__data_structures__DOT__data_use_per_way[0U] + = this->__PVT__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__data + [(0x1fU & (vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__1__KET____DOT__bank_addr + >> 6U))][0U]; + this->__PVT__data_structures__DOT__data_use_per_way[1U] + = this->__PVT__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__data + [(0x1fU & (vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__1__KET____DOT__bank_addr + >> 6U))][1U]; + this->__PVT__data_structures__DOT__data_use_per_way[2U] + = this->__PVT__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__data + [(0x1fU & (vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__1__KET____DOT__bank_addr + >> 6U))][2U]; + this->__PVT__data_structures__DOT__data_use_per_way[3U] + = this->__PVT__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__data + [(0x1fU & (vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__1__KET____DOT__bank_addr + >> 6U))][3U]; + this->__PVT__data_structures__DOT__data_use_per_way[4U] + = this->__PVT__data_structures__DOT__each_way__BRA__1__KET____DOT__data_structures__DOT__data + [(0x1fU & (vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__1__KET____DOT__bank_addr + >> 6U))][0U]; + this->__PVT__data_structures__DOT__data_use_per_way[5U] + = this->__PVT__data_structures__DOT__each_way__BRA__1__KET____DOT__data_structures__DOT__data + [(0x1fU & (vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__1__KET____DOT__bank_addr + >> 6U))][1U]; + this->__PVT__data_structures__DOT__data_use_per_way[6U] + = this->__PVT__data_structures__DOT__each_way__BRA__1__KET____DOT__data_structures__DOT__data + [(0x1fU & (vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__1__KET____DOT__bank_addr + >> 6U))][2U]; + this->__PVT__data_structures__DOT__data_use_per_way[7U] + = this->__PVT__data_structures__DOT__each_way__BRA__1__KET____DOT__data_structures__DOT__data + [(0x1fU & (vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__1__KET____DOT__bank_addr + >> 6U))][3U]; + this->__PVT__data_structures__DOT__valid_use_per_way + = ((2U & (IData)(this->__PVT__data_structures__DOT__valid_use_per_way)) + | this->__PVT__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__valid + [(0x1fU & (vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__1__KET____DOT__bank_addr + >> 6U))]); + this->__PVT__data_structures__DOT__valid_use_per_way + = ((1U & (IData)(this->__PVT__data_structures__DOT__valid_use_per_way)) + | (this->__PVT__data_structures__DOT__each_way__BRA__1__KET____DOT__data_structures__DOT__valid + [(0x1fU & (vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__1__KET____DOT__bank_addr + >> 6U))] << 1U)); + this->__PVT__data_structures__DOT__tag_use_per_way + = ((VL_ULL(0x3ffffe00000) & this->__PVT__data_structures__DOT__tag_use_per_way) + | (IData)((IData)(this->__PVT__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__tag + [(0x1fU & (vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__1__KET____DOT__bank_addr + >> 6U))]))); + this->__PVT__data_structures__DOT__tag_use_per_way + = ((VL_ULL(0x1fffff) & this->__PVT__data_structures__DOT__tag_use_per_way) + | ((QData)((IData)(this->__PVT__data_structures__DOT__each_way__BRA__1__KET____DOT__data_structures__DOT__tag + [(0x1fU & (vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__1__KET____DOT__bank_addr + >> 6U))])) + << 0x15U)); + this->__PVT__data_structures__DOT__dirty_use_per_way + = ((2U & (IData)(this->__PVT__data_structures__DOT__dirty_use_per_way)) + | (IData)(this->data_structures__DOT____Vcellout__each_way__BRA__0__KET____DOT__data_structures__dirty_use)); + this->__PVT__data_structures__DOT__dirty_use_per_way + = ((1U & (IData)(this->__PVT__data_structures__DOT__dirty_use_per_way)) + | ((IData)(this->data_structures__DOT____Vcellout__each_way__BRA__1__KET____DOT__data_structures__dirty_use) + << 1U)); + this->__PVT__data_write[0U] = ((IData)(this->__PVT__write_from_mem) + ? vlSymsp->TOP__cache_simX__DOT__VX_dram_req_rsp.i_m_readdata[4U] + : this->__PVT__use_write_data); + this->__PVT__data_write[1U] = ((IData)(this->__PVT__write_from_mem) + ? vlSymsp->TOP__cache_simX__DOT__VX_dram_req_rsp.i_m_readdata[5U] + : this->__PVT__use_write_data); + this->__PVT__data_write[2U] = ((IData)(this->__PVT__write_from_mem) + ? vlSymsp->TOP__cache_simX__DOT__VX_dram_req_rsp.i_m_readdata[6U] + : this->__PVT__use_write_data); + this->__PVT__data_write[3U] = ((IData)(this->__PVT__write_from_mem) + ? vlSymsp->TOP__cache_simX__DOT__VX_dram_req_rsp.i_m_readdata[7U] + : this->__PVT__use_write_data); + this->__PVT__data_structures__DOT__invalid_found = 0U; + if ((1U & (~ ((IData)(this->__PVT__data_structures__DOT__valid_use_per_way) + >> 1U)))) { + this->__PVT__data_structures__DOT__invalid_found = 1U; + } + if ((1U & (~ (IData)(this->__PVT__data_structures__DOT__valid_use_per_way)))) { + this->__PVT__data_structures__DOT__invalid_found = 1U; + } + this->__PVT__data_structures__DOT__invalid_index = 0U; + if ((1U & (~ ((IData)(this->__PVT__data_structures__DOT__valid_use_per_way) + >> 1U)))) { + this->__PVT__data_structures__DOT__invalid_index = 1U; + } + if ((1U & (~ (IData)(this->__PVT__data_structures__DOT__valid_use_per_way)))) { + this->__PVT__data_structures__DOT__invalid_index = 0U; + } + this->__PVT__data_structures__DOT__hit_per_way + = ((2U & (IData)(this->__PVT__data_structures__DOT__hit_per_way)) + | (((IData)(this->__PVT__data_structures__DOT__valid_use_per_way) + & ((0x1fffffU & (IData)(this->__PVT__data_structures__DOT__tag_use_per_way)) + == (0x1fffffU & (vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__1__KET____DOT__bank_addr + >> 0xbU)))) ? 1U + : 0U)); + this->__PVT__data_structures__DOT__hit_per_way + = ((1U & (IData)(this->__PVT__data_structures__DOT__hit_per_way)) + | (((((IData)(this->__PVT__data_structures__DOT__valid_use_per_way) + >> 1U) & ((0x1fffffU & (IData)((this->__PVT__data_structures__DOT__tag_use_per_way + >> 0x15U))) + == (0x1fffffU & (vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__1__KET____DOT__bank_addr + >> 0xbU)))) + ? 1U : 0U) << 1U)); + this->__PVT__data_structures__DOT__data_write_per_way[0U] + = this->__PVT__data_write[0U]; + this->__PVT__data_structures__DOT__data_write_per_way[1U] + = this->__PVT__data_write[1U]; + this->__PVT__data_structures__DOT__data_write_per_way[2U] + = this->__PVT__data_write[2U]; + this->__PVT__data_structures__DOT__data_write_per_way[3U] + = this->__PVT__data_write[3U]; + this->__PVT__data_structures__DOT__data_write_per_way[4U] + = this->__PVT__data_write[0U]; + this->__PVT__data_structures__DOT__data_write_per_way[5U] + = this->__PVT__data_write[1U]; + this->__PVT__data_structures__DOT__data_write_per_way[6U] + = this->__PVT__data_write[2U]; + this->__PVT__data_structures__DOT__data_write_per_way[7U] + = this->__PVT__data_write[3U]; + this->__PVT__data_structures__DOT__genblk1__DOT__way_indexing__DOT__found = 0U; + if ((2U & (IData)(this->__PVT__data_structures__DOT__hit_per_way))) { + this->__PVT__data_structures__DOT__genblk1__DOT__way_indexing__DOT__found = 1U; + } + if ((1U & (IData)(this->__PVT__data_structures__DOT__hit_per_way))) { + this->__PVT__data_structures__DOT__genblk1__DOT__way_indexing__DOT__found = 1U; + } + this->__PVT__data_structures__DOT__way_index = 0U; + if ((2U & (IData)(this->__PVT__data_structures__DOT__hit_per_way))) { + this->__PVT__data_structures__DOT__way_index = 1U; + } + if ((1U & (IData)(this->__PVT__data_structures__DOT__hit_per_way))) { + this->__PVT__data_structures__DOT__way_index = 0U; + } + this->__PVT__data_structures__DOT__way_use_Qual + = ((0U != (IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT__state)) + ? (IData)(this->__PVT__way_to_update) : (IData)(this->__PVT__data_structures__DOT__way_index)); + this->__PVT__data_structures__DOT__write_from_mem_per_way + = ((2U & (IData)(this->__PVT__data_structures__DOT__write_from_mem_per_way)) + | ((IData)(this->__PVT__write_from_mem) + & (~ (IData)(this->__PVT__data_structures__DOT__way_use_Qual)))); + this->__PVT__data_structures__DOT__write_from_mem_per_way + = ((1U & (IData)(this->__PVT__data_structures__DOT__write_from_mem_per_way)) + | (((IData)(this->__PVT__write_from_mem) + & (IData)(this->__PVT__data_structures__DOT__way_use_Qual)) + << 1U)); + this->__Vcellout__data_structures__data_use[0U] + = (((0U == (0x1fU & ((IData)(this->__PVT__data_structures__DOT__way_use_Qual) + << 7U))) ? 0U : (this->__PVT__data_structures__DOT__data_use_per_way[ + ((IData)(1U) + + (4U + & ((IData)(this->__PVT__data_structures__DOT__way_use_Qual) + << 2U)))] + << ((IData)(0x20U) + - + (0x1fU + & ((IData)(this->__PVT__data_structures__DOT__way_use_Qual) + << 7U))))) + | (this->__PVT__data_structures__DOT__data_use_per_way[ + (4U & ((IData)(this->__PVT__data_structures__DOT__way_use_Qual) + << 2U))] >> (0x1fU & ((IData)(this->__PVT__data_structures__DOT__way_use_Qual) + << 7U)))); + this->__Vcellout__data_structures__data_use[1U] + = (((0U == (0x1fU & ((IData)(this->__PVT__data_structures__DOT__way_use_Qual) + << 7U))) ? 0U : (this->__PVT__data_structures__DOT__data_use_per_way[ + ((IData)(2U) + + (4U + & ((IData)(this->__PVT__data_structures__DOT__way_use_Qual) + << 2U)))] + << ((IData)(0x20U) + - + (0x1fU + & ((IData)(this->__PVT__data_structures__DOT__way_use_Qual) + << 7U))))) + | (this->__PVT__data_structures__DOT__data_use_per_way[ + ((IData)(1U) + (4U & ((IData)(this->__PVT__data_structures__DOT__way_use_Qual) + << 2U)))] >> (0x1fU + & ((IData)(this->__PVT__data_structures__DOT__way_use_Qual) + << 7U)))); + this->__Vcellout__data_structures__data_use[2U] + = (((0U == (0x1fU & ((IData)(this->__PVT__data_structures__DOT__way_use_Qual) + << 7U))) ? 0U : (this->__PVT__data_structures__DOT__data_use_per_way[ + ((IData)(3U) + + (4U + & ((IData)(this->__PVT__data_structures__DOT__way_use_Qual) + << 2U)))] + << ((IData)(0x20U) + - + (0x1fU + & ((IData)(this->__PVT__data_structures__DOT__way_use_Qual) + << 7U))))) + | (this->__PVT__data_structures__DOT__data_use_per_way[ + ((IData)(2U) + (4U & ((IData)(this->__PVT__data_structures__DOT__way_use_Qual) + << 2U)))] >> (0x1fU + & ((IData)(this->__PVT__data_structures__DOT__way_use_Qual) + << 7U)))); + this->__Vcellout__data_structures__data_use[3U] + = (((0U == (0x1fU & ((IData)(this->__PVT__data_structures__DOT__way_use_Qual) + << 7U))) ? 0U : (this->__PVT__data_structures__DOT__data_use_per_way[ + ((IData)(4U) + + (4U + & ((IData)(this->__PVT__data_structures__DOT__way_use_Qual) + << 2U)))] + << ((IData)(0x20U) + - + (0x1fU + & ((IData)(this->__PVT__data_structures__DOT__way_use_Qual) + << 7U))))) + | (this->__PVT__data_structures__DOT__data_use_per_way[ + ((IData)(3U) + (4U & ((IData)(this->__PVT__data_structures__DOT__way_use_Qual) + << 2U)))] >> (0x1fU + & ((IData)(this->__PVT__data_structures__DOT__way_use_Qual) + << 7U)))); + this->__PVT__valid_use = (1U & ((IData)(this->__PVT__data_structures__DOT__valid_use_per_way) + >> (IData)(this->__PVT__data_structures__DOT__way_use_Qual))); + this->__PVT__tag_use = ((0x29U >= (0x3fU & ((IData)(0x15U) + * (IData)(this->__PVT__data_structures__DOT__way_use_Qual)))) + ? (0x1fffffU & (IData)( + (this->__PVT__data_structures__DOT__tag_use_per_way + >> + (0x3fU + & ((IData)(0x15U) + * (IData)(this->__PVT__data_structures__DOT__way_use_Qual)))))) + : 0U); + this->__PVT__data_unQual = (((0U == (3U & vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__1__KET____DOT__bank_addr)) + | (2U == (IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__cache_driver_in_mem_read))) + ? this->__Vcellout__data_structures__data_use[ + (3U & (vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__1__KET____DOT__bank_addr + >> 4U))] : ( + (1U + == + (3U + & vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__1__KET____DOT__bank_addr)) + ? + (this->__Vcellout__data_structures__data_use[ + (3U + & (vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__1__KET____DOT__bank_addr + >> 4U))] + >> 8U) + : + ((2U + == + (3U + & vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__1__KET____DOT__bank_addr)) + ? + (this->__Vcellout__data_structures__data_use[ + (3U + & (vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__1__KET____DOT__bank_addr + >> 4U))] + >> 0x10U) + : + (this->__Vcellout__data_structures__data_use[ + (3U + & (vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__1__KET____DOT__bank_addr + >> 4U))] + >> 0x18U)))); + this->__PVT__miss = (((this->__PVT__tag_use != + (0x1fffffU & (vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__1__KET____DOT__bank_addr + >> 0xbU))) + & (IData)(this->__PVT__valid_use)) + & (IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__1__KET____DOT__use_valid_in)); + this->__PVT__genblk1__BRA__0__KET____DOT__normal_write + = (((IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__read_or_write) + & ((IData)(this->__PVT__access) & (0U == + (3U + & (vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__1__KET____DOT__bank_addr + >> 4U))))) + & (~ (IData)(this->__PVT__miss))); + this->__PVT__genblk1__BRA__1__KET____DOT__normal_write + = (((IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__read_or_write) + & ((IData)(this->__PVT__access) & (1U == + (3U + & (vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__1__KET____DOT__bank_addr + >> 4U))))) + & (~ (IData)(this->__PVT__miss))); + this->__PVT__genblk1__BRA__2__KET____DOT__normal_write + = (((IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__read_or_write) + & ((IData)(this->__PVT__access) & (2U == + (3U + & (vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__1__KET____DOT__bank_addr + >> 4U))))) + & (~ (IData)(this->__PVT__miss))); + this->__PVT__genblk1__BRA__3__KET____DOT__normal_write + = (((IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__read_or_write) + & ((IData)(this->__PVT__access) & (3U == + (3U + & (vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__1__KET____DOT__bank_addr + >> 4U))))) + & (~ (IData)(this->__PVT__miss))); + this->__PVT__we = ((0xfff0U & (IData)(this->__PVT__we)) + | ((IData)(this->__PVT__write_from_mem) + ? 0xfU : (((IData)(this->__PVT__genblk1__BRA__0__KET____DOT__normal_write) + & (2U == (IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__cache_driver_in_mem_write))) + ? 0xfU : (((IData)(this->__PVT__genblk1__BRA__0__KET____DOT__normal_write) + & (0U + == (IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__cache_driver_in_mem_write))) + ? (IData)(this->__PVT__sb_mask) + : + (((IData)(this->__PVT__genblk1__BRA__0__KET____DOT__normal_write) + & (1U + == (IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__cache_driver_in_mem_write))) + ? + ((0U + == + (3U + & vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__1__KET____DOT__bank_addr)) + ? 3U + : 0xcU) + : 0U))))); + this->__PVT__we = ((0xff0fU & (IData)(this->__PVT__we)) + | (((IData)(this->__PVT__write_from_mem) + ? 0xfU : (((IData)(this->__PVT__genblk1__BRA__1__KET____DOT__normal_write) + & (2U == (IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__cache_driver_in_mem_write))) + ? 0xfU : (((IData)(this->__PVT__genblk1__BRA__1__KET____DOT__normal_write) + & (0U + == (IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__cache_driver_in_mem_write))) + ? (IData)(this->__PVT__sb_mask) + : + (((IData)(this->__PVT__genblk1__BRA__1__KET____DOT__normal_write) + & (1U + == (IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__cache_driver_in_mem_write))) + ? + ((0U + == + (3U + & vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__1__KET____DOT__bank_addr)) + ? 3U + : 0xcU) + : 0U)))) + << 4U)); + this->__PVT__we = ((0xf0ffU & (IData)(this->__PVT__we)) + | (((IData)(this->__PVT__write_from_mem) + ? 0xfU : (((IData)(this->__PVT__genblk1__BRA__2__KET____DOT__normal_write) + & (2U == (IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__cache_driver_in_mem_write))) + ? 0xfU : (((IData)(this->__PVT__genblk1__BRA__2__KET____DOT__normal_write) + & (0U + == (IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__cache_driver_in_mem_write))) + ? (IData)(this->__PVT__sb_mask) + : + (((IData)(this->__PVT__genblk1__BRA__2__KET____DOT__normal_write) + & (1U + == (IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__cache_driver_in_mem_write))) + ? + ((0U + == + (3U + & vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__1__KET____DOT__bank_addr)) + ? 3U + : 0xcU) + : 0U)))) + << 8U)); + this->__PVT__we = ((0xfffU & (IData)(this->__PVT__we)) + | (((IData)(this->__PVT__write_from_mem) + ? 0xfU : (((IData)(this->__PVT__genblk1__BRA__3__KET____DOT__normal_write) + & (2U == (IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__cache_driver_in_mem_write))) + ? 0xfU : (((IData)(this->__PVT__genblk1__BRA__3__KET____DOT__normal_write) + & (0U + == (IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__cache_driver_in_mem_write))) + ? (IData)(this->__PVT__sb_mask) + : + (((IData)(this->__PVT__genblk1__BRA__3__KET____DOT__normal_write) + & (1U + == (IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__cache_driver_in_mem_write))) + ? + ((0U + == + (3U + & vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__1__KET____DOT__bank_addr)) + ? 3U + : 0xcU) + : 0U)))) + << 0xcU)); + this->__PVT__data_structures__DOT__we_per_way = + ((0xffff0000U & this->__PVT__data_structures__DOT__we_per_way) + | ((IData)(this->__PVT__data_structures__DOT__way_use_Qual) + ? 0U : (0xffffU & (IData)(this->__PVT__we)))); + this->__PVT__data_structures__DOT__we_per_way = + ((0xffffU & this->__PVT__data_structures__DOT__we_per_way) + | (((IData)(this->__PVT__data_structures__DOT__way_use_Qual) + ? (0xffffU & (IData)(this->__PVT__we)) + : 0U) << 0x10U)); +} + +void Vcache_simX_VX_Cache_Bank__pi7::_settle__TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__2__KET____DOT__bank_structure__3(Vcache_simX__Syms* __restrict vlSymsp) { + VL_DEBUG_IF(VL_DBG_MSGF("+ Vcache_simX_VX_Cache_Bank__pi7::_settle__TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__2__KET____DOT__bank_structure__3\n"); ); + Vcache_simX* __restrict vlTOPp VL_ATTR_UNUSED = vlSymsp->TOPp; + // Variables + WData/*31:0*/ __Vtemp169[4]; + WData/*31:0*/ __Vtemp170[4]; + WData/*31:0*/ __Vtemp171[4]; + WData/*31:0*/ __Vtemp172[4]; + WData/*31:0*/ __Vtemp173[4]; + WData/*31:0*/ __Vtemp174[4]; + WData/*31:0*/ __Vtemp175[4]; + // Body + this->__PVT__way_to_update = vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT__global_way_to_evict; + this->__PVT__write_from_mem = ((2U == (IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT__state)) + & (IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__2__KET____DOT__use_valid_in)); + this->__PVT__access = ((0U == (IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT__state)) + & (IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__2__KET____DOT__use_valid_in)); + this->data_structures__DOT____Vcellout__each_way__BRA__0__KET____DOT__data_structures__dirty_use + = this->__PVT__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__dirty + [(0x1fU & (vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__2__KET____DOT__bank_addr + >> 6U))]; + this->data_structures__DOT____Vcellout__each_way__BRA__1__KET____DOT__data_structures__dirty_use + = this->__PVT__data_structures__DOT__each_way__BRA__1__KET____DOT__data_structures__DOT__dirty + [(0x1fU & (vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__2__KET____DOT__bank_addr + >> 6U))]; + __Vtemp169[0U] = 0U; + __Vtemp169[1U] = 0U; + __Vtemp169[2U] = 0U; + __Vtemp169[3U] = 0U; + __Vtemp170[0U] = 0U; + __Vtemp170[1U] = 0U; + __Vtemp170[2U] = 0U; + __Vtemp170[3U] = 0U; + __Vtemp171[0U] = 0U; + __Vtemp171[1U] = 0U; + __Vtemp171[2U] = 0U; + __Vtemp171[3U] = 0U; + __Vtemp172[0U] = 0U; + __Vtemp172[1U] = 0U; + __Vtemp172[2U] = 0U; + __Vtemp172[3U] = 0U; + __Vtemp173[0U] = 0U; + __Vtemp173[1U] = 0U; + __Vtemp173[2U] = 0U; + __Vtemp173[3U] = 0U; + __Vtemp174[0U] = 0U; + __Vtemp174[1U] = 0U; + __Vtemp174[2U] = 0U; + __Vtemp174[3U] = 0U; + __Vtemp175[0U] = 0U; + __Vtemp175[1U] = 0U; + __Vtemp175[2U] = 0U; + __Vtemp175[3U] = 0U; + this->__PVT__use_write_data = ((0U == (IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__cache_driver_in_mem_write)) + ? ((1U == (3U & vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__2__KET____DOT__bank_addr)) + ? (0xff00U + & (__Vtemp169[ + (3U & + ((IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT__index_per_bank) + >> 4U))] + << 8U)) + : ((2U == (3U + & vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__2__KET____DOT__bank_addr)) + ? (0xff0000U + & (__Vtemp170[ + (3U + & ((IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT__index_per_bank) + >> 4U))] + << 0x10U)) + : ((3U + == + (3U + & vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__2__KET____DOT__bank_addr)) + ? (0xff000000U + & (__Vtemp171[ + (3U + & ((IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT__index_per_bank) + >> 4U))] + << 0x18U)) + : __Vtemp172[ + (3U + & ((IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT__index_per_bank) + >> 4U))]))) + : ((1U == (IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__cache_driver_in_mem_write)) + ? ((2U == (3U + & vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__2__KET____DOT__bank_addr)) + ? (0xffff0000U + & (__Vtemp173[ + (3U + & ((IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT__index_per_bank) + >> 4U))] + << 0x10U)) + : __Vtemp174[ + (3U & ((IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT__index_per_bank) + >> 4U))]) + : __Vtemp175[ + (3U & ((IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT__index_per_bank) + >> 4U))])); + this->__PVT__sb_mask = ((0U == (3U & vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__2__KET____DOT__bank_addr)) + ? 1U : ((1U == (3U & vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__2__KET____DOT__bank_addr)) + ? 2U : ((2U == + (3U + & vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__2__KET____DOT__bank_addr)) + ? 4U + : 8U))); + this->__PVT__data_structures__DOT__data_use_per_way[0U] + = this->__PVT__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__data + [(0x1fU & (vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__2__KET____DOT__bank_addr + >> 6U))][0U]; + this->__PVT__data_structures__DOT__data_use_per_way[1U] + = this->__PVT__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__data + [(0x1fU & (vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__2__KET____DOT__bank_addr + >> 6U))][1U]; + this->__PVT__data_structures__DOT__data_use_per_way[2U] + = this->__PVT__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__data + [(0x1fU & (vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__2__KET____DOT__bank_addr + >> 6U))][2U]; + this->__PVT__data_structures__DOT__data_use_per_way[3U] + = this->__PVT__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__data + [(0x1fU & (vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__2__KET____DOT__bank_addr + >> 6U))][3U]; + this->__PVT__data_structures__DOT__data_use_per_way[4U] + = this->__PVT__data_structures__DOT__each_way__BRA__1__KET____DOT__data_structures__DOT__data + [(0x1fU & (vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__2__KET____DOT__bank_addr + >> 6U))][0U]; + this->__PVT__data_structures__DOT__data_use_per_way[5U] + = this->__PVT__data_structures__DOT__each_way__BRA__1__KET____DOT__data_structures__DOT__data + [(0x1fU & (vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__2__KET____DOT__bank_addr + >> 6U))][1U]; + this->__PVT__data_structures__DOT__data_use_per_way[6U] + = this->__PVT__data_structures__DOT__each_way__BRA__1__KET____DOT__data_structures__DOT__data + [(0x1fU & (vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__2__KET____DOT__bank_addr + >> 6U))][2U]; + this->__PVT__data_structures__DOT__data_use_per_way[7U] + = this->__PVT__data_structures__DOT__each_way__BRA__1__KET____DOT__data_structures__DOT__data + [(0x1fU & (vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__2__KET____DOT__bank_addr + >> 6U))][3U]; + this->__PVT__data_structures__DOT__valid_use_per_way + = ((2U & (IData)(this->__PVT__data_structures__DOT__valid_use_per_way)) + | this->__PVT__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__valid + [(0x1fU & (vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__2__KET____DOT__bank_addr + >> 6U))]); + this->__PVT__data_structures__DOT__valid_use_per_way + = ((1U & (IData)(this->__PVT__data_structures__DOT__valid_use_per_way)) + | (this->__PVT__data_structures__DOT__each_way__BRA__1__KET____DOT__data_structures__DOT__valid + [(0x1fU & (vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__2__KET____DOT__bank_addr + >> 6U))] << 1U)); + this->__PVT__data_structures__DOT__tag_use_per_way + = ((VL_ULL(0x3ffffe00000) & this->__PVT__data_structures__DOT__tag_use_per_way) + | (IData)((IData)(this->__PVT__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__tag + [(0x1fU & (vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__2__KET____DOT__bank_addr + >> 6U))]))); + this->__PVT__data_structures__DOT__tag_use_per_way + = ((VL_ULL(0x1fffff) & this->__PVT__data_structures__DOT__tag_use_per_way) + | ((QData)((IData)(this->__PVT__data_structures__DOT__each_way__BRA__1__KET____DOT__data_structures__DOT__tag + [(0x1fU & (vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__2__KET____DOT__bank_addr + >> 6U))])) + << 0x15U)); + this->__PVT__data_structures__DOT__dirty_use_per_way + = ((2U & (IData)(this->__PVT__data_structures__DOT__dirty_use_per_way)) + | (IData)(this->data_structures__DOT____Vcellout__each_way__BRA__0__KET____DOT__data_structures__dirty_use)); + this->__PVT__data_structures__DOT__dirty_use_per_way + = ((1U & (IData)(this->__PVT__data_structures__DOT__dirty_use_per_way)) + | ((IData)(this->data_structures__DOT____Vcellout__each_way__BRA__1__KET____DOT__data_structures__dirty_use) + << 1U)); + this->__PVT__data_write[0U] = ((IData)(this->__PVT__write_from_mem) + ? vlSymsp->TOP__cache_simX__DOT__VX_dram_req_rsp.i_m_readdata[8U] + : this->__PVT__use_write_data); + this->__PVT__data_write[1U] = ((IData)(this->__PVT__write_from_mem) + ? vlSymsp->TOP__cache_simX__DOT__VX_dram_req_rsp.i_m_readdata[9U] + : this->__PVT__use_write_data); + this->__PVT__data_write[2U] = ((IData)(this->__PVT__write_from_mem) + ? vlSymsp->TOP__cache_simX__DOT__VX_dram_req_rsp.i_m_readdata[0xaU] + : this->__PVT__use_write_data); + this->__PVT__data_write[3U] = ((IData)(this->__PVT__write_from_mem) + ? vlSymsp->TOP__cache_simX__DOT__VX_dram_req_rsp.i_m_readdata[0xbU] + : this->__PVT__use_write_data); + this->__PVT__data_structures__DOT__invalid_found = 0U; + if ((1U & (~ ((IData)(this->__PVT__data_structures__DOT__valid_use_per_way) + >> 1U)))) { + this->__PVT__data_structures__DOT__invalid_found = 1U; + } + if ((1U & (~ (IData)(this->__PVT__data_structures__DOT__valid_use_per_way)))) { + this->__PVT__data_structures__DOT__invalid_found = 1U; + } + this->__PVT__data_structures__DOT__invalid_index = 0U; + if ((1U & (~ ((IData)(this->__PVT__data_structures__DOT__valid_use_per_way) + >> 1U)))) { + this->__PVT__data_structures__DOT__invalid_index = 1U; + } + if ((1U & (~ (IData)(this->__PVT__data_structures__DOT__valid_use_per_way)))) { + this->__PVT__data_structures__DOT__invalid_index = 0U; + } + this->__PVT__data_structures__DOT__hit_per_way + = ((2U & (IData)(this->__PVT__data_structures__DOT__hit_per_way)) + | (((IData)(this->__PVT__data_structures__DOT__valid_use_per_way) + & ((0x1fffffU & (IData)(this->__PVT__data_structures__DOT__tag_use_per_way)) + == (0x1fffffU & (vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__2__KET____DOT__bank_addr + >> 0xbU)))) ? 1U + : 0U)); + this->__PVT__data_structures__DOT__hit_per_way + = ((1U & (IData)(this->__PVT__data_structures__DOT__hit_per_way)) + | (((((IData)(this->__PVT__data_structures__DOT__valid_use_per_way) + >> 1U) & ((0x1fffffU & (IData)((this->__PVT__data_structures__DOT__tag_use_per_way + >> 0x15U))) + == (0x1fffffU & (vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__2__KET____DOT__bank_addr + >> 0xbU)))) + ? 1U : 0U) << 1U)); + this->__PVT__data_structures__DOT__data_write_per_way[0U] + = this->__PVT__data_write[0U]; + this->__PVT__data_structures__DOT__data_write_per_way[1U] + = this->__PVT__data_write[1U]; + this->__PVT__data_structures__DOT__data_write_per_way[2U] + = this->__PVT__data_write[2U]; + this->__PVT__data_structures__DOT__data_write_per_way[3U] + = this->__PVT__data_write[3U]; + this->__PVT__data_structures__DOT__data_write_per_way[4U] + = this->__PVT__data_write[0U]; + this->__PVT__data_structures__DOT__data_write_per_way[5U] + = this->__PVT__data_write[1U]; + this->__PVT__data_structures__DOT__data_write_per_way[6U] + = this->__PVT__data_write[2U]; + this->__PVT__data_structures__DOT__data_write_per_way[7U] + = this->__PVT__data_write[3U]; + this->__PVT__data_structures__DOT__genblk1__DOT__way_indexing__DOT__found = 0U; + if ((2U & (IData)(this->__PVT__data_structures__DOT__hit_per_way))) { + this->__PVT__data_structures__DOT__genblk1__DOT__way_indexing__DOT__found = 1U; + } + if ((1U & (IData)(this->__PVT__data_structures__DOT__hit_per_way))) { + this->__PVT__data_structures__DOT__genblk1__DOT__way_indexing__DOT__found = 1U; + } + this->__PVT__data_structures__DOT__way_index = 0U; + if ((2U & (IData)(this->__PVT__data_structures__DOT__hit_per_way))) { + this->__PVT__data_structures__DOT__way_index = 1U; + } + if ((1U & (IData)(this->__PVT__data_structures__DOT__hit_per_way))) { + this->__PVT__data_structures__DOT__way_index = 0U; + } + this->__PVT__data_structures__DOT__way_use_Qual + = ((0U != (IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT__state)) + ? (IData)(this->__PVT__way_to_update) : (IData)(this->__PVT__data_structures__DOT__way_index)); + this->__PVT__data_structures__DOT__write_from_mem_per_way + = ((2U & (IData)(this->__PVT__data_structures__DOT__write_from_mem_per_way)) + | ((IData)(this->__PVT__write_from_mem) + & (~ (IData)(this->__PVT__data_structures__DOT__way_use_Qual)))); + this->__PVT__data_structures__DOT__write_from_mem_per_way + = ((1U & (IData)(this->__PVT__data_structures__DOT__write_from_mem_per_way)) + | (((IData)(this->__PVT__write_from_mem) + & (IData)(this->__PVT__data_structures__DOT__way_use_Qual)) + << 1U)); + this->__Vcellout__data_structures__data_use[0U] + = (((0U == (0x1fU & ((IData)(this->__PVT__data_structures__DOT__way_use_Qual) + << 7U))) ? 0U : (this->__PVT__data_structures__DOT__data_use_per_way[ + ((IData)(1U) + + (4U + & ((IData)(this->__PVT__data_structures__DOT__way_use_Qual) + << 2U)))] + << ((IData)(0x20U) + - + (0x1fU + & ((IData)(this->__PVT__data_structures__DOT__way_use_Qual) + << 7U))))) + | (this->__PVT__data_structures__DOT__data_use_per_way[ + (4U & ((IData)(this->__PVT__data_structures__DOT__way_use_Qual) + << 2U))] >> (0x1fU & ((IData)(this->__PVT__data_structures__DOT__way_use_Qual) + << 7U)))); + this->__Vcellout__data_structures__data_use[1U] + = (((0U == (0x1fU & ((IData)(this->__PVT__data_structures__DOT__way_use_Qual) + << 7U))) ? 0U : (this->__PVT__data_structures__DOT__data_use_per_way[ + ((IData)(2U) + + (4U + & ((IData)(this->__PVT__data_structures__DOT__way_use_Qual) + << 2U)))] + << ((IData)(0x20U) + - + (0x1fU + & ((IData)(this->__PVT__data_structures__DOT__way_use_Qual) + << 7U))))) + | (this->__PVT__data_structures__DOT__data_use_per_way[ + ((IData)(1U) + (4U & ((IData)(this->__PVT__data_structures__DOT__way_use_Qual) + << 2U)))] >> (0x1fU + & ((IData)(this->__PVT__data_structures__DOT__way_use_Qual) + << 7U)))); + this->__Vcellout__data_structures__data_use[2U] + = (((0U == (0x1fU & ((IData)(this->__PVT__data_structures__DOT__way_use_Qual) + << 7U))) ? 0U : (this->__PVT__data_structures__DOT__data_use_per_way[ + ((IData)(3U) + + (4U + & ((IData)(this->__PVT__data_structures__DOT__way_use_Qual) + << 2U)))] + << ((IData)(0x20U) + - + (0x1fU + & ((IData)(this->__PVT__data_structures__DOT__way_use_Qual) + << 7U))))) + | (this->__PVT__data_structures__DOT__data_use_per_way[ + ((IData)(2U) + (4U & ((IData)(this->__PVT__data_structures__DOT__way_use_Qual) + << 2U)))] >> (0x1fU + & ((IData)(this->__PVT__data_structures__DOT__way_use_Qual) + << 7U)))); + this->__Vcellout__data_structures__data_use[3U] + = (((0U == (0x1fU & ((IData)(this->__PVT__data_structures__DOT__way_use_Qual) + << 7U))) ? 0U : (this->__PVT__data_structures__DOT__data_use_per_way[ + ((IData)(4U) + + (4U + & ((IData)(this->__PVT__data_structures__DOT__way_use_Qual) + << 2U)))] + << ((IData)(0x20U) + - + (0x1fU + & ((IData)(this->__PVT__data_structures__DOT__way_use_Qual) + << 7U))))) + | (this->__PVT__data_structures__DOT__data_use_per_way[ + ((IData)(3U) + (4U & ((IData)(this->__PVT__data_structures__DOT__way_use_Qual) + << 2U)))] >> (0x1fU + & ((IData)(this->__PVT__data_structures__DOT__way_use_Qual) + << 7U)))); + this->__PVT__valid_use = (1U & ((IData)(this->__PVT__data_structures__DOT__valid_use_per_way) + >> (IData)(this->__PVT__data_structures__DOT__way_use_Qual))); + this->__PVT__tag_use = ((0x29U >= (0x3fU & ((IData)(0x15U) + * (IData)(this->__PVT__data_structures__DOT__way_use_Qual)))) + ? (0x1fffffU & (IData)( + (this->__PVT__data_structures__DOT__tag_use_per_way + >> + (0x3fU + & ((IData)(0x15U) + * (IData)(this->__PVT__data_structures__DOT__way_use_Qual)))))) + : 0U); + this->__PVT__data_unQual = (((0U == (3U & vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__2__KET____DOT__bank_addr)) + | (2U == (IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__cache_driver_in_mem_read))) + ? this->__Vcellout__data_structures__data_use[ + (3U & (vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__2__KET____DOT__bank_addr + >> 4U))] : ( + (1U + == + (3U + & vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__2__KET____DOT__bank_addr)) + ? + (this->__Vcellout__data_structures__data_use[ + (3U + & (vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__2__KET____DOT__bank_addr + >> 4U))] + >> 8U) + : + ((2U + == + (3U + & vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__2__KET____DOT__bank_addr)) + ? + (this->__Vcellout__data_structures__data_use[ + (3U + & (vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__2__KET____DOT__bank_addr + >> 4U))] + >> 0x10U) + : + (this->__Vcellout__data_structures__data_use[ + (3U + & (vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__2__KET____DOT__bank_addr + >> 4U))] + >> 0x18U)))); + this->__PVT__miss = (((this->__PVT__tag_use != + (0x1fffffU & (vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__2__KET____DOT__bank_addr + >> 0xbU))) + & (IData)(this->__PVT__valid_use)) + & (IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__2__KET____DOT__use_valid_in)); + this->__PVT__genblk1__BRA__0__KET____DOT__normal_write + = (((IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__read_or_write) + & ((IData)(this->__PVT__access) & (0U == + (3U + & (vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__2__KET____DOT__bank_addr + >> 4U))))) + & (~ (IData)(this->__PVT__miss))); + this->__PVT__genblk1__BRA__1__KET____DOT__normal_write + = (((IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__read_or_write) + & ((IData)(this->__PVT__access) & (1U == + (3U + & (vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__2__KET____DOT__bank_addr + >> 4U))))) + & (~ (IData)(this->__PVT__miss))); + this->__PVT__genblk1__BRA__2__KET____DOT__normal_write + = (((IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__read_or_write) + & ((IData)(this->__PVT__access) & (2U == + (3U + & (vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__2__KET____DOT__bank_addr + >> 4U))))) + & (~ (IData)(this->__PVT__miss))); + this->__PVT__genblk1__BRA__3__KET____DOT__normal_write + = (((IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__read_or_write) + & ((IData)(this->__PVT__access) & (3U == + (3U + & (vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__2__KET____DOT__bank_addr + >> 4U))))) + & (~ (IData)(this->__PVT__miss))); + this->__PVT__we = ((0xfff0U & (IData)(this->__PVT__we)) + | ((IData)(this->__PVT__write_from_mem) + ? 0xfU : (((IData)(this->__PVT__genblk1__BRA__0__KET____DOT__normal_write) + & (2U == (IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__cache_driver_in_mem_write))) + ? 0xfU : (((IData)(this->__PVT__genblk1__BRA__0__KET____DOT__normal_write) + & (0U + == (IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__cache_driver_in_mem_write))) + ? (IData)(this->__PVT__sb_mask) + : + (((IData)(this->__PVT__genblk1__BRA__0__KET____DOT__normal_write) + & (1U + == (IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__cache_driver_in_mem_write))) + ? + ((0U + == + (3U + & vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__2__KET____DOT__bank_addr)) + ? 3U + : 0xcU) + : 0U))))); + this->__PVT__we = ((0xff0fU & (IData)(this->__PVT__we)) + | (((IData)(this->__PVT__write_from_mem) + ? 0xfU : (((IData)(this->__PVT__genblk1__BRA__1__KET____DOT__normal_write) + & (2U == (IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__cache_driver_in_mem_write))) + ? 0xfU : (((IData)(this->__PVT__genblk1__BRA__1__KET____DOT__normal_write) + & (0U + == (IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__cache_driver_in_mem_write))) + ? (IData)(this->__PVT__sb_mask) + : + (((IData)(this->__PVT__genblk1__BRA__1__KET____DOT__normal_write) + & (1U + == (IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__cache_driver_in_mem_write))) + ? + ((0U + == + (3U + & vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__2__KET____DOT__bank_addr)) + ? 3U + : 0xcU) + : 0U)))) + << 4U)); + this->__PVT__we = ((0xf0ffU & (IData)(this->__PVT__we)) + | (((IData)(this->__PVT__write_from_mem) + ? 0xfU : (((IData)(this->__PVT__genblk1__BRA__2__KET____DOT__normal_write) + & (2U == (IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__cache_driver_in_mem_write))) + ? 0xfU : (((IData)(this->__PVT__genblk1__BRA__2__KET____DOT__normal_write) + & (0U + == (IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__cache_driver_in_mem_write))) + ? (IData)(this->__PVT__sb_mask) + : + (((IData)(this->__PVT__genblk1__BRA__2__KET____DOT__normal_write) + & (1U + == (IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__cache_driver_in_mem_write))) + ? + ((0U + == + (3U + & vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__2__KET____DOT__bank_addr)) + ? 3U + : 0xcU) + : 0U)))) + << 8U)); + this->__PVT__we = ((0xfffU & (IData)(this->__PVT__we)) + | (((IData)(this->__PVT__write_from_mem) + ? 0xfU : (((IData)(this->__PVT__genblk1__BRA__3__KET____DOT__normal_write) + & (2U == (IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__cache_driver_in_mem_write))) + ? 0xfU : (((IData)(this->__PVT__genblk1__BRA__3__KET____DOT__normal_write) + & (0U + == (IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__cache_driver_in_mem_write))) + ? (IData)(this->__PVT__sb_mask) + : + (((IData)(this->__PVT__genblk1__BRA__3__KET____DOT__normal_write) + & (1U + == (IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__cache_driver_in_mem_write))) + ? + ((0U + == + (3U + & vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__2__KET____DOT__bank_addr)) + ? 3U + : 0xcU) + : 0U)))) + << 0xcU)); + this->__PVT__data_structures__DOT__we_per_way = + ((0xffff0000U & this->__PVT__data_structures__DOT__we_per_way) + | ((IData)(this->__PVT__data_structures__DOT__way_use_Qual) + ? 0U : (0xffffU & (IData)(this->__PVT__we)))); + this->__PVT__data_structures__DOT__we_per_way = + ((0xffffU & this->__PVT__data_structures__DOT__we_per_way) + | (((IData)(this->__PVT__data_structures__DOT__way_use_Qual) + ? (0xffffU & (IData)(this->__PVT__we)) + : 0U) << 0x10U)); +} + +VL_INLINE_OPT void Vcache_simX_VX_Cache_Bank__pi7::_sequent__TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__2__KET____DOT__bank_structure__7(Vcache_simX__Syms* __restrict vlSymsp) { + VL_DEBUG_IF(VL_DBG_MSGF("+ Vcache_simX_VX_Cache_Bank__pi7::_sequent__TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__2__KET____DOT__bank_structure__7\n"); ); + Vcache_simX* __restrict vlTOPp VL_ATTR_UNUSED = vlSymsp->TOPp; + // Body + this->__PVT__way_to_update = vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT__global_way_to_evict; + this->__Vdlyvset__data_structures__DOT__each_way__BRA__1__KET____DOT__data_structures__DOT__dirty__v0 = 0U; + this->__Vdlyvset__data_structures__DOT__each_way__BRA__1__KET____DOT__data_structures__DOT__dirty__v32 = 0U; + this->__Vdlyvset__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__dirty__v0 = 0U; + this->__Vdlyvset__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__dirty__v32 = 0U; + this->__Vdlyvset__data_structures__DOT__each_way__BRA__1__KET____DOT__data_structures__DOT__valid__v0 = 0U; + this->__Vdlyvset__data_structures__DOT__each_way__BRA__1__KET____DOT__data_structures__DOT__valid__v32 = 0U; + this->__Vdlyvset__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__valid__v0 = 0U; + this->__Vdlyvset__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__valid__v32 = 0U; + this->__Vdlyvset__data_structures__DOT__each_way__BRA__1__KET____DOT__data_structures__DOT__tag__v0 = 0U; + this->__Vdlyvset__data_structures__DOT__each_way__BRA__1__KET____DOT__data_structures__DOT__tag__v32 = 0U; + this->__Vdlyvset__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__tag__v0 = 0U; + this->__Vdlyvset__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__tag__v32 = 0U; + if (vlTOPp->reset) { + this->__PVT__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__ini_ind = 0x20U; + } + if ((1U & (~ (IData)(vlTOPp->reset)))) { + this->__PVT__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__f = 4U; + } + if (vlTOPp->reset) { + this->__PVT__data_structures__DOT__each_way__BRA__1__KET____DOT__data_structures__DOT__ini_ind = 0x20U; + } + if ((1U & (~ (IData)(vlTOPp->reset)))) { + this->__PVT__data_structures__DOT__each_way__BRA__1__KET____DOT__data_structures__DOT__f = 4U; + } + this->__Vdlyvset__data_structures__DOT__each_way__BRA__1__KET____DOT__data_structures__DOT__data__v0 = 0U; + this->__Vdlyvset__data_structures__DOT__each_way__BRA__1__KET____DOT__data_structures__DOT__data__v32 = 0U; + this->__Vdlyvset__data_structures__DOT__each_way__BRA__1__KET____DOT__data_structures__DOT__data__v33 = 0U; + this->__Vdlyvset__data_structures__DOT__each_way__BRA__1__KET____DOT__data_structures__DOT__data__v34 = 0U; + this->__Vdlyvset__data_structures__DOT__each_way__BRA__1__KET____DOT__data_structures__DOT__data__v35 = 0U; + this->__Vdlyvset__data_structures__DOT__each_way__BRA__1__KET____DOT__data_structures__DOT__data__v36 = 0U; + this->__Vdlyvset__data_structures__DOT__each_way__BRA__1__KET____DOT__data_structures__DOT__data__v37 = 0U; + this->__Vdlyvset__data_structures__DOT__each_way__BRA__1__KET____DOT__data_structures__DOT__data__v38 = 0U; + this->__Vdlyvset__data_structures__DOT__each_way__BRA__1__KET____DOT__data_structures__DOT__data__v39 = 0U; + this->__Vdlyvset__data_structures__DOT__each_way__BRA__1__KET____DOT__data_structures__DOT__data__v40 = 0U; + this->__Vdlyvset__data_structures__DOT__each_way__BRA__1__KET____DOT__data_structures__DOT__data__v41 = 0U; + this->__Vdlyvset__data_structures__DOT__each_way__BRA__1__KET____DOT__data_structures__DOT__data__v42 = 0U; + this->__Vdlyvset__data_structures__DOT__each_way__BRA__1__KET____DOT__data_structures__DOT__data__v43 = 0U; + this->__Vdlyvset__data_structures__DOT__each_way__BRA__1__KET____DOT__data_structures__DOT__data__v44 = 0U; + this->__Vdlyvset__data_structures__DOT__each_way__BRA__1__KET____DOT__data_structures__DOT__data__v45 = 0U; + this->__Vdlyvset__data_structures__DOT__each_way__BRA__1__KET____DOT__data_structures__DOT__data__v46 = 0U; + this->__Vdlyvset__data_structures__DOT__each_way__BRA__1__KET____DOT__data_structures__DOT__data__v47 = 0U; + this->__Vdlyvset__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__data__v0 = 0U; + this->__Vdlyvset__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__data__v32 = 0U; + this->__Vdlyvset__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__data__v33 = 0U; + this->__Vdlyvset__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__data__v34 = 0U; + this->__Vdlyvset__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__data__v35 = 0U; + this->__Vdlyvset__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__data__v36 = 0U; + this->__Vdlyvset__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__data__v37 = 0U; + this->__Vdlyvset__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__data__v38 = 0U; + this->__Vdlyvset__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__data__v39 = 0U; + this->__Vdlyvset__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__data__v40 = 0U; + this->__Vdlyvset__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__data__v41 = 0U; + this->__Vdlyvset__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__data__v42 = 0U; + this->__Vdlyvset__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__data__v43 = 0U; + this->__Vdlyvset__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__data__v44 = 0U; + this->__Vdlyvset__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__data__v45 = 0U; + this->__Vdlyvset__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__data__v46 = 0U; + this->__Vdlyvset__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__data__v47 = 0U; + if (vlTOPp->reset) { + this->__Vdlyvset__data_structures__DOT__each_way__BRA__1__KET____DOT__data_structures__DOT__dirty__v0 = 1U; + } else { + if ((1U & (((~ (IData)(this->data_structures__DOT____Vcellout__each_way__BRA__1__KET____DOT__data_structures__dirty_use)) + & (0U != (0xffffU & (this->__PVT__data_structures__DOT__we_per_way + >> 0x10U)))) + | ((IData)(this->__PVT__data_structures__DOT__write_from_mem_per_way) + >> 1U)))) { + this->__Vdlyvval__data_structures__DOT__each_way__BRA__1__KET____DOT__data_structures__DOT__dirty__v32 + = ((2U & (IData)(this->__PVT__data_structures__DOT__write_from_mem_per_way)) + ? 0U : (1U & (0U != (0xffffU & + (this->__PVT__data_structures__DOT__we_per_way + >> 0x10U))))); + this->__Vdlyvset__data_structures__DOT__each_way__BRA__1__KET____DOT__data_structures__DOT__dirty__v32 = 1U; + this->__Vdlyvdim0__data_structures__DOT__each_way__BRA__1__KET____DOT__data_structures__DOT__dirty__v32 + = (0x1fU & (vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__2__KET____DOT__bank_addr + >> 6U)); + } + } + if (vlTOPp->reset) { + this->__Vdlyvset__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__dirty__v0 = 1U; + } else { + if ((1U & (((~ (IData)(this->data_structures__DOT____Vcellout__each_way__BRA__0__KET____DOT__data_structures__dirty_use)) + & (0U != (0xffffU & this->__PVT__data_structures__DOT__we_per_way))) + | (IData)(this->__PVT__data_structures__DOT__write_from_mem_per_way)))) { + this->__Vdlyvval__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__dirty__v32 + = ((1U & (IData)(this->__PVT__data_structures__DOT__write_from_mem_per_way)) + ? 0U : (1U & (0U != (0xffffU & this->__PVT__data_structures__DOT__we_per_way)))); + this->__Vdlyvset__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__dirty__v32 = 1U; + this->__Vdlyvdim0__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__dirty__v32 + = (0x1fU & (vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__2__KET____DOT__bank_addr + >> 6U)); + } + } + if (vlTOPp->reset) { + this->__Vdlyvset__data_structures__DOT__each_way__BRA__1__KET____DOT__data_structures__DOT__valid__v0 = 1U; + } else { + if ((2U & (IData)(this->__PVT__data_structures__DOT__write_from_mem_per_way))) { + this->__Vdlyvset__data_structures__DOT__each_way__BRA__1__KET____DOT__data_structures__DOT__valid__v32 = 1U; + this->__Vdlyvdim0__data_structures__DOT__each_way__BRA__1__KET____DOT__data_structures__DOT__valid__v32 + = (0x1fU & (vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__2__KET____DOT__bank_addr + >> 6U)); + } + } + if (vlTOPp->reset) { + this->__Vdlyvset__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__valid__v0 = 1U; + } else { + if ((1U & (IData)(this->__PVT__data_structures__DOT__write_from_mem_per_way))) { + this->__Vdlyvset__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__valid__v32 = 1U; + this->__Vdlyvdim0__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__valid__v32 + = (0x1fU & (vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__2__KET____DOT__bank_addr + >> 6U)); + } + } + if (vlTOPp->reset) { + this->__Vdlyvset__data_structures__DOT__each_way__BRA__1__KET____DOT__data_structures__DOT__tag__v0 = 1U; + } else { + if ((2U & (IData)(this->__PVT__data_structures__DOT__write_from_mem_per_way))) { + this->__Vdlyvval__data_structures__DOT__each_way__BRA__1__KET____DOT__data_structures__DOT__tag__v32 + = (0x1fffffU & (vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__2__KET____DOT__bank_addr + >> 0xbU)); + this->__Vdlyvset__data_structures__DOT__each_way__BRA__1__KET____DOT__data_structures__DOT__tag__v32 = 1U; + this->__Vdlyvdim0__data_structures__DOT__each_way__BRA__1__KET____DOT__data_structures__DOT__tag__v32 + = (0x1fU & (vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__2__KET____DOT__bank_addr + >> 6U)); + } + } + if (vlTOPp->reset) { + this->__Vdlyvset__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__tag__v0 = 1U; + } else { + if ((1U & (IData)(this->__PVT__data_structures__DOT__write_from_mem_per_way))) { + this->__Vdlyvval__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__tag__v32 + = (0x1fffffU & (vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__2__KET____DOT__bank_addr + >> 0xbU)); + this->__Vdlyvset__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__tag__v32 = 1U; + this->__Vdlyvdim0__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__tag__v32 + = (0x1fU & (vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__2__KET____DOT__bank_addr + >> 6U)); + } + } + if (vlTOPp->reset) { + this->__Vdlyvset__data_structures__DOT__each_way__BRA__1__KET____DOT__data_structures__DOT__data__v0 = 1U; + } else { + if ((0x10000U & this->__PVT__data_structures__DOT__we_per_way)) { + this->__Vdlyvval__data_structures__DOT__each_way__BRA__1__KET____DOT__data_structures__DOT__data__v32 + = (0xffU & this->__PVT__data_structures__DOT__data_write_per_way[4U]); + this->__Vdlyvset__data_structures__DOT__each_way__BRA__1__KET____DOT__data_structures__DOT__data__v32 = 1U; + this->__Vdlyvlsb__data_structures__DOT__each_way__BRA__1__KET____DOT__data_structures__DOT__data__v32 = 0U; + this->__Vdlyvdim0__data_structures__DOT__each_way__BRA__1__KET____DOT__data_structures__DOT__data__v32 + = (0x1fU & (vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__2__KET____DOT__bank_addr + >> 6U)); + } + if ((0x20000U & this->__PVT__data_structures__DOT__we_per_way)) { + this->__Vdlyvval__data_structures__DOT__each_way__BRA__1__KET____DOT__data_structures__DOT__data__v33 + = (0xffU & ((this->__PVT__data_structures__DOT__data_write_per_way[5U] + << 0x18U) | (this->__PVT__data_structures__DOT__data_write_per_way[4U] + >> 8U))); + this->__Vdlyvset__data_structures__DOT__each_way__BRA__1__KET____DOT__data_structures__DOT__data__v33 = 1U; + this->__Vdlyvlsb__data_structures__DOT__each_way__BRA__1__KET____DOT__data_structures__DOT__data__v33 = 8U; + this->__Vdlyvdim0__data_structures__DOT__each_way__BRA__1__KET____DOT__data_structures__DOT__data__v33 + = (0x1fU & (vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__2__KET____DOT__bank_addr + >> 6U)); + } + if ((0x40000U & this->__PVT__data_structures__DOT__we_per_way)) { + this->__Vdlyvval__data_structures__DOT__each_way__BRA__1__KET____DOT__data_structures__DOT__data__v34 + = (0xffU & ((this->__PVT__data_structures__DOT__data_write_per_way[5U] + << 0x10U) | (this->__PVT__data_structures__DOT__data_write_per_way[4U] + >> 0x10U))); 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+ this->__PVT__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__data[0x1cU][2U] = 0U; + this->__PVT__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__data[0x1cU][3U] = 0U; + this->__PVT__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__data[0x1dU][0U] = 0U; + this->__PVT__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__data[0x1dU][1U] = 0U; + this->__PVT__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__data[0x1dU][2U] = 0U; + this->__PVT__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__data[0x1dU][3U] = 0U; + this->__PVT__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__data[0x1eU][0U] = 0U; + this->__PVT__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__data[0x1eU][1U] = 0U; + this->__PVT__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__data[0x1eU][2U] = 0U; + this->__PVT__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__data[0x1eU][3U] = 0U; + this->__PVT__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__data[0x1fU][0U] = 0U; + this->__PVT__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__data[0x1fU][1U] = 0U; + this->__PVT__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__data[0x1fU][2U] = 0U; + this->__PVT__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__data[0x1fU][3U] = 0U; + } + if (this->__Vdlyvset__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__data__v32) { + VL_ASSIGNSEL_WIII(8,(IData)(this->__Vdlyvlsb__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__data__v32), + this->__PVT__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__data + [this->__Vdlyvdim0__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__data__v32], this->__Vdlyvval__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__data__v32); + } + if (this->__Vdlyvset__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__data__v33) { + VL_ASSIGNSEL_WIII(8,(IData)(this->__Vdlyvlsb__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__data__v33), + this->__PVT__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__data + [this->__Vdlyvdim0__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__data__v33], this->__Vdlyvval__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__data__v33); + } + if (this->__Vdlyvset__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__data__v34) { + VL_ASSIGNSEL_WIII(8,(IData)(this->__Vdlyvlsb__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__data__v34), + this->__PVT__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__data + [this->__Vdlyvdim0__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__data__v34], this->__Vdlyvval__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__data__v34); + } + if (this->__Vdlyvset__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__data__v35) { + VL_ASSIGNSEL_WIII(8,(IData)(this->__Vdlyvlsb__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__data__v35), + this->__PVT__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__data + [this->__Vdlyvdim0__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__data__v35], this->__Vdlyvval__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__data__v35); + } + if (this->__Vdlyvset__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__data__v36) { + VL_ASSIGNSEL_WIII(8,(IData)(this->__Vdlyvlsb__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__data__v36), + this->__PVT__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__data + [this->__Vdlyvdim0__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__data__v36], this->__Vdlyvval__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__data__v36); + } + if (this->__Vdlyvset__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__data__v37) { + VL_ASSIGNSEL_WIII(8,(IData)(this->__Vdlyvlsb__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__data__v37), + this->__PVT__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__data + [this->__Vdlyvdim0__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__data__v37], this->__Vdlyvval__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__data__v37); + } + if (this->__Vdlyvset__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__data__v38) { + VL_ASSIGNSEL_WIII(8,(IData)(this->__Vdlyvlsb__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__data__v38), + this->__PVT__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__data + [this->__Vdlyvdim0__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__data__v38], this->__Vdlyvval__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__data__v38); + } + if (this->__Vdlyvset__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__data__v39) { + VL_ASSIGNSEL_WIII(8,(IData)(this->__Vdlyvlsb__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__data__v39), + this->__PVT__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__data + [this->__Vdlyvdim0__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__data__v39], this->__Vdlyvval__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__data__v39); + } + if (this->__Vdlyvset__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__data__v40) { + VL_ASSIGNSEL_WIII(8,(IData)(this->__Vdlyvlsb__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__data__v40), + this->__PVT__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__data + [this->__Vdlyvdim0__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__data__v40], this->__Vdlyvval__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__data__v40); + } + if (this->__Vdlyvset__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__data__v41) { + VL_ASSIGNSEL_WIII(8,(IData)(this->__Vdlyvlsb__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__data__v41), + this->__PVT__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__data + [this->__Vdlyvdim0__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__data__v41], this->__Vdlyvval__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__data__v41); + } + if (this->__Vdlyvset__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__data__v42) { + VL_ASSIGNSEL_WIII(8,(IData)(this->__Vdlyvlsb__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__data__v42), + this->__PVT__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__data + [this->__Vdlyvdim0__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__data__v42], this->__Vdlyvval__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__data__v42); + } + if (this->__Vdlyvset__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__data__v43) { + VL_ASSIGNSEL_WIII(8,(IData)(this->__Vdlyvlsb__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__data__v43), + this->__PVT__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__data + [this->__Vdlyvdim0__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__data__v43], this->__Vdlyvval__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__data__v43); + } + if (this->__Vdlyvset__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__data__v44) { + VL_ASSIGNSEL_WIII(8,(IData)(this->__Vdlyvlsb__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__data__v44), + this->__PVT__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__data + [this->__Vdlyvdim0__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__data__v44], this->__Vdlyvval__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__data__v44); + } + if (this->__Vdlyvset__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__data__v45) { + VL_ASSIGNSEL_WIII(8,(IData)(this->__Vdlyvlsb__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__data__v45), + this->__PVT__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__data + [this->__Vdlyvdim0__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__data__v45], this->__Vdlyvval__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__data__v45); + } + if (this->__Vdlyvset__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__data__v46) { + VL_ASSIGNSEL_WIII(8,(IData)(this->__Vdlyvlsb__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__data__v46), + this->__PVT__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__data + [this->__Vdlyvdim0__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__data__v46], this->__Vdlyvval__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__data__v46); + } + if (this->__Vdlyvset__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__data__v47) { + VL_ASSIGNSEL_WIII(8,(IData)(this->__Vdlyvlsb__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__data__v47), + this->__PVT__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__data + [this->__Vdlyvdim0__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__data__v47], this->__Vdlyvval__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__data__v47); + } +} + +VL_INLINE_OPT void Vcache_simX_VX_Cache_Bank__pi7::_combo__TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__2__KET____DOT__bank_structure__11(Vcache_simX__Syms* __restrict vlSymsp) { + VL_DEBUG_IF(VL_DBG_MSGF("+ Vcache_simX_VX_Cache_Bank__pi7::_combo__TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__2__KET____DOT__bank_structure__11\n"); ); + Vcache_simX* __restrict vlTOPp VL_ATTR_UNUSED = vlSymsp->TOPp; + // Variables + WData/*31:0*/ __Vtemp243[4]; + WData/*31:0*/ __Vtemp244[4]; + WData/*31:0*/ __Vtemp245[4]; + WData/*31:0*/ __Vtemp246[4]; + WData/*31:0*/ __Vtemp247[4]; + WData/*31:0*/ __Vtemp248[4]; + WData/*31:0*/ __Vtemp249[4]; + // Body + this->__PVT__write_from_mem = ((2U == (IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT__state)) + & (IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__2__KET____DOT__use_valid_in)); + this->__PVT__access = ((0U == (IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT__state)) + & (IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__2__KET____DOT__use_valid_in)); + this->data_structures__DOT____Vcellout__each_way__BRA__0__KET____DOT__data_structures__dirty_use + = this->__PVT__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__dirty + [(0x1fU & (vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__2__KET____DOT__bank_addr + >> 6U))]; + this->data_structures__DOT____Vcellout__each_way__BRA__1__KET____DOT__data_structures__dirty_use + = this->__PVT__data_structures__DOT__each_way__BRA__1__KET____DOT__data_structures__DOT__dirty + [(0x1fU & (vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__2__KET____DOT__bank_addr + >> 6U))]; + __Vtemp243[0U] = 0U; + __Vtemp243[1U] = 0U; + __Vtemp243[2U] = 0U; + __Vtemp243[3U] = 0U; + __Vtemp244[0U] = 0U; + __Vtemp244[1U] = 0U; + __Vtemp244[2U] = 0U; + __Vtemp244[3U] = 0U; + __Vtemp245[0U] = 0U; + __Vtemp245[1U] = 0U; + __Vtemp245[2U] = 0U; + __Vtemp245[3U] = 0U; + __Vtemp246[0U] = 0U; + __Vtemp246[1U] = 0U; + __Vtemp246[2U] = 0U; + __Vtemp246[3U] = 0U; + __Vtemp247[0U] = 0U; + __Vtemp247[1U] = 0U; + __Vtemp247[2U] = 0U; + __Vtemp247[3U] = 0U; + __Vtemp248[0U] = 0U; + __Vtemp248[1U] = 0U; + __Vtemp248[2U] = 0U; + __Vtemp248[3U] = 0U; + __Vtemp249[0U] = 0U; + __Vtemp249[1U] = 0U; + __Vtemp249[2U] = 0U; + __Vtemp249[3U] = 0U; + this->__PVT__use_write_data = ((0U == (IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__cache_driver_in_mem_write)) + ? ((1U == (3U & vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__2__KET____DOT__bank_addr)) + ? (0xff00U + & (__Vtemp243[ + (3U & + ((IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT__index_per_bank) + >> 4U))] + << 8U)) + : ((2U == (3U + & vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__2__KET____DOT__bank_addr)) + ? (0xff0000U + & (__Vtemp244[ + (3U + & ((IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT__index_per_bank) + >> 4U))] + << 0x10U)) + : ((3U + == + (3U + & vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__2__KET____DOT__bank_addr)) + ? (0xff000000U + & (__Vtemp245[ + (3U + & ((IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT__index_per_bank) + >> 4U))] + << 0x18U)) + : __Vtemp246[ + (3U + & ((IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT__index_per_bank) + >> 4U))]))) + : ((1U == (IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__cache_driver_in_mem_write)) + ? ((2U == (3U + & vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__2__KET____DOT__bank_addr)) + ? (0xffff0000U + & (__Vtemp247[ + (3U + & ((IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT__index_per_bank) + >> 4U))] + << 0x10U)) + : __Vtemp248[ + (3U & ((IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT__index_per_bank) + >> 4U))]) + : __Vtemp249[ + (3U & ((IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT__index_per_bank) + >> 4U))])); + this->__PVT__sb_mask = ((0U == (3U & vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__2__KET____DOT__bank_addr)) + ? 1U : ((1U == (3U & vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__2__KET____DOT__bank_addr)) + ? 2U : ((2U == + (3U + & vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__2__KET____DOT__bank_addr)) + ? 4U + : 8U))); + this->__PVT__data_structures__DOT__data_use_per_way[0U] + = this->__PVT__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__data + [(0x1fU & (vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__2__KET____DOT__bank_addr + >> 6U))][0U]; + this->__PVT__data_structures__DOT__data_use_per_way[1U] + = this->__PVT__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__data + [(0x1fU & (vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__2__KET____DOT__bank_addr + >> 6U))][1U]; + this->__PVT__data_structures__DOT__data_use_per_way[2U] + = this->__PVT__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__data + [(0x1fU & (vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__2__KET____DOT__bank_addr + >> 6U))][2U]; + this->__PVT__data_structures__DOT__data_use_per_way[3U] + = this->__PVT__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__data + [(0x1fU & (vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__2__KET____DOT__bank_addr + >> 6U))][3U]; + this->__PVT__data_structures__DOT__data_use_per_way[4U] + = this->__PVT__data_structures__DOT__each_way__BRA__1__KET____DOT__data_structures__DOT__data + [(0x1fU & (vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__2__KET____DOT__bank_addr + >> 6U))][0U]; + this->__PVT__data_structures__DOT__data_use_per_way[5U] + = this->__PVT__data_structures__DOT__each_way__BRA__1__KET____DOT__data_structures__DOT__data + [(0x1fU & (vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__2__KET____DOT__bank_addr + >> 6U))][1U]; + this->__PVT__data_structures__DOT__data_use_per_way[6U] + = this->__PVT__data_structures__DOT__each_way__BRA__1__KET____DOT__data_structures__DOT__data + [(0x1fU & (vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__2__KET____DOT__bank_addr + >> 6U))][2U]; + this->__PVT__data_structures__DOT__data_use_per_way[7U] + = this->__PVT__data_structures__DOT__each_way__BRA__1__KET____DOT__data_structures__DOT__data + [(0x1fU & (vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__2__KET____DOT__bank_addr + >> 6U))][3U]; + this->__PVT__data_structures__DOT__valid_use_per_way + = ((2U & (IData)(this->__PVT__data_structures__DOT__valid_use_per_way)) + | this->__PVT__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__valid + [(0x1fU & (vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__2__KET____DOT__bank_addr + >> 6U))]); + this->__PVT__data_structures__DOT__valid_use_per_way + = ((1U & (IData)(this->__PVT__data_structures__DOT__valid_use_per_way)) + | (this->__PVT__data_structures__DOT__each_way__BRA__1__KET____DOT__data_structures__DOT__valid + [(0x1fU & (vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__2__KET____DOT__bank_addr + >> 6U))] << 1U)); + this->__PVT__data_structures__DOT__tag_use_per_way + = ((VL_ULL(0x3ffffe00000) & this->__PVT__data_structures__DOT__tag_use_per_way) + | (IData)((IData)(this->__PVT__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__tag + [(0x1fU & (vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__2__KET____DOT__bank_addr + >> 6U))]))); + this->__PVT__data_structures__DOT__tag_use_per_way + = ((VL_ULL(0x1fffff) & this->__PVT__data_structures__DOT__tag_use_per_way) + | ((QData)((IData)(this->__PVT__data_structures__DOT__each_way__BRA__1__KET____DOT__data_structures__DOT__tag + [(0x1fU & (vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__2__KET____DOT__bank_addr + >> 6U))])) + << 0x15U)); + this->__PVT__data_structures__DOT__dirty_use_per_way + = ((2U & (IData)(this->__PVT__data_structures__DOT__dirty_use_per_way)) + | (IData)(this->data_structures__DOT____Vcellout__each_way__BRA__0__KET____DOT__data_structures__dirty_use)); + this->__PVT__data_structures__DOT__dirty_use_per_way + = ((1U & (IData)(this->__PVT__data_structures__DOT__dirty_use_per_way)) + | ((IData)(this->data_structures__DOT____Vcellout__each_way__BRA__1__KET____DOT__data_structures__dirty_use) + << 1U)); + this->__PVT__data_write[0U] = ((IData)(this->__PVT__write_from_mem) + ? vlSymsp->TOP__cache_simX__DOT__VX_dram_req_rsp.i_m_readdata[8U] + : this->__PVT__use_write_data); + this->__PVT__data_write[1U] = ((IData)(this->__PVT__write_from_mem) + ? vlSymsp->TOP__cache_simX__DOT__VX_dram_req_rsp.i_m_readdata[9U] + : this->__PVT__use_write_data); + this->__PVT__data_write[2U] = ((IData)(this->__PVT__write_from_mem) + ? vlSymsp->TOP__cache_simX__DOT__VX_dram_req_rsp.i_m_readdata[0xaU] + : this->__PVT__use_write_data); + this->__PVT__data_write[3U] = ((IData)(this->__PVT__write_from_mem) + ? vlSymsp->TOP__cache_simX__DOT__VX_dram_req_rsp.i_m_readdata[0xbU] + : this->__PVT__use_write_data); + this->__PVT__data_structures__DOT__invalid_found = 0U; + if ((1U & (~ ((IData)(this->__PVT__data_structures__DOT__valid_use_per_way) + >> 1U)))) { + this->__PVT__data_structures__DOT__invalid_found = 1U; + } + if ((1U & (~ (IData)(this->__PVT__data_structures__DOT__valid_use_per_way)))) { + this->__PVT__data_structures__DOT__invalid_found = 1U; + } + this->__PVT__data_structures__DOT__invalid_index = 0U; + if ((1U & (~ ((IData)(this->__PVT__data_structures__DOT__valid_use_per_way) + >> 1U)))) { + this->__PVT__data_structures__DOT__invalid_index = 1U; + } + if ((1U & (~ (IData)(this->__PVT__data_structures__DOT__valid_use_per_way)))) { + this->__PVT__data_structures__DOT__invalid_index = 0U; + } + this->__PVT__data_structures__DOT__hit_per_way + = ((2U & (IData)(this->__PVT__data_structures__DOT__hit_per_way)) + | (((IData)(this->__PVT__data_structures__DOT__valid_use_per_way) + & ((0x1fffffU & (IData)(this->__PVT__data_structures__DOT__tag_use_per_way)) + == (0x1fffffU & (vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__2__KET____DOT__bank_addr + >> 0xbU)))) ? 1U + : 0U)); + this->__PVT__data_structures__DOT__hit_per_way + = ((1U & (IData)(this->__PVT__data_structures__DOT__hit_per_way)) + | (((((IData)(this->__PVT__data_structures__DOT__valid_use_per_way) + >> 1U) & ((0x1fffffU & (IData)((this->__PVT__data_structures__DOT__tag_use_per_way + >> 0x15U))) + == (0x1fffffU & (vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__2__KET____DOT__bank_addr + >> 0xbU)))) + ? 1U : 0U) << 1U)); + this->__PVT__data_structures__DOT__data_write_per_way[0U] + = this->__PVT__data_write[0U]; + this->__PVT__data_structures__DOT__data_write_per_way[1U] + = this->__PVT__data_write[1U]; + this->__PVT__data_structures__DOT__data_write_per_way[2U] + = this->__PVT__data_write[2U]; + this->__PVT__data_structures__DOT__data_write_per_way[3U] + = this->__PVT__data_write[3U]; + this->__PVT__data_structures__DOT__data_write_per_way[4U] + = this->__PVT__data_write[0U]; + this->__PVT__data_structures__DOT__data_write_per_way[5U] + = this->__PVT__data_write[1U]; + this->__PVT__data_structures__DOT__data_write_per_way[6U] + = this->__PVT__data_write[2U]; + this->__PVT__data_structures__DOT__data_write_per_way[7U] + = this->__PVT__data_write[3U]; + this->__PVT__data_structures__DOT__genblk1__DOT__way_indexing__DOT__found = 0U; + if ((2U & (IData)(this->__PVT__data_structures__DOT__hit_per_way))) { + this->__PVT__data_structures__DOT__genblk1__DOT__way_indexing__DOT__found = 1U; + } + if ((1U & (IData)(this->__PVT__data_structures__DOT__hit_per_way))) { + this->__PVT__data_structures__DOT__genblk1__DOT__way_indexing__DOT__found = 1U; + } + this->__PVT__data_structures__DOT__way_index = 0U; + if ((2U & (IData)(this->__PVT__data_structures__DOT__hit_per_way))) { + this->__PVT__data_structures__DOT__way_index = 1U; + } + if ((1U & (IData)(this->__PVT__data_structures__DOT__hit_per_way))) { + this->__PVT__data_structures__DOT__way_index = 0U; + } + this->__PVT__data_structures__DOT__way_use_Qual + = ((0U != (IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT__state)) + ? (IData)(this->__PVT__way_to_update) : (IData)(this->__PVT__data_structures__DOT__way_index)); + this->__PVT__data_structures__DOT__write_from_mem_per_way + = ((2U & (IData)(this->__PVT__data_structures__DOT__write_from_mem_per_way)) + | ((IData)(this->__PVT__write_from_mem) + & (~ (IData)(this->__PVT__data_structures__DOT__way_use_Qual)))); + this->__PVT__data_structures__DOT__write_from_mem_per_way + = ((1U & (IData)(this->__PVT__data_structures__DOT__write_from_mem_per_way)) + | (((IData)(this->__PVT__write_from_mem) + & (IData)(this->__PVT__data_structures__DOT__way_use_Qual)) + << 1U)); + this->__Vcellout__data_structures__data_use[0U] + = (((0U == (0x1fU & ((IData)(this->__PVT__data_structures__DOT__way_use_Qual) + << 7U))) ? 0U : (this->__PVT__data_structures__DOT__data_use_per_way[ + ((IData)(1U) + + (4U + & ((IData)(this->__PVT__data_structures__DOT__way_use_Qual) + << 2U)))] + << ((IData)(0x20U) + - + (0x1fU + & ((IData)(this->__PVT__data_structures__DOT__way_use_Qual) + << 7U))))) + | (this->__PVT__data_structures__DOT__data_use_per_way[ + (4U & ((IData)(this->__PVT__data_structures__DOT__way_use_Qual) + << 2U))] >> (0x1fU & ((IData)(this->__PVT__data_structures__DOT__way_use_Qual) + << 7U)))); + this->__Vcellout__data_structures__data_use[1U] + = (((0U == (0x1fU & ((IData)(this->__PVT__data_structures__DOT__way_use_Qual) + << 7U))) ? 0U : (this->__PVT__data_structures__DOT__data_use_per_way[ + ((IData)(2U) + + (4U + & ((IData)(this->__PVT__data_structures__DOT__way_use_Qual) + << 2U)))] + << ((IData)(0x20U) + - + (0x1fU + & ((IData)(this->__PVT__data_structures__DOT__way_use_Qual) + << 7U))))) + | (this->__PVT__data_structures__DOT__data_use_per_way[ + ((IData)(1U) + (4U & ((IData)(this->__PVT__data_structures__DOT__way_use_Qual) + << 2U)))] >> (0x1fU + & ((IData)(this->__PVT__data_structures__DOT__way_use_Qual) + << 7U)))); + this->__Vcellout__data_structures__data_use[2U] + = (((0U == (0x1fU & ((IData)(this->__PVT__data_structures__DOT__way_use_Qual) + << 7U))) ? 0U : (this->__PVT__data_structures__DOT__data_use_per_way[ + ((IData)(3U) + + (4U + & ((IData)(this->__PVT__data_structures__DOT__way_use_Qual) + << 2U)))] + << ((IData)(0x20U) + - + (0x1fU + & ((IData)(this->__PVT__data_structures__DOT__way_use_Qual) + << 7U))))) + | (this->__PVT__data_structures__DOT__data_use_per_way[ + ((IData)(2U) + (4U & ((IData)(this->__PVT__data_structures__DOT__way_use_Qual) + << 2U)))] >> (0x1fU + & ((IData)(this->__PVT__data_structures__DOT__way_use_Qual) + << 7U)))); + this->__Vcellout__data_structures__data_use[3U] + = (((0U == (0x1fU & ((IData)(this->__PVT__data_structures__DOT__way_use_Qual) + << 7U))) ? 0U : (this->__PVT__data_structures__DOT__data_use_per_way[ + ((IData)(4U) + + (4U + & ((IData)(this->__PVT__data_structures__DOT__way_use_Qual) + << 2U)))] + << ((IData)(0x20U) + - + (0x1fU + & ((IData)(this->__PVT__data_structures__DOT__way_use_Qual) + << 7U))))) + | (this->__PVT__data_structures__DOT__data_use_per_way[ + ((IData)(3U) + (4U & ((IData)(this->__PVT__data_structures__DOT__way_use_Qual) + << 2U)))] >> (0x1fU + & ((IData)(this->__PVT__data_structures__DOT__way_use_Qual) + << 7U)))); + this->__PVT__valid_use = (1U & ((IData)(this->__PVT__data_structures__DOT__valid_use_per_way) + >> (IData)(this->__PVT__data_structures__DOT__way_use_Qual))); + this->__PVT__tag_use = ((0x29U >= (0x3fU & ((IData)(0x15U) + * (IData)(this->__PVT__data_structures__DOT__way_use_Qual)))) + ? (0x1fffffU & (IData)( + (this->__PVT__data_structures__DOT__tag_use_per_way + >> + (0x3fU + & ((IData)(0x15U) + * (IData)(this->__PVT__data_structures__DOT__way_use_Qual)))))) + : 0U); + this->__PVT__data_unQual = (((0U == (3U & vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__2__KET____DOT__bank_addr)) + | (2U == (IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__cache_driver_in_mem_read))) + ? this->__Vcellout__data_structures__data_use[ + (3U & (vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__2__KET____DOT__bank_addr + >> 4U))] : ( + (1U + == + (3U + & vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__2__KET____DOT__bank_addr)) + ? + (this->__Vcellout__data_structures__data_use[ + (3U + & (vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__2__KET____DOT__bank_addr + >> 4U))] + >> 8U) + : + ((2U + == + (3U + & vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__2__KET____DOT__bank_addr)) + ? + (this->__Vcellout__data_structures__data_use[ + (3U + & (vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__2__KET____DOT__bank_addr + >> 4U))] + >> 0x10U) + : + (this->__Vcellout__data_structures__data_use[ + (3U + & (vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__2__KET____DOT__bank_addr + >> 4U))] + >> 0x18U)))); + this->__PVT__miss = (((this->__PVT__tag_use != + (0x1fffffU & (vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__2__KET____DOT__bank_addr + >> 0xbU))) + & (IData)(this->__PVT__valid_use)) + & (IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__2__KET____DOT__use_valid_in)); + this->__PVT__genblk1__BRA__0__KET____DOT__normal_write + = (((IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__read_or_write) + & ((IData)(this->__PVT__access) & (0U == + (3U + & (vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__2__KET____DOT__bank_addr + >> 4U))))) + & (~ (IData)(this->__PVT__miss))); + this->__PVT__genblk1__BRA__1__KET____DOT__normal_write + = (((IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__read_or_write) + & ((IData)(this->__PVT__access) & (1U == + (3U + & (vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__2__KET____DOT__bank_addr + >> 4U))))) + & (~ (IData)(this->__PVT__miss))); + this->__PVT__genblk1__BRA__2__KET____DOT__normal_write + = (((IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__read_or_write) + & ((IData)(this->__PVT__access) & (2U == + (3U + & (vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__2__KET____DOT__bank_addr + >> 4U))))) + & (~ (IData)(this->__PVT__miss))); + this->__PVT__genblk1__BRA__3__KET____DOT__normal_write + = (((IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__read_or_write) + & ((IData)(this->__PVT__access) & (3U == + (3U + & (vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__2__KET____DOT__bank_addr + >> 4U))))) + & (~ (IData)(this->__PVT__miss))); + this->__PVT__we = ((0xfff0U & (IData)(this->__PVT__we)) + | ((IData)(this->__PVT__write_from_mem) + ? 0xfU : (((IData)(this->__PVT__genblk1__BRA__0__KET____DOT__normal_write) + & (2U == (IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__cache_driver_in_mem_write))) + ? 0xfU : (((IData)(this->__PVT__genblk1__BRA__0__KET____DOT__normal_write) + & (0U + == (IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__cache_driver_in_mem_write))) + ? (IData)(this->__PVT__sb_mask) + : + (((IData)(this->__PVT__genblk1__BRA__0__KET____DOT__normal_write) + & (1U + == (IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__cache_driver_in_mem_write))) + ? + ((0U + == + (3U + & vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__2__KET____DOT__bank_addr)) + ? 3U + : 0xcU) + : 0U))))); + this->__PVT__we = ((0xff0fU & (IData)(this->__PVT__we)) + | (((IData)(this->__PVT__write_from_mem) + ? 0xfU : (((IData)(this->__PVT__genblk1__BRA__1__KET____DOT__normal_write) + & (2U == (IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__cache_driver_in_mem_write))) + ? 0xfU : (((IData)(this->__PVT__genblk1__BRA__1__KET____DOT__normal_write) + & (0U + == (IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__cache_driver_in_mem_write))) + ? (IData)(this->__PVT__sb_mask) + : + (((IData)(this->__PVT__genblk1__BRA__1__KET____DOT__normal_write) + & (1U + == (IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__cache_driver_in_mem_write))) + ? + ((0U + == + (3U + & vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__2__KET____DOT__bank_addr)) + ? 3U + : 0xcU) + : 0U)))) + << 4U)); + this->__PVT__we = ((0xf0ffU & (IData)(this->__PVT__we)) + | (((IData)(this->__PVT__write_from_mem) + ? 0xfU : (((IData)(this->__PVT__genblk1__BRA__2__KET____DOT__normal_write) + & (2U == (IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__cache_driver_in_mem_write))) + ? 0xfU : (((IData)(this->__PVT__genblk1__BRA__2__KET____DOT__normal_write) + & (0U + == (IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__cache_driver_in_mem_write))) + ? (IData)(this->__PVT__sb_mask) + : + (((IData)(this->__PVT__genblk1__BRA__2__KET____DOT__normal_write) + & (1U + == (IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__cache_driver_in_mem_write))) + ? + ((0U + == + (3U + & vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__2__KET____DOT__bank_addr)) + ? 3U + : 0xcU) + : 0U)))) + << 8U)); + this->__PVT__we = ((0xfffU & (IData)(this->__PVT__we)) + | (((IData)(this->__PVT__write_from_mem) + ? 0xfU : (((IData)(this->__PVT__genblk1__BRA__3__KET____DOT__normal_write) + & (2U == (IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__cache_driver_in_mem_write))) + ? 0xfU : (((IData)(this->__PVT__genblk1__BRA__3__KET____DOT__normal_write) + & (0U + == (IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__cache_driver_in_mem_write))) + ? (IData)(this->__PVT__sb_mask) + : + (((IData)(this->__PVT__genblk1__BRA__3__KET____DOT__normal_write) + & (1U + == (IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__cache_driver_in_mem_write))) + ? + ((0U + == + (3U + & vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__2__KET____DOT__bank_addr)) + ? 3U + : 0xcU) + : 0U)))) + << 0xcU)); + this->__PVT__data_structures__DOT__we_per_way = + ((0xffff0000U & this->__PVT__data_structures__DOT__we_per_way) + | ((IData)(this->__PVT__data_structures__DOT__way_use_Qual) + ? 0U : (0xffffU & (IData)(this->__PVT__we)))); + this->__PVT__data_structures__DOT__we_per_way = + ((0xffffU & this->__PVT__data_structures__DOT__we_per_way) + | (((IData)(this->__PVT__data_structures__DOT__way_use_Qual) + ? (0xffffU & (IData)(this->__PVT__we)) + : 0U) << 0x10U)); +} + +void Vcache_simX_VX_Cache_Bank__pi7::_settle__TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__3__KET____DOT__bank_structure__4(Vcache_simX__Syms* __restrict vlSymsp) { + VL_DEBUG_IF(VL_DBG_MSGF("+ Vcache_simX_VX_Cache_Bank__pi7::_settle__TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__3__KET____DOT__bank_structure__4\n"); ); + Vcache_simX* __restrict vlTOPp VL_ATTR_UNUSED = vlSymsp->TOPp; + // Variables + WData/*31:0*/ __Vtemp253[4]; + WData/*31:0*/ __Vtemp254[4]; + WData/*31:0*/ __Vtemp255[4]; + WData/*31:0*/ __Vtemp256[4]; + WData/*31:0*/ __Vtemp257[4]; + WData/*31:0*/ __Vtemp258[4]; + WData/*31:0*/ __Vtemp259[4]; + // Body + this->__PVT__way_to_update = vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT__global_way_to_evict; + this->__PVT__write_from_mem = ((2U == (IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT__state)) + & (IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__3__KET____DOT__use_valid_in)); + this->__PVT__access = ((0U == (IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT__state)) + & (IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__3__KET____DOT__use_valid_in)); + this->data_structures__DOT____Vcellout__each_way__BRA__0__KET____DOT__data_structures__dirty_use + = this->__PVT__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__dirty + [(0x1fU & (vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__3__KET____DOT__bank_addr + >> 6U))]; + this->data_structures__DOT____Vcellout__each_way__BRA__1__KET____DOT__data_structures__dirty_use + = this->__PVT__data_structures__DOT__each_way__BRA__1__KET____DOT__data_structures__DOT__dirty + [(0x1fU & (vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__3__KET____DOT__bank_addr + >> 6U))]; + __Vtemp253[0U] = 0U; + __Vtemp253[1U] = 0U; + __Vtemp253[2U] = 0U; + __Vtemp253[3U] = 0U; + __Vtemp254[0U] = 0U; + __Vtemp254[1U] = 0U; + __Vtemp254[2U] = 0U; + __Vtemp254[3U] = 0U; + __Vtemp255[0U] = 0U; + __Vtemp255[1U] = 0U; + __Vtemp255[2U] = 0U; + __Vtemp255[3U] = 0U; + __Vtemp256[0U] = 0U; + __Vtemp256[1U] = 0U; + __Vtemp256[2U] = 0U; + __Vtemp256[3U] = 0U; + __Vtemp257[0U] = 0U; + __Vtemp257[1U] = 0U; + __Vtemp257[2U] = 0U; + __Vtemp257[3U] = 0U; + __Vtemp258[0U] = 0U; + __Vtemp258[1U] = 0U; + __Vtemp258[2U] = 0U; + __Vtemp258[3U] = 0U; + __Vtemp259[0U] = 0U; + __Vtemp259[1U] = 0U; + __Vtemp259[2U] = 0U; + __Vtemp259[3U] = 0U; + this->__PVT__use_write_data = ((0U == (IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__cache_driver_in_mem_write)) + ? ((1U == (3U & vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__3__KET____DOT__bank_addr)) + ? (0xff00U + & (__Vtemp253[ + (3U & + ((IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT__index_per_bank) + >> 6U))] + << 8U)) + : ((2U == (3U + & vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__3__KET____DOT__bank_addr)) + ? (0xff0000U + & (__Vtemp254[ + (3U + & ((IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT__index_per_bank) + >> 6U))] + << 0x10U)) + : ((3U + == + (3U + & vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__3__KET____DOT__bank_addr)) + ? (0xff000000U + & (__Vtemp255[ + (3U + & ((IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT__index_per_bank) + >> 6U))] + << 0x18U)) + : __Vtemp256[ + (3U + & ((IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT__index_per_bank) + >> 6U))]))) + : ((1U == (IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__cache_driver_in_mem_write)) + ? ((2U == (3U + & vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__3__KET____DOT__bank_addr)) + ? (0xffff0000U + & (__Vtemp257[ + (3U + & ((IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT__index_per_bank) + >> 6U))] + << 0x10U)) + : __Vtemp258[ + (3U & ((IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT__index_per_bank) + >> 6U))]) + : __Vtemp259[ + (3U & ((IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT__index_per_bank) + >> 6U))])); + this->__PVT__sb_mask = ((0U == (3U & vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__3__KET____DOT__bank_addr)) + ? 1U : ((1U == (3U & vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__3__KET____DOT__bank_addr)) + ? 2U : ((2U == + (3U + & vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__3__KET____DOT__bank_addr)) + ? 4U + : 8U))); + this->__PVT__data_structures__DOT__data_use_per_way[0U] + = this->__PVT__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__data + [(0x1fU & (vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__3__KET____DOT__bank_addr + >> 6U))][0U]; + this->__PVT__data_structures__DOT__data_use_per_way[1U] + = this->__PVT__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__data + [(0x1fU & (vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__3__KET____DOT__bank_addr + >> 6U))][1U]; + this->__PVT__data_structures__DOT__data_use_per_way[2U] + = this->__PVT__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__data + [(0x1fU & (vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__3__KET____DOT__bank_addr + >> 6U))][2U]; + this->__PVT__data_structures__DOT__data_use_per_way[3U] + = this->__PVT__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__data + [(0x1fU & (vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__3__KET____DOT__bank_addr + >> 6U))][3U]; + this->__PVT__data_structures__DOT__data_use_per_way[4U] + = this->__PVT__data_structures__DOT__each_way__BRA__1__KET____DOT__data_structures__DOT__data + [(0x1fU & (vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__3__KET____DOT__bank_addr + >> 6U))][0U]; + this->__PVT__data_structures__DOT__data_use_per_way[5U] + = this->__PVT__data_structures__DOT__each_way__BRA__1__KET____DOT__data_structures__DOT__data + [(0x1fU & (vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__3__KET____DOT__bank_addr + >> 6U))][1U]; + this->__PVT__data_structures__DOT__data_use_per_way[6U] + = this->__PVT__data_structures__DOT__each_way__BRA__1__KET____DOT__data_structures__DOT__data + [(0x1fU & (vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__3__KET____DOT__bank_addr + >> 6U))][2U]; + this->__PVT__data_structures__DOT__data_use_per_way[7U] + = this->__PVT__data_structures__DOT__each_way__BRA__1__KET____DOT__data_structures__DOT__data + [(0x1fU & (vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__3__KET____DOT__bank_addr + >> 6U))][3U]; + this->__PVT__data_structures__DOT__valid_use_per_way + = ((2U & (IData)(this->__PVT__data_structures__DOT__valid_use_per_way)) + | this->__PVT__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__valid + [(0x1fU & (vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__3__KET____DOT__bank_addr + >> 6U))]); + this->__PVT__data_structures__DOT__valid_use_per_way + = ((1U & (IData)(this->__PVT__data_structures__DOT__valid_use_per_way)) + | (this->__PVT__data_structures__DOT__each_way__BRA__1__KET____DOT__data_structures__DOT__valid + [(0x1fU & (vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__3__KET____DOT__bank_addr + >> 6U))] << 1U)); + this->__PVT__data_structures__DOT__tag_use_per_way + = ((VL_ULL(0x3ffffe00000) & this->__PVT__data_structures__DOT__tag_use_per_way) + | (IData)((IData)(this->__PVT__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__tag + [(0x1fU & (vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__3__KET____DOT__bank_addr + >> 6U))]))); + this->__PVT__data_structures__DOT__tag_use_per_way + = ((VL_ULL(0x1fffff) & this->__PVT__data_structures__DOT__tag_use_per_way) + | ((QData)((IData)(this->__PVT__data_structures__DOT__each_way__BRA__1__KET____DOT__data_structures__DOT__tag + [(0x1fU & (vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__3__KET____DOT__bank_addr + >> 6U))])) + << 0x15U)); + this->__PVT__data_structures__DOT__dirty_use_per_way + = ((2U & (IData)(this->__PVT__data_structures__DOT__dirty_use_per_way)) + | (IData)(this->data_structures__DOT____Vcellout__each_way__BRA__0__KET____DOT__data_structures__dirty_use)); + this->__PVT__data_structures__DOT__dirty_use_per_way + = ((1U & (IData)(this->__PVT__data_structures__DOT__dirty_use_per_way)) + | ((IData)(this->data_structures__DOT____Vcellout__each_way__BRA__1__KET____DOT__data_structures__dirty_use) + << 1U)); + this->__PVT__data_write[0U] = ((IData)(this->__PVT__write_from_mem) + ? vlSymsp->TOP__cache_simX__DOT__VX_dram_req_rsp.i_m_readdata[0xcU] + : this->__PVT__use_write_data); + this->__PVT__data_write[1U] = ((IData)(this->__PVT__write_from_mem) + ? vlSymsp->TOP__cache_simX__DOT__VX_dram_req_rsp.i_m_readdata[0xdU] + : this->__PVT__use_write_data); + this->__PVT__data_write[2U] = ((IData)(this->__PVT__write_from_mem) + ? vlSymsp->TOP__cache_simX__DOT__VX_dram_req_rsp.i_m_readdata[0xeU] + : this->__PVT__use_write_data); + this->__PVT__data_write[3U] = ((IData)(this->__PVT__write_from_mem) + ? vlSymsp->TOP__cache_simX__DOT__VX_dram_req_rsp.i_m_readdata[0xfU] + : this->__PVT__use_write_data); + this->__PVT__data_structures__DOT__invalid_found = 0U; + if ((1U & (~ ((IData)(this->__PVT__data_structures__DOT__valid_use_per_way) + >> 1U)))) { + this->__PVT__data_structures__DOT__invalid_found = 1U; + } + if ((1U & (~ (IData)(this->__PVT__data_structures__DOT__valid_use_per_way)))) { + this->__PVT__data_structures__DOT__invalid_found = 1U; + } + this->__PVT__data_structures__DOT__invalid_index = 0U; + if ((1U & (~ ((IData)(this->__PVT__data_structures__DOT__valid_use_per_way) + >> 1U)))) { + this->__PVT__data_structures__DOT__invalid_index = 1U; + } + if ((1U & (~ (IData)(this->__PVT__data_structures__DOT__valid_use_per_way)))) { + this->__PVT__data_structures__DOT__invalid_index = 0U; + } + this->__PVT__data_structures__DOT__hit_per_way + = ((2U & (IData)(this->__PVT__data_structures__DOT__hit_per_way)) + | (((IData)(this->__PVT__data_structures__DOT__valid_use_per_way) + & ((0x1fffffU & (IData)(this->__PVT__data_structures__DOT__tag_use_per_way)) + == (0x1fffffU & (vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__3__KET____DOT__bank_addr + >> 0xbU)))) ? 1U + : 0U)); + this->__PVT__data_structures__DOT__hit_per_way + = ((1U & (IData)(this->__PVT__data_structures__DOT__hit_per_way)) + | (((((IData)(this->__PVT__data_structures__DOT__valid_use_per_way) + >> 1U) & ((0x1fffffU & (IData)((this->__PVT__data_structures__DOT__tag_use_per_way + >> 0x15U))) + == (0x1fffffU & (vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__3__KET____DOT__bank_addr + >> 0xbU)))) + ? 1U : 0U) << 1U)); + this->__PVT__data_structures__DOT__data_write_per_way[0U] + = this->__PVT__data_write[0U]; + this->__PVT__data_structures__DOT__data_write_per_way[1U] + = this->__PVT__data_write[1U]; + this->__PVT__data_structures__DOT__data_write_per_way[2U] + = this->__PVT__data_write[2U]; + this->__PVT__data_structures__DOT__data_write_per_way[3U] + = this->__PVT__data_write[3U]; + this->__PVT__data_structures__DOT__data_write_per_way[4U] + = this->__PVT__data_write[0U]; + this->__PVT__data_structures__DOT__data_write_per_way[5U] + = this->__PVT__data_write[1U]; + this->__PVT__data_structures__DOT__data_write_per_way[6U] + = this->__PVT__data_write[2U]; + this->__PVT__data_structures__DOT__data_write_per_way[7U] + = this->__PVT__data_write[3U]; + this->__PVT__data_structures__DOT__genblk1__DOT__way_indexing__DOT__found = 0U; + if ((2U & (IData)(this->__PVT__data_structures__DOT__hit_per_way))) { + this->__PVT__data_structures__DOT__genblk1__DOT__way_indexing__DOT__found = 1U; + } + if ((1U & (IData)(this->__PVT__data_structures__DOT__hit_per_way))) { + this->__PVT__data_structures__DOT__genblk1__DOT__way_indexing__DOT__found = 1U; + } + this->__PVT__data_structures__DOT__way_index = 0U; + if ((2U & (IData)(this->__PVT__data_structures__DOT__hit_per_way))) { + this->__PVT__data_structures__DOT__way_index = 1U; + } + if ((1U & (IData)(this->__PVT__data_structures__DOT__hit_per_way))) { + this->__PVT__data_structures__DOT__way_index = 0U; + } + this->__PVT__data_structures__DOT__way_use_Qual + = ((0U != (IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT__state)) + ? (IData)(this->__PVT__way_to_update) : (IData)(this->__PVT__data_structures__DOT__way_index)); + this->__PVT__data_structures__DOT__write_from_mem_per_way + = ((2U & (IData)(this->__PVT__data_structures__DOT__write_from_mem_per_way)) + | ((IData)(this->__PVT__write_from_mem) + & (~ (IData)(this->__PVT__data_structures__DOT__way_use_Qual)))); + this->__PVT__data_structures__DOT__write_from_mem_per_way + = ((1U & (IData)(this->__PVT__data_structures__DOT__write_from_mem_per_way)) + | (((IData)(this->__PVT__write_from_mem) + & (IData)(this->__PVT__data_structures__DOT__way_use_Qual)) + << 1U)); + this->__Vcellout__data_structures__data_use[0U] + = (((0U == (0x1fU & ((IData)(this->__PVT__data_structures__DOT__way_use_Qual) + << 7U))) ? 0U : (this->__PVT__data_structures__DOT__data_use_per_way[ + ((IData)(1U) + + (4U + & ((IData)(this->__PVT__data_structures__DOT__way_use_Qual) + << 2U)))] + << ((IData)(0x20U) + - + (0x1fU + & ((IData)(this->__PVT__data_structures__DOT__way_use_Qual) + << 7U))))) + | (this->__PVT__data_structures__DOT__data_use_per_way[ + (4U & ((IData)(this->__PVT__data_structures__DOT__way_use_Qual) + << 2U))] >> (0x1fU & ((IData)(this->__PVT__data_structures__DOT__way_use_Qual) + << 7U)))); + this->__Vcellout__data_structures__data_use[1U] + = (((0U == (0x1fU & ((IData)(this->__PVT__data_structures__DOT__way_use_Qual) + << 7U))) ? 0U : (this->__PVT__data_structures__DOT__data_use_per_way[ + ((IData)(2U) + + (4U + & ((IData)(this->__PVT__data_structures__DOT__way_use_Qual) + << 2U)))] + << ((IData)(0x20U) + - + (0x1fU + & ((IData)(this->__PVT__data_structures__DOT__way_use_Qual) + << 7U))))) + | (this->__PVT__data_structures__DOT__data_use_per_way[ + ((IData)(1U) + (4U & ((IData)(this->__PVT__data_structures__DOT__way_use_Qual) + << 2U)))] >> (0x1fU + & ((IData)(this->__PVT__data_structures__DOT__way_use_Qual) + << 7U)))); + this->__Vcellout__data_structures__data_use[2U] + = (((0U == (0x1fU & ((IData)(this->__PVT__data_structures__DOT__way_use_Qual) + << 7U))) ? 0U : (this->__PVT__data_structures__DOT__data_use_per_way[ + ((IData)(3U) + + (4U + & ((IData)(this->__PVT__data_structures__DOT__way_use_Qual) + << 2U)))] + << ((IData)(0x20U) + - + (0x1fU + & ((IData)(this->__PVT__data_structures__DOT__way_use_Qual) + << 7U))))) + | (this->__PVT__data_structures__DOT__data_use_per_way[ + ((IData)(2U) + (4U & ((IData)(this->__PVT__data_structures__DOT__way_use_Qual) + << 2U)))] >> (0x1fU + & ((IData)(this->__PVT__data_structures__DOT__way_use_Qual) + << 7U)))); + this->__Vcellout__data_structures__data_use[3U] + = (((0U == (0x1fU & ((IData)(this->__PVT__data_structures__DOT__way_use_Qual) + << 7U))) ? 0U : (this->__PVT__data_structures__DOT__data_use_per_way[ + ((IData)(4U) + + (4U + & ((IData)(this->__PVT__data_structures__DOT__way_use_Qual) + << 2U)))] + << ((IData)(0x20U) + - + (0x1fU + & ((IData)(this->__PVT__data_structures__DOT__way_use_Qual) + << 7U))))) + | (this->__PVT__data_structures__DOT__data_use_per_way[ + ((IData)(3U) + (4U & ((IData)(this->__PVT__data_structures__DOT__way_use_Qual) + << 2U)))] >> (0x1fU + & ((IData)(this->__PVT__data_structures__DOT__way_use_Qual) + << 7U)))); + this->__PVT__valid_use = (1U & ((IData)(this->__PVT__data_structures__DOT__valid_use_per_way) + >> (IData)(this->__PVT__data_structures__DOT__way_use_Qual))); + this->__PVT__tag_use = ((0x29U >= (0x3fU & ((IData)(0x15U) + * (IData)(this->__PVT__data_structures__DOT__way_use_Qual)))) + ? (0x1fffffU & (IData)( + (this->__PVT__data_structures__DOT__tag_use_per_way + >> + (0x3fU + & ((IData)(0x15U) + * (IData)(this->__PVT__data_structures__DOT__way_use_Qual)))))) + : 0U); + this->__PVT__data_unQual = (((0U == (3U & vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__3__KET____DOT__bank_addr)) + | (2U == (IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__cache_driver_in_mem_read))) + ? this->__Vcellout__data_structures__data_use[ + (3U & (vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__3__KET____DOT__bank_addr + >> 4U))] : ( + (1U + == + (3U + & vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__3__KET____DOT__bank_addr)) + ? + (this->__Vcellout__data_structures__data_use[ + (3U + & (vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__3__KET____DOT__bank_addr + >> 4U))] + >> 8U) + : + ((2U + == + (3U + & vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__3__KET____DOT__bank_addr)) + ? + (this->__Vcellout__data_structures__data_use[ + (3U + & (vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__3__KET____DOT__bank_addr + >> 4U))] + >> 0x10U) + : + (this->__Vcellout__data_structures__data_use[ + (3U + & (vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__3__KET____DOT__bank_addr + >> 4U))] + >> 0x18U)))); + this->__PVT__miss = (((this->__PVT__tag_use != + (0x1fffffU & (vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__3__KET____DOT__bank_addr + >> 0xbU))) + & (IData)(this->__PVT__valid_use)) + & (IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__3__KET____DOT__use_valid_in)); + this->__PVT__genblk1__BRA__0__KET____DOT__normal_write + = (((IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__read_or_write) + & ((IData)(this->__PVT__access) & (0U == + (3U + & (vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__3__KET____DOT__bank_addr + >> 4U))))) + & (~ (IData)(this->__PVT__miss))); + this->__PVT__genblk1__BRA__1__KET____DOT__normal_write + = (((IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__read_or_write) + & ((IData)(this->__PVT__access) & (1U == + (3U + & (vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__3__KET____DOT__bank_addr + >> 4U))))) + & (~ (IData)(this->__PVT__miss))); + this->__PVT__genblk1__BRA__2__KET____DOT__normal_write + = (((IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__read_or_write) + & ((IData)(this->__PVT__access) & (2U == + (3U + & (vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__3__KET____DOT__bank_addr + >> 4U))))) + & (~ (IData)(this->__PVT__miss))); + this->__PVT__genblk1__BRA__3__KET____DOT__normal_write + = (((IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__read_or_write) + & ((IData)(this->__PVT__access) & (3U == + (3U + & (vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__3__KET____DOT__bank_addr + >> 4U))))) + & (~ (IData)(this->__PVT__miss))); + this->__PVT__we = ((0xfff0U & (IData)(this->__PVT__we)) + | ((IData)(this->__PVT__write_from_mem) + ? 0xfU : (((IData)(this->__PVT__genblk1__BRA__0__KET____DOT__normal_write) + & (2U == (IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__cache_driver_in_mem_write))) + ? 0xfU : (((IData)(this->__PVT__genblk1__BRA__0__KET____DOT__normal_write) + & (0U + == (IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__cache_driver_in_mem_write))) + ? (IData)(this->__PVT__sb_mask) + : + (((IData)(this->__PVT__genblk1__BRA__0__KET____DOT__normal_write) + & (1U + == (IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__cache_driver_in_mem_write))) + ? + ((0U + == + (3U + & vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__3__KET____DOT__bank_addr)) + ? 3U + : 0xcU) + : 0U))))); + this->__PVT__we = ((0xff0fU & (IData)(this->__PVT__we)) + | (((IData)(this->__PVT__write_from_mem) + ? 0xfU : (((IData)(this->__PVT__genblk1__BRA__1__KET____DOT__normal_write) + & (2U == (IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__cache_driver_in_mem_write))) + ? 0xfU : (((IData)(this->__PVT__genblk1__BRA__1__KET____DOT__normal_write) + & (0U + == (IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__cache_driver_in_mem_write))) + ? (IData)(this->__PVT__sb_mask) + : + (((IData)(this->__PVT__genblk1__BRA__1__KET____DOT__normal_write) + & (1U + == (IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__cache_driver_in_mem_write))) + ? + ((0U + == + (3U + & vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__3__KET____DOT__bank_addr)) + ? 3U + : 0xcU) + : 0U)))) + << 4U)); + this->__PVT__we = ((0xf0ffU & (IData)(this->__PVT__we)) + | (((IData)(this->__PVT__write_from_mem) + ? 0xfU : (((IData)(this->__PVT__genblk1__BRA__2__KET____DOT__normal_write) + & (2U == (IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__cache_driver_in_mem_write))) + ? 0xfU : (((IData)(this->__PVT__genblk1__BRA__2__KET____DOT__normal_write) + & (0U + == (IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__cache_driver_in_mem_write))) + ? (IData)(this->__PVT__sb_mask) + : + (((IData)(this->__PVT__genblk1__BRA__2__KET____DOT__normal_write) + & (1U + == (IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__cache_driver_in_mem_write))) + ? + ((0U + == + (3U + & vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__3__KET____DOT__bank_addr)) + ? 3U + : 0xcU) + : 0U)))) + << 8U)); + this->__PVT__we = ((0xfffU & (IData)(this->__PVT__we)) + | (((IData)(this->__PVT__write_from_mem) + ? 0xfU : (((IData)(this->__PVT__genblk1__BRA__3__KET____DOT__normal_write) + & (2U == (IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__cache_driver_in_mem_write))) + ? 0xfU : (((IData)(this->__PVT__genblk1__BRA__3__KET____DOT__normal_write) + & (0U + == (IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__cache_driver_in_mem_write))) + ? (IData)(this->__PVT__sb_mask) + : + (((IData)(this->__PVT__genblk1__BRA__3__KET____DOT__normal_write) + & (1U + == (IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__cache_driver_in_mem_write))) + ? + ((0U + == + (3U + & vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__3__KET____DOT__bank_addr)) + ? 3U + : 0xcU) + : 0U)))) + << 0xcU)); + this->__PVT__data_structures__DOT__we_per_way = + ((0xffff0000U & this->__PVT__data_structures__DOT__we_per_way) + | ((IData)(this->__PVT__data_structures__DOT__way_use_Qual) + ? 0U : (0xffffU & (IData)(this->__PVT__we)))); + this->__PVT__data_structures__DOT__we_per_way = + ((0xffffU & this->__PVT__data_structures__DOT__we_per_way) + | (((IData)(this->__PVT__data_structures__DOT__way_use_Qual) + ? (0xffffU & (IData)(this->__PVT__we)) + : 0U) << 0x10U)); +} + +VL_INLINE_OPT void Vcache_simX_VX_Cache_Bank__pi7::_sequent__TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__3__KET____DOT__bank_structure__8(Vcache_simX__Syms* __restrict vlSymsp) { + VL_DEBUG_IF(VL_DBG_MSGF("+ Vcache_simX_VX_Cache_Bank__pi7::_sequent__TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__3__KET____DOT__bank_structure__8\n"); ); + Vcache_simX* __restrict vlTOPp VL_ATTR_UNUSED = vlSymsp->TOPp; + // Body + this->__PVT__way_to_update = vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT__global_way_to_evict; + this->__Vdlyvset__data_structures__DOT__each_way__BRA__1__KET____DOT__data_structures__DOT__dirty__v0 = 0U; + this->__Vdlyvset__data_structures__DOT__each_way__BRA__1__KET____DOT__data_structures__DOT__dirty__v32 = 0U; + this->__Vdlyvset__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__dirty__v0 = 0U; + this->__Vdlyvset__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__dirty__v32 = 0U; + this->__Vdlyvset__data_structures__DOT__each_way__BRA__1__KET____DOT__data_structures__DOT__valid__v0 = 0U; + this->__Vdlyvset__data_structures__DOT__each_way__BRA__1__KET____DOT__data_structures__DOT__valid__v32 = 0U; + this->__Vdlyvset__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__valid__v0 = 0U; + this->__Vdlyvset__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__valid__v32 = 0U; + this->__Vdlyvset__data_structures__DOT__each_way__BRA__1__KET____DOT__data_structures__DOT__tag__v0 = 0U; + this->__Vdlyvset__data_structures__DOT__each_way__BRA__1__KET____DOT__data_structures__DOT__tag__v32 = 0U; + this->__Vdlyvset__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__tag__v0 = 0U; + this->__Vdlyvset__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__tag__v32 = 0U; + if (vlTOPp->reset) { + this->__PVT__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__ini_ind = 0x20U; + } + if ((1U & (~ (IData)(vlTOPp->reset)))) { + this->__PVT__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__f = 4U; + } + if (vlTOPp->reset) { + this->__PVT__data_structures__DOT__each_way__BRA__1__KET____DOT__data_structures__DOT__ini_ind = 0x20U; + } + if ((1U & (~ (IData)(vlTOPp->reset)))) { + this->__PVT__data_structures__DOT__each_way__BRA__1__KET____DOT__data_structures__DOT__f = 4U; + } + this->__Vdlyvset__data_structures__DOT__each_way__BRA__1__KET____DOT__data_structures__DOT__data__v0 = 0U; + this->__Vdlyvset__data_structures__DOT__each_way__BRA__1__KET____DOT__data_structures__DOT__data__v32 = 0U; + this->__Vdlyvset__data_structures__DOT__each_way__BRA__1__KET____DOT__data_structures__DOT__data__v33 = 0U; + this->__Vdlyvset__data_structures__DOT__each_way__BRA__1__KET____DOT__data_structures__DOT__data__v34 = 0U; + this->__Vdlyvset__data_structures__DOT__each_way__BRA__1__KET____DOT__data_structures__DOT__data__v35 = 0U; + this->__Vdlyvset__data_structures__DOT__each_way__BRA__1__KET____DOT__data_structures__DOT__data__v36 = 0U; + this->__Vdlyvset__data_structures__DOT__each_way__BRA__1__KET____DOT__data_structures__DOT__data__v37 = 0U; + this->__Vdlyvset__data_structures__DOT__each_way__BRA__1__KET____DOT__data_structures__DOT__data__v38 = 0U; + this->__Vdlyvset__data_structures__DOT__each_way__BRA__1__KET____DOT__data_structures__DOT__data__v39 = 0U; + this->__Vdlyvset__data_structures__DOT__each_way__BRA__1__KET____DOT__data_structures__DOT__data__v40 = 0U; + this->__Vdlyvset__data_structures__DOT__each_way__BRA__1__KET____DOT__data_structures__DOT__data__v41 = 0U; + this->__Vdlyvset__data_structures__DOT__each_way__BRA__1__KET____DOT__data_structures__DOT__data__v42 = 0U; + this->__Vdlyvset__data_structures__DOT__each_way__BRA__1__KET____DOT__data_structures__DOT__data__v43 = 0U; + this->__Vdlyvset__data_structures__DOT__each_way__BRA__1__KET____DOT__data_structures__DOT__data__v44 = 0U; + this->__Vdlyvset__data_structures__DOT__each_way__BRA__1__KET____DOT__data_structures__DOT__data__v45 = 0U; + this->__Vdlyvset__data_structures__DOT__each_way__BRA__1__KET____DOT__data_structures__DOT__data__v46 = 0U; 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+ } + if (this->__Vdlyvset__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__data__v42) { + VL_ASSIGNSEL_WIII(8,(IData)(this->__Vdlyvlsb__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__data__v42), + this->__PVT__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__data + [this->__Vdlyvdim0__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__data__v42], this->__Vdlyvval__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__data__v42); + } + if (this->__Vdlyvset__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__data__v43) { + VL_ASSIGNSEL_WIII(8,(IData)(this->__Vdlyvlsb__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__data__v43), + this->__PVT__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__data + [this->__Vdlyvdim0__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__data__v43], this->__Vdlyvval__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__data__v43); + } + if (this->__Vdlyvset__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__data__v44) { + VL_ASSIGNSEL_WIII(8,(IData)(this->__Vdlyvlsb__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__data__v44), + this->__PVT__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__data + [this->__Vdlyvdim0__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__data__v44], this->__Vdlyvval__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__data__v44); + } + if (this->__Vdlyvset__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__data__v45) { + VL_ASSIGNSEL_WIII(8,(IData)(this->__Vdlyvlsb__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__data__v45), + this->__PVT__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__data + [this->__Vdlyvdim0__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__data__v45], this->__Vdlyvval__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__data__v45); + } + if (this->__Vdlyvset__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__data__v46) { + VL_ASSIGNSEL_WIII(8,(IData)(this->__Vdlyvlsb__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__data__v46), + this->__PVT__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__data + [this->__Vdlyvdim0__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__data__v46], this->__Vdlyvval__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__data__v46); + } + if (this->__Vdlyvset__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__data__v47) { + VL_ASSIGNSEL_WIII(8,(IData)(this->__Vdlyvlsb__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__data__v47), + this->__PVT__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__data + [this->__Vdlyvdim0__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__data__v47], this->__Vdlyvval__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__data__v47); + } +} + +VL_INLINE_OPT void Vcache_simX_VX_Cache_Bank__pi7::_combo__TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__3__KET____DOT__bank_structure__12(Vcache_simX__Syms* __restrict vlSymsp) { + VL_DEBUG_IF(VL_DBG_MSGF("+ Vcache_simX_VX_Cache_Bank__pi7::_combo__TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__3__KET____DOT__bank_structure__12\n"); ); + Vcache_simX* __restrict vlTOPp VL_ATTR_UNUSED = vlSymsp->TOPp; + // Variables + WData/*31:0*/ __Vtemp327[4]; + WData/*31:0*/ __Vtemp328[4]; + WData/*31:0*/ __Vtemp329[4]; + WData/*31:0*/ __Vtemp330[4]; + WData/*31:0*/ __Vtemp331[4]; + WData/*31:0*/ __Vtemp332[4]; + WData/*31:0*/ __Vtemp333[4]; + // Body + this->__PVT__write_from_mem = ((2U == (IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT__state)) + & (IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__3__KET____DOT__use_valid_in)); + this->__PVT__access = ((0U == (IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT__state)) + & (IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__3__KET____DOT__use_valid_in)); + this->data_structures__DOT____Vcellout__each_way__BRA__0__KET____DOT__data_structures__dirty_use + = this->__PVT__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__dirty + [(0x1fU & (vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__3__KET____DOT__bank_addr + >> 6U))]; + this->data_structures__DOT____Vcellout__each_way__BRA__1__KET____DOT__data_structures__dirty_use + = this->__PVT__data_structures__DOT__each_way__BRA__1__KET____DOT__data_structures__DOT__dirty + [(0x1fU & (vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__3__KET____DOT__bank_addr + >> 6U))]; + __Vtemp327[0U] = 0U; + __Vtemp327[1U] = 0U; + __Vtemp327[2U] = 0U; + __Vtemp327[3U] = 0U; + __Vtemp328[0U] = 0U; + __Vtemp328[1U] = 0U; + __Vtemp328[2U] = 0U; + __Vtemp328[3U] = 0U; + __Vtemp329[0U] = 0U; + __Vtemp329[1U] = 0U; + __Vtemp329[2U] = 0U; + __Vtemp329[3U] = 0U; + __Vtemp330[0U] = 0U; + __Vtemp330[1U] = 0U; + __Vtemp330[2U] = 0U; + __Vtemp330[3U] = 0U; + __Vtemp331[0U] = 0U; + __Vtemp331[1U] = 0U; + __Vtemp331[2U] = 0U; + __Vtemp331[3U] = 0U; + __Vtemp332[0U] = 0U; + __Vtemp332[1U] = 0U; + __Vtemp332[2U] = 0U; + __Vtemp332[3U] = 0U; + __Vtemp333[0U] = 0U; + __Vtemp333[1U] = 0U; + __Vtemp333[2U] = 0U; + __Vtemp333[3U] = 0U; + this->__PVT__use_write_data = ((0U == (IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__cache_driver_in_mem_write)) + ? ((1U == (3U & vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__3__KET____DOT__bank_addr)) + ? (0xff00U + & (__Vtemp327[ + (3U & + ((IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT__index_per_bank) + >> 6U))] + << 8U)) + : ((2U == (3U + & vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__3__KET____DOT__bank_addr)) + ? (0xff0000U + & (__Vtemp328[ + (3U + & ((IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT__index_per_bank) + >> 6U))] + << 0x10U)) + : ((3U + == + (3U + & vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__3__KET____DOT__bank_addr)) + ? (0xff000000U + & (__Vtemp329[ + (3U + & ((IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT__index_per_bank) + >> 6U))] + << 0x18U)) + : __Vtemp330[ + (3U + & ((IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT__index_per_bank) + >> 6U))]))) + : ((1U == (IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__cache_driver_in_mem_write)) + ? ((2U == (3U + & vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__3__KET____DOT__bank_addr)) + ? (0xffff0000U + & (__Vtemp331[ + (3U + & ((IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT__index_per_bank) + >> 6U))] + << 0x10U)) + : __Vtemp332[ + (3U & ((IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT__index_per_bank) + >> 6U))]) + : __Vtemp333[ + (3U & ((IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT__index_per_bank) + >> 6U))])); + this->__PVT__sb_mask = ((0U == (3U & vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__3__KET____DOT__bank_addr)) + ? 1U : ((1U == (3U & vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__3__KET____DOT__bank_addr)) + ? 2U : ((2U == + (3U + & vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__3__KET____DOT__bank_addr)) + ? 4U + : 8U))); + this->__PVT__data_structures__DOT__data_use_per_way[0U] + = this->__PVT__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__data + [(0x1fU & (vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__3__KET____DOT__bank_addr + >> 6U))][0U]; + this->__PVT__data_structures__DOT__data_use_per_way[1U] + = this->__PVT__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__data + [(0x1fU & (vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__3__KET____DOT__bank_addr + >> 6U))][1U]; + this->__PVT__data_structures__DOT__data_use_per_way[2U] + = this->__PVT__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__data + [(0x1fU & (vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__3__KET____DOT__bank_addr + >> 6U))][2U]; + this->__PVT__data_structures__DOT__data_use_per_way[3U] + = this->__PVT__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__data + [(0x1fU & (vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__3__KET____DOT__bank_addr + >> 6U))][3U]; + this->__PVT__data_structures__DOT__data_use_per_way[4U] + = this->__PVT__data_structures__DOT__each_way__BRA__1__KET____DOT__data_structures__DOT__data + [(0x1fU & (vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__3__KET____DOT__bank_addr + >> 6U))][0U]; + this->__PVT__data_structures__DOT__data_use_per_way[5U] + = this->__PVT__data_structures__DOT__each_way__BRA__1__KET____DOT__data_structures__DOT__data + [(0x1fU & (vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__3__KET____DOT__bank_addr + >> 6U))][1U]; + this->__PVT__data_structures__DOT__data_use_per_way[6U] + = this->__PVT__data_structures__DOT__each_way__BRA__1__KET____DOT__data_structures__DOT__data + [(0x1fU & (vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__3__KET____DOT__bank_addr + >> 6U))][2U]; + this->__PVT__data_structures__DOT__data_use_per_way[7U] + = this->__PVT__data_structures__DOT__each_way__BRA__1__KET____DOT__data_structures__DOT__data + [(0x1fU & (vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__3__KET____DOT__bank_addr + >> 6U))][3U]; + this->__PVT__data_structures__DOT__valid_use_per_way + = ((2U & (IData)(this->__PVT__data_structures__DOT__valid_use_per_way)) + | this->__PVT__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__valid + [(0x1fU & (vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__3__KET____DOT__bank_addr + >> 6U))]); + this->__PVT__data_structures__DOT__valid_use_per_way + = ((1U & (IData)(this->__PVT__data_structures__DOT__valid_use_per_way)) + | (this->__PVT__data_structures__DOT__each_way__BRA__1__KET____DOT__data_structures__DOT__valid + [(0x1fU & (vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__3__KET____DOT__bank_addr + >> 6U))] << 1U)); + this->__PVT__data_structures__DOT__tag_use_per_way + = ((VL_ULL(0x3ffffe00000) & this->__PVT__data_structures__DOT__tag_use_per_way) + | (IData)((IData)(this->__PVT__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__tag + [(0x1fU & (vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__3__KET____DOT__bank_addr + >> 6U))]))); + this->__PVT__data_structures__DOT__tag_use_per_way + = ((VL_ULL(0x1fffff) & this->__PVT__data_structures__DOT__tag_use_per_way) + | ((QData)((IData)(this->__PVT__data_structures__DOT__each_way__BRA__1__KET____DOT__data_structures__DOT__tag + [(0x1fU & (vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__3__KET____DOT__bank_addr + >> 6U))])) + << 0x15U)); + this->__PVT__data_structures__DOT__dirty_use_per_way + = ((2U & (IData)(this->__PVT__data_structures__DOT__dirty_use_per_way)) + | (IData)(this->data_structures__DOT____Vcellout__each_way__BRA__0__KET____DOT__data_structures__dirty_use)); + this->__PVT__data_structures__DOT__dirty_use_per_way + = ((1U & (IData)(this->__PVT__data_structures__DOT__dirty_use_per_way)) + | ((IData)(this->data_structures__DOT____Vcellout__each_way__BRA__1__KET____DOT__data_structures__dirty_use) + << 1U)); + this->__PVT__data_write[0U] = ((IData)(this->__PVT__write_from_mem) + ? vlSymsp->TOP__cache_simX__DOT__VX_dram_req_rsp.i_m_readdata[0xcU] + : this->__PVT__use_write_data); + this->__PVT__data_write[1U] = ((IData)(this->__PVT__write_from_mem) + ? vlSymsp->TOP__cache_simX__DOT__VX_dram_req_rsp.i_m_readdata[0xdU] + : this->__PVT__use_write_data); + this->__PVT__data_write[2U] = ((IData)(this->__PVT__write_from_mem) + ? vlSymsp->TOP__cache_simX__DOT__VX_dram_req_rsp.i_m_readdata[0xeU] + : this->__PVT__use_write_data); + this->__PVT__data_write[3U] = ((IData)(this->__PVT__write_from_mem) + ? vlSymsp->TOP__cache_simX__DOT__VX_dram_req_rsp.i_m_readdata[0xfU] + : this->__PVT__use_write_data); + this->__PVT__data_structures__DOT__invalid_found = 0U; + if ((1U & (~ ((IData)(this->__PVT__data_structures__DOT__valid_use_per_way) + >> 1U)))) { + this->__PVT__data_structures__DOT__invalid_found = 1U; + } + if ((1U & (~ (IData)(this->__PVT__data_structures__DOT__valid_use_per_way)))) { + this->__PVT__data_structures__DOT__invalid_found = 1U; + } + this->__PVT__data_structures__DOT__invalid_index = 0U; + if ((1U & (~ ((IData)(this->__PVT__data_structures__DOT__valid_use_per_way) + >> 1U)))) { + this->__PVT__data_structures__DOT__invalid_index = 1U; + } + if ((1U & (~ (IData)(this->__PVT__data_structures__DOT__valid_use_per_way)))) { + this->__PVT__data_structures__DOT__invalid_index = 0U; + } + this->__PVT__data_structures__DOT__hit_per_way + = ((2U & (IData)(this->__PVT__data_structures__DOT__hit_per_way)) + | (((IData)(this->__PVT__data_structures__DOT__valid_use_per_way) + & ((0x1fffffU & (IData)(this->__PVT__data_structures__DOT__tag_use_per_way)) + == (0x1fffffU & (vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__3__KET____DOT__bank_addr + >> 0xbU)))) ? 1U + : 0U)); + this->__PVT__data_structures__DOT__hit_per_way + = ((1U & (IData)(this->__PVT__data_structures__DOT__hit_per_way)) + | (((((IData)(this->__PVT__data_structures__DOT__valid_use_per_way) + >> 1U) & ((0x1fffffU & (IData)((this->__PVT__data_structures__DOT__tag_use_per_way + >> 0x15U))) + == (0x1fffffU & (vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__3__KET____DOT__bank_addr + >> 0xbU)))) + ? 1U : 0U) << 1U)); + this->__PVT__data_structures__DOT__data_write_per_way[0U] + = this->__PVT__data_write[0U]; + this->__PVT__data_structures__DOT__data_write_per_way[1U] + = this->__PVT__data_write[1U]; + this->__PVT__data_structures__DOT__data_write_per_way[2U] + = this->__PVT__data_write[2U]; + this->__PVT__data_structures__DOT__data_write_per_way[3U] + = this->__PVT__data_write[3U]; + this->__PVT__data_structures__DOT__data_write_per_way[4U] + = this->__PVT__data_write[0U]; + this->__PVT__data_structures__DOT__data_write_per_way[5U] + = this->__PVT__data_write[1U]; + this->__PVT__data_structures__DOT__data_write_per_way[6U] + = this->__PVT__data_write[2U]; + this->__PVT__data_structures__DOT__data_write_per_way[7U] + = this->__PVT__data_write[3U]; + this->__PVT__data_structures__DOT__genblk1__DOT__way_indexing__DOT__found = 0U; + if ((2U & (IData)(this->__PVT__data_structures__DOT__hit_per_way))) { + this->__PVT__data_structures__DOT__genblk1__DOT__way_indexing__DOT__found = 1U; + } + if ((1U & (IData)(this->__PVT__data_structures__DOT__hit_per_way))) { + this->__PVT__data_structures__DOT__genblk1__DOT__way_indexing__DOT__found = 1U; + } + this->__PVT__data_structures__DOT__way_index = 0U; + if ((2U & (IData)(this->__PVT__data_structures__DOT__hit_per_way))) { + this->__PVT__data_structures__DOT__way_index = 1U; + } + if ((1U & (IData)(this->__PVT__data_structures__DOT__hit_per_way))) { + this->__PVT__data_structures__DOT__way_index = 0U; + } + this->__PVT__data_structures__DOT__way_use_Qual + = ((0U != (IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT__state)) + ? (IData)(this->__PVT__way_to_update) : (IData)(this->__PVT__data_structures__DOT__way_index)); + this->__PVT__data_structures__DOT__write_from_mem_per_way + = ((2U & (IData)(this->__PVT__data_structures__DOT__write_from_mem_per_way)) + | ((IData)(this->__PVT__write_from_mem) + & (~ (IData)(this->__PVT__data_structures__DOT__way_use_Qual)))); + this->__PVT__data_structures__DOT__write_from_mem_per_way + = ((1U & (IData)(this->__PVT__data_structures__DOT__write_from_mem_per_way)) + | (((IData)(this->__PVT__write_from_mem) + & (IData)(this->__PVT__data_structures__DOT__way_use_Qual)) + << 1U)); + this->__Vcellout__data_structures__data_use[0U] + = (((0U == (0x1fU & ((IData)(this->__PVT__data_structures__DOT__way_use_Qual) + << 7U))) ? 0U : (this->__PVT__data_structures__DOT__data_use_per_way[ + ((IData)(1U) + + (4U + & ((IData)(this->__PVT__data_structures__DOT__way_use_Qual) + << 2U)))] + << ((IData)(0x20U) + - + (0x1fU + & ((IData)(this->__PVT__data_structures__DOT__way_use_Qual) + << 7U))))) + | (this->__PVT__data_structures__DOT__data_use_per_way[ + (4U & ((IData)(this->__PVT__data_structures__DOT__way_use_Qual) + << 2U))] >> (0x1fU & ((IData)(this->__PVT__data_structures__DOT__way_use_Qual) + << 7U)))); + this->__Vcellout__data_structures__data_use[1U] + = (((0U == (0x1fU & ((IData)(this->__PVT__data_structures__DOT__way_use_Qual) + << 7U))) ? 0U : (this->__PVT__data_structures__DOT__data_use_per_way[ + ((IData)(2U) + + (4U + & ((IData)(this->__PVT__data_structures__DOT__way_use_Qual) + << 2U)))] + << ((IData)(0x20U) + - + (0x1fU + & ((IData)(this->__PVT__data_structures__DOT__way_use_Qual) + << 7U))))) + | (this->__PVT__data_structures__DOT__data_use_per_way[ + ((IData)(1U) + (4U & ((IData)(this->__PVT__data_structures__DOT__way_use_Qual) + << 2U)))] >> (0x1fU + & ((IData)(this->__PVT__data_structures__DOT__way_use_Qual) + << 7U)))); + this->__Vcellout__data_structures__data_use[2U] + = (((0U == (0x1fU & ((IData)(this->__PVT__data_structures__DOT__way_use_Qual) + << 7U))) ? 0U : (this->__PVT__data_structures__DOT__data_use_per_way[ + ((IData)(3U) + + (4U + & ((IData)(this->__PVT__data_structures__DOT__way_use_Qual) + << 2U)))] + << ((IData)(0x20U) + - + (0x1fU + & ((IData)(this->__PVT__data_structures__DOT__way_use_Qual) + << 7U))))) + | (this->__PVT__data_structures__DOT__data_use_per_way[ + ((IData)(2U) + (4U & ((IData)(this->__PVT__data_structures__DOT__way_use_Qual) + << 2U)))] >> (0x1fU + & ((IData)(this->__PVT__data_structures__DOT__way_use_Qual) + << 7U)))); + this->__Vcellout__data_structures__data_use[3U] + = (((0U == (0x1fU & ((IData)(this->__PVT__data_structures__DOT__way_use_Qual) + << 7U))) ? 0U : (this->__PVT__data_structures__DOT__data_use_per_way[ + ((IData)(4U) + + (4U + & ((IData)(this->__PVT__data_structures__DOT__way_use_Qual) + << 2U)))] + << ((IData)(0x20U) + - + (0x1fU + & ((IData)(this->__PVT__data_structures__DOT__way_use_Qual) + << 7U))))) + | (this->__PVT__data_structures__DOT__data_use_per_way[ + ((IData)(3U) + (4U & ((IData)(this->__PVT__data_structures__DOT__way_use_Qual) + << 2U)))] >> (0x1fU + & ((IData)(this->__PVT__data_structures__DOT__way_use_Qual) + << 7U)))); + this->__PVT__valid_use = (1U & ((IData)(this->__PVT__data_structures__DOT__valid_use_per_way) + >> (IData)(this->__PVT__data_structures__DOT__way_use_Qual))); + this->__PVT__tag_use = ((0x29U >= (0x3fU & ((IData)(0x15U) + * (IData)(this->__PVT__data_structures__DOT__way_use_Qual)))) + ? (0x1fffffU & (IData)( + (this->__PVT__data_structures__DOT__tag_use_per_way + >> + (0x3fU + & ((IData)(0x15U) + * (IData)(this->__PVT__data_structures__DOT__way_use_Qual)))))) + : 0U); + this->__PVT__data_unQual = (((0U == (3U & vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__3__KET____DOT__bank_addr)) + | (2U == (IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__cache_driver_in_mem_read))) + ? this->__Vcellout__data_structures__data_use[ + (3U & (vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__3__KET____DOT__bank_addr + >> 4U))] : ( + (1U + == + (3U + & vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__3__KET____DOT__bank_addr)) + ? + (this->__Vcellout__data_structures__data_use[ + (3U + & (vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__3__KET____DOT__bank_addr + >> 4U))] + >> 8U) + : + ((2U + == + (3U + & vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__3__KET____DOT__bank_addr)) + ? + (this->__Vcellout__data_structures__data_use[ + (3U + & (vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__3__KET____DOT__bank_addr + >> 4U))] + >> 0x10U) + : + (this->__Vcellout__data_structures__data_use[ + (3U + & (vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__3__KET____DOT__bank_addr + >> 4U))] + >> 0x18U)))); + this->__PVT__miss = (((this->__PVT__tag_use != + (0x1fffffU & (vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__3__KET____DOT__bank_addr + >> 0xbU))) + & (IData)(this->__PVT__valid_use)) + & (IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__3__KET____DOT__use_valid_in)); + this->__PVT__genblk1__BRA__0__KET____DOT__normal_write + = (((IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__read_or_write) + & ((IData)(this->__PVT__access) & (0U == + (3U + & (vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__3__KET____DOT__bank_addr + >> 4U))))) + & (~ (IData)(this->__PVT__miss))); + this->__PVT__genblk1__BRA__1__KET____DOT__normal_write + = (((IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__read_or_write) + & ((IData)(this->__PVT__access) & (1U == + (3U + & (vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__3__KET____DOT__bank_addr + >> 4U))))) + & (~ (IData)(this->__PVT__miss))); + this->__PVT__genblk1__BRA__2__KET____DOT__normal_write + = (((IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__read_or_write) + & ((IData)(this->__PVT__access) & (2U == + (3U + & (vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__3__KET____DOT__bank_addr + >> 4U))))) + & (~ (IData)(this->__PVT__miss))); + this->__PVT__genblk1__BRA__3__KET____DOT__normal_write + = (((IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__read_or_write) + & ((IData)(this->__PVT__access) & (3U == + (3U + & (vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__3__KET____DOT__bank_addr + >> 4U))))) + & (~ (IData)(this->__PVT__miss))); + this->__PVT__we = ((0xfff0U & (IData)(this->__PVT__we)) + | ((IData)(this->__PVT__write_from_mem) + ? 0xfU : (((IData)(this->__PVT__genblk1__BRA__0__KET____DOT__normal_write) + & (2U == (IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__cache_driver_in_mem_write))) + ? 0xfU : (((IData)(this->__PVT__genblk1__BRA__0__KET____DOT__normal_write) + & (0U + == (IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__cache_driver_in_mem_write))) + ? (IData)(this->__PVT__sb_mask) + : + (((IData)(this->__PVT__genblk1__BRA__0__KET____DOT__normal_write) + & (1U + == (IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__cache_driver_in_mem_write))) + ? + ((0U + == + (3U + & vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__3__KET____DOT__bank_addr)) + ? 3U + : 0xcU) + : 0U))))); + this->__PVT__we = ((0xff0fU & (IData)(this->__PVT__we)) + | (((IData)(this->__PVT__write_from_mem) + ? 0xfU : (((IData)(this->__PVT__genblk1__BRA__1__KET____DOT__normal_write) + & (2U == (IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__cache_driver_in_mem_write))) + ? 0xfU : (((IData)(this->__PVT__genblk1__BRA__1__KET____DOT__normal_write) + & (0U + == (IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__cache_driver_in_mem_write))) + ? (IData)(this->__PVT__sb_mask) + : + (((IData)(this->__PVT__genblk1__BRA__1__KET____DOT__normal_write) + & (1U + == (IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__cache_driver_in_mem_write))) + ? + ((0U + == + (3U + & vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__3__KET____DOT__bank_addr)) + ? 3U + : 0xcU) + : 0U)))) + << 4U)); + this->__PVT__we = ((0xf0ffU & (IData)(this->__PVT__we)) + | (((IData)(this->__PVT__write_from_mem) + ? 0xfU : (((IData)(this->__PVT__genblk1__BRA__2__KET____DOT__normal_write) + & (2U == (IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__cache_driver_in_mem_write))) + ? 0xfU : (((IData)(this->__PVT__genblk1__BRA__2__KET____DOT__normal_write) + & (0U + == (IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__cache_driver_in_mem_write))) + ? (IData)(this->__PVT__sb_mask) + : + (((IData)(this->__PVT__genblk1__BRA__2__KET____DOT__normal_write) + & (1U + == (IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__cache_driver_in_mem_write))) + ? + ((0U + == + (3U + & vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__3__KET____DOT__bank_addr)) + ? 3U + : 0xcU) + : 0U)))) + << 8U)); + this->__PVT__we = ((0xfffU & (IData)(this->__PVT__we)) + | (((IData)(this->__PVT__write_from_mem) + ? 0xfU : (((IData)(this->__PVT__genblk1__BRA__3__KET____DOT__normal_write) + & (2U == (IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__cache_driver_in_mem_write))) + ? 0xfU : (((IData)(this->__PVT__genblk1__BRA__3__KET____DOT__normal_write) + & (0U + == (IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__cache_driver_in_mem_write))) + ? (IData)(this->__PVT__sb_mask) + : + (((IData)(this->__PVT__genblk1__BRA__3__KET____DOT__normal_write) + & (1U + == (IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__cache_driver_in_mem_write))) + ? + ((0U + == + (3U + & vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__3__KET____DOT__bank_addr)) + ? 3U + : 0xcU) + : 0U)))) + << 0xcU)); + this->__PVT__data_structures__DOT__we_per_way = + ((0xffff0000U & this->__PVT__data_structures__DOT__we_per_way) + | ((IData)(this->__PVT__data_structures__DOT__way_use_Qual) + ? 0U : (0xffffU & (IData)(this->__PVT__we)))); + this->__PVT__data_structures__DOT__we_per_way = + ((0xffffU & this->__PVT__data_structures__DOT__we_per_way) + | (((IData)(this->__PVT__data_structures__DOT__way_use_Qual) + ? (0xffffU & (IData)(this->__PVT__we)) + : 0U) << 0x10U)); +} + +void Vcache_simX_VX_Cache_Bank__pi7::_ctor_var_reset() { + VL_DEBUG_IF(VL_DBG_MSGF("+ Vcache_simX_VX_Cache_Bank__pi7::_ctor_var_reset\n"); ); + // Body + rst = VL_RAND_RESET_I(1); + clk = VL_RAND_RESET_I(1); + state = VL_RAND_RESET_I(4); + actual_index = VL_RAND_RESET_I(5); + o_tag = VL_RAND_RESET_I(21); + block_offset = VL_RAND_RESET_I(2); + writedata = VL_RAND_RESET_I(32); + valid_in = VL_RAND_RESET_I(1); + read_or_write = VL_RAND_RESET_I(1); + VL_RAND_RESET_W(128,fetched_writedata); + i_p_mem_read = VL_RAND_RESET_I(3); + i_p_mem_write = VL_RAND_RESET_I(3); + byte_select = VL_RAND_RESET_I(2); + evicted_way = VL_RAND_RESET_I(1); + readdata = VL_RAND_RESET_I(32); + hit = VL_RAND_RESET_I(1); + eviction_wb = VL_RAND_RESET_I(1); + eviction_addr = VL_RAND_RESET_I(32); + VL_RAND_RESET_W(128,data_evicted); + __PVT__tag_use = VL_RAND_RESET_I(21); + __PVT__valid_use = VL_RAND_RESET_I(1); + __PVT__access = VL_RAND_RESET_I(1); + __PVT__write_from_mem = VL_RAND_RESET_I(1); + __PVT__miss = VL_RAND_RESET_I(1); + __PVT__way_to_update = VL_RAND_RESET_I(1); + __PVT__data_unQual = VL_RAND_RESET_I(32); + __PVT__use_write_data = VL_RAND_RESET_I(32); + __PVT__sb_mask = VL_RAND_RESET_I(4); + __PVT__we = VL_RAND_RESET_I(16); + VL_RAND_RESET_W(128,__PVT__data_write); + VL_RAND_RESET_W(128,__Vcellout__data_structures__data_use); + __PVT__genblk1__BRA__0__KET____DOT__normal_write = VL_RAND_RESET_I(1); + __PVT__genblk1__BRA__1__KET____DOT__normal_write = VL_RAND_RESET_I(1); + __PVT__genblk1__BRA__2__KET____DOT__normal_write = VL_RAND_RESET_I(1); + __PVT__genblk1__BRA__3__KET____DOT__normal_write = VL_RAND_RESET_I(1); + __PVT__data_structures__DOT__tag_use_per_way = VL_RAND_RESET_Q(42); + VL_RAND_RESET_W(256,__PVT__data_structures__DOT__data_use_per_way); + __PVT__data_structures__DOT__valid_use_per_way = VL_RAND_RESET_I(2); + __PVT__data_structures__DOT__dirty_use_per_way = VL_RAND_RESET_I(2); + __PVT__data_structures__DOT__hit_per_way = VL_RAND_RESET_I(2); + __PVT__data_structures__DOT__we_per_way = VL_RAND_RESET_I(32); + VL_RAND_RESET_W(256,__PVT__data_structures__DOT__data_write_per_way); + __PVT__data_structures__DOT__write_from_mem_per_way = VL_RAND_RESET_I(2); + __PVT__data_structures__DOT__invalid_found = VL_RAND_RESET_I(1); + __PVT__data_structures__DOT__way_index = VL_RAND_RESET_I(1); + __PVT__data_structures__DOT__invalid_index = VL_RAND_RESET_I(1); + __PVT__data_structures__DOT__way_use_Qual = VL_RAND_RESET_I(1); + data_structures__DOT____Vcellout__each_way__BRA__0__KET____DOT__data_structures__dirty_use = VL_RAND_RESET_I(1); + data_structures__DOT____Vcellout__each_way__BRA__1__KET____DOT__data_structures__dirty_use = VL_RAND_RESET_I(1); + __PVT__data_structures__DOT__genblk1__DOT__way_indexing__DOT__found = VL_RAND_RESET_I(1); + { int __Vi0=0; for (; __Vi0<32; ++__Vi0) { + VL_RAND_RESET_W(128,__PVT__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__data[__Vi0]); + }} + { int __Vi0=0; for (; __Vi0<32; ++__Vi0) { + __PVT__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__tag[__Vi0] = VL_RAND_RESET_I(21); + }} + { int __Vi0=0; for (; __Vi0<32; ++__Vi0) { + __PVT__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__valid[__Vi0] = VL_RAND_RESET_I(1); + }} + { int __Vi0=0; for (; __Vi0<32; ++__Vi0) { + __PVT__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__dirty[__Vi0] = VL_RAND_RESET_I(1); + }} + __PVT__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__f = VL_RAND_RESET_I(32); + __PVT__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__ini_ind = VL_RAND_RESET_I(32); + { int __Vi0=0; for (; __Vi0<32; ++__Vi0) { + VL_RAND_RESET_W(128,__PVT__data_structures__DOT__each_way__BRA__1__KET____DOT__data_structures__DOT__data[__Vi0]); + }} + { int __Vi0=0; for (; __Vi0<32; ++__Vi0) { + __PVT__data_structures__DOT__each_way__BRA__1__KET____DOT__data_structures__DOT__tag[__Vi0] = VL_RAND_RESET_I(21); + }} + { int __Vi0=0; for (; __Vi0<32; ++__Vi0) { + __PVT__data_structures__DOT__each_way__BRA__1__KET____DOT__data_structures__DOT__valid[__Vi0] = VL_RAND_RESET_I(1); + }} + { int __Vi0=0; for (; __Vi0<32; ++__Vi0) { + __PVT__data_structures__DOT__each_way__BRA__1__KET____DOT__data_structures__DOT__dirty[__Vi0] = VL_RAND_RESET_I(1); + }} + __PVT__data_structures__DOT__each_way__BRA__1__KET____DOT__data_structures__DOT__f = VL_RAND_RESET_I(32); + __PVT__data_structures__DOT__each_way__BRA__1__KET____DOT__data_structures__DOT__ini_ind = VL_RAND_RESET_I(32); + __Vdlyvset__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__valid__v0 = 0; + __Vdlyvdim0__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__valid__v32 = 0; + __Vdlyvset__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__valid__v32 = 0; + __Vdlyvset__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__tag__v0 = 0; + __Vdlyvdim0__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__tag__v32 = 0; + __Vdlyvval__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__tag__v32 = VL_RAND_RESET_I(21); + __Vdlyvset__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__tag__v32 = 0; + __Vdlyvset__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__data__v0 = 0; + __Vdlyvdim0__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__data__v32 = 0; + __Vdlyvlsb__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__data__v32 = 0; + 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Verilated -*- C++ -*- +// DESCRIPTION: Verilator output: Design internal header +// See Vcache_simX.h for the primary calling header + +#ifndef _Vcache_simX_VX_Cache_Bank__pi7_H_ +#define _Vcache_simX_VX_Cache_Bank__pi7_H_ + +#include "verilated.h" + +class Vcache_simX__Syms; +class VerilatedVcd; + +//---------- + +VL_MODULE(Vcache_simX_VX_Cache_Bank__pi7) { + public: + + // PORTS + VL_IN8(rst,0,0); + VL_IN8(clk,0,0); + VL_IN8(state,3,0); + VL_IN8(actual_index,4,0); + VL_IN8(block_offset,1,0); + VL_IN8(valid_in,0,0); + VL_IN8(read_or_write,0,0); + VL_IN8(i_p_mem_read,2,0); + VL_IN8(i_p_mem_write,2,0); + VL_IN8(byte_select,1,0); + VL_IN8(evicted_way,0,0); + VL_OUT8(hit,0,0); + VL_OUT8(eviction_wb,0,0); + VL_IN(o_tag,20,0); + VL_IN(writedata,31,0); + VL_INW(fetched_writedata,127,0,4); + VL_OUT(readdata,31,0); + VL_OUT(eviction_addr,31,0); + VL_OUTW(data_evicted,127,0,4); + + // LOCAL SIGNALS + CData/*0:0*/ __PVT__valid_use; + CData/*0:0*/ __PVT__access; + CData/*0:0*/ __PVT__write_from_mem; + CData/*0:0*/ __PVT__miss; + CData/*0:0*/ __PVT__way_to_update; + CData/*3:0*/ __PVT__sb_mask; + SData/*3:0*/ __PVT__we; + CData/*0:0*/ __PVT__genblk1__BRA__0__KET____DOT__normal_write; + CData/*0:0*/ __PVT__genblk1__BRA__1__KET____DOT__normal_write; + CData/*0:0*/ __PVT__genblk1__BRA__2__KET____DOT__normal_write; + CData/*0:0*/ __PVT__genblk1__BRA__3__KET____DOT__normal_write; + CData/*1:0*/ __PVT__data_structures__DOT__valid_use_per_way; + CData/*1:0*/ __PVT__data_structures__DOT__dirty_use_per_way; + CData/*1:0*/ __PVT__data_structures__DOT__hit_per_way; + IData/*3:0*/ __PVT__data_structures__DOT__we_per_way; + CData/*1:0*/ __PVT__data_structures__DOT__write_from_mem_per_way; + CData/*0:0*/ __PVT__data_structures__DOT__invalid_found; + CData/*0:0*/ __PVT__data_structures__DOT__way_index; + CData/*0:0*/ __PVT__data_structures__DOT__invalid_index; + CData/*0:0*/ __PVT__data_structures__DOT__way_use_Qual; + CData/*0:0*/ __PVT__data_structures__DOT__genblk1__DOT__way_indexing__DOT__found; + IData/*20:0*/ __PVT__tag_use; + IData/*31:0*/ __PVT__data_unQual; + IData/*31:0*/ __PVT__use_write_data; + WData/*31:0*/ __PVT__data_write[4]; + QData/*20:0*/ __PVT__data_structures__DOT__tag_use_per_way; + WData/*31:0*/ __PVT__data_structures__DOT__data_use_per_way[8]; + WData/*31:0*/ __PVT__data_structures__DOT__data_write_per_way[8]; + IData/*31:0*/ __PVT__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__f; + IData/*31:0*/ __PVT__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__ini_ind; + IData/*31:0*/ __PVT__data_structures__DOT__each_way__BRA__1__KET____DOT__data_structures__DOT__f; + IData/*31:0*/ __PVT__data_structures__DOT__each_way__BRA__1__KET____DOT__data_structures__DOT__ini_ind; + WData/*7:0*/ __PVT__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__data[32][4]; + IData/*20:0*/ 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__Vdlyvdim0__data_structures__DOT__each_way__BRA__1__KET____DOT__data_structures__DOT__data__v41; + CData/*6:0*/ __Vdlyvlsb__data_structures__DOT__each_way__BRA__1__KET____DOT__data_structures__DOT__data__v41; + CData/*7:0*/ __Vdlyvval__data_structures__DOT__each_way__BRA__1__KET____DOT__data_structures__DOT__data__v41; + CData/*0:0*/ __Vdlyvset__data_structures__DOT__each_way__BRA__1__KET____DOT__data_structures__DOT__data__v41; + CData/*4:0*/ __Vdlyvdim0__data_structures__DOT__each_way__BRA__1__KET____DOT__data_structures__DOT__data__v42; + CData/*6:0*/ __Vdlyvlsb__data_structures__DOT__each_way__BRA__1__KET____DOT__data_structures__DOT__data__v42; + CData/*7:0*/ __Vdlyvval__data_structures__DOT__each_way__BRA__1__KET____DOT__data_structures__DOT__data__v42; + CData/*0:0*/ __Vdlyvset__data_structures__DOT__each_way__BRA__1__KET____DOT__data_structures__DOT__data__v42; + }; + struct { + CData/*4:0*/ __Vdlyvdim0__data_structures__DOT__each_way__BRA__1__KET____DOT__data_structures__DOT__data__v43; + CData/*6:0*/ __Vdlyvlsb__data_structures__DOT__each_way__BRA__1__KET____DOT__data_structures__DOT__data__v43; + CData/*7:0*/ __Vdlyvval__data_structures__DOT__each_way__BRA__1__KET____DOT__data_structures__DOT__data__v43; + CData/*0:0*/ __Vdlyvset__data_structures__DOT__each_way__BRA__1__KET____DOT__data_structures__DOT__data__v43; + CData/*4:0*/ __Vdlyvdim0__data_structures__DOT__each_way__BRA__1__KET____DOT__data_structures__DOT__data__v44; + CData/*6:0*/ __Vdlyvlsb__data_structures__DOT__each_way__BRA__1__KET____DOT__data_structures__DOT__data__v44; + CData/*7:0*/ __Vdlyvval__data_structures__DOT__each_way__BRA__1__KET____DOT__data_structures__DOT__data__v44; + CData/*0:0*/ __Vdlyvset__data_structures__DOT__each_way__BRA__1__KET____DOT__data_structures__DOT__data__v44; + CData/*4:0*/ __Vdlyvdim0__data_structures__DOT__each_way__BRA__1__KET____DOT__data_structures__DOT__data__v45; + CData/*6:0*/ __Vdlyvlsb__data_structures__DOT__each_way__BRA__1__KET____DOT__data_structures__DOT__data__v45; + CData/*7:0*/ __Vdlyvval__data_structures__DOT__each_way__BRA__1__KET____DOT__data_structures__DOT__data__v45; + CData/*0:0*/ __Vdlyvset__data_structures__DOT__each_way__BRA__1__KET____DOT__data_structures__DOT__data__v45; + CData/*4:0*/ __Vdlyvdim0__data_structures__DOT__each_way__BRA__1__KET____DOT__data_structures__DOT__data__v46; + CData/*6:0*/ __Vdlyvlsb__data_structures__DOT__each_way__BRA__1__KET____DOT__data_structures__DOT__data__v46; + CData/*7:0*/ __Vdlyvval__data_structures__DOT__each_way__BRA__1__KET____DOT__data_structures__DOT__data__v46; + CData/*0:0*/ __Vdlyvset__data_structures__DOT__each_way__BRA__1__KET____DOT__data_structures__DOT__data__v46; + CData/*4:0*/ __Vdlyvdim0__data_structures__DOT__each_way__BRA__1__KET____DOT__data_structures__DOT__data__v47; + CData/*6:0*/ __Vdlyvlsb__data_structures__DOT__each_way__BRA__1__KET____DOT__data_structures__DOT__data__v47; + CData/*7:0*/ __Vdlyvval__data_structures__DOT__each_way__BRA__1__KET____DOT__data_structures__DOT__data__v47; + CData/*0:0*/ __Vdlyvset__data_structures__DOT__each_way__BRA__1__KET____DOT__data_structures__DOT__data__v47; + CData/*0:0*/ __Vdlyvset__data_structures__DOT__each_way__BRA__1__KET____DOT__data_structures__DOT__dirty__v0; + CData/*4:0*/ __Vdlyvdim0__data_structures__DOT__each_way__BRA__1__KET____DOT__data_structures__DOT__dirty__v32; + CData/*0:0*/ __Vdlyvval__data_structures__DOT__each_way__BRA__1__KET____DOT__data_structures__DOT__dirty__v32; + CData/*0:0*/ __Vdlyvset__data_structures__DOT__each_way__BRA__1__KET____DOT__data_structures__DOT__dirty__v32; + WData/*31:0*/ __Vcellout__data_structures__data_use[4]; + IData/*20:0*/ __Vdlyvval__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__tag__v32; + IData/*20:0*/ __Vdlyvval__data_structures__DOT__each_way__BRA__1__KET____DOT__data_structures__DOT__tag__v32; + }; + + // INTERNAL VARIABLES + private: + Vcache_simX__Syms* __VlSymsp; // Symbol table + public: + + // PARAMETERS + + // CONSTRUCTORS + private: + VL_UNCOPYABLE(Vcache_simX_VX_Cache_Bank__pi7); ///< Copying not allowed + public: + Vcache_simX_VX_Cache_Bank__pi7(const char* name = "TOP"); + ~Vcache_simX_VX_Cache_Bank__pi7(); + + // API METHODS + + // INTERNAL METHODS + void __Vconfigure(Vcache_simX__Syms* symsp, bool first); + void _combo__TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__9(Vcache_simX__Syms* __restrict vlSymsp); + void _combo__TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__1__KET____DOT__bank_structure__10(Vcache_simX__Syms* __restrict vlSymsp); + void _combo__TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__2__KET____DOT__bank_structure__11(Vcache_simX__Syms* __restrict vlSymsp); + void _combo__TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__3__KET____DOT__bank_structure__12(Vcache_simX__Syms* __restrict vlSymsp); + private: + void _ctor_var_reset() VL_ATTR_COLD; + public: + void _sequent__TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__5(Vcache_simX__Syms* __restrict vlSymsp); + void _sequent__TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__1__KET____DOT__bank_structure__6(Vcache_simX__Syms* __restrict vlSymsp); + void _sequent__TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__2__KET____DOT__bank_structure__7(Vcache_simX__Syms* __restrict vlSymsp); + void _sequent__TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__3__KET____DOT__bank_structure__8(Vcache_simX__Syms* __restrict vlSymsp); + void _settle__TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__1(Vcache_simX__Syms* __restrict vlSymsp) VL_ATTR_COLD; + void _settle__TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__1__KET____DOT__bank_structure__2(Vcache_simX__Syms* __restrict vlSymsp) VL_ATTR_COLD; + void _settle__TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__2__KET____DOT__bank_structure__3(Vcache_simX__Syms* __restrict vlSymsp) VL_ATTR_COLD; + void _settle__TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__3__KET____DOT__bank_structure__4(Vcache_simX__Syms* __restrict vlSymsp) VL_ATTR_COLD; + static void traceInit(VerilatedVcd* vcdp, void* userthis, uint32_t code); + static void traceFull(VerilatedVcd* vcdp, void* userthis, uint32_t code); + static void traceChg(VerilatedVcd* vcdp, void* userthis, uint32_t code); +} VL_ATTR_ALIGNED(128); + +#endif // guard diff --git a/simX/obj_dir/Vcache_simX_VX_dcache_request_inter.cpp b/simX/obj_dir/Vcache_simX_VX_dcache_request_inter.cpp new file mode 100644 index 00000000..a3e3ff34 --- /dev/null +++ b/simX/obj_dir/Vcache_simX_VX_dcache_request_inter.cpp @@ -0,0 +1,37 @@ +// Verilated -*- C++ -*- +// DESCRIPTION: Verilator output: Design implementation internals +// See Vcache_simX.h for the primary calling header + +#include "Vcache_simX_VX_dcache_request_inter.h" +#include "Vcache_simX__Syms.h" + + +//-------------------- +// STATIC VARIABLES + + +//-------------------- + +VL_CTOR_IMP(Vcache_simX_VX_dcache_request_inter) { + // Reset internal values + // Reset structure values + _ctor_var_reset(); +} + +void Vcache_simX_VX_dcache_request_inter::__Vconfigure(Vcache_simX__Syms* vlSymsp, bool first) { + if (0 && first) {} // Prevent unused + this->__VlSymsp = vlSymsp; +} + +Vcache_simX_VX_dcache_request_inter::~Vcache_simX_VX_dcache_request_inter() { +} + +//-------------------- +// Internal Methods + +void Vcache_simX_VX_dcache_request_inter::_ctor_var_reset() { + VL_DEBUG_IF(VL_DBG_MSGF("+ Vcache_simX_VX_dcache_request_inter::_ctor_var_reset\n"); ); + // Body + VL_RAND_RESET_W(128,out_cache_driver_in_address); + out_cache_driver_in_valid = VL_RAND_RESET_I(4); +} diff --git a/simX/obj_dir/Vcache_simX_VX_dcache_request_inter.h b/simX/obj_dir/Vcache_simX_VX_dcache_request_inter.h new file mode 100644 index 00000000..dae363d3 --- /dev/null +++ b/simX/obj_dir/Vcache_simX_VX_dcache_request_inter.h @@ -0,0 +1,52 @@ +// Verilated -*- C++ -*- +// DESCRIPTION: Verilator output: Design internal header +// See Vcache_simX.h for the primary calling header + +#ifndef _Vcache_simX_VX_dcache_request_inter_H_ +#define _Vcache_simX_VX_dcache_request_inter_H_ + +#include "verilated.h" + +class Vcache_simX__Syms; +class VerilatedVcd; + +//---------- + +VL_MODULE(Vcache_simX_VX_dcache_request_inter) { + public: + + // PORTS + + // LOCAL SIGNALS + CData/*3:0*/ out_cache_driver_in_valid; + WData/*31:0*/ out_cache_driver_in_address[4]; + + // LOCAL VARIABLES + + // INTERNAL VARIABLES + private: + Vcache_simX__Syms* __VlSymsp; // Symbol table + public: + + // PARAMETERS + + // CONSTRUCTORS + private: + VL_UNCOPYABLE(Vcache_simX_VX_dcache_request_inter); ///< Copying not allowed + public: + Vcache_simX_VX_dcache_request_inter(const char* name = "TOP"); + ~Vcache_simX_VX_dcache_request_inter(); + + // API METHODS + + // INTERNAL METHODS + void __Vconfigure(Vcache_simX__Syms* symsp, bool first); + private: + void _ctor_var_reset() VL_ATTR_COLD; + public: + static void traceInit(VerilatedVcd* vcdp, void* userthis, uint32_t code); + static void traceFull(VerilatedVcd* vcdp, void* userthis, uint32_t code); + static void traceChg(VerilatedVcd* vcdp, void* userthis, uint32_t code); +} VL_ATTR_ALIGNED(128); + +#endif // guard diff --git a/simX/obj_dir/Vcache_simX_VX_dram_req_rsp_inter__N1_NB4.cpp b/simX/obj_dir/Vcache_simX_VX_dram_req_rsp_inter__N1_NB4.cpp new file mode 100644 index 00000000..bac834de --- /dev/null +++ b/simX/obj_dir/Vcache_simX_VX_dram_req_rsp_inter__N1_NB4.cpp @@ -0,0 +1,36 @@ +// Verilated -*- C++ -*- +// DESCRIPTION: Verilator output: Design implementation internals +// See Vcache_simX.h for the primary calling header + +#include "Vcache_simX_VX_dram_req_rsp_inter__N1_NB4.h" +#include "Vcache_simX__Syms.h" + + +//-------------------- +// STATIC VARIABLES + + +//-------------------- + +VL_CTOR_IMP(Vcache_simX_VX_dram_req_rsp_inter__N1_NB4) { + // Reset internal values + // Reset structure values + _ctor_var_reset(); +} + +void Vcache_simX_VX_dram_req_rsp_inter__N1_NB4::__Vconfigure(Vcache_simX__Syms* vlSymsp, bool first) { + if (0 && first) {} // Prevent unused + this->__VlSymsp = vlSymsp; +} + +Vcache_simX_VX_dram_req_rsp_inter__N1_NB4::~Vcache_simX_VX_dram_req_rsp_inter__N1_NB4() { +} + +//-------------------- +// Internal Methods + +void Vcache_simX_VX_dram_req_rsp_inter__N1_NB4::_ctor_var_reset() { + VL_DEBUG_IF(VL_DBG_MSGF("+ Vcache_simX_VX_dram_req_rsp_inter__N1_NB4::_ctor_var_reset\n"); ); + // Body + VL_RAND_RESET_W(128,i_m_readdata); +} diff --git a/simX/obj_dir/Vcache_simX_VX_dram_req_rsp_inter__N1_NB4.h b/simX/obj_dir/Vcache_simX_VX_dram_req_rsp_inter__N1_NB4.h new file mode 100644 index 00000000..98144512 --- /dev/null +++ b/simX/obj_dir/Vcache_simX_VX_dram_req_rsp_inter__N1_NB4.h @@ -0,0 +1,51 @@ +// Verilated -*- C++ -*- +// DESCRIPTION: Verilator output: Design internal header +// See Vcache_simX.h for the primary calling header + +#ifndef _Vcache_simX_VX_dram_req_rsp_inter__N1_NB4_H_ +#define _Vcache_simX_VX_dram_req_rsp_inter__N1_NB4_H_ + +#include "verilated.h" + +class Vcache_simX__Syms; +class VerilatedVcd; + +//---------- + +VL_MODULE(Vcache_simX_VX_dram_req_rsp_inter__N1_NB4) { + public: + + // PORTS + + // LOCAL SIGNALS + WData/*31:0*/ i_m_readdata[4]; + + // LOCAL VARIABLES + + // INTERNAL VARIABLES + private: + Vcache_simX__Syms* __VlSymsp; // Symbol table + public: + + // PARAMETERS + + // CONSTRUCTORS + private: + VL_UNCOPYABLE(Vcache_simX_VX_dram_req_rsp_inter__N1_NB4); ///< Copying not allowed + public: + Vcache_simX_VX_dram_req_rsp_inter__N1_NB4(const char* name = "TOP"); + ~Vcache_simX_VX_dram_req_rsp_inter__N1_NB4(); + + // API METHODS + + // INTERNAL METHODS + void __Vconfigure(Vcache_simX__Syms* symsp, bool first); + private: + void _ctor_var_reset() VL_ATTR_COLD; + public: + static void traceInit(VerilatedVcd* vcdp, void* userthis, uint32_t code); + static void traceFull(VerilatedVcd* vcdp, void* userthis, uint32_t code); + static void traceChg(VerilatedVcd* vcdp, void* userthis, uint32_t code); +} VL_ATTR_ALIGNED(128); + +#endif // guard diff --git a/simX/obj_dir/Vcache_simX_VX_dram_req_rsp_inter__N4_NB4.cpp b/simX/obj_dir/Vcache_simX_VX_dram_req_rsp_inter__N4_NB4.cpp new file mode 100644 index 00000000..7fc02687 --- /dev/null +++ b/simX/obj_dir/Vcache_simX_VX_dram_req_rsp_inter__N4_NB4.cpp @@ -0,0 +1,36 @@ +// Verilated -*- C++ -*- +// DESCRIPTION: Verilator output: Design implementation internals +// See Vcache_simX.h for the primary calling header + +#include "Vcache_simX_VX_dram_req_rsp_inter__N4_NB4.h" +#include "Vcache_simX__Syms.h" + + +//-------------------- +// STATIC VARIABLES + + +//-------------------- + +VL_CTOR_IMP(Vcache_simX_VX_dram_req_rsp_inter__N4_NB4) { + // Reset internal values + // Reset structure values + _ctor_var_reset(); +} + +void Vcache_simX_VX_dram_req_rsp_inter__N4_NB4::__Vconfigure(Vcache_simX__Syms* vlSymsp, bool first) { + if (0 && first) {} // Prevent unused + this->__VlSymsp = vlSymsp; +} + +Vcache_simX_VX_dram_req_rsp_inter__N4_NB4::~Vcache_simX_VX_dram_req_rsp_inter__N4_NB4() { +} + +//-------------------- +// Internal Methods + +void Vcache_simX_VX_dram_req_rsp_inter__N4_NB4::_ctor_var_reset() { + VL_DEBUG_IF(VL_DBG_MSGF("+ Vcache_simX_VX_dram_req_rsp_inter__N4_NB4::_ctor_var_reset\n"); ); + // Body + VL_RAND_RESET_W(512,i_m_readdata); +} diff --git a/simX/obj_dir/Vcache_simX_VX_dram_req_rsp_inter__N4_NB4.h b/simX/obj_dir/Vcache_simX_VX_dram_req_rsp_inter__N4_NB4.h new file mode 100644 index 00000000..b016fb4a --- /dev/null +++ b/simX/obj_dir/Vcache_simX_VX_dram_req_rsp_inter__N4_NB4.h @@ -0,0 +1,51 @@ +// Verilated -*- C++ -*- +// DESCRIPTION: Verilator output: Design internal header +// See Vcache_simX.h for the primary calling header + +#ifndef _Vcache_simX_VX_dram_req_rsp_inter__N4_NB4_H_ +#define _Vcache_simX_VX_dram_req_rsp_inter__N4_NB4_H_ + +#include "verilated.h" + +class Vcache_simX__Syms; +class VerilatedVcd; + +//---------- + +VL_MODULE(Vcache_simX_VX_dram_req_rsp_inter__N4_NB4) { + public: + + // PORTS + + // LOCAL SIGNALS + WData/*31:0*/ i_m_readdata[16]; + + // LOCAL VARIABLES + + // INTERNAL VARIABLES + private: + Vcache_simX__Syms* __VlSymsp; // Symbol table + public: + + // PARAMETERS + + // CONSTRUCTORS + private: + VL_UNCOPYABLE(Vcache_simX_VX_dram_req_rsp_inter__N4_NB4); ///< Copying not allowed + public: + Vcache_simX_VX_dram_req_rsp_inter__N4_NB4(const char* name = "TOP"); + ~Vcache_simX_VX_dram_req_rsp_inter__N4_NB4(); + + // API METHODS + + // INTERNAL METHODS + void __Vconfigure(Vcache_simX__Syms* symsp, bool first); + private: + void _ctor_var_reset() VL_ATTR_COLD; + public: + static void traceInit(VerilatedVcd* vcdp, void* userthis, uint32_t code); + static void traceFull(VerilatedVcd* vcdp, void* userthis, uint32_t code); + static void traceChg(VerilatedVcd* vcdp, void* userthis, uint32_t code); +} VL_ATTR_ALIGNED(128); + +#endif // guard diff --git a/simX/obj_dir/Vcache_simX__ALL.a b/simX/obj_dir/Vcache_simX__ALL.a new file mode 100644 index 00000000..bca48c47 Binary files /dev/null and b/simX/obj_dir/Vcache_simX__ALL.a differ diff --git a/simX/obj_dir/Vcache_simX__ALLcls.cpp b/simX/obj_dir/Vcache_simX__ALLcls.cpp new file mode 100644 index 00000000..6dd6dcbe --- /dev/null +++ b/simX/obj_dir/Vcache_simX__ALLcls.cpp @@ -0,0 +1,7 @@ +// DESCRIPTION: Generated by verilator_includer via makefile +#define VL_INCLUDE_OPT include +#include "Vcache_simX.cpp" +#include "Vcache_simX_VX_dram_req_rsp_inter__N4_NB4.cpp" +#include "Vcache_simX_VX_dram_req_rsp_inter__N1_NB4.cpp" +#include "Vcache_simX_VX_dcache_request_inter.cpp" +#include "Vcache_simX_VX_Cache_Bank__pi7.cpp" diff --git a/simX/obj_dir/Vcache_simX__ALLcls.d b/simX/obj_dir/Vcache_simX__ALLcls.d new file mode 100644 index 00000000..6608fb1c --- /dev/null +++ b/simX/obj_dir/Vcache_simX__ALLcls.d @@ -0,0 +1,10 @@ +Vcache_simX__ALLcls.o: Vcache_simX__ALLcls.cpp Vcache_simX.cpp \ + Vcache_simX.h /usr/local/share/verilator/include/verilated.h \ + /usr/local/share/verilator/include/verilatedos.h Vcache_simX__Syms.h \ + Vcache_simX_VX_dram_req_rsp_inter__N4_NB4.h \ + Vcache_simX_VX_dram_req_rsp_inter__N1_NB4.h \ + Vcache_simX_VX_dcache_request_inter.h Vcache_simX_VX_Cache_Bank__pi7.h \ + Vcache_simX_VX_dram_req_rsp_inter__N4_NB4.cpp \ + Vcache_simX_VX_dram_req_rsp_inter__N1_NB4.cpp \ + Vcache_simX_VX_dcache_request_inter.cpp \ + Vcache_simX_VX_Cache_Bank__pi7.cpp diff --git a/simX/obj_dir/Vcache_simX__ALLcls.o b/simX/obj_dir/Vcache_simX__ALLcls.o new file mode 100644 index 00000000..e1dd586b Binary files /dev/null and b/simX/obj_dir/Vcache_simX__ALLcls.o differ diff --git a/simX/obj_dir/Vcache_simX__ALLsup.cpp b/simX/obj_dir/Vcache_simX__ALLsup.cpp new file mode 100644 index 00000000..e6a8008f --- /dev/null +++ b/simX/obj_dir/Vcache_simX__ALLsup.cpp @@ -0,0 +1,5 @@ +// DESCRIPTION: Generated by verilator_includer via makefile +#define VL_INCLUDE_OPT include +#include "Vcache_simX__Trace.cpp" +#include "Vcache_simX__Syms.cpp" +#include "Vcache_simX__Trace__Slow.cpp" diff --git a/simX/obj_dir/Vcache_simX__ALLsup.d b/simX/obj_dir/Vcache_simX__ALLsup.d new file mode 100644 index 00000000..030b051d --- /dev/null +++ b/simX/obj_dir/Vcache_simX__ALLsup.d @@ -0,0 +1,9 @@ +Vcache_simX__ALLsup.o: Vcache_simX__ALLsup.cpp Vcache_simX__Trace.cpp \ + /usr/local/share/verilator/include/verilated_vcd_c.h \ + /usr/local/share/verilator/include/verilatedos.h \ + /usr/local/share/verilator/include/verilated.h Vcache_simX__Syms.h \ + /usr/local/share/verilator/include/verilated.h Vcache_simX.h \ + Vcache_simX_VX_dram_req_rsp_inter__N4_NB4.h \ + Vcache_simX_VX_dram_req_rsp_inter__N1_NB4.h \ + Vcache_simX_VX_dcache_request_inter.h Vcache_simX_VX_Cache_Bank__pi7.h \ + Vcache_simX__Syms.cpp Vcache_simX__Trace__Slow.cpp diff --git a/simX/obj_dir/Vcache_simX__ALLsup.o b/simX/obj_dir/Vcache_simX__ALLsup.o new file mode 100644 index 00000000..59c015c9 Binary files /dev/null and b/simX/obj_dir/Vcache_simX__ALLsup.o differ diff --git a/simX/obj_dir/Vcache_simX__Syms.cpp b/simX/obj_dir/Vcache_simX__Syms.cpp new file mode 100644 index 00000000..470d538c --- /dev/null +++ b/simX/obj_dir/Vcache_simX__Syms.cpp @@ -0,0 +1,47 @@ +// Verilated -*- C++ -*- +// DESCRIPTION: Verilator output: Symbol table implementation internals + +#include "Vcache_simX__Syms.h" +#include "Vcache_simX.h" +#include "Vcache_simX_VX_dram_req_rsp_inter__N4_NB4.h" +#include "Vcache_simX_VX_dram_req_rsp_inter__N1_NB4.h" +#include "Vcache_simX_VX_dcache_request_inter.h" +#include "Vcache_simX_VX_Cache_Bank__pi7.h" + + + +// FUNCTIONS +Vcache_simX__Syms::Vcache_simX__Syms(Vcache_simX* topp, const char* namep) + // Setup locals + : __Vm_namep(namep) + , __Vm_activity(false) + , __Vm_didInit(false) + // Setup submodule names + , TOP__cache_simX__DOT__VX_dcache_req(Verilated::catName(topp->name(),"cache_simX.VX_dcache_req")) + , TOP__cache_simX__DOT__VX_dram_req_rsp(Verilated::catName(topp->name(),"cache_simX.VX_dram_req_rsp")) + , TOP__cache_simX__DOT__VX_dram_req_rsp_icache(Verilated::catName(topp->name(),"cache_simX.VX_dram_req_rsp_icache")) + , TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__0__KET____DOT__bank_structure(Verilated::catName(topp->name(),"cache_simX.dmem_controller.dcache.genblk3[0].bank_structure")) + , TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__1__KET____DOT__bank_structure(Verilated::catName(topp->name(),"cache_simX.dmem_controller.dcache.genblk3[1].bank_structure")) + , TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__2__KET____DOT__bank_structure(Verilated::catName(topp->name(),"cache_simX.dmem_controller.dcache.genblk3[2].bank_structure")) + , TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__3__KET____DOT__bank_structure(Verilated::catName(topp->name(),"cache_simX.dmem_controller.dcache.genblk3[3].bank_structure")) +{ + // Pointer to top level + TOPp = topp; + // Setup each module's pointers to their submodules + TOPp->__PVT__cache_simX__DOT__VX_dcache_req = &TOP__cache_simX__DOT__VX_dcache_req; + TOPp->__PVT__cache_simX__DOT__VX_dram_req_rsp = &TOP__cache_simX__DOT__VX_dram_req_rsp; + TOPp->__PVT__cache_simX__DOT__VX_dram_req_rsp_icache = &TOP__cache_simX__DOT__VX_dram_req_rsp_icache; + TOPp->__PVT__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__0__KET____DOT__bank_structure = &TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__0__KET____DOT__bank_structure; + TOPp->__PVT__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__1__KET____DOT__bank_structure = &TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__1__KET____DOT__bank_structure; + TOPp->__PVT__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__2__KET____DOT__bank_structure = &TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__2__KET____DOT__bank_structure; + TOPp->__PVT__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__3__KET____DOT__bank_structure = &TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__3__KET____DOT__bank_structure; + // Setup each module's pointer back to symbol table (for public functions) + TOPp->__Vconfigure(this, true); + TOP__cache_simX__DOT__VX_dcache_req.__Vconfigure(this, true); + TOP__cache_simX__DOT__VX_dram_req_rsp.__Vconfigure(this, true); + TOP__cache_simX__DOT__VX_dram_req_rsp_icache.__Vconfigure(this, true); + TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__0__KET____DOT__bank_structure.__Vconfigure(this, true); + TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__1__KET____DOT__bank_structure.__Vconfigure(this, false); + TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__2__KET____DOT__bank_structure.__Vconfigure(this, false); + TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__3__KET____DOT__bank_structure.__Vconfigure(this, false); +} diff --git a/simX/obj_dir/Vcache_simX__Syms.h b/simX/obj_dir/Vcache_simX__Syms.h new file mode 100644 index 00000000..512e8596 --- /dev/null +++ b/simX/obj_dir/Vcache_simX__Syms.h @@ -0,0 +1,48 @@ +// Verilated -*- C++ -*- +// DESCRIPTION: Verilator output: Symbol table internal header +// +// Internal details; most calling programs do not need this header, +// unless using verilator public meta comments. + +#ifndef _Vcache_simX__Syms_H_ +#define _Vcache_simX__Syms_H_ + +#include "verilated.h" + +// INCLUDE MODULE CLASSES +#include "Vcache_simX.h" +#include "Vcache_simX_VX_dram_req_rsp_inter__N4_NB4.h" +#include "Vcache_simX_VX_dram_req_rsp_inter__N1_NB4.h" +#include "Vcache_simX_VX_dcache_request_inter.h" +#include "Vcache_simX_VX_Cache_Bank__pi7.h" + +// SYMS CLASS +class Vcache_simX__Syms : public VerilatedSyms { + public: + + // LOCAL STATE + const char* __Vm_namep; + bool __Vm_activity; ///< Used by trace routines to determine change occurred + bool __Vm_didInit; + + // SUBCELL STATE + Vcache_simX* TOPp; + Vcache_simX_VX_dcache_request_inter TOP__cache_simX__DOT__VX_dcache_req; + Vcache_simX_VX_dram_req_rsp_inter__N4_NB4 TOP__cache_simX__DOT__VX_dram_req_rsp; + Vcache_simX_VX_dram_req_rsp_inter__N1_NB4 TOP__cache_simX__DOT__VX_dram_req_rsp_icache; + Vcache_simX_VX_Cache_Bank__pi7 TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__0__KET____DOT__bank_structure; + Vcache_simX_VX_Cache_Bank__pi7 TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__1__KET____DOT__bank_structure; + Vcache_simX_VX_Cache_Bank__pi7 TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__2__KET____DOT__bank_structure; + Vcache_simX_VX_Cache_Bank__pi7 TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__3__KET____DOT__bank_structure; + + // CREATORS + Vcache_simX__Syms(Vcache_simX* topp, const char* namep); + ~Vcache_simX__Syms() {} + + // METHODS + inline const char* name() { return __Vm_namep; } + inline bool getClearActivity() { bool r=__Vm_activity; __Vm_activity=false; return r; } + +} VL_ATTR_ALIGNED(64); + +#endif // guard diff --git a/simX/obj_dir/Vcache_simX__Trace.cpp b/simX/obj_dir/Vcache_simX__Trace.cpp new file mode 100644 index 00000000..01049cf4 --- /dev/null +++ b/simX/obj_dir/Vcache_simX__Trace.cpp @@ -0,0 +1,5887 @@ +// Verilated -*- C++ -*- +// DESCRIPTION: Verilator output: Tracing implementation internals +#include "verilated_vcd_c.h" +#include "Vcache_simX__Syms.h" + + +//====================== + +void Vcache_simX::traceChg(VerilatedVcd* vcdp, void* userthis, uint32_t code) { + // Callback from vcd->dump() + Vcache_simX* t = (Vcache_simX*)userthis; + Vcache_simX__Syms* __restrict vlSymsp = t->__VlSymsp; // Setup global symbol table + if (vlSymsp->getClearActivity()) { + t->traceChgThis(vlSymsp, vcdp, code); + } +} + +//====================== + + +void Vcache_simX::traceChgThis(Vcache_simX__Syms* __restrict vlSymsp, VerilatedVcd* vcdp, uint32_t code) { + Vcache_simX* __restrict vlTOPp VL_ATTR_UNUSED = vlSymsp->TOPp; + int c = code; + if (0 && vcdp && c) {} // Prevent unused + // Body + { + if (VL_UNLIKELY((1U & (vlTOPp->__Vm_traceActivity + | (vlTOPp->__Vm_traceActivity + >> 1U))))) { + vlTOPp->traceChgThis__2(vlSymsp, vcdp, code); + } + if (VL_UNLIKELY((1U & ((vlTOPp->__Vm_traceActivity + | (vlTOPp->__Vm_traceActivity + >> 1U)) | (vlTOPp->__Vm_traceActivity + >> 2U))))) { + vlTOPp->traceChgThis__3(vlSymsp, vcdp, code); + } + if (VL_UNLIKELY((1U & (vlTOPp->__Vm_traceActivity + | (vlTOPp->__Vm_traceActivity + >> 2U))))) { + vlTOPp->traceChgThis__4(vlSymsp, vcdp, code); + } + if (VL_UNLIKELY((4U & vlTOPp->__Vm_traceActivity))) { + vlTOPp->traceChgThis__5(vlSymsp, vcdp, code); + } + vlTOPp->traceChgThis__6(vlSymsp, vcdp, code); + } + // Final + vlTOPp->__Vm_traceActivity = 0U; +} + +void Vcache_simX::traceChgThis__2(Vcache_simX__Syms* __restrict vlSymsp, VerilatedVcd* vcdp, uint32_t code) { + Vcache_simX* __restrict vlTOPp VL_ATTR_UNUSED = vlSymsp->TOPp; + int c = code; + if (0 && vcdp && c) {} // Prevent unused + // Variables + WData/*31:0*/ __Vtemp546[4]; + WData/*31:0*/ __Vtemp551[4]; + WData/*31:0*/ __Vtemp554[4]; + WData/*31:0*/ __Vtemp555[4]; + WData/*31:0*/ __Vtemp556[4]; + WData/*31:0*/ __Vtemp557[4]; + WData/*31:0*/ __Vtemp558[4]; + WData/*31:0*/ __Vtemp559[4]; + WData/*31:0*/ __Vtemp560[4]; + WData/*31:0*/ __Vtemp561[4]; + WData/*31:0*/ __Vtemp562[4]; + WData/*31:0*/ __Vtemp563[4]; + WData/*31:0*/ __Vtemp564[4]; + WData/*31:0*/ __Vtemp565[4]; + WData/*31:0*/ __Vtemp566[4]; + WData/*31:0*/ __Vtemp567[4]; + WData/*31:0*/ __Vtemp568[4]; + WData/*31:0*/ __Vtemp569[4]; + WData/*31:0*/ __Vtemp570[4]; + WData/*31:0*/ __Vtemp571[4]; + WData/*31:0*/ __Vtemp572[4]; + WData/*31:0*/ __Vtemp573[4]; + WData/*31:0*/ __Vtemp574[4]; + WData/*31:0*/ __Vtemp575[4]; + WData/*31:0*/ __Vtemp576[4]; + WData/*31:0*/ __Vtemp577[4]; + WData/*31:0*/ __Vtemp578[4]; + WData/*31:0*/ __Vtemp579[4]; + WData/*31:0*/ __Vtemp580[4]; + WData/*31:0*/ __Vtemp581[4]; + WData/*31:0*/ __Vtemp582[4]; + WData/*31:0*/ __Vtemp583[4]; + WData/*31:0*/ __Vtemp584[4]; + WData/*31:0*/ __Vtemp585[4]; + WData/*31:0*/ __Vtemp586[4]; + WData/*31:0*/ __Vtemp587[4]; + WData/*31:0*/ __Vtemp588[4]; + WData/*31:0*/ __Vtemp589[4]; + WData/*31:0*/ __Vtemp590[4]; + WData/*31:0*/ __Vtemp591[4]; + WData/*31:0*/ __Vtemp592[4]; + WData/*31:0*/ __Vtemp593[4]; + WData/*31:0*/ __Vtemp594[4]; + WData/*31:0*/ __Vtemp595[4]; + WData/*31:0*/ __Vtemp596[4]; + // Body + { + vcdp->chgBus(c+1,((0xffffffc0U & vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT__eviction_addr_per_bank[0U])),32); + vcdp->chgArray(c+2,(vlTOPp->cache_simX__DOT__dmem_controller__DOT____Vcellout__dcache__o_m_writedata),512); + vcdp->chgBus(c+18,((0xfffffff0U & ((vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__tag_use + << 9U) + | (0x1f0U + & vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_addr)))),32); + __Vtemp546[0U] = (((0U == (0x1fU & ((IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__data_structures__DOT__way_use_Qual) + << 7U))) + ? 0U : (vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__data_structures__DOT__data_use_per_way[ + ((IData)(1U) + + (4U & ((IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__data_structures__DOT__way_use_Qual) + << 2U)))] + << ((IData)(0x20U) + - (0x1fU & + ((IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__data_structures__DOT__way_use_Qual) + << 7U))))) + | (vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__data_structures__DOT__data_use_per_way[ + (4U & ((IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__data_structures__DOT__way_use_Qual) + << 2U))] >> (0x1fU + & ((IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__data_structures__DOT__way_use_Qual) + << 7U)))); + __Vtemp546[1U] = (((0U == (0x1fU & ((IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__data_structures__DOT__way_use_Qual) + << 7U))) + ? 0U : (vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__data_structures__DOT__data_use_per_way[ + ((IData)(2U) + + (4U & ((IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__data_structures__DOT__way_use_Qual) + << 2U)))] + << ((IData)(0x20U) + - (0x1fU & + ((IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__data_structures__DOT__way_use_Qual) + << 7U))))) + | (vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__data_structures__DOT__data_use_per_way[ + ((IData)(1U) + (4U & ((IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__data_structures__DOT__way_use_Qual) + << 2U)))] + >> (0x1fU & ((IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__data_structures__DOT__way_use_Qual) + << 7U)))); + __Vtemp546[2U] = (((0U == (0x1fU & ((IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__data_structures__DOT__way_use_Qual) + << 7U))) + ? 0U : (vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__data_structures__DOT__data_use_per_way[ + ((IData)(3U) + + (4U & ((IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__data_structures__DOT__way_use_Qual) + << 2U)))] + << ((IData)(0x20U) + - (0x1fU & + ((IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__data_structures__DOT__way_use_Qual) + << 7U))))) + | (vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__data_structures__DOT__data_use_per_way[ + ((IData)(2U) + (4U & ((IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__data_structures__DOT__way_use_Qual) + << 2U)))] + >> (0x1fU & ((IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__data_structures__DOT__way_use_Qual) + << 7U)))); + __Vtemp546[3U] = (((0U == (0x1fU & ((IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__data_structures__DOT__way_use_Qual) + << 7U))) + ? 0U : (vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__data_structures__DOT__data_use_per_way[ + ((IData)(4U) + + (4U & ((IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__data_structures__DOT__way_use_Qual) + << 2U)))] + << ((IData)(0x20U) + - (0x1fU & + ((IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__data_structures__DOT__way_use_Qual) + << 7U))))) + | (vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__data_structures__DOT__data_use_per_way[ + ((IData)(3U) + (4U & ((IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__data_structures__DOT__way_use_Qual) + << 2U)))] + >> (0x1fU & ((IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__data_structures__DOT__way_use_Qual) + << 7U)))); + vcdp->chgArray(c+19,(__Vtemp546),128); + vcdp->chgArray(c+23,(vlSymsp->TOP__cache_simX__DOT__VX_dcache_req.out_cache_driver_in_address),128); + vcdp->chgBus(c+27,(vlSymsp->TOP__cache_simX__DOT__VX_dcache_req.out_cache_driver_in_valid),4); + __Vtemp551[0U] = ((0xffU == (0xffU & ((vlSymsp->TOP__cache_simX__DOT__VX_dcache_req.out_cache_driver_in_address[1U] + << 8U) + | (vlSymsp->TOP__cache_simX__DOT__VX_dcache_req.out_cache_driver_in_address[0U] + >> 0x18U)))) + ? (((~ (IData)((0U != (IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__vx_priority_encoder_sm__DOT__more_than_one_valid)))) + & (0U != (IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__orig_in_valid))) + ? vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__temp_out_data[0U] + : 0U) : vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT__new_final_data_read_Qual[0U]); + __Vtemp551[1U] = ((0xffU == (0xffU & ((vlSymsp->TOP__cache_simX__DOT__VX_dcache_req.out_cache_driver_in_address[1U] + << 8U) + | (vlSymsp->TOP__cache_simX__DOT__VX_dcache_req.out_cache_driver_in_address[0U] + >> 0x18U)))) + ? (((~ (IData)((0U != (IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__vx_priority_encoder_sm__DOT__more_than_one_valid)))) + & (0U != (IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__orig_in_valid))) + ? vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__temp_out_data[1U] + : 0U) : vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT__new_final_data_read_Qual[1U]); + __Vtemp551[2U] = ((0xffU == (0xffU & ((vlSymsp->TOP__cache_simX__DOT__VX_dcache_req.out_cache_driver_in_address[1U] + << 8U) + | (vlSymsp->TOP__cache_simX__DOT__VX_dcache_req.out_cache_driver_in_address[0U] + >> 0x18U)))) + ? (((~ (IData)((0U != (IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__vx_priority_encoder_sm__DOT__more_than_one_valid)))) + & (0U != (IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__orig_in_valid))) + ? vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__temp_out_data[2U] + : 0U) : vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT__new_final_data_read_Qual[2U]); + __Vtemp551[3U] = ((0xffU == (0xffU & ((vlSymsp->TOP__cache_simX__DOT__VX_dcache_req.out_cache_driver_in_address[1U] + << 8U) + | (vlSymsp->TOP__cache_simX__DOT__VX_dcache_req.out_cache_driver_in_address[0U] + >> 0x18U)))) + ? (((~ (IData)((0U != (IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__vx_priority_encoder_sm__DOT__more_than_one_valid)))) + & (0U != (IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__orig_in_valid))) + ? vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__temp_out_data[3U] + : 0U) : vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT__new_final_data_read_Qual[3U]); + vcdp->chgArray(c+28,(__Vtemp551),128); + vcdp->chgBit(c+32,((0xffU == (0xffU & ((vlSymsp->TOP__cache_simX__DOT__VX_dcache_req.out_cache_driver_in_address[1U] + << 8U) + | (vlSymsp->TOP__cache_simX__DOT__VX_dcache_req.out_cache_driver_in_address[0U] + >> 0x18U)))))); + vcdp->chgBus(c+33,(vlTOPp->cache_simX__DOT__dmem_controller__DOT__sm_driver_in_valid),4); + vcdp->chgBus(c+34,(vlTOPp->cache_simX__DOT__dmem_controller__DOT__cache_driver_in_valid),4); + vcdp->chgBit(c+35,(vlTOPp->cache_simX__DOT__dmem_controller__DOT__read_or_write)); + vcdp->chgBus(c+36,(vlTOPp->cache_simX__DOT__dmem_controller__DOT__cache_driver_in_mem_read),3); + vcdp->chgBus(c+37,(vlTOPp->cache_simX__DOT__dmem_controller__DOT__cache_driver_in_mem_write),3); + vcdp->chgBus(c+38,(vlTOPp->cache_simX__DOT__dmem_controller__DOT__sm_driver_in_mem_read),3); + vcdp->chgBus(c+39,(vlTOPp->cache_simX__DOT__dmem_controller__DOT__sm_driver_in_mem_write),3); + vcdp->chgArray(c+40,(vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT__new_final_data_read_Qual),128); + __Vtemp554[0U] = (((~ (IData)((0U != (IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__vx_priority_encoder_sm__DOT__more_than_one_valid)))) + & (0U != (IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__orig_in_valid))) + ? vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__temp_out_data[0U] + : 0U); + __Vtemp554[1U] = (((~ (IData)((0U != (IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__vx_priority_encoder_sm__DOT__more_than_one_valid)))) + & (0U != (IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__orig_in_valid))) + ? vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__temp_out_data[1U] + : 0U); + __Vtemp554[2U] = (((~ (IData)((0U != (IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__vx_priority_encoder_sm__DOT__more_than_one_valid)))) + & (0U != (IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__orig_in_valid))) + ? vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__temp_out_data[2U] + : 0U); + __Vtemp554[3U] = (((~ (IData)((0U != (IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__vx_priority_encoder_sm__DOT__more_than_one_valid)))) + & (0U != (IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__orig_in_valid))) + ? vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__temp_out_data[3U] + : 0U); + vcdp->chgArray(c+44,(__Vtemp554),128); + vcdp->chgBus(c+48,((((~ (IData)((0U != (IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__vx_priority_encoder_sm__DOT__more_than_one_valid)))) + & (0U != (IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__orig_in_valid))) + ? (0xfU & (IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__temp_out_valid)) + : 0U)),4); + vcdp->chgBit(c+49,((0U != (IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__vx_priority_encoder_sm__DOT__more_than_one_valid)))); + vcdp->chgBus(c+50,(vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache_driver_in_mem_read),3); + vcdp->chgArray(c+51,(vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT____Vcellout__vx_priority_encoder_sm__out_address),128); + vcdp->chgArray(c+55,(vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT____Vcellout__vx_priority_encoder_sm__out_data),128); + vcdp->chgBus(c+59,(vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__vx_priority_encoder_sm__DOT__internal_out_valid),4); + vcdp->chgBus(c+60,(vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__temp_out_valid),4); + vcdp->chgArray(c+61,(vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__temp_out_data),128); + vcdp->chgBus(c+65,(vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__block_addr),28); + vcdp->chgArray(c+66,(vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__block_wdata),512); + vcdp->chgArray(c+82,(vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__block_rdata),512); + vcdp->chgBus(c+98,(vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__block_we),8); + vcdp->chgBit(c+99,(((~ (IData)((0U != (IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__vx_priority_encoder_sm__DOT__more_than_one_valid)))) + & (0U != (IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__orig_in_valid))))); + vcdp->chgBus(c+100,(vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__vx_priority_encoder_sm__DOT__internal_req_num),12); + vcdp->chgBus(c+101,(vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__orig_in_valid),4); + vcdp->chgBit(c+102,(vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__genblk2__BRA__0__KET____DOT__shm_write)); + vcdp->chgBit(c+103,(vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__genblk2__BRA__1__KET____DOT__shm_write)); + vcdp->chgBit(c+104,(vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__genblk2__BRA__2__KET____DOT__shm_write)); + vcdp->chgBit(c+105,(vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__genblk2__BRA__3__KET____DOT__shm_write)); + vcdp->chgBus(c+106,(vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__vx_priority_encoder_sm__DOT__serviced),4); + vcdp->chgBus(c+107,(vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__vx_priority_encoder_sm__DOT__use_valid),4); + vcdp->chgBus(c+108,(vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__vx_priority_encoder_sm__DOT____Vcellout__vx_bank_valid__bank_valids),16); + vcdp->chgBus(c+109,(vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__vx_priority_encoder_sm__DOT__more_than_one_valid),4); + vcdp->chgBus(c+110,(vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__vx_priority_encoder_sm__DOT__internal_req_num),8); + vcdp->chgBus(c+111,(vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__vx_priority_encoder_sm__DOT__serviced_qual),4); + vcdp->chgBus(c+112,(vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__vx_priority_encoder_sm__DOT__genblk1__BRA__0__KET____DOT__num_valids),3); + vcdp->chgBus(c+113,(vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__vx_priority_encoder_sm__DOT__genblk1__BRA__1__KET____DOT__num_valids),3); + vcdp->chgBus(c+114,(vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__vx_priority_encoder_sm__DOT__genblk1__BRA__2__KET____DOT__num_valids),3); + vcdp->chgBus(c+115,(vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__vx_priority_encoder_sm__DOT__genblk1__BRA__3__KET____DOT__num_valids),3); + vcdp->chgBus(c+116,((0xfU & (IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__vx_priority_encoder_sm__DOT____Vcellout__vx_bank_valid__bank_valids))),4); + vcdp->chgBus(c+117,((0xfU & ((IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__vx_priority_encoder_sm__DOT____Vcellout__vx_bank_valid__bank_valids) + >> 4U))),4); + vcdp->chgBus(c+118,((0xfU & ((IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__vx_priority_encoder_sm__DOT____Vcellout__vx_bank_valid__bank_valids) + >> 8U))),4); + vcdp->chgBus(c+119,((0xfU & ((IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__vx_priority_encoder_sm__DOT____Vcellout__vx_bank_valid__bank_valids) + >> 0xcU))),4); + vcdp->chgBus(c+120,(vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__vx_priority_encoder_sm__DOT____Vcellout__genblk2__BRA__0__KET____DOT__vx_priority_encoder__index),2); + vcdp->chgBit(c+121,(vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__vx_priority_encoder_sm__DOT____Vcellout__genblk2__BRA__0__KET____DOT__vx_priority_encoder__found)); + vcdp->chgBus(c+122,(vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__vx_priority_encoder_sm__DOT__genblk2__BRA__0__KET____DOT__vx_priority_encoder__DOT__i),32); + vcdp->chgBus(c+123,(vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__vx_priority_encoder_sm__DOT____Vcellout__genblk2__BRA__1__KET____DOT__vx_priority_encoder__index),2); + vcdp->chgBit(c+124,(vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__vx_priority_encoder_sm__DOT____Vcellout__genblk2__BRA__1__KET____DOT__vx_priority_encoder__found)); + vcdp->chgBus(c+125,(vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__vx_priority_encoder_sm__DOT__genblk2__BRA__1__KET____DOT__vx_priority_encoder__DOT__i),32); + vcdp->chgBus(c+126,(vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__vx_priority_encoder_sm__DOT____Vcellout__genblk2__BRA__2__KET____DOT__vx_priority_encoder__index),2); + vcdp->chgBit(c+127,(vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__vx_priority_encoder_sm__DOT____Vcellout__genblk2__BRA__2__KET____DOT__vx_priority_encoder__found)); + vcdp->chgBus(c+128,(vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__vx_priority_encoder_sm__DOT__genblk2__BRA__2__KET____DOT__vx_priority_encoder__DOT__i),32); + vcdp->chgBus(c+129,(vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__vx_priority_encoder_sm__DOT____Vcellout__genblk2__BRA__3__KET____DOT__vx_priority_encoder__index),2); + vcdp->chgBit(c+130,(vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__vx_priority_encoder_sm__DOT____Vcellout__genblk2__BRA__3__KET____DOT__vx_priority_encoder__found)); + vcdp->chgBus(c+131,(vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__vx_priority_encoder_sm__DOT__genblk2__BRA__3__KET____DOT__vx_priority_encoder__DOT__i),32); + vcdp->chgBus(c+132,((0x7fU & vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__block_addr)),7); + __Vtemp555[0U] = vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__block_wdata[0U]; + __Vtemp555[1U] = vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__block_wdata[1U]; + __Vtemp555[2U] = vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__block_wdata[2U]; + __Vtemp555[3U] = vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__block_wdata[3U]; + vcdp->chgArray(c+133,(__Vtemp555),128); + vcdp->chgBus(c+137,((3U & (IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__block_we))),2); + vcdp->chgBus(c+138,((0x7fU & (vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__block_addr + >> 7U))),7); + __Vtemp556[0U] = vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__block_wdata[4U]; + __Vtemp556[1U] = vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__block_wdata[5U]; + __Vtemp556[2U] = vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__block_wdata[6U]; + __Vtemp556[3U] = vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__block_wdata[7U]; + vcdp->chgArray(c+139,(__Vtemp556),128); + vcdp->chgBus(c+143,((3U & ((IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__block_we) + >> 2U))),2); + vcdp->chgBus(c+144,((0x7fU & (vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__block_addr + >> 0xeU))),7); + __Vtemp557[0U] = vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__block_wdata[8U]; + __Vtemp557[1U] = vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__block_wdata[9U]; + __Vtemp557[2U] = vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__block_wdata[0xaU]; + __Vtemp557[3U] = vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__block_wdata[0xbU]; + vcdp->chgArray(c+145,(__Vtemp557),128); + vcdp->chgBus(c+149,((3U & ((IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__block_we) + >> 4U))),2); + vcdp->chgBus(c+150,((0x7fU & (vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__block_addr + >> 0x15U))),7); + __Vtemp558[0U] = vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__block_wdata[0xcU]; + __Vtemp558[1U] = vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__block_wdata[0xdU]; + __Vtemp558[2U] = vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__block_wdata[0xeU]; + __Vtemp558[3U] = vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__block_wdata[0xfU]; + vcdp->chgArray(c+151,(__Vtemp558),128); + vcdp->chgBus(c+155,((3U & ((IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__block_we) + >> 6U))),2); + vcdp->chgArray(c+156,(vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT__new_final_data_read),128); + vcdp->chgBus(c+160,(vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT____Vcellout__multip_banks__thread_track_banks),16); + vcdp->chgBus(c+161,(vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT__index_per_bank),8); + vcdp->chgBus(c+162,(vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT__use_mask_per_bank),16); + vcdp->chgBus(c+163,(vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT__valid_per_bank),4); + vcdp->chgBus(c+164,(vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT__threads_serviced_per_bank),16); + vcdp->chgArray(c+165,(vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT__readdata_per_bank),128); + vcdp->chgBus(c+169,(vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT__hit_per_bank),4); + vcdp->chgBus(c+170,(vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT__eviction_wb),4); + vcdp->chgBus(c+171,(vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT__new_state),4); + vcdp->chgBus(c+172,(vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT__use_valid),4); + vcdp->chgBus(c+173,(vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT__new_stored_valid),4); + vcdp->chgArray(c+174,(vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT__eviction_addr_per_bank),128); + vcdp->chgBit(c+178,((0U != (IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__cache_driver_in_valid)))); + vcdp->chgBus(c+179,(vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT__threads_serviced_Qual),4); + vcdp->chgBus(c+180,(vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT__debug_hit_per_bank_mask[0]),4); + vcdp->chgBus(c+181,(vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT__debug_hit_per_bank_mask[1]),4); + vcdp->chgBus(c+182,(vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT__debug_hit_per_bank_mask[2]),4); + vcdp->chgBus(c+183,(vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT__debug_hit_per_bank_mask[3]),4); + vcdp->chgBus(c+184,(vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT__detect_bank_miss),4); + vcdp->chgBus(c+185,(vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT__miss_bank_index),2); + vcdp->chgBit(c+186,(vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT__miss_found)); + vcdp->chgBus(c+187,((0xfU & (IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT____Vcellout__multip_banks__thread_track_banks))),4); + vcdp->chgBus(c+188,((3U & (IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT__index_per_bank))),2); + vcdp->chgBit(c+189,((1U & (IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT__hit_per_bank)))); + vcdp->chgBus(c+190,(vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT__readdata_per_bank[0U]),32); + vcdp->chgBus(c+191,((0xfU & ((IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT____Vcellout__multip_banks__thread_track_banks) + >> 4U))),4); + vcdp->chgBus(c+192,((3U & ((IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT__index_per_bank) + >> 2U))),2); + vcdp->chgBit(c+193,((1U & ((IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT__hit_per_bank) + >> 1U)))); + vcdp->chgBus(c+194,(vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT__readdata_per_bank[1U]),32); + vcdp->chgBus(c+195,((0xfU & ((IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT____Vcellout__multip_banks__thread_track_banks) + >> 8U))),4); + vcdp->chgBus(c+196,((3U & ((IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT__index_per_bank) + >> 4U))),2); + vcdp->chgBit(c+197,((1U & ((IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT__hit_per_bank) + >> 2U)))); + vcdp->chgBus(c+198,(vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT__readdata_per_bank[2U]),32); + vcdp->chgBus(c+199,((0xfU & ((IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT____Vcellout__multip_banks__thread_track_banks) + >> 0xcU))),4); + vcdp->chgBus(c+200,((3U & ((IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT__index_per_bank) + >> 6U))),2); + vcdp->chgBit(c+201,((1U & ((IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT__hit_per_bank) + >> 3U)))); + vcdp->chgBus(c+202,(vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT__readdata_per_bank[3U]),32); + vcdp->chgBus(c+203,(vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__0__KET____DOT__bank_addr),32); + vcdp->chgBus(c+204,((3U & vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__0__KET____DOT__bank_addr)),2); + vcdp->chgBus(c+205,((3U & (vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__0__KET____DOT__bank_addr + >> 4U))),2); + vcdp->chgBus(c+206,((0x1fU & (vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__0__KET____DOT__bank_addr + >> 6U))),5); + vcdp->chgBus(c+207,((0x1fffffU & (vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__0__KET____DOT__bank_addr + >> 0xbU))),21); + vcdp->chgBit(c+208,((1U & (IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT__valid_per_bank)))); + vcdp->chgBit(c+209,(vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__0__KET____DOT__use_valid_in)); + vcdp->chgBus(c+210,(vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__1__KET____DOT__bank_addr),32); + vcdp->chgBus(c+211,((3U & vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__1__KET____DOT__bank_addr)),2); + vcdp->chgBus(c+212,((3U & (vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__1__KET____DOT__bank_addr + >> 4U))),2); + vcdp->chgBus(c+213,((0x1fU & (vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__1__KET____DOT__bank_addr + >> 6U))),5); + vcdp->chgBus(c+214,((0x1fffffU & (vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__1__KET____DOT__bank_addr + >> 0xbU))),21); + vcdp->chgBit(c+215,((1U & ((IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT__valid_per_bank) + >> 1U)))); + vcdp->chgBit(c+216,(vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__1__KET____DOT__use_valid_in)); + vcdp->chgBus(c+217,(vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__2__KET____DOT__bank_addr),32); + vcdp->chgBus(c+218,((3U & vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__2__KET____DOT__bank_addr)),2); + vcdp->chgBus(c+219,((3U & (vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__2__KET____DOT__bank_addr + >> 4U))),2); + vcdp->chgBus(c+220,((0x1fU & (vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__2__KET____DOT__bank_addr + >> 6U))),5); + vcdp->chgBus(c+221,((0x1fffffU & (vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__2__KET____DOT__bank_addr + >> 0xbU))),21); + vcdp->chgBit(c+222,((1U & ((IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT__valid_per_bank) + >> 2U)))); + vcdp->chgBit(c+223,(vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__2__KET____DOT__use_valid_in)); + vcdp->chgBus(c+224,(vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__3__KET____DOT__bank_addr),32); + vcdp->chgBus(c+225,((3U & vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__3__KET____DOT__bank_addr)),2); + vcdp->chgBus(c+226,((3U & (vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__3__KET____DOT__bank_addr + >> 4U))),2); + vcdp->chgBus(c+227,((0x1fU & (vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__3__KET____DOT__bank_addr + >> 6U))),5); + vcdp->chgBus(c+228,((0x1fffffU & (vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__3__KET____DOT__bank_addr + >> 0xbU))),21); + vcdp->chgBit(c+229,((1U & ((IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT__valid_per_bank) + >> 3U)))); + vcdp->chgBit(c+230,(vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__3__KET____DOT__use_valid_in)); + vcdp->chgBus(c+231,(vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT__get_miss_index__DOT__i),32); + vcdp->chgBus(c+232,(((IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT____Vcellout__genblk1__BRA__0__KET____DOT__choose_thread__found) + ? (0xfU & ((IData)(1U) + << (IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT____Vcellout__genblk1__BRA__0__KET____DOT__choose_thread__index))) + : 0U)),4); + vcdp->chgBus(c+233,(vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT____Vcellout__genblk1__BRA__0__KET____DOT__choose_thread__index),2); + vcdp->chgBit(c+234,(vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT____Vcellout__genblk1__BRA__0__KET____DOT__choose_thread__found)); + vcdp->chgBus(c+235,(vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk1__BRA__0__KET____DOT__choose_thread__DOT__i),32); + vcdp->chgBus(c+236,(((IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT____Vcellout__genblk1__BRA__1__KET____DOT__choose_thread__found) + ? (0xfU & ((IData)(1U) + << (IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT____Vcellout__genblk1__BRA__1__KET____DOT__choose_thread__index))) + : 0U)),4); + vcdp->chgBus(c+237,(vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT____Vcellout__genblk1__BRA__1__KET____DOT__choose_thread__index),2); + vcdp->chgBit(c+238,(vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT____Vcellout__genblk1__BRA__1__KET____DOT__choose_thread__found)); + vcdp->chgBus(c+239,(vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk1__BRA__1__KET____DOT__choose_thread__DOT__i),32); + vcdp->chgBus(c+240,(((IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT____Vcellout__genblk1__BRA__2__KET____DOT__choose_thread__found) + ? (0xfU & ((IData)(1U) + << (IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT____Vcellout__genblk1__BRA__2__KET____DOT__choose_thread__index))) + : 0U)),4); + vcdp->chgBus(c+241,(vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT____Vcellout__genblk1__BRA__2__KET____DOT__choose_thread__index),2); + vcdp->chgBit(c+242,(vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT____Vcellout__genblk1__BRA__2__KET____DOT__choose_thread__found)); + vcdp->chgBus(c+243,(vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk1__BRA__2__KET____DOT__choose_thread__DOT__i),32); + vcdp->chgBus(c+244,(((IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT____Vcellout__genblk1__BRA__3__KET____DOT__choose_thread__found) + ? (0xfU & ((IData)(1U) + << (IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT____Vcellout__genblk1__BRA__3__KET____DOT__choose_thread__index))) + : 0U)),4); + vcdp->chgBus(c+245,(vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT____Vcellout__genblk1__BRA__3__KET____DOT__choose_thread__index),2); + vcdp->chgBit(c+246,(vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT____Vcellout__genblk1__BRA__3__KET____DOT__choose_thread__found)); + vcdp->chgBus(c+247,(vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk1__BRA__3__KET____DOT__choose_thread__DOT__i),32); + vcdp->chgBus(c+248,(vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__new_final_data_read),32); + vcdp->chgBit(c+249,(vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT____Vcellout__multip_banks__thread_track_banks)); + vcdp->chgBit(c+250,(vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT____Vcellout__genblk1__BRA__0__KET____DOT__choose_thread__index)); + vcdp->chgBit(c+251,(((IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__valid_per_bank) + ? (1U & ((IData)(1U) + << (IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT____Vcellout__genblk1__BRA__0__KET____DOT__choose_thread__index))) + : 0U))); + vcdp->chgBit(c+252,(vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__valid_per_bank)); + vcdp->chgBit(c+253,(vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__threads_serviced_per_bank)); + vcdp->chgBus(c+254,(((IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__access) + ? ((0U == (IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache_driver_in_mem_read)) + ? ((0x80U & vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__data_unQual) + ? (0xffffff00U + | vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__data_unQual) + : (0xffU & vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__data_unQual)) + : ((1U == (IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache_driver_in_mem_read)) + ? ((0x8000U & vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__data_unQual) + ? (0xffff0000U + | vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__data_unQual) + : (0xffffU + & vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__data_unQual)) + : ((5U == (IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache_driver_in_mem_read)) + ? (0xffffU + & vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__data_unQual) + : ((4U == (IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache_driver_in_mem_read)) + ? (0xffU + & vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__data_unQual) + : vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__data_unQual)))) + : 0U)),32); + vcdp->chgBit(c+255,(vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__hit_per_bank)); + vcdp->chgBit(c+256,((1U & ((IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__data_structures__DOT__dirty_use_per_way) + >> (IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__data_structures__DOT__way_use_Qual))))); + vcdp->chgBus(c+257,(vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__new_state),4); + vcdp->chgBit(c+258,(vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__use_valid)); + vcdp->chgBit(c+259,(vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__new_stored_valid)); + vcdp->chgBus(c+260,(((vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__tag_use + << 9U) | (0x1f0U & vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_addr))),32); + vcdp->chgBit(c+261,(vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__threads_serviced_per_bank)); + vcdp->chgBit(c+262,(vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__debug_hit_per_bank_mask[0])); + vcdp->chgBit(c+263,(vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__detect_bank_miss)); + vcdp->chgBit(c+264,(vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__miss_bank_index)); + vcdp->chgBit(c+265,(vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__miss_found)); + vcdp->chgBit(c+266,(vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__hit_per_bank)); + vcdp->chgBus(c+267,(vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_addr),32); + vcdp->chgBus(c+268,((3U & vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_addr)),2); + vcdp->chgBus(c+269,((3U & (vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_addr + >> 2U))),2); + vcdp->chgBus(c+270,((0x1fU & (vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_addr + >> 4U))),5); + vcdp->chgBus(c+271,((0x7fffffU & (vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_addr + >> 9U))),23); + vcdp->chgBit(c+272,(vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__valid_per_bank)); + vcdp->chgBit(c+273,(vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__use_valid_in)); + vcdp->chgBus(c+274,(0U),32); + vcdp->chgBus(c+275,(vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__tag_use),23); + vcdp->chgBit(c+276,(vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__valid_use)); + vcdp->chgBit(c+277,(vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__access)); + vcdp->chgBit(c+278,(vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__write_from_mem)); + vcdp->chgBit(c+279,((((vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__tag_use + != (0x7fffffU & (vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_addr + >> 9U))) + & (IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__valid_use)) + & (IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__use_valid_in)))); + vcdp->chgBit(c+280,((2U == (IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache_driver_in_mem_read)))); + vcdp->chgBit(c+281,((0U == (IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache_driver_in_mem_read)))); + vcdp->chgBit(c+282,((1U == (IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache_driver_in_mem_read)))); + vcdp->chgBit(c+283,((5U == (IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache_driver_in_mem_read)))); + vcdp->chgBit(c+284,((4U == (IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache_driver_in_mem_read)))); + vcdp->chgBit(c+285,((0U == (3U & vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_addr)))); + vcdp->chgBit(c+286,((1U == (3U & vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_addr)))); + vcdp->chgBit(c+287,((2U == (3U & vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_addr)))); + vcdp->chgBit(c+288,((3U == (3U & vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_addr)))); + vcdp->chgBus(c+289,(vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__data_unQual),32); + vcdp->chgBus(c+290,(((0x80U & vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__data_unQual) + ? (0xffffff00U | vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__data_unQual) + : (0xffU & vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__data_unQual))),32); + vcdp->chgBus(c+291,(((0x8000U & vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__data_unQual) + ? (0xffff0000U | vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__data_unQual) + : (0xffffU & vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__data_unQual))),32); + vcdp->chgBus(c+292,((0xffU & vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__data_unQual)),32); + vcdp->chgBus(c+293,((0xffffU & vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__data_unQual)),32); + vcdp->chgBus(c+294,(0U),32); + vcdp->chgBus(c+295,(0U),32); + vcdp->chgBus(c+296,(((0U == (IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache_driver_in_mem_read)) + ? ((0x80U & vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__data_unQual) + ? (0xffffff00U | vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__data_unQual) + : (0xffU & vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__data_unQual)) + : ((1U == (IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache_driver_in_mem_read)) + ? ((0x8000U & vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__data_unQual) + ? (0xffff0000U + | vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__data_unQual) + : (0xffffU & vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__data_unQual)) + : ((5U == (IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache_driver_in_mem_read)) + ? (0xffffU & vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__data_unQual) + : ((4U == (IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache_driver_in_mem_read)) + ? (0xffU + & vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__data_unQual) + : vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__data_unQual))))),32); + vcdp->chgBus(c+297,(vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__sb_mask),4); + vcdp->chgBus(c+298,(((0U == (3U & vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_addr)) + ? 3U : 0xcU)),4); + vcdp->chgBus(c+299,(vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__we),16); + vcdp->chgArray(c+300,(vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__data_write),128); + vcdp->chgQuad(c+304,(vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__data_structures__DOT__tag_use_per_way),46); + vcdp->chgArray(c+306,(vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__data_structures__DOT__data_use_per_way),256); + vcdp->chgBus(c+314,(vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__data_structures__DOT__valid_use_per_way),2); + vcdp->chgBus(c+315,(vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__data_structures__DOT__dirty_use_per_way),2); + vcdp->chgBus(c+316,(vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__data_structures__DOT__hit_per_way),2); + vcdp->chgBus(c+317,(vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__data_structures__DOT__we_per_way),32); + vcdp->chgArray(c+318,(vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__data_structures__DOT__data_write_per_way),256); + vcdp->chgBus(c+326,(vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__data_structures__DOT__write_from_mem_per_way),2); + vcdp->chgBit(c+327,(vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__data_structures__DOT__invalid_found)); + vcdp->chgBit(c+328,(vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__data_structures__DOT__way_index)); + vcdp->chgBit(c+329,(vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__data_structures__DOT__invalid_index)); + vcdp->chgBit(c+330,(vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__data_structures__DOT__way_use_Qual)); + vcdp->chgBus(c+331,((3U & (~ (IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__data_structures__DOT__valid_use_per_way)))),2); + vcdp->chgBit(c+332,(vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__data_structures__DOT__genblk1__DOT__way_indexing__DOT__found)); + vcdp->chgBus(c+333,((0xffffU & vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__data_structures__DOT__we_per_way)),16); + vcdp->chgBit(c+334,((1U & (IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__data_structures__DOT__write_from_mem_per_way)))); + __Vtemp559[0U] = vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__data_structures__DOT__data_write_per_way[0U]; + __Vtemp559[1U] = vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__data_structures__DOT__data_write_per_way[1U]; + __Vtemp559[2U] = vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__data_structures__DOT__data_write_per_way[2U]; + __Vtemp559[3U] = vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__data_structures__DOT__data_write_per_way[3U]; + vcdp->chgArray(c+335,(__Vtemp559),128); + vcdp->chgBit(c+339,(vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__data_structures__DOT____Vcellout__each_way__BRA__0__KET____DOT__data_structures__dirty_use)); + vcdp->chgBit(c+340,((0U != (0xffffU & vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__data_structures__DOT__we_per_way)))); + vcdp->chgBit(c+341,((1U & (((~ (IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__data_structures__DOT____Vcellout__each_way__BRA__0__KET____DOT__data_structures__dirty_use)) + & (0U != (0xffffU + & vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__data_structures__DOT__we_per_way))) + | (IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__data_structures__DOT__write_from_mem_per_way))))); + vcdp->chgBit(c+342,(((1U & (IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__data_structures__DOT__write_from_mem_per_way)) + ? 0U : (1U & (0U != (0xffffU + & vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__data_structures__DOT__we_per_way)))))); + vcdp->chgBus(c+343,((0xffffU & (vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__data_structures__DOT__we_per_way + >> 0x10U))),16); + vcdp->chgBit(c+344,((1U & ((IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__data_structures__DOT__write_from_mem_per_way) + >> 1U)))); + __Vtemp560[0U] = vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__data_structures__DOT__data_write_per_way[4U]; + __Vtemp560[1U] = vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__data_structures__DOT__data_write_per_way[5U]; + __Vtemp560[2U] = vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__data_structures__DOT__data_write_per_way[6U]; + __Vtemp560[3U] = vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__data_structures__DOT__data_write_per_way[7U]; + vcdp->chgArray(c+345,(__Vtemp560),128); + vcdp->chgBit(c+349,(vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__data_structures__DOT____Vcellout__each_way__BRA__1__KET____DOT__data_structures__dirty_use)); + vcdp->chgBit(c+350,((0U != (0xffffU & (vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__data_structures__DOT__we_per_way + >> 0x10U))))); + vcdp->chgBit(c+351,((1U & (((~ (IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__data_structures__DOT____Vcellout__each_way__BRA__1__KET____DOT__data_structures__dirty_use)) + & (0U != (0xffffU + & (vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__data_structures__DOT__we_per_way + >> 0x10U)))) + | ((IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__data_structures__DOT__write_from_mem_per_way) + >> 1U))))); + vcdp->chgBit(c+352,(((2U & (IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__data_structures__DOT__write_from_mem_per_way)) + ? 0U : (1U & (0U != (0xffffU + & (vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__data_structures__DOT__we_per_way + >> 0x10U))))))); + __Vtemp561[0U] = 0U; + __Vtemp561[1U] = 0U; + __Vtemp561[2U] = 0U; + __Vtemp561[3U] = 0U; + vcdp->chgBus(c+353,(__Vtemp561[(3U & (IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT__index_per_bank))]),32); + vcdp->chgBus(c+354,(((IData)(vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__0__KET____DOT__bank_structure.__PVT__access) + ? ((0U == (IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__cache_driver_in_mem_read)) + ? ((0x80U & vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__0__KET____DOT__bank_structure.__PVT__data_unQual) + ? (0xffffff00U + | vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__0__KET____DOT__bank_structure.__PVT__data_unQual) + : (0xffU & vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__0__KET____DOT__bank_structure.__PVT__data_unQual)) + : ((1U == (IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__cache_driver_in_mem_read)) + ? ((0x8000U & vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__0__KET____DOT__bank_structure.__PVT__data_unQual) + ? (0xffff0000U + | vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__0__KET____DOT__bank_structure.__PVT__data_unQual) + : (0xffffU + & vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__0__KET____DOT__bank_structure.__PVT__data_unQual)) + : ((5U == (IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__cache_driver_in_mem_read)) + ? (0xffffU + & vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__0__KET____DOT__bank_structure.__PVT__data_unQual) + : ((4U == (IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__cache_driver_in_mem_read)) + ? (0xffU + & vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__0__KET____DOT__bank_structure.__PVT__data_unQual) + : vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__0__KET____DOT__bank_structure.__PVT__data_unQual)))) + : 0U)),32); + vcdp->chgBit(c+355,((((IData)(vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__0__KET____DOT__bank_structure.__PVT__access) + & (vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__0__KET____DOT__bank_structure.__PVT__tag_use + == (0x1fffffU & (vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__0__KET____DOT__bank_addr + >> 0xbU)))) + & (IData)(vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__0__KET____DOT__bank_structure.__PVT__valid_use)))); + vcdp->chgBit(c+356,((1U & ((IData)(vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__0__KET____DOT__bank_structure.__PVT__data_structures__DOT__dirty_use_per_way) + >> (IData)(vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__0__KET____DOT__bank_structure.__PVT__data_structures__DOT__way_use_Qual))))); + vcdp->chgBus(c+357,(((vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__0__KET____DOT__bank_structure.__PVT__tag_use + << 0xbU) | (0x7c0U & vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__0__KET____DOT__bank_addr))),32); + vcdp->chgArray(c+358,(vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__0__KET____DOT__bank_structure.__Vcellout__data_structures__data_use),128); + vcdp->chgBus(c+362,(vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__0__KET____DOT__bank_structure.__PVT__tag_use),21); + vcdp->chgBit(c+363,(vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__0__KET____DOT__bank_structure.__PVT__valid_use)); + vcdp->chgBit(c+364,(vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__0__KET____DOT__bank_structure.__PVT__access)); + vcdp->chgBit(c+365,(vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__0__KET____DOT__bank_structure.__PVT__write_from_mem)); + vcdp->chgBit(c+366,(vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__0__KET____DOT__bank_structure.__PVT__miss)); + vcdp->chgBit(c+367,((2U == (IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__cache_driver_in_mem_read)))); + vcdp->chgBit(c+368,((0U == (IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__cache_driver_in_mem_read)))); + vcdp->chgBit(c+369,((1U == (IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__cache_driver_in_mem_read)))); + vcdp->chgBit(c+370,((5U == (IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__cache_driver_in_mem_read)))); + vcdp->chgBit(c+371,((4U == (IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__cache_driver_in_mem_read)))); + vcdp->chgBit(c+372,((2U == (IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__cache_driver_in_mem_write)))); + vcdp->chgBit(c+373,((0U == (IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__cache_driver_in_mem_write)))); + vcdp->chgBit(c+374,((1U == (IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__cache_driver_in_mem_write)))); + vcdp->chgBit(c+375,((0U == (3U & vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__0__KET____DOT__bank_addr)))); + vcdp->chgBit(c+376,((1U == (3U & vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__0__KET____DOT__bank_addr)))); + vcdp->chgBit(c+377,((2U == (3U & vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__0__KET____DOT__bank_addr)))); + vcdp->chgBit(c+378,((3U == (3U & vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__0__KET____DOT__bank_addr)))); + vcdp->chgBus(c+379,(vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__0__KET____DOT__bank_structure.__PVT__data_unQual),32); + vcdp->chgBus(c+380,(((0x80U & vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__0__KET____DOT__bank_structure.__PVT__data_unQual) + ? (0xffffff00U | vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__0__KET____DOT__bank_structure.__PVT__data_unQual) + : (0xffU & vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__0__KET____DOT__bank_structure.__PVT__data_unQual))),32); + vcdp->chgBus(c+381,(((0x8000U & vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__0__KET____DOT__bank_structure.__PVT__data_unQual) + ? (0xffff0000U | vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__0__KET____DOT__bank_structure.__PVT__data_unQual) + : (0xffffU & vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__0__KET____DOT__bank_structure.__PVT__data_unQual))),32); + vcdp->chgBus(c+382,((0xffU & vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__0__KET____DOT__bank_structure.__PVT__data_unQual)),32); + vcdp->chgBus(c+383,((0xffffU & vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__0__KET____DOT__bank_structure.__PVT__data_unQual)),32); + __Vtemp562[0U] = 0U; + __Vtemp562[1U] = 0U; + __Vtemp562[2U] = 0U; + __Vtemp562[3U] = 0U; + __Vtemp563[0U] = 0U; + __Vtemp563[1U] = 0U; + __Vtemp563[2U] = 0U; + __Vtemp563[3U] = 0U; + __Vtemp564[0U] = 0U; + __Vtemp564[1U] = 0U; + __Vtemp564[2U] = 0U; + __Vtemp564[3U] = 0U; + __Vtemp565[0U] = 0U; + __Vtemp565[1U] = 0U; + __Vtemp565[2U] = 0U; + __Vtemp565[3U] = 0U; + vcdp->chgBus(c+384,(((1U == (3U & vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__0__KET____DOT__bank_addr)) + ? (0xff00U & (__Vtemp562[ + (3U & (IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT__index_per_bank))] + << 8U)) + : ((2U == (3U & vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__0__KET____DOT__bank_addr)) + ? (0xff0000U & (__Vtemp563[ + (3U + & (IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT__index_per_bank))] + << 0x10U)) + : ((3U == (3U & vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__0__KET____DOT__bank_addr)) + ? (0xff000000U + & (__Vtemp564[ + (3U & (IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT__index_per_bank))] + << 0x18U)) + : __Vtemp565[ + (3U & (IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT__index_per_bank))])))),32); + __Vtemp566[0U] = 0U; + __Vtemp566[1U] = 0U; + __Vtemp566[2U] = 0U; + __Vtemp566[3U] = 0U; + __Vtemp567[0U] = 0U; + __Vtemp567[1U] = 0U; + __Vtemp567[2U] = 0U; + __Vtemp567[3U] = 0U; + vcdp->chgBus(c+385,(((2U == (3U & vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__0__KET____DOT__bank_addr)) + ? (0xffff0000U & (__Vtemp566[ + (3U + & (IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT__index_per_bank))] + << 0x10U)) + : __Vtemp567[(3U & (IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT__index_per_bank))])),32); + vcdp->chgBus(c+386,(vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__0__KET____DOT__bank_structure.__PVT__use_write_data),32); + vcdp->chgBus(c+387,(((0U == (IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__cache_driver_in_mem_read)) + ? ((0x80U & vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__0__KET____DOT__bank_structure.__PVT__data_unQual) + ? (0xffffff00U | vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__0__KET____DOT__bank_structure.__PVT__data_unQual) + : (0xffU & vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__0__KET____DOT__bank_structure.__PVT__data_unQual)) + : ((1U == (IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__cache_driver_in_mem_read)) + ? ((0x8000U & vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__0__KET____DOT__bank_structure.__PVT__data_unQual) + ? (0xffff0000U + | vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__0__KET____DOT__bank_structure.__PVT__data_unQual) + : (0xffffU & vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__0__KET____DOT__bank_structure.__PVT__data_unQual)) + : ((5U == (IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__cache_driver_in_mem_read)) + ? (0xffffU & vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__0__KET____DOT__bank_structure.__PVT__data_unQual) + : ((4U == (IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__cache_driver_in_mem_read)) + ? (0xffU + & vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__0__KET____DOT__bank_structure.__PVT__data_unQual) + : vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__0__KET____DOT__bank_structure.__PVT__data_unQual))))),32); + vcdp->chgBus(c+388,(vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__0__KET____DOT__bank_structure.__PVT__sb_mask),4); + vcdp->chgBus(c+389,(((0U == (3U & vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__0__KET____DOT__bank_addr)) + ? 3U : 0xcU)),4); + vcdp->chgBus(c+390,(vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__0__KET____DOT__bank_structure.__PVT__we),16); + vcdp->chgArray(c+391,(vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__0__KET____DOT__bank_structure.__PVT__data_write),128); + vcdp->chgBit(c+395,(vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__0__KET____DOT__bank_structure.__PVT__genblk1__BRA__0__KET____DOT__normal_write)); + vcdp->chgBit(c+396,(vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__0__KET____DOT__bank_structure.__PVT__genblk1__BRA__1__KET____DOT__normal_write)); + vcdp->chgBit(c+397,(vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__0__KET____DOT__bank_structure.__PVT__genblk1__BRA__2__KET____DOT__normal_write)); + vcdp->chgBit(c+398,(vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__0__KET____DOT__bank_structure.__PVT__genblk1__BRA__3__KET____DOT__normal_write)); + vcdp->chgQuad(c+399,(vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__0__KET____DOT__bank_structure.__PVT__data_structures__DOT__tag_use_per_way),42); + vcdp->chgArray(c+401,(vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__0__KET____DOT__bank_structure.__PVT__data_structures__DOT__data_use_per_way),256); + vcdp->chgBus(c+409,(vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__0__KET____DOT__bank_structure.__PVT__data_structures__DOT__valid_use_per_way),2); + vcdp->chgBus(c+410,(vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__0__KET____DOT__bank_structure.__PVT__data_structures__DOT__dirty_use_per_way),2); + vcdp->chgBus(c+411,(vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__0__KET____DOT__bank_structure.__PVT__data_structures__DOT__hit_per_way),2); + vcdp->chgBus(c+412,(vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__0__KET____DOT__bank_structure.__PVT__data_structures__DOT__we_per_way),32); + vcdp->chgArray(c+413,(vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__0__KET____DOT__bank_structure.__PVT__data_structures__DOT__data_write_per_way),256); + vcdp->chgBus(c+421,(vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__0__KET____DOT__bank_structure.__PVT__data_structures__DOT__write_from_mem_per_way),2); + vcdp->chgBit(c+422,(vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__0__KET____DOT__bank_structure.__PVT__data_structures__DOT__invalid_found)); + vcdp->chgBit(c+423,(vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__0__KET____DOT__bank_structure.__PVT__data_structures__DOT__way_index)); + vcdp->chgBit(c+424,(vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__0__KET____DOT__bank_structure.__PVT__data_structures__DOT__invalid_index)); + vcdp->chgBit(c+425,(vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__0__KET____DOT__bank_structure.__PVT__data_structures__DOT__way_use_Qual)); + vcdp->chgBus(c+426,((3U & (~ (IData)(vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__0__KET____DOT__bank_structure.__PVT__data_structures__DOT__valid_use_per_way)))),2); + vcdp->chgBit(c+427,(vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__0__KET____DOT__bank_structure.__PVT__data_structures__DOT__genblk1__DOT__way_indexing__DOT__found)); + vcdp->chgBus(c+428,((0xffffU & vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__0__KET____DOT__bank_structure.__PVT__data_structures__DOT__we_per_way)),16); + vcdp->chgBit(c+429,((1U & (IData)(vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__0__KET____DOT__bank_structure.__PVT__data_structures__DOT__write_from_mem_per_way)))); + __Vtemp568[0U] = vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__0__KET____DOT__bank_structure.__PVT__data_structures__DOT__data_write_per_way[0U]; + __Vtemp568[1U] = vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__0__KET____DOT__bank_structure.__PVT__data_structures__DOT__data_write_per_way[1U]; + __Vtemp568[2U] = vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__0__KET____DOT__bank_structure.__PVT__data_structures__DOT__data_write_per_way[2U]; + __Vtemp568[3U] = vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__0__KET____DOT__bank_structure.__PVT__data_structures__DOT__data_write_per_way[3U]; + vcdp->chgArray(c+430,(__Vtemp568),128); + vcdp->chgBit(c+434,(vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__0__KET____DOT__bank_structure.data_structures__DOT____Vcellout__each_way__BRA__0__KET____DOT__data_structures__dirty_use)); + vcdp->chgBit(c+435,((0U != (0xffffU & vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__0__KET____DOT__bank_structure.__PVT__data_structures__DOT__we_per_way)))); + vcdp->chgBit(c+436,((1U & (((~ (IData)(vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__0__KET____DOT__bank_structure.data_structures__DOT____Vcellout__each_way__BRA__0__KET____DOT__data_structures__dirty_use)) + & (0U != (0xffffU + & vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__0__KET____DOT__bank_structure.__PVT__data_structures__DOT__we_per_way))) + | (IData)(vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__0__KET____DOT__bank_structure.__PVT__data_structures__DOT__write_from_mem_per_way))))); + vcdp->chgBit(c+437,(((1U & (IData)(vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__0__KET____DOT__bank_structure.__PVT__data_structures__DOT__write_from_mem_per_way)) + ? 0U : (1U & (0U != (0xffffU + & vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__0__KET____DOT__bank_structure.__PVT__data_structures__DOT__we_per_way)))))); + vcdp->chgBus(c+438,((0xffffU & (vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__0__KET____DOT__bank_structure.__PVT__data_structures__DOT__we_per_way + >> 0x10U))),16); + vcdp->chgBit(c+439,((1U & ((IData)(vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__0__KET____DOT__bank_structure.__PVT__data_structures__DOT__write_from_mem_per_way) + >> 1U)))); + __Vtemp569[0U] = vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__0__KET____DOT__bank_structure.__PVT__data_structures__DOT__data_write_per_way[4U]; + __Vtemp569[1U] = vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__0__KET____DOT__bank_structure.__PVT__data_structures__DOT__data_write_per_way[5U]; + __Vtemp569[2U] = vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__0__KET____DOT__bank_structure.__PVT__data_structures__DOT__data_write_per_way[6U]; + __Vtemp569[3U] = vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__0__KET____DOT__bank_structure.__PVT__data_structures__DOT__data_write_per_way[7U]; + vcdp->chgArray(c+440,(__Vtemp569),128); + vcdp->chgBit(c+444,(vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__0__KET____DOT__bank_structure.data_structures__DOT____Vcellout__each_way__BRA__1__KET____DOT__data_structures__dirty_use)); + vcdp->chgBit(c+445,((0U != (0xffffU & (vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__0__KET____DOT__bank_structure.__PVT__data_structures__DOT__we_per_way + >> 0x10U))))); + vcdp->chgBit(c+446,((1U & (((~ (IData)(vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__0__KET____DOT__bank_structure.data_structures__DOT____Vcellout__each_way__BRA__1__KET____DOT__data_structures__dirty_use)) + & (0U != (0xffffU + & (vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__0__KET____DOT__bank_structure.__PVT__data_structures__DOT__we_per_way + >> 0x10U)))) + | ((IData)(vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__0__KET____DOT__bank_structure.__PVT__data_structures__DOT__write_from_mem_per_way) + >> 1U))))); + vcdp->chgBit(c+447,(((2U & (IData)(vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__0__KET____DOT__bank_structure.__PVT__data_structures__DOT__write_from_mem_per_way)) + ? 0U : (1U & (0U != (0xffffU + & (vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__0__KET____DOT__bank_structure.__PVT__data_structures__DOT__we_per_way + >> 0x10U))))))); + __Vtemp570[0U] = 0U; + __Vtemp570[1U] = 0U; + __Vtemp570[2U] = 0U; + __Vtemp570[3U] = 0U; + vcdp->chgBus(c+448,(__Vtemp570[(3U & ((IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT__index_per_bank) + >> 2U))]),32); + vcdp->chgBus(c+449,(((IData)(vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__1__KET____DOT__bank_structure.__PVT__access) + ? ((0U == (IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__cache_driver_in_mem_read)) + ? ((0x80U & vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__1__KET____DOT__bank_structure.__PVT__data_unQual) + ? (0xffffff00U + | vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__1__KET____DOT__bank_structure.__PVT__data_unQual) + : (0xffU & vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__1__KET____DOT__bank_structure.__PVT__data_unQual)) + : ((1U == (IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__cache_driver_in_mem_read)) + ? ((0x8000U & vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__1__KET____DOT__bank_structure.__PVT__data_unQual) + ? (0xffff0000U + | vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__1__KET____DOT__bank_structure.__PVT__data_unQual) + : (0xffffU + & vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__1__KET____DOT__bank_structure.__PVT__data_unQual)) + : ((5U == (IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__cache_driver_in_mem_read)) + ? (0xffffU + & vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__1__KET____DOT__bank_structure.__PVT__data_unQual) + : ((4U == (IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__cache_driver_in_mem_read)) + ? (0xffU + & vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__1__KET____DOT__bank_structure.__PVT__data_unQual) + : vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__1__KET____DOT__bank_structure.__PVT__data_unQual)))) + : 0U)),32); + vcdp->chgBit(c+450,((((IData)(vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__1__KET____DOT__bank_structure.__PVT__access) + & (vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__1__KET____DOT__bank_structure.__PVT__tag_use + == (0x1fffffU & (vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__1__KET____DOT__bank_addr + >> 0xbU)))) + & (IData)(vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__1__KET____DOT__bank_structure.__PVT__valid_use)))); + vcdp->chgBit(c+451,((1U & ((IData)(vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__1__KET____DOT__bank_structure.__PVT__data_structures__DOT__dirty_use_per_way) + >> (IData)(vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__1__KET____DOT__bank_structure.__PVT__data_structures__DOT__way_use_Qual))))); + vcdp->chgBus(c+452,(((vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__1__KET____DOT__bank_structure.__PVT__tag_use + << 0xbU) | (0x7c0U & vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__1__KET____DOT__bank_addr))),32); + vcdp->chgArray(c+453,(vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__1__KET____DOT__bank_structure.__Vcellout__data_structures__data_use),128); + vcdp->chgBus(c+457,(vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__1__KET____DOT__bank_structure.__PVT__tag_use),21); + vcdp->chgBit(c+458,(vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__1__KET____DOT__bank_structure.__PVT__valid_use)); + vcdp->chgBit(c+459,(vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__1__KET____DOT__bank_structure.__PVT__access)); + vcdp->chgBit(c+460,(vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__1__KET____DOT__bank_structure.__PVT__write_from_mem)); + vcdp->chgBit(c+461,(vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__1__KET____DOT__bank_structure.__PVT__miss)); + vcdp->chgBit(c+462,((0U == (3U & vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__1__KET____DOT__bank_addr)))); + vcdp->chgBit(c+463,((1U == (3U & vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__1__KET____DOT__bank_addr)))); + vcdp->chgBit(c+464,((2U == (3U & vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__1__KET____DOT__bank_addr)))); + vcdp->chgBit(c+465,((3U == (3U & vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__1__KET____DOT__bank_addr)))); + vcdp->chgBus(c+466,(vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__1__KET____DOT__bank_structure.__PVT__data_unQual),32); + vcdp->chgBus(c+467,(((0x80U & vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__1__KET____DOT__bank_structure.__PVT__data_unQual) + ? (0xffffff00U | vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__1__KET____DOT__bank_structure.__PVT__data_unQual) + : (0xffU & vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__1__KET____DOT__bank_structure.__PVT__data_unQual))),32); + vcdp->chgBus(c+468,(((0x8000U & vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__1__KET____DOT__bank_structure.__PVT__data_unQual) + ? (0xffff0000U | vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__1__KET____DOT__bank_structure.__PVT__data_unQual) + : (0xffffU & vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__1__KET____DOT__bank_structure.__PVT__data_unQual))),32); + vcdp->chgBus(c+469,((0xffU & vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__1__KET____DOT__bank_structure.__PVT__data_unQual)),32); + vcdp->chgBus(c+470,((0xffffU & vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__1__KET____DOT__bank_structure.__PVT__data_unQual)),32); + __Vtemp571[0U] = 0U; + __Vtemp571[1U] = 0U; + __Vtemp571[2U] = 0U; + __Vtemp571[3U] = 0U; + __Vtemp572[0U] = 0U; + __Vtemp572[1U] = 0U; + __Vtemp572[2U] = 0U; + __Vtemp572[3U] = 0U; + __Vtemp573[0U] = 0U; + __Vtemp573[1U] = 0U; + __Vtemp573[2U] = 0U; + __Vtemp573[3U] = 0U; + __Vtemp574[0U] = 0U; + __Vtemp574[1U] = 0U; + __Vtemp574[2U] = 0U; + __Vtemp574[3U] = 0U; + vcdp->chgBus(c+471,(((1U == (3U & vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__1__KET____DOT__bank_addr)) + ? (0xff00U & (__Vtemp571[ + (3U & ((IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT__index_per_bank) + >> 2U))] + << 8U)) + : ((2U == (3U & vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__1__KET____DOT__bank_addr)) + ? (0xff0000U & (__Vtemp572[ + (3U + & ((IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT__index_per_bank) + >> 2U))] + << 0x10U)) + : ((3U == (3U & vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__1__KET____DOT__bank_addr)) + ? (0xff000000U + & (__Vtemp573[ + (3U & ((IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT__index_per_bank) + >> 2U))] + << 0x18U)) + : __Vtemp574[ + (3U & ((IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT__index_per_bank) + >> 2U))])))),32); + __Vtemp575[0U] = 0U; + __Vtemp575[1U] = 0U; + __Vtemp575[2U] = 0U; + __Vtemp575[3U] = 0U; + __Vtemp576[0U] = 0U; + __Vtemp576[1U] = 0U; + __Vtemp576[2U] = 0U; + __Vtemp576[3U] = 0U; + vcdp->chgBus(c+472,(((2U == (3U & vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__1__KET____DOT__bank_addr)) + ? (0xffff0000U & (__Vtemp575[ + (3U + & ((IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT__index_per_bank) + >> 2U))] + << 0x10U)) + : __Vtemp576[(3U & ((IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT__index_per_bank) + >> 2U))])),32); + vcdp->chgBus(c+473,(vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__1__KET____DOT__bank_structure.__PVT__use_write_data),32); + vcdp->chgBus(c+474,(((0U == (IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__cache_driver_in_mem_read)) + ? ((0x80U & vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__1__KET____DOT__bank_structure.__PVT__data_unQual) + ? (0xffffff00U | vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__1__KET____DOT__bank_structure.__PVT__data_unQual) + : (0xffU & vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__1__KET____DOT__bank_structure.__PVT__data_unQual)) + : ((1U == (IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__cache_driver_in_mem_read)) + ? ((0x8000U & vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__1__KET____DOT__bank_structure.__PVT__data_unQual) + ? (0xffff0000U + | vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__1__KET____DOT__bank_structure.__PVT__data_unQual) + : (0xffffU & vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__1__KET____DOT__bank_structure.__PVT__data_unQual)) + : ((5U == (IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__cache_driver_in_mem_read)) + ? (0xffffU & vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__1__KET____DOT__bank_structure.__PVT__data_unQual) + : ((4U == (IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__cache_driver_in_mem_read)) + ? (0xffU + & vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__1__KET____DOT__bank_structure.__PVT__data_unQual) + : vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__1__KET____DOT__bank_structure.__PVT__data_unQual))))),32); + vcdp->chgBus(c+475,(vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__1__KET____DOT__bank_structure.__PVT__sb_mask),4); + vcdp->chgBus(c+476,(((0U == (3U & vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__1__KET____DOT__bank_addr)) + ? 3U : 0xcU)),4); + vcdp->chgBus(c+477,(vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__1__KET____DOT__bank_structure.__PVT__we),16); + vcdp->chgArray(c+478,(vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__1__KET____DOT__bank_structure.__PVT__data_write),128); + vcdp->chgBit(c+482,(vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__1__KET____DOT__bank_structure.__PVT__genblk1__BRA__0__KET____DOT__normal_write)); + vcdp->chgBit(c+483,(vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__1__KET____DOT__bank_structure.__PVT__genblk1__BRA__1__KET____DOT__normal_write)); + vcdp->chgBit(c+484,(vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__1__KET____DOT__bank_structure.__PVT__genblk1__BRA__2__KET____DOT__normal_write)); + vcdp->chgBit(c+485,(vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__1__KET____DOT__bank_structure.__PVT__genblk1__BRA__3__KET____DOT__normal_write)); + vcdp->chgQuad(c+486,(vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__1__KET____DOT__bank_structure.__PVT__data_structures__DOT__tag_use_per_way),42); + vcdp->chgArray(c+488,(vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__1__KET____DOT__bank_structure.__PVT__data_structures__DOT__data_use_per_way),256); + vcdp->chgBus(c+496,(vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__1__KET____DOT__bank_structure.__PVT__data_structures__DOT__valid_use_per_way),2); + vcdp->chgBus(c+497,(vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__1__KET____DOT__bank_structure.__PVT__data_structures__DOT__dirty_use_per_way),2); + vcdp->chgBus(c+498,(vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__1__KET____DOT__bank_structure.__PVT__data_structures__DOT__hit_per_way),2); + vcdp->chgBus(c+499,(vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__1__KET____DOT__bank_structure.__PVT__data_structures__DOT__we_per_way),32); + vcdp->chgArray(c+500,(vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__1__KET____DOT__bank_structure.__PVT__data_structures__DOT__data_write_per_way),256); + vcdp->chgBus(c+508,(vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__1__KET____DOT__bank_structure.__PVT__data_structures__DOT__write_from_mem_per_way),2); + vcdp->chgBit(c+509,(vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__1__KET____DOT__bank_structure.__PVT__data_structures__DOT__invalid_found)); + vcdp->chgBit(c+510,(vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__1__KET____DOT__bank_structure.__PVT__data_structures__DOT__way_index)); + vcdp->chgBit(c+511,(vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__1__KET____DOT__bank_structure.__PVT__data_structures__DOT__invalid_index)); + vcdp->chgBit(c+512,(vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__1__KET____DOT__bank_structure.__PVT__data_structures__DOT__way_use_Qual)); + vcdp->chgBus(c+513,((3U & (~ (IData)(vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__1__KET____DOT__bank_structure.__PVT__data_structures__DOT__valid_use_per_way)))),2); + vcdp->chgBit(c+514,(vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__1__KET____DOT__bank_structure.__PVT__data_structures__DOT__genblk1__DOT__way_indexing__DOT__found)); + vcdp->chgBus(c+515,((0xffffU & vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__1__KET____DOT__bank_structure.__PVT__data_structures__DOT__we_per_way)),16); + vcdp->chgBit(c+516,((1U & (IData)(vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__1__KET____DOT__bank_structure.__PVT__data_structures__DOT__write_from_mem_per_way)))); + __Vtemp577[0U] = vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__1__KET____DOT__bank_structure.__PVT__data_structures__DOT__data_write_per_way[0U]; + __Vtemp577[1U] = vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__1__KET____DOT__bank_structure.__PVT__data_structures__DOT__data_write_per_way[1U]; + __Vtemp577[2U] = vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__1__KET____DOT__bank_structure.__PVT__data_structures__DOT__data_write_per_way[2U]; + __Vtemp577[3U] = vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__1__KET____DOT__bank_structure.__PVT__data_structures__DOT__data_write_per_way[3U]; + vcdp->chgArray(c+517,(__Vtemp577),128); + vcdp->chgBit(c+521,(vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__1__KET____DOT__bank_structure.data_structures__DOT____Vcellout__each_way__BRA__0__KET____DOT__data_structures__dirty_use)); + vcdp->chgBit(c+522,((0U != (0xffffU & vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__1__KET____DOT__bank_structure.__PVT__data_structures__DOT__we_per_way)))); + vcdp->chgBit(c+523,((1U & (((~ (IData)(vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__1__KET____DOT__bank_structure.data_structures__DOT____Vcellout__each_way__BRA__0__KET____DOT__data_structures__dirty_use)) + & (0U != (0xffffU + & vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__1__KET____DOT__bank_structure.__PVT__data_structures__DOT__we_per_way))) + | (IData)(vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__1__KET____DOT__bank_structure.__PVT__data_structures__DOT__write_from_mem_per_way))))); + vcdp->chgBit(c+524,(((1U & (IData)(vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__1__KET____DOT__bank_structure.__PVT__data_structures__DOT__write_from_mem_per_way)) + ? 0U : (1U & (0U != (0xffffU + & vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__1__KET____DOT__bank_structure.__PVT__data_structures__DOT__we_per_way)))))); + vcdp->chgBus(c+525,((0xffffU & (vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__1__KET____DOT__bank_structure.__PVT__data_structures__DOT__we_per_way + >> 0x10U))),16); + vcdp->chgBit(c+526,((1U & ((IData)(vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__1__KET____DOT__bank_structure.__PVT__data_structures__DOT__write_from_mem_per_way) + >> 1U)))); + __Vtemp578[0U] = vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__1__KET____DOT__bank_structure.__PVT__data_structures__DOT__data_write_per_way[4U]; + __Vtemp578[1U] = vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__1__KET____DOT__bank_structure.__PVT__data_structures__DOT__data_write_per_way[5U]; + __Vtemp578[2U] = vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__1__KET____DOT__bank_structure.__PVT__data_structures__DOT__data_write_per_way[6U]; + __Vtemp578[3U] = vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__1__KET____DOT__bank_structure.__PVT__data_structures__DOT__data_write_per_way[7U]; + vcdp->chgArray(c+527,(__Vtemp578),128); + vcdp->chgBit(c+531,(vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__1__KET____DOT__bank_structure.data_structures__DOT____Vcellout__each_way__BRA__1__KET____DOT__data_structures__dirty_use)); + vcdp->chgBit(c+532,((0U != (0xffffU & (vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__1__KET____DOT__bank_structure.__PVT__data_structures__DOT__we_per_way + >> 0x10U))))); + vcdp->chgBit(c+533,((1U & (((~ (IData)(vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__1__KET____DOT__bank_structure.data_structures__DOT____Vcellout__each_way__BRA__1__KET____DOT__data_structures__dirty_use)) + & (0U != (0xffffU + & (vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__1__KET____DOT__bank_structure.__PVT__data_structures__DOT__we_per_way + >> 0x10U)))) + | ((IData)(vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__1__KET____DOT__bank_structure.__PVT__data_structures__DOT__write_from_mem_per_way) + >> 1U))))); + vcdp->chgBit(c+534,(((2U & (IData)(vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__1__KET____DOT__bank_structure.__PVT__data_structures__DOT__write_from_mem_per_way)) + ? 0U : (1U & (0U != (0xffffU + & (vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__1__KET____DOT__bank_structure.__PVT__data_structures__DOT__we_per_way + >> 0x10U))))))); + __Vtemp579[0U] = 0U; + __Vtemp579[1U] = 0U; + __Vtemp579[2U] = 0U; + __Vtemp579[3U] = 0U; + vcdp->chgBus(c+535,(__Vtemp579[(3U & ((IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT__index_per_bank) + >> 4U))]),32); + vcdp->chgBus(c+536,(((IData)(vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__2__KET____DOT__bank_structure.__PVT__access) + ? ((0U == (IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__cache_driver_in_mem_read)) + ? ((0x80U & vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__2__KET____DOT__bank_structure.__PVT__data_unQual) + ? (0xffffff00U + | vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__2__KET____DOT__bank_structure.__PVT__data_unQual) + : (0xffU & vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__2__KET____DOT__bank_structure.__PVT__data_unQual)) + : ((1U == (IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__cache_driver_in_mem_read)) + ? ((0x8000U & vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__2__KET____DOT__bank_structure.__PVT__data_unQual) + ? (0xffff0000U + | vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__2__KET____DOT__bank_structure.__PVT__data_unQual) + : (0xffffU + & vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__2__KET____DOT__bank_structure.__PVT__data_unQual)) + : ((5U == (IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__cache_driver_in_mem_read)) + ? (0xffffU + & vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__2__KET____DOT__bank_structure.__PVT__data_unQual) + : ((4U == (IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__cache_driver_in_mem_read)) + ? (0xffU + & vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__2__KET____DOT__bank_structure.__PVT__data_unQual) + : vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__2__KET____DOT__bank_structure.__PVT__data_unQual)))) + : 0U)),32); + vcdp->chgBit(c+537,((((IData)(vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__2__KET____DOT__bank_structure.__PVT__access) + & (vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__2__KET____DOT__bank_structure.__PVT__tag_use + == (0x1fffffU & (vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__2__KET____DOT__bank_addr + >> 0xbU)))) + & (IData)(vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__2__KET____DOT__bank_structure.__PVT__valid_use)))); + vcdp->chgBit(c+538,((1U & ((IData)(vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__2__KET____DOT__bank_structure.__PVT__data_structures__DOT__dirty_use_per_way) + >> (IData)(vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__2__KET____DOT__bank_structure.__PVT__data_structures__DOT__way_use_Qual))))); + vcdp->chgBus(c+539,(((vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__2__KET____DOT__bank_structure.__PVT__tag_use + << 0xbU) | (0x7c0U & vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__2__KET____DOT__bank_addr))),32); + vcdp->chgArray(c+540,(vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__2__KET____DOT__bank_structure.__Vcellout__data_structures__data_use),128); + vcdp->chgBus(c+544,(vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__2__KET____DOT__bank_structure.__PVT__tag_use),21); + vcdp->chgBit(c+545,(vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__2__KET____DOT__bank_structure.__PVT__valid_use)); + vcdp->chgBit(c+546,(vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__2__KET____DOT__bank_structure.__PVT__access)); + vcdp->chgBit(c+547,(vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__2__KET____DOT__bank_structure.__PVT__write_from_mem)); + vcdp->chgBit(c+548,(vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__2__KET____DOT__bank_structure.__PVT__miss)); + vcdp->chgBit(c+549,((0U == (3U & vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__2__KET____DOT__bank_addr)))); + vcdp->chgBit(c+550,((1U == (3U & vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__2__KET____DOT__bank_addr)))); + vcdp->chgBit(c+551,((2U == (3U & vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__2__KET____DOT__bank_addr)))); + vcdp->chgBit(c+552,((3U == (3U & vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__2__KET____DOT__bank_addr)))); + vcdp->chgBus(c+553,(vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__2__KET____DOT__bank_structure.__PVT__data_unQual),32); + vcdp->chgBus(c+554,(((0x80U & vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__2__KET____DOT__bank_structure.__PVT__data_unQual) + ? (0xffffff00U | vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__2__KET____DOT__bank_structure.__PVT__data_unQual) + : (0xffU & vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__2__KET____DOT__bank_structure.__PVT__data_unQual))),32); + vcdp->chgBus(c+555,(((0x8000U & vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__2__KET____DOT__bank_structure.__PVT__data_unQual) + ? (0xffff0000U | vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__2__KET____DOT__bank_structure.__PVT__data_unQual) + : (0xffffU & vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__2__KET____DOT__bank_structure.__PVT__data_unQual))),32); + vcdp->chgBus(c+556,((0xffU & vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__2__KET____DOT__bank_structure.__PVT__data_unQual)),32); + vcdp->chgBus(c+557,((0xffffU & vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__2__KET____DOT__bank_structure.__PVT__data_unQual)),32); + __Vtemp580[0U] = 0U; + __Vtemp580[1U] = 0U; + __Vtemp580[2U] = 0U; + __Vtemp580[3U] = 0U; + __Vtemp581[0U] = 0U; + __Vtemp581[1U] = 0U; + __Vtemp581[2U] = 0U; + __Vtemp581[3U] = 0U; + __Vtemp582[0U] = 0U; + __Vtemp582[1U] = 0U; + __Vtemp582[2U] = 0U; + __Vtemp582[3U] = 0U; + __Vtemp583[0U] = 0U; + __Vtemp583[1U] = 0U; + __Vtemp583[2U] = 0U; + __Vtemp583[3U] = 0U; + vcdp->chgBus(c+558,(((1U == (3U & vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__2__KET____DOT__bank_addr)) + ? (0xff00U & (__Vtemp580[ + (3U & ((IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT__index_per_bank) + >> 4U))] + << 8U)) + : ((2U == (3U & vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__2__KET____DOT__bank_addr)) + ? (0xff0000U & (__Vtemp581[ + (3U + & ((IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT__index_per_bank) + >> 4U))] + << 0x10U)) + : ((3U == (3U & vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__2__KET____DOT__bank_addr)) + ? (0xff000000U + & (__Vtemp582[ + (3U & ((IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT__index_per_bank) + >> 4U))] + << 0x18U)) + : __Vtemp583[ + (3U & ((IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT__index_per_bank) + >> 4U))])))),32); + __Vtemp584[0U] = 0U; + __Vtemp584[1U] = 0U; + __Vtemp584[2U] = 0U; + __Vtemp584[3U] = 0U; + __Vtemp585[0U] = 0U; + __Vtemp585[1U] = 0U; + __Vtemp585[2U] = 0U; + __Vtemp585[3U] = 0U; + vcdp->chgBus(c+559,(((2U == (3U & vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__2__KET____DOT__bank_addr)) + ? (0xffff0000U & (__Vtemp584[ + (3U + & ((IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT__index_per_bank) + >> 4U))] + << 0x10U)) + : __Vtemp585[(3U & ((IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT__index_per_bank) + >> 4U))])),32); + vcdp->chgBus(c+560,(vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__2__KET____DOT__bank_structure.__PVT__use_write_data),32); + vcdp->chgBus(c+561,(((0U == (IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__cache_driver_in_mem_read)) + ? ((0x80U & vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__2__KET____DOT__bank_structure.__PVT__data_unQual) + ? (0xffffff00U | vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__2__KET____DOT__bank_structure.__PVT__data_unQual) + : (0xffU & vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__2__KET____DOT__bank_structure.__PVT__data_unQual)) + : ((1U == (IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__cache_driver_in_mem_read)) + ? ((0x8000U & vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__2__KET____DOT__bank_structure.__PVT__data_unQual) + ? (0xffff0000U + | vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__2__KET____DOT__bank_structure.__PVT__data_unQual) + : (0xffffU & vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__2__KET____DOT__bank_structure.__PVT__data_unQual)) + : ((5U == (IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__cache_driver_in_mem_read)) + ? (0xffffU & vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__2__KET____DOT__bank_structure.__PVT__data_unQual) + : ((4U == (IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__cache_driver_in_mem_read)) + ? (0xffU + & vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__2__KET____DOT__bank_structure.__PVT__data_unQual) + : vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__2__KET____DOT__bank_structure.__PVT__data_unQual))))),32); + vcdp->chgBus(c+562,(vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__2__KET____DOT__bank_structure.__PVT__sb_mask),4); + vcdp->chgBus(c+563,(((0U == (3U & vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__2__KET____DOT__bank_addr)) + ? 3U : 0xcU)),4); + vcdp->chgBus(c+564,(vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__2__KET____DOT__bank_structure.__PVT__we),16); + vcdp->chgArray(c+565,(vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__2__KET____DOT__bank_structure.__PVT__data_write),128); + vcdp->chgBit(c+569,(vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__2__KET____DOT__bank_structure.__PVT__genblk1__BRA__0__KET____DOT__normal_write)); + vcdp->chgBit(c+570,(vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__2__KET____DOT__bank_structure.__PVT__genblk1__BRA__1__KET____DOT__normal_write)); + vcdp->chgBit(c+571,(vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__2__KET____DOT__bank_structure.__PVT__genblk1__BRA__2__KET____DOT__normal_write)); + vcdp->chgBit(c+572,(vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__2__KET____DOT__bank_structure.__PVT__genblk1__BRA__3__KET____DOT__normal_write)); + vcdp->chgQuad(c+573,(vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__2__KET____DOT__bank_structure.__PVT__data_structures__DOT__tag_use_per_way),42); + vcdp->chgArray(c+575,(vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__2__KET____DOT__bank_structure.__PVT__data_structures__DOT__data_use_per_way),256); + vcdp->chgBus(c+583,(vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__2__KET____DOT__bank_structure.__PVT__data_structures__DOT__valid_use_per_way),2); + vcdp->chgBus(c+584,(vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__2__KET____DOT__bank_structure.__PVT__data_structures__DOT__dirty_use_per_way),2); + vcdp->chgBus(c+585,(vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__2__KET____DOT__bank_structure.__PVT__data_structures__DOT__hit_per_way),2); + vcdp->chgBus(c+586,(vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__2__KET____DOT__bank_structure.__PVT__data_structures__DOT__we_per_way),32); + vcdp->chgArray(c+587,(vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__2__KET____DOT__bank_structure.__PVT__data_structures__DOT__data_write_per_way),256); + vcdp->chgBus(c+595,(vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__2__KET____DOT__bank_structure.__PVT__data_structures__DOT__write_from_mem_per_way),2); + vcdp->chgBit(c+596,(vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__2__KET____DOT__bank_structure.__PVT__data_structures__DOT__invalid_found)); + vcdp->chgBit(c+597,(vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__2__KET____DOT__bank_structure.__PVT__data_structures__DOT__way_index)); + vcdp->chgBit(c+598,(vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__2__KET____DOT__bank_structure.__PVT__data_structures__DOT__invalid_index)); + vcdp->chgBit(c+599,(vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__2__KET____DOT__bank_structure.__PVT__data_structures__DOT__way_use_Qual)); + vcdp->chgBus(c+600,((3U & (~ (IData)(vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__2__KET____DOT__bank_structure.__PVT__data_structures__DOT__valid_use_per_way)))),2); + vcdp->chgBit(c+601,(vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__2__KET____DOT__bank_structure.__PVT__data_structures__DOT__genblk1__DOT__way_indexing__DOT__found)); + vcdp->chgBus(c+602,((0xffffU & vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__2__KET____DOT__bank_structure.__PVT__data_structures__DOT__we_per_way)),16); + vcdp->chgBit(c+603,((1U & (IData)(vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__2__KET____DOT__bank_structure.__PVT__data_structures__DOT__write_from_mem_per_way)))); + __Vtemp586[0U] = vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__2__KET____DOT__bank_structure.__PVT__data_structures__DOT__data_write_per_way[0U]; + __Vtemp586[1U] = vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__2__KET____DOT__bank_structure.__PVT__data_structures__DOT__data_write_per_way[1U]; + __Vtemp586[2U] = vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__2__KET____DOT__bank_structure.__PVT__data_structures__DOT__data_write_per_way[2U]; + __Vtemp586[3U] = vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__2__KET____DOT__bank_structure.__PVT__data_structures__DOT__data_write_per_way[3U]; + vcdp->chgArray(c+604,(__Vtemp586),128); + vcdp->chgBit(c+608,(vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__2__KET____DOT__bank_structure.data_structures__DOT____Vcellout__each_way__BRA__0__KET____DOT__data_structures__dirty_use)); + vcdp->chgBit(c+609,((0U != (0xffffU & vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__2__KET____DOT__bank_structure.__PVT__data_structures__DOT__we_per_way)))); + vcdp->chgBit(c+610,((1U & (((~ (IData)(vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__2__KET____DOT__bank_structure.data_structures__DOT____Vcellout__each_way__BRA__0__KET____DOT__data_structures__dirty_use)) + & (0U != (0xffffU + & vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__2__KET____DOT__bank_structure.__PVT__data_structures__DOT__we_per_way))) + | (IData)(vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__2__KET____DOT__bank_structure.__PVT__data_structures__DOT__write_from_mem_per_way))))); + vcdp->chgBit(c+611,(((1U & (IData)(vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__2__KET____DOT__bank_structure.__PVT__data_structures__DOT__write_from_mem_per_way)) + ? 0U : (1U & (0U != (0xffffU + & vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__2__KET____DOT__bank_structure.__PVT__data_structures__DOT__we_per_way)))))); + vcdp->chgBus(c+612,((0xffffU & (vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__2__KET____DOT__bank_structure.__PVT__data_structures__DOT__we_per_way + >> 0x10U))),16); + vcdp->chgBit(c+613,((1U & ((IData)(vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__2__KET____DOT__bank_structure.__PVT__data_structures__DOT__write_from_mem_per_way) + >> 1U)))); + __Vtemp587[0U] = vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__2__KET____DOT__bank_structure.__PVT__data_structures__DOT__data_write_per_way[4U]; + __Vtemp587[1U] = vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__2__KET____DOT__bank_structure.__PVT__data_structures__DOT__data_write_per_way[5U]; + __Vtemp587[2U] = vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__2__KET____DOT__bank_structure.__PVT__data_structures__DOT__data_write_per_way[6U]; + __Vtemp587[3U] = vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__2__KET____DOT__bank_structure.__PVT__data_structures__DOT__data_write_per_way[7U]; + vcdp->chgArray(c+614,(__Vtemp587),128); + vcdp->chgBit(c+618,(vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__2__KET____DOT__bank_structure.data_structures__DOT____Vcellout__each_way__BRA__1__KET____DOT__data_structures__dirty_use)); + vcdp->chgBit(c+619,((0U != (0xffffU & (vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__2__KET____DOT__bank_structure.__PVT__data_structures__DOT__we_per_way + >> 0x10U))))); + vcdp->chgBit(c+620,((1U & (((~ (IData)(vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__2__KET____DOT__bank_structure.data_structures__DOT____Vcellout__each_way__BRA__1__KET____DOT__data_structures__dirty_use)) + & (0U != (0xffffU + & (vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__2__KET____DOT__bank_structure.__PVT__data_structures__DOT__we_per_way + >> 0x10U)))) + | ((IData)(vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__2__KET____DOT__bank_structure.__PVT__data_structures__DOT__write_from_mem_per_way) + >> 1U))))); + vcdp->chgBit(c+621,(((2U & (IData)(vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__2__KET____DOT__bank_structure.__PVT__data_structures__DOT__write_from_mem_per_way)) + ? 0U : (1U & (0U != (0xffffU + & (vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__2__KET____DOT__bank_structure.__PVT__data_structures__DOT__we_per_way + >> 0x10U))))))); + __Vtemp588[0U] = 0U; + __Vtemp588[1U] = 0U; + __Vtemp588[2U] = 0U; + __Vtemp588[3U] = 0U; + vcdp->chgBus(c+622,(__Vtemp588[(3U & ((IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT__index_per_bank) + >> 6U))]),32); + vcdp->chgBus(c+623,(((IData)(vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__3__KET____DOT__bank_structure.__PVT__access) + ? ((0U == (IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__cache_driver_in_mem_read)) + ? ((0x80U & vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__3__KET____DOT__bank_structure.__PVT__data_unQual) + ? (0xffffff00U + | vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__3__KET____DOT__bank_structure.__PVT__data_unQual) + : (0xffU & vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__3__KET____DOT__bank_structure.__PVT__data_unQual)) + : ((1U == (IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__cache_driver_in_mem_read)) + ? ((0x8000U & vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__3__KET____DOT__bank_structure.__PVT__data_unQual) + ? (0xffff0000U + | vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__3__KET____DOT__bank_structure.__PVT__data_unQual) + : (0xffffU + & vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__3__KET____DOT__bank_structure.__PVT__data_unQual)) + : ((5U == (IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__cache_driver_in_mem_read)) + ? (0xffffU + & vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__3__KET____DOT__bank_structure.__PVT__data_unQual) + : ((4U == (IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__cache_driver_in_mem_read)) + ? (0xffU + & vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__3__KET____DOT__bank_structure.__PVT__data_unQual) + : vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__3__KET____DOT__bank_structure.__PVT__data_unQual)))) + : 0U)),32); + vcdp->chgBit(c+624,((((IData)(vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__3__KET____DOT__bank_structure.__PVT__access) + & (vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__3__KET____DOT__bank_structure.__PVT__tag_use + == (0x1fffffU & (vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__3__KET____DOT__bank_addr + >> 0xbU)))) + & (IData)(vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__3__KET____DOT__bank_structure.__PVT__valid_use)))); + vcdp->chgBit(c+625,((1U & ((IData)(vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__3__KET____DOT__bank_structure.__PVT__data_structures__DOT__dirty_use_per_way) + >> (IData)(vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__3__KET____DOT__bank_structure.__PVT__data_structures__DOT__way_use_Qual))))); + vcdp->chgBus(c+626,(((vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__3__KET____DOT__bank_structure.__PVT__tag_use + << 0xbU) | (0x7c0U & vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__3__KET____DOT__bank_addr))),32); + vcdp->chgArray(c+627,(vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__3__KET____DOT__bank_structure.__Vcellout__data_structures__data_use),128); + vcdp->chgBus(c+631,(vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__3__KET____DOT__bank_structure.__PVT__tag_use),21); + vcdp->chgBit(c+632,(vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__3__KET____DOT__bank_structure.__PVT__valid_use)); + vcdp->chgBit(c+633,(vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__3__KET____DOT__bank_structure.__PVT__access)); + vcdp->chgBit(c+634,(vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__3__KET____DOT__bank_structure.__PVT__write_from_mem)); + vcdp->chgBit(c+635,(vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__3__KET____DOT__bank_structure.__PVT__miss)); + vcdp->chgBit(c+636,((0U == (3U & vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__3__KET____DOT__bank_addr)))); + vcdp->chgBit(c+637,((1U == (3U & vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__3__KET____DOT__bank_addr)))); + vcdp->chgBit(c+638,((2U == (3U & vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__3__KET____DOT__bank_addr)))); + vcdp->chgBit(c+639,((3U == (3U & vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__3__KET____DOT__bank_addr)))); + vcdp->chgBus(c+640,(vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__3__KET____DOT__bank_structure.__PVT__data_unQual),32); + vcdp->chgBus(c+641,(((0x80U & vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__3__KET____DOT__bank_structure.__PVT__data_unQual) + ? (0xffffff00U | vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__3__KET____DOT__bank_structure.__PVT__data_unQual) + : (0xffU & vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__3__KET____DOT__bank_structure.__PVT__data_unQual))),32); + vcdp->chgBus(c+642,(((0x8000U & vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__3__KET____DOT__bank_structure.__PVT__data_unQual) + ? (0xffff0000U | vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__3__KET____DOT__bank_structure.__PVT__data_unQual) + : (0xffffU & vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__3__KET____DOT__bank_structure.__PVT__data_unQual))),32); + vcdp->chgBus(c+643,((0xffU & vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__3__KET____DOT__bank_structure.__PVT__data_unQual)),32); + vcdp->chgBus(c+644,((0xffffU & vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__3__KET____DOT__bank_structure.__PVT__data_unQual)),32); + __Vtemp589[0U] = 0U; + __Vtemp589[1U] = 0U; + __Vtemp589[2U] = 0U; + __Vtemp589[3U] = 0U; + __Vtemp590[0U] = 0U; + __Vtemp590[1U] = 0U; + __Vtemp590[2U] = 0U; + __Vtemp590[3U] = 0U; + __Vtemp591[0U] = 0U; + __Vtemp591[1U] = 0U; + __Vtemp591[2U] = 0U; + __Vtemp591[3U] = 0U; + __Vtemp592[0U] = 0U; + __Vtemp592[1U] = 0U; + __Vtemp592[2U] = 0U; + __Vtemp592[3U] = 0U; + vcdp->chgBus(c+645,(((1U == (3U & vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__3__KET____DOT__bank_addr)) + ? (0xff00U & (__Vtemp589[ + (3U & ((IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT__index_per_bank) + >> 6U))] + << 8U)) + : ((2U == (3U & vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__3__KET____DOT__bank_addr)) + ? (0xff0000U & (__Vtemp590[ + (3U + & ((IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT__index_per_bank) + >> 6U))] + << 0x10U)) + : ((3U == (3U & vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__3__KET____DOT__bank_addr)) + ? (0xff000000U + & (__Vtemp591[ + (3U & ((IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT__index_per_bank) + >> 6U))] + << 0x18U)) + : __Vtemp592[ + (3U & ((IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT__index_per_bank) + >> 6U))])))),32); + __Vtemp593[0U] = 0U; + __Vtemp593[1U] = 0U; + __Vtemp593[2U] = 0U; + __Vtemp593[3U] = 0U; + __Vtemp594[0U] = 0U; + __Vtemp594[1U] = 0U; + __Vtemp594[2U] = 0U; + __Vtemp594[3U] = 0U; + vcdp->chgBus(c+646,(((2U == (3U & vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__3__KET____DOT__bank_addr)) + ? (0xffff0000U & (__Vtemp593[ + (3U + & ((IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT__index_per_bank) + >> 6U))] + << 0x10U)) + : __Vtemp594[(3U & ((IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT__index_per_bank) + >> 6U))])),32); + vcdp->chgBus(c+647,(vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__3__KET____DOT__bank_structure.__PVT__use_write_data),32); + vcdp->chgBus(c+648,(((0U == (IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__cache_driver_in_mem_read)) + ? ((0x80U & vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__3__KET____DOT__bank_structure.__PVT__data_unQual) + ? (0xffffff00U | vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__3__KET____DOT__bank_structure.__PVT__data_unQual) + : (0xffU & vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__3__KET____DOT__bank_structure.__PVT__data_unQual)) + : ((1U == (IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__cache_driver_in_mem_read)) + ? ((0x8000U & vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__3__KET____DOT__bank_structure.__PVT__data_unQual) + ? (0xffff0000U + | vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__3__KET____DOT__bank_structure.__PVT__data_unQual) + : (0xffffU & vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__3__KET____DOT__bank_structure.__PVT__data_unQual)) + : ((5U == (IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__cache_driver_in_mem_read)) + ? (0xffffU & vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__3__KET____DOT__bank_structure.__PVT__data_unQual) + : ((4U == (IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__cache_driver_in_mem_read)) + ? (0xffU + & vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__3__KET____DOT__bank_structure.__PVT__data_unQual) + : vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__3__KET____DOT__bank_structure.__PVT__data_unQual))))),32); + vcdp->chgBus(c+649,(vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__3__KET____DOT__bank_structure.__PVT__sb_mask),4); + vcdp->chgBus(c+650,(((0U == (3U & vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__3__KET____DOT__bank_addr)) + ? 3U : 0xcU)),4); + vcdp->chgBus(c+651,(vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__3__KET____DOT__bank_structure.__PVT__we),16); + vcdp->chgArray(c+652,(vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__3__KET____DOT__bank_structure.__PVT__data_write),128); + vcdp->chgBit(c+656,(vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__3__KET____DOT__bank_structure.__PVT__genblk1__BRA__0__KET____DOT__normal_write)); + vcdp->chgBit(c+657,(vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__3__KET____DOT__bank_structure.__PVT__genblk1__BRA__1__KET____DOT__normal_write)); + vcdp->chgBit(c+658,(vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__3__KET____DOT__bank_structure.__PVT__genblk1__BRA__2__KET____DOT__normal_write)); + vcdp->chgBit(c+659,(vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__3__KET____DOT__bank_structure.__PVT__genblk1__BRA__3__KET____DOT__normal_write)); + vcdp->chgQuad(c+660,(vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__3__KET____DOT__bank_structure.__PVT__data_structures__DOT__tag_use_per_way),42); + vcdp->chgArray(c+662,(vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__3__KET____DOT__bank_structure.__PVT__data_structures__DOT__data_use_per_way),256); + vcdp->chgBus(c+670,(vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__3__KET____DOT__bank_structure.__PVT__data_structures__DOT__valid_use_per_way),2); + vcdp->chgBus(c+671,(vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__3__KET____DOT__bank_structure.__PVT__data_structures__DOT__dirty_use_per_way),2); + vcdp->chgBus(c+672,(vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__3__KET____DOT__bank_structure.__PVT__data_structures__DOT__hit_per_way),2); + vcdp->chgBus(c+673,(vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__3__KET____DOT__bank_structure.__PVT__data_structures__DOT__we_per_way),32); + vcdp->chgArray(c+674,(vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__3__KET____DOT__bank_structure.__PVT__data_structures__DOT__data_write_per_way),256); + vcdp->chgBus(c+682,(vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__3__KET____DOT__bank_structure.__PVT__data_structures__DOT__write_from_mem_per_way),2); + vcdp->chgBit(c+683,(vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__3__KET____DOT__bank_structure.__PVT__data_structures__DOT__invalid_found)); + vcdp->chgBit(c+684,(vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__3__KET____DOT__bank_structure.__PVT__data_structures__DOT__way_index)); + vcdp->chgBit(c+685,(vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__3__KET____DOT__bank_structure.__PVT__data_structures__DOT__invalid_index)); + vcdp->chgBit(c+686,(vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__3__KET____DOT__bank_structure.__PVT__data_structures__DOT__way_use_Qual)); + vcdp->chgBus(c+687,((3U & (~ (IData)(vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__3__KET____DOT__bank_structure.__PVT__data_structures__DOT__valid_use_per_way)))),2); + vcdp->chgBit(c+688,(vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__3__KET____DOT__bank_structure.__PVT__data_structures__DOT__genblk1__DOT__way_indexing__DOT__found)); + vcdp->chgBus(c+689,((0xffffU & vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__3__KET____DOT__bank_structure.__PVT__data_structures__DOT__we_per_way)),16); + vcdp->chgBit(c+690,((1U & (IData)(vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__3__KET____DOT__bank_structure.__PVT__data_structures__DOT__write_from_mem_per_way)))); + __Vtemp595[0U] = vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__3__KET____DOT__bank_structure.__PVT__data_structures__DOT__data_write_per_way[0U]; + __Vtemp595[1U] = vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__3__KET____DOT__bank_structure.__PVT__data_structures__DOT__data_write_per_way[1U]; + __Vtemp595[2U] = vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__3__KET____DOT__bank_structure.__PVT__data_structures__DOT__data_write_per_way[2U]; + __Vtemp595[3U] = vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__3__KET____DOT__bank_structure.__PVT__data_structures__DOT__data_write_per_way[3U]; + vcdp->chgArray(c+691,(__Vtemp595),128); + vcdp->chgBit(c+695,(vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__3__KET____DOT__bank_structure.data_structures__DOT____Vcellout__each_way__BRA__0__KET____DOT__data_structures__dirty_use)); + vcdp->chgBit(c+696,((0U != (0xffffU & vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__3__KET____DOT__bank_structure.__PVT__data_structures__DOT__we_per_way)))); + vcdp->chgBit(c+697,((1U & (((~ (IData)(vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__3__KET____DOT__bank_structure.data_structures__DOT____Vcellout__each_way__BRA__0__KET____DOT__data_structures__dirty_use)) + & (0U != (0xffffU + & vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__3__KET____DOT__bank_structure.__PVT__data_structures__DOT__we_per_way))) + | (IData)(vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__3__KET____DOT__bank_structure.__PVT__data_structures__DOT__write_from_mem_per_way))))); + vcdp->chgBit(c+698,(((1U & (IData)(vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__3__KET____DOT__bank_structure.__PVT__data_structures__DOT__write_from_mem_per_way)) + ? 0U : (1U & (0U != (0xffffU + & vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__3__KET____DOT__bank_structure.__PVT__data_structures__DOT__we_per_way)))))); + vcdp->chgBus(c+699,((0xffffU & (vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__3__KET____DOT__bank_structure.__PVT__data_structures__DOT__we_per_way + >> 0x10U))),16); + vcdp->chgBit(c+700,((1U & ((IData)(vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__3__KET____DOT__bank_structure.__PVT__data_structures__DOT__write_from_mem_per_way) + >> 1U)))); + __Vtemp596[0U] = vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__3__KET____DOT__bank_structure.__PVT__data_structures__DOT__data_write_per_way[4U]; + __Vtemp596[1U] = vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__3__KET____DOT__bank_structure.__PVT__data_structures__DOT__data_write_per_way[5U]; + __Vtemp596[2U] = vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__3__KET____DOT__bank_structure.__PVT__data_structures__DOT__data_write_per_way[6U]; + __Vtemp596[3U] = vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__3__KET____DOT__bank_structure.__PVT__data_structures__DOT__data_write_per_way[7U]; + vcdp->chgArray(c+701,(__Vtemp596),128); + vcdp->chgBit(c+705,(vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__3__KET____DOT__bank_structure.data_structures__DOT____Vcellout__each_way__BRA__1__KET____DOT__data_structures__dirty_use)); + vcdp->chgBit(c+706,((0U != (0xffffU & (vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__3__KET____DOT__bank_structure.__PVT__data_structures__DOT__we_per_way + >> 0x10U))))); + vcdp->chgBit(c+707,((1U & (((~ (IData)(vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__3__KET____DOT__bank_structure.data_structures__DOT____Vcellout__each_way__BRA__1__KET____DOT__data_structures__dirty_use)) + & (0U != (0xffffU + & (vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__3__KET____DOT__bank_structure.__PVT__data_structures__DOT__we_per_way + >> 0x10U)))) + | ((IData)(vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__3__KET____DOT__bank_structure.__PVT__data_structures__DOT__write_from_mem_per_way) + >> 1U))))); + vcdp->chgBit(c+708,(((2U & (IData)(vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__3__KET____DOT__bank_structure.__PVT__data_structures__DOT__write_from_mem_per_way)) + ? 0U : (1U & (0U != (0xffffU + & (vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__3__KET____DOT__bank_structure.__PVT__data_structures__DOT__we_per_way + >> 0x10U))))))); + } +} + +void Vcache_simX::traceChgThis__3(Vcache_simX__Syms* __restrict vlSymsp, VerilatedVcd* vcdp, uint32_t code) { + Vcache_simX* __restrict vlTOPp VL_ATTR_UNUSED = vlSymsp->TOPp; + int c = code; + if (0 && vcdp && c) {} // Prevent unused + // Variables + WData/*7:0*/ __Vtemp609[4]; + WData/*7:0*/ __Vtemp610[4]; + WData/*7:0*/ __Vtemp611[4]; + WData/*7:0*/ __Vtemp612[4]; + WData/*7:0*/ __Vtemp613[4]; + WData/*7:0*/ __Vtemp614[4]; + WData/*7:0*/ __Vtemp615[4]; + WData/*7:0*/ __Vtemp616[4]; + WData/*7:0*/ __Vtemp617[4]; + WData/*7:0*/ __Vtemp618[4]; + WData/*31:0*/ __Vtemp599[4]; + WData/*31:0*/ __Vtemp602[4]; + WData/*31:0*/ __Vtemp605[4]; + WData/*31:0*/ __Vtemp608[4]; + // Body + { + vcdp->chgBit(c+709,(((1U == (IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT__state)) + & (0U != (IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT__eviction_wb))))); + vcdp->chgBit(c+710,(((1U == (IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__state)) + & ((IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__data_structures__DOT__dirty_use_per_way) + >> (IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__data_structures__DOT__way_use_Qual))))); + vcdp->chgBus(c+711,(((IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__threads_serviced_per_bank) + ? vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__new_final_data_read + : vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__final_data_read)),32); + vcdp->chgBit(c+712,(((IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__new_stored_valid) + | (0U != (IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__state))))); + vcdp->chgBit(c+713,(((0U != (IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__vx_priority_encoder_sm__DOT__more_than_one_valid)) + | ((0U != (IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT__new_stored_valid)) + | (0U != (IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT__state)))))); + vcdp->chgBit(c+714,(((0U != (IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT__new_stored_valid)) + | (0U != (IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT__state))))); + vcdp->chgBit(c+715,((1U & ((~ ((0U != (IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT__new_stored_valid)) + | (0U != (IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT__state)))) + & (IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__cache_driver_in_valid))))); + vcdp->chgBus(c+716,(((0U == (IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__vx_priority_encoder_sm__DOT__left_requests)) + ? ((IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__orig_in_valid) + & (~ (IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__vx_priority_encoder_sm__DOT__serviced_qual))) + : ((IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__vx_priority_encoder_sm__DOT__left_requests) + & (~ (IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__vx_priority_encoder_sm__DOT__serviced_qual))))),4); + __Vtemp599[0U] = ((IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__genblk2__BRA__0__KET____DOT__shm_write) + ? 0U : vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__genblk2__BRA__0__KET____DOT__vx_shared_memory_block__DOT__shared_memory + [(0x7fU & vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__block_addr)][0U]); + __Vtemp599[1U] = ((IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__genblk2__BRA__0__KET____DOT__shm_write) + ? 0U : vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__genblk2__BRA__0__KET____DOT__vx_shared_memory_block__DOT__shared_memory + [(0x7fU & vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__block_addr)][1U]); + __Vtemp599[2U] = ((IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__genblk2__BRA__0__KET____DOT__shm_write) + ? 0U : vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__genblk2__BRA__0__KET____DOT__vx_shared_memory_block__DOT__shared_memory + [(0x7fU & vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__block_addr)][2U]); + __Vtemp599[3U] = ((IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__genblk2__BRA__0__KET____DOT__shm_write) + ? 0U : vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__genblk2__BRA__0__KET____DOT__vx_shared_memory_block__DOT__shared_memory + [(0x7fU & vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__block_addr)][3U]); + vcdp->chgArray(c+717,(__Vtemp599),128); + __Vtemp602[0U] = ((IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__genblk2__BRA__1__KET____DOT__shm_write) + ? 0U : vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__genblk2__BRA__1__KET____DOT__vx_shared_memory_block__DOT__shared_memory + [(0x7fU & (vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__block_addr + >> 7U))][0U]); + __Vtemp602[1U] = ((IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__genblk2__BRA__1__KET____DOT__shm_write) + ? 0U : vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__genblk2__BRA__1__KET____DOT__vx_shared_memory_block__DOT__shared_memory + [(0x7fU & (vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__block_addr + >> 7U))][1U]); + __Vtemp602[2U] = ((IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__genblk2__BRA__1__KET____DOT__shm_write) + ? 0U : vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__genblk2__BRA__1__KET____DOT__vx_shared_memory_block__DOT__shared_memory + [(0x7fU & (vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__block_addr + >> 7U))][2U]); + __Vtemp602[3U] = ((IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__genblk2__BRA__1__KET____DOT__shm_write) + ? 0U : vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__genblk2__BRA__1__KET____DOT__vx_shared_memory_block__DOT__shared_memory + [(0x7fU & (vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__block_addr + >> 7U))][3U]); + vcdp->chgArray(c+721,(__Vtemp602),128); + __Vtemp605[0U] = ((IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__genblk2__BRA__2__KET____DOT__shm_write) + ? 0U : vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__genblk2__BRA__2__KET____DOT__vx_shared_memory_block__DOT__shared_memory + [(0x7fU & (vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__block_addr + >> 0xeU))][0U]); + __Vtemp605[1U] = ((IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__genblk2__BRA__2__KET____DOT__shm_write) + ? 0U : vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__genblk2__BRA__2__KET____DOT__vx_shared_memory_block__DOT__shared_memory + [(0x7fU & (vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__block_addr + >> 0xeU))][1U]); + __Vtemp605[2U] = ((IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__genblk2__BRA__2__KET____DOT__shm_write) + ? 0U : vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__genblk2__BRA__2__KET____DOT__vx_shared_memory_block__DOT__shared_memory + [(0x7fU & (vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__block_addr + >> 0xeU))][2U]); + __Vtemp605[3U] = ((IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__genblk2__BRA__2__KET____DOT__shm_write) + ? 0U : vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__genblk2__BRA__2__KET____DOT__vx_shared_memory_block__DOT__shared_memory + [(0x7fU & (vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__block_addr + >> 0xeU))][3U]); + vcdp->chgArray(c+725,(__Vtemp605),128); + __Vtemp608[0U] = ((IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__genblk2__BRA__3__KET____DOT__shm_write) + ? 0U : vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__genblk2__BRA__3__KET____DOT__vx_shared_memory_block__DOT__shared_memory + [(0x7fU & (vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__block_addr + >> 0x15U))][0U]); + __Vtemp608[1U] = ((IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__genblk2__BRA__3__KET____DOT__shm_write) + ? 0U : vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__genblk2__BRA__3__KET____DOT__vx_shared_memory_block__DOT__shared_memory + [(0x7fU & (vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__block_addr + >> 0x15U))][1U]); + __Vtemp608[2U] = ((IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__genblk2__BRA__3__KET____DOT__shm_write) + ? 0U : vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__genblk2__BRA__3__KET____DOT__vx_shared_memory_block__DOT__shared_memory + [(0x7fU & (vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__block_addr + >> 0x15U))][2U]); + __Vtemp608[3U] = ((IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__genblk2__BRA__3__KET____DOT__shm_write) + ? 0U : vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__genblk2__BRA__3__KET____DOT__vx_shared_memory_block__DOT__shared_memory + [(0x7fU & (vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__block_addr + >> 0x15U))][3U]); + vcdp->chgArray(c+729,(__Vtemp608),128); + vcdp->chgBit(c+733,(((2U == (IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT__state)) + & (0U == (IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT__new_state))))); + vcdp->chgBit(c+734,(((2U == (IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__state)) + & (0U == (IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__new_state))))); + vcdp->chgBus(c+735,(vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__tag + [(0x1fU & (vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_addr + >> 4U))]),23); + __Vtemp609[0U] = vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__data + [(0x1fU & (vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_addr + >> 4U))][0U]; + __Vtemp609[1U] = vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__data + [(0x1fU & (vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_addr + >> 4U))][1U]; + __Vtemp609[2U] = vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__data + [(0x1fU & (vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_addr + >> 4U))][2U]; + __Vtemp609[3U] = vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__data + [(0x1fU & (vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_addr + >> 4U))][3U]; + vcdp->chgArray(c+736,(__Vtemp609),128); + vcdp->chgBit(c+740,(vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__valid + [(0x1fU & (vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_addr + >> 4U))])); + vcdp->chgBus(c+741,(vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__data_structures__DOT__each_way__BRA__1__KET____DOT__data_structures__DOT__tag + [(0x1fU & (vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_addr + >> 4U))]),23); + __Vtemp610[0U] = vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__data_structures__DOT__each_way__BRA__1__KET____DOT__data_structures__DOT__data + [(0x1fU & (vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_addr + >> 4U))][0U]; + __Vtemp610[1U] = vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__data_structures__DOT__each_way__BRA__1__KET____DOT__data_structures__DOT__data + [(0x1fU & (vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_addr + >> 4U))][1U]; + __Vtemp610[2U] = vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__data_structures__DOT__each_way__BRA__1__KET____DOT__data_structures__DOT__data + [(0x1fU & (vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_addr + >> 4U))][2U]; + __Vtemp610[3U] = vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__data_structures__DOT__each_way__BRA__1__KET____DOT__data_structures__DOT__data + [(0x1fU & (vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_addr + >> 4U))][3U]; + vcdp->chgArray(c+742,(__Vtemp610),128); + vcdp->chgBit(c+746,(vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__data_structures__DOT__each_way__BRA__1__KET____DOT__data_structures__DOT__valid + [(0x1fU & (vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_addr + >> 4U))])); + vcdp->chgBus(c+747,(vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__0__KET____DOT__bank_structure.__PVT__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__tag + [(0x1fU & (vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__0__KET____DOT__bank_addr + >> 6U))]),21); + __Vtemp611[0U] = vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__0__KET____DOT__bank_structure.__PVT__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__data + [(0x1fU & (vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__0__KET____DOT__bank_addr + >> 6U))][0U]; + __Vtemp611[1U] = vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__0__KET____DOT__bank_structure.__PVT__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__data + [(0x1fU & (vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__0__KET____DOT__bank_addr + >> 6U))][1U]; + __Vtemp611[2U] = vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__0__KET____DOT__bank_structure.__PVT__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__data + [(0x1fU & (vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__0__KET____DOT__bank_addr + >> 6U))][2U]; + __Vtemp611[3U] = vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__0__KET____DOT__bank_structure.__PVT__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__data + [(0x1fU & (vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__0__KET____DOT__bank_addr + >> 6U))][3U]; + vcdp->chgArray(c+748,(__Vtemp611),128); + vcdp->chgBit(c+752,(vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__0__KET____DOT__bank_structure.__PVT__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__valid + [(0x1fU & (vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__0__KET____DOT__bank_addr + >> 6U))])); + vcdp->chgBus(c+753,(vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__0__KET____DOT__bank_structure.__PVT__data_structures__DOT__each_way__BRA__1__KET____DOT__data_structures__DOT__tag + [(0x1fU & (vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__0__KET____DOT__bank_addr + >> 6U))]),21); + __Vtemp612[0U] = vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__0__KET____DOT__bank_structure.__PVT__data_structures__DOT__each_way__BRA__1__KET____DOT__data_structures__DOT__data + [(0x1fU & (vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__0__KET____DOT__bank_addr + >> 6U))][0U]; + __Vtemp612[1U] = vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__0__KET____DOT__bank_structure.__PVT__data_structures__DOT__each_way__BRA__1__KET____DOT__data_structures__DOT__data + [(0x1fU & (vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__0__KET____DOT__bank_addr + >> 6U))][1U]; + __Vtemp612[2U] = vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__0__KET____DOT__bank_structure.__PVT__data_structures__DOT__each_way__BRA__1__KET____DOT__data_structures__DOT__data + [(0x1fU & (vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__0__KET____DOT__bank_addr + >> 6U))][2U]; + __Vtemp612[3U] = vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__0__KET____DOT__bank_structure.__PVT__data_structures__DOT__each_way__BRA__1__KET____DOT__data_structures__DOT__data + [(0x1fU & (vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__0__KET____DOT__bank_addr + >> 6U))][3U]; + vcdp->chgArray(c+754,(__Vtemp612),128); + vcdp->chgBit(c+758,(vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__0__KET____DOT__bank_structure.__PVT__data_structures__DOT__each_way__BRA__1__KET____DOT__data_structures__DOT__valid + [(0x1fU & (vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__0__KET____DOT__bank_addr + >> 6U))])); + vcdp->chgBus(c+759,(vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__1__KET____DOT__bank_structure.__PVT__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__tag + [(0x1fU & (vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__1__KET____DOT__bank_addr + >> 6U))]),21); + __Vtemp613[0U] = vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__1__KET____DOT__bank_structure.__PVT__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__data + [(0x1fU & (vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__1__KET____DOT__bank_addr + >> 6U))][0U]; + __Vtemp613[1U] = vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__1__KET____DOT__bank_structure.__PVT__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__data + [(0x1fU & (vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__1__KET____DOT__bank_addr + >> 6U))][1U]; + __Vtemp613[2U] = vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__1__KET____DOT__bank_structure.__PVT__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__data + [(0x1fU & (vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__1__KET____DOT__bank_addr + >> 6U))][2U]; + __Vtemp613[3U] = vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__1__KET____DOT__bank_structure.__PVT__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__data + [(0x1fU & (vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__1__KET____DOT__bank_addr + >> 6U))][3U]; + vcdp->chgArray(c+760,(__Vtemp613),128); + vcdp->chgBit(c+764,(vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__1__KET____DOT__bank_structure.__PVT__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__valid + [(0x1fU & (vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__1__KET____DOT__bank_addr + >> 6U))])); + vcdp->chgBus(c+765,(vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__1__KET____DOT__bank_structure.__PVT__data_structures__DOT__each_way__BRA__1__KET____DOT__data_structures__DOT__tag + [(0x1fU & (vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__1__KET____DOT__bank_addr + >> 6U))]),21); + __Vtemp614[0U] = vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__1__KET____DOT__bank_structure.__PVT__data_structures__DOT__each_way__BRA__1__KET____DOT__data_structures__DOT__data + [(0x1fU & (vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__1__KET____DOT__bank_addr + >> 6U))][0U]; + __Vtemp614[1U] = vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__1__KET____DOT__bank_structure.__PVT__data_structures__DOT__each_way__BRA__1__KET____DOT__data_structures__DOT__data + [(0x1fU & (vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__1__KET____DOT__bank_addr + >> 6U))][1U]; + __Vtemp614[2U] = vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__1__KET____DOT__bank_structure.__PVT__data_structures__DOT__each_way__BRA__1__KET____DOT__data_structures__DOT__data + [(0x1fU & (vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__1__KET____DOT__bank_addr + >> 6U))][2U]; + __Vtemp614[3U] = vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__1__KET____DOT__bank_structure.__PVT__data_structures__DOT__each_way__BRA__1__KET____DOT__data_structures__DOT__data + [(0x1fU & (vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__1__KET____DOT__bank_addr + >> 6U))][3U]; + vcdp->chgArray(c+766,(__Vtemp614),128); + vcdp->chgBit(c+770,(vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__1__KET____DOT__bank_structure.__PVT__data_structures__DOT__each_way__BRA__1__KET____DOT__data_structures__DOT__valid + [(0x1fU & (vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__1__KET____DOT__bank_addr + >> 6U))])); + vcdp->chgBus(c+771,(vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__2__KET____DOT__bank_structure.__PVT__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__tag + [(0x1fU & (vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__2__KET____DOT__bank_addr + >> 6U))]),21); + __Vtemp615[0U] = vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__2__KET____DOT__bank_structure.__PVT__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__data + [(0x1fU & (vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__2__KET____DOT__bank_addr + >> 6U))][0U]; + __Vtemp615[1U] = vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__2__KET____DOT__bank_structure.__PVT__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__data + [(0x1fU & (vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__2__KET____DOT__bank_addr + >> 6U))][1U]; + __Vtemp615[2U] = vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__2__KET____DOT__bank_structure.__PVT__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__data + [(0x1fU & (vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__2__KET____DOT__bank_addr + >> 6U))][2U]; + __Vtemp615[3U] = vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__2__KET____DOT__bank_structure.__PVT__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__data + [(0x1fU & (vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__2__KET____DOT__bank_addr + >> 6U))][3U]; + vcdp->chgArray(c+772,(__Vtemp615),128); + vcdp->chgBit(c+776,(vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__2__KET____DOT__bank_structure.__PVT__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__valid + [(0x1fU & (vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__2__KET____DOT__bank_addr + >> 6U))])); + vcdp->chgBus(c+777,(vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__2__KET____DOT__bank_structure.__PVT__data_structures__DOT__each_way__BRA__1__KET____DOT__data_structures__DOT__tag + [(0x1fU & (vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__2__KET____DOT__bank_addr + >> 6U))]),21); + __Vtemp616[0U] = vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__2__KET____DOT__bank_structure.__PVT__data_structures__DOT__each_way__BRA__1__KET____DOT__data_structures__DOT__data + [(0x1fU & (vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__2__KET____DOT__bank_addr + >> 6U))][0U]; + __Vtemp616[1U] = vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__2__KET____DOT__bank_structure.__PVT__data_structures__DOT__each_way__BRA__1__KET____DOT__data_structures__DOT__data + [(0x1fU & (vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__2__KET____DOT__bank_addr + >> 6U))][1U]; + __Vtemp616[2U] = vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__2__KET____DOT__bank_structure.__PVT__data_structures__DOT__each_way__BRA__1__KET____DOT__data_structures__DOT__data + [(0x1fU & (vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__2__KET____DOT__bank_addr + >> 6U))][2U]; + __Vtemp616[3U] = vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__2__KET____DOT__bank_structure.__PVT__data_structures__DOT__each_way__BRA__1__KET____DOT__data_structures__DOT__data + [(0x1fU & (vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__2__KET____DOT__bank_addr + >> 6U))][3U]; + vcdp->chgArray(c+778,(__Vtemp616),128); + vcdp->chgBit(c+782,(vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__2__KET____DOT__bank_structure.__PVT__data_structures__DOT__each_way__BRA__1__KET____DOT__data_structures__DOT__valid + [(0x1fU & (vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__2__KET____DOT__bank_addr + >> 6U))])); + vcdp->chgBus(c+783,(vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__3__KET____DOT__bank_structure.__PVT__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__tag + [(0x1fU & (vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__3__KET____DOT__bank_addr + >> 6U))]),21); + __Vtemp617[0U] = vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__3__KET____DOT__bank_structure.__PVT__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__data + [(0x1fU & (vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__3__KET____DOT__bank_addr + >> 6U))][0U]; + __Vtemp617[1U] = vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__3__KET____DOT__bank_structure.__PVT__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__data + [(0x1fU & (vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__3__KET____DOT__bank_addr + >> 6U))][1U]; + __Vtemp617[2U] = vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__3__KET____DOT__bank_structure.__PVT__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__data + [(0x1fU & (vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__3__KET____DOT__bank_addr + >> 6U))][2U]; + __Vtemp617[3U] = vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__3__KET____DOT__bank_structure.__PVT__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__data + [(0x1fU & (vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__3__KET____DOT__bank_addr + >> 6U))][3U]; + vcdp->chgArray(c+784,(__Vtemp617),128); + vcdp->chgBit(c+788,(vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__3__KET____DOT__bank_structure.__PVT__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__valid + [(0x1fU & (vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__3__KET____DOT__bank_addr + >> 6U))])); + vcdp->chgBus(c+789,(vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__3__KET____DOT__bank_structure.__PVT__data_structures__DOT__each_way__BRA__1__KET____DOT__data_structures__DOT__tag + [(0x1fU & (vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__3__KET____DOT__bank_addr + >> 6U))]),21); + __Vtemp618[0U] = vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__3__KET____DOT__bank_structure.__PVT__data_structures__DOT__each_way__BRA__1__KET____DOT__data_structures__DOT__data + [(0x1fU & (vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__3__KET____DOT__bank_addr + >> 6U))][0U]; + __Vtemp618[1U] = vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__3__KET____DOT__bank_structure.__PVT__data_structures__DOT__each_way__BRA__1__KET____DOT__data_structures__DOT__data + [(0x1fU & (vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__3__KET____DOT__bank_addr + >> 6U))][1U]; + __Vtemp618[2U] = vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__3__KET____DOT__bank_structure.__PVT__data_structures__DOT__each_way__BRA__1__KET____DOT__data_structures__DOT__data + [(0x1fU & (vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__3__KET____DOT__bank_addr + >> 6U))][2U]; + __Vtemp618[3U] = vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__3__KET____DOT__bank_structure.__PVT__data_structures__DOT__each_way__BRA__1__KET____DOT__data_structures__DOT__data + [(0x1fU & (vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__3__KET____DOT__bank_addr + >> 6U))][3U]; + vcdp->chgArray(c+790,(__Vtemp618),128); + vcdp->chgBit(c+794,(vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__3__KET____DOT__bank_structure.__PVT__data_structures__DOT__each_way__BRA__1__KET____DOT__data_structures__DOT__valid + [(0x1fU & (vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__3__KET____DOT__bank_addr + >> 6U))])); + } +} + +void Vcache_simX::traceChgThis__4(Vcache_simX__Syms* __restrict vlSymsp, VerilatedVcd* vcdp, uint32_t code) { + Vcache_simX* __restrict vlTOPp VL_ATTR_UNUSED = vlSymsp->TOPp; + int c = code; + if (0 && vcdp && c) {} // Prevent unused + // Body + { + vcdp->chgBit(c+795,(vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__way_to_update)); + vcdp->chgBit(c+796,(vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__0__KET____DOT__bank_structure.__PVT__way_to_update)); + vcdp->chgBit(c+797,(vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__1__KET____DOT__bank_structure.__PVT__way_to_update)); + vcdp->chgBit(c+798,(vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__2__KET____DOT__bank_structure.__PVT__way_to_update)); + vcdp->chgBit(c+799,(vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__3__KET____DOT__bank_structure.__PVT__way_to_update)); + } +} + +void Vcache_simX::traceChgThis__5(Vcache_simX__Syms* __restrict vlSymsp, VerilatedVcd* vcdp, uint32_t code) { + Vcache_simX* __restrict vlTOPp VL_ATTR_UNUSED = vlSymsp->TOPp; + int c = code; + if (0 && vcdp && c) {} // Prevent unused + // Variables + WData/*7:0*/ __Vtemp619[4]; + WData/*7:0*/ __Vtemp620[4]; + WData/*7:0*/ __Vtemp621[4]; + WData/*7:0*/ __Vtemp622[4]; + WData/*7:0*/ __Vtemp623[4]; + WData/*7:0*/ __Vtemp624[4]; + WData/*7:0*/ __Vtemp625[4]; + WData/*7:0*/ __Vtemp626[4]; + WData/*7:0*/ __Vtemp627[4]; + WData/*7:0*/ __Vtemp628[4]; + WData/*7:0*/ __Vtemp629[4]; + WData/*7:0*/ __Vtemp630[4]; + WData/*7:0*/ __Vtemp631[4]; + WData/*7:0*/ __Vtemp632[4]; + WData/*7:0*/ __Vtemp633[4]; + WData/*7:0*/ __Vtemp634[4]; + WData/*7:0*/ __Vtemp635[4]; + WData/*7:0*/ __Vtemp636[4]; + WData/*7:0*/ __Vtemp637[4]; + WData/*7:0*/ __Vtemp638[4]; + WData/*7:0*/ __Vtemp639[4]; + WData/*7:0*/ __Vtemp640[4]; + WData/*7:0*/ __Vtemp641[4]; + WData/*7:0*/ __Vtemp642[4]; + WData/*7:0*/ __Vtemp643[4]; + WData/*7:0*/ __Vtemp644[4]; + WData/*7:0*/ __Vtemp645[4]; + WData/*7:0*/ __Vtemp646[4]; + WData/*7:0*/ __Vtemp647[4]; + WData/*7:0*/ __Vtemp648[4]; + WData/*7:0*/ __Vtemp649[4]; + WData/*7:0*/ __Vtemp650[4]; + WData/*7:0*/ __Vtemp651[4]; + WData/*7:0*/ __Vtemp652[4]; + WData/*7:0*/ __Vtemp653[4]; + WData/*7:0*/ __Vtemp654[4]; + WData/*7:0*/ __Vtemp655[4]; + WData/*7:0*/ __Vtemp656[4]; + WData/*7:0*/ __Vtemp657[4]; + WData/*7:0*/ __Vtemp658[4]; + WData/*7:0*/ __Vtemp659[4]; + WData/*7:0*/ __Vtemp660[4]; + WData/*7:0*/ __Vtemp661[4]; + WData/*7:0*/ __Vtemp662[4]; + WData/*7:0*/ __Vtemp663[4]; + WData/*7:0*/ __Vtemp664[4]; + WData/*7:0*/ __Vtemp665[4]; + WData/*7:0*/ __Vtemp666[4]; + WData/*7:0*/ __Vtemp667[4]; + WData/*7:0*/ __Vtemp668[4]; + WData/*7:0*/ __Vtemp669[4]; + WData/*7:0*/ __Vtemp670[4]; + WData/*7:0*/ __Vtemp671[4]; + WData/*7:0*/ __Vtemp672[4]; + WData/*7:0*/ __Vtemp673[4]; + WData/*7:0*/ __Vtemp674[4]; + WData/*7:0*/ __Vtemp675[4]; + WData/*7:0*/ __Vtemp676[4]; + WData/*7:0*/ __Vtemp677[4]; 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+ vcdp->chgBus(c+804,((0xfffffff0U & vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__miss_addr)),32); + vcdp->chgBit(c+805,((1U == (IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__state)))); + vcdp->chgBus(c+806,(vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__vx_priority_encoder_sm__DOT__left_requests),4); + vcdp->chgBit(c+807,((0U != (IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__vx_priority_encoder_sm__DOT__left_requests)))); + vcdp->chgBus(c+808,(vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__genblk2__BRA__0__KET____DOT__vx_shared_memory_block__DOT__curr_ind),32); + vcdp->chgBus(c+809,(vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__genblk2__BRA__1__KET____DOT__vx_shared_memory_block__DOT__curr_ind),32); + vcdp->chgBus(c+810,(vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__genblk2__BRA__2__KET____DOT__vx_shared_memory_block__DOT__curr_ind),32); + vcdp->chgBus(c+811,(vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__genblk2__BRA__3__KET____DOT__vx_shared_memory_block__DOT__curr_ind),32); + vcdp->chgArray(c+812,(vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT__final_data_read),128); + vcdp->chgBit(c+816,(vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT__global_way_to_evict)); + vcdp->chgBus(c+817,(vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT__state),4); + vcdp->chgBus(c+818,(vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT__stored_valid),4); + vcdp->chgBus(c+819,(vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT__miss_addr),32); + vcdp->chgBus(c+820,(vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__final_data_read),32); + vcdp->chgBit(c+821,(vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__global_way_to_evict)); + vcdp->chgBus(c+822,(vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__state),4); + vcdp->chgBit(c+823,(vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__stored_valid)); + vcdp->chgBus(c+824,(vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__miss_addr),32); + __Vtemp619[0U] = vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__data + [0U][0U]; + __Vtemp619[1U] = vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__data + [0U][1U]; + __Vtemp619[2U] = vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__data + [0U][2U]; + __Vtemp619[3U] = vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__data + [0U][3U]; + vcdp->chgArray(c+825,(__Vtemp619),128); + __Vtemp620[0U] = vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__data + [1U][0U]; + __Vtemp620[1U] = vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__data + [1U][1U]; + __Vtemp620[2U] = vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__data + [1U][2U]; + __Vtemp620[3U] = vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__data + [1U][3U]; + vcdp->chgArray(c+829,(__Vtemp620),128); + __Vtemp621[0U] = vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__data + [2U][0U]; + __Vtemp621[1U] = vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__data + [2U][1U]; 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+ vcdp->chgBit(c+3043,(vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__3__KET____DOT__bank_structure.__PVT__data_structures__DOT__each_way__BRA__1__KET____DOT__data_structures__DOT__valid[24])); + vcdp->chgBit(c+3044,(vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__3__KET____DOT__bank_structure.__PVT__data_structures__DOT__each_way__BRA__1__KET____DOT__data_structures__DOT__valid[25])); + vcdp->chgBit(c+3045,(vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__3__KET____DOT__bank_structure.__PVT__data_structures__DOT__each_way__BRA__1__KET____DOT__data_structures__DOT__valid[26])); + vcdp->chgBit(c+3046,(vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__3__KET____DOT__bank_structure.__PVT__data_structures__DOT__each_way__BRA__1__KET____DOT__data_structures__DOT__valid[27])); + vcdp->chgBit(c+3047,(vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__3__KET____DOT__bank_structure.__PVT__data_structures__DOT__each_way__BRA__1__KET____DOT__data_structures__DOT__valid[28])); + vcdp->chgBit(c+3048,(vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__3__KET____DOT__bank_structure.__PVT__data_structures__DOT__each_way__BRA__1__KET____DOT__data_structures__DOT__valid[29])); + vcdp->chgBit(c+3049,(vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__3__KET____DOT__bank_structure.__PVT__data_structures__DOT__each_way__BRA__1__KET____DOT__data_structures__DOT__valid[30])); + vcdp->chgBit(c+3050,(vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__3__KET____DOT__bank_structure.__PVT__data_structures__DOT__each_way__BRA__1__KET____DOT__data_structures__DOT__valid[31])); + vcdp->chgBit(c+3051,(vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__3__KET____DOT__bank_structure.__PVT__data_structures__DOT__each_way__BRA__1__KET____DOT__data_structures__DOT__dirty[0])); + vcdp->chgBit(c+3052,(vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__3__KET____DOT__bank_structure.__PVT__data_structures__DOT__each_way__BRA__1__KET____DOT__data_structures__DOT__dirty[1])); + vcdp->chgBit(c+3053,(vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__3__KET____DOT__bank_structure.__PVT__data_structures__DOT__each_way__BRA__1__KET____DOT__data_structures__DOT__dirty[2])); + vcdp->chgBit(c+3054,(vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__3__KET____DOT__bank_structure.__PVT__data_structures__DOT__each_way__BRA__1__KET____DOT__data_structures__DOT__dirty[3])); + vcdp->chgBit(c+3055,(vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__3__KET____DOT__bank_structure.__PVT__data_structures__DOT__each_way__BRA__1__KET____DOT__data_structures__DOT__dirty[4])); + vcdp->chgBit(c+3056,(vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__3__KET____DOT__bank_structure.__PVT__data_structures__DOT__each_way__BRA__1__KET____DOT__data_structures__DOT__dirty[5])); + vcdp->chgBit(c+3057,(vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__3__KET____DOT__bank_structure.__PVT__data_structures__DOT__each_way__BRA__1__KET____DOT__data_structures__DOT__dirty[6])); + vcdp->chgBit(c+3058,(vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__3__KET____DOT__bank_structure.__PVT__data_structures__DOT__each_way__BRA__1__KET____DOT__data_structures__DOT__dirty[7])); + vcdp->chgBit(c+3059,(vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__3__KET____DOT__bank_structure.__PVT__data_structures__DOT__each_way__BRA__1__KET____DOT__data_structures__DOT__dirty[8])); + vcdp->chgBit(c+3060,(vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__3__KET____DOT__bank_structure.__PVT__data_structures__DOT__each_way__BRA__1__KET____DOT__data_structures__DOT__dirty[9])); + vcdp->chgBit(c+3061,(vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__3__KET____DOT__bank_structure.__PVT__data_structures__DOT__each_way__BRA__1__KET____DOT__data_structures__DOT__dirty[10])); + vcdp->chgBit(c+3062,(vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__3__KET____DOT__bank_structure.__PVT__data_structures__DOT__each_way__BRA__1__KET____DOT__data_structures__DOT__dirty[11])); + vcdp->chgBit(c+3063,(vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__3__KET____DOT__bank_structure.__PVT__data_structures__DOT__each_way__BRA__1__KET____DOT__data_structures__DOT__dirty[12])); + vcdp->chgBit(c+3064,(vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__3__KET____DOT__bank_structure.__PVT__data_structures__DOT__each_way__BRA__1__KET____DOT__data_structures__DOT__dirty[13])); + vcdp->chgBit(c+3065,(vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__3__KET____DOT__bank_structure.__PVT__data_structures__DOT__each_way__BRA__1__KET____DOT__data_structures__DOT__dirty[14])); + vcdp->chgBit(c+3066,(vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__3__KET____DOT__bank_structure.__PVT__data_structures__DOT__each_way__BRA__1__KET____DOT__data_structures__DOT__dirty[15])); + vcdp->chgBit(c+3067,(vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__3__KET____DOT__bank_structure.__PVT__data_structures__DOT__each_way__BRA__1__KET____DOT__data_structures__DOT__dirty[16])); + vcdp->chgBit(c+3068,(vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__3__KET____DOT__bank_structure.__PVT__data_structures__DOT__each_way__BRA__1__KET____DOT__data_structures__DOT__dirty[17])); + vcdp->chgBit(c+3069,(vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__3__KET____DOT__bank_structure.__PVT__data_structures__DOT__each_way__BRA__1__KET____DOT__data_structures__DOT__dirty[18])); + vcdp->chgBit(c+3070,(vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__3__KET____DOT__bank_structure.__PVT__data_structures__DOT__each_way__BRA__1__KET____DOT__data_structures__DOT__dirty[19])); + vcdp->chgBit(c+3071,(vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__3__KET____DOT__bank_structure.__PVT__data_structures__DOT__each_way__BRA__1__KET____DOT__data_structures__DOT__dirty[20])); + vcdp->chgBit(c+3072,(vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__3__KET____DOT__bank_structure.__PVT__data_structures__DOT__each_way__BRA__1__KET____DOT__data_structures__DOT__dirty[21])); + vcdp->chgBit(c+3073,(vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__3__KET____DOT__bank_structure.__PVT__data_structures__DOT__each_way__BRA__1__KET____DOT__data_structures__DOT__dirty[22])); + vcdp->chgBit(c+3074,(vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__3__KET____DOT__bank_structure.__PVT__data_structures__DOT__each_way__BRA__1__KET____DOT__data_structures__DOT__dirty[23])); + vcdp->chgBit(c+3075,(vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__3__KET____DOT__bank_structure.__PVT__data_structures__DOT__each_way__BRA__1__KET____DOT__data_structures__DOT__dirty[24])); + vcdp->chgBit(c+3076,(vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__3__KET____DOT__bank_structure.__PVT__data_structures__DOT__each_way__BRA__1__KET____DOT__data_structures__DOT__dirty[25])); + vcdp->chgBit(c+3077,(vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__3__KET____DOT__bank_structure.__PVT__data_structures__DOT__each_way__BRA__1__KET____DOT__data_structures__DOT__dirty[26])); + vcdp->chgBit(c+3078,(vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__3__KET____DOT__bank_structure.__PVT__data_structures__DOT__each_way__BRA__1__KET____DOT__data_structures__DOT__dirty[27])); + vcdp->chgBit(c+3079,(vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__3__KET____DOT__bank_structure.__PVT__data_structures__DOT__each_way__BRA__1__KET____DOT__data_structures__DOT__dirty[28])); + vcdp->chgBit(c+3080,(vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__3__KET____DOT__bank_structure.__PVT__data_structures__DOT__each_way__BRA__1__KET____DOT__data_structures__DOT__dirty[29])); + vcdp->chgBit(c+3081,(vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__3__KET____DOT__bank_structure.__PVT__data_structures__DOT__each_way__BRA__1__KET____DOT__data_structures__DOT__dirty[30])); + vcdp->chgBit(c+3082,(vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__3__KET____DOT__bank_structure.__PVT__data_structures__DOT__each_way__BRA__1__KET____DOT__data_structures__DOT__dirty[31])); + vcdp->chgBus(c+3083,(vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__3__KET____DOT__bank_structure.__PVT__data_structures__DOT__each_way__BRA__1__KET____DOT__data_structures__DOT__f),32); + vcdp->chgBus(c+3084,(vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__3__KET____DOT__bank_structure.__PVT__data_structures__DOT__each_way__BRA__1__KET____DOT__data_structures__DOT__ini_ind),32); + } +} + +void Vcache_simX::traceChgThis__6(Vcache_simX__Syms* __restrict vlSymsp, VerilatedVcd* vcdp, uint32_t code) { + Vcache_simX* __restrict vlTOPp VL_ATTR_UNUSED = vlSymsp->TOPp; + int c = code; + if (0 && vcdp && c) {} // Prevent unused + // Body + { + vcdp->chgBit(c+3085,(vlTOPp->clk)); + vcdp->chgBit(c+3086,(vlTOPp->reset)); + vcdp->chgBus(c+3087,(vlTOPp->in_icache_pc_addr),32); + vcdp->chgBit(c+3088,(vlTOPp->in_icache_valid_pc_addr)); + vcdp->chgBit(c+3089,(vlTOPp->out_icache_stall)); + vcdp->chgBus(c+3090,(vlTOPp->in_dcache_mem_read),3); + vcdp->chgBus(c+3091,(vlTOPp->in_dcache_mem_write),3); + vcdp->chgBit(c+3092,(vlTOPp->in_dcache_in_valid[0])); + vcdp->chgBit(c+3093,(vlTOPp->in_dcache_in_valid[1])); + vcdp->chgBit(c+3094,(vlTOPp->in_dcache_in_valid[2])); + vcdp->chgBit(c+3095,(vlTOPp->in_dcache_in_valid[3])); + vcdp->chgBus(c+3096,(vlTOPp->in_dcache_in_address[0]),32); + vcdp->chgBus(c+3097,(vlTOPp->in_dcache_in_address[1]),32); + vcdp->chgBus(c+3098,(vlTOPp->in_dcache_in_address[2]),32); + vcdp->chgBus(c+3099,(vlTOPp->in_dcache_in_address[3]),32); + vcdp->chgBit(c+3100,(vlTOPp->out_dcache_stall)); + vcdp->chgBus(c+3101,(((IData)(vlTOPp->in_icache_valid_pc_addr) + ? 2U : 7U)),3); + } +} diff --git a/simX/obj_dir/Vcache_simX__Trace__Slow.cpp b/simX/obj_dir/Vcache_simX__Trace__Slow.cpp new file mode 100644 index 00000000..8a717b89 --- /dev/null +++ b/simX/obj_dir/Vcache_simX__Trace__Slow.cpp @@ -0,0 +1,7759 @@ +// Verilated -*- C++ -*- +// DESCRIPTION: Verilator output: Tracing implementation internals +#include "verilated_vcd_c.h" +#include "Vcache_simX__Syms.h" + + +//====================== + +void Vcache_simX::trace(VerilatedVcdC* tfp, int, int) { + tfp->spTrace()->addCallback(&Vcache_simX::traceInit, &Vcache_simX::traceFull, &Vcache_simX::traceChg, this); +} +void Vcache_simX::traceInit(VerilatedVcd* vcdp, void* userthis, uint32_t code) { + // Callback from vcd->open() + Vcache_simX* t = (Vcache_simX*)userthis; + Vcache_simX__Syms* __restrict vlSymsp = t->__VlSymsp; // Setup global symbol table + if (!Verilated::calcUnusedSigs()) { + VL_FATAL_MT(__FILE__, __LINE__, __FILE__, + "Turning on wave traces requires Verilated::traceEverOn(true) call before time 0."); + } + vcdp->scopeEscape(' '); + t->traceInitThis(vlSymsp, vcdp, code); + vcdp->scopeEscape('.'); +} +void Vcache_simX::traceFull(VerilatedVcd* vcdp, void* userthis, uint32_t code) { + // Callback from vcd->dump() + Vcache_simX* t = (Vcache_simX*)userthis; + Vcache_simX__Syms* __restrict vlSymsp = t->__VlSymsp; // Setup global symbol table + t->traceFullThis(vlSymsp, vcdp, code); +} + +//====================== + + +void Vcache_simX::traceInitThis(Vcache_simX__Syms* __restrict vlSymsp, VerilatedVcd* vcdp, uint32_t code) { + Vcache_simX* __restrict vlTOPp VL_ATTR_UNUSED = vlSymsp->TOPp; + int c = code; + if (0 && vcdp && c) {} // Prevent unused + vcdp->module(vlSymsp->name()); // Setup signal names + // Body + { + vlTOPp->traceInitThis__1(vlSymsp, vcdp, code); + } +} + +void Vcache_simX::traceFullThis(Vcache_simX__Syms* __restrict vlSymsp, VerilatedVcd* vcdp, uint32_t code) { + Vcache_simX* __restrict vlTOPp VL_ATTR_UNUSED = vlSymsp->TOPp; + int c = code; + if (0 && vcdp && c) {} // Prevent unused + // Body + { + vlTOPp->traceFullThis__1(vlSymsp, vcdp, code); + } + // Final + vlTOPp->__Vm_traceActivity = 0U; +} + +void Vcache_simX::traceInitThis__1(Vcache_simX__Syms* __restrict vlSymsp, VerilatedVcd* vcdp, uint32_t code) { + Vcache_simX* __restrict vlTOPp VL_ATTR_UNUSED = vlSymsp->TOPp; + int c = code; + if (0 && vcdp && c) {} // Prevent unused + // Body + { + vcdp->declBit(c+3085,"clk",-1); + vcdp->declBit(c+3086,"reset",-1); + vcdp->declBus(c+3087,"in_icache_pc_addr",-1,31,0); + vcdp->declBit(c+3088,"in_icache_valid_pc_addr",-1); + vcdp->declBit(c+3089,"out_icache_stall",-1); + vcdp->declBus(c+3090,"in_dcache_mem_read",-1,2,0); + vcdp->declBus(c+3091,"in_dcache_mem_write",-1,2,0); + {int i; for (i=0; i<4; i++) { + vcdp->declBit(c+3092+i*1,"in_dcache_in_valid",(i+0));}} + {int i; for (i=0; i<4; i++) { + vcdp->declBus(c+3096+i*1,"in_dcache_in_address",(i+0),31,0);}} + vcdp->declBit(c+3100,"out_dcache_stall",-1); + vcdp->declBit(c+3085,"cache_simX clk",-1); + vcdp->declBit(c+3086,"cache_simX reset",-1); + vcdp->declBus(c+3087,"cache_simX in_icache_pc_addr",-1,31,0); + vcdp->declBit(c+3088,"cache_simX in_icache_valid_pc_addr",-1); + vcdp->declBit(c+3089,"cache_simX out_icache_stall",-1); + vcdp->declBus(c+3090,"cache_simX in_dcache_mem_read",-1,2,0); + vcdp->declBus(c+3091,"cache_simX in_dcache_mem_write",-1,2,0); + {int i; for (i=0; i<4; i++) { + vcdp->declBit(c+3092+i*1,"cache_simX in_dcache_in_valid",(i+0));}} + {int i; for (i=0; i<4; i++) { + vcdp->declBus(c+3096+i*1,"cache_simX in_dcache_in_address",(i+0),31,0);}} + vcdp->declBit(c+3100,"cache_simX out_dcache_stall",-1); + vcdp->declBit(c+800,"cache_simX icache_i_m_ready",-1); + vcdp->declBit(c+801,"cache_simX dcache_i_m_ready",-1); + vcdp->declBit(c+3085,"cache_simX dmem_controller clk",-1); + vcdp->declBit(c+3086,"cache_simX dmem_controller reset",-1); + vcdp->declBus(c+3102,"cache_simX dmem_controller VX_dram_req_rsp NUMBER_BANKS",-1,31,0); + vcdp->declBus(c+3102,"cache_simX dmem_controller VX_dram_req_rsp NUM_WORDS_PER_BLOCK",-1,31,0); + vcdp->declBus(c+1,"cache_simX dmem_controller VX_dram_req_rsp o_m_evict_addr",-1,31,0); + vcdp->declBus(c+802,"cache_simX dmem_controller VX_dram_req_rsp o_m_read_addr",-1,31,0); + vcdp->declBit(c+803,"cache_simX dmem_controller VX_dram_req_rsp o_m_valid",-1); + vcdp->declArray(c+2,"cache_simX dmem_controller VX_dram_req_rsp o_m_writedata",-1,511,0); + vcdp->declBit(c+709,"cache_simX dmem_controller VX_dram_req_rsp o_m_read_or_write",-1); + vcdp->declArray(c+3103,"cache_simX dmem_controller VX_dram_req_rsp i_m_readdata",-1,511,0); + vcdp->declBit(c+801,"cache_simX dmem_controller VX_dram_req_rsp i_m_ready",-1); + vcdp->declBus(c+3119,"cache_simX dmem_controller VX_dram_req_rsp_icache NUMBER_BANKS",-1,31,0); + vcdp->declBus(c+3102,"cache_simX dmem_controller VX_dram_req_rsp_icache NUM_WORDS_PER_BLOCK",-1,31,0); + vcdp->declBus(c+18,"cache_simX dmem_controller VX_dram_req_rsp_icache o_m_evict_addr",-1,31,0); + vcdp->declBus(c+804,"cache_simX dmem_controller VX_dram_req_rsp_icache o_m_read_addr",-1,31,0); + vcdp->declBit(c+805,"cache_simX dmem_controller VX_dram_req_rsp_icache o_m_valid",-1); + vcdp->declArray(c+19,"cache_simX dmem_controller VX_dram_req_rsp_icache o_m_writedata",-1,127,0); + vcdp->declBit(c+710,"cache_simX dmem_controller VX_dram_req_rsp_icache o_m_read_or_write",-1); + vcdp->declArray(c+3120,"cache_simX dmem_controller VX_dram_req_rsp_icache i_m_readdata",-1,127,0); + vcdp->declBit(c+800,"cache_simX dmem_controller VX_dram_req_rsp_icache i_m_ready",-1); + vcdp->declBus(c+3087,"cache_simX dmem_controller VX_icache_req pc_address",-1,31,0); + vcdp->declBus(c+3101,"cache_simX dmem_controller VX_icache_req out_cache_driver_in_mem_read",-1,2,0); + vcdp->declBus(c+3124,"cache_simX dmem_controller VX_icache_req out_cache_driver_in_mem_write",-1,2,0); + vcdp->declBit(c+3088,"cache_simX dmem_controller VX_icache_req out_cache_driver_in_valid",-1); + vcdp->declBus(c+3125,"cache_simX dmem_controller VX_icache_req out_cache_driver_in_data",-1,31,0); + vcdp->declBus(c+711,"cache_simX dmem_controller VX_icache_rsp instruction",-1,31,0); + vcdp->declBit(c+712,"cache_simX dmem_controller VX_icache_rsp delay",-1); + vcdp->declArray(c+23,"cache_simX dmem_controller VX_dcache_req out_cache_driver_in_address",-1,127,0); + vcdp->declBus(c+3090,"cache_simX dmem_controller VX_dcache_req out_cache_driver_in_mem_read",-1,2,0); + vcdp->declBus(c+3091,"cache_simX dmem_controller VX_dcache_req out_cache_driver_in_mem_write",-1,2,0); + vcdp->declBus(c+27,"cache_simX dmem_controller VX_dcache_req out_cache_driver_in_valid",-1,3,0); + vcdp->declArray(c+3126,"cache_simX dmem_controller VX_dcache_req out_cache_driver_in_data",-1,127,0); + vcdp->declArray(c+28,"cache_simX dmem_controller VX_dcache_rsp in_cache_driver_out_data",-1,127,0); + vcdp->declBit(c+713,"cache_simX dmem_controller VX_dcache_rsp delay",-1); + vcdp->declBit(c+32,"cache_simX dmem_controller to_shm",-1); + vcdp->declBus(c+33,"cache_simX dmem_controller sm_driver_in_valid",-1,3,0); + vcdp->declBus(c+34,"cache_simX dmem_controller cache_driver_in_valid",-1,3,0); + vcdp->declBit(c+35,"cache_simX dmem_controller read_or_write",-1); + vcdp->declArray(c+23,"cache_simX dmem_controller cache_driver_in_address",-1,127,0); + vcdp->declBus(c+36,"cache_simX dmem_controller cache_driver_in_mem_read",-1,2,0); + vcdp->declBus(c+37,"cache_simX dmem_controller cache_driver_in_mem_write",-1,2,0); + vcdp->declArray(c+3126,"cache_simX dmem_controller cache_driver_in_data",-1,127,0); + vcdp->declBus(c+38,"cache_simX dmem_controller sm_driver_in_mem_read",-1,2,0); + vcdp->declBus(c+39,"cache_simX dmem_controller sm_driver_in_mem_write",-1,2,0); + vcdp->declArray(c+40,"cache_simX dmem_controller cache_driver_out_data",-1,127,0); + vcdp->declArray(c+44,"cache_simX dmem_controller sm_driver_out_data",-1,127,0); + vcdp->declBus(c+48,"cache_simX dmem_controller cache_driver_out_valid",-1,3,0); + vcdp->declBit(c+49,"cache_simX dmem_controller sm_delay",-1); + vcdp->declBit(c+714,"cache_simX dmem_controller cache_delay",-1); + vcdp->declBus(c+711,"cache_simX dmem_controller icache_instruction_out",-1,31,0); + vcdp->declBit(c+712,"cache_simX dmem_controller icache_delay",-1); + vcdp->declBit(c+3088,"cache_simX dmem_controller icache_driver_in_valid",-1); + vcdp->declBus(c+3087,"cache_simX dmem_controller icache_driver_in_address",-1,31,0); + vcdp->declBus(c+50,"cache_simX dmem_controller icache_driver_in_mem_read",-1,2,0); + vcdp->declBus(c+3124,"cache_simX dmem_controller icache_driver_in_mem_write",-1,2,0); + vcdp->declBus(c+3125,"cache_simX dmem_controller icache_driver_in_data",-1,31,0); + vcdp->declBit(c+3130,"cache_simX dmem_controller read_or_write_ic",-1); + vcdp->declBit(c+715,"cache_simX dmem_controller valid_read_cache",-1); + vcdp->declBus(c+3131,"cache_simX dmem_controller shared_memory SM_SIZE",-1,31,0); + vcdp->declBus(c+3102,"cache_simX dmem_controller shared_memory SM_BANKS",-1,31,0); + vcdp->declBus(c+3132,"cache_simX dmem_controller shared_memory SM_BYTES_PER_READ",-1,31,0); + vcdp->declBus(c+3102,"cache_simX dmem_controller shared_memory SM_WORDS_PER_READ",-1,31,0); + vcdp->declBus(c+3133,"cache_simX dmem_controller shared_memory SM_LOG_WORDS_PER_READ",-1,31,0); + vcdp->declBus(c+3134,"cache_simX dmem_controller shared_memory SM_HEIGHT",-1,31,0); + vcdp->declBus(c+3133,"cache_simX dmem_controller shared_memory SM_BANK_OFFSET_START",-1,31,0); + vcdp->declBus(c+3135,"cache_simX dmem_controller shared_memory SM_BANK_OFFSET_END",-1,31,0); + vcdp->declBus(c+3102,"cache_simX dmem_controller shared_memory SM_BLOCK_OFFSET_START",-1,31,0); + vcdp->declBus(c+3136,"cache_simX dmem_controller shared_memory SM_BLOCK_OFFSET_END",-1,31,0); + vcdp->declBus(c+3137,"cache_simX dmem_controller shared_memory SM_INDEX_START",-1,31,0); + vcdp->declBus(c+3138,"cache_simX dmem_controller shared_memory SM_INDEX_END",-1,31,0); + vcdp->declBus(c+3102,"cache_simX dmem_controller shared_memory NUM_REQ",-1,31,0); + vcdp->declBus(c+3133,"cache_simX dmem_controller shared_memory BITS_PER_BANK",-1,31,0); + vcdp->declBit(c+3085,"cache_simX dmem_controller shared_memory clk",-1); + vcdp->declBit(c+3086,"cache_simX dmem_controller shared_memory reset",-1); + vcdp->declBus(c+33,"cache_simX dmem_controller shared_memory in_valid",-1,3,0); + vcdp->declArray(c+23,"cache_simX dmem_controller shared_memory in_address",-1,127,0); + vcdp->declArray(c+3126,"cache_simX dmem_controller shared_memory in_data",-1,127,0); + vcdp->declBus(c+38,"cache_simX dmem_controller shared_memory mem_read",-1,2,0); + vcdp->declBus(c+39,"cache_simX dmem_controller shared_memory mem_write",-1,2,0); + vcdp->declBus(c+48,"cache_simX dmem_controller shared_memory out_valid",-1,3,0); + vcdp->declArray(c+44,"cache_simX dmem_controller shared_memory out_data",-1,127,0); + vcdp->declBit(c+49,"cache_simX dmem_controller shared_memory stall",-1); + vcdp->declArray(c+51,"cache_simX dmem_controller shared_memory temp_address",-1,127,0); + vcdp->declArray(c+55,"cache_simX dmem_controller shared_memory temp_in_data",-1,127,0); + vcdp->declBus(c+59,"cache_simX dmem_controller shared_memory temp_in_valid",-1,3,0); + vcdp->declBus(c+60,"cache_simX dmem_controller shared_memory temp_out_valid",-1,3,0); + vcdp->declArray(c+61,"cache_simX dmem_controller shared_memory temp_out_data",-1,127,0); + vcdp->declBus(c+65,"cache_simX dmem_controller shared_memory block_addr",-1,27,0); + vcdp->declArray(c+66,"cache_simX dmem_controller shared_memory block_wdata",-1,511,0); + vcdp->declArray(c+82,"cache_simX dmem_controller shared_memory block_rdata",-1,511,0); + vcdp->declBus(c+98,"cache_simX dmem_controller shared_memory block_we",-1,7,0); + vcdp->declBit(c+99,"cache_simX dmem_controller shared_memory send_data",-1); + vcdp->declBus(c+100,"cache_simX dmem_controller shared_memory req_num",-1,11,0); + vcdp->declBus(c+101,"cache_simX dmem_controller shared_memory orig_in_valid",-1,3,0); + vcdp->declBus(c+3139,"cache_simX dmem_controller shared_memory i",-1,31,0); + vcdp->declBit(c+102,"cache_simX dmem_controller shared_memory genblk2[0] shm_write",-1); + vcdp->declBit(c+103,"cache_simX dmem_controller shared_memory genblk2[1] shm_write",-1); + vcdp->declBit(c+104,"cache_simX dmem_controller shared_memory genblk2[2] shm_write",-1); + vcdp->declBit(c+105,"cache_simX dmem_controller shared_memory genblk2[3] shm_write",-1); + vcdp->declBus(c+3135,"cache_simX dmem_controller shared_memory vx_priority_encoder_sm NB",-1,31,0); + vcdp->declBus(c+3133,"cache_simX dmem_controller shared_memory vx_priority_encoder_sm BITS_PER_BANK",-1,31,0); + vcdp->declBus(c+3102,"cache_simX dmem_controller shared_memory vx_priority_encoder_sm NUM_REQ",-1,31,0); + vcdp->declBit(c+3085,"cache_simX dmem_controller shared_memory vx_priority_encoder_sm clk",-1); + vcdp->declBit(c+3086,"cache_simX dmem_controller shared_memory vx_priority_encoder_sm reset",-1); + vcdp->declBus(c+101,"cache_simX dmem_controller shared_memory vx_priority_encoder_sm in_valid",-1,3,0); + vcdp->declArray(c+23,"cache_simX dmem_controller shared_memory vx_priority_encoder_sm in_address",-1,127,0); + vcdp->declArray(c+3126,"cache_simX dmem_controller shared_memory vx_priority_encoder_sm in_data",-1,127,0); + vcdp->declBus(c+59,"cache_simX dmem_controller shared_memory vx_priority_encoder_sm out_valid",-1,3,0); + vcdp->declArray(c+51,"cache_simX dmem_controller shared_memory vx_priority_encoder_sm out_address",-1,127,0); + vcdp->declArray(c+55,"cache_simX dmem_controller shared_memory vx_priority_encoder_sm out_data",-1,127,0); + vcdp->declBus(c+100,"cache_simX dmem_controller shared_memory vx_priority_encoder_sm req_num",-1,11,0); + vcdp->declBit(c+49,"cache_simX dmem_controller shared_memory vx_priority_encoder_sm stall",-1); + vcdp->declBit(c+99,"cache_simX dmem_controller shared_memory vx_priority_encoder_sm send_data",-1); + vcdp->declBus(c+806,"cache_simX dmem_controller shared_memory vx_priority_encoder_sm left_requests",-1,3,0); + vcdp->declBus(c+106,"cache_simX dmem_controller shared_memory vx_priority_encoder_sm serviced",-1,3,0); + vcdp->declBus(c+107,"cache_simX dmem_controller shared_memory vx_priority_encoder_sm use_valid",-1,3,0); + vcdp->declBit(c+807,"cache_simX dmem_controller shared_memory vx_priority_encoder_sm requests_left",-1); + vcdp->declBus(c+108,"cache_simX dmem_controller shared_memory vx_priority_encoder_sm bank_valids",-1,15,0); + vcdp->declBus(c+109,"cache_simX dmem_controller shared_memory vx_priority_encoder_sm more_than_one_valid",-1,3,0); + vcdp->declBus(c+110,"cache_simX dmem_controller shared_memory vx_priority_encoder_sm internal_req_num",-1,7,0); + vcdp->declBus(c+59,"cache_simX dmem_controller shared_memory vx_priority_encoder_sm internal_out_valid",-1,3,0); + vcdp->declBus(c+3139,"cache_simX dmem_controller shared_memory vx_priority_encoder_sm curr_b",-1,31,0); + vcdp->declBus(c+111,"cache_simX dmem_controller shared_memory vx_priority_encoder_sm serviced_qual",-1,3,0); + vcdp->declBus(c+716,"cache_simX dmem_controller shared_memory vx_priority_encoder_sm new_left_requests",-1,3,0); + vcdp->declBus(c+112,"cache_simX dmem_controller shared_memory vx_priority_encoder_sm genblk1[0] num_valids",-1,2,0); + vcdp->declBus(c+113,"cache_simX dmem_controller shared_memory vx_priority_encoder_sm genblk1[1] num_valids",-1,2,0); + vcdp->declBus(c+114,"cache_simX dmem_controller shared_memory vx_priority_encoder_sm genblk1[2] num_valids",-1,2,0); + vcdp->declBus(c+115,"cache_simX dmem_controller shared_memory vx_priority_encoder_sm genblk1[3] num_valids",-1,2,0); + vcdp->declBus(c+3135,"cache_simX dmem_controller shared_memory vx_priority_encoder_sm vx_bank_valid NB",-1,31,0); + vcdp->declBus(c+3133,"cache_simX dmem_controller shared_memory vx_priority_encoder_sm vx_bank_valid BITS_PER_BANK",-1,31,0); + vcdp->declBus(c+107,"cache_simX dmem_controller shared_memory vx_priority_encoder_sm vx_bank_valid in_valids",-1,3,0); + vcdp->declArray(c+23,"cache_simX dmem_controller shared_memory vx_priority_encoder_sm vx_bank_valid in_addr",-1,127,0); + vcdp->declBus(c+108,"cache_simX dmem_controller shared_memory vx_priority_encoder_sm vx_bank_valid bank_valids",-1,15,0); + vcdp->declBus(c+3139,"cache_simX dmem_controller shared_memory vx_priority_encoder_sm vx_bank_valid i",-1,31,0); + vcdp->declBus(c+3139,"cache_simX dmem_controller shared_memory vx_priority_encoder_sm vx_bank_valid j",-1,31,0); + vcdp->declBus(c+3102,"cache_simX dmem_controller shared_memory vx_priority_encoder_sm genblk1[0] valids_counter N",-1,31,0); + vcdp->declBus(c+116,"cache_simX dmem_controller shared_memory vx_priority_encoder_sm genblk1[0] valids_counter valids",-1,3,0); + vcdp->declBus(c+112,"cache_simX dmem_controller shared_memory vx_priority_encoder_sm genblk1[0] valids_counter count",-1,2,0); + vcdp->declBus(c+3140,"cache_simX dmem_controller shared_memory vx_priority_encoder_sm genblk1[0] valids_counter i",-1,31,0); + vcdp->declBus(c+3102,"cache_simX dmem_controller shared_memory vx_priority_encoder_sm genblk1[1] valids_counter N",-1,31,0); + vcdp->declBus(c+117,"cache_simX dmem_controller shared_memory vx_priority_encoder_sm genblk1[1] valids_counter valids",-1,3,0); + vcdp->declBus(c+113,"cache_simX dmem_controller shared_memory vx_priority_encoder_sm genblk1[1] valids_counter count",-1,2,0); + vcdp->declBus(c+3140,"cache_simX dmem_controller shared_memory vx_priority_encoder_sm genblk1[1] valids_counter i",-1,31,0); + vcdp->declBus(c+3102,"cache_simX dmem_controller shared_memory vx_priority_encoder_sm genblk1[2] valids_counter N",-1,31,0); + vcdp->declBus(c+118,"cache_simX dmem_controller shared_memory vx_priority_encoder_sm genblk1[2] valids_counter valids",-1,3,0); + vcdp->declBus(c+114,"cache_simX dmem_controller shared_memory vx_priority_encoder_sm genblk1[2] valids_counter count",-1,2,0); + vcdp->declBus(c+3140,"cache_simX dmem_controller shared_memory vx_priority_encoder_sm genblk1[2] valids_counter i",-1,31,0); + vcdp->declBus(c+3102,"cache_simX dmem_controller shared_memory vx_priority_encoder_sm genblk1[3] valids_counter N",-1,31,0); + vcdp->declBus(c+119,"cache_simX dmem_controller shared_memory vx_priority_encoder_sm genblk1[3] valids_counter valids",-1,3,0); + vcdp->declBus(c+115,"cache_simX dmem_controller shared_memory vx_priority_encoder_sm genblk1[3] valids_counter count",-1,2,0); + vcdp->declBus(c+3140,"cache_simX dmem_controller shared_memory vx_priority_encoder_sm genblk1[3] valids_counter i",-1,31,0); + vcdp->declBus(c+3102,"cache_simX dmem_controller shared_memory vx_priority_encoder_sm genblk2[0] vx_priority_encoder N",-1,31,0); + vcdp->declBus(c+116,"cache_simX dmem_controller shared_memory vx_priority_encoder_sm genblk2[0] vx_priority_encoder valids",-1,3,0); + vcdp->declBus(c+120,"cache_simX dmem_controller shared_memory vx_priority_encoder_sm genblk2[0] vx_priority_encoder index",-1,1,0); + vcdp->declBit(c+121,"cache_simX dmem_controller shared_memory vx_priority_encoder_sm genblk2[0] vx_priority_encoder found",-1); + vcdp->declBus(c+122,"cache_simX dmem_controller shared_memory vx_priority_encoder_sm genblk2[0] vx_priority_encoder i",-1,31,0); + vcdp->declBus(c+3102,"cache_simX dmem_controller shared_memory vx_priority_encoder_sm genblk2[1] vx_priority_encoder N",-1,31,0); + vcdp->declBus(c+117,"cache_simX dmem_controller shared_memory vx_priority_encoder_sm genblk2[1] vx_priority_encoder valids",-1,3,0); + vcdp->declBus(c+123,"cache_simX dmem_controller shared_memory vx_priority_encoder_sm genblk2[1] vx_priority_encoder index",-1,1,0); + vcdp->declBit(c+124,"cache_simX dmem_controller shared_memory vx_priority_encoder_sm genblk2[1] vx_priority_encoder found",-1); + vcdp->declBus(c+125,"cache_simX dmem_controller shared_memory vx_priority_encoder_sm genblk2[1] vx_priority_encoder i",-1,31,0); + vcdp->declBus(c+3102,"cache_simX dmem_controller shared_memory vx_priority_encoder_sm genblk2[2] vx_priority_encoder N",-1,31,0); + vcdp->declBus(c+118,"cache_simX dmem_controller shared_memory vx_priority_encoder_sm genblk2[2] vx_priority_encoder valids",-1,3,0); + vcdp->declBus(c+126,"cache_simX dmem_controller shared_memory vx_priority_encoder_sm genblk2[2] vx_priority_encoder index",-1,1,0); + vcdp->declBit(c+127,"cache_simX dmem_controller shared_memory vx_priority_encoder_sm genblk2[2] vx_priority_encoder found",-1); + vcdp->declBus(c+128,"cache_simX dmem_controller shared_memory vx_priority_encoder_sm genblk2[2] vx_priority_encoder i",-1,31,0); + vcdp->declBus(c+3102,"cache_simX dmem_controller shared_memory vx_priority_encoder_sm genblk2[3] vx_priority_encoder N",-1,31,0); + vcdp->declBus(c+119,"cache_simX dmem_controller shared_memory vx_priority_encoder_sm genblk2[3] vx_priority_encoder valids",-1,3,0); + vcdp->declBus(c+129,"cache_simX dmem_controller shared_memory vx_priority_encoder_sm genblk2[3] vx_priority_encoder index",-1,1,0); + vcdp->declBit(c+130,"cache_simX dmem_controller shared_memory vx_priority_encoder_sm genblk2[3] vx_priority_encoder found",-1); + vcdp->declBus(c+131,"cache_simX dmem_controller shared_memory vx_priority_encoder_sm genblk2[3] vx_priority_encoder i",-1,31,0); + vcdp->declBus(c+3141,"cache_simX dmem_controller shared_memory genblk2[0] vx_shared_memory_block SMB_SIZE",-1,31,0); + vcdp->declBus(c+3132,"cache_simX dmem_controller shared_memory genblk2[0] vx_shared_memory_block SMB_BYTES_PER_READ",-1,31,0); + vcdp->declBus(c+3102,"cache_simX dmem_controller shared_memory genblk2[0] vx_shared_memory_block SMB_WORDS_PER_READ",-1,31,0); + vcdp->declBus(c+3133,"cache_simX dmem_controller shared_memory genblk2[0] vx_shared_memory_block SMB_LOG_WORDS_PER_READ",-1,31,0); + vcdp->declBus(c+3134,"cache_simX dmem_controller shared_memory genblk2[0] vx_shared_memory_block SMB_HEIGHT",-1,31,0); + vcdp->declBus(c+3135,"cache_simX dmem_controller shared_memory genblk2[0] vx_shared_memory_block BITS_PER_BANK",-1,31,0); + vcdp->declBit(c+3085,"cache_simX dmem_controller shared_memory genblk2[0] vx_shared_memory_block clk",-1); + vcdp->declBit(c+3086,"cache_simX dmem_controller shared_memory genblk2[0] vx_shared_memory_block reset",-1); + vcdp->declBus(c+132,"cache_simX dmem_controller shared_memory genblk2[0] vx_shared_memory_block addr",-1,6,0); + vcdp->declArray(c+133,"cache_simX dmem_controller shared_memory genblk2[0] vx_shared_memory_block wdata",-1,127,0); + vcdp->declBus(c+137,"cache_simX dmem_controller shared_memory genblk2[0] vx_shared_memory_block we",-1,1,0); + vcdp->declBit(c+102,"cache_simX dmem_controller shared_memory genblk2[0] vx_shared_memory_block shm_write",-1); + vcdp->declArray(c+717,"cache_simX dmem_controller shared_memory genblk2[0] vx_shared_memory_block data_out",-1,127,0); + vcdp->declBus(c+808,"cache_simX dmem_controller shared_memory genblk2[0] vx_shared_memory_block curr_ind",-1,31,0); + vcdp->declBus(c+3141,"cache_simX dmem_controller shared_memory genblk2[1] vx_shared_memory_block SMB_SIZE",-1,31,0); + vcdp->declBus(c+3132,"cache_simX dmem_controller shared_memory genblk2[1] vx_shared_memory_block SMB_BYTES_PER_READ",-1,31,0); + vcdp->declBus(c+3102,"cache_simX dmem_controller shared_memory genblk2[1] vx_shared_memory_block SMB_WORDS_PER_READ",-1,31,0); + vcdp->declBus(c+3133,"cache_simX dmem_controller shared_memory genblk2[1] vx_shared_memory_block SMB_LOG_WORDS_PER_READ",-1,31,0); + vcdp->declBus(c+3134,"cache_simX dmem_controller shared_memory genblk2[1] vx_shared_memory_block SMB_HEIGHT",-1,31,0); + vcdp->declBus(c+3135,"cache_simX dmem_controller shared_memory genblk2[1] vx_shared_memory_block BITS_PER_BANK",-1,31,0); + vcdp->declBit(c+3085,"cache_simX dmem_controller shared_memory genblk2[1] vx_shared_memory_block clk",-1); + vcdp->declBit(c+3086,"cache_simX dmem_controller shared_memory genblk2[1] vx_shared_memory_block reset",-1); + vcdp->declBus(c+138,"cache_simX dmem_controller shared_memory genblk2[1] vx_shared_memory_block addr",-1,6,0); + vcdp->declArray(c+139,"cache_simX dmem_controller shared_memory genblk2[1] vx_shared_memory_block wdata",-1,127,0); + vcdp->declBus(c+143,"cache_simX dmem_controller shared_memory genblk2[1] vx_shared_memory_block we",-1,1,0); + vcdp->declBit(c+103,"cache_simX dmem_controller shared_memory genblk2[1] vx_shared_memory_block shm_write",-1); + vcdp->declArray(c+721,"cache_simX dmem_controller shared_memory genblk2[1] vx_shared_memory_block data_out",-1,127,0); + vcdp->declBus(c+809,"cache_simX dmem_controller shared_memory genblk2[1] vx_shared_memory_block curr_ind",-1,31,0); + vcdp->declBus(c+3141,"cache_simX dmem_controller shared_memory genblk2[2] vx_shared_memory_block SMB_SIZE",-1,31,0); + vcdp->declBus(c+3132,"cache_simX dmem_controller shared_memory genblk2[2] vx_shared_memory_block SMB_BYTES_PER_READ",-1,31,0); + vcdp->declBus(c+3102,"cache_simX dmem_controller shared_memory genblk2[2] vx_shared_memory_block SMB_WORDS_PER_READ",-1,31,0); + vcdp->declBus(c+3133,"cache_simX dmem_controller shared_memory genblk2[2] vx_shared_memory_block SMB_LOG_WORDS_PER_READ",-1,31,0); + vcdp->declBus(c+3134,"cache_simX dmem_controller shared_memory genblk2[2] vx_shared_memory_block SMB_HEIGHT",-1,31,0); + vcdp->declBus(c+3135,"cache_simX dmem_controller shared_memory genblk2[2] vx_shared_memory_block BITS_PER_BANK",-1,31,0); + vcdp->declBit(c+3085,"cache_simX dmem_controller shared_memory genblk2[2] vx_shared_memory_block clk",-1); + vcdp->declBit(c+3086,"cache_simX dmem_controller shared_memory genblk2[2] vx_shared_memory_block reset",-1); + vcdp->declBus(c+144,"cache_simX dmem_controller shared_memory genblk2[2] vx_shared_memory_block addr",-1,6,0); + vcdp->declArray(c+145,"cache_simX dmem_controller shared_memory genblk2[2] vx_shared_memory_block wdata",-1,127,0); + vcdp->declBus(c+149,"cache_simX dmem_controller shared_memory genblk2[2] vx_shared_memory_block we",-1,1,0); + vcdp->declBit(c+104,"cache_simX dmem_controller shared_memory genblk2[2] vx_shared_memory_block shm_write",-1); + vcdp->declArray(c+725,"cache_simX dmem_controller shared_memory genblk2[2] vx_shared_memory_block data_out",-1,127,0); + vcdp->declBus(c+810,"cache_simX dmem_controller shared_memory genblk2[2] vx_shared_memory_block curr_ind",-1,31,0); + vcdp->declBus(c+3141,"cache_simX dmem_controller shared_memory genblk2[3] vx_shared_memory_block SMB_SIZE",-1,31,0); + vcdp->declBus(c+3132,"cache_simX dmem_controller shared_memory genblk2[3] vx_shared_memory_block SMB_BYTES_PER_READ",-1,31,0); + vcdp->declBus(c+3102,"cache_simX dmem_controller shared_memory genblk2[3] vx_shared_memory_block SMB_WORDS_PER_READ",-1,31,0); + vcdp->declBus(c+3133,"cache_simX dmem_controller shared_memory genblk2[3] vx_shared_memory_block SMB_LOG_WORDS_PER_READ",-1,31,0); + vcdp->declBus(c+3134,"cache_simX dmem_controller shared_memory genblk2[3] vx_shared_memory_block SMB_HEIGHT",-1,31,0); + vcdp->declBus(c+3135,"cache_simX dmem_controller shared_memory genblk2[3] vx_shared_memory_block BITS_PER_BANK",-1,31,0); + vcdp->declBit(c+3085,"cache_simX dmem_controller shared_memory genblk2[3] vx_shared_memory_block clk",-1); + vcdp->declBit(c+3086,"cache_simX dmem_controller shared_memory genblk2[3] vx_shared_memory_block reset",-1); + vcdp->declBus(c+150,"cache_simX dmem_controller shared_memory genblk2[3] vx_shared_memory_block addr",-1,6,0); + vcdp->declArray(c+151,"cache_simX dmem_controller shared_memory genblk2[3] vx_shared_memory_block wdata",-1,127,0); + vcdp->declBus(c+155,"cache_simX dmem_controller shared_memory genblk2[3] vx_shared_memory_block we",-1,1,0); + vcdp->declBit(c+105,"cache_simX dmem_controller shared_memory genblk2[3] vx_shared_memory_block shm_write",-1); + vcdp->declArray(c+729,"cache_simX dmem_controller shared_memory genblk2[3] vx_shared_memory_block data_out",-1,127,0); + vcdp->declBus(c+811,"cache_simX dmem_controller shared_memory genblk2[3] vx_shared_memory_block curr_ind",-1,31,0); + vcdp->declBus(c+3141,"cache_simX dmem_controller dcache CACHE_SIZE",-1,31,0); + vcdp->declBus(c+3133,"cache_simX dmem_controller dcache CACHE_WAYS",-1,31,0); + vcdp->declBus(c+3142,"cache_simX dmem_controller dcache CACHE_BLOCK",-1,31,0); + vcdp->declBus(c+3102,"cache_simX dmem_controller dcache CACHE_BANKS",-1,31,0); + vcdp->declBus(c+3133,"cache_simX dmem_controller dcache LOG_NUM_BANKS",-1,31,0); + vcdp->declBus(c+3102,"cache_simX dmem_controller dcache NUM_REQ",-1,31,0); + vcdp->declBus(c+3133,"cache_simX dmem_controller dcache LOG_NUM_REQ",-1,31,0); + vcdp->declBus(c+3143,"cache_simX dmem_controller dcache NUM_IND",-1,31,0); + vcdp->declBus(c+3119,"cache_simX dmem_controller dcache CACHE_WAY_INDEX",-1,31,0); + vcdp->declBus(c+3102,"cache_simX dmem_controller dcache NUM_WORDS_PER_BLOCK",-1,31,0); + vcdp->declBus(c+3125,"cache_simX dmem_controller dcache OFFSET_SIZE_START",-1,31,0); + vcdp->declBus(c+3119,"cache_simX dmem_controller dcache OFFSET_SIZE_END",-1,31,0); + vcdp->declBus(c+3125,"cache_simX dmem_controller dcache TAG_SIZE_START",-1,31,0); + vcdp->declBus(c+3144,"cache_simX dmem_controller dcache TAG_SIZE_END",-1,31,0); + vcdp->declBus(c+3125,"cache_simX dmem_controller dcache IND_SIZE_START",-1,31,0); + vcdp->declBus(c+3102,"cache_simX dmem_controller dcache IND_SIZE_END",-1,31,0); + vcdp->declBus(c+3145,"cache_simX dmem_controller dcache ADDR_TAG_START",-1,31,0); + vcdp->declBus(c+3146,"cache_simX dmem_controller dcache ADDR_TAG_END",-1,31,0); + vcdp->declBus(c+3102,"cache_simX dmem_controller dcache ADDR_OFFSET_START",-1,31,0); + vcdp->declBus(c+3136,"cache_simX dmem_controller dcache ADDR_OFFSET_END",-1,31,0); + vcdp->declBus(c+3137,"cache_simX dmem_controller dcache ADDR_IND_START",-1,31,0); + vcdp->declBus(c+3147,"cache_simX dmem_controller dcache ADDR_IND_END",-1,31,0); + vcdp->declBus(c+3148,"cache_simX dmem_controller dcache MEM_ADDR_REQ_MASK",-1,31,0); + vcdp->declBus(c+3125,"cache_simX dmem_controller dcache CACHE_IDLE",-1,31,0); + vcdp->declBus(c+3119,"cache_simX dmem_controller dcache SEND_MEM_REQ",-1,31,0); + vcdp->declBus(c+3133,"cache_simX dmem_controller dcache RECIV_MEM_RSP",-1,31,0); + vcdp->declBit(c+3085,"cache_simX dmem_controller dcache clk",-1); + vcdp->declBit(c+3086,"cache_simX dmem_controller dcache rst",-1); + vcdp->declBus(c+34,"cache_simX dmem_controller dcache i_p_valid",-1,3,0); + vcdp->declArray(c+23,"cache_simX dmem_controller dcache i_p_addr",-1,127,0); + vcdp->declArray(c+3126,"cache_simX dmem_controller dcache i_p_writedata",-1,127,0); + vcdp->declBit(c+35,"cache_simX dmem_controller dcache i_p_read_or_write",-1); + vcdp->declArray(c+40,"cache_simX dmem_controller dcache o_p_readdata",-1,127,0); + vcdp->declBit(c+714,"cache_simX dmem_controller dcache o_p_delay",-1); + vcdp->declBus(c+1,"cache_simX dmem_controller dcache o_m_evict_addr",-1,31,0); + vcdp->declBus(c+802,"cache_simX dmem_controller dcache o_m_read_addr",-1,31,0); + vcdp->declBit(c+803,"cache_simX dmem_controller dcache o_m_valid",-1); + vcdp->declArray(c+2,"cache_simX dmem_controller dcache o_m_writedata",-1,511,0); + vcdp->declBit(c+709,"cache_simX dmem_controller dcache o_m_read_or_write",-1); + vcdp->declArray(c+3103,"cache_simX dmem_controller dcache i_m_readdata",-1,511,0); + vcdp->declBit(c+801,"cache_simX dmem_controller dcache i_m_ready",-1); + vcdp->declBus(c+36,"cache_simX dmem_controller dcache i_p_mem_read",-1,2,0); + vcdp->declBus(c+37,"cache_simX dmem_controller dcache i_p_mem_write",-1,2,0); + vcdp->declArray(c+812,"cache_simX dmem_controller dcache final_data_read",-1,127,0); + vcdp->declArray(c+156,"cache_simX dmem_controller dcache new_final_data_read",-1,127,0); + vcdp->declArray(c+40,"cache_simX dmem_controller dcache new_final_data_read_Qual",-1,127,0); + vcdp->declBus(c+816,"cache_simX dmem_controller dcache global_way_to_evict",-1,0,0); + vcdp->declBus(c+160,"cache_simX dmem_controller dcache thread_track_banks",-1,15,0); + vcdp->declBus(c+161,"cache_simX dmem_controller dcache index_per_bank",-1,7,0); + vcdp->declBus(c+162,"cache_simX dmem_controller dcache use_mask_per_bank",-1,15,0); + vcdp->declBus(c+163,"cache_simX dmem_controller dcache valid_per_bank",-1,3,0); + vcdp->declBus(c+164,"cache_simX dmem_controller dcache threads_serviced_per_bank",-1,15,0); + vcdp->declArray(c+165,"cache_simX dmem_controller dcache readdata_per_bank",-1,127,0); + vcdp->declBus(c+169,"cache_simX dmem_controller dcache hit_per_bank",-1,3,0); + vcdp->declBus(c+170,"cache_simX dmem_controller dcache eviction_wb",-1,3,0); + vcdp->declBus(c+3149,"cache_simX dmem_controller dcache eviction_wb_old",-1,3,0); + vcdp->declBus(c+817,"cache_simX dmem_controller dcache state",-1,3,0); + vcdp->declBus(c+171,"cache_simX dmem_controller dcache new_state",-1,3,0); + vcdp->declBus(c+172,"cache_simX dmem_controller dcache use_valid",-1,3,0); + vcdp->declBus(c+818,"cache_simX dmem_controller dcache stored_valid",-1,3,0); + vcdp->declBus(c+173,"cache_simX dmem_controller dcache new_stored_valid",-1,3,0); + vcdp->declArray(c+174,"cache_simX dmem_controller dcache eviction_addr_per_bank",-1,127,0); + vcdp->declBus(c+819,"cache_simX dmem_controller dcache miss_addr",-1,31,0); + vcdp->declBit(c+178,"cache_simX dmem_controller dcache curr_processor_request_valid",-1); + vcdp->declBus(c+179,"cache_simX dmem_controller dcache threads_serviced_Qual",-1,3,0); + {int i; for (i=0; i<4; i++) { + vcdp->declBus(c+180+i*1,"cache_simX dmem_controller dcache debug_hit_per_bank_mask",(i+0),3,0);}} + vcdp->declBus(c+3139,"cache_simX dmem_controller dcache test_bid",-1,31,0); + vcdp->declBus(c+184,"cache_simX dmem_controller dcache detect_bank_miss",-1,3,0); + vcdp->declBus(c+3139,"cache_simX dmem_controller dcache bbid",-1,31,0); + vcdp->declBit(c+714,"cache_simX dmem_controller dcache delay",-1); + vcdp->declBus(c+161,"cache_simX dmem_controller dcache send_index_to_bank",-1,7,0); + vcdp->declBus(c+185,"cache_simX dmem_controller dcache miss_bank_index",-1,1,0); + vcdp->declBit(c+186,"cache_simX dmem_controller dcache miss_found",-1); + vcdp->declBit(c+733,"cache_simX dmem_controller dcache update_global_way_to_evict",-1); + vcdp->declBus(c+3150,"cache_simX dmem_controller dcache init_b",-1,31,0); + vcdp->declBus(c+187,"cache_simX dmem_controller dcache genblk1[0] use_threads_track_banks",-1,3,0); + vcdp->declBus(c+188,"cache_simX dmem_controller dcache genblk1[0] use_thread_index",-1,1,0); + vcdp->declBit(c+189,"cache_simX dmem_controller dcache genblk1[0] use_write_final_data",-1); + vcdp->declBus(c+190,"cache_simX dmem_controller dcache genblk1[0] use_data_final_data",-1,31,0); + vcdp->declBus(c+191,"cache_simX dmem_controller dcache genblk1[1] use_threads_track_banks",-1,3,0); + vcdp->declBus(c+192,"cache_simX dmem_controller dcache genblk1[1] use_thread_index",-1,1,0); + vcdp->declBit(c+193,"cache_simX dmem_controller dcache genblk1[1] use_write_final_data",-1); + vcdp->declBus(c+194,"cache_simX dmem_controller dcache genblk1[1] use_data_final_data",-1,31,0); + vcdp->declBus(c+195,"cache_simX dmem_controller dcache genblk1[2] use_threads_track_banks",-1,3,0); + vcdp->declBus(c+196,"cache_simX dmem_controller dcache genblk1[2] use_thread_index",-1,1,0); + vcdp->declBit(c+197,"cache_simX dmem_controller dcache genblk1[2] use_write_final_data",-1); + vcdp->declBus(c+198,"cache_simX dmem_controller dcache genblk1[2] use_data_final_data",-1,31,0); + vcdp->declBus(c+199,"cache_simX dmem_controller dcache genblk1[3] use_threads_track_banks",-1,3,0); + vcdp->declBus(c+200,"cache_simX dmem_controller dcache genblk1[3] use_thread_index",-1,1,0); + vcdp->declBit(c+201,"cache_simX dmem_controller dcache genblk1[3] use_write_final_data",-1); + vcdp->declBus(c+202,"cache_simX dmem_controller dcache genblk1[3] use_data_final_data",-1,31,0); + vcdp->declBus(c+203,"cache_simX dmem_controller dcache genblk3[0] bank_addr",-1,31,0); + vcdp->declBus(c+204,"cache_simX dmem_controller dcache genblk3[0] byte_select",-1,1,0); + vcdp->declBus(c+205,"cache_simX dmem_controller dcache genblk3[0] cache_offset",-1,1,0); + vcdp->declBus(c+206,"cache_simX dmem_controller dcache genblk3[0] cache_index",-1,4,0); + vcdp->declBus(c+207,"cache_simX dmem_controller dcache genblk3[0] cache_tag",-1,20,0); + vcdp->declBit(c+208,"cache_simX dmem_controller dcache genblk3[0] normal_valid_in",-1); + vcdp->declBit(c+209,"cache_simX dmem_controller dcache genblk3[0] use_valid_in",-1); + vcdp->declBus(c+210,"cache_simX dmem_controller dcache genblk3[1] bank_addr",-1,31,0); + vcdp->declBus(c+211,"cache_simX dmem_controller dcache genblk3[1] byte_select",-1,1,0); + vcdp->declBus(c+212,"cache_simX dmem_controller dcache genblk3[1] cache_offset",-1,1,0); + vcdp->declBus(c+213,"cache_simX dmem_controller dcache genblk3[1] cache_index",-1,4,0); + vcdp->declBus(c+214,"cache_simX dmem_controller dcache genblk3[1] cache_tag",-1,20,0); + vcdp->declBit(c+215,"cache_simX dmem_controller dcache genblk3[1] normal_valid_in",-1); + vcdp->declBit(c+216,"cache_simX dmem_controller dcache genblk3[1] use_valid_in",-1); + vcdp->declBus(c+217,"cache_simX dmem_controller dcache genblk3[2] bank_addr",-1,31,0); + vcdp->declBus(c+218,"cache_simX dmem_controller dcache genblk3[2] byte_select",-1,1,0); + vcdp->declBus(c+219,"cache_simX dmem_controller dcache genblk3[2] cache_offset",-1,1,0); + vcdp->declBus(c+220,"cache_simX dmem_controller dcache genblk3[2] cache_index",-1,4,0); + vcdp->declBus(c+221,"cache_simX dmem_controller dcache genblk3[2] cache_tag",-1,20,0); + vcdp->declBit(c+222,"cache_simX dmem_controller dcache genblk3[2] normal_valid_in",-1); + vcdp->declBit(c+223,"cache_simX dmem_controller dcache genblk3[2] use_valid_in",-1); + vcdp->declBus(c+224,"cache_simX dmem_controller dcache genblk3[3] bank_addr",-1,31,0); + vcdp->declBus(c+225,"cache_simX dmem_controller dcache genblk3[3] byte_select",-1,1,0); + vcdp->declBus(c+226,"cache_simX dmem_controller dcache genblk3[3] cache_offset",-1,1,0); + vcdp->declBus(c+227,"cache_simX dmem_controller dcache genblk3[3] cache_index",-1,4,0); + vcdp->declBus(c+228,"cache_simX dmem_controller dcache genblk3[3] cache_tag",-1,20,0); + vcdp->declBit(c+229,"cache_simX dmem_controller dcache genblk3[3] normal_valid_in",-1); + vcdp->declBit(c+230,"cache_simX dmem_controller dcache genblk3[3] use_valid_in",-1); + vcdp->declBus(c+3102,"cache_simX dmem_controller dcache multip_banks NUMBER_BANKS",-1,31,0); + vcdp->declBus(c+3133,"cache_simX dmem_controller dcache multip_banks LOG_NUM_BANKS",-1,31,0); + vcdp->declBus(c+3102,"cache_simX dmem_controller dcache multip_banks NUM_REQ",-1,31,0); + vcdp->declBus(c+172,"cache_simX dmem_controller dcache multip_banks i_p_valid",-1,3,0); + vcdp->declArray(c+23,"cache_simX dmem_controller dcache multip_banks i_p_addr",-1,127,0); + vcdp->declBus(c+160,"cache_simX dmem_controller dcache multip_banks thread_track_banks",-1,15,0); + vcdp->declBus(c+3139,"cache_simX dmem_controller dcache multip_banks t_id",-1,31,0); + vcdp->declBus(c+3102,"cache_simX dmem_controller dcache get_miss_index N",-1,31,0); + vcdp->declBus(c+184,"cache_simX dmem_controller dcache get_miss_index valids",-1,3,0); + vcdp->declBus(c+185,"cache_simX dmem_controller dcache get_miss_index index",-1,1,0); + vcdp->declBit(c+186,"cache_simX dmem_controller dcache get_miss_index found",-1); + vcdp->declBus(c+231,"cache_simX dmem_controller dcache get_miss_index i",-1,31,0); + vcdp->declBus(c+3102,"cache_simX dmem_controller dcache genblk1[0] choose_thread N",-1,31,0); + vcdp->declBus(c+187,"cache_simX dmem_controller dcache genblk1[0] choose_thread valids",-1,3,0); + vcdp->declBus(c+232,"cache_simX dmem_controller dcache genblk1[0] choose_thread mask",-1,3,0); + vcdp->declBus(c+233,"cache_simX dmem_controller dcache genblk1[0] choose_thread index",-1,1,0); + vcdp->declBit(c+234,"cache_simX dmem_controller dcache genblk1[0] choose_thread found",-1); + vcdp->declBus(c+235,"cache_simX dmem_controller dcache genblk1[0] choose_thread i",-1,31,0); + vcdp->declBus(c+3102,"cache_simX dmem_controller dcache genblk1[1] choose_thread N",-1,31,0); + vcdp->declBus(c+191,"cache_simX dmem_controller dcache genblk1[1] choose_thread valids",-1,3,0); + vcdp->declBus(c+236,"cache_simX dmem_controller dcache genblk1[1] choose_thread mask",-1,3,0); + vcdp->declBus(c+237,"cache_simX dmem_controller dcache genblk1[1] choose_thread index",-1,1,0); + vcdp->declBit(c+238,"cache_simX dmem_controller dcache genblk1[1] choose_thread found",-1); + vcdp->declBus(c+239,"cache_simX dmem_controller dcache genblk1[1] choose_thread i",-1,31,0); + vcdp->declBus(c+3102,"cache_simX dmem_controller dcache genblk1[2] choose_thread N",-1,31,0); + vcdp->declBus(c+195,"cache_simX dmem_controller dcache genblk1[2] choose_thread valids",-1,3,0); + vcdp->declBus(c+240,"cache_simX dmem_controller dcache genblk1[2] choose_thread mask",-1,3,0); + vcdp->declBus(c+241,"cache_simX dmem_controller dcache genblk1[2] choose_thread index",-1,1,0); + vcdp->declBit(c+242,"cache_simX dmem_controller dcache genblk1[2] choose_thread found",-1); + vcdp->declBus(c+243,"cache_simX dmem_controller dcache genblk1[2] choose_thread i",-1,31,0); + vcdp->declBus(c+3102,"cache_simX dmem_controller dcache genblk1[3] choose_thread N",-1,31,0); + vcdp->declBus(c+199,"cache_simX dmem_controller dcache genblk1[3] choose_thread valids",-1,3,0); + vcdp->declBus(c+244,"cache_simX dmem_controller dcache genblk1[3] choose_thread mask",-1,3,0); + vcdp->declBus(c+245,"cache_simX dmem_controller dcache genblk1[3] choose_thread index",-1,1,0); + vcdp->declBit(c+246,"cache_simX dmem_controller dcache genblk1[3] choose_thread found",-1); + vcdp->declBus(c+247,"cache_simX dmem_controller dcache genblk1[3] choose_thread i",-1,31,0); + vcdp->declBus(c+3151,"cache_simX dmem_controller icache CACHE_SIZE",-1,31,0); + vcdp->declBus(c+3133,"cache_simX dmem_controller icache CACHE_WAYS",-1,31,0); + vcdp->declBus(c+3132,"cache_simX dmem_controller icache CACHE_BLOCK",-1,31,0); + vcdp->declBus(c+3119,"cache_simX dmem_controller icache CACHE_BANKS",-1,31,0); + vcdp->declBus(c+3119,"cache_simX dmem_controller icache LOG_NUM_BANKS",-1,31,0); + vcdp->declBus(c+3119,"cache_simX dmem_controller icache NUM_REQ",-1,31,0); + vcdp->declBus(c+3119,"cache_simX dmem_controller icache LOG_NUM_REQ",-1,31,0); + vcdp->declBus(c+3143,"cache_simX dmem_controller icache NUM_IND",-1,31,0); + vcdp->declBus(c+3119,"cache_simX dmem_controller icache CACHE_WAY_INDEX",-1,31,0); + vcdp->declBus(c+3102,"cache_simX dmem_controller icache NUM_WORDS_PER_BLOCK",-1,31,0); + vcdp->declBus(c+3125,"cache_simX dmem_controller icache OFFSET_SIZE_START",-1,31,0); + vcdp->declBus(c+3119,"cache_simX dmem_controller icache OFFSET_SIZE_END",-1,31,0); + vcdp->declBus(c+3125,"cache_simX dmem_controller icache TAG_SIZE_START",-1,31,0); + vcdp->declBus(c+3152,"cache_simX dmem_controller icache TAG_SIZE_END",-1,31,0); + vcdp->declBus(c+3125,"cache_simX dmem_controller icache IND_SIZE_START",-1,31,0); + vcdp->declBus(c+3102,"cache_simX dmem_controller icache IND_SIZE_END",-1,31,0); + vcdp->declBus(c+3153,"cache_simX dmem_controller icache ADDR_TAG_START",-1,31,0); + vcdp->declBus(c+3146,"cache_simX dmem_controller icache ADDR_TAG_END",-1,31,0); + vcdp->declBus(c+3133,"cache_simX dmem_controller icache ADDR_OFFSET_START",-1,31,0); + vcdp->declBus(c+3135,"cache_simX dmem_controller icache ADDR_OFFSET_END",-1,31,0); + vcdp->declBus(c+3102,"cache_simX dmem_controller icache ADDR_IND_START",-1,31,0); + vcdp->declBus(c+3154,"cache_simX dmem_controller icache ADDR_IND_END",-1,31,0); + vcdp->declBus(c+3155,"cache_simX dmem_controller icache MEM_ADDR_REQ_MASK",-1,31,0); + vcdp->declBus(c+3125,"cache_simX dmem_controller icache CACHE_IDLE",-1,31,0); + vcdp->declBus(c+3119,"cache_simX dmem_controller icache SEND_MEM_REQ",-1,31,0); + vcdp->declBus(c+3133,"cache_simX dmem_controller icache RECIV_MEM_RSP",-1,31,0); + vcdp->declBit(c+3085,"cache_simX dmem_controller icache clk",-1); + vcdp->declBit(c+3086,"cache_simX dmem_controller icache rst",-1); + vcdp->declBus(c+3088,"cache_simX dmem_controller icache i_p_valid",-1,0,0); + vcdp->declBus(c+3087,"cache_simX dmem_controller icache i_p_addr",-1,31,0); + vcdp->declBus(c+3125,"cache_simX dmem_controller icache i_p_writedata",-1,31,0); + vcdp->declBit(c+3130,"cache_simX dmem_controller icache i_p_read_or_write",-1); + vcdp->declBus(c+711,"cache_simX dmem_controller icache o_p_readdata",-1,31,0); + vcdp->declBit(c+712,"cache_simX dmem_controller icache o_p_delay",-1); + vcdp->declBus(c+18,"cache_simX dmem_controller icache o_m_evict_addr",-1,31,0); + vcdp->declBus(c+804,"cache_simX dmem_controller icache o_m_read_addr",-1,31,0); + vcdp->declBit(c+805,"cache_simX dmem_controller icache o_m_valid",-1); + vcdp->declArray(c+19,"cache_simX dmem_controller icache o_m_writedata",-1,127,0); + vcdp->declBit(c+710,"cache_simX dmem_controller icache o_m_read_or_write",-1); + vcdp->declArray(c+3120,"cache_simX dmem_controller icache i_m_readdata",-1,127,0); + vcdp->declBit(c+800,"cache_simX dmem_controller icache i_m_ready",-1); + vcdp->declBus(c+50,"cache_simX dmem_controller icache i_p_mem_read",-1,2,0); + vcdp->declBus(c+3124,"cache_simX dmem_controller icache i_p_mem_write",-1,2,0); + vcdp->declBus(c+820,"cache_simX dmem_controller icache final_data_read",-1,31,0); + vcdp->declBus(c+248,"cache_simX dmem_controller icache new_final_data_read",-1,31,0); + vcdp->declBus(c+711,"cache_simX dmem_controller icache new_final_data_read_Qual",-1,31,0); + vcdp->declBus(c+821,"cache_simX dmem_controller icache global_way_to_evict",-1,0,0); + vcdp->declBus(c+249,"cache_simX dmem_controller icache thread_track_banks",-1,0,0); + vcdp->declBus(c+250,"cache_simX dmem_controller icache index_per_bank",-1,0,0); + vcdp->declBus(c+251,"cache_simX dmem_controller icache use_mask_per_bank",-1,0,0); + vcdp->declBus(c+252,"cache_simX dmem_controller icache valid_per_bank",-1,0,0); + vcdp->declBus(c+253,"cache_simX dmem_controller icache threads_serviced_per_bank",-1,0,0); + vcdp->declBus(c+254,"cache_simX dmem_controller icache readdata_per_bank",-1,31,0); + vcdp->declBus(c+255,"cache_simX dmem_controller icache hit_per_bank",-1,0,0); + vcdp->declBus(c+256,"cache_simX dmem_controller icache eviction_wb",-1,0,0); + vcdp->declBus(c+3156,"cache_simX dmem_controller icache eviction_wb_old",-1,0,0); + vcdp->declBus(c+822,"cache_simX dmem_controller icache state",-1,3,0); + vcdp->declBus(c+257,"cache_simX dmem_controller icache new_state",-1,3,0); + vcdp->declBus(c+258,"cache_simX dmem_controller icache use_valid",-1,0,0); + vcdp->declBus(c+823,"cache_simX dmem_controller icache stored_valid",-1,0,0); + vcdp->declBus(c+259,"cache_simX dmem_controller icache new_stored_valid",-1,0,0); + vcdp->declBus(c+260,"cache_simX dmem_controller icache eviction_addr_per_bank",-1,31,0); + vcdp->declBus(c+824,"cache_simX dmem_controller icache miss_addr",-1,31,0); + vcdp->declBit(c+3088,"cache_simX dmem_controller icache curr_processor_request_valid",-1); + vcdp->declBus(c+261,"cache_simX dmem_controller icache threads_serviced_Qual",-1,0,0); + {int i; for (i=0; i<1; i++) { + vcdp->declBus(c+262+i*1,"cache_simX dmem_controller icache debug_hit_per_bank_mask",(i+0),0,0);}} + vcdp->declBus(c+3157,"cache_simX dmem_controller icache test_bid",-1,31,0); + vcdp->declBus(c+263,"cache_simX dmem_controller icache detect_bank_miss",-1,0,0); + vcdp->declBus(c+3157,"cache_simX dmem_controller icache bbid",-1,31,0); + vcdp->declBit(c+712,"cache_simX dmem_controller icache delay",-1); + vcdp->declBus(c+250,"cache_simX dmem_controller icache send_index_to_bank",-1,0,0); + vcdp->declBus(c+264,"cache_simX dmem_controller icache miss_bank_index",-1,0,0); + vcdp->declBit(c+265,"cache_simX dmem_controller icache miss_found",-1); + vcdp->declBit(c+734,"cache_simX dmem_controller icache update_global_way_to_evict",-1); + vcdp->declBus(c+3158,"cache_simX dmem_controller icache init_b",-1,31,0); + vcdp->declBus(c+249,"cache_simX dmem_controller icache genblk1[0] use_threads_track_banks",-1,0,0); + vcdp->declBus(c+250,"cache_simX dmem_controller icache genblk1[0] use_thread_index",-1,0,0); + vcdp->declBit(c+266,"cache_simX dmem_controller icache genblk1[0] use_write_final_data",-1); + vcdp->declBus(c+254,"cache_simX dmem_controller icache genblk1[0] use_data_final_data",-1,31,0); + vcdp->declBus(c+267,"cache_simX dmem_controller icache genblk3[0] bank_addr",-1,31,0); + vcdp->declBus(c+268,"cache_simX dmem_controller icache genblk3[0] byte_select",-1,1,0); + vcdp->declBus(c+269,"cache_simX dmem_controller icache genblk3[0] cache_offset",-1,1,0); + vcdp->declBus(c+270,"cache_simX dmem_controller icache genblk3[0] cache_index",-1,4,0); + vcdp->declBus(c+271,"cache_simX dmem_controller icache genblk3[0] cache_tag",-1,22,0); + vcdp->declBit(c+272,"cache_simX dmem_controller icache genblk3[0] normal_valid_in",-1); + vcdp->declBit(c+273,"cache_simX dmem_controller icache genblk3[0] use_valid_in",-1); + vcdp->declBus(c+3119,"cache_simX dmem_controller icache multip_banks NUMBER_BANKS",-1,31,0); + vcdp->declBus(c+3119,"cache_simX dmem_controller icache multip_banks LOG_NUM_BANKS",-1,31,0); + vcdp->declBus(c+3119,"cache_simX dmem_controller icache multip_banks NUM_REQ",-1,31,0); + vcdp->declBus(c+258,"cache_simX dmem_controller icache multip_banks i_p_valid",-1,0,0); + vcdp->declBus(c+3087,"cache_simX dmem_controller icache multip_banks i_p_addr",-1,31,0); + vcdp->declBus(c+249,"cache_simX dmem_controller icache multip_banks thread_track_banks",-1,0,0); + vcdp->declBus(c+3157,"cache_simX dmem_controller icache multip_banks t_id",-1,31,0); + vcdp->declBus(c+3119,"cache_simX dmem_controller icache get_miss_index N",-1,31,0); + vcdp->declBus(c+263,"cache_simX dmem_controller icache get_miss_index valids",-1,0,0); + vcdp->declBus(c+264,"cache_simX dmem_controller icache get_miss_index index",-1,0,0); + vcdp->declBit(c+265,"cache_simX dmem_controller icache get_miss_index found",-1); + vcdp->declBus(c+3140,"cache_simX dmem_controller icache get_miss_index i",-1,31,0); + vcdp->declBus(c+3119,"cache_simX dmem_controller icache genblk1[0] choose_thread N",-1,31,0); + vcdp->declBus(c+249,"cache_simX dmem_controller icache genblk1[0] choose_thread valids",-1,0,0); + vcdp->declBus(c+251,"cache_simX dmem_controller icache genblk1[0] choose_thread mask",-1,0,0); + vcdp->declBus(c+250,"cache_simX dmem_controller icache genblk1[0] choose_thread index",-1,0,0); + vcdp->declBit(c+252,"cache_simX dmem_controller icache genblk1[0] choose_thread found",-1); + vcdp->declBus(c+3157,"cache_simX dmem_controller icache genblk1[0] choose_thread i",-1,31,0); + vcdp->declBus(c+3151,"cache_simX dmem_controller icache genblk3[0] bank_structure CACHE_SIZE",-1,31,0); + vcdp->declBus(c+3133,"cache_simX dmem_controller icache genblk3[0] bank_structure CACHE_WAYS",-1,31,0); + vcdp->declBus(c+3132,"cache_simX dmem_controller icache genblk3[0] bank_structure CACHE_BLOCK",-1,31,0); + vcdp->declBus(c+3119,"cache_simX dmem_controller icache genblk3[0] bank_structure CACHE_BANKS",-1,31,0); + vcdp->declBus(c+3119,"cache_simX dmem_controller icache genblk3[0] bank_structure LOG_NUM_BANKS",-1,31,0); + vcdp->declBus(c+3119,"cache_simX dmem_controller icache genblk3[0] bank_structure NUM_REQ",-1,31,0); + vcdp->declBus(c+3119,"cache_simX dmem_controller icache genblk3[0] bank_structure LOG_NUM_REQ",-1,31,0); + vcdp->declBus(c+3143,"cache_simX dmem_controller icache genblk3[0] bank_structure NUM_IND",-1,31,0); + vcdp->declBus(c+3119,"cache_simX dmem_controller icache genblk3[0] bank_structure CACHE_WAY_INDEX",-1,31,0); + vcdp->declBus(c+3102,"cache_simX dmem_controller icache genblk3[0] bank_structure NUM_WORDS_PER_BLOCK",-1,31,0); + vcdp->declBus(c+3125,"cache_simX dmem_controller icache genblk3[0] bank_structure OFFSET_SIZE_START",-1,31,0); + vcdp->declBus(c+3119,"cache_simX dmem_controller icache genblk3[0] bank_structure OFFSET_SIZE_END",-1,31,0); + vcdp->declBus(c+3125,"cache_simX dmem_controller icache genblk3[0] bank_structure TAG_SIZE_START",-1,31,0); + vcdp->declBus(c+3152,"cache_simX dmem_controller icache genblk3[0] bank_structure TAG_SIZE_END",-1,31,0); + vcdp->declBus(c+3125,"cache_simX dmem_controller icache genblk3[0] bank_structure IND_SIZE_START",-1,31,0); + vcdp->declBus(c+3102,"cache_simX dmem_controller icache genblk3[0] bank_structure IND_SIZE_END",-1,31,0); + vcdp->declBus(c+3153,"cache_simX dmem_controller icache genblk3[0] bank_structure ADDR_TAG_START",-1,31,0); + vcdp->declBus(c+3146,"cache_simX dmem_controller icache genblk3[0] bank_structure ADDR_TAG_END",-1,31,0); + vcdp->declBus(c+3133,"cache_simX dmem_controller icache genblk3[0] bank_structure ADDR_OFFSET_START",-1,31,0); + vcdp->declBus(c+3135,"cache_simX dmem_controller icache genblk3[0] bank_structure ADDR_OFFSET_END",-1,31,0); + vcdp->declBus(c+3102,"cache_simX dmem_controller icache genblk3[0] bank_structure ADDR_IND_START",-1,31,0); + vcdp->declBus(c+3154,"cache_simX dmem_controller icache genblk3[0] bank_structure ADDR_IND_END",-1,31,0); + vcdp->declBus(c+3125,"cache_simX dmem_controller icache genblk3[0] bank_structure CACHE_IDLE",-1,31,0); + vcdp->declBus(c+3119,"cache_simX dmem_controller icache genblk3[0] bank_structure SEND_MEM_REQ",-1,31,0); + vcdp->declBus(c+3133,"cache_simX dmem_controller icache genblk3[0] bank_structure RECIV_MEM_RSP",-1,31,0); + vcdp->declBus(c+3102,"cache_simX dmem_controller icache genblk3[0] bank_structure BLOCK_NUM_BITS",-1,31,0); + vcdp->declBit(c+3086,"cache_simX dmem_controller icache genblk3[0] bank_structure rst",-1); + vcdp->declBit(c+3085,"cache_simX dmem_controller icache genblk3[0] bank_structure clk",-1); + vcdp->declBus(c+822,"cache_simX dmem_controller icache genblk3[0] bank_structure state",-1,3,0); + vcdp->declBus(c+270,"cache_simX dmem_controller icache genblk3[0] bank_structure actual_index",-1,4,0); + vcdp->declBus(c+271,"cache_simX dmem_controller icache genblk3[0] bank_structure o_tag",-1,22,0); + vcdp->declBus(c+269,"cache_simX dmem_controller icache genblk3[0] bank_structure block_offset",-1,1,0); + vcdp->declBus(c+274,"cache_simX dmem_controller icache genblk3[0] bank_structure writedata",-1,31,0); + vcdp->declBit(c+273,"cache_simX dmem_controller icache genblk3[0] bank_structure valid_in",-1); + vcdp->declBit(c+3130,"cache_simX dmem_controller icache genblk3[0] bank_structure read_or_write",-1); + vcdp->declArray(c+3120,"cache_simX dmem_controller icache genblk3[0] bank_structure fetched_writedata",-1,127,0); + vcdp->declBus(c+50,"cache_simX dmem_controller icache genblk3[0] bank_structure i_p_mem_read",-1,2,0); + vcdp->declBus(c+3124,"cache_simX dmem_controller icache genblk3[0] bank_structure i_p_mem_write",-1,2,0); + vcdp->declBus(c+268,"cache_simX dmem_controller icache genblk3[0] bank_structure byte_select",-1,1,0); + vcdp->declBus(c+821,"cache_simX dmem_controller icache genblk3[0] bank_structure evicted_way",-1,0,0); + vcdp->declBus(c+254,"cache_simX dmem_controller icache genblk3[0] bank_structure readdata",-1,31,0); + vcdp->declBit(c+255,"cache_simX dmem_controller icache genblk3[0] bank_structure hit",-1); + vcdp->declBit(c+256,"cache_simX dmem_controller icache genblk3[0] bank_structure eviction_wb",-1); + vcdp->declBus(c+260,"cache_simX dmem_controller icache genblk3[0] bank_structure eviction_addr",-1,31,0); + vcdp->declArray(c+19,"cache_simX dmem_controller icache genblk3[0] bank_structure data_evicted",-1,127,0); + vcdp->declArray(c+19,"cache_simX dmem_controller icache genblk3[0] bank_structure data_use",-1,127,0); + vcdp->declBus(c+275,"cache_simX dmem_controller icache genblk3[0] bank_structure tag_use",-1,22,0); + vcdp->declBus(c+275,"cache_simX dmem_controller icache genblk3[0] bank_structure eviction_tag",-1,22,0); + vcdp->declBit(c+276,"cache_simX dmem_controller icache genblk3[0] bank_structure valid_use",-1); + vcdp->declBit(c+256,"cache_simX dmem_controller icache genblk3[0] bank_structure dirty_use",-1); + vcdp->declBit(c+277,"cache_simX dmem_controller icache genblk3[0] bank_structure access",-1); + vcdp->declBit(c+278,"cache_simX dmem_controller icache genblk3[0] bank_structure write_from_mem",-1); + vcdp->declBit(c+279,"cache_simX dmem_controller icache genblk3[0] bank_structure miss",-1); + vcdp->declBus(c+795,"cache_simX dmem_controller icache genblk3[0] bank_structure way_to_update",-1,0,0); + vcdp->declBit(c+280,"cache_simX dmem_controller icache genblk3[0] bank_structure lw",-1); + vcdp->declBit(c+281,"cache_simX dmem_controller icache genblk3[0] bank_structure lb",-1); + vcdp->declBit(c+282,"cache_simX dmem_controller icache genblk3[0] bank_structure lh",-1); + vcdp->declBit(c+283,"cache_simX dmem_controller icache genblk3[0] bank_structure lhu",-1); + vcdp->declBit(c+284,"cache_simX dmem_controller icache genblk3[0] bank_structure lbu",-1); + vcdp->declBit(c+3130,"cache_simX dmem_controller icache genblk3[0] bank_structure sw",-1); + vcdp->declBit(c+3130,"cache_simX dmem_controller icache genblk3[0] bank_structure sb",-1); + vcdp->declBit(c+3130,"cache_simX dmem_controller icache genblk3[0] bank_structure sh",-1); + vcdp->declBit(c+285,"cache_simX dmem_controller icache genblk3[0] bank_structure b0",-1); + vcdp->declBit(c+286,"cache_simX dmem_controller icache genblk3[0] bank_structure b1",-1); + vcdp->declBit(c+287,"cache_simX dmem_controller icache genblk3[0] bank_structure b2",-1); + vcdp->declBit(c+288,"cache_simX dmem_controller icache genblk3[0] bank_structure b3",-1); + vcdp->declBus(c+289,"cache_simX dmem_controller icache genblk3[0] bank_structure data_unQual",-1,31,0); + vcdp->declBus(c+290,"cache_simX dmem_controller icache genblk3[0] bank_structure lb_data",-1,31,0); + vcdp->declBus(c+291,"cache_simX dmem_controller icache genblk3[0] bank_structure lh_data",-1,31,0); + vcdp->declBus(c+292,"cache_simX dmem_controller icache genblk3[0] bank_structure lbu_data",-1,31,0); + vcdp->declBus(c+293,"cache_simX dmem_controller icache genblk3[0] bank_structure lhu_data",-1,31,0); + vcdp->declBus(c+289,"cache_simX dmem_controller icache genblk3[0] bank_structure lw_data",-1,31,0); + vcdp->declBus(c+274,"cache_simX dmem_controller icache genblk3[0] bank_structure sw_data",-1,31,0); + vcdp->declBus(c+294,"cache_simX dmem_controller icache genblk3[0] bank_structure sb_data",-1,31,0); + vcdp->declBus(c+295,"cache_simX dmem_controller icache genblk3[0] bank_structure sh_data",-1,31,0); + vcdp->declBus(c+274,"cache_simX dmem_controller icache genblk3[0] bank_structure use_write_data",-1,31,0); + vcdp->declBus(c+296,"cache_simX dmem_controller icache genblk3[0] bank_structure data_Qual",-1,31,0); + vcdp->declBus(c+297,"cache_simX dmem_controller icache genblk3[0] bank_structure sb_mask",-1,3,0); + vcdp->declBus(c+298,"cache_simX dmem_controller icache genblk3[0] bank_structure sh_mask",-1,3,0); + vcdp->declBus(c+299,"cache_simX dmem_controller icache genblk3[0] bank_structure we",-1,15,0); + vcdp->declArray(c+300,"cache_simX dmem_controller icache genblk3[0] bank_structure data_write",-1,127,0); + vcdp->declBit(c+3130,"cache_simX dmem_controller icache genblk3[0] bank_structure genblk1[0] normal_write",-1); + vcdp->declBit(c+3130,"cache_simX dmem_controller icache genblk3[0] bank_structure genblk1[1] normal_write",-1); + vcdp->declBit(c+3130,"cache_simX dmem_controller icache genblk3[0] bank_structure genblk1[2] normal_write",-1); + vcdp->declBit(c+3130,"cache_simX dmem_controller icache genblk3[0] bank_structure genblk1[3] normal_write",-1); + vcdp->declBus(c+3133,"cache_simX dmem_controller icache genblk3[0] bank_structure data_structures CACHE_WAYS",-1,31,0); + vcdp->declBus(c+3143,"cache_simX dmem_controller icache genblk3[0] bank_structure data_structures NUM_IND",-1,31,0); + vcdp->declBus(c+3119,"cache_simX dmem_controller icache genblk3[0] bank_structure data_structures CACHE_WAY_INDEX",-1,31,0); + vcdp->declBus(c+3102,"cache_simX dmem_controller icache genblk3[0] bank_structure data_structures NUM_WORDS_PER_BLOCK",-1,31,0); + vcdp->declBus(c+3125,"cache_simX dmem_controller icache genblk3[0] bank_structure data_structures TAG_SIZE_START",-1,31,0); + vcdp->declBus(c+3152,"cache_simX dmem_controller icache genblk3[0] bank_structure data_structures TAG_SIZE_END",-1,31,0); + vcdp->declBus(c+3125,"cache_simX dmem_controller icache genblk3[0] bank_structure data_structures IND_SIZE_START",-1,31,0); + vcdp->declBus(c+3102,"cache_simX dmem_controller icache genblk3[0] bank_structure data_structures IND_SIZE_END",-1,31,0); + vcdp->declBit(c+3085,"cache_simX dmem_controller icache genblk3[0] bank_structure data_structures clk",-1); + vcdp->declBit(c+3086,"cache_simX dmem_controller icache genblk3[0] bank_structure data_structures rst",-1); + vcdp->declBit(c+273,"cache_simX dmem_controller icache genblk3[0] bank_structure data_structures valid_in",-1); + vcdp->declBus(c+822,"cache_simX dmem_controller icache genblk3[0] bank_structure data_structures state",-1,3,0); + vcdp->declBus(c+270,"cache_simX dmem_controller icache genblk3[0] bank_structure data_structures addr",-1,4,0); + vcdp->declBus(c+299,"cache_simX dmem_controller icache genblk3[0] bank_structure data_structures we",-1,15,0); + vcdp->declBit(c+278,"cache_simX dmem_controller icache genblk3[0] bank_structure data_structures evict",-1); + vcdp->declBus(c+795,"cache_simX dmem_controller icache genblk3[0] bank_structure data_structures way_to_update",-1,0,0); + vcdp->declArray(c+300,"cache_simX dmem_controller icache genblk3[0] bank_structure data_structures data_write",-1,127,0); + vcdp->declBus(c+271,"cache_simX dmem_controller icache genblk3[0] bank_structure data_structures tag_write",-1,22,0); + vcdp->declBus(c+275,"cache_simX dmem_controller icache genblk3[0] bank_structure data_structures tag_use",-1,22,0); + vcdp->declArray(c+19,"cache_simX dmem_controller icache genblk3[0] bank_structure data_structures data_use",-1,127,0); + vcdp->declBit(c+276,"cache_simX dmem_controller icache genblk3[0] bank_structure data_structures valid_use",-1); + vcdp->declBit(c+256,"cache_simX dmem_controller icache genblk3[0] bank_structure data_structures dirty_use",-1); + vcdp->declQuad(c+304,"cache_simX dmem_controller icache genblk3[0] bank_structure data_structures tag_use_per_way",-1,45,0); + vcdp->declArray(c+306,"cache_simX dmem_controller icache genblk3[0] bank_structure data_structures data_use_per_way",-1,255,0); + vcdp->declBus(c+314,"cache_simX dmem_controller icache genblk3[0] bank_structure data_structures valid_use_per_way",-1,1,0); + vcdp->declBus(c+315,"cache_simX dmem_controller icache genblk3[0] bank_structure data_structures dirty_use_per_way",-1,1,0); + vcdp->declBus(c+316,"cache_simX dmem_controller icache genblk3[0] bank_structure data_structures hit_per_way",-1,1,0); + vcdp->declBus(c+317,"cache_simX dmem_controller icache genblk3[0] bank_structure data_structures we_per_way",-1,31,0); + vcdp->declArray(c+318,"cache_simX dmem_controller icache genblk3[0] bank_structure data_structures data_write_per_way",-1,255,0); + vcdp->declBus(c+326,"cache_simX dmem_controller icache genblk3[0] bank_structure data_structures write_from_mem_per_way",-1,1,0); + vcdp->declBit(c+327,"cache_simX dmem_controller icache genblk3[0] bank_structure data_structures invalid_found",-1); + vcdp->declBus(c+328,"cache_simX dmem_controller icache genblk3[0] bank_structure data_structures way_index",-1,0,0); + vcdp->declBus(c+329,"cache_simX dmem_controller icache genblk3[0] bank_structure data_structures invalid_index",-1,0,0); + vcdp->declBus(c+3125,"cache_simX dmem_controller icache genblk3[0] bank_structure data_structures CACHE_IDLE",-1,31,0); + vcdp->declBus(c+3119,"cache_simX dmem_controller icache genblk3[0] bank_structure data_structures SEND_MEM_REQ",-1,31,0); + vcdp->declBus(c+3133,"cache_simX dmem_controller icache genblk3[0] bank_structure data_structures RECIV_MEM_RSP",-1,31,0); + vcdp->declBus(c+330,"cache_simX dmem_controller icache genblk3[0] bank_structure data_structures way_use_Qual",-1,0,0); + vcdp->declBus(c+3133,"cache_simX dmem_controller icache genblk3[0] bank_structure data_structures genblk1 valid_index N",-1,31,0); + vcdp->declBus(c+331,"cache_simX dmem_controller icache genblk3[0] bank_structure data_structures genblk1 valid_index valids",-1,1,0); + vcdp->declBus(c+329,"cache_simX dmem_controller icache genblk3[0] bank_structure data_structures genblk1 valid_index index",-1,0,0); + vcdp->declBit(c+327,"cache_simX dmem_controller icache genblk3[0] bank_structure data_structures genblk1 valid_index found",-1); + vcdp->declBus(c+3140,"cache_simX dmem_controller icache genblk3[0] bank_structure data_structures genblk1 valid_index i",-1,31,0); + vcdp->declBus(c+3133,"cache_simX dmem_controller icache genblk3[0] bank_structure data_structures genblk1 way_indexing N",-1,31,0); + vcdp->declBus(c+316,"cache_simX dmem_controller icache genblk3[0] bank_structure data_structures genblk1 way_indexing valids",-1,1,0); + vcdp->declBus(c+328,"cache_simX dmem_controller icache genblk3[0] bank_structure data_structures genblk1 way_indexing index",-1,0,0); + vcdp->declBit(c+332,"cache_simX dmem_controller icache genblk3[0] bank_structure data_structures genblk1 way_indexing found",-1); + vcdp->declBus(c+3140,"cache_simX dmem_controller icache genblk3[0] bank_structure data_structures genblk1 way_indexing i",-1,31,0); + vcdp->declBus(c+3143,"cache_simX dmem_controller icache genblk3[0] bank_structure data_structures each_way[0] data_structures NUM_IND",-1,31,0); + vcdp->declBus(c+3102,"cache_simX dmem_controller icache genblk3[0] bank_structure data_structures each_way[0] data_structures NUM_WORDS_PER_BLOCK",-1,31,0); + vcdp->declBus(c+3125,"cache_simX dmem_controller icache genblk3[0] bank_structure data_structures each_way[0] data_structures TAG_SIZE_START",-1,31,0); + vcdp->declBus(c+3152,"cache_simX dmem_controller icache genblk3[0] bank_structure data_structures each_way[0] data_structures TAG_SIZE_END",-1,31,0); + vcdp->declBus(c+3125,"cache_simX dmem_controller icache genblk3[0] bank_structure data_structures each_way[0] data_structures IND_SIZE_START",-1,31,0); + vcdp->declBus(c+3102,"cache_simX dmem_controller icache genblk3[0] bank_structure data_structures each_way[0] data_structures IND_SIZE_END",-1,31,0); + vcdp->declBit(c+3085,"cache_simX dmem_controller icache genblk3[0] bank_structure data_structures each_way[0] data_structures clk",-1); + vcdp->declBit(c+3086,"cache_simX dmem_controller icache genblk3[0] bank_structure data_structures each_way[0] data_structures rst",-1); + vcdp->declBus(c+270,"cache_simX dmem_controller icache genblk3[0] bank_structure data_structures each_way[0] data_structures addr",-1,4,0); + vcdp->declBus(c+333,"cache_simX dmem_controller icache genblk3[0] bank_structure data_structures each_way[0] data_structures we",-1,15,0); + vcdp->declBit(c+334,"cache_simX dmem_controller icache genblk3[0] bank_structure data_structures each_way[0] data_structures evict",-1); + vcdp->declArray(c+335,"cache_simX dmem_controller icache genblk3[0] bank_structure data_structures each_way[0] data_structures data_write",-1,127,0); + vcdp->declBus(c+271,"cache_simX dmem_controller icache genblk3[0] bank_structure data_structures each_way[0] data_structures tag_write",-1,22,0); + vcdp->declBus(c+735,"cache_simX dmem_controller icache genblk3[0] bank_structure data_structures each_way[0] data_structures tag_use",-1,22,0); + vcdp->declArray(c+736,"cache_simX dmem_controller icache genblk3[0] bank_structure data_structures each_way[0] data_structures data_use",-1,127,0); + vcdp->declBit(c+740,"cache_simX dmem_controller icache genblk3[0] bank_structure data_structures each_way[0] data_structures valid_use",-1); + vcdp->declBit(c+339,"cache_simX dmem_controller icache genblk3[0] bank_structure data_structures each_way[0] data_structures dirty_use",-1); + vcdp->declBit(c+340,"cache_simX dmem_controller icache genblk3[0] bank_structure data_structures each_way[0] data_structures currently_writing",-1); + vcdp->declBit(c+341,"cache_simX dmem_controller icache genblk3[0] bank_structure data_structures each_way[0] data_structures update_dirty",-1); + vcdp->declBit(c+342,"cache_simX dmem_controller icache genblk3[0] bank_structure data_structures each_way[0] data_structures dirt_new",-1); + vcdp->declArray(c+825,"cache_simX dmem_controller icache genblk3[0] bank_structure data_structures each_way[0] data_structures data(0)",-1,127,0); + vcdp->declArray(c+829,"cache_simX dmem_controller icache genblk3[0] bank_structure data_structures each_way[0] data_structures data(1)",-1,127,0); + vcdp->declArray(c+833,"cache_simX dmem_controller icache genblk3[0] bank_structure data_structures each_way[0] data_structures data(2)",-1,127,0); + vcdp->declArray(c+837,"cache_simX dmem_controller icache genblk3[0] bank_structure data_structures each_way[0] data_structures data(3)",-1,127,0); + vcdp->declArray(c+841,"cache_simX dmem_controller icache genblk3[0] bank_structure data_structures each_way[0] data_structures data(4)",-1,127,0); + vcdp->declArray(c+845,"cache_simX dmem_controller icache genblk3[0] bank_structure data_structures each_way[0] data_structures data(5)",-1,127,0); + vcdp->declArray(c+849,"cache_simX dmem_controller icache genblk3[0] bank_structure data_structures each_way[0] data_structures data(6)",-1,127,0); + vcdp->declArray(c+853,"cache_simX dmem_controller icache genblk3[0] bank_structure data_structures each_way[0] data_structures data(7)",-1,127,0); + vcdp->declArray(c+857,"cache_simX dmem_controller icache genblk3[0] bank_structure data_structures each_way[0] data_structures data(8)",-1,127,0); + vcdp->declArray(c+861,"cache_simX dmem_controller icache genblk3[0] bank_structure data_structures each_way[0] data_structures data(9)",-1,127,0); + vcdp->declArray(c+865,"cache_simX dmem_controller icache genblk3[0] bank_structure data_structures each_way[0] data_structures data(10)",-1,127,0); + vcdp->declArray(c+869,"cache_simX dmem_controller icache genblk3[0] bank_structure data_structures each_way[0] data_structures data(11)",-1,127,0); + vcdp->declArray(c+873,"cache_simX dmem_controller icache genblk3[0] bank_structure data_structures each_way[0] data_structures data(12)",-1,127,0); + vcdp->declArray(c+877,"cache_simX dmem_controller icache genblk3[0] bank_structure data_structures each_way[0] data_structures data(13)",-1,127,0); + vcdp->declArray(c+881,"cache_simX dmem_controller icache genblk3[0] bank_structure data_structures each_way[0] data_structures data(14)",-1,127,0); + vcdp->declArray(c+885,"cache_simX dmem_controller icache genblk3[0] bank_structure data_structures each_way[0] data_structures data(15)",-1,127,0); + vcdp->declArray(c+889,"cache_simX dmem_controller icache genblk3[0] bank_structure data_structures each_way[0] data_structures data(16)",-1,127,0); + vcdp->declArray(c+893,"cache_simX dmem_controller icache genblk3[0] bank_structure data_structures each_way[0] data_structures data(17)",-1,127,0); + vcdp->declArray(c+897,"cache_simX dmem_controller icache genblk3[0] bank_structure data_structures each_way[0] data_structures data(18)",-1,127,0); + vcdp->declArray(c+901,"cache_simX dmem_controller icache genblk3[0] bank_structure data_structures each_way[0] data_structures data(19)",-1,127,0); + vcdp->declArray(c+905,"cache_simX dmem_controller icache genblk3[0] bank_structure data_structures each_way[0] data_structures data(20)",-1,127,0); + vcdp->declArray(c+909,"cache_simX dmem_controller icache genblk3[0] bank_structure data_structures each_way[0] data_structures data(21)",-1,127,0); + vcdp->declArray(c+913,"cache_simX dmem_controller icache genblk3[0] bank_structure data_structures each_way[0] data_structures data(22)",-1,127,0); + vcdp->declArray(c+917,"cache_simX dmem_controller icache genblk3[0] bank_structure data_structures each_way[0] data_structures data(23)",-1,127,0); + vcdp->declArray(c+921,"cache_simX dmem_controller icache genblk3[0] bank_structure data_structures each_way[0] data_structures data(24)",-1,127,0); + vcdp->declArray(c+925,"cache_simX dmem_controller icache genblk3[0] bank_structure data_structures each_way[0] data_structures data(25)",-1,127,0); + vcdp->declArray(c+929,"cache_simX dmem_controller icache genblk3[0] bank_structure data_structures each_way[0] data_structures data(26)",-1,127,0); + vcdp->declArray(c+933,"cache_simX dmem_controller icache genblk3[0] bank_structure data_structures each_way[0] data_structures data(27)",-1,127,0); + vcdp->declArray(c+937,"cache_simX dmem_controller icache genblk3[0] bank_structure data_structures each_way[0] data_structures data(28)",-1,127,0); + vcdp->declArray(c+941,"cache_simX dmem_controller icache genblk3[0] bank_structure data_structures each_way[0] data_structures data(29)",-1,127,0); + vcdp->declArray(c+945,"cache_simX dmem_controller icache genblk3[0] bank_structure data_structures each_way[0] data_structures data(30)",-1,127,0); + vcdp->declArray(c+949,"cache_simX dmem_controller icache genblk3[0] bank_structure data_structures each_way[0] data_structures data(31)",-1,127,0); + {int i; for (i=0; i<32; i++) { + vcdp->declBus(c+953+i*1,"cache_simX dmem_controller icache genblk3[0] bank_structure data_structures each_way[0] data_structures tag",(i+0),22,0);}} + {int i; for (i=0; i<32; i++) { + vcdp->declBit(c+985+i*1,"cache_simX dmem_controller icache genblk3[0] bank_structure data_structures each_way[0] data_structures valid",(i+0));}} + {int i; for (i=0; i<32; i++) { + vcdp->declBit(c+1017+i*1,"cache_simX dmem_controller icache genblk3[0] bank_structure data_structures each_way[0] data_structures dirty",(i+0));}} + vcdp->declBus(c+1049,"cache_simX dmem_controller icache genblk3[0] bank_structure data_structures each_way[0] data_structures f",-1,31,0); + vcdp->declBus(c+1050,"cache_simX dmem_controller icache genblk3[0] bank_structure data_structures each_way[0] data_structures ini_ind",-1,31,0); + vcdp->declBus(c+3143,"cache_simX dmem_controller icache genblk3[0] bank_structure data_structures each_way[1] data_structures NUM_IND",-1,31,0); + vcdp->declBus(c+3102,"cache_simX dmem_controller icache genblk3[0] bank_structure data_structures each_way[1] data_structures NUM_WORDS_PER_BLOCK",-1,31,0); + vcdp->declBus(c+3125,"cache_simX dmem_controller icache genblk3[0] bank_structure data_structures each_way[1] data_structures TAG_SIZE_START",-1,31,0); + vcdp->declBus(c+3152,"cache_simX dmem_controller icache genblk3[0] bank_structure data_structures each_way[1] data_structures TAG_SIZE_END",-1,31,0); + vcdp->declBus(c+3125,"cache_simX dmem_controller icache genblk3[0] bank_structure data_structures each_way[1] data_structures IND_SIZE_START",-1,31,0); + vcdp->declBus(c+3102,"cache_simX dmem_controller icache genblk3[0] bank_structure data_structures each_way[1] data_structures IND_SIZE_END",-1,31,0); + vcdp->declBit(c+3085,"cache_simX dmem_controller icache genblk3[0] bank_structure data_structures each_way[1] data_structures clk",-1); + vcdp->declBit(c+3086,"cache_simX dmem_controller icache genblk3[0] bank_structure data_structures each_way[1] data_structures rst",-1); + vcdp->declBus(c+270,"cache_simX dmem_controller icache genblk3[0] bank_structure data_structures each_way[1] data_structures addr",-1,4,0); + vcdp->declBus(c+343,"cache_simX dmem_controller icache genblk3[0] bank_structure data_structures each_way[1] data_structures we",-1,15,0); + vcdp->declBit(c+344,"cache_simX dmem_controller icache genblk3[0] bank_structure data_structures each_way[1] data_structures evict",-1); + vcdp->declArray(c+345,"cache_simX dmem_controller icache genblk3[0] bank_structure data_structures each_way[1] data_structures data_write",-1,127,0); + vcdp->declBus(c+271,"cache_simX dmem_controller icache genblk3[0] bank_structure data_structures each_way[1] data_structures tag_write",-1,22,0); + vcdp->declBus(c+741,"cache_simX dmem_controller icache genblk3[0] bank_structure data_structures each_way[1] data_structures tag_use",-1,22,0); + vcdp->declArray(c+742,"cache_simX dmem_controller icache genblk3[0] bank_structure data_structures each_way[1] data_structures data_use",-1,127,0); + vcdp->declBit(c+746,"cache_simX dmem_controller icache genblk3[0] bank_structure data_structures each_way[1] data_structures valid_use",-1); + vcdp->declBit(c+349,"cache_simX dmem_controller icache genblk3[0] bank_structure data_structures each_way[1] data_structures dirty_use",-1); + vcdp->declBit(c+350,"cache_simX dmem_controller icache genblk3[0] bank_structure data_structures each_way[1] data_structures currently_writing",-1); + vcdp->declBit(c+351,"cache_simX dmem_controller icache genblk3[0] bank_structure data_structures each_way[1] data_structures update_dirty",-1); + vcdp->declBit(c+352,"cache_simX dmem_controller icache genblk3[0] bank_structure data_structures each_way[1] data_structures dirt_new",-1); + vcdp->declArray(c+1051,"cache_simX dmem_controller icache genblk3[0] bank_structure data_structures each_way[1] data_structures data(0)",-1,127,0); + vcdp->declArray(c+1055,"cache_simX dmem_controller icache genblk3[0] bank_structure data_structures each_way[1] data_structures data(1)",-1,127,0); + vcdp->declArray(c+1059,"cache_simX dmem_controller icache genblk3[0] bank_structure data_structures each_way[1] data_structures data(2)",-1,127,0); + vcdp->declArray(c+1063,"cache_simX dmem_controller icache genblk3[0] bank_structure data_structures each_way[1] data_structures data(3)",-1,127,0); + vcdp->declArray(c+1067,"cache_simX dmem_controller icache genblk3[0] bank_structure data_structures each_way[1] data_structures data(4)",-1,127,0); + vcdp->declArray(c+1071,"cache_simX dmem_controller icache genblk3[0] bank_structure data_structures each_way[1] data_structures data(5)",-1,127,0); + vcdp->declArray(c+1075,"cache_simX dmem_controller icache genblk3[0] bank_structure data_structures each_way[1] data_structures data(6)",-1,127,0); + vcdp->declArray(c+1079,"cache_simX dmem_controller icache genblk3[0] bank_structure data_structures each_way[1] data_structures data(7)",-1,127,0); + vcdp->declArray(c+1083,"cache_simX dmem_controller icache genblk3[0] bank_structure data_structures each_way[1] data_structures data(8)",-1,127,0); + vcdp->declArray(c+1087,"cache_simX dmem_controller icache genblk3[0] bank_structure data_structures each_way[1] data_structures data(9)",-1,127,0); + vcdp->declArray(c+1091,"cache_simX dmem_controller icache genblk3[0] bank_structure data_structures each_way[1] data_structures data(10)",-1,127,0); + vcdp->declArray(c+1095,"cache_simX dmem_controller icache genblk3[0] bank_structure data_structures each_way[1] data_structures data(11)",-1,127,0); + vcdp->declArray(c+1099,"cache_simX dmem_controller icache genblk3[0] bank_structure data_structures each_way[1] data_structures data(12)",-1,127,0); + vcdp->declArray(c+1103,"cache_simX dmem_controller icache genblk3[0] bank_structure data_structures each_way[1] data_structures data(13)",-1,127,0); + vcdp->declArray(c+1107,"cache_simX dmem_controller icache genblk3[0] bank_structure data_structures each_way[1] data_structures data(14)",-1,127,0); + vcdp->declArray(c+1111,"cache_simX dmem_controller icache genblk3[0] bank_structure data_structures each_way[1] data_structures data(15)",-1,127,0); + vcdp->declArray(c+1115,"cache_simX dmem_controller icache genblk3[0] bank_structure data_structures each_way[1] data_structures data(16)",-1,127,0); + vcdp->declArray(c+1119,"cache_simX dmem_controller icache genblk3[0] bank_structure data_structures each_way[1] data_structures data(17)",-1,127,0); + vcdp->declArray(c+1123,"cache_simX dmem_controller icache genblk3[0] bank_structure data_structures each_way[1] data_structures data(18)",-1,127,0); + vcdp->declArray(c+1127,"cache_simX dmem_controller icache genblk3[0] bank_structure data_structures each_way[1] data_structures data(19)",-1,127,0); + vcdp->declArray(c+1131,"cache_simX dmem_controller icache genblk3[0] bank_structure data_structures each_way[1] data_structures data(20)",-1,127,0); + vcdp->declArray(c+1135,"cache_simX dmem_controller icache genblk3[0] bank_structure data_structures each_way[1] data_structures data(21)",-1,127,0); + vcdp->declArray(c+1139,"cache_simX dmem_controller icache genblk3[0] bank_structure data_structures each_way[1] data_structures data(22)",-1,127,0); + vcdp->declArray(c+1143,"cache_simX dmem_controller icache genblk3[0] bank_structure data_structures each_way[1] data_structures data(23)",-1,127,0); + vcdp->declArray(c+1147,"cache_simX dmem_controller icache genblk3[0] bank_structure data_structures each_way[1] data_structures data(24)",-1,127,0); + vcdp->declArray(c+1151,"cache_simX dmem_controller icache genblk3[0] bank_structure data_structures each_way[1] data_structures data(25)",-1,127,0); + vcdp->declArray(c+1155,"cache_simX dmem_controller icache genblk3[0] bank_structure data_structures each_way[1] data_structures data(26)",-1,127,0); + vcdp->declArray(c+1159,"cache_simX dmem_controller icache genblk3[0] bank_structure data_structures each_way[1] data_structures data(27)",-1,127,0); + vcdp->declArray(c+1163,"cache_simX dmem_controller icache genblk3[0] bank_structure data_structures each_way[1] data_structures data(28)",-1,127,0); + vcdp->declArray(c+1167,"cache_simX dmem_controller icache genblk3[0] bank_structure data_structures each_way[1] data_structures data(29)",-1,127,0); + vcdp->declArray(c+1171,"cache_simX dmem_controller icache genblk3[0] bank_structure data_structures each_way[1] data_structures data(30)",-1,127,0); + vcdp->declArray(c+1175,"cache_simX dmem_controller icache genblk3[0] bank_structure data_structures each_way[1] data_structures data(31)",-1,127,0); + {int i; for (i=0; i<32; i++) { + vcdp->declBus(c+1179+i*1,"cache_simX dmem_controller icache genblk3[0] bank_structure data_structures each_way[1] data_structures tag",(i+0),22,0);}} + {int i; for (i=0; i<32; i++) { + vcdp->declBit(c+1211+i*1,"cache_simX dmem_controller icache genblk3[0] bank_structure data_structures each_way[1] data_structures valid",(i+0));}} + {int i; for (i=0; i<32; i++) { + vcdp->declBit(c+1243+i*1,"cache_simX dmem_controller icache genblk3[0] bank_structure data_structures each_way[1] data_structures dirty",(i+0));}} + vcdp->declBus(c+1275,"cache_simX dmem_controller icache genblk3[0] bank_structure data_structures each_way[1] data_structures f",-1,31,0); + vcdp->declBus(c+1276,"cache_simX dmem_controller icache genblk3[0] bank_structure data_structures each_way[1] data_structures ini_ind",-1,31,0); + vcdp->declBus(c+3087,"cache_simX VX_icache_req pc_address",-1,31,0); + vcdp->declBus(c+3101,"cache_simX VX_icache_req out_cache_driver_in_mem_read",-1,2,0); + vcdp->declBus(c+3124,"cache_simX VX_icache_req out_cache_driver_in_mem_write",-1,2,0); + vcdp->declBit(c+3088,"cache_simX VX_icache_req out_cache_driver_in_valid",-1); + vcdp->declBus(c+3125,"cache_simX VX_icache_req out_cache_driver_in_data",-1,31,0); + vcdp->declBus(c+711,"cache_simX VX_icache_rsp instruction",-1,31,0); + vcdp->declBit(c+712,"cache_simX VX_icache_rsp delay",-1); + vcdp->declBus(c+3102,"cache_simX VX_dram_req_rsp NUMBER_BANKS",-1,31,0); + vcdp->declBus(c+3102,"cache_simX VX_dram_req_rsp NUM_WORDS_PER_BLOCK",-1,31,0); + vcdp->declBus(c+1,"cache_simX VX_dram_req_rsp o_m_evict_addr",-1,31,0); + vcdp->declBus(c+802,"cache_simX VX_dram_req_rsp o_m_read_addr",-1,31,0); + vcdp->declBit(c+803,"cache_simX VX_dram_req_rsp o_m_valid",-1); + vcdp->declArray(c+2,"cache_simX VX_dram_req_rsp o_m_writedata",-1,511,0); + vcdp->declBit(c+709,"cache_simX VX_dram_req_rsp o_m_read_or_write",-1); + vcdp->declArray(c+3103,"cache_simX VX_dram_req_rsp i_m_readdata",-1,511,0); + vcdp->declBit(c+801,"cache_simX VX_dram_req_rsp i_m_ready",-1); + vcdp->declBus(c+3119,"cache_simX VX_dram_req_rsp_icache NUMBER_BANKS",-1,31,0); + vcdp->declBus(c+3102,"cache_simX VX_dram_req_rsp_icache NUM_WORDS_PER_BLOCK",-1,31,0); + vcdp->declBus(c+18,"cache_simX VX_dram_req_rsp_icache o_m_evict_addr",-1,31,0); + vcdp->declBus(c+804,"cache_simX VX_dram_req_rsp_icache o_m_read_addr",-1,31,0); + vcdp->declBit(c+805,"cache_simX VX_dram_req_rsp_icache o_m_valid",-1); + vcdp->declArray(c+19,"cache_simX VX_dram_req_rsp_icache o_m_writedata",-1,127,0); + vcdp->declBit(c+710,"cache_simX VX_dram_req_rsp_icache o_m_read_or_write",-1); + vcdp->declArray(c+3120,"cache_simX VX_dram_req_rsp_icache i_m_readdata",-1,127,0); + vcdp->declBit(c+800,"cache_simX VX_dram_req_rsp_icache i_m_ready",-1); + vcdp->declArray(c+23,"cache_simX VX_dcache_req out_cache_driver_in_address",-1,127,0); + vcdp->declBus(c+3090,"cache_simX VX_dcache_req out_cache_driver_in_mem_read",-1,2,0); + vcdp->declBus(c+3091,"cache_simX VX_dcache_req out_cache_driver_in_mem_write",-1,2,0); + vcdp->declBus(c+27,"cache_simX VX_dcache_req out_cache_driver_in_valid",-1,3,0); + vcdp->declArray(c+3126,"cache_simX VX_dcache_req out_cache_driver_in_data",-1,127,0); + vcdp->declArray(c+28,"cache_simX VX_dcache_rsp in_cache_driver_out_data",-1,127,0); + vcdp->declBit(c+713,"cache_simX VX_dcache_rsp delay",-1); + vcdp->declBus(c+3141,"cache_simX dmem_controller dcache genblk3[0] bank_structure CACHE_SIZE",-1,31,0); + vcdp->declBus(c+3133,"cache_simX dmem_controller dcache genblk3[0] bank_structure CACHE_WAYS",-1,31,0); + vcdp->declBus(c+3142,"cache_simX dmem_controller dcache genblk3[0] bank_structure CACHE_BLOCK",-1,31,0); + vcdp->declBus(c+3102,"cache_simX dmem_controller dcache genblk3[0] bank_structure CACHE_BANKS",-1,31,0); + vcdp->declBus(c+3133,"cache_simX dmem_controller dcache genblk3[0] bank_structure LOG_NUM_BANKS",-1,31,0); + vcdp->declBus(c+3102,"cache_simX dmem_controller dcache genblk3[0] bank_structure NUM_REQ",-1,31,0); + vcdp->declBus(c+3133,"cache_simX dmem_controller dcache genblk3[0] bank_structure LOG_NUM_REQ",-1,31,0); + vcdp->declBus(c+3143,"cache_simX dmem_controller dcache genblk3[0] bank_structure NUM_IND",-1,31,0); + vcdp->declBus(c+3119,"cache_simX dmem_controller dcache genblk3[0] bank_structure CACHE_WAY_INDEX",-1,31,0); + vcdp->declBus(c+3102,"cache_simX dmem_controller dcache genblk3[0] bank_structure NUM_WORDS_PER_BLOCK",-1,31,0); + vcdp->declBus(c+3125,"cache_simX dmem_controller dcache genblk3[0] bank_structure OFFSET_SIZE_START",-1,31,0); + vcdp->declBus(c+3119,"cache_simX dmem_controller dcache genblk3[0] bank_structure OFFSET_SIZE_END",-1,31,0); + vcdp->declBus(c+3125,"cache_simX dmem_controller dcache genblk3[0] bank_structure TAG_SIZE_START",-1,31,0); + vcdp->declBus(c+3144,"cache_simX dmem_controller dcache genblk3[0] bank_structure TAG_SIZE_END",-1,31,0); + vcdp->declBus(c+3125,"cache_simX dmem_controller dcache genblk3[0] bank_structure IND_SIZE_START",-1,31,0); + vcdp->declBus(c+3102,"cache_simX dmem_controller dcache genblk3[0] bank_structure IND_SIZE_END",-1,31,0); + vcdp->declBus(c+3145,"cache_simX dmem_controller dcache genblk3[0] bank_structure ADDR_TAG_START",-1,31,0); + vcdp->declBus(c+3146,"cache_simX dmem_controller dcache genblk3[0] bank_structure ADDR_TAG_END",-1,31,0); + vcdp->declBus(c+3102,"cache_simX dmem_controller dcache genblk3[0] bank_structure ADDR_OFFSET_START",-1,31,0); + vcdp->declBus(c+3136,"cache_simX dmem_controller dcache genblk3[0] bank_structure ADDR_OFFSET_END",-1,31,0); + vcdp->declBus(c+3137,"cache_simX dmem_controller dcache genblk3[0] bank_structure ADDR_IND_START",-1,31,0); + vcdp->declBus(c+3147,"cache_simX dmem_controller dcache genblk3[0] bank_structure ADDR_IND_END",-1,31,0); + vcdp->declBus(c+3125,"cache_simX dmem_controller dcache genblk3[0] bank_structure CACHE_IDLE",-1,31,0); + vcdp->declBus(c+3119,"cache_simX dmem_controller dcache genblk3[0] bank_structure SEND_MEM_REQ",-1,31,0); + vcdp->declBus(c+3133,"cache_simX dmem_controller dcache genblk3[0] bank_structure RECIV_MEM_RSP",-1,31,0); + vcdp->declBus(c+3137,"cache_simX dmem_controller dcache genblk3[0] bank_structure BLOCK_NUM_BITS",-1,31,0); + vcdp->declBit(c+3086,"cache_simX dmem_controller dcache genblk3[0] bank_structure rst",-1); + vcdp->declBit(c+3085,"cache_simX dmem_controller dcache genblk3[0] bank_structure clk",-1); + vcdp->declBus(c+817,"cache_simX dmem_controller dcache genblk3[0] bank_structure state",-1,3,0); + vcdp->declBus(c+206,"cache_simX dmem_controller dcache genblk3[0] bank_structure actual_index",-1,4,0); + vcdp->declBus(c+207,"cache_simX dmem_controller dcache genblk3[0] bank_structure o_tag",-1,20,0); + vcdp->declBus(c+205,"cache_simX dmem_controller dcache genblk3[0] bank_structure block_offset",-1,1,0); + vcdp->declBus(c+353,"cache_simX dmem_controller dcache genblk3[0] bank_structure writedata",-1,31,0); + vcdp->declBit(c+209,"cache_simX dmem_controller dcache genblk3[0] bank_structure valid_in",-1); + vcdp->declBit(c+35,"cache_simX dmem_controller dcache genblk3[0] bank_structure read_or_write",-1); + vcdp->declArray(c+3159,"cache_simX dmem_controller dcache genblk3[0] bank_structure fetched_writedata",-1,127,0); + vcdp->declBus(c+36,"cache_simX dmem_controller dcache genblk3[0] bank_structure i_p_mem_read",-1,2,0); + vcdp->declBus(c+37,"cache_simX dmem_controller dcache genblk3[0] bank_structure i_p_mem_write",-1,2,0); + vcdp->declBus(c+204,"cache_simX dmem_controller dcache genblk3[0] bank_structure byte_select",-1,1,0); + vcdp->declBus(c+816,"cache_simX dmem_controller dcache genblk3[0] bank_structure evicted_way",-1,0,0); + vcdp->declBus(c+354,"cache_simX dmem_controller dcache genblk3[0] bank_structure readdata",-1,31,0); + vcdp->declBit(c+355,"cache_simX dmem_controller dcache genblk3[0] bank_structure hit",-1); + vcdp->declBit(c+356,"cache_simX dmem_controller dcache genblk3[0] bank_structure eviction_wb",-1); + vcdp->declBus(c+357,"cache_simX dmem_controller dcache genblk3[0] bank_structure eviction_addr",-1,31,0); + vcdp->declArray(c+358,"cache_simX dmem_controller dcache genblk3[0] bank_structure data_evicted",-1,127,0); + vcdp->declArray(c+358,"cache_simX dmem_controller dcache genblk3[0] bank_structure data_use",-1,127,0); + vcdp->declBus(c+362,"cache_simX dmem_controller dcache genblk3[0] bank_structure tag_use",-1,20,0); + vcdp->declBus(c+362,"cache_simX dmem_controller dcache genblk3[0] bank_structure eviction_tag",-1,20,0); + vcdp->declBit(c+363,"cache_simX dmem_controller dcache genblk3[0] bank_structure valid_use",-1); + vcdp->declBit(c+356,"cache_simX dmem_controller dcache genblk3[0] bank_structure dirty_use",-1); + vcdp->declBit(c+364,"cache_simX dmem_controller dcache genblk3[0] bank_structure access",-1); + vcdp->declBit(c+365,"cache_simX dmem_controller dcache genblk3[0] bank_structure write_from_mem",-1); + vcdp->declBit(c+366,"cache_simX dmem_controller dcache genblk3[0] bank_structure miss",-1); + vcdp->declBus(c+796,"cache_simX dmem_controller dcache genblk3[0] bank_structure way_to_update",-1,0,0); + vcdp->declBit(c+367,"cache_simX dmem_controller dcache genblk3[0] bank_structure lw",-1); + vcdp->declBit(c+368,"cache_simX dmem_controller dcache genblk3[0] bank_structure lb",-1); + vcdp->declBit(c+369,"cache_simX dmem_controller dcache genblk3[0] bank_structure lh",-1); + vcdp->declBit(c+370,"cache_simX dmem_controller dcache genblk3[0] bank_structure lhu",-1); + vcdp->declBit(c+371,"cache_simX dmem_controller dcache genblk3[0] bank_structure lbu",-1); + vcdp->declBit(c+372,"cache_simX dmem_controller dcache genblk3[0] bank_structure sw",-1); + vcdp->declBit(c+373,"cache_simX dmem_controller dcache genblk3[0] bank_structure sb",-1); + vcdp->declBit(c+374,"cache_simX dmem_controller dcache genblk3[0] bank_structure sh",-1); + vcdp->declBit(c+375,"cache_simX dmem_controller dcache genblk3[0] bank_structure b0",-1); + vcdp->declBit(c+376,"cache_simX dmem_controller dcache genblk3[0] bank_structure b1",-1); + vcdp->declBit(c+377,"cache_simX dmem_controller dcache genblk3[0] bank_structure b2",-1); + vcdp->declBit(c+378,"cache_simX dmem_controller dcache genblk3[0] bank_structure b3",-1); + vcdp->declBus(c+379,"cache_simX dmem_controller dcache genblk3[0] bank_structure data_unQual",-1,31,0); + vcdp->declBus(c+380,"cache_simX dmem_controller dcache genblk3[0] bank_structure lb_data",-1,31,0); + vcdp->declBus(c+381,"cache_simX dmem_controller dcache genblk3[0] bank_structure lh_data",-1,31,0); + vcdp->declBus(c+382,"cache_simX dmem_controller dcache genblk3[0] bank_structure lbu_data",-1,31,0); + vcdp->declBus(c+383,"cache_simX dmem_controller dcache genblk3[0] bank_structure lhu_data",-1,31,0); + vcdp->declBus(c+379,"cache_simX dmem_controller dcache genblk3[0] bank_structure lw_data",-1,31,0); + vcdp->declBus(c+353,"cache_simX dmem_controller dcache genblk3[0] bank_structure sw_data",-1,31,0); + vcdp->declBus(c+384,"cache_simX dmem_controller dcache genblk3[0] bank_structure sb_data",-1,31,0); + vcdp->declBus(c+385,"cache_simX dmem_controller dcache genblk3[0] bank_structure sh_data",-1,31,0); + vcdp->declBus(c+386,"cache_simX dmem_controller dcache genblk3[0] bank_structure use_write_data",-1,31,0); + vcdp->declBus(c+387,"cache_simX dmem_controller dcache genblk3[0] bank_structure data_Qual",-1,31,0); + vcdp->declBus(c+388,"cache_simX dmem_controller dcache genblk3[0] bank_structure sb_mask",-1,3,0); + vcdp->declBus(c+389,"cache_simX dmem_controller dcache genblk3[0] bank_structure sh_mask",-1,3,0); + vcdp->declBus(c+390,"cache_simX dmem_controller dcache genblk3[0] bank_structure we",-1,15,0); + vcdp->declArray(c+391,"cache_simX dmem_controller dcache genblk3[0] bank_structure data_write",-1,127,0); + vcdp->declBit(c+395,"cache_simX dmem_controller dcache genblk3[0] bank_structure genblk1[0] normal_write",-1); + vcdp->declBit(c+396,"cache_simX dmem_controller dcache genblk3[0] bank_structure genblk1[1] normal_write",-1); + vcdp->declBit(c+397,"cache_simX dmem_controller dcache genblk3[0] bank_structure genblk1[2] normal_write",-1); + vcdp->declBit(c+398,"cache_simX dmem_controller dcache genblk3[0] bank_structure genblk1[3] normal_write",-1); + vcdp->declBus(c+3133,"cache_simX dmem_controller dcache genblk3[0] bank_structure data_structures CACHE_WAYS",-1,31,0); + vcdp->declBus(c+3143,"cache_simX dmem_controller dcache genblk3[0] bank_structure data_structures NUM_IND",-1,31,0); + vcdp->declBus(c+3119,"cache_simX dmem_controller dcache genblk3[0] bank_structure data_structures CACHE_WAY_INDEX",-1,31,0); + vcdp->declBus(c+3102,"cache_simX dmem_controller dcache genblk3[0] bank_structure data_structures NUM_WORDS_PER_BLOCK",-1,31,0); + vcdp->declBus(c+3125,"cache_simX dmem_controller dcache genblk3[0] bank_structure data_structures TAG_SIZE_START",-1,31,0); + vcdp->declBus(c+3144,"cache_simX dmem_controller dcache genblk3[0] bank_structure data_structures TAG_SIZE_END",-1,31,0); + vcdp->declBus(c+3125,"cache_simX dmem_controller dcache genblk3[0] bank_structure data_structures IND_SIZE_START",-1,31,0); + vcdp->declBus(c+3102,"cache_simX dmem_controller dcache genblk3[0] bank_structure data_structures IND_SIZE_END",-1,31,0); + vcdp->declBit(c+3085,"cache_simX dmem_controller dcache genblk3[0] bank_structure data_structures clk",-1); + vcdp->declBit(c+3086,"cache_simX dmem_controller dcache genblk3[0] bank_structure data_structures rst",-1); + vcdp->declBit(c+209,"cache_simX dmem_controller dcache genblk3[0] bank_structure data_structures valid_in",-1); + vcdp->declBus(c+817,"cache_simX dmem_controller dcache genblk3[0] bank_structure data_structures state",-1,3,0); + vcdp->declBus(c+206,"cache_simX dmem_controller dcache genblk3[0] bank_structure data_structures addr",-1,4,0); + vcdp->declBus(c+390,"cache_simX dmem_controller dcache genblk3[0] bank_structure data_structures we",-1,15,0); + vcdp->declBit(c+365,"cache_simX dmem_controller dcache genblk3[0] bank_structure data_structures evict",-1); + vcdp->declBus(c+796,"cache_simX dmem_controller dcache genblk3[0] bank_structure data_structures way_to_update",-1,0,0); + vcdp->declArray(c+391,"cache_simX dmem_controller dcache genblk3[0] bank_structure data_structures data_write",-1,127,0); + vcdp->declBus(c+207,"cache_simX dmem_controller dcache genblk3[0] bank_structure data_structures tag_write",-1,20,0); + vcdp->declBus(c+362,"cache_simX dmem_controller dcache genblk3[0] bank_structure data_structures tag_use",-1,20,0); + vcdp->declArray(c+358,"cache_simX dmem_controller dcache genblk3[0] bank_structure data_structures data_use",-1,127,0); + vcdp->declBit(c+363,"cache_simX dmem_controller dcache genblk3[0] bank_structure data_structures valid_use",-1); + vcdp->declBit(c+356,"cache_simX dmem_controller dcache genblk3[0] bank_structure data_structures dirty_use",-1); + vcdp->declQuad(c+399,"cache_simX dmem_controller dcache genblk3[0] bank_structure data_structures tag_use_per_way",-1,41,0); + vcdp->declArray(c+401,"cache_simX dmem_controller dcache genblk3[0] bank_structure data_structures data_use_per_way",-1,255,0); + vcdp->declBus(c+409,"cache_simX dmem_controller dcache genblk3[0] bank_structure data_structures valid_use_per_way",-1,1,0); + vcdp->declBus(c+410,"cache_simX dmem_controller dcache genblk3[0] bank_structure data_structures dirty_use_per_way",-1,1,0); + vcdp->declBus(c+411,"cache_simX dmem_controller dcache genblk3[0] bank_structure data_structures hit_per_way",-1,1,0); + vcdp->declBus(c+412,"cache_simX dmem_controller dcache genblk3[0] bank_structure data_structures we_per_way",-1,31,0); + vcdp->declArray(c+413,"cache_simX dmem_controller dcache genblk3[0] bank_structure data_structures data_write_per_way",-1,255,0); + vcdp->declBus(c+421,"cache_simX dmem_controller dcache genblk3[0] bank_structure data_structures write_from_mem_per_way",-1,1,0); + vcdp->declBit(c+422,"cache_simX dmem_controller dcache genblk3[0] bank_structure data_structures invalid_found",-1); + vcdp->declBus(c+423,"cache_simX dmem_controller dcache genblk3[0] bank_structure data_structures way_index",-1,0,0); + vcdp->declBus(c+424,"cache_simX dmem_controller dcache genblk3[0] bank_structure data_structures invalid_index",-1,0,0); + vcdp->declBus(c+3125,"cache_simX dmem_controller dcache genblk3[0] bank_structure data_structures CACHE_IDLE",-1,31,0); + vcdp->declBus(c+3119,"cache_simX dmem_controller dcache genblk3[0] bank_structure data_structures SEND_MEM_REQ",-1,31,0); + vcdp->declBus(c+3133,"cache_simX dmem_controller dcache genblk3[0] bank_structure data_structures RECIV_MEM_RSP",-1,31,0); + vcdp->declBus(c+425,"cache_simX dmem_controller dcache genblk3[0] bank_structure data_structures way_use_Qual",-1,0,0); + vcdp->declBus(c+3133,"cache_simX dmem_controller dcache genblk3[0] bank_structure data_structures genblk1 valid_index N",-1,31,0); + vcdp->declBus(c+426,"cache_simX dmem_controller dcache genblk3[0] bank_structure data_structures genblk1 valid_index valids",-1,1,0); + vcdp->declBus(c+424,"cache_simX dmem_controller dcache genblk3[0] bank_structure data_structures genblk1 valid_index index",-1,0,0); + vcdp->declBit(c+422,"cache_simX dmem_controller dcache genblk3[0] bank_structure data_structures genblk1 valid_index found",-1); + vcdp->declBus(c+3140,"cache_simX dmem_controller dcache genblk3[0] bank_structure data_structures genblk1 valid_index i",-1,31,0); + vcdp->declBus(c+3133,"cache_simX dmem_controller dcache genblk3[0] bank_structure data_structures genblk1 way_indexing N",-1,31,0); + vcdp->declBus(c+411,"cache_simX dmem_controller dcache genblk3[0] bank_structure data_structures genblk1 way_indexing valids",-1,1,0); + vcdp->declBus(c+423,"cache_simX dmem_controller dcache genblk3[0] bank_structure data_structures genblk1 way_indexing index",-1,0,0); + vcdp->declBit(c+427,"cache_simX dmem_controller dcache genblk3[0] bank_structure data_structures genblk1 way_indexing found",-1); + vcdp->declBus(c+3140,"cache_simX dmem_controller dcache genblk3[0] bank_structure data_structures genblk1 way_indexing i",-1,31,0); + vcdp->declBus(c+3143,"cache_simX dmem_controller dcache genblk3[0] bank_structure data_structures each_way[0] data_structures NUM_IND",-1,31,0); + vcdp->declBus(c+3102,"cache_simX dmem_controller dcache genblk3[0] bank_structure data_structures each_way[0] data_structures NUM_WORDS_PER_BLOCK",-1,31,0); + vcdp->declBus(c+3125,"cache_simX dmem_controller dcache genblk3[0] bank_structure data_structures each_way[0] data_structures TAG_SIZE_START",-1,31,0); + vcdp->declBus(c+3144,"cache_simX dmem_controller dcache genblk3[0] bank_structure data_structures each_way[0] data_structures TAG_SIZE_END",-1,31,0); + vcdp->declBus(c+3125,"cache_simX dmem_controller dcache genblk3[0] bank_structure data_structures each_way[0] data_structures IND_SIZE_START",-1,31,0); + vcdp->declBus(c+3102,"cache_simX dmem_controller dcache genblk3[0] bank_structure data_structures each_way[0] data_structures IND_SIZE_END",-1,31,0); + vcdp->declBit(c+3085,"cache_simX dmem_controller dcache genblk3[0] bank_structure data_structures each_way[0] data_structures clk",-1); + vcdp->declBit(c+3086,"cache_simX dmem_controller dcache genblk3[0] bank_structure data_structures each_way[0] data_structures rst",-1); + vcdp->declBus(c+206,"cache_simX dmem_controller dcache genblk3[0] bank_structure data_structures each_way[0] data_structures addr",-1,4,0); + vcdp->declBus(c+428,"cache_simX dmem_controller dcache genblk3[0] bank_structure data_structures each_way[0] data_structures we",-1,15,0); + vcdp->declBit(c+429,"cache_simX dmem_controller dcache genblk3[0] bank_structure data_structures each_way[0] data_structures evict",-1); + vcdp->declArray(c+430,"cache_simX dmem_controller dcache genblk3[0] bank_structure data_structures each_way[0] data_structures data_write",-1,127,0); + vcdp->declBus(c+207,"cache_simX dmem_controller dcache genblk3[0] bank_structure data_structures each_way[0] data_structures tag_write",-1,20,0); + vcdp->declBus(c+747,"cache_simX dmem_controller dcache genblk3[0] bank_structure data_structures each_way[0] data_structures tag_use",-1,20,0); + vcdp->declArray(c+748,"cache_simX dmem_controller dcache genblk3[0] bank_structure data_structures each_way[0] data_structures data_use",-1,127,0); + vcdp->declBit(c+752,"cache_simX dmem_controller dcache genblk3[0] bank_structure data_structures each_way[0] data_structures valid_use",-1); + vcdp->declBit(c+434,"cache_simX dmem_controller dcache genblk3[0] bank_structure data_structures each_way[0] data_structures dirty_use",-1); + vcdp->declBit(c+435,"cache_simX dmem_controller dcache genblk3[0] bank_structure data_structures each_way[0] data_structures currently_writing",-1); + vcdp->declBit(c+436,"cache_simX dmem_controller dcache genblk3[0] bank_structure data_structures each_way[0] data_structures update_dirty",-1); + vcdp->declBit(c+437,"cache_simX dmem_controller dcache genblk3[0] bank_structure data_structures each_way[0] data_structures dirt_new",-1); + vcdp->declArray(c+1277,"cache_simX dmem_controller dcache genblk3[0] bank_structure data_structures each_way[0] data_structures data(0)",-1,127,0); + vcdp->declArray(c+1281,"cache_simX dmem_controller dcache genblk3[0] bank_structure data_structures each_way[0] data_structures data(1)",-1,127,0); + vcdp->declArray(c+1285,"cache_simX dmem_controller dcache genblk3[0] bank_structure data_structures each_way[0] data_structures data(2)",-1,127,0); + vcdp->declArray(c+1289,"cache_simX dmem_controller dcache genblk3[0] bank_structure data_structures each_way[0] data_structures data(3)",-1,127,0); + vcdp->declArray(c+1293,"cache_simX dmem_controller dcache genblk3[0] bank_structure data_structures each_way[0] data_structures data(4)",-1,127,0); + vcdp->declArray(c+1297,"cache_simX dmem_controller dcache genblk3[0] bank_structure data_structures each_way[0] data_structures data(5)",-1,127,0); + vcdp->declArray(c+1301,"cache_simX dmem_controller dcache genblk3[0] bank_structure data_structures each_way[0] data_structures data(6)",-1,127,0); + vcdp->declArray(c+1305,"cache_simX dmem_controller dcache genblk3[0] bank_structure data_structures each_way[0] data_structures data(7)",-1,127,0); + vcdp->declArray(c+1309,"cache_simX dmem_controller dcache genblk3[0] bank_structure data_structures each_way[0] data_structures data(8)",-1,127,0); + vcdp->declArray(c+1313,"cache_simX dmem_controller dcache genblk3[0] bank_structure data_structures each_way[0] data_structures data(9)",-1,127,0); + vcdp->declArray(c+1317,"cache_simX dmem_controller dcache genblk3[0] bank_structure data_structures each_way[0] data_structures data(10)",-1,127,0); + vcdp->declArray(c+1321,"cache_simX dmem_controller dcache genblk3[0] bank_structure data_structures each_way[0] data_structures data(11)",-1,127,0); + vcdp->declArray(c+1325,"cache_simX dmem_controller dcache genblk3[0] bank_structure data_structures each_way[0] data_structures data(12)",-1,127,0); + vcdp->declArray(c+1329,"cache_simX dmem_controller dcache genblk3[0] bank_structure data_structures each_way[0] data_structures data(13)",-1,127,0); + vcdp->declArray(c+1333,"cache_simX dmem_controller dcache genblk3[0] bank_structure data_structures each_way[0] data_structures data(14)",-1,127,0); + vcdp->declArray(c+1337,"cache_simX dmem_controller dcache genblk3[0] bank_structure data_structures each_way[0] data_structures data(15)",-1,127,0); + vcdp->declArray(c+1341,"cache_simX dmem_controller dcache genblk3[0] bank_structure data_structures each_way[0] data_structures data(16)",-1,127,0); + vcdp->declArray(c+1345,"cache_simX dmem_controller dcache genblk3[0] bank_structure data_structures each_way[0] data_structures data(17)",-1,127,0); + vcdp->declArray(c+1349,"cache_simX dmem_controller dcache genblk3[0] bank_structure data_structures each_way[0] data_structures data(18)",-1,127,0); + vcdp->declArray(c+1353,"cache_simX dmem_controller dcache genblk3[0] bank_structure data_structures each_way[0] data_structures data(19)",-1,127,0); + vcdp->declArray(c+1357,"cache_simX dmem_controller dcache genblk3[0] bank_structure data_structures each_way[0] data_structures data(20)",-1,127,0); + vcdp->declArray(c+1361,"cache_simX dmem_controller dcache genblk3[0] bank_structure data_structures each_way[0] data_structures data(21)",-1,127,0); + vcdp->declArray(c+1365,"cache_simX dmem_controller dcache genblk3[0] bank_structure data_structures each_way[0] data_structures data(22)",-1,127,0); + vcdp->declArray(c+1369,"cache_simX dmem_controller dcache genblk3[0] bank_structure data_structures each_way[0] data_structures data(23)",-1,127,0); + vcdp->declArray(c+1373,"cache_simX dmem_controller dcache genblk3[0] bank_structure data_structures each_way[0] data_structures data(24)",-1,127,0); + vcdp->declArray(c+1377,"cache_simX dmem_controller dcache genblk3[0] bank_structure data_structures each_way[0] data_structures data(25)",-1,127,0); + vcdp->declArray(c+1381,"cache_simX dmem_controller dcache genblk3[0] bank_structure data_structures each_way[0] data_structures data(26)",-1,127,0); + vcdp->declArray(c+1385,"cache_simX dmem_controller dcache genblk3[0] bank_structure data_structures each_way[0] data_structures data(27)",-1,127,0); + vcdp->declArray(c+1389,"cache_simX dmem_controller dcache genblk3[0] bank_structure data_structures each_way[0] data_structures data(28)",-1,127,0); + vcdp->declArray(c+1393,"cache_simX dmem_controller dcache genblk3[0] bank_structure data_structures each_way[0] data_structures data(29)",-1,127,0); + vcdp->declArray(c+1397,"cache_simX dmem_controller dcache genblk3[0] bank_structure data_structures each_way[0] data_structures data(30)",-1,127,0); + vcdp->declArray(c+1401,"cache_simX dmem_controller dcache genblk3[0] bank_structure data_structures each_way[0] data_structures data(31)",-1,127,0); + {int i; for (i=0; i<32; i++) { + vcdp->declBus(c+1405+i*1,"cache_simX dmem_controller dcache genblk3[0] bank_structure data_structures each_way[0] data_structures tag",(i+0),20,0);}} + {int i; for (i=0; i<32; i++) { + vcdp->declBit(c+1437+i*1,"cache_simX dmem_controller dcache genblk3[0] bank_structure data_structures each_way[0] data_structures valid",(i+0));}} + {int i; for (i=0; i<32; i++) { + vcdp->declBit(c+1469+i*1,"cache_simX dmem_controller dcache genblk3[0] bank_structure data_structures each_way[0] data_structures dirty",(i+0));}} + vcdp->declBus(c+1501,"cache_simX dmem_controller dcache genblk3[0] bank_structure data_structures each_way[0] data_structures f",-1,31,0); + vcdp->declBus(c+1502,"cache_simX dmem_controller dcache genblk3[0] bank_structure data_structures each_way[0] data_structures ini_ind",-1,31,0); + vcdp->declBus(c+3143,"cache_simX dmem_controller dcache genblk3[0] bank_structure data_structures each_way[1] data_structures NUM_IND",-1,31,0); + vcdp->declBus(c+3102,"cache_simX dmem_controller dcache genblk3[0] bank_structure data_structures each_way[1] data_structures NUM_WORDS_PER_BLOCK",-1,31,0); + vcdp->declBus(c+3125,"cache_simX dmem_controller dcache genblk3[0] bank_structure data_structures each_way[1] data_structures TAG_SIZE_START",-1,31,0); + vcdp->declBus(c+3144,"cache_simX dmem_controller dcache genblk3[0] bank_structure data_structures each_way[1] data_structures TAG_SIZE_END",-1,31,0); + vcdp->declBus(c+3125,"cache_simX dmem_controller dcache genblk3[0] bank_structure data_structures each_way[1] data_structures IND_SIZE_START",-1,31,0); + vcdp->declBus(c+3102,"cache_simX dmem_controller dcache genblk3[0] bank_structure data_structures each_way[1] data_structures IND_SIZE_END",-1,31,0); + vcdp->declBit(c+3085,"cache_simX dmem_controller dcache genblk3[0] bank_structure data_structures each_way[1] data_structures clk",-1); + vcdp->declBit(c+3086,"cache_simX dmem_controller dcache genblk3[0] bank_structure data_structures each_way[1] data_structures rst",-1); + vcdp->declBus(c+206,"cache_simX dmem_controller dcache genblk3[0] bank_structure data_structures each_way[1] data_structures addr",-1,4,0); + vcdp->declBus(c+438,"cache_simX dmem_controller dcache genblk3[0] bank_structure data_structures each_way[1] data_structures we",-1,15,0); + vcdp->declBit(c+439,"cache_simX dmem_controller dcache genblk3[0] bank_structure data_structures each_way[1] data_structures evict",-1); + vcdp->declArray(c+440,"cache_simX dmem_controller dcache genblk3[0] bank_structure data_structures each_way[1] data_structures data_write",-1,127,0); + vcdp->declBus(c+207,"cache_simX dmem_controller dcache genblk3[0] bank_structure data_structures each_way[1] data_structures tag_write",-1,20,0); + vcdp->declBus(c+753,"cache_simX dmem_controller dcache genblk3[0] bank_structure data_structures each_way[1] data_structures tag_use",-1,20,0); + vcdp->declArray(c+754,"cache_simX dmem_controller dcache genblk3[0] bank_structure data_structures each_way[1] data_structures data_use",-1,127,0); + vcdp->declBit(c+758,"cache_simX dmem_controller dcache genblk3[0] bank_structure data_structures each_way[1] data_structures valid_use",-1); + vcdp->declBit(c+444,"cache_simX dmem_controller dcache genblk3[0] bank_structure data_structures each_way[1] data_structures dirty_use",-1); + vcdp->declBit(c+445,"cache_simX dmem_controller dcache genblk3[0] bank_structure data_structures each_way[1] data_structures currently_writing",-1); + vcdp->declBit(c+446,"cache_simX dmem_controller dcache genblk3[0] bank_structure data_structures each_way[1] data_structures update_dirty",-1); + vcdp->declBit(c+447,"cache_simX dmem_controller dcache genblk3[0] bank_structure data_structures each_way[1] data_structures dirt_new",-1); + vcdp->declArray(c+1503,"cache_simX dmem_controller dcache genblk3[0] bank_structure data_structures each_way[1] data_structures data(0)",-1,127,0); + vcdp->declArray(c+1507,"cache_simX dmem_controller dcache genblk3[0] bank_structure data_structures each_way[1] data_structures data(1)",-1,127,0); + vcdp->declArray(c+1511,"cache_simX dmem_controller dcache genblk3[0] bank_structure data_structures each_way[1] data_structures data(2)",-1,127,0); + vcdp->declArray(c+1515,"cache_simX dmem_controller dcache genblk3[0] bank_structure data_structures each_way[1] data_structures data(3)",-1,127,0); + vcdp->declArray(c+1519,"cache_simX dmem_controller dcache genblk3[0] bank_structure data_structures each_way[1] data_structures data(4)",-1,127,0); + vcdp->declArray(c+1523,"cache_simX dmem_controller dcache genblk3[0] bank_structure data_structures each_way[1] data_structures data(5)",-1,127,0); + vcdp->declArray(c+1527,"cache_simX dmem_controller dcache genblk3[0] bank_structure data_structures each_way[1] data_structures data(6)",-1,127,0); + vcdp->declArray(c+1531,"cache_simX dmem_controller dcache genblk3[0] bank_structure data_structures each_way[1] data_structures data(7)",-1,127,0); + vcdp->declArray(c+1535,"cache_simX dmem_controller dcache genblk3[0] bank_structure data_structures each_way[1] data_structures data(8)",-1,127,0); + vcdp->declArray(c+1539,"cache_simX dmem_controller dcache genblk3[0] bank_structure data_structures each_way[1] data_structures data(9)",-1,127,0); + vcdp->declArray(c+1543,"cache_simX dmem_controller dcache genblk3[0] bank_structure data_structures each_way[1] data_structures data(10)",-1,127,0); + vcdp->declArray(c+1547,"cache_simX dmem_controller dcache genblk3[0] bank_structure data_structures each_way[1] data_structures data(11)",-1,127,0); + vcdp->declArray(c+1551,"cache_simX dmem_controller dcache genblk3[0] bank_structure data_structures each_way[1] data_structures data(12)",-1,127,0); + vcdp->declArray(c+1555,"cache_simX dmem_controller dcache genblk3[0] bank_structure data_structures each_way[1] data_structures data(13)",-1,127,0); + vcdp->declArray(c+1559,"cache_simX dmem_controller dcache genblk3[0] bank_structure data_structures each_way[1] data_structures data(14)",-1,127,0); + vcdp->declArray(c+1563,"cache_simX dmem_controller dcache genblk3[0] bank_structure data_structures each_way[1] data_structures data(15)",-1,127,0); + vcdp->declArray(c+1567,"cache_simX dmem_controller dcache genblk3[0] bank_structure data_structures each_way[1] data_structures data(16)",-1,127,0); + vcdp->declArray(c+1571,"cache_simX dmem_controller dcache genblk3[0] bank_structure data_structures each_way[1] data_structures data(17)",-1,127,0); + vcdp->declArray(c+1575,"cache_simX dmem_controller dcache genblk3[0] bank_structure data_structures each_way[1] data_structures data(18)",-1,127,0); + vcdp->declArray(c+1579,"cache_simX dmem_controller dcache genblk3[0] bank_structure data_structures each_way[1] data_structures data(19)",-1,127,0); + vcdp->declArray(c+1583,"cache_simX dmem_controller dcache genblk3[0] bank_structure data_structures each_way[1] data_structures data(20)",-1,127,0); + vcdp->declArray(c+1587,"cache_simX dmem_controller dcache genblk3[0] bank_structure data_structures each_way[1] data_structures data(21)",-1,127,0); + vcdp->declArray(c+1591,"cache_simX dmem_controller dcache genblk3[0] bank_structure data_structures each_way[1] data_structures data(22)",-1,127,0); + vcdp->declArray(c+1595,"cache_simX dmem_controller dcache genblk3[0] bank_structure data_structures each_way[1] data_structures data(23)",-1,127,0); + vcdp->declArray(c+1599,"cache_simX dmem_controller dcache genblk3[0] bank_structure data_structures each_way[1] data_structures data(24)",-1,127,0); + vcdp->declArray(c+1603,"cache_simX dmem_controller dcache genblk3[0] bank_structure data_structures each_way[1] data_structures data(25)",-1,127,0); + vcdp->declArray(c+1607,"cache_simX dmem_controller dcache genblk3[0] bank_structure data_structures each_way[1] data_structures data(26)",-1,127,0); + vcdp->declArray(c+1611,"cache_simX dmem_controller dcache genblk3[0] bank_structure data_structures each_way[1] data_structures data(27)",-1,127,0); + vcdp->declArray(c+1615,"cache_simX dmem_controller dcache genblk3[0] bank_structure data_structures each_way[1] data_structures data(28)",-1,127,0); + vcdp->declArray(c+1619,"cache_simX dmem_controller dcache genblk3[0] bank_structure data_structures each_way[1] data_structures data(29)",-1,127,0); + vcdp->declArray(c+1623,"cache_simX dmem_controller dcache genblk3[0] bank_structure data_structures each_way[1] data_structures data(30)",-1,127,0); + vcdp->declArray(c+1627,"cache_simX dmem_controller dcache genblk3[0] bank_structure data_structures each_way[1] data_structures data(31)",-1,127,0); + {int i; for (i=0; i<32; i++) { + vcdp->declBus(c+1631+i*1,"cache_simX dmem_controller dcache genblk3[0] bank_structure data_structures each_way[1] data_structures tag",(i+0),20,0);}} + {int i; for (i=0; i<32; i++) { + vcdp->declBit(c+1663+i*1,"cache_simX dmem_controller dcache genblk3[0] bank_structure data_structures each_way[1] data_structures valid",(i+0));}} + {int i; for (i=0; i<32; i++) { + vcdp->declBit(c+1695+i*1,"cache_simX dmem_controller dcache genblk3[0] bank_structure data_structures each_way[1] data_structures dirty",(i+0));}} + vcdp->declBus(c+1727,"cache_simX dmem_controller dcache genblk3[0] bank_structure data_structures each_way[1] data_structures f",-1,31,0); + vcdp->declBus(c+1728,"cache_simX dmem_controller dcache genblk3[0] bank_structure data_structures each_way[1] data_structures ini_ind",-1,31,0); + vcdp->declBus(c+3141,"cache_simX dmem_controller dcache genblk3[1] bank_structure CACHE_SIZE",-1,31,0); + vcdp->declBus(c+3133,"cache_simX dmem_controller dcache genblk3[1] bank_structure CACHE_WAYS",-1,31,0); + vcdp->declBus(c+3142,"cache_simX dmem_controller dcache genblk3[1] bank_structure CACHE_BLOCK",-1,31,0); + vcdp->declBus(c+3102,"cache_simX dmem_controller dcache genblk3[1] bank_structure CACHE_BANKS",-1,31,0); + vcdp->declBus(c+3133,"cache_simX dmem_controller dcache genblk3[1] bank_structure LOG_NUM_BANKS",-1,31,0); + vcdp->declBus(c+3102,"cache_simX dmem_controller dcache genblk3[1] bank_structure NUM_REQ",-1,31,0); + vcdp->declBus(c+3133,"cache_simX dmem_controller dcache genblk3[1] bank_structure LOG_NUM_REQ",-1,31,0); + vcdp->declBus(c+3143,"cache_simX dmem_controller dcache genblk3[1] bank_structure NUM_IND",-1,31,0); + vcdp->declBus(c+3119,"cache_simX dmem_controller dcache genblk3[1] bank_structure CACHE_WAY_INDEX",-1,31,0); + vcdp->declBus(c+3102,"cache_simX dmem_controller dcache genblk3[1] bank_structure NUM_WORDS_PER_BLOCK",-1,31,0); + vcdp->declBus(c+3125,"cache_simX dmem_controller dcache genblk3[1] bank_structure OFFSET_SIZE_START",-1,31,0); + vcdp->declBus(c+3119,"cache_simX dmem_controller dcache genblk3[1] bank_structure OFFSET_SIZE_END",-1,31,0); + vcdp->declBus(c+3125,"cache_simX dmem_controller dcache genblk3[1] bank_structure TAG_SIZE_START",-1,31,0); + vcdp->declBus(c+3144,"cache_simX dmem_controller dcache genblk3[1] bank_structure TAG_SIZE_END",-1,31,0); + vcdp->declBus(c+3125,"cache_simX dmem_controller dcache genblk3[1] bank_structure IND_SIZE_START",-1,31,0); + vcdp->declBus(c+3102,"cache_simX dmem_controller dcache genblk3[1] bank_structure IND_SIZE_END",-1,31,0); + vcdp->declBus(c+3145,"cache_simX dmem_controller dcache genblk3[1] bank_structure ADDR_TAG_START",-1,31,0); + vcdp->declBus(c+3146,"cache_simX dmem_controller dcache genblk3[1] bank_structure ADDR_TAG_END",-1,31,0); + vcdp->declBus(c+3102,"cache_simX dmem_controller dcache genblk3[1] bank_structure ADDR_OFFSET_START",-1,31,0); + vcdp->declBus(c+3136,"cache_simX dmem_controller dcache genblk3[1] bank_structure ADDR_OFFSET_END",-1,31,0); + vcdp->declBus(c+3137,"cache_simX dmem_controller dcache genblk3[1] bank_structure ADDR_IND_START",-1,31,0); + vcdp->declBus(c+3147,"cache_simX dmem_controller dcache genblk3[1] bank_structure ADDR_IND_END",-1,31,0); + vcdp->declBus(c+3125,"cache_simX dmem_controller dcache genblk3[1] bank_structure CACHE_IDLE",-1,31,0); + vcdp->declBus(c+3119,"cache_simX dmem_controller dcache genblk3[1] bank_structure SEND_MEM_REQ",-1,31,0); + vcdp->declBus(c+3133,"cache_simX dmem_controller dcache genblk3[1] bank_structure RECIV_MEM_RSP",-1,31,0); + vcdp->declBus(c+3137,"cache_simX dmem_controller dcache genblk3[1] bank_structure BLOCK_NUM_BITS",-1,31,0); + vcdp->declBit(c+3086,"cache_simX dmem_controller dcache genblk3[1] bank_structure rst",-1); + vcdp->declBit(c+3085,"cache_simX dmem_controller dcache genblk3[1] bank_structure clk",-1); + vcdp->declBus(c+817,"cache_simX dmem_controller dcache genblk3[1] bank_structure state",-1,3,0); + vcdp->declBus(c+213,"cache_simX dmem_controller dcache genblk3[1] bank_structure actual_index",-1,4,0); + vcdp->declBus(c+214,"cache_simX dmem_controller dcache genblk3[1] bank_structure o_tag",-1,20,0); + vcdp->declBus(c+212,"cache_simX dmem_controller dcache genblk3[1] bank_structure block_offset",-1,1,0); + vcdp->declBus(c+448,"cache_simX dmem_controller dcache genblk3[1] bank_structure writedata",-1,31,0); + vcdp->declBit(c+216,"cache_simX dmem_controller dcache genblk3[1] bank_structure valid_in",-1); + vcdp->declBit(c+35,"cache_simX dmem_controller dcache genblk3[1] bank_structure read_or_write",-1); + vcdp->declArray(c+3163,"cache_simX dmem_controller dcache genblk3[1] bank_structure fetched_writedata",-1,127,0); + vcdp->declBus(c+36,"cache_simX dmem_controller dcache genblk3[1] bank_structure i_p_mem_read",-1,2,0); + vcdp->declBus(c+37,"cache_simX dmem_controller dcache genblk3[1] bank_structure i_p_mem_write",-1,2,0); + vcdp->declBus(c+211,"cache_simX dmem_controller dcache genblk3[1] bank_structure byte_select",-1,1,0); + vcdp->declBus(c+816,"cache_simX dmem_controller dcache genblk3[1] bank_structure evicted_way",-1,0,0); + vcdp->declBus(c+449,"cache_simX dmem_controller dcache genblk3[1] bank_structure readdata",-1,31,0); + vcdp->declBit(c+450,"cache_simX dmem_controller dcache genblk3[1] bank_structure hit",-1); + vcdp->declBit(c+451,"cache_simX dmem_controller dcache genblk3[1] bank_structure eviction_wb",-1); + vcdp->declBus(c+452,"cache_simX dmem_controller dcache genblk3[1] bank_structure eviction_addr",-1,31,0); + vcdp->declArray(c+453,"cache_simX dmem_controller dcache genblk3[1] bank_structure data_evicted",-1,127,0); + vcdp->declArray(c+453,"cache_simX dmem_controller dcache genblk3[1] bank_structure data_use",-1,127,0); + vcdp->declBus(c+457,"cache_simX dmem_controller dcache genblk3[1] bank_structure tag_use",-1,20,0); + vcdp->declBus(c+457,"cache_simX dmem_controller dcache genblk3[1] bank_structure eviction_tag",-1,20,0); + vcdp->declBit(c+458,"cache_simX dmem_controller dcache genblk3[1] bank_structure valid_use",-1); + vcdp->declBit(c+451,"cache_simX dmem_controller dcache genblk3[1] bank_structure dirty_use",-1); + vcdp->declBit(c+459,"cache_simX dmem_controller dcache genblk3[1] bank_structure access",-1); + vcdp->declBit(c+460,"cache_simX dmem_controller dcache genblk3[1] bank_structure write_from_mem",-1); + vcdp->declBit(c+461,"cache_simX dmem_controller dcache genblk3[1] bank_structure miss",-1); + vcdp->declBus(c+797,"cache_simX dmem_controller dcache genblk3[1] bank_structure way_to_update",-1,0,0); + vcdp->declBit(c+367,"cache_simX dmem_controller dcache genblk3[1] bank_structure lw",-1); + vcdp->declBit(c+368,"cache_simX dmem_controller dcache genblk3[1] bank_structure lb",-1); + vcdp->declBit(c+369,"cache_simX dmem_controller dcache genblk3[1] bank_structure lh",-1); + vcdp->declBit(c+370,"cache_simX dmem_controller dcache genblk3[1] bank_structure lhu",-1); + vcdp->declBit(c+371,"cache_simX dmem_controller dcache genblk3[1] bank_structure lbu",-1); + vcdp->declBit(c+372,"cache_simX dmem_controller dcache genblk3[1] bank_structure sw",-1); + vcdp->declBit(c+373,"cache_simX dmem_controller dcache genblk3[1] bank_structure sb",-1); + vcdp->declBit(c+374,"cache_simX dmem_controller dcache genblk3[1] bank_structure sh",-1); + vcdp->declBit(c+462,"cache_simX dmem_controller dcache genblk3[1] bank_structure b0",-1); + vcdp->declBit(c+463,"cache_simX dmem_controller dcache genblk3[1] bank_structure b1",-1); + vcdp->declBit(c+464,"cache_simX dmem_controller dcache genblk3[1] bank_structure b2",-1); + vcdp->declBit(c+465,"cache_simX dmem_controller dcache genblk3[1] bank_structure b3",-1); + vcdp->declBus(c+466,"cache_simX dmem_controller dcache genblk3[1] bank_structure data_unQual",-1,31,0); + vcdp->declBus(c+467,"cache_simX dmem_controller dcache genblk3[1] bank_structure lb_data",-1,31,0); + vcdp->declBus(c+468,"cache_simX dmem_controller dcache genblk3[1] bank_structure lh_data",-1,31,0); + vcdp->declBus(c+469,"cache_simX dmem_controller dcache genblk3[1] bank_structure lbu_data",-1,31,0); + vcdp->declBus(c+470,"cache_simX dmem_controller dcache genblk3[1] bank_structure lhu_data",-1,31,0); + vcdp->declBus(c+466,"cache_simX dmem_controller dcache genblk3[1] bank_structure lw_data",-1,31,0); + vcdp->declBus(c+448,"cache_simX dmem_controller dcache genblk3[1] bank_structure sw_data",-1,31,0); + vcdp->declBus(c+471,"cache_simX dmem_controller dcache genblk3[1] bank_structure sb_data",-1,31,0); + vcdp->declBus(c+472,"cache_simX dmem_controller dcache genblk3[1] bank_structure sh_data",-1,31,0); + vcdp->declBus(c+473,"cache_simX dmem_controller dcache genblk3[1] bank_structure use_write_data",-1,31,0); + vcdp->declBus(c+474,"cache_simX dmem_controller dcache genblk3[1] bank_structure data_Qual",-1,31,0); + vcdp->declBus(c+475,"cache_simX dmem_controller dcache genblk3[1] bank_structure sb_mask",-1,3,0); + vcdp->declBus(c+476,"cache_simX dmem_controller dcache genblk3[1] bank_structure sh_mask",-1,3,0); + vcdp->declBus(c+477,"cache_simX dmem_controller dcache genblk3[1] bank_structure we",-1,15,0); + vcdp->declArray(c+478,"cache_simX dmem_controller dcache genblk3[1] bank_structure data_write",-1,127,0); + vcdp->declBit(c+482,"cache_simX dmem_controller dcache genblk3[1] bank_structure genblk1[0] normal_write",-1); + vcdp->declBit(c+483,"cache_simX dmem_controller dcache genblk3[1] bank_structure genblk1[1] normal_write",-1); + vcdp->declBit(c+484,"cache_simX dmem_controller dcache genblk3[1] bank_structure genblk1[2] normal_write",-1); + vcdp->declBit(c+485,"cache_simX dmem_controller dcache genblk3[1] bank_structure genblk1[3] normal_write",-1); + vcdp->declBus(c+3133,"cache_simX dmem_controller dcache genblk3[1] bank_structure data_structures CACHE_WAYS",-1,31,0); + vcdp->declBus(c+3143,"cache_simX dmem_controller dcache genblk3[1] bank_structure data_structures NUM_IND",-1,31,0); + vcdp->declBus(c+3119,"cache_simX dmem_controller dcache genblk3[1] bank_structure data_structures CACHE_WAY_INDEX",-1,31,0); + vcdp->declBus(c+3102,"cache_simX dmem_controller dcache genblk3[1] bank_structure data_structures NUM_WORDS_PER_BLOCK",-1,31,0); + vcdp->declBus(c+3125,"cache_simX dmem_controller dcache genblk3[1] bank_structure data_structures TAG_SIZE_START",-1,31,0); + vcdp->declBus(c+3144,"cache_simX dmem_controller dcache genblk3[1] bank_structure data_structures TAG_SIZE_END",-1,31,0); + vcdp->declBus(c+3125,"cache_simX dmem_controller dcache genblk3[1] bank_structure data_structures IND_SIZE_START",-1,31,0); + vcdp->declBus(c+3102,"cache_simX dmem_controller dcache genblk3[1] bank_structure data_structures IND_SIZE_END",-1,31,0); + vcdp->declBit(c+3085,"cache_simX dmem_controller dcache genblk3[1] bank_structure data_structures clk",-1); + vcdp->declBit(c+3086,"cache_simX dmem_controller dcache genblk3[1] bank_structure data_structures rst",-1); + vcdp->declBit(c+216,"cache_simX dmem_controller dcache genblk3[1] bank_structure data_structures valid_in",-1); + vcdp->declBus(c+817,"cache_simX dmem_controller dcache genblk3[1] bank_structure data_structures state",-1,3,0); + vcdp->declBus(c+213,"cache_simX dmem_controller dcache genblk3[1] bank_structure data_structures addr",-1,4,0); + vcdp->declBus(c+477,"cache_simX dmem_controller dcache genblk3[1] bank_structure data_structures we",-1,15,0); + vcdp->declBit(c+460,"cache_simX dmem_controller dcache genblk3[1] bank_structure data_structures evict",-1); + vcdp->declBus(c+797,"cache_simX dmem_controller dcache genblk3[1] bank_structure data_structures way_to_update",-1,0,0); + vcdp->declArray(c+478,"cache_simX dmem_controller dcache genblk3[1] bank_structure data_structures data_write",-1,127,0); + vcdp->declBus(c+214,"cache_simX dmem_controller dcache genblk3[1] bank_structure data_structures tag_write",-1,20,0); + vcdp->declBus(c+457,"cache_simX dmem_controller dcache genblk3[1] bank_structure data_structures tag_use",-1,20,0); + vcdp->declArray(c+453,"cache_simX dmem_controller dcache genblk3[1] bank_structure data_structures data_use",-1,127,0); + vcdp->declBit(c+458,"cache_simX dmem_controller dcache genblk3[1] bank_structure data_structures valid_use",-1); + vcdp->declBit(c+451,"cache_simX dmem_controller dcache genblk3[1] bank_structure data_structures dirty_use",-1); + vcdp->declQuad(c+486,"cache_simX dmem_controller dcache genblk3[1] bank_structure data_structures tag_use_per_way",-1,41,0); + vcdp->declArray(c+488,"cache_simX dmem_controller dcache genblk3[1] bank_structure data_structures data_use_per_way",-1,255,0); + vcdp->declBus(c+496,"cache_simX dmem_controller dcache genblk3[1] bank_structure data_structures valid_use_per_way",-1,1,0); + vcdp->declBus(c+497,"cache_simX dmem_controller dcache genblk3[1] bank_structure data_structures dirty_use_per_way",-1,1,0); + vcdp->declBus(c+498,"cache_simX dmem_controller dcache genblk3[1] bank_structure data_structures hit_per_way",-1,1,0); + vcdp->declBus(c+499,"cache_simX dmem_controller dcache genblk3[1] bank_structure data_structures we_per_way",-1,31,0); + vcdp->declArray(c+500,"cache_simX dmem_controller dcache genblk3[1] bank_structure data_structures data_write_per_way",-1,255,0); + vcdp->declBus(c+508,"cache_simX dmem_controller dcache genblk3[1] bank_structure data_structures write_from_mem_per_way",-1,1,0); + vcdp->declBit(c+509,"cache_simX dmem_controller dcache genblk3[1] bank_structure data_structures invalid_found",-1); + vcdp->declBus(c+510,"cache_simX dmem_controller dcache genblk3[1] bank_structure data_structures way_index",-1,0,0); + vcdp->declBus(c+511,"cache_simX dmem_controller dcache genblk3[1] bank_structure data_structures invalid_index",-1,0,0); + vcdp->declBus(c+3125,"cache_simX dmem_controller dcache genblk3[1] bank_structure data_structures CACHE_IDLE",-1,31,0); + vcdp->declBus(c+3119,"cache_simX dmem_controller dcache genblk3[1] bank_structure data_structures SEND_MEM_REQ",-1,31,0); + vcdp->declBus(c+3133,"cache_simX dmem_controller dcache genblk3[1] bank_structure data_structures RECIV_MEM_RSP",-1,31,0); + vcdp->declBus(c+512,"cache_simX dmem_controller dcache genblk3[1] bank_structure data_structures way_use_Qual",-1,0,0); + vcdp->declBus(c+3133,"cache_simX dmem_controller dcache genblk3[1] bank_structure data_structures genblk1 valid_index N",-1,31,0); + vcdp->declBus(c+513,"cache_simX dmem_controller dcache genblk3[1] bank_structure data_structures genblk1 valid_index valids",-1,1,0); + vcdp->declBus(c+511,"cache_simX dmem_controller dcache genblk3[1] bank_structure data_structures genblk1 valid_index index",-1,0,0); + vcdp->declBit(c+509,"cache_simX dmem_controller dcache genblk3[1] bank_structure data_structures genblk1 valid_index found",-1); + vcdp->declBus(c+3140,"cache_simX dmem_controller dcache genblk3[1] bank_structure data_structures genblk1 valid_index i",-1,31,0); + vcdp->declBus(c+3133,"cache_simX dmem_controller dcache genblk3[1] bank_structure data_structures genblk1 way_indexing N",-1,31,0); + vcdp->declBus(c+498,"cache_simX dmem_controller dcache genblk3[1] bank_structure data_structures genblk1 way_indexing valids",-1,1,0); + vcdp->declBus(c+510,"cache_simX dmem_controller dcache genblk3[1] bank_structure data_structures genblk1 way_indexing index",-1,0,0); + vcdp->declBit(c+514,"cache_simX dmem_controller dcache genblk3[1] bank_structure data_structures genblk1 way_indexing found",-1); + vcdp->declBus(c+3140,"cache_simX dmem_controller dcache genblk3[1] bank_structure data_structures genblk1 way_indexing i",-1,31,0); + vcdp->declBus(c+3143,"cache_simX dmem_controller dcache genblk3[1] bank_structure data_structures each_way[0] data_structures NUM_IND",-1,31,0); + vcdp->declBus(c+3102,"cache_simX dmem_controller dcache genblk3[1] bank_structure data_structures each_way[0] data_structures NUM_WORDS_PER_BLOCK",-1,31,0); + vcdp->declBus(c+3125,"cache_simX dmem_controller dcache genblk3[1] bank_structure data_structures each_way[0] data_structures TAG_SIZE_START",-1,31,0); + vcdp->declBus(c+3144,"cache_simX dmem_controller dcache genblk3[1] bank_structure data_structures each_way[0] data_structures TAG_SIZE_END",-1,31,0); + vcdp->declBus(c+3125,"cache_simX dmem_controller dcache genblk3[1] bank_structure data_structures each_way[0] data_structures IND_SIZE_START",-1,31,0); + vcdp->declBus(c+3102,"cache_simX dmem_controller dcache genblk3[1] bank_structure data_structures each_way[0] data_structures IND_SIZE_END",-1,31,0); + vcdp->declBit(c+3085,"cache_simX dmem_controller dcache genblk3[1] bank_structure data_structures each_way[0] data_structures clk",-1); + vcdp->declBit(c+3086,"cache_simX dmem_controller dcache genblk3[1] bank_structure data_structures each_way[0] data_structures rst",-1); + vcdp->declBus(c+213,"cache_simX dmem_controller dcache genblk3[1] bank_structure data_structures each_way[0] data_structures addr",-1,4,0); + vcdp->declBus(c+515,"cache_simX dmem_controller dcache genblk3[1] bank_structure data_structures each_way[0] data_structures we",-1,15,0); + vcdp->declBit(c+516,"cache_simX dmem_controller dcache genblk3[1] bank_structure data_structures each_way[0] data_structures evict",-1); + vcdp->declArray(c+517,"cache_simX dmem_controller dcache genblk3[1] bank_structure data_structures each_way[0] data_structures data_write",-1,127,0); + vcdp->declBus(c+214,"cache_simX dmem_controller dcache genblk3[1] bank_structure data_structures each_way[0] data_structures tag_write",-1,20,0); + vcdp->declBus(c+759,"cache_simX dmem_controller dcache genblk3[1] bank_structure data_structures each_way[0] data_structures tag_use",-1,20,0); + vcdp->declArray(c+760,"cache_simX dmem_controller dcache genblk3[1] bank_structure data_structures each_way[0] data_structures data_use",-1,127,0); + vcdp->declBit(c+764,"cache_simX dmem_controller dcache genblk3[1] bank_structure data_structures each_way[0] data_structures valid_use",-1); + vcdp->declBit(c+521,"cache_simX dmem_controller dcache genblk3[1] bank_structure data_structures each_way[0] data_structures dirty_use",-1); + vcdp->declBit(c+522,"cache_simX dmem_controller dcache genblk3[1] bank_structure data_structures each_way[0] data_structures currently_writing",-1); + vcdp->declBit(c+523,"cache_simX dmem_controller dcache genblk3[1] bank_structure data_structures each_way[0] data_structures update_dirty",-1); + vcdp->declBit(c+524,"cache_simX dmem_controller dcache genblk3[1] bank_structure data_structures each_way[0] data_structures dirt_new",-1); + vcdp->declArray(c+1729,"cache_simX dmem_controller dcache genblk3[1] bank_structure data_structures each_way[0] data_structures data(0)",-1,127,0); + vcdp->declArray(c+1733,"cache_simX dmem_controller dcache genblk3[1] bank_structure data_structures each_way[0] data_structures data(1)",-1,127,0); + vcdp->declArray(c+1737,"cache_simX dmem_controller dcache genblk3[1] bank_structure data_structures each_way[0] data_structures data(2)",-1,127,0); + vcdp->declArray(c+1741,"cache_simX dmem_controller dcache genblk3[1] bank_structure data_structures each_way[0] data_structures data(3)",-1,127,0); + vcdp->declArray(c+1745,"cache_simX dmem_controller dcache genblk3[1] bank_structure data_structures each_way[0] data_structures data(4)",-1,127,0); + vcdp->declArray(c+1749,"cache_simX dmem_controller dcache genblk3[1] bank_structure data_structures each_way[0] data_structures data(5)",-1,127,0); + vcdp->declArray(c+1753,"cache_simX dmem_controller dcache genblk3[1] bank_structure data_structures each_way[0] data_structures data(6)",-1,127,0); + vcdp->declArray(c+1757,"cache_simX dmem_controller dcache genblk3[1] bank_structure data_structures each_way[0] data_structures data(7)",-1,127,0); + vcdp->declArray(c+1761,"cache_simX dmem_controller dcache genblk3[1] bank_structure data_structures each_way[0] data_structures data(8)",-1,127,0); + vcdp->declArray(c+1765,"cache_simX dmem_controller dcache genblk3[1] bank_structure data_structures each_way[0] data_structures data(9)",-1,127,0); + vcdp->declArray(c+1769,"cache_simX dmem_controller dcache genblk3[1] bank_structure data_structures each_way[0] data_structures data(10)",-1,127,0); + vcdp->declArray(c+1773,"cache_simX dmem_controller dcache genblk3[1] bank_structure data_structures each_way[0] data_structures data(11)",-1,127,0); + vcdp->declArray(c+1777,"cache_simX dmem_controller dcache genblk3[1] bank_structure data_structures each_way[0] data_structures data(12)",-1,127,0); + vcdp->declArray(c+1781,"cache_simX dmem_controller dcache genblk3[1] bank_structure data_structures each_way[0] data_structures data(13)",-1,127,0); + vcdp->declArray(c+1785,"cache_simX dmem_controller dcache genblk3[1] bank_structure data_structures each_way[0] data_structures data(14)",-1,127,0); + vcdp->declArray(c+1789,"cache_simX dmem_controller dcache genblk3[1] bank_structure data_structures each_way[0] data_structures data(15)",-1,127,0); + vcdp->declArray(c+1793,"cache_simX dmem_controller dcache genblk3[1] bank_structure data_structures each_way[0] data_structures data(16)",-1,127,0); + vcdp->declArray(c+1797,"cache_simX dmem_controller dcache genblk3[1] bank_structure data_structures each_way[0] data_structures data(17)",-1,127,0); + vcdp->declArray(c+1801,"cache_simX dmem_controller dcache genblk3[1] bank_structure data_structures each_way[0] data_structures data(18)",-1,127,0); + vcdp->declArray(c+1805,"cache_simX dmem_controller dcache genblk3[1] bank_structure data_structures each_way[0] data_structures data(19)",-1,127,0); + vcdp->declArray(c+1809,"cache_simX dmem_controller dcache genblk3[1] bank_structure data_structures each_way[0] data_structures data(20)",-1,127,0); + vcdp->declArray(c+1813,"cache_simX dmem_controller dcache genblk3[1] bank_structure data_structures each_way[0] data_structures data(21)",-1,127,0); + vcdp->declArray(c+1817,"cache_simX dmem_controller dcache genblk3[1] bank_structure data_structures each_way[0] data_structures data(22)",-1,127,0); + vcdp->declArray(c+1821,"cache_simX dmem_controller dcache genblk3[1] bank_structure data_structures each_way[0] data_structures data(23)",-1,127,0); + vcdp->declArray(c+1825,"cache_simX dmem_controller dcache genblk3[1] bank_structure data_structures each_way[0] data_structures data(24)",-1,127,0); + vcdp->declArray(c+1829,"cache_simX dmem_controller dcache genblk3[1] bank_structure data_structures each_way[0] data_structures data(25)",-1,127,0); + vcdp->declArray(c+1833,"cache_simX dmem_controller dcache genblk3[1] bank_structure data_structures each_way[0] data_structures data(26)",-1,127,0); + vcdp->declArray(c+1837,"cache_simX dmem_controller dcache genblk3[1] bank_structure data_structures each_way[0] data_structures data(27)",-1,127,0); + vcdp->declArray(c+1841,"cache_simX dmem_controller dcache genblk3[1] bank_structure data_structures each_way[0] data_structures data(28)",-1,127,0); + vcdp->declArray(c+1845,"cache_simX dmem_controller dcache genblk3[1] bank_structure data_structures each_way[0] data_structures data(29)",-1,127,0); + vcdp->declArray(c+1849,"cache_simX dmem_controller dcache genblk3[1] bank_structure data_structures each_way[0] data_structures data(30)",-1,127,0); + vcdp->declArray(c+1853,"cache_simX dmem_controller dcache genblk3[1] bank_structure data_structures each_way[0] data_structures data(31)",-1,127,0); + {int i; for (i=0; i<32; i++) { + vcdp->declBus(c+1857+i*1,"cache_simX dmem_controller dcache genblk3[1] bank_structure data_structures each_way[0] data_structures tag",(i+0),20,0);}} + {int i; for (i=0; i<32; i++) { + vcdp->declBit(c+1889+i*1,"cache_simX dmem_controller dcache genblk3[1] bank_structure data_structures each_way[0] data_structures valid",(i+0));}} + {int i; for (i=0; i<32; i++) { + vcdp->declBit(c+1921+i*1,"cache_simX dmem_controller dcache genblk3[1] bank_structure data_structures each_way[0] data_structures dirty",(i+0));}} + vcdp->declBus(c+1953,"cache_simX dmem_controller dcache genblk3[1] bank_structure data_structures each_way[0] data_structures f",-1,31,0); + vcdp->declBus(c+1954,"cache_simX dmem_controller dcache genblk3[1] bank_structure data_structures each_way[0] data_structures ini_ind",-1,31,0); + vcdp->declBus(c+3143,"cache_simX dmem_controller dcache genblk3[1] bank_structure data_structures each_way[1] data_structures NUM_IND",-1,31,0); + vcdp->declBus(c+3102,"cache_simX dmem_controller dcache genblk3[1] bank_structure data_structures each_way[1] data_structures NUM_WORDS_PER_BLOCK",-1,31,0); + vcdp->declBus(c+3125,"cache_simX dmem_controller dcache genblk3[1] bank_structure data_structures each_way[1] data_structures TAG_SIZE_START",-1,31,0); + vcdp->declBus(c+3144,"cache_simX dmem_controller dcache genblk3[1] bank_structure data_structures each_way[1] data_structures TAG_SIZE_END",-1,31,0); + vcdp->declBus(c+3125,"cache_simX dmem_controller dcache genblk3[1] bank_structure data_structures each_way[1] data_structures IND_SIZE_START",-1,31,0); + vcdp->declBus(c+3102,"cache_simX dmem_controller dcache genblk3[1] bank_structure data_structures each_way[1] data_structures IND_SIZE_END",-1,31,0); + vcdp->declBit(c+3085,"cache_simX dmem_controller dcache genblk3[1] bank_structure data_structures each_way[1] data_structures clk",-1); + vcdp->declBit(c+3086,"cache_simX dmem_controller dcache genblk3[1] bank_structure data_structures each_way[1] data_structures rst",-1); + vcdp->declBus(c+213,"cache_simX dmem_controller dcache genblk3[1] bank_structure data_structures each_way[1] data_structures addr",-1,4,0); + vcdp->declBus(c+525,"cache_simX dmem_controller dcache genblk3[1] bank_structure data_structures each_way[1] data_structures we",-1,15,0); + vcdp->declBit(c+526,"cache_simX dmem_controller dcache genblk3[1] bank_structure data_structures each_way[1] data_structures evict",-1); + vcdp->declArray(c+527,"cache_simX dmem_controller dcache genblk3[1] bank_structure data_structures each_way[1] data_structures data_write",-1,127,0); + vcdp->declBus(c+214,"cache_simX dmem_controller dcache genblk3[1] bank_structure data_structures each_way[1] data_structures tag_write",-1,20,0); + vcdp->declBus(c+765,"cache_simX dmem_controller dcache genblk3[1] bank_structure data_structures each_way[1] data_structures tag_use",-1,20,0); + vcdp->declArray(c+766,"cache_simX dmem_controller dcache genblk3[1] bank_structure data_structures each_way[1] data_structures data_use",-1,127,0); + vcdp->declBit(c+770,"cache_simX dmem_controller dcache genblk3[1] bank_structure data_structures each_way[1] data_structures valid_use",-1); + vcdp->declBit(c+531,"cache_simX dmem_controller dcache genblk3[1] bank_structure data_structures each_way[1] data_structures dirty_use",-1); + vcdp->declBit(c+532,"cache_simX dmem_controller dcache genblk3[1] bank_structure data_structures each_way[1] data_structures currently_writing",-1); + vcdp->declBit(c+533,"cache_simX dmem_controller dcache genblk3[1] bank_structure data_structures each_way[1] data_structures update_dirty",-1); + vcdp->declBit(c+534,"cache_simX dmem_controller dcache genblk3[1] bank_structure data_structures each_way[1] data_structures dirt_new",-1); + vcdp->declArray(c+1955,"cache_simX dmem_controller dcache genblk3[1] bank_structure data_structures each_way[1] data_structures data(0)",-1,127,0); + vcdp->declArray(c+1959,"cache_simX dmem_controller dcache genblk3[1] bank_structure data_structures each_way[1] data_structures data(1)",-1,127,0); + vcdp->declArray(c+1963,"cache_simX dmem_controller dcache genblk3[1] bank_structure data_structures each_way[1] data_structures data(2)",-1,127,0); + vcdp->declArray(c+1967,"cache_simX dmem_controller dcache genblk3[1] bank_structure data_structures each_way[1] data_structures data(3)",-1,127,0); + vcdp->declArray(c+1971,"cache_simX dmem_controller dcache genblk3[1] bank_structure data_structures each_way[1] data_structures data(4)",-1,127,0); + vcdp->declArray(c+1975,"cache_simX dmem_controller dcache genblk3[1] bank_structure data_structures each_way[1] data_structures data(5)",-1,127,0); + vcdp->declArray(c+1979,"cache_simX dmem_controller dcache genblk3[1] bank_structure data_structures each_way[1] data_structures data(6)",-1,127,0); + vcdp->declArray(c+1983,"cache_simX dmem_controller dcache genblk3[1] bank_structure data_structures each_way[1] data_structures data(7)",-1,127,0); + vcdp->declArray(c+1987,"cache_simX dmem_controller dcache genblk3[1] bank_structure data_structures each_way[1] data_structures data(8)",-1,127,0); + vcdp->declArray(c+1991,"cache_simX dmem_controller dcache genblk3[1] bank_structure data_structures each_way[1] data_structures data(9)",-1,127,0); + vcdp->declArray(c+1995,"cache_simX dmem_controller dcache genblk3[1] bank_structure data_structures each_way[1] data_structures data(10)",-1,127,0); + vcdp->declArray(c+1999,"cache_simX dmem_controller dcache genblk3[1] bank_structure data_structures each_way[1] data_structures data(11)",-1,127,0); + vcdp->declArray(c+2003,"cache_simX dmem_controller dcache genblk3[1] bank_structure data_structures each_way[1] data_structures data(12)",-1,127,0); + vcdp->declArray(c+2007,"cache_simX dmem_controller dcache genblk3[1] bank_structure data_structures each_way[1] data_structures data(13)",-1,127,0); + vcdp->declArray(c+2011,"cache_simX dmem_controller dcache genblk3[1] bank_structure data_structures each_way[1] data_structures data(14)",-1,127,0); + vcdp->declArray(c+2015,"cache_simX dmem_controller dcache genblk3[1] bank_structure data_structures each_way[1] data_structures data(15)",-1,127,0); + vcdp->declArray(c+2019,"cache_simX dmem_controller dcache genblk3[1] bank_structure data_structures each_way[1] data_structures data(16)",-1,127,0); + vcdp->declArray(c+2023,"cache_simX dmem_controller dcache genblk3[1] bank_structure data_structures each_way[1] data_structures data(17)",-1,127,0); + vcdp->declArray(c+2027,"cache_simX dmem_controller dcache genblk3[1] bank_structure data_structures each_way[1] data_structures data(18)",-1,127,0); + vcdp->declArray(c+2031,"cache_simX dmem_controller dcache genblk3[1] bank_structure data_structures each_way[1] data_structures data(19)",-1,127,0); + vcdp->declArray(c+2035,"cache_simX dmem_controller dcache genblk3[1] bank_structure data_structures each_way[1] data_structures data(20)",-1,127,0); + vcdp->declArray(c+2039,"cache_simX dmem_controller dcache genblk3[1] bank_structure data_structures each_way[1] data_structures data(21)",-1,127,0); + vcdp->declArray(c+2043,"cache_simX dmem_controller dcache genblk3[1] bank_structure data_structures each_way[1] data_structures data(22)",-1,127,0); + vcdp->declArray(c+2047,"cache_simX dmem_controller dcache genblk3[1] bank_structure data_structures each_way[1] data_structures data(23)",-1,127,0); + vcdp->declArray(c+2051,"cache_simX dmem_controller dcache genblk3[1] bank_structure data_structures each_way[1] data_structures data(24)",-1,127,0); + vcdp->declArray(c+2055,"cache_simX dmem_controller dcache genblk3[1] bank_structure data_structures each_way[1] data_structures data(25)",-1,127,0); + vcdp->declArray(c+2059,"cache_simX dmem_controller dcache genblk3[1] bank_structure data_structures each_way[1] data_structures data(26)",-1,127,0); + vcdp->declArray(c+2063,"cache_simX dmem_controller dcache genblk3[1] bank_structure data_structures each_way[1] data_structures data(27)",-1,127,0); + vcdp->declArray(c+2067,"cache_simX dmem_controller dcache genblk3[1] bank_structure data_structures each_way[1] data_structures data(28)",-1,127,0); + vcdp->declArray(c+2071,"cache_simX dmem_controller dcache genblk3[1] bank_structure data_structures each_way[1] data_structures data(29)",-1,127,0); + vcdp->declArray(c+2075,"cache_simX dmem_controller dcache genblk3[1] bank_structure data_structures each_way[1] data_structures data(30)",-1,127,0); + vcdp->declArray(c+2079,"cache_simX dmem_controller dcache genblk3[1] bank_structure data_structures each_way[1] data_structures data(31)",-1,127,0); + {int i; for (i=0; i<32; i++) { + vcdp->declBus(c+2083+i*1,"cache_simX dmem_controller dcache genblk3[1] bank_structure data_structures each_way[1] data_structures tag",(i+0),20,0);}} + {int i; for (i=0; i<32; i++) { + vcdp->declBit(c+2115+i*1,"cache_simX dmem_controller dcache genblk3[1] bank_structure data_structures each_way[1] data_structures valid",(i+0));}} + {int i; for (i=0; i<32; i++) { + vcdp->declBit(c+2147+i*1,"cache_simX dmem_controller dcache genblk3[1] bank_structure data_structures each_way[1] data_structures dirty",(i+0));}} + vcdp->declBus(c+2179,"cache_simX dmem_controller dcache genblk3[1] bank_structure data_structures each_way[1] data_structures f",-1,31,0); + vcdp->declBus(c+2180,"cache_simX dmem_controller dcache genblk3[1] bank_structure data_structures each_way[1] data_structures ini_ind",-1,31,0); + vcdp->declBus(c+3141,"cache_simX dmem_controller dcache genblk3[2] bank_structure CACHE_SIZE",-1,31,0); + vcdp->declBus(c+3133,"cache_simX dmem_controller dcache genblk3[2] bank_structure CACHE_WAYS",-1,31,0); + vcdp->declBus(c+3142,"cache_simX dmem_controller dcache genblk3[2] bank_structure CACHE_BLOCK",-1,31,0); + vcdp->declBus(c+3102,"cache_simX dmem_controller dcache genblk3[2] bank_structure CACHE_BANKS",-1,31,0); + vcdp->declBus(c+3133,"cache_simX dmem_controller dcache genblk3[2] bank_structure LOG_NUM_BANKS",-1,31,0); + vcdp->declBus(c+3102,"cache_simX dmem_controller dcache genblk3[2] bank_structure NUM_REQ",-1,31,0); + vcdp->declBus(c+3133,"cache_simX dmem_controller dcache genblk3[2] bank_structure LOG_NUM_REQ",-1,31,0); + vcdp->declBus(c+3143,"cache_simX dmem_controller dcache genblk3[2] bank_structure NUM_IND",-1,31,0); + vcdp->declBus(c+3119,"cache_simX dmem_controller dcache genblk3[2] bank_structure CACHE_WAY_INDEX",-1,31,0); + vcdp->declBus(c+3102,"cache_simX dmem_controller dcache genblk3[2] bank_structure NUM_WORDS_PER_BLOCK",-1,31,0); + vcdp->declBus(c+3125,"cache_simX dmem_controller dcache genblk3[2] bank_structure OFFSET_SIZE_START",-1,31,0); + vcdp->declBus(c+3119,"cache_simX dmem_controller dcache genblk3[2] bank_structure OFFSET_SIZE_END",-1,31,0); + vcdp->declBus(c+3125,"cache_simX dmem_controller dcache genblk3[2] bank_structure TAG_SIZE_START",-1,31,0); + vcdp->declBus(c+3144,"cache_simX dmem_controller dcache genblk3[2] bank_structure TAG_SIZE_END",-1,31,0); + vcdp->declBus(c+3125,"cache_simX dmem_controller dcache genblk3[2] bank_structure IND_SIZE_START",-1,31,0); + vcdp->declBus(c+3102,"cache_simX dmem_controller dcache genblk3[2] bank_structure IND_SIZE_END",-1,31,0); + vcdp->declBus(c+3145,"cache_simX dmem_controller dcache genblk3[2] bank_structure ADDR_TAG_START",-1,31,0); + vcdp->declBus(c+3146,"cache_simX dmem_controller dcache genblk3[2] bank_structure ADDR_TAG_END",-1,31,0); + vcdp->declBus(c+3102,"cache_simX dmem_controller dcache genblk3[2] bank_structure ADDR_OFFSET_START",-1,31,0); + vcdp->declBus(c+3136,"cache_simX dmem_controller dcache genblk3[2] bank_structure ADDR_OFFSET_END",-1,31,0); + vcdp->declBus(c+3137,"cache_simX dmem_controller dcache genblk3[2] bank_structure ADDR_IND_START",-1,31,0); + vcdp->declBus(c+3147,"cache_simX dmem_controller dcache genblk3[2] bank_structure ADDR_IND_END",-1,31,0); + vcdp->declBus(c+3125,"cache_simX dmem_controller dcache genblk3[2] bank_structure CACHE_IDLE",-1,31,0); + vcdp->declBus(c+3119,"cache_simX dmem_controller dcache genblk3[2] bank_structure SEND_MEM_REQ",-1,31,0); + vcdp->declBus(c+3133,"cache_simX dmem_controller dcache genblk3[2] bank_structure RECIV_MEM_RSP",-1,31,0); + vcdp->declBus(c+3137,"cache_simX dmem_controller dcache genblk3[2] bank_structure BLOCK_NUM_BITS",-1,31,0); + vcdp->declBit(c+3086,"cache_simX dmem_controller dcache genblk3[2] bank_structure rst",-1); + vcdp->declBit(c+3085,"cache_simX dmem_controller dcache genblk3[2] bank_structure clk",-1); + vcdp->declBus(c+817,"cache_simX dmem_controller dcache genblk3[2] bank_structure state",-1,3,0); + vcdp->declBus(c+220,"cache_simX dmem_controller dcache genblk3[2] bank_structure actual_index",-1,4,0); + vcdp->declBus(c+221,"cache_simX dmem_controller dcache genblk3[2] bank_structure o_tag",-1,20,0); + vcdp->declBus(c+219,"cache_simX dmem_controller dcache genblk3[2] bank_structure block_offset",-1,1,0); + vcdp->declBus(c+535,"cache_simX dmem_controller dcache genblk3[2] bank_structure writedata",-1,31,0); + vcdp->declBit(c+223,"cache_simX dmem_controller dcache genblk3[2] bank_structure valid_in",-1); + vcdp->declBit(c+35,"cache_simX dmem_controller dcache genblk3[2] bank_structure read_or_write",-1); + vcdp->declArray(c+3167,"cache_simX dmem_controller dcache genblk3[2] bank_structure fetched_writedata",-1,127,0); + vcdp->declBus(c+36,"cache_simX dmem_controller dcache genblk3[2] bank_structure i_p_mem_read",-1,2,0); + vcdp->declBus(c+37,"cache_simX dmem_controller dcache genblk3[2] bank_structure i_p_mem_write",-1,2,0); + vcdp->declBus(c+218,"cache_simX dmem_controller dcache genblk3[2] bank_structure byte_select",-1,1,0); + vcdp->declBus(c+816,"cache_simX dmem_controller dcache genblk3[2] bank_structure evicted_way",-1,0,0); + vcdp->declBus(c+536,"cache_simX dmem_controller dcache genblk3[2] bank_structure readdata",-1,31,0); + vcdp->declBit(c+537,"cache_simX dmem_controller dcache genblk3[2] bank_structure hit",-1); + vcdp->declBit(c+538,"cache_simX dmem_controller dcache genblk3[2] bank_structure eviction_wb",-1); + vcdp->declBus(c+539,"cache_simX dmem_controller dcache genblk3[2] bank_structure eviction_addr",-1,31,0); + vcdp->declArray(c+540,"cache_simX dmem_controller dcache genblk3[2] bank_structure data_evicted",-1,127,0); + vcdp->declArray(c+540,"cache_simX dmem_controller dcache genblk3[2] bank_structure data_use",-1,127,0); + vcdp->declBus(c+544,"cache_simX dmem_controller dcache genblk3[2] bank_structure tag_use",-1,20,0); + vcdp->declBus(c+544,"cache_simX dmem_controller dcache genblk3[2] bank_structure eviction_tag",-1,20,0); + vcdp->declBit(c+545,"cache_simX dmem_controller dcache genblk3[2] bank_structure valid_use",-1); + vcdp->declBit(c+538,"cache_simX dmem_controller dcache genblk3[2] bank_structure dirty_use",-1); + vcdp->declBit(c+546,"cache_simX dmem_controller dcache genblk3[2] bank_structure access",-1); + vcdp->declBit(c+547,"cache_simX dmem_controller dcache genblk3[2] bank_structure write_from_mem",-1); + vcdp->declBit(c+548,"cache_simX dmem_controller dcache genblk3[2] bank_structure miss",-1); + vcdp->declBus(c+798,"cache_simX dmem_controller dcache genblk3[2] bank_structure way_to_update",-1,0,0); + vcdp->declBit(c+367,"cache_simX dmem_controller dcache genblk3[2] bank_structure lw",-1); + vcdp->declBit(c+368,"cache_simX dmem_controller dcache genblk3[2] bank_structure lb",-1); + vcdp->declBit(c+369,"cache_simX dmem_controller dcache genblk3[2] bank_structure lh",-1); + vcdp->declBit(c+370,"cache_simX dmem_controller dcache genblk3[2] bank_structure lhu",-1); + vcdp->declBit(c+371,"cache_simX dmem_controller dcache genblk3[2] bank_structure lbu",-1); + vcdp->declBit(c+372,"cache_simX dmem_controller dcache genblk3[2] bank_structure sw",-1); + vcdp->declBit(c+373,"cache_simX dmem_controller dcache genblk3[2] bank_structure sb",-1); + vcdp->declBit(c+374,"cache_simX dmem_controller dcache genblk3[2] bank_structure sh",-1); + vcdp->declBit(c+549,"cache_simX dmem_controller dcache genblk3[2] bank_structure b0",-1); + vcdp->declBit(c+550,"cache_simX dmem_controller dcache genblk3[2] bank_structure b1",-1); + vcdp->declBit(c+551,"cache_simX dmem_controller dcache genblk3[2] bank_structure b2",-1); + vcdp->declBit(c+552,"cache_simX dmem_controller dcache genblk3[2] bank_structure b3",-1); + vcdp->declBus(c+553,"cache_simX dmem_controller dcache genblk3[2] bank_structure data_unQual",-1,31,0); + vcdp->declBus(c+554,"cache_simX dmem_controller dcache genblk3[2] bank_structure lb_data",-1,31,0); + vcdp->declBus(c+555,"cache_simX dmem_controller dcache genblk3[2] bank_structure lh_data",-1,31,0); + vcdp->declBus(c+556,"cache_simX dmem_controller dcache genblk3[2] bank_structure lbu_data",-1,31,0); + vcdp->declBus(c+557,"cache_simX dmem_controller dcache genblk3[2] bank_structure lhu_data",-1,31,0); + vcdp->declBus(c+553,"cache_simX dmem_controller dcache genblk3[2] bank_structure lw_data",-1,31,0); + vcdp->declBus(c+535,"cache_simX dmem_controller dcache genblk3[2] bank_structure sw_data",-1,31,0); + vcdp->declBus(c+558,"cache_simX dmem_controller dcache genblk3[2] bank_structure sb_data",-1,31,0); + vcdp->declBus(c+559,"cache_simX dmem_controller dcache genblk3[2] bank_structure sh_data",-1,31,0); + vcdp->declBus(c+560,"cache_simX dmem_controller dcache genblk3[2] bank_structure use_write_data",-1,31,0); + vcdp->declBus(c+561,"cache_simX dmem_controller dcache genblk3[2] bank_structure data_Qual",-1,31,0); + vcdp->declBus(c+562,"cache_simX dmem_controller dcache genblk3[2] bank_structure sb_mask",-1,3,0); + vcdp->declBus(c+563,"cache_simX dmem_controller dcache genblk3[2] bank_structure sh_mask",-1,3,0); + vcdp->declBus(c+564,"cache_simX dmem_controller dcache genblk3[2] bank_structure we",-1,15,0); + vcdp->declArray(c+565,"cache_simX dmem_controller dcache genblk3[2] bank_structure data_write",-1,127,0); + vcdp->declBit(c+569,"cache_simX dmem_controller dcache genblk3[2] bank_structure genblk1[0] normal_write",-1); + vcdp->declBit(c+570,"cache_simX dmem_controller dcache genblk3[2] bank_structure genblk1[1] normal_write",-1); + vcdp->declBit(c+571,"cache_simX dmem_controller dcache genblk3[2] bank_structure genblk1[2] normal_write",-1); + vcdp->declBit(c+572,"cache_simX dmem_controller dcache genblk3[2] bank_structure genblk1[3] normal_write",-1); + vcdp->declBus(c+3133,"cache_simX dmem_controller dcache genblk3[2] bank_structure data_structures CACHE_WAYS",-1,31,0); + vcdp->declBus(c+3143,"cache_simX dmem_controller dcache genblk3[2] bank_structure data_structures NUM_IND",-1,31,0); + vcdp->declBus(c+3119,"cache_simX dmem_controller dcache genblk3[2] bank_structure data_structures CACHE_WAY_INDEX",-1,31,0); + vcdp->declBus(c+3102,"cache_simX dmem_controller dcache genblk3[2] bank_structure data_structures NUM_WORDS_PER_BLOCK",-1,31,0); + vcdp->declBus(c+3125,"cache_simX dmem_controller dcache genblk3[2] bank_structure data_structures TAG_SIZE_START",-1,31,0); + vcdp->declBus(c+3144,"cache_simX dmem_controller dcache genblk3[2] bank_structure data_structures TAG_SIZE_END",-1,31,0); + vcdp->declBus(c+3125,"cache_simX dmem_controller dcache genblk3[2] bank_structure data_structures IND_SIZE_START",-1,31,0); + vcdp->declBus(c+3102,"cache_simX dmem_controller dcache genblk3[2] bank_structure data_structures IND_SIZE_END",-1,31,0); + vcdp->declBit(c+3085,"cache_simX dmem_controller dcache genblk3[2] bank_structure data_structures clk",-1); + vcdp->declBit(c+3086,"cache_simX dmem_controller dcache genblk3[2] bank_structure data_structures rst",-1); + vcdp->declBit(c+223,"cache_simX dmem_controller dcache genblk3[2] bank_structure data_structures valid_in",-1); + vcdp->declBus(c+817,"cache_simX dmem_controller dcache genblk3[2] bank_structure data_structures state",-1,3,0); + vcdp->declBus(c+220,"cache_simX dmem_controller dcache genblk3[2] bank_structure data_structures addr",-1,4,0); + vcdp->declBus(c+564,"cache_simX dmem_controller dcache genblk3[2] bank_structure data_structures we",-1,15,0); + vcdp->declBit(c+547,"cache_simX dmem_controller dcache genblk3[2] bank_structure data_structures evict",-1); + vcdp->declBus(c+798,"cache_simX dmem_controller dcache genblk3[2] bank_structure data_structures way_to_update",-1,0,0); + vcdp->declArray(c+565,"cache_simX dmem_controller dcache genblk3[2] bank_structure data_structures data_write",-1,127,0); + vcdp->declBus(c+221,"cache_simX dmem_controller dcache genblk3[2] bank_structure data_structures tag_write",-1,20,0); + vcdp->declBus(c+544,"cache_simX dmem_controller dcache genblk3[2] bank_structure data_structures tag_use",-1,20,0); + vcdp->declArray(c+540,"cache_simX dmem_controller dcache genblk3[2] bank_structure data_structures data_use",-1,127,0); + vcdp->declBit(c+545,"cache_simX dmem_controller dcache genblk3[2] bank_structure data_structures valid_use",-1); + vcdp->declBit(c+538,"cache_simX dmem_controller dcache genblk3[2] bank_structure data_structures dirty_use",-1); + vcdp->declQuad(c+573,"cache_simX dmem_controller dcache genblk3[2] bank_structure data_structures tag_use_per_way",-1,41,0); + vcdp->declArray(c+575,"cache_simX dmem_controller dcache genblk3[2] bank_structure data_structures data_use_per_way",-1,255,0); + vcdp->declBus(c+583,"cache_simX dmem_controller dcache genblk3[2] bank_structure data_structures valid_use_per_way",-1,1,0); + vcdp->declBus(c+584,"cache_simX dmem_controller dcache genblk3[2] bank_structure data_structures dirty_use_per_way",-1,1,0); + vcdp->declBus(c+585,"cache_simX dmem_controller dcache genblk3[2] bank_structure data_structures hit_per_way",-1,1,0); + vcdp->declBus(c+586,"cache_simX dmem_controller dcache genblk3[2] bank_structure data_structures we_per_way",-1,31,0); + vcdp->declArray(c+587,"cache_simX dmem_controller dcache genblk3[2] bank_structure data_structures data_write_per_way",-1,255,0); + vcdp->declBus(c+595,"cache_simX dmem_controller dcache genblk3[2] bank_structure data_structures write_from_mem_per_way",-1,1,0); + vcdp->declBit(c+596,"cache_simX dmem_controller dcache genblk3[2] bank_structure data_structures invalid_found",-1); + vcdp->declBus(c+597,"cache_simX dmem_controller dcache genblk3[2] bank_structure data_structures way_index",-1,0,0); + vcdp->declBus(c+598,"cache_simX dmem_controller dcache genblk3[2] bank_structure data_structures invalid_index",-1,0,0); + vcdp->declBus(c+3125,"cache_simX dmem_controller dcache genblk3[2] bank_structure data_structures CACHE_IDLE",-1,31,0); + vcdp->declBus(c+3119,"cache_simX dmem_controller dcache genblk3[2] bank_structure data_structures SEND_MEM_REQ",-1,31,0); + vcdp->declBus(c+3133,"cache_simX dmem_controller dcache genblk3[2] bank_structure data_structures RECIV_MEM_RSP",-1,31,0); + vcdp->declBus(c+599,"cache_simX dmem_controller dcache genblk3[2] bank_structure data_structures way_use_Qual",-1,0,0); + vcdp->declBus(c+3133,"cache_simX dmem_controller dcache genblk3[2] bank_structure data_structures genblk1 valid_index N",-1,31,0); + vcdp->declBus(c+600,"cache_simX dmem_controller dcache genblk3[2] bank_structure data_structures genblk1 valid_index valids",-1,1,0); + vcdp->declBus(c+598,"cache_simX dmem_controller dcache genblk3[2] bank_structure data_structures genblk1 valid_index index",-1,0,0); + vcdp->declBit(c+596,"cache_simX dmem_controller dcache genblk3[2] bank_structure data_structures genblk1 valid_index found",-1); + vcdp->declBus(c+3140,"cache_simX dmem_controller dcache genblk3[2] bank_structure data_structures genblk1 valid_index i",-1,31,0); + vcdp->declBus(c+3133,"cache_simX dmem_controller dcache genblk3[2] bank_structure data_structures genblk1 way_indexing N",-1,31,0); + vcdp->declBus(c+585,"cache_simX dmem_controller dcache genblk3[2] bank_structure data_structures genblk1 way_indexing valids",-1,1,0); + vcdp->declBus(c+597,"cache_simX dmem_controller dcache genblk3[2] bank_structure data_structures genblk1 way_indexing index",-1,0,0); + vcdp->declBit(c+601,"cache_simX dmem_controller dcache genblk3[2] bank_structure data_structures genblk1 way_indexing found",-1); + vcdp->declBus(c+3140,"cache_simX dmem_controller dcache genblk3[2] bank_structure data_structures genblk1 way_indexing i",-1,31,0); + vcdp->declBus(c+3143,"cache_simX dmem_controller dcache genblk3[2] bank_structure data_structures each_way[0] data_structures NUM_IND",-1,31,0); + vcdp->declBus(c+3102,"cache_simX dmem_controller dcache genblk3[2] bank_structure data_structures each_way[0] data_structures NUM_WORDS_PER_BLOCK",-1,31,0); + vcdp->declBus(c+3125,"cache_simX dmem_controller dcache genblk3[2] bank_structure data_structures each_way[0] data_structures TAG_SIZE_START",-1,31,0); + vcdp->declBus(c+3144,"cache_simX dmem_controller dcache genblk3[2] bank_structure data_structures each_way[0] data_structures TAG_SIZE_END",-1,31,0); + vcdp->declBus(c+3125,"cache_simX dmem_controller dcache genblk3[2] bank_structure data_structures each_way[0] data_structures IND_SIZE_START",-1,31,0); + vcdp->declBus(c+3102,"cache_simX dmem_controller dcache genblk3[2] bank_structure data_structures each_way[0] data_structures IND_SIZE_END",-1,31,0); + vcdp->declBit(c+3085,"cache_simX dmem_controller dcache genblk3[2] bank_structure data_structures each_way[0] data_structures clk",-1); + vcdp->declBit(c+3086,"cache_simX dmem_controller dcache genblk3[2] bank_structure data_structures each_way[0] data_structures rst",-1); + vcdp->declBus(c+220,"cache_simX dmem_controller dcache genblk3[2] bank_structure data_structures each_way[0] data_structures addr",-1,4,0); + vcdp->declBus(c+602,"cache_simX dmem_controller dcache genblk3[2] bank_structure data_structures each_way[0] data_structures we",-1,15,0); + vcdp->declBit(c+603,"cache_simX dmem_controller dcache genblk3[2] bank_structure data_structures each_way[0] data_structures evict",-1); + vcdp->declArray(c+604,"cache_simX dmem_controller dcache genblk3[2] bank_structure data_structures each_way[0] data_structures data_write",-1,127,0); + vcdp->declBus(c+221,"cache_simX dmem_controller dcache genblk3[2] bank_structure data_structures each_way[0] data_structures tag_write",-1,20,0); + vcdp->declBus(c+771,"cache_simX dmem_controller dcache genblk3[2] bank_structure data_structures each_way[0] data_structures tag_use",-1,20,0); + vcdp->declArray(c+772,"cache_simX dmem_controller dcache genblk3[2] bank_structure data_structures each_way[0] data_structures data_use",-1,127,0); + vcdp->declBit(c+776,"cache_simX dmem_controller dcache genblk3[2] bank_structure data_structures each_way[0] data_structures valid_use",-1); + vcdp->declBit(c+608,"cache_simX dmem_controller dcache genblk3[2] bank_structure data_structures each_way[0] data_structures dirty_use",-1); + vcdp->declBit(c+609,"cache_simX dmem_controller dcache genblk3[2] bank_structure data_structures each_way[0] data_structures currently_writing",-1); + vcdp->declBit(c+610,"cache_simX dmem_controller dcache genblk3[2] bank_structure data_structures each_way[0] data_structures update_dirty",-1); + vcdp->declBit(c+611,"cache_simX dmem_controller dcache genblk3[2] bank_structure data_structures each_way[0] data_structures dirt_new",-1); + vcdp->declArray(c+2181,"cache_simX dmem_controller dcache genblk3[2] bank_structure data_structures each_way[0] data_structures data(0)",-1,127,0); + vcdp->declArray(c+2185,"cache_simX dmem_controller dcache genblk3[2] bank_structure data_structures each_way[0] data_structures data(1)",-1,127,0); + vcdp->declArray(c+2189,"cache_simX dmem_controller dcache genblk3[2] bank_structure data_structures each_way[0] data_structures data(2)",-1,127,0); + vcdp->declArray(c+2193,"cache_simX dmem_controller dcache genblk3[2] bank_structure data_structures each_way[0] data_structures data(3)",-1,127,0); + vcdp->declArray(c+2197,"cache_simX dmem_controller dcache genblk3[2] bank_structure data_structures each_way[0] data_structures data(4)",-1,127,0); + vcdp->declArray(c+2201,"cache_simX dmem_controller dcache genblk3[2] bank_structure data_structures each_way[0] data_structures data(5)",-1,127,0); + vcdp->declArray(c+2205,"cache_simX dmem_controller dcache genblk3[2] bank_structure data_structures each_way[0] data_structures data(6)",-1,127,0); + vcdp->declArray(c+2209,"cache_simX dmem_controller dcache genblk3[2] bank_structure data_structures each_way[0] data_structures data(7)",-1,127,0); + vcdp->declArray(c+2213,"cache_simX dmem_controller dcache genblk3[2] bank_structure data_structures each_way[0] data_structures data(8)",-1,127,0); + vcdp->declArray(c+2217,"cache_simX dmem_controller dcache genblk3[2] bank_structure data_structures each_way[0] data_structures data(9)",-1,127,0); + vcdp->declArray(c+2221,"cache_simX dmem_controller dcache genblk3[2] bank_structure data_structures each_way[0] data_structures data(10)",-1,127,0); + vcdp->declArray(c+2225,"cache_simX dmem_controller dcache genblk3[2] bank_structure data_structures each_way[0] data_structures data(11)",-1,127,0); + vcdp->declArray(c+2229,"cache_simX dmem_controller dcache genblk3[2] bank_structure data_structures each_way[0] data_structures data(12)",-1,127,0); + vcdp->declArray(c+2233,"cache_simX dmem_controller dcache genblk3[2] bank_structure data_structures each_way[0] data_structures data(13)",-1,127,0); + vcdp->declArray(c+2237,"cache_simX dmem_controller dcache genblk3[2] bank_structure data_structures each_way[0] data_structures data(14)",-1,127,0); + vcdp->declArray(c+2241,"cache_simX dmem_controller dcache genblk3[2] bank_structure data_structures each_way[0] data_structures data(15)",-1,127,0); + vcdp->declArray(c+2245,"cache_simX dmem_controller dcache genblk3[2] bank_structure data_structures each_way[0] data_structures data(16)",-1,127,0); + vcdp->declArray(c+2249,"cache_simX dmem_controller dcache genblk3[2] bank_structure data_structures each_way[0] data_structures data(17)",-1,127,0); + vcdp->declArray(c+2253,"cache_simX dmem_controller dcache genblk3[2] bank_structure data_structures each_way[0] data_structures data(18)",-1,127,0); + vcdp->declArray(c+2257,"cache_simX dmem_controller dcache genblk3[2] bank_structure data_structures each_way[0] data_structures data(19)",-1,127,0); + vcdp->declArray(c+2261,"cache_simX dmem_controller dcache genblk3[2] bank_structure data_structures each_way[0] data_structures data(20)",-1,127,0); + vcdp->declArray(c+2265,"cache_simX dmem_controller dcache genblk3[2] bank_structure data_structures each_way[0] data_structures data(21)",-1,127,0); + vcdp->declArray(c+2269,"cache_simX dmem_controller dcache genblk3[2] bank_structure data_structures each_way[0] data_structures data(22)",-1,127,0); + vcdp->declArray(c+2273,"cache_simX dmem_controller dcache genblk3[2] bank_structure data_structures each_way[0] data_structures data(23)",-1,127,0); + vcdp->declArray(c+2277,"cache_simX dmem_controller dcache genblk3[2] bank_structure data_structures each_way[0] data_structures data(24)",-1,127,0); + vcdp->declArray(c+2281,"cache_simX dmem_controller dcache genblk3[2] bank_structure data_structures each_way[0] data_structures data(25)",-1,127,0); + vcdp->declArray(c+2285,"cache_simX dmem_controller dcache genblk3[2] bank_structure data_structures each_way[0] data_structures data(26)",-1,127,0); + vcdp->declArray(c+2289,"cache_simX dmem_controller dcache genblk3[2] bank_structure data_structures each_way[0] data_structures data(27)",-1,127,0); + vcdp->declArray(c+2293,"cache_simX dmem_controller dcache genblk3[2] bank_structure data_structures each_way[0] data_structures data(28)",-1,127,0); + vcdp->declArray(c+2297,"cache_simX dmem_controller dcache genblk3[2] bank_structure data_structures each_way[0] data_structures data(29)",-1,127,0); + vcdp->declArray(c+2301,"cache_simX dmem_controller dcache genblk3[2] bank_structure data_structures each_way[0] data_structures data(30)",-1,127,0); + vcdp->declArray(c+2305,"cache_simX dmem_controller dcache genblk3[2] bank_structure data_structures each_way[0] data_structures data(31)",-1,127,0); + {int i; for (i=0; i<32; i++) { + vcdp->declBus(c+2309+i*1,"cache_simX dmem_controller dcache genblk3[2] bank_structure data_structures each_way[0] data_structures tag",(i+0),20,0);}} + {int i; for (i=0; i<32; i++) { + vcdp->declBit(c+2341+i*1,"cache_simX dmem_controller dcache genblk3[2] bank_structure data_structures each_way[0] data_structures valid",(i+0));}} + {int i; for (i=0; i<32; i++) { + vcdp->declBit(c+2373+i*1,"cache_simX dmem_controller dcache genblk3[2] bank_structure data_structures each_way[0] data_structures dirty",(i+0));}} + vcdp->declBus(c+2405,"cache_simX dmem_controller dcache genblk3[2] bank_structure data_structures each_way[0] data_structures f",-1,31,0); + vcdp->declBus(c+2406,"cache_simX dmem_controller dcache genblk3[2] bank_structure data_structures each_way[0] data_structures ini_ind",-1,31,0); + vcdp->declBus(c+3143,"cache_simX dmem_controller dcache genblk3[2] bank_structure data_structures each_way[1] data_structures NUM_IND",-1,31,0); + vcdp->declBus(c+3102,"cache_simX dmem_controller dcache genblk3[2] bank_structure data_structures each_way[1] data_structures NUM_WORDS_PER_BLOCK",-1,31,0); + vcdp->declBus(c+3125,"cache_simX dmem_controller dcache genblk3[2] bank_structure data_structures each_way[1] data_structures TAG_SIZE_START",-1,31,0); + vcdp->declBus(c+3144,"cache_simX dmem_controller dcache genblk3[2] bank_structure data_structures each_way[1] data_structures TAG_SIZE_END",-1,31,0); + vcdp->declBus(c+3125,"cache_simX dmem_controller dcache genblk3[2] bank_structure data_structures each_way[1] data_structures IND_SIZE_START",-1,31,0); + vcdp->declBus(c+3102,"cache_simX dmem_controller dcache genblk3[2] bank_structure data_structures each_way[1] data_structures IND_SIZE_END",-1,31,0); + vcdp->declBit(c+3085,"cache_simX dmem_controller dcache genblk3[2] bank_structure data_structures each_way[1] data_structures clk",-1); + vcdp->declBit(c+3086,"cache_simX dmem_controller dcache genblk3[2] bank_structure data_structures each_way[1] data_structures rst",-1); + vcdp->declBus(c+220,"cache_simX dmem_controller dcache genblk3[2] bank_structure data_structures each_way[1] data_structures addr",-1,4,0); + vcdp->declBus(c+612,"cache_simX dmem_controller dcache genblk3[2] bank_structure data_structures each_way[1] data_structures we",-1,15,0); + vcdp->declBit(c+613,"cache_simX dmem_controller dcache genblk3[2] bank_structure data_structures each_way[1] data_structures evict",-1); + vcdp->declArray(c+614,"cache_simX dmem_controller dcache genblk3[2] bank_structure data_structures each_way[1] data_structures data_write",-1,127,0); + vcdp->declBus(c+221,"cache_simX dmem_controller dcache genblk3[2] bank_structure data_structures each_way[1] data_structures tag_write",-1,20,0); + vcdp->declBus(c+777,"cache_simX dmem_controller dcache genblk3[2] bank_structure data_structures each_way[1] data_structures tag_use",-1,20,0); + vcdp->declArray(c+778,"cache_simX dmem_controller dcache genblk3[2] bank_structure data_structures each_way[1] data_structures data_use",-1,127,0); + vcdp->declBit(c+782,"cache_simX dmem_controller dcache genblk3[2] bank_structure data_structures each_way[1] data_structures valid_use",-1); + vcdp->declBit(c+618,"cache_simX dmem_controller dcache genblk3[2] bank_structure data_structures each_way[1] data_structures dirty_use",-1); + vcdp->declBit(c+619,"cache_simX dmem_controller dcache genblk3[2] bank_structure data_structures each_way[1] data_structures currently_writing",-1); + vcdp->declBit(c+620,"cache_simX dmem_controller dcache genblk3[2] bank_structure data_structures each_way[1] data_structures update_dirty",-1); + vcdp->declBit(c+621,"cache_simX dmem_controller dcache genblk3[2] bank_structure data_structures each_way[1] data_structures dirt_new",-1); + vcdp->declArray(c+2407,"cache_simX dmem_controller dcache genblk3[2] bank_structure data_structures each_way[1] data_structures data(0)",-1,127,0); + vcdp->declArray(c+2411,"cache_simX dmem_controller dcache genblk3[2] bank_structure data_structures each_way[1] data_structures data(1)",-1,127,0); + vcdp->declArray(c+2415,"cache_simX dmem_controller dcache genblk3[2] bank_structure data_structures each_way[1] data_structures data(2)",-1,127,0); + vcdp->declArray(c+2419,"cache_simX dmem_controller dcache genblk3[2] bank_structure data_structures each_way[1] data_structures data(3)",-1,127,0); + vcdp->declArray(c+2423,"cache_simX dmem_controller dcache genblk3[2] bank_structure data_structures each_way[1] data_structures data(4)",-1,127,0); + vcdp->declArray(c+2427,"cache_simX dmem_controller dcache genblk3[2] bank_structure data_structures each_way[1] data_structures data(5)",-1,127,0); + vcdp->declArray(c+2431,"cache_simX dmem_controller dcache genblk3[2] bank_structure data_structures each_way[1] data_structures data(6)",-1,127,0); + vcdp->declArray(c+2435,"cache_simX dmem_controller dcache genblk3[2] bank_structure data_structures each_way[1] data_structures data(7)",-1,127,0); + vcdp->declArray(c+2439,"cache_simX dmem_controller dcache genblk3[2] bank_structure data_structures each_way[1] data_structures data(8)",-1,127,0); + vcdp->declArray(c+2443,"cache_simX dmem_controller dcache genblk3[2] bank_structure data_structures each_way[1] data_structures data(9)",-1,127,0); + vcdp->declArray(c+2447,"cache_simX dmem_controller dcache genblk3[2] bank_structure data_structures each_way[1] data_structures data(10)",-1,127,0); + vcdp->declArray(c+2451,"cache_simX dmem_controller dcache genblk3[2] bank_structure data_structures each_way[1] data_structures data(11)",-1,127,0); + vcdp->declArray(c+2455,"cache_simX dmem_controller dcache genblk3[2] bank_structure data_structures each_way[1] data_structures data(12)",-1,127,0); + vcdp->declArray(c+2459,"cache_simX dmem_controller dcache genblk3[2] bank_structure data_structures each_way[1] data_structures data(13)",-1,127,0); + vcdp->declArray(c+2463,"cache_simX dmem_controller dcache genblk3[2] bank_structure data_structures each_way[1] data_structures data(14)",-1,127,0); + vcdp->declArray(c+2467,"cache_simX dmem_controller dcache genblk3[2] bank_structure data_structures each_way[1] data_structures data(15)",-1,127,0); + vcdp->declArray(c+2471,"cache_simX dmem_controller dcache genblk3[2] bank_structure data_structures each_way[1] data_structures data(16)",-1,127,0); + vcdp->declArray(c+2475,"cache_simX dmem_controller dcache genblk3[2] bank_structure data_structures each_way[1] data_structures data(17)",-1,127,0); + vcdp->declArray(c+2479,"cache_simX dmem_controller dcache genblk3[2] bank_structure data_structures each_way[1] data_structures data(18)",-1,127,0); + vcdp->declArray(c+2483,"cache_simX dmem_controller dcache genblk3[2] bank_structure data_structures each_way[1] data_structures data(19)",-1,127,0); + vcdp->declArray(c+2487,"cache_simX dmem_controller dcache genblk3[2] bank_structure data_structures each_way[1] data_structures data(20)",-1,127,0); + vcdp->declArray(c+2491,"cache_simX dmem_controller dcache genblk3[2] bank_structure data_structures each_way[1] data_structures data(21)",-1,127,0); + vcdp->declArray(c+2495,"cache_simX dmem_controller dcache genblk3[2] bank_structure data_structures each_way[1] data_structures data(22)",-1,127,0); + vcdp->declArray(c+2499,"cache_simX dmem_controller dcache genblk3[2] bank_structure data_structures each_way[1] data_structures data(23)",-1,127,0); + vcdp->declArray(c+2503,"cache_simX dmem_controller dcache genblk3[2] bank_structure data_structures each_way[1] data_structures data(24)",-1,127,0); + vcdp->declArray(c+2507,"cache_simX dmem_controller dcache genblk3[2] bank_structure data_structures each_way[1] data_structures data(25)",-1,127,0); + vcdp->declArray(c+2511,"cache_simX dmem_controller dcache genblk3[2] bank_structure data_structures each_way[1] data_structures data(26)",-1,127,0); + vcdp->declArray(c+2515,"cache_simX dmem_controller dcache genblk3[2] bank_structure data_structures each_way[1] data_structures data(27)",-1,127,0); + vcdp->declArray(c+2519,"cache_simX dmem_controller dcache genblk3[2] bank_structure data_structures each_way[1] data_structures data(28)",-1,127,0); + vcdp->declArray(c+2523,"cache_simX dmem_controller dcache genblk3[2] bank_structure data_structures each_way[1] data_structures data(29)",-1,127,0); + vcdp->declArray(c+2527,"cache_simX dmem_controller dcache genblk3[2] bank_structure data_structures each_way[1] data_structures data(30)",-1,127,0); + vcdp->declArray(c+2531,"cache_simX dmem_controller dcache genblk3[2] bank_structure data_structures each_way[1] data_structures data(31)",-1,127,0); + {int i; for (i=0; i<32; i++) { + vcdp->declBus(c+2535+i*1,"cache_simX dmem_controller dcache genblk3[2] bank_structure data_structures each_way[1] data_structures tag",(i+0),20,0);}} + {int i; for (i=0; i<32; i++) { + vcdp->declBit(c+2567+i*1,"cache_simX dmem_controller dcache genblk3[2] bank_structure data_structures each_way[1] data_structures valid",(i+0));}} + {int i; for (i=0; i<32; i++) { + vcdp->declBit(c+2599+i*1,"cache_simX dmem_controller dcache genblk3[2] bank_structure data_structures each_way[1] data_structures dirty",(i+0));}} + vcdp->declBus(c+2631,"cache_simX dmem_controller dcache genblk3[2] bank_structure data_structures each_way[1] data_structures f",-1,31,0); + vcdp->declBus(c+2632,"cache_simX dmem_controller dcache genblk3[2] bank_structure data_structures each_way[1] data_structures ini_ind",-1,31,0); + vcdp->declBus(c+3141,"cache_simX dmem_controller dcache genblk3[3] bank_structure CACHE_SIZE",-1,31,0); + vcdp->declBus(c+3133,"cache_simX dmem_controller dcache genblk3[3] bank_structure CACHE_WAYS",-1,31,0); + vcdp->declBus(c+3142,"cache_simX dmem_controller dcache genblk3[3] bank_structure CACHE_BLOCK",-1,31,0); + vcdp->declBus(c+3102,"cache_simX dmem_controller dcache genblk3[3] bank_structure CACHE_BANKS",-1,31,0); + vcdp->declBus(c+3133,"cache_simX dmem_controller dcache genblk3[3] bank_structure LOG_NUM_BANKS",-1,31,0); + vcdp->declBus(c+3102,"cache_simX dmem_controller dcache genblk3[3] bank_structure NUM_REQ",-1,31,0); + vcdp->declBus(c+3133,"cache_simX dmem_controller dcache genblk3[3] bank_structure LOG_NUM_REQ",-1,31,0); + vcdp->declBus(c+3143,"cache_simX dmem_controller dcache genblk3[3] bank_structure NUM_IND",-1,31,0); + vcdp->declBus(c+3119,"cache_simX dmem_controller dcache genblk3[3] bank_structure CACHE_WAY_INDEX",-1,31,0); + vcdp->declBus(c+3102,"cache_simX dmem_controller dcache genblk3[3] bank_structure NUM_WORDS_PER_BLOCK",-1,31,0); + vcdp->declBus(c+3125,"cache_simX dmem_controller dcache genblk3[3] bank_structure OFFSET_SIZE_START",-1,31,0); + vcdp->declBus(c+3119,"cache_simX dmem_controller dcache genblk3[3] bank_structure OFFSET_SIZE_END",-1,31,0); + vcdp->declBus(c+3125,"cache_simX dmem_controller dcache genblk3[3] bank_structure TAG_SIZE_START",-1,31,0); + vcdp->declBus(c+3144,"cache_simX dmem_controller dcache genblk3[3] bank_structure TAG_SIZE_END",-1,31,0); + vcdp->declBus(c+3125,"cache_simX dmem_controller dcache genblk3[3] bank_structure IND_SIZE_START",-1,31,0); + vcdp->declBus(c+3102,"cache_simX dmem_controller dcache genblk3[3] bank_structure IND_SIZE_END",-1,31,0); + vcdp->declBus(c+3145,"cache_simX dmem_controller dcache genblk3[3] bank_structure ADDR_TAG_START",-1,31,0); + vcdp->declBus(c+3146,"cache_simX dmem_controller dcache genblk3[3] bank_structure ADDR_TAG_END",-1,31,0); + vcdp->declBus(c+3102,"cache_simX dmem_controller dcache genblk3[3] bank_structure ADDR_OFFSET_START",-1,31,0); + vcdp->declBus(c+3136,"cache_simX dmem_controller dcache genblk3[3] bank_structure ADDR_OFFSET_END",-1,31,0); + vcdp->declBus(c+3137,"cache_simX dmem_controller dcache genblk3[3] bank_structure ADDR_IND_START",-1,31,0); + vcdp->declBus(c+3147,"cache_simX dmem_controller dcache genblk3[3] bank_structure ADDR_IND_END",-1,31,0); + vcdp->declBus(c+3125,"cache_simX dmem_controller dcache genblk3[3] bank_structure CACHE_IDLE",-1,31,0); + vcdp->declBus(c+3119,"cache_simX dmem_controller dcache genblk3[3] bank_structure SEND_MEM_REQ",-1,31,0); + vcdp->declBus(c+3133,"cache_simX dmem_controller dcache genblk3[3] bank_structure RECIV_MEM_RSP",-1,31,0); + vcdp->declBus(c+3137,"cache_simX dmem_controller dcache genblk3[3] bank_structure BLOCK_NUM_BITS",-1,31,0); + vcdp->declBit(c+3086,"cache_simX dmem_controller dcache genblk3[3] bank_structure rst",-1); + vcdp->declBit(c+3085,"cache_simX dmem_controller dcache genblk3[3] bank_structure clk",-1); + vcdp->declBus(c+817,"cache_simX dmem_controller dcache genblk3[3] bank_structure state",-1,3,0); + vcdp->declBus(c+227,"cache_simX dmem_controller dcache genblk3[3] bank_structure actual_index",-1,4,0); + vcdp->declBus(c+228,"cache_simX dmem_controller dcache genblk3[3] bank_structure o_tag",-1,20,0); + vcdp->declBus(c+226,"cache_simX dmem_controller dcache genblk3[3] bank_structure block_offset",-1,1,0); + vcdp->declBus(c+622,"cache_simX dmem_controller dcache genblk3[3] bank_structure writedata",-1,31,0); + vcdp->declBit(c+230,"cache_simX dmem_controller dcache genblk3[3] bank_structure valid_in",-1); + vcdp->declBit(c+35,"cache_simX dmem_controller dcache genblk3[3] bank_structure read_or_write",-1); + vcdp->declArray(c+3171,"cache_simX dmem_controller dcache genblk3[3] bank_structure fetched_writedata",-1,127,0); + vcdp->declBus(c+36,"cache_simX dmem_controller dcache genblk3[3] bank_structure i_p_mem_read",-1,2,0); + vcdp->declBus(c+37,"cache_simX dmem_controller dcache genblk3[3] bank_structure i_p_mem_write",-1,2,0); + vcdp->declBus(c+225,"cache_simX dmem_controller dcache genblk3[3] bank_structure byte_select",-1,1,0); + vcdp->declBus(c+816,"cache_simX dmem_controller dcache genblk3[3] bank_structure evicted_way",-1,0,0); + vcdp->declBus(c+623,"cache_simX dmem_controller dcache genblk3[3] bank_structure readdata",-1,31,0); + vcdp->declBit(c+624,"cache_simX dmem_controller dcache genblk3[3] bank_structure hit",-1); + vcdp->declBit(c+625,"cache_simX dmem_controller dcache genblk3[3] bank_structure eviction_wb",-1); + vcdp->declBus(c+626,"cache_simX dmem_controller dcache genblk3[3] bank_structure eviction_addr",-1,31,0); + vcdp->declArray(c+627,"cache_simX dmem_controller dcache genblk3[3] bank_structure data_evicted",-1,127,0); + vcdp->declArray(c+627,"cache_simX dmem_controller dcache genblk3[3] bank_structure data_use",-1,127,0); + vcdp->declBus(c+631,"cache_simX dmem_controller dcache genblk3[3] bank_structure tag_use",-1,20,0); + vcdp->declBus(c+631,"cache_simX dmem_controller dcache genblk3[3] bank_structure eviction_tag",-1,20,0); + vcdp->declBit(c+632,"cache_simX dmem_controller dcache genblk3[3] bank_structure valid_use",-1); + vcdp->declBit(c+625,"cache_simX dmem_controller dcache genblk3[3] bank_structure dirty_use",-1); + vcdp->declBit(c+633,"cache_simX dmem_controller dcache genblk3[3] bank_structure access",-1); + vcdp->declBit(c+634,"cache_simX dmem_controller dcache genblk3[3] bank_structure write_from_mem",-1); + vcdp->declBit(c+635,"cache_simX dmem_controller dcache genblk3[3] bank_structure miss",-1); + vcdp->declBus(c+799,"cache_simX dmem_controller dcache genblk3[3] bank_structure way_to_update",-1,0,0); + vcdp->declBit(c+367,"cache_simX dmem_controller dcache genblk3[3] bank_structure lw",-1); + vcdp->declBit(c+368,"cache_simX dmem_controller dcache genblk3[3] bank_structure lb",-1); + vcdp->declBit(c+369,"cache_simX dmem_controller dcache genblk3[3] bank_structure lh",-1); + vcdp->declBit(c+370,"cache_simX dmem_controller dcache genblk3[3] bank_structure lhu",-1); + vcdp->declBit(c+371,"cache_simX dmem_controller dcache genblk3[3] bank_structure lbu",-1); + vcdp->declBit(c+372,"cache_simX dmem_controller dcache genblk3[3] bank_structure sw",-1); + vcdp->declBit(c+373,"cache_simX dmem_controller dcache genblk3[3] bank_structure sb",-1); + vcdp->declBit(c+374,"cache_simX dmem_controller dcache genblk3[3] bank_structure sh",-1); + vcdp->declBit(c+636,"cache_simX dmem_controller dcache genblk3[3] bank_structure b0",-1); + vcdp->declBit(c+637,"cache_simX dmem_controller dcache genblk3[3] bank_structure b1",-1); + vcdp->declBit(c+638,"cache_simX dmem_controller dcache genblk3[3] bank_structure b2",-1); + vcdp->declBit(c+639,"cache_simX dmem_controller dcache genblk3[3] bank_structure b3",-1); + vcdp->declBus(c+640,"cache_simX dmem_controller dcache genblk3[3] bank_structure data_unQual",-1,31,0); + vcdp->declBus(c+641,"cache_simX dmem_controller dcache genblk3[3] bank_structure lb_data",-1,31,0); + vcdp->declBus(c+642,"cache_simX dmem_controller dcache genblk3[3] bank_structure lh_data",-1,31,0); + vcdp->declBus(c+643,"cache_simX dmem_controller dcache genblk3[3] bank_structure lbu_data",-1,31,0); + vcdp->declBus(c+644,"cache_simX dmem_controller dcache genblk3[3] bank_structure lhu_data",-1,31,0); + vcdp->declBus(c+640,"cache_simX dmem_controller dcache genblk3[3] bank_structure lw_data",-1,31,0); + vcdp->declBus(c+622,"cache_simX dmem_controller dcache genblk3[3] bank_structure sw_data",-1,31,0); + vcdp->declBus(c+645,"cache_simX dmem_controller dcache genblk3[3] bank_structure sb_data",-1,31,0); + vcdp->declBus(c+646,"cache_simX dmem_controller dcache genblk3[3] bank_structure sh_data",-1,31,0); + vcdp->declBus(c+647,"cache_simX dmem_controller dcache genblk3[3] bank_structure use_write_data",-1,31,0); + vcdp->declBus(c+648,"cache_simX dmem_controller dcache genblk3[3] bank_structure data_Qual",-1,31,0); + vcdp->declBus(c+649,"cache_simX dmem_controller dcache genblk3[3] bank_structure sb_mask",-1,3,0); + vcdp->declBus(c+650,"cache_simX dmem_controller dcache genblk3[3] bank_structure sh_mask",-1,3,0); + vcdp->declBus(c+651,"cache_simX dmem_controller dcache genblk3[3] bank_structure we",-1,15,0); + vcdp->declArray(c+652,"cache_simX dmem_controller dcache genblk3[3] bank_structure data_write",-1,127,0); + vcdp->declBit(c+656,"cache_simX dmem_controller dcache genblk3[3] bank_structure genblk1[0] normal_write",-1); + vcdp->declBit(c+657,"cache_simX dmem_controller dcache genblk3[3] bank_structure genblk1[1] normal_write",-1); + vcdp->declBit(c+658,"cache_simX dmem_controller dcache genblk3[3] bank_structure genblk1[2] normal_write",-1); + vcdp->declBit(c+659,"cache_simX dmem_controller dcache genblk3[3] bank_structure genblk1[3] normal_write",-1); + vcdp->declBus(c+3133,"cache_simX dmem_controller dcache genblk3[3] bank_structure data_structures CACHE_WAYS",-1,31,0); + vcdp->declBus(c+3143,"cache_simX dmem_controller dcache genblk3[3] bank_structure data_structures NUM_IND",-1,31,0); + vcdp->declBus(c+3119,"cache_simX dmem_controller dcache genblk3[3] bank_structure data_structures CACHE_WAY_INDEX",-1,31,0); + vcdp->declBus(c+3102,"cache_simX dmem_controller dcache genblk3[3] bank_structure data_structures NUM_WORDS_PER_BLOCK",-1,31,0); + vcdp->declBus(c+3125,"cache_simX dmem_controller dcache genblk3[3] bank_structure data_structures TAG_SIZE_START",-1,31,0); + vcdp->declBus(c+3144,"cache_simX dmem_controller dcache genblk3[3] bank_structure data_structures TAG_SIZE_END",-1,31,0); + vcdp->declBus(c+3125,"cache_simX dmem_controller dcache genblk3[3] bank_structure data_structures IND_SIZE_START",-1,31,0); + vcdp->declBus(c+3102,"cache_simX dmem_controller dcache genblk3[3] bank_structure data_structures IND_SIZE_END",-1,31,0); + vcdp->declBit(c+3085,"cache_simX dmem_controller dcache genblk3[3] bank_structure data_structures clk",-1); + vcdp->declBit(c+3086,"cache_simX dmem_controller dcache genblk3[3] bank_structure data_structures rst",-1); + vcdp->declBit(c+230,"cache_simX dmem_controller dcache genblk3[3] bank_structure data_structures valid_in",-1); + vcdp->declBus(c+817,"cache_simX dmem_controller dcache genblk3[3] bank_structure data_structures state",-1,3,0); + vcdp->declBus(c+227,"cache_simX dmem_controller dcache genblk3[3] bank_structure data_structures addr",-1,4,0); + vcdp->declBus(c+651,"cache_simX dmem_controller dcache genblk3[3] bank_structure data_structures we",-1,15,0); + vcdp->declBit(c+634,"cache_simX dmem_controller dcache genblk3[3] bank_structure data_structures evict",-1); + vcdp->declBus(c+799,"cache_simX dmem_controller dcache genblk3[3] bank_structure data_structures way_to_update",-1,0,0); + vcdp->declArray(c+652,"cache_simX dmem_controller dcache genblk3[3] bank_structure data_structures data_write",-1,127,0); + vcdp->declBus(c+228,"cache_simX dmem_controller dcache genblk3[3] bank_structure data_structures tag_write",-1,20,0); + vcdp->declBus(c+631,"cache_simX dmem_controller dcache genblk3[3] bank_structure data_structures tag_use",-1,20,0); + vcdp->declArray(c+627,"cache_simX dmem_controller dcache genblk3[3] bank_structure data_structures data_use",-1,127,0); + vcdp->declBit(c+632,"cache_simX dmem_controller dcache genblk3[3] bank_structure data_structures valid_use",-1); + vcdp->declBit(c+625,"cache_simX dmem_controller dcache genblk3[3] bank_structure data_structures dirty_use",-1); + vcdp->declQuad(c+660,"cache_simX dmem_controller dcache genblk3[3] bank_structure data_structures tag_use_per_way",-1,41,0); + vcdp->declArray(c+662,"cache_simX dmem_controller dcache genblk3[3] bank_structure data_structures data_use_per_way",-1,255,0); + vcdp->declBus(c+670,"cache_simX dmem_controller dcache genblk3[3] bank_structure data_structures valid_use_per_way",-1,1,0); + vcdp->declBus(c+671,"cache_simX dmem_controller dcache genblk3[3] bank_structure data_structures dirty_use_per_way",-1,1,0); + vcdp->declBus(c+672,"cache_simX dmem_controller dcache genblk3[3] bank_structure data_structures hit_per_way",-1,1,0); + vcdp->declBus(c+673,"cache_simX dmem_controller dcache genblk3[3] bank_structure data_structures we_per_way",-1,31,0); + vcdp->declArray(c+674,"cache_simX dmem_controller dcache genblk3[3] bank_structure data_structures data_write_per_way",-1,255,0); + vcdp->declBus(c+682,"cache_simX dmem_controller dcache genblk3[3] bank_structure data_structures write_from_mem_per_way",-1,1,0); + vcdp->declBit(c+683,"cache_simX dmem_controller dcache genblk3[3] bank_structure data_structures invalid_found",-1); + vcdp->declBus(c+684,"cache_simX dmem_controller dcache genblk3[3] bank_structure data_structures way_index",-1,0,0); + vcdp->declBus(c+685,"cache_simX dmem_controller dcache genblk3[3] bank_structure data_structures invalid_index",-1,0,0); + vcdp->declBus(c+3125,"cache_simX dmem_controller dcache genblk3[3] bank_structure data_structures CACHE_IDLE",-1,31,0); + vcdp->declBus(c+3119,"cache_simX dmem_controller dcache genblk3[3] bank_structure data_structures SEND_MEM_REQ",-1,31,0); + vcdp->declBus(c+3133,"cache_simX dmem_controller dcache genblk3[3] bank_structure data_structures RECIV_MEM_RSP",-1,31,0); + vcdp->declBus(c+686,"cache_simX dmem_controller dcache genblk3[3] bank_structure data_structures way_use_Qual",-1,0,0); + vcdp->declBus(c+3133,"cache_simX dmem_controller dcache genblk3[3] bank_structure data_structures genblk1 valid_index N",-1,31,0); + vcdp->declBus(c+687,"cache_simX dmem_controller dcache genblk3[3] bank_structure data_structures genblk1 valid_index valids",-1,1,0); + vcdp->declBus(c+685,"cache_simX dmem_controller dcache genblk3[3] bank_structure data_structures genblk1 valid_index index",-1,0,0); + vcdp->declBit(c+683,"cache_simX dmem_controller dcache genblk3[3] bank_structure data_structures genblk1 valid_index found",-1); + vcdp->declBus(c+3140,"cache_simX dmem_controller dcache genblk3[3] bank_structure data_structures genblk1 valid_index i",-1,31,0); + vcdp->declBus(c+3133,"cache_simX dmem_controller dcache genblk3[3] bank_structure data_structures genblk1 way_indexing N",-1,31,0); + vcdp->declBus(c+672,"cache_simX dmem_controller dcache genblk3[3] bank_structure data_structures genblk1 way_indexing valids",-1,1,0); + vcdp->declBus(c+684,"cache_simX dmem_controller dcache genblk3[3] bank_structure data_structures genblk1 way_indexing index",-1,0,0); + vcdp->declBit(c+688,"cache_simX dmem_controller dcache genblk3[3] bank_structure data_structures genblk1 way_indexing found",-1); + vcdp->declBus(c+3140,"cache_simX dmem_controller dcache genblk3[3] bank_structure data_structures genblk1 way_indexing i",-1,31,0); + vcdp->declBus(c+3143,"cache_simX dmem_controller dcache genblk3[3] bank_structure data_structures each_way[0] data_structures NUM_IND",-1,31,0); + vcdp->declBus(c+3102,"cache_simX dmem_controller dcache genblk3[3] bank_structure data_structures each_way[0] data_structures NUM_WORDS_PER_BLOCK",-1,31,0); + vcdp->declBus(c+3125,"cache_simX dmem_controller dcache genblk3[3] bank_structure data_structures each_way[0] data_structures TAG_SIZE_START",-1,31,0); + vcdp->declBus(c+3144,"cache_simX dmem_controller dcache genblk3[3] bank_structure data_structures each_way[0] data_structures TAG_SIZE_END",-1,31,0); + vcdp->declBus(c+3125,"cache_simX dmem_controller dcache genblk3[3] bank_structure data_structures each_way[0] data_structures IND_SIZE_START",-1,31,0); + vcdp->declBus(c+3102,"cache_simX dmem_controller dcache genblk3[3] bank_structure data_structures each_way[0] data_structures IND_SIZE_END",-1,31,0); + vcdp->declBit(c+3085,"cache_simX dmem_controller dcache genblk3[3] bank_structure data_structures each_way[0] data_structures clk",-1); + vcdp->declBit(c+3086,"cache_simX dmem_controller dcache genblk3[3] bank_structure data_structures each_way[0] data_structures rst",-1); + vcdp->declBus(c+227,"cache_simX dmem_controller dcache genblk3[3] bank_structure data_structures each_way[0] data_structures addr",-1,4,0); + vcdp->declBus(c+689,"cache_simX dmem_controller dcache genblk3[3] bank_structure data_structures each_way[0] data_structures we",-1,15,0); + vcdp->declBit(c+690,"cache_simX dmem_controller dcache genblk3[3] bank_structure data_structures each_way[0] data_structures evict",-1); + vcdp->declArray(c+691,"cache_simX dmem_controller dcache genblk3[3] bank_structure data_structures each_way[0] data_structures data_write",-1,127,0); + vcdp->declBus(c+228,"cache_simX dmem_controller dcache genblk3[3] bank_structure data_structures each_way[0] data_structures tag_write",-1,20,0); + vcdp->declBus(c+783,"cache_simX dmem_controller dcache genblk3[3] bank_structure data_structures each_way[0] data_structures tag_use",-1,20,0); + vcdp->declArray(c+784,"cache_simX dmem_controller dcache genblk3[3] bank_structure data_structures each_way[0] data_structures data_use",-1,127,0); + vcdp->declBit(c+788,"cache_simX dmem_controller dcache genblk3[3] bank_structure data_structures each_way[0] data_structures valid_use",-1); + vcdp->declBit(c+695,"cache_simX dmem_controller dcache genblk3[3] bank_structure data_structures each_way[0] data_structures dirty_use",-1); + vcdp->declBit(c+696,"cache_simX dmem_controller dcache genblk3[3] bank_structure data_structures each_way[0] data_structures currently_writing",-1); + vcdp->declBit(c+697,"cache_simX dmem_controller dcache genblk3[3] bank_structure data_structures each_way[0] data_structures update_dirty",-1); + vcdp->declBit(c+698,"cache_simX dmem_controller dcache genblk3[3] bank_structure data_structures each_way[0] data_structures dirt_new",-1); + vcdp->declArray(c+2633,"cache_simX dmem_controller dcache genblk3[3] bank_structure data_structures each_way[0] data_structures data(0)",-1,127,0); + vcdp->declArray(c+2637,"cache_simX dmem_controller dcache genblk3[3] bank_structure data_structures each_way[0] data_structures data(1)",-1,127,0); + vcdp->declArray(c+2641,"cache_simX dmem_controller dcache genblk3[3] bank_structure data_structures each_way[0] data_structures data(2)",-1,127,0); + vcdp->declArray(c+2645,"cache_simX dmem_controller dcache genblk3[3] bank_structure data_structures each_way[0] data_structures data(3)",-1,127,0); + vcdp->declArray(c+2649,"cache_simX dmem_controller dcache genblk3[3] bank_structure data_structures each_way[0] data_structures data(4)",-1,127,0); + vcdp->declArray(c+2653,"cache_simX dmem_controller dcache genblk3[3] bank_structure data_structures each_way[0] data_structures data(5)",-1,127,0); + vcdp->declArray(c+2657,"cache_simX dmem_controller dcache genblk3[3] bank_structure data_structures each_way[0] data_structures data(6)",-1,127,0); + vcdp->declArray(c+2661,"cache_simX dmem_controller dcache genblk3[3] bank_structure data_structures each_way[0] data_structures data(7)",-1,127,0); + vcdp->declArray(c+2665,"cache_simX dmem_controller dcache genblk3[3] bank_structure data_structures each_way[0] data_structures data(8)",-1,127,0); + vcdp->declArray(c+2669,"cache_simX dmem_controller dcache genblk3[3] bank_structure data_structures each_way[0] data_structures data(9)",-1,127,0); + vcdp->declArray(c+2673,"cache_simX dmem_controller dcache genblk3[3] bank_structure data_structures each_way[0] data_structures data(10)",-1,127,0); + vcdp->declArray(c+2677,"cache_simX dmem_controller dcache genblk3[3] bank_structure data_structures each_way[0] data_structures data(11)",-1,127,0); + vcdp->declArray(c+2681,"cache_simX dmem_controller dcache genblk3[3] bank_structure data_structures each_way[0] data_structures data(12)",-1,127,0); + vcdp->declArray(c+2685,"cache_simX dmem_controller dcache genblk3[3] bank_structure data_structures each_way[0] data_structures data(13)",-1,127,0); + vcdp->declArray(c+2689,"cache_simX dmem_controller dcache genblk3[3] bank_structure data_structures each_way[0] data_structures data(14)",-1,127,0); + vcdp->declArray(c+2693,"cache_simX dmem_controller dcache genblk3[3] bank_structure data_structures each_way[0] data_structures data(15)",-1,127,0); + vcdp->declArray(c+2697,"cache_simX dmem_controller dcache genblk3[3] bank_structure data_structures each_way[0] data_structures data(16)",-1,127,0); + vcdp->declArray(c+2701,"cache_simX dmem_controller dcache genblk3[3] bank_structure data_structures each_way[0] data_structures data(17)",-1,127,0); + vcdp->declArray(c+2705,"cache_simX dmem_controller dcache genblk3[3] bank_structure data_structures each_way[0] data_structures data(18)",-1,127,0); + vcdp->declArray(c+2709,"cache_simX dmem_controller dcache genblk3[3] bank_structure data_structures each_way[0] data_structures data(19)",-1,127,0); + vcdp->declArray(c+2713,"cache_simX dmem_controller dcache genblk3[3] bank_structure data_structures each_way[0] data_structures data(20)",-1,127,0); + vcdp->declArray(c+2717,"cache_simX dmem_controller dcache genblk3[3] bank_structure data_structures each_way[0] data_structures data(21)",-1,127,0); + vcdp->declArray(c+2721,"cache_simX dmem_controller dcache genblk3[3] bank_structure data_structures each_way[0] data_structures data(22)",-1,127,0); + vcdp->declArray(c+2725,"cache_simX dmem_controller dcache genblk3[3] bank_structure data_structures each_way[0] data_structures data(23)",-1,127,0); + vcdp->declArray(c+2729,"cache_simX dmem_controller dcache genblk3[3] bank_structure data_structures each_way[0] data_structures data(24)",-1,127,0); + vcdp->declArray(c+2733,"cache_simX dmem_controller dcache genblk3[3] bank_structure data_structures each_way[0] data_structures data(25)",-1,127,0); + vcdp->declArray(c+2737,"cache_simX dmem_controller dcache genblk3[3] bank_structure data_structures each_way[0] data_structures data(26)",-1,127,0); + vcdp->declArray(c+2741,"cache_simX dmem_controller dcache genblk3[3] bank_structure data_structures each_way[0] data_structures data(27)",-1,127,0); + vcdp->declArray(c+2745,"cache_simX dmem_controller dcache genblk3[3] bank_structure data_structures each_way[0] data_structures data(28)",-1,127,0); + vcdp->declArray(c+2749,"cache_simX dmem_controller dcache genblk3[3] bank_structure data_structures each_way[0] data_structures data(29)",-1,127,0); + vcdp->declArray(c+2753,"cache_simX dmem_controller dcache genblk3[3] bank_structure data_structures each_way[0] data_structures data(30)",-1,127,0); + vcdp->declArray(c+2757,"cache_simX dmem_controller dcache genblk3[3] bank_structure data_structures each_way[0] data_structures data(31)",-1,127,0); + {int i; for (i=0; i<32; i++) { + vcdp->declBus(c+2761+i*1,"cache_simX dmem_controller dcache genblk3[3] bank_structure data_structures each_way[0] data_structures tag",(i+0),20,0);}} + {int i; for (i=0; i<32; i++) { + vcdp->declBit(c+2793+i*1,"cache_simX dmem_controller dcache genblk3[3] bank_structure data_structures each_way[0] data_structures valid",(i+0));}} + {int i; for (i=0; i<32; i++) { + vcdp->declBit(c+2825+i*1,"cache_simX dmem_controller dcache genblk3[3] bank_structure data_structures each_way[0] data_structures dirty",(i+0));}} + vcdp->declBus(c+2857,"cache_simX dmem_controller dcache genblk3[3] bank_structure data_structures each_way[0] data_structures f",-1,31,0); + vcdp->declBus(c+2858,"cache_simX dmem_controller dcache genblk3[3] bank_structure data_structures each_way[0] data_structures ini_ind",-1,31,0); + vcdp->declBus(c+3143,"cache_simX dmem_controller dcache genblk3[3] bank_structure data_structures each_way[1] data_structures NUM_IND",-1,31,0); + vcdp->declBus(c+3102,"cache_simX dmem_controller dcache genblk3[3] bank_structure data_structures each_way[1] data_structures NUM_WORDS_PER_BLOCK",-1,31,0); + vcdp->declBus(c+3125,"cache_simX dmem_controller dcache genblk3[3] bank_structure data_structures each_way[1] data_structures TAG_SIZE_START",-1,31,0); + vcdp->declBus(c+3144,"cache_simX dmem_controller dcache genblk3[3] bank_structure data_structures each_way[1] data_structures TAG_SIZE_END",-1,31,0); + vcdp->declBus(c+3125,"cache_simX dmem_controller dcache genblk3[3] bank_structure data_structures each_way[1] data_structures IND_SIZE_START",-1,31,0); + vcdp->declBus(c+3102,"cache_simX dmem_controller dcache genblk3[3] bank_structure data_structures each_way[1] data_structures IND_SIZE_END",-1,31,0); + vcdp->declBit(c+3085,"cache_simX dmem_controller dcache genblk3[3] bank_structure data_structures each_way[1] data_structures clk",-1); + vcdp->declBit(c+3086,"cache_simX dmem_controller dcache genblk3[3] bank_structure data_structures each_way[1] data_structures rst",-1); + vcdp->declBus(c+227,"cache_simX dmem_controller dcache genblk3[3] bank_structure data_structures each_way[1] data_structures addr",-1,4,0); + vcdp->declBus(c+699,"cache_simX dmem_controller dcache genblk3[3] bank_structure data_structures each_way[1] data_structures we",-1,15,0); + vcdp->declBit(c+700,"cache_simX dmem_controller dcache genblk3[3] bank_structure data_structures each_way[1] data_structures evict",-1); + vcdp->declArray(c+701,"cache_simX dmem_controller dcache genblk3[3] bank_structure data_structures each_way[1] data_structures data_write",-1,127,0); + vcdp->declBus(c+228,"cache_simX dmem_controller dcache genblk3[3] bank_structure data_structures each_way[1] data_structures tag_write",-1,20,0); + vcdp->declBus(c+789,"cache_simX dmem_controller dcache genblk3[3] bank_structure data_structures each_way[1] data_structures tag_use",-1,20,0); + vcdp->declArray(c+790,"cache_simX dmem_controller dcache genblk3[3] bank_structure data_structures each_way[1] data_structures data_use",-1,127,0); + vcdp->declBit(c+794,"cache_simX dmem_controller dcache genblk3[3] bank_structure data_structures each_way[1] data_structures valid_use",-1); + vcdp->declBit(c+705,"cache_simX dmem_controller dcache genblk3[3] bank_structure data_structures each_way[1] data_structures dirty_use",-1); + vcdp->declBit(c+706,"cache_simX dmem_controller dcache genblk3[3] bank_structure data_structures each_way[1] data_structures currently_writing",-1); + vcdp->declBit(c+707,"cache_simX dmem_controller dcache genblk3[3] bank_structure data_structures each_way[1] data_structures update_dirty",-1); + vcdp->declBit(c+708,"cache_simX dmem_controller dcache genblk3[3] bank_structure data_structures each_way[1] data_structures dirt_new",-1); + vcdp->declArray(c+2859,"cache_simX dmem_controller dcache genblk3[3] bank_structure data_structures each_way[1] data_structures data(0)",-1,127,0); + vcdp->declArray(c+2863,"cache_simX dmem_controller dcache genblk3[3] bank_structure data_structures each_way[1] data_structures data(1)",-1,127,0); + vcdp->declArray(c+2867,"cache_simX dmem_controller dcache genblk3[3] bank_structure data_structures each_way[1] data_structures data(2)",-1,127,0); + vcdp->declArray(c+2871,"cache_simX dmem_controller dcache genblk3[3] bank_structure data_structures each_way[1] data_structures data(3)",-1,127,0); + vcdp->declArray(c+2875,"cache_simX dmem_controller dcache genblk3[3] bank_structure data_structures each_way[1] data_structures data(4)",-1,127,0); + vcdp->declArray(c+2879,"cache_simX dmem_controller dcache genblk3[3] bank_structure data_structures each_way[1] data_structures data(5)",-1,127,0); + vcdp->declArray(c+2883,"cache_simX dmem_controller dcache genblk3[3] bank_structure data_structures each_way[1] data_structures data(6)",-1,127,0); + vcdp->declArray(c+2887,"cache_simX dmem_controller dcache genblk3[3] bank_structure data_structures each_way[1] data_structures data(7)",-1,127,0); + vcdp->declArray(c+2891,"cache_simX dmem_controller dcache genblk3[3] bank_structure data_structures each_way[1] data_structures data(8)",-1,127,0); + vcdp->declArray(c+2895,"cache_simX dmem_controller dcache genblk3[3] bank_structure data_structures each_way[1] data_structures data(9)",-1,127,0); + vcdp->declArray(c+2899,"cache_simX dmem_controller dcache genblk3[3] bank_structure data_structures each_way[1] data_structures data(10)",-1,127,0); + vcdp->declArray(c+2903,"cache_simX dmem_controller dcache genblk3[3] bank_structure data_structures each_way[1] data_structures data(11)",-1,127,0); + vcdp->declArray(c+2907,"cache_simX dmem_controller dcache genblk3[3] bank_structure data_structures each_way[1] data_structures data(12)",-1,127,0); + vcdp->declArray(c+2911,"cache_simX dmem_controller dcache genblk3[3] bank_structure data_structures each_way[1] data_structures data(13)",-1,127,0); + vcdp->declArray(c+2915,"cache_simX dmem_controller dcache genblk3[3] bank_structure data_structures each_way[1] data_structures data(14)",-1,127,0); + vcdp->declArray(c+2919,"cache_simX dmem_controller dcache genblk3[3] bank_structure data_structures each_way[1] data_structures data(15)",-1,127,0); + vcdp->declArray(c+2923,"cache_simX dmem_controller dcache genblk3[3] bank_structure data_structures each_way[1] data_structures data(16)",-1,127,0); + vcdp->declArray(c+2927,"cache_simX dmem_controller dcache genblk3[3] bank_structure data_structures each_way[1] data_structures data(17)",-1,127,0); + vcdp->declArray(c+2931,"cache_simX dmem_controller dcache genblk3[3] bank_structure data_structures each_way[1] data_structures data(18)",-1,127,0); + vcdp->declArray(c+2935,"cache_simX dmem_controller dcache genblk3[3] bank_structure data_structures each_way[1] data_structures data(19)",-1,127,0); + vcdp->declArray(c+2939,"cache_simX dmem_controller dcache genblk3[3] bank_structure data_structures each_way[1] data_structures data(20)",-1,127,0); + vcdp->declArray(c+2943,"cache_simX dmem_controller dcache genblk3[3] bank_structure data_structures each_way[1] data_structures data(21)",-1,127,0); + vcdp->declArray(c+2947,"cache_simX dmem_controller dcache genblk3[3] bank_structure data_structures each_way[1] data_structures data(22)",-1,127,0); + vcdp->declArray(c+2951,"cache_simX dmem_controller dcache genblk3[3] bank_structure data_structures each_way[1] data_structures data(23)",-1,127,0); + vcdp->declArray(c+2955,"cache_simX dmem_controller dcache genblk3[3] bank_structure data_structures each_way[1] data_structures data(24)",-1,127,0); + vcdp->declArray(c+2959,"cache_simX dmem_controller dcache genblk3[3] bank_structure data_structures each_way[1] data_structures data(25)",-1,127,0); + vcdp->declArray(c+2963,"cache_simX dmem_controller dcache genblk3[3] bank_structure data_structures each_way[1] data_structures data(26)",-1,127,0); + vcdp->declArray(c+2967,"cache_simX dmem_controller dcache genblk3[3] bank_structure data_structures each_way[1] data_structures data(27)",-1,127,0); + vcdp->declArray(c+2971,"cache_simX dmem_controller dcache genblk3[3] bank_structure data_structures each_way[1] data_structures data(28)",-1,127,0); + vcdp->declArray(c+2975,"cache_simX dmem_controller dcache genblk3[3] bank_structure data_structures each_way[1] data_structures data(29)",-1,127,0); + vcdp->declArray(c+2979,"cache_simX dmem_controller dcache genblk3[3] bank_structure data_structures each_way[1] data_structures data(30)",-1,127,0); + vcdp->declArray(c+2983,"cache_simX dmem_controller dcache genblk3[3] bank_structure data_structures each_way[1] data_structures data(31)",-1,127,0); + {int i; for (i=0; i<32; i++) { + vcdp->declBus(c+2987+i*1,"cache_simX dmem_controller dcache genblk3[3] bank_structure data_structures each_way[1] data_structures tag",(i+0),20,0);}} + {int i; for (i=0; i<32; i++) { + vcdp->declBit(c+3019+i*1,"cache_simX dmem_controller dcache genblk3[3] bank_structure data_structures each_way[1] data_structures valid",(i+0));}} + {int i; for (i=0; i<32; i++) { + vcdp->declBit(c+3051+i*1,"cache_simX dmem_controller dcache genblk3[3] bank_structure data_structures each_way[1] data_structures dirty",(i+0));}} + vcdp->declBus(c+3083,"cache_simX dmem_controller dcache genblk3[3] bank_structure data_structures each_way[1] data_structures f",-1,31,0); + vcdp->declBus(c+3084,"cache_simX dmem_controller dcache genblk3[3] bank_structure data_structures each_way[1] data_structures ini_ind",-1,31,0); + } +} + +void Vcache_simX::traceFullThis__1(Vcache_simX__Syms* __restrict vlSymsp, VerilatedVcd* vcdp, uint32_t code) { + Vcache_simX* __restrict vlTOPp VL_ATTR_UNUSED = vlSymsp->TOPp; + int c = code; + if (0 && vcdp && c) {} // Prevent unused + // Variables + WData/*7:0*/ __Vtemp211[4]; + WData/*7:0*/ __Vtemp212[4]; + WData/*7:0*/ __Vtemp213[4]; + WData/*7:0*/ __Vtemp214[4]; + WData/*7:0*/ __Vtemp215[4]; + WData/*7:0*/ __Vtemp216[4]; + WData/*7:0*/ __Vtemp217[4]; + WData/*7:0*/ __Vtemp218[4]; + WData/*7:0*/ __Vtemp219[4]; + WData/*7:0*/ __Vtemp220[4]; + WData/*7:0*/ __Vtemp221[4]; + WData/*7:0*/ __Vtemp222[4]; + WData/*7:0*/ __Vtemp223[4]; + WData/*7:0*/ __Vtemp224[4]; + WData/*7:0*/ __Vtemp225[4]; + WData/*7:0*/ __Vtemp226[4]; + WData/*7:0*/ __Vtemp227[4]; + WData/*7:0*/ __Vtemp228[4]; + WData/*7:0*/ __Vtemp229[4]; + WData/*7:0*/ __Vtemp230[4]; + WData/*7:0*/ __Vtemp231[4]; + WData/*7:0*/ __Vtemp232[4]; + WData/*7:0*/ __Vtemp233[4]; + WData/*7:0*/ __Vtemp234[4]; + WData/*7:0*/ __Vtemp235[4]; + WData/*7:0*/ __Vtemp236[4]; + WData/*7:0*/ __Vtemp237[4]; + WData/*7:0*/ __Vtemp238[4]; + WData/*7:0*/ __Vtemp239[4]; + WData/*7:0*/ __Vtemp240[4]; + WData/*7:0*/ __Vtemp241[4]; + WData/*7:0*/ __Vtemp242[4]; + WData/*7:0*/ __Vtemp243[4]; + WData/*7:0*/ __Vtemp244[4]; + WData/*7:0*/ __Vtemp245[4]; + WData/*7:0*/ __Vtemp246[4]; + WData/*7:0*/ __Vtemp247[4]; + WData/*7:0*/ __Vtemp248[4]; + WData/*7:0*/ __Vtemp249[4]; + WData/*7:0*/ __Vtemp250[4]; + WData/*7:0*/ __Vtemp251[4]; + WData/*7:0*/ __Vtemp252[4]; + WData/*7:0*/ __Vtemp253[4]; + WData/*7:0*/ __Vtemp254[4]; + WData/*7:0*/ __Vtemp255[4]; + WData/*7:0*/ __Vtemp256[4]; + WData/*7:0*/ __Vtemp257[4]; + WData/*7:0*/ __Vtemp258[4]; + WData/*7:0*/ __Vtemp259[4]; + WData/*7:0*/ __Vtemp260[4]; + WData/*7:0*/ __Vtemp261[4]; + WData/*7:0*/ __Vtemp262[4]; + WData/*7:0*/ __Vtemp263[4]; + WData/*7:0*/ __Vtemp264[4]; + WData/*7:0*/ __Vtemp265[4]; + WData/*7:0*/ __Vtemp266[4]; + WData/*7:0*/ __Vtemp267[4]; + WData/*7:0*/ __Vtemp268[4]; + WData/*7:0*/ __Vtemp269[4]; + WData/*7:0*/ __Vtemp270[4]; + WData/*7:0*/ __Vtemp271[4]; + WData/*7:0*/ __Vtemp272[4]; + WData/*7:0*/ __Vtemp273[4]; + WData/*7:0*/ __Vtemp274[4]; + WData/*7:0*/ __Vtemp275[4]; + WData/*7:0*/ __Vtemp276[4]; + WData/*7:0*/ __Vtemp277[4]; + WData/*7:0*/ __Vtemp278[4]; + WData/*7:0*/ __Vtemp279[4]; + WData/*7:0*/ __Vtemp280[4]; + WData/*7:0*/ __Vtemp281[4]; + WData/*7:0*/ __Vtemp282[4]; + WData/*7:0*/ __Vtemp283[4]; + WData/*7:0*/ __Vtemp284[4]; + WData/*7:0*/ __Vtemp285[4]; + WData/*7:0*/ __Vtemp286[4]; + WData/*7:0*/ __Vtemp287[4]; + WData/*7:0*/ __Vtemp288[4]; + WData/*7:0*/ __Vtemp289[4]; + WData/*7:0*/ __Vtemp290[4]; + WData/*7:0*/ __Vtemp291[4]; + WData/*7:0*/ __Vtemp292[4]; + WData/*7:0*/ __Vtemp293[4]; + WData/*7:0*/ __Vtemp294[4]; + WData/*7:0*/ __Vtemp295[4]; + WData/*7:0*/ __Vtemp296[4]; + WData/*7:0*/ __Vtemp297[4]; + WData/*7:0*/ __Vtemp298[4]; + WData/*7:0*/ __Vtemp299[4]; + WData/*7:0*/ __Vtemp300[4]; + WData/*7:0*/ __Vtemp301[4]; + WData/*7:0*/ __Vtemp302[4]; + WData/*7:0*/ __Vtemp303[4]; + WData/*7:0*/ __Vtemp304[4]; + WData/*7:0*/ __Vtemp305[4]; + WData/*7:0*/ __Vtemp306[4]; + WData/*7:0*/ __Vtemp307[4]; + WData/*7:0*/ __Vtemp308[4]; + WData/*7:0*/ __Vtemp309[4]; + WData/*7:0*/ __Vtemp310[4]; + WData/*7:0*/ __Vtemp311[4]; + WData/*7:0*/ __Vtemp312[4]; + WData/*7:0*/ __Vtemp313[4]; + WData/*7:0*/ __Vtemp314[4]; + WData/*7:0*/ __Vtemp315[4]; + WData/*7:0*/ __Vtemp316[4]; + WData/*7:0*/ __Vtemp317[4]; + WData/*7:0*/ __Vtemp318[4]; + WData/*7:0*/ __Vtemp319[4]; + WData/*7:0*/ __Vtemp320[4]; + WData/*7:0*/ __Vtemp321[4]; + WData/*7:0*/ __Vtemp322[4]; + WData/*7:0*/ __Vtemp323[4]; + WData/*7:0*/ __Vtemp324[4]; + WData/*7:0*/ __Vtemp325[4]; + WData/*7:0*/ __Vtemp326[4]; + WData/*7:0*/ __Vtemp327[4]; + WData/*7:0*/ __Vtemp328[4]; + WData/*7:0*/ __Vtemp329[4]; + WData/*7:0*/ __Vtemp330[4]; + WData/*7:0*/ __Vtemp331[4]; + WData/*7:0*/ __Vtemp332[4]; + WData/*7:0*/ __Vtemp333[4]; + WData/*7:0*/ __Vtemp334[4]; + WData/*7:0*/ __Vtemp335[4]; + WData/*7:0*/ __Vtemp336[4]; + WData/*7:0*/ __Vtemp337[4]; + WData/*7:0*/ __Vtemp338[4]; + WData/*7:0*/ __Vtemp339[4]; + WData/*7:0*/ __Vtemp340[4]; + WData/*7:0*/ __Vtemp341[4]; + WData/*7:0*/ __Vtemp342[4]; + WData/*7:0*/ __Vtemp343[4]; + WData/*7:0*/ __Vtemp344[4]; + WData/*7:0*/ __Vtemp345[4]; + WData/*7:0*/ __Vtemp346[4]; + WData/*7:0*/ __Vtemp347[4]; + WData/*7:0*/ __Vtemp348[4]; + WData/*7:0*/ __Vtemp349[4]; + WData/*7:0*/ __Vtemp350[4]; + WData/*7:0*/ __Vtemp351[4]; + WData/*7:0*/ __Vtemp352[4]; + WData/*7:0*/ __Vtemp353[4]; + WData/*7:0*/ __Vtemp354[4]; + WData/*7:0*/ __Vtemp355[4]; + WData/*7:0*/ __Vtemp356[4]; + WData/*7:0*/ __Vtemp357[4]; + WData/*7:0*/ __Vtemp358[4]; + WData/*7:0*/ __Vtemp359[4]; + WData/*7:0*/ __Vtemp360[4]; + WData/*7:0*/ __Vtemp361[4]; + WData/*7:0*/ __Vtemp362[4]; + WData/*7:0*/ __Vtemp363[4]; + WData/*7:0*/ __Vtemp364[4]; + WData/*7:0*/ __Vtemp365[4]; + WData/*7:0*/ __Vtemp366[4]; + WData/*7:0*/ __Vtemp367[4]; + WData/*7:0*/ __Vtemp368[4]; + WData/*7:0*/ __Vtemp369[4]; + WData/*7:0*/ __Vtemp370[4]; + WData/*7:0*/ __Vtemp371[4]; + WData/*7:0*/ __Vtemp372[4]; + WData/*7:0*/ __Vtemp373[4]; + WData/*7:0*/ __Vtemp374[4]; + WData/*7:0*/ __Vtemp375[4]; + WData/*7:0*/ __Vtemp376[4]; + WData/*7:0*/ __Vtemp377[4]; + WData/*7:0*/ __Vtemp378[4]; + WData/*7:0*/ __Vtemp379[4]; + WData/*7:0*/ __Vtemp380[4]; + WData/*7:0*/ __Vtemp381[4]; + WData/*7:0*/ __Vtemp382[4]; + WData/*7:0*/ __Vtemp383[4]; + WData/*7:0*/ __Vtemp384[4]; + WData/*7:0*/ __Vtemp385[4]; + WData/*7:0*/ __Vtemp386[4]; + WData/*7:0*/ __Vtemp387[4]; + WData/*7:0*/ __Vtemp388[4]; + WData/*7:0*/ __Vtemp389[4]; + WData/*7:0*/ __Vtemp390[4]; + WData/*7:0*/ __Vtemp391[4]; + WData/*7:0*/ __Vtemp392[4]; + WData/*7:0*/ __Vtemp393[4]; + WData/*7:0*/ __Vtemp394[4]; + WData/*7:0*/ __Vtemp395[4]; + WData/*7:0*/ __Vtemp396[4]; + WData/*7:0*/ __Vtemp397[4]; + WData/*7:0*/ __Vtemp398[4]; + WData/*7:0*/ __Vtemp399[4]; + WData/*7:0*/ __Vtemp400[4]; + WData/*7:0*/ __Vtemp401[4]; + WData/*7:0*/ __Vtemp402[4]; + WData/*7:0*/ __Vtemp403[4]; + WData/*7:0*/ __Vtemp404[4]; + WData/*7:0*/ __Vtemp405[4]; + WData/*7:0*/ __Vtemp406[4]; + WData/*7:0*/ __Vtemp407[4]; + WData/*7:0*/ __Vtemp408[4]; + WData/*7:0*/ __Vtemp409[4]; + WData/*7:0*/ __Vtemp410[4]; + WData/*7:0*/ __Vtemp411[4]; + WData/*7:0*/ __Vtemp412[4]; + WData/*7:0*/ __Vtemp413[4]; + WData/*7:0*/ __Vtemp414[4]; + WData/*7:0*/ __Vtemp415[4]; + WData/*7:0*/ __Vtemp416[4]; + WData/*7:0*/ __Vtemp417[4]; + WData/*7:0*/ __Vtemp418[4]; + WData/*7:0*/ __Vtemp419[4]; + WData/*7:0*/ __Vtemp420[4]; + WData/*7:0*/ __Vtemp421[4]; + WData/*7:0*/ __Vtemp422[4]; + WData/*7:0*/ __Vtemp423[4]; + WData/*7:0*/ __Vtemp424[4]; + WData/*7:0*/ __Vtemp425[4]; + WData/*7:0*/ __Vtemp426[4]; + WData/*7:0*/ __Vtemp427[4]; + WData/*7:0*/ __Vtemp428[4]; + WData/*7:0*/ __Vtemp429[4]; + WData/*7:0*/ __Vtemp430[4]; + WData/*7:0*/ __Vtemp431[4]; + WData/*7:0*/ __Vtemp432[4]; + WData/*7:0*/ __Vtemp433[4]; + WData/*7:0*/ __Vtemp434[4]; + WData/*7:0*/ __Vtemp435[4]; + WData/*7:0*/ __Vtemp436[4]; + WData/*7:0*/ __Vtemp437[4]; + WData/*7:0*/ __Vtemp438[4]; + WData/*7:0*/ __Vtemp439[4]; + WData/*7:0*/ __Vtemp440[4]; + WData/*7:0*/ __Vtemp441[4]; + WData/*7:0*/ __Vtemp442[4]; + WData/*7:0*/ __Vtemp443[4]; + WData/*7:0*/ __Vtemp444[4]; + WData/*7:0*/ __Vtemp445[4]; + WData/*7:0*/ __Vtemp446[4]; + WData/*7:0*/ __Vtemp447[4]; + WData/*7:0*/ __Vtemp448[4]; + WData/*7:0*/ __Vtemp449[4]; + WData/*7:0*/ __Vtemp450[4]; + WData/*7:0*/ __Vtemp451[4]; + WData/*7:0*/ __Vtemp452[4]; + WData/*7:0*/ __Vtemp453[4]; + WData/*7:0*/ __Vtemp454[4]; + WData/*7:0*/ __Vtemp455[4]; + WData/*7:0*/ __Vtemp456[4]; + WData/*7:0*/ __Vtemp457[4]; + WData/*7:0*/ __Vtemp458[4]; + WData/*7:0*/ __Vtemp459[4]; + WData/*7:0*/ __Vtemp460[4]; + WData/*7:0*/ __Vtemp461[4]; + WData/*7:0*/ __Vtemp462[4]; + WData/*7:0*/ __Vtemp463[4]; + WData/*7:0*/ __Vtemp464[4]; + WData/*7:0*/ __Vtemp465[4]; + WData/*7:0*/ __Vtemp466[4]; + WData/*7:0*/ __Vtemp467[4]; + WData/*7:0*/ __Vtemp468[4]; + WData/*7:0*/ __Vtemp469[4]; + WData/*7:0*/ __Vtemp470[4]; + WData/*7:0*/ __Vtemp471[4]; + WData/*7:0*/ __Vtemp472[4]; + WData/*7:0*/ __Vtemp473[4]; + WData/*7:0*/ __Vtemp474[4]; + WData/*7:0*/ __Vtemp475[4]; + WData/*7:0*/ __Vtemp476[4]; + WData/*7:0*/ __Vtemp477[4]; + WData/*7:0*/ __Vtemp478[4]; + WData/*7:0*/ __Vtemp479[4]; + WData/*7:0*/ __Vtemp480[4]; + WData/*7:0*/ __Vtemp481[4]; + WData/*7:0*/ __Vtemp482[4]; + WData/*7:0*/ __Vtemp483[4]; + WData/*7:0*/ __Vtemp484[4]; + WData/*7:0*/ __Vtemp485[4]; + WData/*7:0*/ __Vtemp486[4]; + WData/*7:0*/ __Vtemp487[4]; + WData/*7:0*/ __Vtemp488[4]; + WData/*7:0*/ __Vtemp489[4]; + WData/*7:0*/ __Vtemp490[4]; + WData/*7:0*/ __Vtemp491[4]; + WData/*7:0*/ __Vtemp492[4]; + WData/*7:0*/ __Vtemp493[4]; + WData/*7:0*/ __Vtemp494[4]; + WData/*7:0*/ __Vtemp495[4]; + WData/*7:0*/ __Vtemp496[4]; + WData/*7:0*/ __Vtemp497[4]; + WData/*7:0*/ __Vtemp498[4]; + WData/*7:0*/ __Vtemp499[4]; + WData/*7:0*/ __Vtemp500[4]; + WData/*7:0*/ __Vtemp501[4]; + WData/*7:0*/ __Vtemp502[4]; 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+ WData/*31:0*/ __Vtemp183[4]; + WData/*31:0*/ __Vtemp184[4]; + WData/*31:0*/ __Vtemp185[4]; + WData/*31:0*/ __Vtemp186[4]; + WData/*31:0*/ __Vtemp187[4]; + WData/*31:0*/ __Vtemp188[4]; + WData/*31:0*/ __Vtemp189[4]; + WData/*31:0*/ __Vtemp190[4]; + WData/*31:0*/ __Vtemp191[4]; + WData/*31:0*/ __Vtemp192[4]; + WData/*31:0*/ __Vtemp193[4]; + WData/*31:0*/ __Vtemp194[4]; + WData/*31:0*/ __Vtemp195[4]; + WData/*31:0*/ __Vtemp196[4]; + WData/*31:0*/ __Vtemp197[4]; + WData/*31:0*/ __Vtemp198[4]; + WData/*31:0*/ __Vtemp201[4]; + WData/*31:0*/ __Vtemp204[4]; + WData/*31:0*/ __Vtemp207[4]; + WData/*31:0*/ __Vtemp210[4]; + WData/*31:0*/ __Vtemp541[4]; + WData/*31:0*/ __Vtemp542[4]; + WData/*31:0*/ __Vtemp543[4]; + WData/*31:0*/ __Vtemp544[4]; + WData/*31:0*/ __Vtemp545[4]; + // Body + { + vcdp->fullBus(c+1,((0xffffffc0U & vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT__eviction_addr_per_bank[0U])),32); + vcdp->fullArray(c+2,(vlTOPp->cache_simX__DOT__dmem_controller__DOT____Vcellout__dcache__o_m_writedata),512); + vcdp->fullBus(c+18,((0xfffffff0U & ((vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__tag_use + << 9U) + | (0x1f0U + & vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_addr)))),32); + __Vtemp148[0U] = (((0U == (0x1fU & ((IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__data_structures__DOT__way_use_Qual) + << 7U))) + ? 0U : (vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__data_structures__DOT__data_use_per_way[ + ((IData)(1U) + + (4U & ((IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__data_structures__DOT__way_use_Qual) + << 2U)))] + << ((IData)(0x20U) + - (0x1fU & + ((IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__data_structures__DOT__way_use_Qual) + << 7U))))) + | (vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__data_structures__DOT__data_use_per_way[ + (4U & ((IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__data_structures__DOT__way_use_Qual) + << 2U))] >> (0x1fU + & ((IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__data_structures__DOT__way_use_Qual) + << 7U)))); + __Vtemp148[1U] = (((0U == (0x1fU & ((IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__data_structures__DOT__way_use_Qual) + << 7U))) + ? 0U : (vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__data_structures__DOT__data_use_per_way[ + ((IData)(2U) + + (4U & ((IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__data_structures__DOT__way_use_Qual) + << 2U)))] + << ((IData)(0x20U) + - (0x1fU & + ((IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__data_structures__DOT__way_use_Qual) + << 7U))))) + | (vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__data_structures__DOT__data_use_per_way[ + ((IData)(1U) + (4U & ((IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__data_structures__DOT__way_use_Qual) + << 2U)))] + >> (0x1fU & ((IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__data_structures__DOT__way_use_Qual) + << 7U)))); + __Vtemp148[2U] = (((0U == (0x1fU & ((IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__data_structures__DOT__way_use_Qual) + << 7U))) + ? 0U : (vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__data_structures__DOT__data_use_per_way[ + ((IData)(3U) + + (4U & ((IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__data_structures__DOT__way_use_Qual) + << 2U)))] + << ((IData)(0x20U) + - (0x1fU & + ((IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__data_structures__DOT__way_use_Qual) + << 7U))))) + | (vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__data_structures__DOT__data_use_per_way[ + ((IData)(2U) + (4U & ((IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__data_structures__DOT__way_use_Qual) + << 2U)))] + >> (0x1fU & ((IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__data_structures__DOT__way_use_Qual) + << 7U)))); + __Vtemp148[3U] = (((0U == (0x1fU & ((IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__data_structures__DOT__way_use_Qual) + << 7U))) + ? 0U : (vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__data_structures__DOT__data_use_per_way[ + ((IData)(4U) + + (4U & ((IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__data_structures__DOT__way_use_Qual) + << 2U)))] + << ((IData)(0x20U) + - (0x1fU & + ((IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__data_structures__DOT__way_use_Qual) + << 7U))))) + | (vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__data_structures__DOT__data_use_per_way[ + ((IData)(3U) + (4U & ((IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__data_structures__DOT__way_use_Qual) + << 2U)))] + >> (0x1fU & ((IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__data_structures__DOT__way_use_Qual) + << 7U)))); + vcdp->fullArray(c+19,(__Vtemp148),128); + vcdp->fullArray(c+23,(vlSymsp->TOP__cache_simX__DOT__VX_dcache_req.out_cache_driver_in_address),128); + vcdp->fullBus(c+27,(vlSymsp->TOP__cache_simX__DOT__VX_dcache_req.out_cache_driver_in_valid),4); + __Vtemp153[0U] = ((0xffU == (0xffU & ((vlSymsp->TOP__cache_simX__DOT__VX_dcache_req.out_cache_driver_in_address[1U] + << 8U) + | (vlSymsp->TOP__cache_simX__DOT__VX_dcache_req.out_cache_driver_in_address[0U] + >> 0x18U)))) + ? (((~ (IData)((0U != (IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__vx_priority_encoder_sm__DOT__more_than_one_valid)))) + & (0U != (IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__orig_in_valid))) + ? vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__temp_out_data[0U] + : 0U) : vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT__new_final_data_read_Qual[0U]); + __Vtemp153[1U] = ((0xffU == (0xffU & ((vlSymsp->TOP__cache_simX__DOT__VX_dcache_req.out_cache_driver_in_address[1U] + << 8U) + | (vlSymsp->TOP__cache_simX__DOT__VX_dcache_req.out_cache_driver_in_address[0U] + >> 0x18U)))) + ? (((~ (IData)((0U != (IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__vx_priority_encoder_sm__DOT__more_than_one_valid)))) + & (0U != (IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__orig_in_valid))) + ? vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__temp_out_data[1U] + : 0U) : vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT__new_final_data_read_Qual[1U]); + __Vtemp153[2U] = ((0xffU == (0xffU & ((vlSymsp->TOP__cache_simX__DOT__VX_dcache_req.out_cache_driver_in_address[1U] + << 8U) + | (vlSymsp->TOP__cache_simX__DOT__VX_dcache_req.out_cache_driver_in_address[0U] + >> 0x18U)))) + ? (((~ (IData)((0U != (IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__vx_priority_encoder_sm__DOT__more_than_one_valid)))) + & (0U != (IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__orig_in_valid))) + ? vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__temp_out_data[2U] + : 0U) : vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT__new_final_data_read_Qual[2U]); + __Vtemp153[3U] = ((0xffU == (0xffU & ((vlSymsp->TOP__cache_simX__DOT__VX_dcache_req.out_cache_driver_in_address[1U] + << 8U) + | (vlSymsp->TOP__cache_simX__DOT__VX_dcache_req.out_cache_driver_in_address[0U] + >> 0x18U)))) + ? (((~ (IData)((0U != (IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__vx_priority_encoder_sm__DOT__more_than_one_valid)))) + & (0U != (IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__orig_in_valid))) + ? vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__temp_out_data[3U] + : 0U) : vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT__new_final_data_read_Qual[3U]); + vcdp->fullArray(c+28,(__Vtemp153),128); + vcdp->fullBit(c+32,((0xffU == (0xffU & ((vlSymsp->TOP__cache_simX__DOT__VX_dcache_req.out_cache_driver_in_address[1U] + << 8U) + | (vlSymsp->TOP__cache_simX__DOT__VX_dcache_req.out_cache_driver_in_address[0U] + >> 0x18U)))))); + vcdp->fullBus(c+33,(vlTOPp->cache_simX__DOT__dmem_controller__DOT__sm_driver_in_valid),4); + vcdp->fullBus(c+34,(vlTOPp->cache_simX__DOT__dmem_controller__DOT__cache_driver_in_valid),4); + vcdp->fullBit(c+35,(vlTOPp->cache_simX__DOT__dmem_controller__DOT__read_or_write)); + vcdp->fullBus(c+36,(vlTOPp->cache_simX__DOT__dmem_controller__DOT__cache_driver_in_mem_read),3); + vcdp->fullBus(c+37,(vlTOPp->cache_simX__DOT__dmem_controller__DOT__cache_driver_in_mem_write),3); + vcdp->fullBus(c+38,(vlTOPp->cache_simX__DOT__dmem_controller__DOT__sm_driver_in_mem_read),3); + vcdp->fullBus(c+39,(vlTOPp->cache_simX__DOT__dmem_controller__DOT__sm_driver_in_mem_write),3); + vcdp->fullArray(c+40,(vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT__new_final_data_read_Qual),128); + __Vtemp156[0U] = (((~ (IData)((0U != (IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__vx_priority_encoder_sm__DOT__more_than_one_valid)))) + & (0U != (IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__orig_in_valid))) + ? vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__temp_out_data[0U] + : 0U); + __Vtemp156[1U] = (((~ (IData)((0U != (IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__vx_priority_encoder_sm__DOT__more_than_one_valid)))) + & (0U != (IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__orig_in_valid))) + ? vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__temp_out_data[1U] + : 0U); + __Vtemp156[2U] = (((~ (IData)((0U != (IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__vx_priority_encoder_sm__DOT__more_than_one_valid)))) + & (0U != (IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__orig_in_valid))) + ? vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__temp_out_data[2U] + : 0U); + __Vtemp156[3U] = (((~ (IData)((0U != (IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__vx_priority_encoder_sm__DOT__more_than_one_valid)))) + & (0U != (IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__orig_in_valid))) + ? vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__temp_out_data[3U] + : 0U); + vcdp->fullArray(c+44,(__Vtemp156),128); + vcdp->fullBus(c+48,((((~ (IData)((0U != (IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__vx_priority_encoder_sm__DOT__more_than_one_valid)))) + & (0U != (IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__orig_in_valid))) + ? (0xfU & (IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__temp_out_valid)) + : 0U)),4); + vcdp->fullBit(c+49,((0U != (IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__vx_priority_encoder_sm__DOT__more_than_one_valid)))); + vcdp->fullBus(c+50,(vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache_driver_in_mem_read),3); + vcdp->fullArray(c+51,(vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT____Vcellout__vx_priority_encoder_sm__out_address),128); + vcdp->fullArray(c+55,(vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT____Vcellout__vx_priority_encoder_sm__out_data),128); + vcdp->fullBus(c+59,(vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__vx_priority_encoder_sm__DOT__internal_out_valid),4); + vcdp->fullBus(c+60,(vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__temp_out_valid),4); + vcdp->fullArray(c+61,(vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__temp_out_data),128); + vcdp->fullBus(c+65,(vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__block_addr),28); + vcdp->fullArray(c+66,(vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__block_wdata),512); + vcdp->fullArray(c+82,(vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__block_rdata),512); + vcdp->fullBus(c+98,(vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__block_we),8); + vcdp->fullBit(c+99,(((~ (IData)((0U != (IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__vx_priority_encoder_sm__DOT__more_than_one_valid)))) + & (0U != (IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__orig_in_valid))))); + vcdp->fullBus(c+100,(vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__vx_priority_encoder_sm__DOT__internal_req_num),12); + vcdp->fullBus(c+101,(vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__orig_in_valid),4); + vcdp->fullBit(c+102,(vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__genblk2__BRA__0__KET____DOT__shm_write)); + vcdp->fullBit(c+103,(vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__genblk2__BRA__1__KET____DOT__shm_write)); + vcdp->fullBit(c+104,(vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__genblk2__BRA__2__KET____DOT__shm_write)); + vcdp->fullBit(c+105,(vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__genblk2__BRA__3__KET____DOT__shm_write)); + vcdp->fullBus(c+106,(vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__vx_priority_encoder_sm__DOT__serviced),4); + vcdp->fullBus(c+107,(vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__vx_priority_encoder_sm__DOT__use_valid),4); + vcdp->fullBus(c+108,(vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__vx_priority_encoder_sm__DOT____Vcellout__vx_bank_valid__bank_valids),16); + vcdp->fullBus(c+109,(vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__vx_priority_encoder_sm__DOT__more_than_one_valid),4); + vcdp->fullBus(c+110,(vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__vx_priority_encoder_sm__DOT__internal_req_num),8); + vcdp->fullBus(c+111,(vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__vx_priority_encoder_sm__DOT__serviced_qual),4); + vcdp->fullBus(c+112,(vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__vx_priority_encoder_sm__DOT__genblk1__BRA__0__KET____DOT__num_valids),3); + vcdp->fullBus(c+113,(vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__vx_priority_encoder_sm__DOT__genblk1__BRA__1__KET____DOT__num_valids),3); + vcdp->fullBus(c+114,(vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__vx_priority_encoder_sm__DOT__genblk1__BRA__2__KET____DOT__num_valids),3); + vcdp->fullBus(c+115,(vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__vx_priority_encoder_sm__DOT__genblk1__BRA__3__KET____DOT__num_valids),3); + vcdp->fullBus(c+116,((0xfU & (IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__vx_priority_encoder_sm__DOT____Vcellout__vx_bank_valid__bank_valids))),4); + vcdp->fullBus(c+117,((0xfU & ((IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__vx_priority_encoder_sm__DOT____Vcellout__vx_bank_valid__bank_valids) + >> 4U))),4); + vcdp->fullBus(c+118,((0xfU & ((IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__vx_priority_encoder_sm__DOT____Vcellout__vx_bank_valid__bank_valids) + >> 8U))),4); + vcdp->fullBus(c+119,((0xfU & ((IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__vx_priority_encoder_sm__DOT____Vcellout__vx_bank_valid__bank_valids) + >> 0xcU))),4); + vcdp->fullBus(c+120,(vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__vx_priority_encoder_sm__DOT____Vcellout__genblk2__BRA__0__KET____DOT__vx_priority_encoder__index),2); + vcdp->fullBit(c+121,(vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__vx_priority_encoder_sm__DOT____Vcellout__genblk2__BRA__0__KET____DOT__vx_priority_encoder__found)); + vcdp->fullBus(c+122,(vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__vx_priority_encoder_sm__DOT__genblk2__BRA__0__KET____DOT__vx_priority_encoder__DOT__i),32); + vcdp->fullBus(c+123,(vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__vx_priority_encoder_sm__DOT____Vcellout__genblk2__BRA__1__KET____DOT__vx_priority_encoder__index),2); + vcdp->fullBit(c+124,(vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__vx_priority_encoder_sm__DOT____Vcellout__genblk2__BRA__1__KET____DOT__vx_priority_encoder__found)); + vcdp->fullBus(c+125,(vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__vx_priority_encoder_sm__DOT__genblk2__BRA__1__KET____DOT__vx_priority_encoder__DOT__i),32); + vcdp->fullBus(c+126,(vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__vx_priority_encoder_sm__DOT____Vcellout__genblk2__BRA__2__KET____DOT__vx_priority_encoder__index),2); + vcdp->fullBit(c+127,(vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__vx_priority_encoder_sm__DOT____Vcellout__genblk2__BRA__2__KET____DOT__vx_priority_encoder__found)); + vcdp->fullBus(c+128,(vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__vx_priority_encoder_sm__DOT__genblk2__BRA__2__KET____DOT__vx_priority_encoder__DOT__i),32); + vcdp->fullBus(c+129,(vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__vx_priority_encoder_sm__DOT____Vcellout__genblk2__BRA__3__KET____DOT__vx_priority_encoder__index),2); + vcdp->fullBit(c+130,(vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__vx_priority_encoder_sm__DOT____Vcellout__genblk2__BRA__3__KET____DOT__vx_priority_encoder__found)); + vcdp->fullBus(c+131,(vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__vx_priority_encoder_sm__DOT__genblk2__BRA__3__KET____DOT__vx_priority_encoder__DOT__i),32); + vcdp->fullBus(c+132,((0x7fU & vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__block_addr)),7); + __Vtemp157[0U] = vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__block_wdata[0U]; + __Vtemp157[1U] = vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__block_wdata[1U]; + __Vtemp157[2U] = vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__block_wdata[2U]; + __Vtemp157[3U] = vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__block_wdata[3U]; + vcdp->fullArray(c+133,(__Vtemp157),128); + vcdp->fullBus(c+137,((3U & (IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__block_we))),2); + vcdp->fullBus(c+138,((0x7fU & (vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__block_addr + >> 7U))),7); + __Vtemp158[0U] = vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__block_wdata[4U]; + __Vtemp158[1U] = vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__block_wdata[5U]; + __Vtemp158[2U] = vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__block_wdata[6U]; + __Vtemp158[3U] = vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__block_wdata[7U]; + vcdp->fullArray(c+139,(__Vtemp158),128); + vcdp->fullBus(c+143,((3U & ((IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__block_we) + >> 2U))),2); + vcdp->fullBus(c+144,((0x7fU & (vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__block_addr + >> 0xeU))),7); + __Vtemp159[0U] = vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__block_wdata[8U]; + __Vtemp159[1U] = vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__block_wdata[9U]; + __Vtemp159[2U] = vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__block_wdata[0xaU]; + __Vtemp159[3U] = vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__block_wdata[0xbU]; + vcdp->fullArray(c+145,(__Vtemp159),128); + vcdp->fullBus(c+149,((3U & ((IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__block_we) + >> 4U))),2); + vcdp->fullBus(c+150,((0x7fU & (vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__block_addr + >> 0x15U))),7); + __Vtemp160[0U] = vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__block_wdata[0xcU]; + __Vtemp160[1U] = vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__block_wdata[0xdU]; + __Vtemp160[2U] = vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__block_wdata[0xeU]; + __Vtemp160[3U] = vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__block_wdata[0xfU]; + vcdp->fullArray(c+151,(__Vtemp160),128); + vcdp->fullBus(c+155,((3U & ((IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__block_we) + >> 6U))),2); + vcdp->fullArray(c+156,(vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT__new_final_data_read),128); + vcdp->fullBus(c+160,(vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT____Vcellout__multip_banks__thread_track_banks),16); + vcdp->fullBus(c+161,(vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT__index_per_bank),8); + vcdp->fullBus(c+162,(vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT__use_mask_per_bank),16); + vcdp->fullBus(c+163,(vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT__valid_per_bank),4); + vcdp->fullBus(c+164,(vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT__threads_serviced_per_bank),16); + vcdp->fullArray(c+165,(vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT__readdata_per_bank),128); + vcdp->fullBus(c+169,(vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT__hit_per_bank),4); + vcdp->fullBus(c+170,(vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT__eviction_wb),4); + vcdp->fullBus(c+171,(vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT__new_state),4); + vcdp->fullBus(c+172,(vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT__use_valid),4); + vcdp->fullBus(c+173,(vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT__new_stored_valid),4); + vcdp->fullArray(c+174,(vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT__eviction_addr_per_bank),128); + vcdp->fullBit(c+178,((0U != (IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__cache_driver_in_valid)))); + vcdp->fullBus(c+179,(vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT__threads_serviced_Qual),4); + vcdp->fullBus(c+180,(vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT__debug_hit_per_bank_mask[0]),4); + vcdp->fullBus(c+181,(vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT__debug_hit_per_bank_mask[1]),4); + vcdp->fullBus(c+182,(vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT__debug_hit_per_bank_mask[2]),4); + vcdp->fullBus(c+183,(vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT__debug_hit_per_bank_mask[3]),4); + vcdp->fullBus(c+184,(vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT__detect_bank_miss),4); + vcdp->fullBus(c+185,(vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT__miss_bank_index),2); + vcdp->fullBit(c+186,(vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT__miss_found)); + vcdp->fullBus(c+187,((0xfU & (IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT____Vcellout__multip_banks__thread_track_banks))),4); + vcdp->fullBus(c+188,((3U & (IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT__index_per_bank))),2); + vcdp->fullBit(c+189,((1U & (IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT__hit_per_bank)))); + vcdp->fullBus(c+190,(vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT__readdata_per_bank[0U]),32); + vcdp->fullBus(c+191,((0xfU & ((IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT____Vcellout__multip_banks__thread_track_banks) + >> 4U))),4); + vcdp->fullBus(c+192,((3U & ((IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT__index_per_bank) + >> 2U))),2); + vcdp->fullBit(c+193,((1U & ((IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT__hit_per_bank) + >> 1U)))); + vcdp->fullBus(c+194,(vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT__readdata_per_bank[1U]),32); + vcdp->fullBus(c+195,((0xfU & ((IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT____Vcellout__multip_banks__thread_track_banks) + >> 8U))),4); + vcdp->fullBus(c+196,((3U & ((IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT__index_per_bank) + >> 4U))),2); + vcdp->fullBit(c+197,((1U & ((IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT__hit_per_bank) + >> 2U)))); + vcdp->fullBus(c+198,(vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT__readdata_per_bank[2U]),32); + vcdp->fullBus(c+199,((0xfU & ((IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT____Vcellout__multip_banks__thread_track_banks) + >> 0xcU))),4); + vcdp->fullBus(c+200,((3U & ((IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT__index_per_bank) + >> 6U))),2); + vcdp->fullBit(c+201,((1U & ((IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT__hit_per_bank) + >> 3U)))); + vcdp->fullBus(c+202,(vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT__readdata_per_bank[3U]),32); + vcdp->fullBus(c+203,(vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__0__KET____DOT__bank_addr),32); + vcdp->fullBus(c+204,((3U & vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__0__KET____DOT__bank_addr)),2); + vcdp->fullBus(c+205,((3U & (vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__0__KET____DOT__bank_addr + >> 4U))),2); + vcdp->fullBus(c+206,((0x1fU & (vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__0__KET____DOT__bank_addr + >> 6U))),5); + vcdp->fullBus(c+207,((0x1fffffU & (vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__0__KET____DOT__bank_addr + >> 0xbU))),21); + vcdp->fullBit(c+208,((1U & (IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT__valid_per_bank)))); + vcdp->fullBit(c+209,(vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__0__KET____DOT__use_valid_in)); + vcdp->fullBus(c+210,(vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__1__KET____DOT__bank_addr),32); + vcdp->fullBus(c+211,((3U & vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__1__KET____DOT__bank_addr)),2); + vcdp->fullBus(c+212,((3U & (vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__1__KET____DOT__bank_addr + >> 4U))),2); + vcdp->fullBus(c+213,((0x1fU & (vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__1__KET____DOT__bank_addr + >> 6U))),5); + vcdp->fullBus(c+214,((0x1fffffU & (vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__1__KET____DOT__bank_addr + >> 0xbU))),21); + vcdp->fullBit(c+215,((1U & ((IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT__valid_per_bank) + >> 1U)))); + vcdp->fullBit(c+216,(vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__1__KET____DOT__use_valid_in)); + vcdp->fullBus(c+217,(vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__2__KET____DOT__bank_addr),32); + vcdp->fullBus(c+218,((3U & vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__2__KET____DOT__bank_addr)),2); + vcdp->fullBus(c+219,((3U & (vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__2__KET____DOT__bank_addr + >> 4U))),2); + vcdp->fullBus(c+220,((0x1fU & (vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__2__KET____DOT__bank_addr + >> 6U))),5); + vcdp->fullBus(c+221,((0x1fffffU & (vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__2__KET____DOT__bank_addr + >> 0xbU))),21); + vcdp->fullBit(c+222,((1U & ((IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT__valid_per_bank) + >> 2U)))); + vcdp->fullBit(c+223,(vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__2__KET____DOT__use_valid_in)); + vcdp->fullBus(c+224,(vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__3__KET____DOT__bank_addr),32); + vcdp->fullBus(c+225,((3U & vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__3__KET____DOT__bank_addr)),2); + vcdp->fullBus(c+226,((3U & (vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__3__KET____DOT__bank_addr + >> 4U))),2); + vcdp->fullBus(c+227,((0x1fU & (vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__3__KET____DOT__bank_addr + >> 6U))),5); + vcdp->fullBus(c+228,((0x1fffffU & (vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__3__KET____DOT__bank_addr + >> 0xbU))),21); + vcdp->fullBit(c+229,((1U & ((IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT__valid_per_bank) + >> 3U)))); + vcdp->fullBit(c+230,(vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__3__KET____DOT__use_valid_in)); + vcdp->fullBus(c+231,(vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT__get_miss_index__DOT__i),32); + vcdp->fullBus(c+232,(((IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT____Vcellout__genblk1__BRA__0__KET____DOT__choose_thread__found) + ? (0xfU & ((IData)(1U) + << (IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT____Vcellout__genblk1__BRA__0__KET____DOT__choose_thread__index))) + : 0U)),4); + vcdp->fullBus(c+233,(vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT____Vcellout__genblk1__BRA__0__KET____DOT__choose_thread__index),2); + vcdp->fullBit(c+234,(vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT____Vcellout__genblk1__BRA__0__KET____DOT__choose_thread__found)); + vcdp->fullBus(c+235,(vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk1__BRA__0__KET____DOT__choose_thread__DOT__i),32); + vcdp->fullBus(c+236,(((IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT____Vcellout__genblk1__BRA__1__KET____DOT__choose_thread__found) + ? (0xfU & ((IData)(1U) + << (IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT____Vcellout__genblk1__BRA__1__KET____DOT__choose_thread__index))) + : 0U)),4); + vcdp->fullBus(c+237,(vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT____Vcellout__genblk1__BRA__1__KET____DOT__choose_thread__index),2); + vcdp->fullBit(c+238,(vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT____Vcellout__genblk1__BRA__1__KET____DOT__choose_thread__found)); + vcdp->fullBus(c+239,(vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk1__BRA__1__KET____DOT__choose_thread__DOT__i),32); + vcdp->fullBus(c+240,(((IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT____Vcellout__genblk1__BRA__2__KET____DOT__choose_thread__found) + ? (0xfU & ((IData)(1U) + << (IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT____Vcellout__genblk1__BRA__2__KET____DOT__choose_thread__index))) + : 0U)),4); + vcdp->fullBus(c+241,(vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT____Vcellout__genblk1__BRA__2__KET____DOT__choose_thread__index),2); + vcdp->fullBit(c+242,(vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT____Vcellout__genblk1__BRA__2__KET____DOT__choose_thread__found)); + vcdp->fullBus(c+243,(vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk1__BRA__2__KET____DOT__choose_thread__DOT__i),32); + vcdp->fullBus(c+244,(((IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT____Vcellout__genblk1__BRA__3__KET____DOT__choose_thread__found) + ? (0xfU & ((IData)(1U) + << (IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT____Vcellout__genblk1__BRA__3__KET____DOT__choose_thread__index))) + : 0U)),4); + vcdp->fullBus(c+245,(vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT____Vcellout__genblk1__BRA__3__KET____DOT__choose_thread__index),2); + vcdp->fullBit(c+246,(vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT____Vcellout__genblk1__BRA__3__KET____DOT__choose_thread__found)); + vcdp->fullBus(c+247,(vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk1__BRA__3__KET____DOT__choose_thread__DOT__i),32); + vcdp->fullBus(c+248,(vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__new_final_data_read),32); + vcdp->fullBit(c+249,(vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT____Vcellout__multip_banks__thread_track_banks)); + vcdp->fullBit(c+250,(vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT____Vcellout__genblk1__BRA__0__KET____DOT__choose_thread__index)); + vcdp->fullBit(c+251,(((IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__valid_per_bank) + ? (1U & ((IData)(1U) + << (IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT____Vcellout__genblk1__BRA__0__KET____DOT__choose_thread__index))) + : 0U))); + vcdp->fullBit(c+252,(vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__valid_per_bank)); + vcdp->fullBit(c+253,(vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__threads_serviced_per_bank)); + vcdp->fullBus(c+254,(((IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__access) + ? ((0U == (IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache_driver_in_mem_read)) + ? ((0x80U & vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__data_unQual) + ? (0xffffff00U + | vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__data_unQual) + : (0xffU & vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__data_unQual)) + : ((1U == (IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache_driver_in_mem_read)) + ? ((0x8000U + & vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__data_unQual) + ? (0xffff0000U + | vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__data_unQual) + : (0xffffU + & vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__data_unQual)) + : ((5U == (IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache_driver_in_mem_read)) + ? (0xffffU + & vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__data_unQual) + : ((4U == (IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache_driver_in_mem_read)) + ? (0xffU + & vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__data_unQual) + : vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__data_unQual)))) + : 0U)),32); + vcdp->fullBit(c+255,(vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__hit_per_bank)); + vcdp->fullBit(c+256,((1U & ((IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__data_structures__DOT__dirty_use_per_way) + >> (IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__data_structures__DOT__way_use_Qual))))); + vcdp->fullBus(c+257,(vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__new_state),4); + vcdp->fullBit(c+258,(vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__use_valid)); + vcdp->fullBit(c+259,(vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__new_stored_valid)); + vcdp->fullBus(c+260,(((vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__tag_use + << 9U) | (0x1f0U & vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_addr))),32); + vcdp->fullBit(c+261,(vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__threads_serviced_per_bank)); + vcdp->fullBit(c+262,(vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__debug_hit_per_bank_mask[0])); + vcdp->fullBit(c+263,(vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__detect_bank_miss)); + vcdp->fullBit(c+264,(vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__miss_bank_index)); + vcdp->fullBit(c+265,(vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__miss_found)); + vcdp->fullBit(c+266,(vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__hit_per_bank)); + vcdp->fullBus(c+267,(vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_addr),32); + vcdp->fullBus(c+268,((3U & vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_addr)),2); + vcdp->fullBus(c+269,((3U & (vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_addr + >> 2U))),2); + vcdp->fullBus(c+270,((0x1fU & (vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_addr + >> 4U))),5); + vcdp->fullBus(c+271,((0x7fffffU & (vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_addr + >> 9U))),23); + vcdp->fullBit(c+272,(vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__valid_per_bank)); + vcdp->fullBit(c+273,(vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__use_valid_in)); + vcdp->fullBus(c+274,(0U),32); + vcdp->fullBus(c+275,(vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__tag_use),23); + vcdp->fullBit(c+276,(vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__valid_use)); + vcdp->fullBit(c+277,(vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__access)); + vcdp->fullBit(c+278,(vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__write_from_mem)); + vcdp->fullBit(c+279,((((vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__tag_use + != (0x7fffffU & (vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_addr + >> 9U))) + & (IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__valid_use)) + & (IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__use_valid_in)))); + vcdp->fullBit(c+280,((2U == (IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache_driver_in_mem_read)))); + vcdp->fullBit(c+281,((0U == (IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache_driver_in_mem_read)))); + vcdp->fullBit(c+282,((1U == (IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache_driver_in_mem_read)))); + vcdp->fullBit(c+283,((5U == (IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache_driver_in_mem_read)))); + vcdp->fullBit(c+284,((4U == (IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache_driver_in_mem_read)))); + vcdp->fullBit(c+285,((0U == (3U & vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_addr)))); + vcdp->fullBit(c+286,((1U == (3U & vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_addr)))); + vcdp->fullBit(c+287,((2U == (3U & vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_addr)))); + vcdp->fullBit(c+288,((3U == (3U & vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_addr)))); + vcdp->fullBus(c+289,(vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__data_unQual),32); + vcdp->fullBus(c+290,(((0x80U & vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__data_unQual) + ? (0xffffff00U | vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__data_unQual) + : (0xffU & vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__data_unQual))),32); + vcdp->fullBus(c+291,(((0x8000U & vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__data_unQual) + ? (0xffff0000U | vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__data_unQual) + : (0xffffU & vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__data_unQual))),32); + vcdp->fullBus(c+292,((0xffU & vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__data_unQual)),32); + vcdp->fullBus(c+293,((0xffffU & vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__data_unQual)),32); + vcdp->fullBus(c+294,(0U),32); + vcdp->fullBus(c+295,(0U),32); + vcdp->fullBus(c+296,(((0U == (IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache_driver_in_mem_read)) + ? ((0x80U & vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__data_unQual) + ? (0xffffff00U | vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__data_unQual) + : (0xffU & vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__data_unQual)) + : ((1U == (IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache_driver_in_mem_read)) + ? ((0x8000U & vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__data_unQual) + ? (0xffff0000U + | vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__data_unQual) + : (0xffffU & vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__data_unQual)) + : ((5U == (IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache_driver_in_mem_read)) + ? (0xffffU & vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__data_unQual) + : ((4U == (IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache_driver_in_mem_read)) + ? (0xffU + & vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__data_unQual) + : vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__data_unQual))))),32); + vcdp->fullBus(c+297,(vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__sb_mask),4); + vcdp->fullBus(c+298,(((0U == (3U & vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_addr)) + ? 3U : 0xcU)),4); + vcdp->fullBus(c+299,(vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__we),16); + vcdp->fullArray(c+300,(vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__data_write),128); + vcdp->fullQuad(c+304,(vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__data_structures__DOT__tag_use_per_way),46); + vcdp->fullArray(c+306,(vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__data_structures__DOT__data_use_per_way),256); + vcdp->fullBus(c+314,(vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__data_structures__DOT__valid_use_per_way),2); + vcdp->fullBus(c+315,(vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__data_structures__DOT__dirty_use_per_way),2); + vcdp->fullBus(c+316,(vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__data_structures__DOT__hit_per_way),2); + vcdp->fullBus(c+317,(vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__data_structures__DOT__we_per_way),32); + vcdp->fullArray(c+318,(vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__data_structures__DOT__data_write_per_way),256); + vcdp->fullBus(c+326,(vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__data_structures__DOT__write_from_mem_per_way),2); + vcdp->fullBit(c+327,(vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__data_structures__DOT__invalid_found)); + vcdp->fullBit(c+328,(vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__data_structures__DOT__way_index)); + vcdp->fullBit(c+329,(vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__data_structures__DOT__invalid_index)); + vcdp->fullBit(c+330,(vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__data_structures__DOT__way_use_Qual)); + vcdp->fullBus(c+331,((3U & (~ (IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__data_structures__DOT__valid_use_per_way)))),2); + vcdp->fullBit(c+332,(vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__data_structures__DOT__genblk1__DOT__way_indexing__DOT__found)); + vcdp->fullBus(c+333,((0xffffU & vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__data_structures__DOT__we_per_way)),16); + vcdp->fullBit(c+334,((1U & (IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__data_structures__DOT__write_from_mem_per_way)))); + __Vtemp161[0U] = vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__data_structures__DOT__data_write_per_way[0U]; + __Vtemp161[1U] = vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__data_structures__DOT__data_write_per_way[1U]; + __Vtemp161[2U] = vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__data_structures__DOT__data_write_per_way[2U]; + __Vtemp161[3U] = vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__data_structures__DOT__data_write_per_way[3U]; + vcdp->fullArray(c+335,(__Vtemp161),128); + vcdp->fullBit(c+339,(vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__data_structures__DOT____Vcellout__each_way__BRA__0__KET____DOT__data_structures__dirty_use)); + vcdp->fullBit(c+340,((0U != (0xffffU & vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__data_structures__DOT__we_per_way)))); + vcdp->fullBit(c+341,((1U & (((~ (IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__data_structures__DOT____Vcellout__each_way__BRA__0__KET____DOT__data_structures__dirty_use)) + & (0U != (0xffffU + & vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__data_structures__DOT__we_per_way))) + | (IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__data_structures__DOT__write_from_mem_per_way))))); + vcdp->fullBit(c+342,(((1U & (IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__data_structures__DOT__write_from_mem_per_way)) + ? 0U : (1U & (0U != + (0xffffU + & vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__data_structures__DOT__we_per_way)))))); + vcdp->fullBus(c+343,((0xffffU & (vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__data_structures__DOT__we_per_way + >> 0x10U))),16); + vcdp->fullBit(c+344,((1U & ((IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__data_structures__DOT__write_from_mem_per_way) + >> 1U)))); + __Vtemp162[0U] = vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__data_structures__DOT__data_write_per_way[4U]; + __Vtemp162[1U] = vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__data_structures__DOT__data_write_per_way[5U]; + __Vtemp162[2U] = vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__data_structures__DOT__data_write_per_way[6U]; + __Vtemp162[3U] = vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__data_structures__DOT__data_write_per_way[7U]; + vcdp->fullArray(c+345,(__Vtemp162),128); + vcdp->fullBit(c+349,(vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__data_structures__DOT____Vcellout__each_way__BRA__1__KET____DOT__data_structures__dirty_use)); + vcdp->fullBit(c+350,((0U != (0xffffU & (vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__data_structures__DOT__we_per_way + >> 0x10U))))); + vcdp->fullBit(c+351,((1U & (((~ (IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__data_structures__DOT____Vcellout__each_way__BRA__1__KET____DOT__data_structures__dirty_use)) + & (0U != (0xffffU + & (vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__data_structures__DOT__we_per_way + >> 0x10U)))) + | ((IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__data_structures__DOT__write_from_mem_per_way) + >> 1U))))); + vcdp->fullBit(c+352,(((2U & (IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__data_structures__DOT__write_from_mem_per_way)) + ? 0U : (1U & (0U != + (0xffffU + & (vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__data_structures__DOT__we_per_way + >> 0x10U))))))); + __Vtemp163[0U] = 0U; + __Vtemp163[1U] = 0U; + __Vtemp163[2U] = 0U; + __Vtemp163[3U] = 0U; + vcdp->fullBus(c+353,(__Vtemp163[(3U & (IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT__index_per_bank))]),32); + vcdp->fullBus(c+354,(((IData)(vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__0__KET____DOT__bank_structure.__PVT__access) + ? ((0U == (IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__cache_driver_in_mem_read)) + ? ((0x80U & vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__0__KET____DOT__bank_structure.__PVT__data_unQual) + ? (0xffffff00U + | vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__0__KET____DOT__bank_structure.__PVT__data_unQual) + : (0xffU & vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__0__KET____DOT__bank_structure.__PVT__data_unQual)) + : ((1U == (IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__cache_driver_in_mem_read)) + ? ((0x8000U + & vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__0__KET____DOT__bank_structure.__PVT__data_unQual) + ? (0xffff0000U + | vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__0__KET____DOT__bank_structure.__PVT__data_unQual) + : (0xffffU + & vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__0__KET____DOT__bank_structure.__PVT__data_unQual)) + : ((5U == (IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__cache_driver_in_mem_read)) + ? (0xffffU + & vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__0__KET____DOT__bank_structure.__PVT__data_unQual) + : ((4U == (IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__cache_driver_in_mem_read)) + ? (0xffU + & vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__0__KET____DOT__bank_structure.__PVT__data_unQual) + : vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__0__KET____DOT__bank_structure.__PVT__data_unQual)))) + : 0U)),32); + vcdp->fullBit(c+355,((((IData)(vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__0__KET____DOT__bank_structure.__PVT__access) + & (vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__0__KET____DOT__bank_structure.__PVT__tag_use + == (0x1fffffU & (vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__0__KET____DOT__bank_addr + >> 0xbU)))) + & (IData)(vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__0__KET____DOT__bank_structure.__PVT__valid_use)))); + vcdp->fullBit(c+356,((1U & ((IData)(vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__0__KET____DOT__bank_structure.__PVT__data_structures__DOT__dirty_use_per_way) + >> (IData)(vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__0__KET____DOT__bank_structure.__PVT__data_structures__DOT__way_use_Qual))))); + vcdp->fullBus(c+357,(((vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__0__KET____DOT__bank_structure.__PVT__tag_use + << 0xbU) | (0x7c0U & vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__0__KET____DOT__bank_addr))),32); + vcdp->fullArray(c+358,(vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__0__KET____DOT__bank_structure.__Vcellout__data_structures__data_use),128); + vcdp->fullBus(c+362,(vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__0__KET____DOT__bank_structure.__PVT__tag_use),21); + vcdp->fullBit(c+363,(vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__0__KET____DOT__bank_structure.__PVT__valid_use)); + vcdp->fullBit(c+364,(vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__0__KET____DOT__bank_structure.__PVT__access)); + vcdp->fullBit(c+365,(vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__0__KET____DOT__bank_structure.__PVT__write_from_mem)); + vcdp->fullBit(c+366,(vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__0__KET____DOT__bank_structure.__PVT__miss)); + vcdp->fullBit(c+367,((2U == (IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__cache_driver_in_mem_read)))); + vcdp->fullBit(c+368,((0U == (IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__cache_driver_in_mem_read)))); + vcdp->fullBit(c+369,((1U == (IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__cache_driver_in_mem_read)))); + vcdp->fullBit(c+370,((5U == (IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__cache_driver_in_mem_read)))); + vcdp->fullBit(c+371,((4U == (IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__cache_driver_in_mem_read)))); + vcdp->fullBit(c+372,((2U == (IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__cache_driver_in_mem_write)))); + vcdp->fullBit(c+373,((0U == (IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__cache_driver_in_mem_write)))); + vcdp->fullBit(c+374,((1U == (IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__cache_driver_in_mem_write)))); + vcdp->fullBit(c+375,((0U == (3U & vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__0__KET____DOT__bank_addr)))); + vcdp->fullBit(c+376,((1U == (3U & vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__0__KET____DOT__bank_addr)))); + vcdp->fullBit(c+377,((2U == (3U & vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__0__KET____DOT__bank_addr)))); + vcdp->fullBit(c+378,((3U == (3U & vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__0__KET____DOT__bank_addr)))); + vcdp->fullBus(c+379,(vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__0__KET____DOT__bank_structure.__PVT__data_unQual),32); + vcdp->fullBus(c+380,(((0x80U & vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__0__KET____DOT__bank_structure.__PVT__data_unQual) + ? (0xffffff00U | vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__0__KET____DOT__bank_structure.__PVT__data_unQual) + : (0xffU & vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__0__KET____DOT__bank_structure.__PVT__data_unQual))),32); + vcdp->fullBus(c+381,(((0x8000U & vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__0__KET____DOT__bank_structure.__PVT__data_unQual) + ? (0xffff0000U | vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__0__KET____DOT__bank_structure.__PVT__data_unQual) + : (0xffffU & vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__0__KET____DOT__bank_structure.__PVT__data_unQual))),32); + vcdp->fullBus(c+382,((0xffU & vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__0__KET____DOT__bank_structure.__PVT__data_unQual)),32); + vcdp->fullBus(c+383,((0xffffU & vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__0__KET____DOT__bank_structure.__PVT__data_unQual)),32); + __Vtemp164[0U] = 0U; + __Vtemp164[1U] = 0U; + __Vtemp164[2U] = 0U; + __Vtemp164[3U] = 0U; + __Vtemp165[0U] = 0U; + __Vtemp165[1U] = 0U; + __Vtemp165[2U] = 0U; + __Vtemp165[3U] = 0U; + __Vtemp166[0U] = 0U; + __Vtemp166[1U] = 0U; + __Vtemp166[2U] = 0U; + __Vtemp166[3U] = 0U; + __Vtemp167[0U] = 0U; + __Vtemp167[1U] = 0U; + __Vtemp167[2U] = 0U; + __Vtemp167[3U] = 0U; + vcdp->fullBus(c+384,(((1U == (3U & vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__0__KET____DOT__bank_addr)) + ? (0xff00U & (__Vtemp164[ + (3U & (IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT__index_per_bank))] + << 8U)) + : ((2U == (3U & vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__0__KET____DOT__bank_addr)) + ? (0xff0000U & ( + __Vtemp165[ + (3U + & (IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT__index_per_bank))] + << 0x10U)) + : ((3U == (3U & vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__0__KET____DOT__bank_addr)) + ? (0xff000000U + & (__Vtemp166[ + (3U & (IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT__index_per_bank))] + << 0x18U)) + : __Vtemp167[ + (3U & (IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT__index_per_bank))])))),32); + __Vtemp168[0U] = 0U; + __Vtemp168[1U] = 0U; + __Vtemp168[2U] = 0U; + __Vtemp168[3U] = 0U; + __Vtemp169[0U] = 0U; + __Vtemp169[1U] = 0U; + __Vtemp169[2U] = 0U; + __Vtemp169[3U] = 0U; + vcdp->fullBus(c+385,(((2U == (3U & vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__0__KET____DOT__bank_addr)) + ? (0xffff0000U & (__Vtemp168[ + (3U + & (IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT__index_per_bank))] + << 0x10U)) + : __Vtemp169[(3U & (IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT__index_per_bank))])),32); + vcdp->fullBus(c+386,(vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__0__KET____DOT__bank_structure.__PVT__use_write_data),32); + vcdp->fullBus(c+387,(((0U == (IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__cache_driver_in_mem_read)) + ? ((0x80U & vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__0__KET____DOT__bank_structure.__PVT__data_unQual) + ? (0xffffff00U | vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__0__KET____DOT__bank_structure.__PVT__data_unQual) + : (0xffU & vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__0__KET____DOT__bank_structure.__PVT__data_unQual)) + : ((1U == (IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__cache_driver_in_mem_read)) + ? ((0x8000U & vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__0__KET____DOT__bank_structure.__PVT__data_unQual) + ? (0xffff0000U + | vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__0__KET____DOT__bank_structure.__PVT__data_unQual) + : (0xffffU & vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__0__KET____DOT__bank_structure.__PVT__data_unQual)) + : ((5U == (IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__cache_driver_in_mem_read)) + ? (0xffffU & vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__0__KET____DOT__bank_structure.__PVT__data_unQual) + : ((4U == (IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__cache_driver_in_mem_read)) + ? (0xffU + & vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__0__KET____DOT__bank_structure.__PVT__data_unQual) + : vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__0__KET____DOT__bank_structure.__PVT__data_unQual))))),32); + vcdp->fullBus(c+388,(vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__0__KET____DOT__bank_structure.__PVT__sb_mask),4); + vcdp->fullBus(c+389,(((0U == (3U & vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__0__KET____DOT__bank_addr)) + ? 3U : 0xcU)),4); + vcdp->fullBus(c+390,(vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__0__KET____DOT__bank_structure.__PVT__we),16); + vcdp->fullArray(c+391,(vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__0__KET____DOT__bank_structure.__PVT__data_write),128); + vcdp->fullBit(c+395,(vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__0__KET____DOT__bank_structure.__PVT__genblk1__BRA__0__KET____DOT__normal_write)); + vcdp->fullBit(c+396,(vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__0__KET____DOT__bank_structure.__PVT__genblk1__BRA__1__KET____DOT__normal_write)); + vcdp->fullBit(c+397,(vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__0__KET____DOT__bank_structure.__PVT__genblk1__BRA__2__KET____DOT__normal_write)); + vcdp->fullBit(c+398,(vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__0__KET____DOT__bank_structure.__PVT__genblk1__BRA__3__KET____DOT__normal_write)); + vcdp->fullQuad(c+399,(vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__0__KET____DOT__bank_structure.__PVT__data_structures__DOT__tag_use_per_way),42); + vcdp->fullArray(c+401,(vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__0__KET____DOT__bank_structure.__PVT__data_structures__DOT__data_use_per_way),256); + vcdp->fullBus(c+409,(vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__0__KET____DOT__bank_structure.__PVT__data_structures__DOT__valid_use_per_way),2); + vcdp->fullBus(c+410,(vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__0__KET____DOT__bank_structure.__PVT__data_structures__DOT__dirty_use_per_way),2); + vcdp->fullBus(c+411,(vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__0__KET____DOT__bank_structure.__PVT__data_structures__DOT__hit_per_way),2); + vcdp->fullBus(c+412,(vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__0__KET____DOT__bank_structure.__PVT__data_structures__DOT__we_per_way),32); + vcdp->fullArray(c+413,(vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__0__KET____DOT__bank_structure.__PVT__data_structures__DOT__data_write_per_way),256); + vcdp->fullBus(c+421,(vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__0__KET____DOT__bank_structure.__PVT__data_structures__DOT__write_from_mem_per_way),2); + vcdp->fullBit(c+422,(vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__0__KET____DOT__bank_structure.__PVT__data_structures__DOT__invalid_found)); + vcdp->fullBit(c+423,(vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__0__KET____DOT__bank_structure.__PVT__data_structures__DOT__way_index)); + vcdp->fullBit(c+424,(vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__0__KET____DOT__bank_structure.__PVT__data_structures__DOT__invalid_index)); + vcdp->fullBit(c+425,(vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__0__KET____DOT__bank_structure.__PVT__data_structures__DOT__way_use_Qual)); + vcdp->fullBus(c+426,((3U & (~ (IData)(vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__0__KET____DOT__bank_structure.__PVT__data_structures__DOT__valid_use_per_way)))),2); + vcdp->fullBit(c+427,(vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__0__KET____DOT__bank_structure.__PVT__data_structures__DOT__genblk1__DOT__way_indexing__DOT__found)); + vcdp->fullBus(c+428,((0xffffU & vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__0__KET____DOT__bank_structure.__PVT__data_structures__DOT__we_per_way)),16); + vcdp->fullBit(c+429,((1U & (IData)(vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__0__KET____DOT__bank_structure.__PVT__data_structures__DOT__write_from_mem_per_way)))); + __Vtemp170[0U] = vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__0__KET____DOT__bank_structure.__PVT__data_structures__DOT__data_write_per_way[0U]; + __Vtemp170[1U] = vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__0__KET____DOT__bank_structure.__PVT__data_structures__DOT__data_write_per_way[1U]; + __Vtemp170[2U] = vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__0__KET____DOT__bank_structure.__PVT__data_structures__DOT__data_write_per_way[2U]; + __Vtemp170[3U] = vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__0__KET____DOT__bank_structure.__PVT__data_structures__DOT__data_write_per_way[3U]; + vcdp->fullArray(c+430,(__Vtemp170),128); + vcdp->fullBit(c+434,(vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__0__KET____DOT__bank_structure.data_structures__DOT____Vcellout__each_way__BRA__0__KET____DOT__data_structures__dirty_use)); + vcdp->fullBit(c+435,((0U != (0xffffU & vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__0__KET____DOT__bank_structure.__PVT__data_structures__DOT__we_per_way)))); + vcdp->fullBit(c+436,((1U & (((~ (IData)(vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__0__KET____DOT__bank_structure.data_structures__DOT____Vcellout__each_way__BRA__0__KET____DOT__data_structures__dirty_use)) + & (0U != (0xffffU + & vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__0__KET____DOT__bank_structure.__PVT__data_structures__DOT__we_per_way))) + | (IData)(vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__0__KET____DOT__bank_structure.__PVT__data_structures__DOT__write_from_mem_per_way))))); + vcdp->fullBit(c+437,(((1U & (IData)(vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__0__KET____DOT__bank_structure.__PVT__data_structures__DOT__write_from_mem_per_way)) + ? 0U : (1U & (0U != + (0xffffU + & vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__0__KET____DOT__bank_structure.__PVT__data_structures__DOT__we_per_way)))))); + vcdp->fullBus(c+438,((0xffffU & (vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__0__KET____DOT__bank_structure.__PVT__data_structures__DOT__we_per_way + >> 0x10U))),16); + vcdp->fullBit(c+439,((1U & ((IData)(vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__0__KET____DOT__bank_structure.__PVT__data_structures__DOT__write_from_mem_per_way) + >> 1U)))); + __Vtemp171[0U] = vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__0__KET____DOT__bank_structure.__PVT__data_structures__DOT__data_write_per_way[4U]; + __Vtemp171[1U] = vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__0__KET____DOT__bank_structure.__PVT__data_structures__DOT__data_write_per_way[5U]; + __Vtemp171[2U] = vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__0__KET____DOT__bank_structure.__PVT__data_structures__DOT__data_write_per_way[6U]; + __Vtemp171[3U] = vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__0__KET____DOT__bank_structure.__PVT__data_structures__DOT__data_write_per_way[7U]; + vcdp->fullArray(c+440,(__Vtemp171),128); + vcdp->fullBit(c+444,(vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__0__KET____DOT__bank_structure.data_structures__DOT____Vcellout__each_way__BRA__1__KET____DOT__data_structures__dirty_use)); + vcdp->fullBit(c+445,((0U != (0xffffU & (vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__0__KET____DOT__bank_structure.__PVT__data_structures__DOT__we_per_way + >> 0x10U))))); + vcdp->fullBit(c+446,((1U & (((~ (IData)(vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__0__KET____DOT__bank_structure.data_structures__DOT____Vcellout__each_way__BRA__1__KET____DOT__data_structures__dirty_use)) + & (0U != (0xffffU + & (vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__0__KET____DOT__bank_structure.__PVT__data_structures__DOT__we_per_way + >> 0x10U)))) + | ((IData)(vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__0__KET____DOT__bank_structure.__PVT__data_structures__DOT__write_from_mem_per_way) + >> 1U))))); + vcdp->fullBit(c+447,(((2U & (IData)(vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__0__KET____DOT__bank_structure.__PVT__data_structures__DOT__write_from_mem_per_way)) + ? 0U : (1U & (0U != + (0xffffU + & (vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__0__KET____DOT__bank_structure.__PVT__data_structures__DOT__we_per_way + >> 0x10U))))))); + __Vtemp172[0U] = 0U; + __Vtemp172[1U] = 0U; + __Vtemp172[2U] = 0U; + __Vtemp172[3U] = 0U; + vcdp->fullBus(c+448,(__Vtemp172[(3U & ((IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT__index_per_bank) + >> 2U))]),32); + vcdp->fullBus(c+449,(((IData)(vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__1__KET____DOT__bank_structure.__PVT__access) + ? ((0U == (IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__cache_driver_in_mem_read)) + ? ((0x80U & vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__1__KET____DOT__bank_structure.__PVT__data_unQual) + ? (0xffffff00U + | vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__1__KET____DOT__bank_structure.__PVT__data_unQual) + : (0xffU & vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__1__KET____DOT__bank_structure.__PVT__data_unQual)) + : ((1U == (IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__cache_driver_in_mem_read)) + ? ((0x8000U + & vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__1__KET____DOT__bank_structure.__PVT__data_unQual) + ? (0xffff0000U + | vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__1__KET____DOT__bank_structure.__PVT__data_unQual) + : (0xffffU + & vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__1__KET____DOT__bank_structure.__PVT__data_unQual)) + : ((5U == (IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__cache_driver_in_mem_read)) + ? (0xffffU + & vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__1__KET____DOT__bank_structure.__PVT__data_unQual) + : ((4U == (IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__cache_driver_in_mem_read)) + ? (0xffU + & vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__1__KET____DOT__bank_structure.__PVT__data_unQual) + : vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__1__KET____DOT__bank_structure.__PVT__data_unQual)))) + : 0U)),32); + vcdp->fullBit(c+450,((((IData)(vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__1__KET____DOT__bank_structure.__PVT__access) + & (vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__1__KET____DOT__bank_structure.__PVT__tag_use + == (0x1fffffU & (vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__1__KET____DOT__bank_addr + >> 0xbU)))) + & (IData)(vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__1__KET____DOT__bank_structure.__PVT__valid_use)))); + vcdp->fullBit(c+451,((1U & ((IData)(vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__1__KET____DOT__bank_structure.__PVT__data_structures__DOT__dirty_use_per_way) + >> (IData)(vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__1__KET____DOT__bank_structure.__PVT__data_structures__DOT__way_use_Qual))))); + vcdp->fullBus(c+452,(((vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__1__KET____DOT__bank_structure.__PVT__tag_use + << 0xbU) | (0x7c0U & vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__1__KET____DOT__bank_addr))),32); + vcdp->fullArray(c+453,(vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__1__KET____DOT__bank_structure.__Vcellout__data_structures__data_use),128); + vcdp->fullBus(c+457,(vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__1__KET____DOT__bank_structure.__PVT__tag_use),21); + vcdp->fullBit(c+458,(vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__1__KET____DOT__bank_structure.__PVT__valid_use)); + vcdp->fullBit(c+459,(vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__1__KET____DOT__bank_structure.__PVT__access)); + vcdp->fullBit(c+460,(vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__1__KET____DOT__bank_structure.__PVT__write_from_mem)); + vcdp->fullBit(c+461,(vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__1__KET____DOT__bank_structure.__PVT__miss)); + vcdp->fullBit(c+462,((0U == (3U & vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__1__KET____DOT__bank_addr)))); + vcdp->fullBit(c+463,((1U == (3U & vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__1__KET____DOT__bank_addr)))); + vcdp->fullBit(c+464,((2U == (3U & vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__1__KET____DOT__bank_addr)))); + vcdp->fullBit(c+465,((3U == (3U & vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__1__KET____DOT__bank_addr)))); + vcdp->fullBus(c+466,(vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__1__KET____DOT__bank_structure.__PVT__data_unQual),32); + vcdp->fullBus(c+467,(((0x80U & vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__1__KET____DOT__bank_structure.__PVT__data_unQual) + ? (0xffffff00U | vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__1__KET____DOT__bank_structure.__PVT__data_unQual) + : (0xffU & vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__1__KET____DOT__bank_structure.__PVT__data_unQual))),32); + vcdp->fullBus(c+468,(((0x8000U & vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__1__KET____DOT__bank_structure.__PVT__data_unQual) + ? (0xffff0000U | vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__1__KET____DOT__bank_structure.__PVT__data_unQual) + : (0xffffU & vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__1__KET____DOT__bank_structure.__PVT__data_unQual))),32); + vcdp->fullBus(c+469,((0xffU & vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__1__KET____DOT__bank_structure.__PVT__data_unQual)),32); + vcdp->fullBus(c+470,((0xffffU & vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__1__KET____DOT__bank_structure.__PVT__data_unQual)),32); + __Vtemp173[0U] = 0U; + __Vtemp173[1U] = 0U; + __Vtemp173[2U] = 0U; + __Vtemp173[3U] = 0U; + __Vtemp174[0U] = 0U; + __Vtemp174[1U] = 0U; + __Vtemp174[2U] = 0U; + __Vtemp174[3U] = 0U; + __Vtemp175[0U] = 0U; + __Vtemp175[1U] = 0U; + __Vtemp175[2U] = 0U; + __Vtemp175[3U] = 0U; + __Vtemp176[0U] = 0U; + __Vtemp176[1U] = 0U; + __Vtemp176[2U] = 0U; + __Vtemp176[3U] = 0U; + vcdp->fullBus(c+471,(((1U == (3U & vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__1__KET____DOT__bank_addr)) + ? (0xff00U & (__Vtemp173[ + (3U & + ((IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT__index_per_bank) + >> 2U))] + << 8U)) + : ((2U == (3U & vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__1__KET____DOT__bank_addr)) + ? (0xff0000U & ( + __Vtemp174[ + (3U + & ((IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT__index_per_bank) + >> 2U))] + << 0x10U)) + : ((3U == (3U & vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__1__KET____DOT__bank_addr)) + ? (0xff000000U + & (__Vtemp175[ + (3U & + ((IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT__index_per_bank) + >> 2U))] + << 0x18U)) + : __Vtemp176[ + (3U & ((IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT__index_per_bank) + >> 2U))])))),32); + __Vtemp177[0U] = 0U; + __Vtemp177[1U] = 0U; + __Vtemp177[2U] = 0U; + __Vtemp177[3U] = 0U; + __Vtemp178[0U] = 0U; + __Vtemp178[1U] = 0U; + __Vtemp178[2U] = 0U; + __Vtemp178[3U] = 0U; + vcdp->fullBus(c+472,(((2U == (3U & vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__1__KET____DOT__bank_addr)) + ? (0xffff0000U & (__Vtemp177[ + (3U + & ((IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT__index_per_bank) + >> 2U))] + << 0x10U)) + : __Vtemp178[(3U & ((IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT__index_per_bank) + >> 2U))])),32); + vcdp->fullBus(c+473,(vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__1__KET____DOT__bank_structure.__PVT__use_write_data),32); + vcdp->fullBus(c+474,(((0U == (IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__cache_driver_in_mem_read)) + ? ((0x80U & vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__1__KET____DOT__bank_structure.__PVT__data_unQual) + ? (0xffffff00U | vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__1__KET____DOT__bank_structure.__PVT__data_unQual) + : (0xffU & vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__1__KET____DOT__bank_structure.__PVT__data_unQual)) + : ((1U == (IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__cache_driver_in_mem_read)) + ? ((0x8000U & vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__1__KET____DOT__bank_structure.__PVT__data_unQual) + ? (0xffff0000U + | vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__1__KET____DOT__bank_structure.__PVT__data_unQual) + : (0xffffU & vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__1__KET____DOT__bank_structure.__PVT__data_unQual)) + : ((5U == (IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__cache_driver_in_mem_read)) + ? (0xffffU & vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__1__KET____DOT__bank_structure.__PVT__data_unQual) + : ((4U == (IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__cache_driver_in_mem_read)) + ? (0xffU + & vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__1__KET____DOT__bank_structure.__PVT__data_unQual) + : vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__1__KET____DOT__bank_structure.__PVT__data_unQual))))),32); + vcdp->fullBus(c+475,(vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__1__KET____DOT__bank_structure.__PVT__sb_mask),4); + vcdp->fullBus(c+476,(((0U == (3U & vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__1__KET____DOT__bank_addr)) + ? 3U : 0xcU)),4); + vcdp->fullBus(c+477,(vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__1__KET____DOT__bank_structure.__PVT__we),16); + vcdp->fullArray(c+478,(vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__1__KET____DOT__bank_structure.__PVT__data_write),128); + vcdp->fullBit(c+482,(vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__1__KET____DOT__bank_structure.__PVT__genblk1__BRA__0__KET____DOT__normal_write)); + vcdp->fullBit(c+483,(vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__1__KET____DOT__bank_structure.__PVT__genblk1__BRA__1__KET____DOT__normal_write)); + vcdp->fullBit(c+484,(vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__1__KET____DOT__bank_structure.__PVT__genblk1__BRA__2__KET____DOT__normal_write)); + vcdp->fullBit(c+485,(vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__1__KET____DOT__bank_structure.__PVT__genblk1__BRA__3__KET____DOT__normal_write)); + vcdp->fullQuad(c+486,(vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__1__KET____DOT__bank_structure.__PVT__data_structures__DOT__tag_use_per_way),42); + vcdp->fullArray(c+488,(vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__1__KET____DOT__bank_structure.__PVT__data_structures__DOT__data_use_per_way),256); + vcdp->fullBus(c+496,(vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__1__KET____DOT__bank_structure.__PVT__data_structures__DOT__valid_use_per_way),2); + vcdp->fullBus(c+497,(vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__1__KET____DOT__bank_structure.__PVT__data_structures__DOT__dirty_use_per_way),2); + vcdp->fullBus(c+498,(vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__1__KET____DOT__bank_structure.__PVT__data_structures__DOT__hit_per_way),2); + vcdp->fullBus(c+499,(vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__1__KET____DOT__bank_structure.__PVT__data_structures__DOT__we_per_way),32); + vcdp->fullArray(c+500,(vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__1__KET____DOT__bank_structure.__PVT__data_structures__DOT__data_write_per_way),256); + vcdp->fullBus(c+508,(vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__1__KET____DOT__bank_structure.__PVT__data_structures__DOT__write_from_mem_per_way),2); + vcdp->fullBit(c+509,(vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__1__KET____DOT__bank_structure.__PVT__data_structures__DOT__invalid_found)); + vcdp->fullBit(c+510,(vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__1__KET____DOT__bank_structure.__PVT__data_structures__DOT__way_index)); + vcdp->fullBit(c+511,(vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__1__KET____DOT__bank_structure.__PVT__data_structures__DOT__invalid_index)); + vcdp->fullBit(c+512,(vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__1__KET____DOT__bank_structure.__PVT__data_structures__DOT__way_use_Qual)); + vcdp->fullBus(c+513,((3U & (~ (IData)(vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__1__KET____DOT__bank_structure.__PVT__data_structures__DOT__valid_use_per_way)))),2); + vcdp->fullBit(c+514,(vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__1__KET____DOT__bank_structure.__PVT__data_structures__DOT__genblk1__DOT__way_indexing__DOT__found)); + vcdp->fullBus(c+515,((0xffffU & vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__1__KET____DOT__bank_structure.__PVT__data_structures__DOT__we_per_way)),16); + vcdp->fullBit(c+516,((1U & (IData)(vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__1__KET____DOT__bank_structure.__PVT__data_structures__DOT__write_from_mem_per_way)))); + __Vtemp179[0U] = vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__1__KET____DOT__bank_structure.__PVT__data_structures__DOT__data_write_per_way[0U]; + __Vtemp179[1U] = vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__1__KET____DOT__bank_structure.__PVT__data_structures__DOT__data_write_per_way[1U]; + __Vtemp179[2U] = vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__1__KET____DOT__bank_structure.__PVT__data_structures__DOT__data_write_per_way[2U]; + __Vtemp179[3U] = vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__1__KET____DOT__bank_structure.__PVT__data_structures__DOT__data_write_per_way[3U]; + vcdp->fullArray(c+517,(__Vtemp179),128); + vcdp->fullBit(c+521,(vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__1__KET____DOT__bank_structure.data_structures__DOT____Vcellout__each_way__BRA__0__KET____DOT__data_structures__dirty_use)); + vcdp->fullBit(c+522,((0U != (0xffffU & vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__1__KET____DOT__bank_structure.__PVT__data_structures__DOT__we_per_way)))); + vcdp->fullBit(c+523,((1U & (((~ (IData)(vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__1__KET____DOT__bank_structure.data_structures__DOT____Vcellout__each_way__BRA__0__KET____DOT__data_structures__dirty_use)) + & (0U != (0xffffU + & vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__1__KET____DOT__bank_structure.__PVT__data_structures__DOT__we_per_way))) + | (IData)(vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__1__KET____DOT__bank_structure.__PVT__data_structures__DOT__write_from_mem_per_way))))); + vcdp->fullBit(c+524,(((1U & (IData)(vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__1__KET____DOT__bank_structure.__PVT__data_structures__DOT__write_from_mem_per_way)) + ? 0U : (1U & (0U != + (0xffffU + & vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__1__KET____DOT__bank_structure.__PVT__data_structures__DOT__we_per_way)))))); + vcdp->fullBus(c+525,((0xffffU & (vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__1__KET____DOT__bank_structure.__PVT__data_structures__DOT__we_per_way + >> 0x10U))),16); + vcdp->fullBit(c+526,((1U & ((IData)(vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__1__KET____DOT__bank_structure.__PVT__data_structures__DOT__write_from_mem_per_way) + >> 1U)))); + __Vtemp180[0U] = vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__1__KET____DOT__bank_structure.__PVT__data_structures__DOT__data_write_per_way[4U]; + __Vtemp180[1U] = vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__1__KET____DOT__bank_structure.__PVT__data_structures__DOT__data_write_per_way[5U]; + __Vtemp180[2U] = vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__1__KET____DOT__bank_structure.__PVT__data_structures__DOT__data_write_per_way[6U]; + __Vtemp180[3U] = vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__1__KET____DOT__bank_structure.__PVT__data_structures__DOT__data_write_per_way[7U]; + vcdp->fullArray(c+527,(__Vtemp180),128); + vcdp->fullBit(c+531,(vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__1__KET____DOT__bank_structure.data_structures__DOT____Vcellout__each_way__BRA__1__KET____DOT__data_structures__dirty_use)); + vcdp->fullBit(c+532,((0U != (0xffffU & (vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__1__KET____DOT__bank_structure.__PVT__data_structures__DOT__we_per_way + >> 0x10U))))); + vcdp->fullBit(c+533,((1U & (((~ (IData)(vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__1__KET____DOT__bank_structure.data_structures__DOT____Vcellout__each_way__BRA__1__KET____DOT__data_structures__dirty_use)) + & (0U != (0xffffU + & (vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__1__KET____DOT__bank_structure.__PVT__data_structures__DOT__we_per_way + >> 0x10U)))) + | ((IData)(vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__1__KET____DOT__bank_structure.__PVT__data_structures__DOT__write_from_mem_per_way) + >> 1U))))); + vcdp->fullBit(c+534,(((2U & (IData)(vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__1__KET____DOT__bank_structure.__PVT__data_structures__DOT__write_from_mem_per_way)) + ? 0U : (1U & (0U != + (0xffffU + & (vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__1__KET____DOT__bank_structure.__PVT__data_structures__DOT__we_per_way + >> 0x10U))))))); + __Vtemp181[0U] = 0U; + __Vtemp181[1U] = 0U; + __Vtemp181[2U] = 0U; + __Vtemp181[3U] = 0U; + vcdp->fullBus(c+535,(__Vtemp181[(3U & ((IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT__index_per_bank) + >> 4U))]),32); + vcdp->fullBus(c+536,(((IData)(vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__2__KET____DOT__bank_structure.__PVT__access) + ? ((0U == (IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__cache_driver_in_mem_read)) + ? ((0x80U & vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__2__KET____DOT__bank_structure.__PVT__data_unQual) + ? (0xffffff00U + | vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__2__KET____DOT__bank_structure.__PVT__data_unQual) + : (0xffU & vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__2__KET____DOT__bank_structure.__PVT__data_unQual)) + : ((1U == (IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__cache_driver_in_mem_read)) + ? ((0x8000U + & vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__2__KET____DOT__bank_structure.__PVT__data_unQual) + ? (0xffff0000U + | vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__2__KET____DOT__bank_structure.__PVT__data_unQual) + : (0xffffU + & vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__2__KET____DOT__bank_structure.__PVT__data_unQual)) + : ((5U == (IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__cache_driver_in_mem_read)) + ? (0xffffU + & vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__2__KET____DOT__bank_structure.__PVT__data_unQual) + : ((4U == (IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__cache_driver_in_mem_read)) + ? (0xffU + & vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__2__KET____DOT__bank_structure.__PVT__data_unQual) + : vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__2__KET____DOT__bank_structure.__PVT__data_unQual)))) + : 0U)),32); + vcdp->fullBit(c+537,((((IData)(vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__2__KET____DOT__bank_structure.__PVT__access) + & (vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__2__KET____DOT__bank_structure.__PVT__tag_use + == (0x1fffffU & (vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__2__KET____DOT__bank_addr + >> 0xbU)))) + & (IData)(vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__2__KET____DOT__bank_structure.__PVT__valid_use)))); + vcdp->fullBit(c+538,((1U & ((IData)(vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__2__KET____DOT__bank_structure.__PVT__data_structures__DOT__dirty_use_per_way) + >> (IData)(vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__2__KET____DOT__bank_structure.__PVT__data_structures__DOT__way_use_Qual))))); + vcdp->fullBus(c+539,(((vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__2__KET____DOT__bank_structure.__PVT__tag_use + << 0xbU) | (0x7c0U & vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__2__KET____DOT__bank_addr))),32); + vcdp->fullArray(c+540,(vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__2__KET____DOT__bank_structure.__Vcellout__data_structures__data_use),128); + vcdp->fullBus(c+544,(vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__2__KET____DOT__bank_structure.__PVT__tag_use),21); + vcdp->fullBit(c+545,(vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__2__KET____DOT__bank_structure.__PVT__valid_use)); + vcdp->fullBit(c+546,(vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__2__KET____DOT__bank_structure.__PVT__access)); + vcdp->fullBit(c+547,(vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__2__KET____DOT__bank_structure.__PVT__write_from_mem)); + vcdp->fullBit(c+548,(vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__2__KET____DOT__bank_structure.__PVT__miss)); + vcdp->fullBit(c+549,((0U == (3U & vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__2__KET____DOT__bank_addr)))); + vcdp->fullBit(c+550,((1U == (3U & vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__2__KET____DOT__bank_addr)))); + vcdp->fullBit(c+551,((2U == (3U & vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__2__KET____DOT__bank_addr)))); + vcdp->fullBit(c+552,((3U == (3U & vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__2__KET____DOT__bank_addr)))); + vcdp->fullBus(c+553,(vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__2__KET____DOT__bank_structure.__PVT__data_unQual),32); + vcdp->fullBus(c+554,(((0x80U & vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__2__KET____DOT__bank_structure.__PVT__data_unQual) + ? (0xffffff00U | vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__2__KET____DOT__bank_structure.__PVT__data_unQual) + : (0xffU & vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__2__KET____DOT__bank_structure.__PVT__data_unQual))),32); + vcdp->fullBus(c+555,(((0x8000U & vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__2__KET____DOT__bank_structure.__PVT__data_unQual) + ? (0xffff0000U | vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__2__KET____DOT__bank_structure.__PVT__data_unQual) + : (0xffffU & vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__2__KET____DOT__bank_structure.__PVT__data_unQual))),32); + vcdp->fullBus(c+556,((0xffU & vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__2__KET____DOT__bank_structure.__PVT__data_unQual)),32); + vcdp->fullBus(c+557,((0xffffU & vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__2__KET____DOT__bank_structure.__PVT__data_unQual)),32); + __Vtemp182[0U] = 0U; + __Vtemp182[1U] = 0U; + __Vtemp182[2U] = 0U; + __Vtemp182[3U] = 0U; + __Vtemp183[0U] = 0U; + __Vtemp183[1U] = 0U; + __Vtemp183[2U] = 0U; + __Vtemp183[3U] = 0U; + __Vtemp184[0U] = 0U; + __Vtemp184[1U] = 0U; + __Vtemp184[2U] = 0U; + __Vtemp184[3U] = 0U; + __Vtemp185[0U] = 0U; + __Vtemp185[1U] = 0U; + __Vtemp185[2U] = 0U; + __Vtemp185[3U] = 0U; + vcdp->fullBus(c+558,(((1U == (3U & vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__2__KET____DOT__bank_addr)) + ? (0xff00U & (__Vtemp182[ + (3U & + ((IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT__index_per_bank) + >> 4U))] + << 8U)) + : ((2U == (3U & vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__2__KET____DOT__bank_addr)) + ? (0xff0000U & ( + __Vtemp183[ + (3U + & ((IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT__index_per_bank) + >> 4U))] + << 0x10U)) + : ((3U == (3U & vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__2__KET____DOT__bank_addr)) + ? (0xff000000U + & (__Vtemp184[ + (3U & + ((IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT__index_per_bank) + >> 4U))] + << 0x18U)) + : __Vtemp185[ + (3U & ((IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT__index_per_bank) + >> 4U))])))),32); + __Vtemp186[0U] = 0U; + __Vtemp186[1U] = 0U; + __Vtemp186[2U] = 0U; + __Vtemp186[3U] = 0U; + __Vtemp187[0U] = 0U; + __Vtemp187[1U] = 0U; + __Vtemp187[2U] = 0U; + __Vtemp187[3U] = 0U; + vcdp->fullBus(c+559,(((2U == (3U & vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__2__KET____DOT__bank_addr)) + ? (0xffff0000U & (__Vtemp186[ + (3U + & ((IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT__index_per_bank) + >> 4U))] + << 0x10U)) + : __Vtemp187[(3U & ((IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT__index_per_bank) + >> 4U))])),32); + vcdp->fullBus(c+560,(vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__2__KET____DOT__bank_structure.__PVT__use_write_data),32); + vcdp->fullBus(c+561,(((0U == (IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__cache_driver_in_mem_read)) + ? ((0x80U & vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__2__KET____DOT__bank_structure.__PVT__data_unQual) + ? (0xffffff00U | vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__2__KET____DOT__bank_structure.__PVT__data_unQual) + : (0xffU & vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__2__KET____DOT__bank_structure.__PVT__data_unQual)) + : ((1U == (IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__cache_driver_in_mem_read)) + ? ((0x8000U & vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__2__KET____DOT__bank_structure.__PVT__data_unQual) + ? (0xffff0000U + | vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__2__KET____DOT__bank_structure.__PVT__data_unQual) + : (0xffffU & vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__2__KET____DOT__bank_structure.__PVT__data_unQual)) + : ((5U == (IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__cache_driver_in_mem_read)) + ? (0xffffU & vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__2__KET____DOT__bank_structure.__PVT__data_unQual) + : ((4U == (IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__cache_driver_in_mem_read)) + ? (0xffU + & vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__2__KET____DOT__bank_structure.__PVT__data_unQual) + : vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__2__KET____DOT__bank_structure.__PVT__data_unQual))))),32); + vcdp->fullBus(c+562,(vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__2__KET____DOT__bank_structure.__PVT__sb_mask),4); + vcdp->fullBus(c+563,(((0U == (3U & vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__2__KET____DOT__bank_addr)) + ? 3U : 0xcU)),4); + vcdp->fullBus(c+564,(vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__2__KET____DOT__bank_structure.__PVT__we),16); + vcdp->fullArray(c+565,(vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__2__KET____DOT__bank_structure.__PVT__data_write),128); + vcdp->fullBit(c+569,(vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__2__KET____DOT__bank_structure.__PVT__genblk1__BRA__0__KET____DOT__normal_write)); + vcdp->fullBit(c+570,(vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__2__KET____DOT__bank_structure.__PVT__genblk1__BRA__1__KET____DOT__normal_write)); + vcdp->fullBit(c+571,(vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__2__KET____DOT__bank_structure.__PVT__genblk1__BRA__2__KET____DOT__normal_write)); + vcdp->fullBit(c+572,(vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__2__KET____DOT__bank_structure.__PVT__genblk1__BRA__3__KET____DOT__normal_write)); + vcdp->fullQuad(c+573,(vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__2__KET____DOT__bank_structure.__PVT__data_structures__DOT__tag_use_per_way),42); + vcdp->fullArray(c+575,(vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__2__KET____DOT__bank_structure.__PVT__data_structures__DOT__data_use_per_way),256); + vcdp->fullBus(c+583,(vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__2__KET____DOT__bank_structure.__PVT__data_structures__DOT__valid_use_per_way),2); + vcdp->fullBus(c+584,(vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__2__KET____DOT__bank_structure.__PVT__data_structures__DOT__dirty_use_per_way),2); + vcdp->fullBus(c+585,(vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__2__KET____DOT__bank_structure.__PVT__data_structures__DOT__hit_per_way),2); + vcdp->fullBus(c+586,(vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__2__KET____DOT__bank_structure.__PVT__data_structures__DOT__we_per_way),32); + vcdp->fullArray(c+587,(vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__2__KET____DOT__bank_structure.__PVT__data_structures__DOT__data_write_per_way),256); + vcdp->fullBus(c+595,(vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__2__KET____DOT__bank_structure.__PVT__data_structures__DOT__write_from_mem_per_way),2); + vcdp->fullBit(c+596,(vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__2__KET____DOT__bank_structure.__PVT__data_structures__DOT__invalid_found)); + vcdp->fullBit(c+597,(vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__2__KET____DOT__bank_structure.__PVT__data_structures__DOT__way_index)); + vcdp->fullBit(c+598,(vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__2__KET____DOT__bank_structure.__PVT__data_structures__DOT__invalid_index)); + vcdp->fullBit(c+599,(vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__2__KET____DOT__bank_structure.__PVT__data_structures__DOT__way_use_Qual)); + vcdp->fullBus(c+600,((3U & (~ (IData)(vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__2__KET____DOT__bank_structure.__PVT__data_structures__DOT__valid_use_per_way)))),2); + vcdp->fullBit(c+601,(vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__2__KET____DOT__bank_structure.__PVT__data_structures__DOT__genblk1__DOT__way_indexing__DOT__found)); + vcdp->fullBus(c+602,((0xffffU & vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__2__KET____DOT__bank_structure.__PVT__data_structures__DOT__we_per_way)),16); + vcdp->fullBit(c+603,((1U & (IData)(vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__2__KET____DOT__bank_structure.__PVT__data_structures__DOT__write_from_mem_per_way)))); + __Vtemp188[0U] = vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__2__KET____DOT__bank_structure.__PVT__data_structures__DOT__data_write_per_way[0U]; + __Vtemp188[1U] = vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__2__KET____DOT__bank_structure.__PVT__data_structures__DOT__data_write_per_way[1U]; + __Vtemp188[2U] = vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__2__KET____DOT__bank_structure.__PVT__data_structures__DOT__data_write_per_way[2U]; + __Vtemp188[3U] = vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__2__KET____DOT__bank_structure.__PVT__data_structures__DOT__data_write_per_way[3U]; + vcdp->fullArray(c+604,(__Vtemp188),128); + vcdp->fullBit(c+608,(vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__2__KET____DOT__bank_structure.data_structures__DOT____Vcellout__each_way__BRA__0__KET____DOT__data_structures__dirty_use)); + vcdp->fullBit(c+609,((0U != (0xffffU & vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__2__KET____DOT__bank_structure.__PVT__data_structures__DOT__we_per_way)))); + vcdp->fullBit(c+610,((1U & (((~ (IData)(vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__2__KET____DOT__bank_structure.data_structures__DOT____Vcellout__each_way__BRA__0__KET____DOT__data_structures__dirty_use)) + & (0U != (0xffffU + & vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__2__KET____DOT__bank_structure.__PVT__data_structures__DOT__we_per_way))) + | (IData)(vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__2__KET____DOT__bank_structure.__PVT__data_structures__DOT__write_from_mem_per_way))))); + vcdp->fullBit(c+611,(((1U & (IData)(vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__2__KET____DOT__bank_structure.__PVT__data_structures__DOT__write_from_mem_per_way)) + ? 0U : (1U & (0U != + (0xffffU + & vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__2__KET____DOT__bank_structure.__PVT__data_structures__DOT__we_per_way)))))); + vcdp->fullBus(c+612,((0xffffU & (vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__2__KET____DOT__bank_structure.__PVT__data_structures__DOT__we_per_way + >> 0x10U))),16); + vcdp->fullBit(c+613,((1U & ((IData)(vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__2__KET____DOT__bank_structure.__PVT__data_structures__DOT__write_from_mem_per_way) + >> 1U)))); + __Vtemp189[0U] = vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__2__KET____DOT__bank_structure.__PVT__data_structures__DOT__data_write_per_way[4U]; + __Vtemp189[1U] = vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__2__KET____DOT__bank_structure.__PVT__data_structures__DOT__data_write_per_way[5U]; + __Vtemp189[2U] = vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__2__KET____DOT__bank_structure.__PVT__data_structures__DOT__data_write_per_way[6U]; + __Vtemp189[3U] = vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__2__KET____DOT__bank_structure.__PVT__data_structures__DOT__data_write_per_way[7U]; + vcdp->fullArray(c+614,(__Vtemp189),128); + vcdp->fullBit(c+618,(vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__2__KET____DOT__bank_structure.data_structures__DOT____Vcellout__each_way__BRA__1__KET____DOT__data_structures__dirty_use)); + vcdp->fullBit(c+619,((0U != (0xffffU & (vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__2__KET____DOT__bank_structure.__PVT__data_structures__DOT__we_per_way + >> 0x10U))))); + vcdp->fullBit(c+620,((1U & (((~ (IData)(vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__2__KET____DOT__bank_structure.data_structures__DOT____Vcellout__each_way__BRA__1__KET____DOT__data_structures__dirty_use)) + & (0U != (0xffffU + & (vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__2__KET____DOT__bank_structure.__PVT__data_structures__DOT__we_per_way + >> 0x10U)))) + | ((IData)(vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__2__KET____DOT__bank_structure.__PVT__data_structures__DOT__write_from_mem_per_way) + >> 1U))))); + vcdp->fullBit(c+621,(((2U & (IData)(vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__2__KET____DOT__bank_structure.__PVT__data_structures__DOT__write_from_mem_per_way)) + ? 0U : (1U & (0U != + (0xffffU + & (vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__2__KET____DOT__bank_structure.__PVT__data_structures__DOT__we_per_way + >> 0x10U))))))); + __Vtemp190[0U] = 0U; + __Vtemp190[1U] = 0U; + __Vtemp190[2U] = 0U; + __Vtemp190[3U] = 0U; + vcdp->fullBus(c+622,(__Vtemp190[(3U & ((IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT__index_per_bank) + >> 6U))]),32); + vcdp->fullBus(c+623,(((IData)(vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__3__KET____DOT__bank_structure.__PVT__access) + ? ((0U == (IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__cache_driver_in_mem_read)) + ? ((0x80U & vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__3__KET____DOT__bank_structure.__PVT__data_unQual) + ? (0xffffff00U + | vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__3__KET____DOT__bank_structure.__PVT__data_unQual) + : (0xffU & vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__3__KET____DOT__bank_structure.__PVT__data_unQual)) + : ((1U == (IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__cache_driver_in_mem_read)) + ? ((0x8000U + & vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__3__KET____DOT__bank_structure.__PVT__data_unQual) + ? (0xffff0000U + | vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__3__KET____DOT__bank_structure.__PVT__data_unQual) + : (0xffffU + & vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__3__KET____DOT__bank_structure.__PVT__data_unQual)) + : ((5U == (IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__cache_driver_in_mem_read)) + ? (0xffffU + & vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__3__KET____DOT__bank_structure.__PVT__data_unQual) + : ((4U == (IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__cache_driver_in_mem_read)) + ? (0xffU + & vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__3__KET____DOT__bank_structure.__PVT__data_unQual) + : vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__3__KET____DOT__bank_structure.__PVT__data_unQual)))) + : 0U)),32); + vcdp->fullBit(c+624,((((IData)(vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__3__KET____DOT__bank_structure.__PVT__access) + & (vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__3__KET____DOT__bank_structure.__PVT__tag_use + == (0x1fffffU & (vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__3__KET____DOT__bank_addr + >> 0xbU)))) + & (IData)(vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__3__KET____DOT__bank_structure.__PVT__valid_use)))); + vcdp->fullBit(c+625,((1U & ((IData)(vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__3__KET____DOT__bank_structure.__PVT__data_structures__DOT__dirty_use_per_way) + >> (IData)(vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__3__KET____DOT__bank_structure.__PVT__data_structures__DOT__way_use_Qual))))); + vcdp->fullBus(c+626,(((vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__3__KET____DOT__bank_structure.__PVT__tag_use + << 0xbU) | (0x7c0U & vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__3__KET____DOT__bank_addr))),32); + vcdp->fullArray(c+627,(vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__3__KET____DOT__bank_structure.__Vcellout__data_structures__data_use),128); + vcdp->fullBus(c+631,(vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__3__KET____DOT__bank_structure.__PVT__tag_use),21); + vcdp->fullBit(c+632,(vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__3__KET____DOT__bank_structure.__PVT__valid_use)); + vcdp->fullBit(c+633,(vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__3__KET____DOT__bank_structure.__PVT__access)); + vcdp->fullBit(c+634,(vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__3__KET____DOT__bank_structure.__PVT__write_from_mem)); + vcdp->fullBit(c+635,(vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__3__KET____DOT__bank_structure.__PVT__miss)); + vcdp->fullBit(c+636,((0U == (3U & vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__3__KET____DOT__bank_addr)))); + vcdp->fullBit(c+637,((1U == (3U & vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__3__KET____DOT__bank_addr)))); + vcdp->fullBit(c+638,((2U == (3U & vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__3__KET____DOT__bank_addr)))); + vcdp->fullBit(c+639,((3U == (3U & vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__3__KET____DOT__bank_addr)))); + vcdp->fullBus(c+640,(vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__3__KET____DOT__bank_structure.__PVT__data_unQual),32); + vcdp->fullBus(c+641,(((0x80U & vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__3__KET____DOT__bank_structure.__PVT__data_unQual) + ? (0xffffff00U | vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__3__KET____DOT__bank_structure.__PVT__data_unQual) + : (0xffU & vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__3__KET____DOT__bank_structure.__PVT__data_unQual))),32); + vcdp->fullBus(c+642,(((0x8000U & vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__3__KET____DOT__bank_structure.__PVT__data_unQual) + ? (0xffff0000U | vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__3__KET____DOT__bank_structure.__PVT__data_unQual) + : (0xffffU & vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__3__KET____DOT__bank_structure.__PVT__data_unQual))),32); + vcdp->fullBus(c+643,((0xffU & vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__3__KET____DOT__bank_structure.__PVT__data_unQual)),32); + vcdp->fullBus(c+644,((0xffffU & vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__3__KET____DOT__bank_structure.__PVT__data_unQual)),32); + __Vtemp191[0U] = 0U; + __Vtemp191[1U] = 0U; + __Vtemp191[2U] = 0U; + __Vtemp191[3U] = 0U; + __Vtemp192[0U] = 0U; + __Vtemp192[1U] = 0U; + __Vtemp192[2U] = 0U; + __Vtemp192[3U] = 0U; + __Vtemp193[0U] = 0U; + __Vtemp193[1U] = 0U; + __Vtemp193[2U] = 0U; + __Vtemp193[3U] = 0U; + __Vtemp194[0U] = 0U; + __Vtemp194[1U] = 0U; + __Vtemp194[2U] = 0U; + __Vtemp194[3U] = 0U; + vcdp->fullBus(c+645,(((1U == (3U & vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__3__KET____DOT__bank_addr)) + ? (0xff00U & (__Vtemp191[ + (3U & + ((IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT__index_per_bank) + >> 6U))] + << 8U)) + : ((2U == (3U & vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__3__KET____DOT__bank_addr)) + ? (0xff0000U & ( + __Vtemp192[ + (3U + & ((IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT__index_per_bank) + >> 6U))] + << 0x10U)) + : ((3U == (3U & vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__3__KET____DOT__bank_addr)) + ? (0xff000000U + & (__Vtemp193[ + (3U & + ((IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT__index_per_bank) + >> 6U))] + << 0x18U)) + : __Vtemp194[ + (3U & ((IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT__index_per_bank) + >> 6U))])))),32); + __Vtemp195[0U] = 0U; + __Vtemp195[1U] = 0U; + __Vtemp195[2U] = 0U; + __Vtemp195[3U] = 0U; + __Vtemp196[0U] = 0U; + __Vtemp196[1U] = 0U; + __Vtemp196[2U] = 0U; + __Vtemp196[3U] = 0U; + vcdp->fullBus(c+646,(((2U == (3U & vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__3__KET____DOT__bank_addr)) + ? (0xffff0000U & (__Vtemp195[ + (3U + & ((IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT__index_per_bank) + >> 6U))] + << 0x10U)) + : __Vtemp196[(3U & ((IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT__index_per_bank) + >> 6U))])),32); + vcdp->fullBus(c+647,(vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__3__KET____DOT__bank_structure.__PVT__use_write_data),32); + vcdp->fullBus(c+648,(((0U == (IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__cache_driver_in_mem_read)) + ? ((0x80U & vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__3__KET____DOT__bank_structure.__PVT__data_unQual) + ? (0xffffff00U | vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__3__KET____DOT__bank_structure.__PVT__data_unQual) + : (0xffU & vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__3__KET____DOT__bank_structure.__PVT__data_unQual)) + : ((1U == (IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__cache_driver_in_mem_read)) + ? ((0x8000U & vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__3__KET____DOT__bank_structure.__PVT__data_unQual) + ? (0xffff0000U + | vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__3__KET____DOT__bank_structure.__PVT__data_unQual) + : (0xffffU & vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__3__KET____DOT__bank_structure.__PVT__data_unQual)) + : ((5U == (IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__cache_driver_in_mem_read)) + ? (0xffffU & vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__3__KET____DOT__bank_structure.__PVT__data_unQual) + : ((4U == (IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__cache_driver_in_mem_read)) + ? (0xffU + & vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__3__KET____DOT__bank_structure.__PVT__data_unQual) + : vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__3__KET____DOT__bank_structure.__PVT__data_unQual))))),32); + vcdp->fullBus(c+649,(vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__3__KET____DOT__bank_structure.__PVT__sb_mask),4); + vcdp->fullBus(c+650,(((0U == (3U & vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__3__KET____DOT__bank_addr)) + ? 3U : 0xcU)),4); + vcdp->fullBus(c+651,(vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__3__KET____DOT__bank_structure.__PVT__we),16); + vcdp->fullArray(c+652,(vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__3__KET____DOT__bank_structure.__PVT__data_write),128); + vcdp->fullBit(c+656,(vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__3__KET____DOT__bank_structure.__PVT__genblk1__BRA__0__KET____DOT__normal_write)); + vcdp->fullBit(c+657,(vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__3__KET____DOT__bank_structure.__PVT__genblk1__BRA__1__KET____DOT__normal_write)); + vcdp->fullBit(c+658,(vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__3__KET____DOT__bank_structure.__PVT__genblk1__BRA__2__KET____DOT__normal_write)); + vcdp->fullBit(c+659,(vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__3__KET____DOT__bank_structure.__PVT__genblk1__BRA__3__KET____DOT__normal_write)); + vcdp->fullQuad(c+660,(vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__3__KET____DOT__bank_structure.__PVT__data_structures__DOT__tag_use_per_way),42); + vcdp->fullArray(c+662,(vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__3__KET____DOT__bank_structure.__PVT__data_structures__DOT__data_use_per_way),256); + vcdp->fullBus(c+670,(vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__3__KET____DOT__bank_structure.__PVT__data_structures__DOT__valid_use_per_way),2); + vcdp->fullBus(c+671,(vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__3__KET____DOT__bank_structure.__PVT__data_structures__DOT__dirty_use_per_way),2); + vcdp->fullBus(c+672,(vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__3__KET____DOT__bank_structure.__PVT__data_structures__DOT__hit_per_way),2); + vcdp->fullBus(c+673,(vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__3__KET____DOT__bank_structure.__PVT__data_structures__DOT__we_per_way),32); + vcdp->fullArray(c+674,(vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__3__KET____DOT__bank_structure.__PVT__data_structures__DOT__data_write_per_way),256); + vcdp->fullBus(c+682,(vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__3__KET____DOT__bank_structure.__PVT__data_structures__DOT__write_from_mem_per_way),2); + vcdp->fullBit(c+683,(vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__3__KET____DOT__bank_structure.__PVT__data_structures__DOT__invalid_found)); + vcdp->fullBit(c+684,(vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__3__KET____DOT__bank_structure.__PVT__data_structures__DOT__way_index)); + vcdp->fullBit(c+685,(vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__3__KET____DOT__bank_structure.__PVT__data_structures__DOT__invalid_index)); + vcdp->fullBit(c+686,(vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__3__KET____DOT__bank_structure.__PVT__data_structures__DOT__way_use_Qual)); + vcdp->fullBus(c+687,((3U & (~ (IData)(vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__3__KET____DOT__bank_structure.__PVT__data_structures__DOT__valid_use_per_way)))),2); + vcdp->fullBit(c+688,(vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__3__KET____DOT__bank_structure.__PVT__data_structures__DOT__genblk1__DOT__way_indexing__DOT__found)); + vcdp->fullBus(c+689,((0xffffU & vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__3__KET____DOT__bank_structure.__PVT__data_structures__DOT__we_per_way)),16); + vcdp->fullBit(c+690,((1U & (IData)(vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__3__KET____DOT__bank_structure.__PVT__data_structures__DOT__write_from_mem_per_way)))); + __Vtemp197[0U] = vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__3__KET____DOT__bank_structure.__PVT__data_structures__DOT__data_write_per_way[0U]; + __Vtemp197[1U] = vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__3__KET____DOT__bank_structure.__PVT__data_structures__DOT__data_write_per_way[1U]; + __Vtemp197[2U] = vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__3__KET____DOT__bank_structure.__PVT__data_structures__DOT__data_write_per_way[2U]; + __Vtemp197[3U] = vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__3__KET____DOT__bank_structure.__PVT__data_structures__DOT__data_write_per_way[3U]; + vcdp->fullArray(c+691,(__Vtemp197),128); + vcdp->fullBit(c+695,(vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__3__KET____DOT__bank_structure.data_structures__DOT____Vcellout__each_way__BRA__0__KET____DOT__data_structures__dirty_use)); + vcdp->fullBit(c+696,((0U != (0xffffU & vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__3__KET____DOT__bank_structure.__PVT__data_structures__DOT__we_per_way)))); + vcdp->fullBit(c+697,((1U & (((~ (IData)(vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__3__KET____DOT__bank_structure.data_structures__DOT____Vcellout__each_way__BRA__0__KET____DOT__data_structures__dirty_use)) + & (0U != (0xffffU + & vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__3__KET____DOT__bank_structure.__PVT__data_structures__DOT__we_per_way))) + | (IData)(vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__3__KET____DOT__bank_structure.__PVT__data_structures__DOT__write_from_mem_per_way))))); + vcdp->fullBit(c+698,(((1U & (IData)(vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__3__KET____DOT__bank_structure.__PVT__data_structures__DOT__write_from_mem_per_way)) + ? 0U : (1U & (0U != + (0xffffU + & vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__3__KET____DOT__bank_structure.__PVT__data_structures__DOT__we_per_way)))))); + vcdp->fullBus(c+699,((0xffffU & (vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__3__KET____DOT__bank_structure.__PVT__data_structures__DOT__we_per_way + >> 0x10U))),16); + vcdp->fullBit(c+700,((1U & ((IData)(vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__3__KET____DOT__bank_structure.__PVT__data_structures__DOT__write_from_mem_per_way) + >> 1U)))); + __Vtemp198[0U] = vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__3__KET____DOT__bank_structure.__PVT__data_structures__DOT__data_write_per_way[4U]; + __Vtemp198[1U] = vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__3__KET____DOT__bank_structure.__PVT__data_structures__DOT__data_write_per_way[5U]; + __Vtemp198[2U] = vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__3__KET____DOT__bank_structure.__PVT__data_structures__DOT__data_write_per_way[6U]; + __Vtemp198[3U] = vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__3__KET____DOT__bank_structure.__PVT__data_structures__DOT__data_write_per_way[7U]; + vcdp->fullArray(c+701,(__Vtemp198),128); + vcdp->fullBit(c+705,(vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__3__KET____DOT__bank_structure.data_structures__DOT____Vcellout__each_way__BRA__1__KET____DOT__data_structures__dirty_use)); + vcdp->fullBit(c+706,((0U != (0xffffU & (vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__3__KET____DOT__bank_structure.__PVT__data_structures__DOT__we_per_way + >> 0x10U))))); + vcdp->fullBit(c+707,((1U & (((~ (IData)(vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__3__KET____DOT__bank_structure.data_structures__DOT____Vcellout__each_way__BRA__1__KET____DOT__data_structures__dirty_use)) + & (0U != (0xffffU + & (vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__3__KET____DOT__bank_structure.__PVT__data_structures__DOT__we_per_way + >> 0x10U)))) + | ((IData)(vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__3__KET____DOT__bank_structure.__PVT__data_structures__DOT__write_from_mem_per_way) + >> 1U))))); + vcdp->fullBit(c+708,(((2U & (IData)(vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__3__KET____DOT__bank_structure.__PVT__data_structures__DOT__write_from_mem_per_way)) + ? 0U : (1U & (0U != + (0xffffU + & (vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__3__KET____DOT__bank_structure.__PVT__data_structures__DOT__we_per_way + >> 0x10U))))))); + vcdp->fullBit(c+709,(((1U == (IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT__state)) + & (0U != (IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT__eviction_wb))))); + vcdp->fullBit(c+710,(((1U == (IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__state)) + & ((IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__data_structures__DOT__dirty_use_per_way) + >> (IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__data_structures__DOT__way_use_Qual))))); + vcdp->fullBus(c+711,(((IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__threads_serviced_per_bank) + ? vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__new_final_data_read + : vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__final_data_read)),32); + vcdp->fullBit(c+712,(((IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__new_stored_valid) + | (0U != (IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__state))))); + vcdp->fullBit(c+713,(((0U != (IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__vx_priority_encoder_sm__DOT__more_than_one_valid)) + | ((0U != (IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT__new_stored_valid)) + | (0U != (IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT__state)))))); + vcdp->fullBit(c+714,(((0U != (IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT__new_stored_valid)) + | (0U != (IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT__state))))); + vcdp->fullBit(c+715,((1U & ((~ ((0U != (IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT__new_stored_valid)) + | (0U != (IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT__state)))) + & (IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__cache_driver_in_valid))))); + vcdp->fullBus(c+716,(((0U == (IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__vx_priority_encoder_sm__DOT__left_requests)) + ? ((IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__orig_in_valid) + & (~ (IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__vx_priority_encoder_sm__DOT__serviced_qual))) + : ((IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__vx_priority_encoder_sm__DOT__left_requests) + & (~ (IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__vx_priority_encoder_sm__DOT__serviced_qual))))),4); + __Vtemp201[0U] = ((IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__genblk2__BRA__0__KET____DOT__shm_write) + ? 0U : vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__genblk2__BRA__0__KET____DOT__vx_shared_memory_block__DOT__shared_memory + [(0x7fU & vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__block_addr)][0U]); + __Vtemp201[1U] = ((IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__genblk2__BRA__0__KET____DOT__shm_write) + ? 0U : vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__genblk2__BRA__0__KET____DOT__vx_shared_memory_block__DOT__shared_memory + [(0x7fU & vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__block_addr)][1U]); + __Vtemp201[2U] = ((IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__genblk2__BRA__0__KET____DOT__shm_write) + ? 0U : vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__genblk2__BRA__0__KET____DOT__vx_shared_memory_block__DOT__shared_memory + [(0x7fU & vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__block_addr)][2U]); + __Vtemp201[3U] = ((IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__genblk2__BRA__0__KET____DOT__shm_write) + ? 0U : vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__genblk2__BRA__0__KET____DOT__vx_shared_memory_block__DOT__shared_memory + [(0x7fU & vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__block_addr)][3U]); + vcdp->fullArray(c+717,(__Vtemp201),128); + __Vtemp204[0U] = ((IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__genblk2__BRA__1__KET____DOT__shm_write) + ? 0U : vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__genblk2__BRA__1__KET____DOT__vx_shared_memory_block__DOT__shared_memory + [(0x7fU & (vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__block_addr + >> 7U))][0U]); + __Vtemp204[1U] = ((IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__genblk2__BRA__1__KET____DOT__shm_write) + ? 0U : vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__genblk2__BRA__1__KET____DOT__vx_shared_memory_block__DOT__shared_memory + [(0x7fU & (vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__block_addr + >> 7U))][1U]); + __Vtemp204[2U] = ((IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__genblk2__BRA__1__KET____DOT__shm_write) + ? 0U : vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__genblk2__BRA__1__KET____DOT__vx_shared_memory_block__DOT__shared_memory + [(0x7fU & (vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__block_addr + >> 7U))][2U]); + __Vtemp204[3U] = ((IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__genblk2__BRA__1__KET____DOT__shm_write) + ? 0U : vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__genblk2__BRA__1__KET____DOT__vx_shared_memory_block__DOT__shared_memory + [(0x7fU & (vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__block_addr + >> 7U))][3U]); + vcdp->fullArray(c+721,(__Vtemp204),128); + __Vtemp207[0U] = ((IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__genblk2__BRA__2__KET____DOT__shm_write) + ? 0U : vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__genblk2__BRA__2__KET____DOT__vx_shared_memory_block__DOT__shared_memory + [(0x7fU & (vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__block_addr + >> 0xeU))][0U]); + __Vtemp207[1U] = ((IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__genblk2__BRA__2__KET____DOT__shm_write) + ? 0U : vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__genblk2__BRA__2__KET____DOT__vx_shared_memory_block__DOT__shared_memory + [(0x7fU & (vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__block_addr + >> 0xeU))][1U]); + __Vtemp207[2U] = ((IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__genblk2__BRA__2__KET____DOT__shm_write) + ? 0U : vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__genblk2__BRA__2__KET____DOT__vx_shared_memory_block__DOT__shared_memory + [(0x7fU & (vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__block_addr + >> 0xeU))][2U]); + __Vtemp207[3U] = ((IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__genblk2__BRA__2__KET____DOT__shm_write) + ? 0U : vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__genblk2__BRA__2__KET____DOT__vx_shared_memory_block__DOT__shared_memory + [(0x7fU & (vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__block_addr + >> 0xeU))][3U]); + vcdp->fullArray(c+725,(__Vtemp207),128); + __Vtemp210[0U] = ((IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__genblk2__BRA__3__KET____DOT__shm_write) + ? 0U : vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__genblk2__BRA__3__KET____DOT__vx_shared_memory_block__DOT__shared_memory + [(0x7fU & (vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__block_addr + >> 0x15U))][0U]); + __Vtemp210[1U] = ((IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__genblk2__BRA__3__KET____DOT__shm_write) + ? 0U : vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__genblk2__BRA__3__KET____DOT__vx_shared_memory_block__DOT__shared_memory + [(0x7fU & (vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__block_addr + >> 0x15U))][1U]); + __Vtemp210[2U] = ((IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__genblk2__BRA__3__KET____DOT__shm_write) + ? 0U : vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__genblk2__BRA__3__KET____DOT__vx_shared_memory_block__DOT__shared_memory + [(0x7fU & (vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__block_addr + >> 0x15U))][2U]); + __Vtemp210[3U] = ((IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__genblk2__BRA__3__KET____DOT__shm_write) + ? 0U : vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__genblk2__BRA__3__KET____DOT__vx_shared_memory_block__DOT__shared_memory + [(0x7fU & (vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__block_addr + >> 0x15U))][3U]); + vcdp->fullArray(c+729,(__Vtemp210),128); + vcdp->fullBit(c+733,(((2U == (IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT__state)) + & (0U == (IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT__new_state))))); + vcdp->fullBit(c+734,(((2U == (IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__state)) + & (0U == (IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__new_state))))); + vcdp->fullBus(c+735,(vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__tag + [(0x1fU & (vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_addr + >> 4U))]),23); + __Vtemp211[0U] = vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__data + [(0x1fU & (vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_addr + >> 4U))][0U]; + __Vtemp211[1U] = vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__data + [(0x1fU & (vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_addr + >> 4U))][1U]; + __Vtemp211[2U] = vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__data + [(0x1fU & (vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_addr + >> 4U))][2U]; + __Vtemp211[3U] = vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__data + [(0x1fU & (vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_addr + >> 4U))][3U]; + vcdp->fullArray(c+736,(__Vtemp211),128); + vcdp->fullBit(c+740,(vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__valid + [(0x1fU & (vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_addr + >> 4U))])); + vcdp->fullBus(c+741,(vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__data_structures__DOT__each_way__BRA__1__KET____DOT__data_structures__DOT__tag + [(0x1fU & (vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_addr + >> 4U))]),23); + __Vtemp212[0U] = vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__data_structures__DOT__each_way__BRA__1__KET____DOT__data_structures__DOT__data + [(0x1fU & (vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_addr + >> 4U))][0U]; + __Vtemp212[1U] = vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__data_structures__DOT__each_way__BRA__1__KET____DOT__data_structures__DOT__data + [(0x1fU & (vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_addr + >> 4U))][1U]; + __Vtemp212[2U] = vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__data_structures__DOT__each_way__BRA__1__KET____DOT__data_structures__DOT__data + [(0x1fU & (vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_addr + >> 4U))][2U]; + __Vtemp212[3U] = vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__data_structures__DOT__each_way__BRA__1__KET____DOT__data_structures__DOT__data + [(0x1fU & (vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_addr + >> 4U))][3U]; + vcdp->fullArray(c+742,(__Vtemp212),128); + vcdp->fullBit(c+746,(vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__data_structures__DOT__each_way__BRA__1__KET____DOT__data_structures__DOT__valid + [(0x1fU & (vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_addr + >> 4U))])); + vcdp->fullBus(c+747,(vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__0__KET____DOT__bank_structure.__PVT__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__tag + [(0x1fU & (vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__0__KET____DOT__bank_addr + >> 6U))]),21); + __Vtemp213[0U] = vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__0__KET____DOT__bank_structure.__PVT__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__data + [(0x1fU & (vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__0__KET____DOT__bank_addr + >> 6U))][0U]; + __Vtemp213[1U] = vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__0__KET____DOT__bank_structure.__PVT__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__data + [(0x1fU & (vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__0__KET____DOT__bank_addr + >> 6U))][1U]; + __Vtemp213[2U] = vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__0__KET____DOT__bank_structure.__PVT__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__data + [(0x1fU & (vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__0__KET____DOT__bank_addr + >> 6U))][2U]; + __Vtemp213[3U] = vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__0__KET____DOT__bank_structure.__PVT__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__data + [(0x1fU & (vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__0__KET____DOT__bank_addr + >> 6U))][3U]; + vcdp->fullArray(c+748,(__Vtemp213),128); + vcdp->fullBit(c+752,(vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__0__KET____DOT__bank_structure.__PVT__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__valid + [(0x1fU & (vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__0__KET____DOT__bank_addr + >> 6U))])); + vcdp->fullBus(c+753,(vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__0__KET____DOT__bank_structure.__PVT__data_structures__DOT__each_way__BRA__1__KET____DOT__data_structures__DOT__tag + [(0x1fU & (vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__0__KET____DOT__bank_addr + >> 6U))]),21); + __Vtemp214[0U] = vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__0__KET____DOT__bank_structure.__PVT__data_structures__DOT__each_way__BRA__1__KET____DOT__data_structures__DOT__data + [(0x1fU & (vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__0__KET____DOT__bank_addr + >> 6U))][0U]; + __Vtemp214[1U] = vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__0__KET____DOT__bank_structure.__PVT__data_structures__DOT__each_way__BRA__1__KET____DOT__data_structures__DOT__data + [(0x1fU & (vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__0__KET____DOT__bank_addr + >> 6U))][1U]; + __Vtemp214[2U] = vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__0__KET____DOT__bank_structure.__PVT__data_structures__DOT__each_way__BRA__1__KET____DOT__data_structures__DOT__data + [(0x1fU & (vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__0__KET____DOT__bank_addr + >> 6U))][2U]; + __Vtemp214[3U] = vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__0__KET____DOT__bank_structure.__PVT__data_structures__DOT__each_way__BRA__1__KET____DOT__data_structures__DOT__data + [(0x1fU & (vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__0__KET____DOT__bank_addr + >> 6U))][3U]; + vcdp->fullArray(c+754,(__Vtemp214),128); + vcdp->fullBit(c+758,(vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__0__KET____DOT__bank_structure.__PVT__data_structures__DOT__each_way__BRA__1__KET____DOT__data_structures__DOT__valid + [(0x1fU & (vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__0__KET____DOT__bank_addr + >> 6U))])); + vcdp->fullBus(c+759,(vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__1__KET____DOT__bank_structure.__PVT__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__tag + [(0x1fU & (vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__1__KET____DOT__bank_addr + >> 6U))]),21); + __Vtemp215[0U] = vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__1__KET____DOT__bank_structure.__PVT__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__data + [(0x1fU & (vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__1__KET____DOT__bank_addr + >> 6U))][0U]; + __Vtemp215[1U] = vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__1__KET____DOT__bank_structure.__PVT__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__data + [(0x1fU & (vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__1__KET____DOT__bank_addr + >> 6U))][1U]; + __Vtemp215[2U] = vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__1__KET____DOT__bank_structure.__PVT__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__data + [(0x1fU & (vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__1__KET____DOT__bank_addr + >> 6U))][2U]; + __Vtemp215[3U] = vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__1__KET____DOT__bank_structure.__PVT__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__data + [(0x1fU & (vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__1__KET____DOT__bank_addr + >> 6U))][3U]; + vcdp->fullArray(c+760,(__Vtemp215),128); + vcdp->fullBit(c+764,(vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__1__KET____DOT__bank_structure.__PVT__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__valid + [(0x1fU & (vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__1__KET____DOT__bank_addr + >> 6U))])); + vcdp->fullBus(c+765,(vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__1__KET____DOT__bank_structure.__PVT__data_structures__DOT__each_way__BRA__1__KET____DOT__data_structures__DOT__tag + [(0x1fU & (vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__1__KET____DOT__bank_addr + >> 6U))]),21); + __Vtemp216[0U] = vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__1__KET____DOT__bank_structure.__PVT__data_structures__DOT__each_way__BRA__1__KET____DOT__data_structures__DOT__data + [(0x1fU & (vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__1__KET____DOT__bank_addr + >> 6U))][0U]; + __Vtemp216[1U] = vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__1__KET____DOT__bank_structure.__PVT__data_structures__DOT__each_way__BRA__1__KET____DOT__data_structures__DOT__data + [(0x1fU & (vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__1__KET____DOT__bank_addr + >> 6U))][1U]; + __Vtemp216[2U] = vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__1__KET____DOT__bank_structure.__PVT__data_structures__DOT__each_way__BRA__1__KET____DOT__data_structures__DOT__data + [(0x1fU & (vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__1__KET____DOT__bank_addr + >> 6U))][2U]; + __Vtemp216[3U] = vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__1__KET____DOT__bank_structure.__PVT__data_structures__DOT__each_way__BRA__1__KET____DOT__data_structures__DOT__data + [(0x1fU & (vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__1__KET____DOT__bank_addr + >> 6U))][3U]; + vcdp->fullArray(c+766,(__Vtemp216),128); + vcdp->fullBit(c+770,(vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__1__KET____DOT__bank_structure.__PVT__data_structures__DOT__each_way__BRA__1__KET____DOT__data_structures__DOT__valid + [(0x1fU & (vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__1__KET____DOT__bank_addr + >> 6U))])); + vcdp->fullBus(c+771,(vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__2__KET____DOT__bank_structure.__PVT__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__tag + [(0x1fU & (vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__2__KET____DOT__bank_addr + >> 6U))]),21); + __Vtemp217[0U] = vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__2__KET____DOT__bank_structure.__PVT__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__data + [(0x1fU & (vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__2__KET____DOT__bank_addr + >> 6U))][0U]; + __Vtemp217[1U] = vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__2__KET____DOT__bank_structure.__PVT__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__data + [(0x1fU & (vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__2__KET____DOT__bank_addr + >> 6U))][1U]; + __Vtemp217[2U] = vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__2__KET____DOT__bank_structure.__PVT__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__data + [(0x1fU & (vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__2__KET____DOT__bank_addr + >> 6U))][2U]; + __Vtemp217[3U] = vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__2__KET____DOT__bank_structure.__PVT__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__data + [(0x1fU & (vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__2__KET____DOT__bank_addr + >> 6U))][3U]; + vcdp->fullArray(c+772,(__Vtemp217),128); + vcdp->fullBit(c+776,(vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__2__KET____DOT__bank_structure.__PVT__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__valid + [(0x1fU & (vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__2__KET____DOT__bank_addr + >> 6U))])); + vcdp->fullBus(c+777,(vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__2__KET____DOT__bank_structure.__PVT__data_structures__DOT__each_way__BRA__1__KET____DOT__data_structures__DOT__tag + [(0x1fU & (vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__2__KET____DOT__bank_addr + >> 6U))]),21); + __Vtemp218[0U] = vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__2__KET____DOT__bank_structure.__PVT__data_structures__DOT__each_way__BRA__1__KET____DOT__data_structures__DOT__data + [(0x1fU & (vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__2__KET____DOT__bank_addr + >> 6U))][0U]; + __Vtemp218[1U] = vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__2__KET____DOT__bank_structure.__PVT__data_structures__DOT__each_way__BRA__1__KET____DOT__data_structures__DOT__data + [(0x1fU & (vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__2__KET____DOT__bank_addr + >> 6U))][1U]; + __Vtemp218[2U] = vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__2__KET____DOT__bank_structure.__PVT__data_structures__DOT__each_way__BRA__1__KET____DOT__data_structures__DOT__data + [(0x1fU & (vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__2__KET____DOT__bank_addr + >> 6U))][2U]; + __Vtemp218[3U] = vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__2__KET____DOT__bank_structure.__PVT__data_structures__DOT__each_way__BRA__1__KET____DOT__data_structures__DOT__data + [(0x1fU & (vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__2__KET____DOT__bank_addr + >> 6U))][3U]; + vcdp->fullArray(c+778,(__Vtemp218),128); + vcdp->fullBit(c+782,(vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__2__KET____DOT__bank_structure.__PVT__data_structures__DOT__each_way__BRA__1__KET____DOT__data_structures__DOT__valid + [(0x1fU & (vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__2__KET____DOT__bank_addr + >> 6U))])); + vcdp->fullBus(c+783,(vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__3__KET____DOT__bank_structure.__PVT__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__tag + [(0x1fU & (vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__3__KET____DOT__bank_addr + >> 6U))]),21); + __Vtemp219[0U] = vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__3__KET____DOT__bank_structure.__PVT__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__data + [(0x1fU & (vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__3__KET____DOT__bank_addr + >> 6U))][0U]; + __Vtemp219[1U] = vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__3__KET____DOT__bank_structure.__PVT__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__data + [(0x1fU & (vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__3__KET____DOT__bank_addr + >> 6U))][1U]; + __Vtemp219[2U] = vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__3__KET____DOT__bank_structure.__PVT__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__data + [(0x1fU & (vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__3__KET____DOT__bank_addr + >> 6U))][2U]; + __Vtemp219[3U] = vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__3__KET____DOT__bank_structure.__PVT__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__data + [(0x1fU & (vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__3__KET____DOT__bank_addr + >> 6U))][3U]; + vcdp->fullArray(c+784,(__Vtemp219),128); + vcdp->fullBit(c+788,(vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__3__KET____DOT__bank_structure.__PVT__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__valid + [(0x1fU & (vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__3__KET____DOT__bank_addr + >> 6U))])); + vcdp->fullBus(c+789,(vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__3__KET____DOT__bank_structure.__PVT__data_structures__DOT__each_way__BRA__1__KET____DOT__data_structures__DOT__tag + [(0x1fU & (vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__3__KET____DOT__bank_addr + >> 6U))]),21); + __Vtemp220[0U] = vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__3__KET____DOT__bank_structure.__PVT__data_structures__DOT__each_way__BRA__1__KET____DOT__data_structures__DOT__data + [(0x1fU & (vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__3__KET____DOT__bank_addr + >> 6U))][0U]; + __Vtemp220[1U] = vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__3__KET____DOT__bank_structure.__PVT__data_structures__DOT__each_way__BRA__1__KET____DOT__data_structures__DOT__data + [(0x1fU & (vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__3__KET____DOT__bank_addr + >> 6U))][1U]; + __Vtemp220[2U] = vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__3__KET____DOT__bank_structure.__PVT__data_structures__DOT__each_way__BRA__1__KET____DOT__data_structures__DOT__data + [(0x1fU & (vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__3__KET____DOT__bank_addr + >> 6U))][2U]; + __Vtemp220[3U] = vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__3__KET____DOT__bank_structure.__PVT__data_structures__DOT__each_way__BRA__1__KET____DOT__data_structures__DOT__data + [(0x1fU & (vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__3__KET____DOT__bank_addr + >> 6U))][3U]; + vcdp->fullArray(c+790,(__Vtemp220),128); + vcdp->fullBit(c+794,(vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__3__KET____DOT__bank_structure.__PVT__data_structures__DOT__each_way__BRA__1__KET____DOT__data_structures__DOT__valid + [(0x1fU & (vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__3__KET____DOT__bank_addr + >> 6U))])); + vcdp->fullBit(c+795,(vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__way_to_update)); + vcdp->fullBit(c+796,(vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__0__KET____DOT__bank_structure.__PVT__way_to_update)); + vcdp->fullBit(c+797,(vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__1__KET____DOT__bank_structure.__PVT__way_to_update)); + vcdp->fullBit(c+798,(vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__2__KET____DOT__bank_structure.__PVT__way_to_update)); + vcdp->fullBit(c+799,(vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__3__KET____DOT__bank_structure.__PVT__way_to_update)); + vcdp->fullBit(c+800,(vlTOPp->cache_simX__DOT__icache_i_m_ready)); + vcdp->fullBit(c+801,(vlTOPp->cache_simX__DOT__dcache_i_m_ready)); + vcdp->fullBus(c+802,((0xffffffc0U & vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT__miss_addr)),32); + vcdp->fullBit(c+803,((1U == (IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT__state)))); + vcdp->fullBus(c+804,((0xfffffff0U & vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__miss_addr)),32); + vcdp->fullBit(c+805,((1U == (IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__state)))); + vcdp->fullBus(c+806,(vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__vx_priority_encoder_sm__DOT__left_requests),4); + vcdp->fullBit(c+807,((0U != (IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__vx_priority_encoder_sm__DOT__left_requests)))); + vcdp->fullBus(c+808,(vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__genblk2__BRA__0__KET____DOT__vx_shared_memory_block__DOT__curr_ind),32); + vcdp->fullBus(c+809,(vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__genblk2__BRA__1__KET____DOT__vx_shared_memory_block__DOT__curr_ind),32); + vcdp->fullBus(c+810,(vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__genblk2__BRA__2__KET____DOT__vx_shared_memory_block__DOT__curr_ind),32); + vcdp->fullBus(c+811,(vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__genblk2__BRA__3__KET____DOT__vx_shared_memory_block__DOT__curr_ind),32); + vcdp->fullArray(c+812,(vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT__final_data_read),128); + vcdp->fullBit(c+816,(vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT__global_way_to_evict)); + vcdp->fullBus(c+817,(vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT__state),4); + vcdp->fullBus(c+818,(vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT__stored_valid),4); + vcdp->fullBus(c+819,(vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT__miss_addr),32); + vcdp->fullBus(c+820,(vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__final_data_read),32); + vcdp->fullBit(c+821,(vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__global_way_to_evict)); + vcdp->fullBus(c+822,(vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__state),4); + vcdp->fullBit(c+823,(vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__stored_valid)); + vcdp->fullBus(c+824,(vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__miss_addr),32); + __Vtemp221[0U] = vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__data + [0U][0U]; + __Vtemp221[1U] = vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__data + [0U][1U]; + __Vtemp221[2U] = vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__data + [0U][2U]; + __Vtemp221[3U] = vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__data + [0U][3U]; + vcdp->fullArray(c+825,(__Vtemp221),128); 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+ vcdp->fullBit(c+3052,(vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__3__KET____DOT__bank_structure.__PVT__data_structures__DOT__each_way__BRA__1__KET____DOT__data_structures__DOT__dirty[1])); + vcdp->fullBit(c+3053,(vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__3__KET____DOT__bank_structure.__PVT__data_structures__DOT__each_way__BRA__1__KET____DOT__data_structures__DOT__dirty[2])); + vcdp->fullBit(c+3054,(vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__3__KET____DOT__bank_structure.__PVT__data_structures__DOT__each_way__BRA__1__KET____DOT__data_structures__DOT__dirty[3])); + vcdp->fullBit(c+3055,(vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__3__KET____DOT__bank_structure.__PVT__data_structures__DOT__each_way__BRA__1__KET____DOT__data_structures__DOT__dirty[4])); + vcdp->fullBit(c+3056,(vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__3__KET____DOT__bank_structure.__PVT__data_structures__DOT__each_way__BRA__1__KET____DOT__data_structures__DOT__dirty[5])); + vcdp->fullBit(c+3057,(vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__3__KET____DOT__bank_structure.__PVT__data_structures__DOT__each_way__BRA__1__KET____DOT__data_structures__DOT__dirty[6])); + vcdp->fullBit(c+3058,(vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__3__KET____DOT__bank_structure.__PVT__data_structures__DOT__each_way__BRA__1__KET____DOT__data_structures__DOT__dirty[7])); + vcdp->fullBit(c+3059,(vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__3__KET____DOT__bank_structure.__PVT__data_structures__DOT__each_way__BRA__1__KET____DOT__data_structures__DOT__dirty[8])); + vcdp->fullBit(c+3060,(vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__3__KET____DOT__bank_structure.__PVT__data_structures__DOT__each_way__BRA__1__KET____DOT__data_structures__DOT__dirty[9])); + vcdp->fullBit(c+3061,(vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__3__KET____DOT__bank_structure.__PVT__data_structures__DOT__each_way__BRA__1__KET____DOT__data_structures__DOT__dirty[10])); + vcdp->fullBit(c+3062,(vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__3__KET____DOT__bank_structure.__PVT__data_structures__DOT__each_way__BRA__1__KET____DOT__data_structures__DOT__dirty[11])); + vcdp->fullBit(c+3063,(vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__3__KET____DOT__bank_structure.__PVT__data_structures__DOT__each_way__BRA__1__KET____DOT__data_structures__DOT__dirty[12])); + vcdp->fullBit(c+3064,(vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__3__KET____DOT__bank_structure.__PVT__data_structures__DOT__each_way__BRA__1__KET____DOT__data_structures__DOT__dirty[13])); + vcdp->fullBit(c+3065,(vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__3__KET____DOT__bank_structure.__PVT__data_structures__DOT__each_way__BRA__1__KET____DOT__data_structures__DOT__dirty[14])); + vcdp->fullBit(c+3066,(vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__3__KET____DOT__bank_structure.__PVT__data_structures__DOT__each_way__BRA__1__KET____DOT__data_structures__DOT__dirty[15])); + vcdp->fullBit(c+3067,(vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__3__KET____DOT__bank_structure.__PVT__data_structures__DOT__each_way__BRA__1__KET____DOT__data_structures__DOT__dirty[16])); + vcdp->fullBit(c+3068,(vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__3__KET____DOT__bank_structure.__PVT__data_structures__DOT__each_way__BRA__1__KET____DOT__data_structures__DOT__dirty[17])); + vcdp->fullBit(c+3069,(vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__3__KET____DOT__bank_structure.__PVT__data_structures__DOT__each_way__BRA__1__KET____DOT__data_structures__DOT__dirty[18])); + vcdp->fullBit(c+3070,(vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__3__KET____DOT__bank_structure.__PVT__data_structures__DOT__each_way__BRA__1__KET____DOT__data_structures__DOT__dirty[19])); + vcdp->fullBit(c+3071,(vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__3__KET____DOT__bank_structure.__PVT__data_structures__DOT__each_way__BRA__1__KET____DOT__data_structures__DOT__dirty[20])); + vcdp->fullBit(c+3072,(vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__3__KET____DOT__bank_structure.__PVT__data_structures__DOT__each_way__BRA__1__KET____DOT__data_structures__DOT__dirty[21])); + vcdp->fullBit(c+3073,(vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__3__KET____DOT__bank_structure.__PVT__data_structures__DOT__each_way__BRA__1__KET____DOT__data_structures__DOT__dirty[22])); + vcdp->fullBit(c+3074,(vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__3__KET____DOT__bank_structure.__PVT__data_structures__DOT__each_way__BRA__1__KET____DOT__data_structures__DOT__dirty[23])); + vcdp->fullBit(c+3075,(vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__3__KET____DOT__bank_structure.__PVT__data_structures__DOT__each_way__BRA__1__KET____DOT__data_structures__DOT__dirty[24])); + vcdp->fullBit(c+3076,(vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__3__KET____DOT__bank_structure.__PVT__data_structures__DOT__each_way__BRA__1__KET____DOT__data_structures__DOT__dirty[25])); + vcdp->fullBit(c+3077,(vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__3__KET____DOT__bank_structure.__PVT__data_structures__DOT__each_way__BRA__1__KET____DOT__data_structures__DOT__dirty[26])); + vcdp->fullBit(c+3078,(vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__3__KET____DOT__bank_structure.__PVT__data_structures__DOT__each_way__BRA__1__KET____DOT__data_structures__DOT__dirty[27])); + vcdp->fullBit(c+3079,(vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__3__KET____DOT__bank_structure.__PVT__data_structures__DOT__each_way__BRA__1__KET____DOT__data_structures__DOT__dirty[28])); + vcdp->fullBit(c+3080,(vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__3__KET____DOT__bank_structure.__PVT__data_structures__DOT__each_way__BRA__1__KET____DOT__data_structures__DOT__dirty[29])); + vcdp->fullBit(c+3081,(vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__3__KET____DOT__bank_structure.__PVT__data_structures__DOT__each_way__BRA__1__KET____DOT__data_structures__DOT__dirty[30])); + vcdp->fullBit(c+3082,(vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__3__KET____DOT__bank_structure.__PVT__data_structures__DOT__each_way__BRA__1__KET____DOT__data_structures__DOT__dirty[31])); + vcdp->fullBus(c+3083,(vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__3__KET____DOT__bank_structure.__PVT__data_structures__DOT__each_way__BRA__1__KET____DOT__data_structures__DOT__f),32); + vcdp->fullBus(c+3084,(vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__3__KET____DOT__bank_structure.__PVT__data_structures__DOT__each_way__BRA__1__KET____DOT__data_structures__DOT__ini_ind),32); + vcdp->fullBit(c+3085,(vlTOPp->clk)); + vcdp->fullBit(c+3086,(vlTOPp->reset)); + vcdp->fullBus(c+3087,(vlTOPp->in_icache_pc_addr),32); + vcdp->fullBit(c+3088,(vlTOPp->in_icache_valid_pc_addr)); + vcdp->fullBit(c+3089,(vlTOPp->out_icache_stall)); + vcdp->fullBus(c+3090,(vlTOPp->in_dcache_mem_read),3); + vcdp->fullBus(c+3091,(vlTOPp->in_dcache_mem_write),3); + vcdp->fullBit(c+3092,(vlTOPp->in_dcache_in_valid[0])); + vcdp->fullBit(c+3093,(vlTOPp->in_dcache_in_valid[1])); + vcdp->fullBit(c+3094,(vlTOPp->in_dcache_in_valid[2])); + vcdp->fullBit(c+3095,(vlTOPp->in_dcache_in_valid[3])); + vcdp->fullBus(c+3096,(vlTOPp->in_dcache_in_address[0]),32); + vcdp->fullBus(c+3097,(vlTOPp->in_dcache_in_address[1]),32); + vcdp->fullBus(c+3098,(vlTOPp->in_dcache_in_address[2]),32); + vcdp->fullBus(c+3099,(vlTOPp->in_dcache_in_address[3]),32); + vcdp->fullBit(c+3100,(vlTOPp->out_dcache_stall)); + vcdp->fullBus(c+3101,(((IData)(vlTOPp->in_icache_valid_pc_addr) + ? 2U : 7U)),3); + vcdp->fullBus(c+3102,(4U),32); + vcdp->fullArray(c+3103,(vlSymsp->TOP__cache_simX__DOT__VX_dram_req_rsp.i_m_readdata),512); + vcdp->fullBus(c+3119,(1U),32); + vcdp->fullArray(c+3120,(vlSymsp->TOP__cache_simX__DOT__VX_dram_req_rsp_icache.i_m_readdata),128); + vcdp->fullBus(c+3124,(7U),3); + vcdp->fullBus(c+3125,(0U),32); + __Vtemp541[0U] = 0U; + __Vtemp541[1U] = 0U; + __Vtemp541[2U] = 0U; + __Vtemp541[3U] = 0U; + vcdp->fullArray(c+3126,(__Vtemp541),128); + vcdp->fullBit(c+3130,(0U)); + vcdp->fullBus(c+3131,(0x2000U),32); + vcdp->fullBus(c+3132,(0x10U),32); + vcdp->fullBus(c+3133,(2U),32); + vcdp->fullBus(c+3134,(0x80U),32); + vcdp->fullBus(c+3135,(3U),32); + vcdp->fullBus(c+3136,(5U),32); + vcdp->fullBus(c+3137,(6U),32); + vcdp->fullBus(c+3138,(0xcU),32); + vcdp->fullBus(c+3139,(4U),32); + vcdp->fullBus(c+3140,(0xffffffffU),32); + vcdp->fullBus(c+3141,(0x1000U),32); + vcdp->fullBus(c+3142,(0x40U),32); + vcdp->fullBus(c+3143,(0x20U),32); + vcdp->fullBus(c+3144,(0x14U),32); + vcdp->fullBus(c+3145,(0xbU),32); + vcdp->fullBus(c+3146,(0x1fU),32); + vcdp->fullBus(c+3147,(0xaU),32); + vcdp->fullBus(c+3148,(0xffffffc0U),32); + vcdp->fullBus(c+3149,(vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT__eviction_wb_old),4); + vcdp->fullBus(c+3150,(vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT__init_b),32); + vcdp->fullBus(c+3151,(0x400U),32); + vcdp->fullBus(c+3152,(0x16U),32); + vcdp->fullBus(c+3153,(9U),32); + vcdp->fullBus(c+3154,(8U),32); + vcdp->fullBus(c+3155,(0xfffffff0U),32); + vcdp->fullBit(c+3156,(vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__eviction_wb_old)); + vcdp->fullBus(c+3157,(1U),32); + vcdp->fullBus(c+3158,(vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__init_b),32); + __Vtemp542[0U] = vlSymsp->TOP__cache_simX__DOT__VX_dram_req_rsp.i_m_readdata[0U]; + __Vtemp542[1U] = vlSymsp->TOP__cache_simX__DOT__VX_dram_req_rsp.i_m_readdata[1U]; + __Vtemp542[2U] = vlSymsp->TOP__cache_simX__DOT__VX_dram_req_rsp.i_m_readdata[2U]; + __Vtemp542[3U] = vlSymsp->TOP__cache_simX__DOT__VX_dram_req_rsp.i_m_readdata[3U]; + vcdp->fullArray(c+3159,(__Vtemp542),128); + __Vtemp543[0U] = vlSymsp->TOP__cache_simX__DOT__VX_dram_req_rsp.i_m_readdata[4U]; + __Vtemp543[1U] = vlSymsp->TOP__cache_simX__DOT__VX_dram_req_rsp.i_m_readdata[5U]; + __Vtemp543[2U] = vlSymsp->TOP__cache_simX__DOT__VX_dram_req_rsp.i_m_readdata[6U]; + __Vtemp543[3U] = vlSymsp->TOP__cache_simX__DOT__VX_dram_req_rsp.i_m_readdata[7U]; + vcdp->fullArray(c+3163,(__Vtemp543),128); + __Vtemp544[0U] = vlSymsp->TOP__cache_simX__DOT__VX_dram_req_rsp.i_m_readdata[8U]; + __Vtemp544[1U] = vlSymsp->TOP__cache_simX__DOT__VX_dram_req_rsp.i_m_readdata[9U]; + __Vtemp544[2U] = vlSymsp->TOP__cache_simX__DOT__VX_dram_req_rsp.i_m_readdata[0xaU]; + __Vtemp544[3U] = vlSymsp->TOP__cache_simX__DOT__VX_dram_req_rsp.i_m_readdata[0xbU]; + vcdp->fullArray(c+3167,(__Vtemp544),128); + __Vtemp545[0U] = vlSymsp->TOP__cache_simX__DOT__VX_dram_req_rsp.i_m_readdata[0xcU]; + __Vtemp545[1U] = vlSymsp->TOP__cache_simX__DOT__VX_dram_req_rsp.i_m_readdata[0xdU]; + __Vtemp545[2U] = vlSymsp->TOP__cache_simX__DOT__VX_dram_req_rsp.i_m_readdata[0xeU]; + __Vtemp545[3U] = vlSymsp->TOP__cache_simX__DOT__VX_dram_req_rsp.i_m_readdata[0xfU]; + vcdp->fullArray(c+3171,(__Vtemp545),128); + } +} diff --git a/simX/obj_dir/Vcache_simX__ver.d b/simX/obj_dir/Vcache_simX__ver.d new file mode 100644 index 00000000..d367ac3c --- /dev/null +++ b/simX/obj_dir/Vcache_simX__ver.d @@ -0,0 +1 @@ +obj_dir/Vcache_simX.cpp obj_dir/Vcache_simX.h obj_dir/Vcache_simX.mk obj_dir/Vcache_simX_VX_Cache_Bank__pi7.cpp obj_dir/Vcache_simX_VX_Cache_Bank__pi7.h obj_dir/Vcache_simX_VX_dcache_request_inter.cpp obj_dir/Vcache_simX_VX_dcache_request_inter.h obj_dir/Vcache_simX_VX_dram_req_rsp_inter__N1_NB4.cpp obj_dir/Vcache_simX_VX_dram_req_rsp_inter__N1_NB4.h obj_dir/Vcache_simX_VX_dram_req_rsp_inter__N4_NB4.cpp obj_dir/Vcache_simX_VX_dram_req_rsp_inter__N4_NB4.h obj_dir/Vcache_simX__Syms.cpp obj_dir/Vcache_simX__Syms.h obj_dir/Vcache_simX__Trace.cpp obj_dir/Vcache_simX__Trace__Slow.cpp obj_dir/Vcache_simX__ver.d obj_dir/Vcache_simX_classes.mk : /usr/local/bin/verilator_bin ../rtl/VX_countones.v ../rtl/VX_define.v ../rtl/VX_dmem_controller.v ../rtl/VX_generic_priority_encoder.v ../rtl/VX_priority_encoder_w_mask.v ../rtl/cache/VX_Cache_Bank.v ../rtl/cache/VX_cache_bank_valid.v ../rtl/cache/VX_cache_data.v ../rtl/cache/VX_cache_data_per_index.v ../rtl/cache/VX_d_cache.v ../rtl/interfaces/VX_dcache_request_inter.v ../rtl/interfaces/VX_dcache_response_inter.v ../rtl/interfaces/VX_dram_req_rsp_inter.v ../rtl/interfaces/VX_icache_request_inter.v ../rtl/interfaces/VX_icache_response_inter.v ../rtl/shared_memory/../VX_define.v ../rtl/shared_memory/VX_bank_valids.v ../rtl/shared_memory/VX_priority_encoder_sm.v ../rtl/shared_memory/VX_shared_memory.v ../rtl/shared_memory/VX_shared_memory_block.v /usr/local/bin/verilator_bin cache_simX.v diff --git a/simX/obj_dir/Vcache_simX__verFiles.dat b/simX/obj_dir/Vcache_simX__verFiles.dat new file mode 100644 index 00000000..45f1e047 --- /dev/null +++ b/simX/obj_dir/Vcache_simX__verFiles.dat @@ -0,0 +1,42 @@ +# DESCRIPTION: Verilator output: Timestamp data for --skip-identical. Delete at will. +C "--compiler gcc -cc cache_simX.v -I. -I../rtl/shared_memory -I../rtl/cache -I../rtl/interfaces -Isimulate -I../rtl --exe simX.cpp args.cpp mem.cpp core.cpp instruction.cpp enc.cpp util.cpp -CFLAGS -std=c++11 -fPIC -O3 -Wno-UNOPTFLAT -Wno-WIDTH --trace -DVL_DEBUG=1" +S 283 10696049115265660 1574383273 224134400 1574383273 224134400 "../rtl/VX_countones.v" +S 7236 5066549581052550 1574383273 231079500 1574383273 231079500 "../rtl/VX_define.v" +S 8325 2251799813945994 1574383273 232119600 1574383273 232119600 "../rtl/VX_dmem_controller.v" +S 517 3096224744077973 1574383273 236061300 1574383273 236061300 "../rtl/VX_generic_priority_encoder.v" +S 683 2814749767367343 1574383273 260714600 1574383273 260714600 "../rtl/VX_priority_encoder_w_mask.v" +S 8590 10977524091976397 1574383273 267695600 1574383273 267695600 "../rtl/cache/VX_Cache_Bank.v" +S 748 10977524091976401 1574383273 277789900 1574383273 277789900 "../rtl/cache/VX_cache_bank_valid.v" +S 7349 9851624185133791 1574383273 278740700 1574383273 278740700 "../rtl/cache/VX_cache_data.v" +S 6476 34058472182250218 1574383273 279715700 1574383273 279715700 "../rtl/cache/VX_cache_data_per_index.v" +S 14456 13229323905661682 1574383273 279715700 1574383273 279715700 "../rtl/cache/VX_d_cache.v" +S 393 5910974511184689 1574383273 301972800 1574383273 301972800 "../rtl/interfaces/VX_dcache_request_inter.v" +S 215 2814749767367474 1574383273 302974100 1574383273 302974100 "../rtl/interfaces/VX_dcache_response_inter.v" +S 870 8725724278291251 1574383273 304006100 1574383273 304006100 "../rtl/interfaces/VX_dram_req_rsp_inter.v" +S 354 6192449487895387 1574383273 313939400 1574383273 313939400 "../rtl/interfaces/VX_icache_request_inter.v" +S 212 27021597764483932 1574383273 313939400 1574383273 313939400 "../rtl/interfaces/VX_icache_response_inter.v" +S 7236 5066549581052550 1574383273 231079500 1574383273 231079500 "../rtl/shared_memory/../VX_define.v" +S 676 3940649674211014 1574383273 400242000 1574383273 400242000 "../rtl/shared_memory/VX_bank_valids.v" +S 3038 3096224744079047 1574383273 411240400 1574383273 411240400 "../rtl/shared_memory/VX_priority_encoder_sm.v" +S 4962 3096224744079048 1574383273 412279700 1574383273 412279700 "../rtl/shared_memory/VX_shared_memory.v" +S 3207 3940649674211020 1574383273 412279700 1574383273 412279700 "../rtl/shared_memory/VX_shared_memory_block.v" +S 5629640 281474978453844 1574044016 334922400 1574044016 333963200 "/usr/local/bin/verilator_bin" +S 3144 1407374883818566 1574383274 742155300 1574383274 742155300 "cache_simX.v" +T 751758 20547673300142630 1574427193 757744700 1574427193 757744700 "obj_dir/Vcache_simX.cpp" +T 31623 7599824371327898 1574427193 691983400 1574427193 691983400 "obj_dir/Vcache_simX.h" +T 2380 7318349394745968 1574427193 846458800 1574427193 846458800 "obj_dir/Vcache_simX.mk" +T 769517 4785074604350062 1574427193 841470700 1574427193 841470700 "obj_dir/Vcache_simX_VX_Cache_Bank__pi7.cpp" +T 24956 5629499534482029 1574427193 770660800 1574427193 770660800 "obj_dir/Vcache_simX_VX_Cache_Bank__pi7.h" +T 1012 5066549581060716 1574427193 766841100 1574427193 766841100 "obj_dir/Vcache_simX_VX_dcache_request_inter.cpp" +T 1356 4785074604350059 1574427193 765276000 1574427193 765276000 "obj_dir/Vcache_simX_VX_dcache_request_inter.h" +T 987 5348024557771370 1574427193 763679100 1574427193 763679100 "obj_dir/Vcache_simX_VX_dram_req_rsp_inter__N1_NB4.cpp" +T 1333 5910974511192681 1574427193 761684400 1574427193 761684400 "obj_dir/Vcache_simX_VX_dram_req_rsp_inter__N1_NB4.h" +T 987 9288674231720551 1574427193 760896800 1574427193 760896800 "obj_dir/Vcache_simX_VX_dram_req_rsp_inter__N4_NB4.cpp" +T 1334 20829148276857269 1574427193 759408000 1574427193 759408000 "obj_dir/Vcache_simX_VX_dram_req_rsp_inter__N4_NB4.h" +T 3838 54606145481948840 1574427193 527314200 1574427193 527314200 "obj_dir/Vcache_simX__Syms.cpp" +T 1968 41939771530004893 1574427193 528311300 1574427193 528311300 "obj_dir/Vcache_simX__Syms.h" +T 762929 82472168176354735 1574427193 687881900 1574427193 687881900 "obj_dir/Vcache_simX__Trace.cpp" +T 990142 253046004063004355 1574427193 619067200 1574427193 619067200 "obj_dir/Vcache_simX__Trace__Slow.cpp" +T 1444 8444249301588593 1574427193 847454700 1574427193 847454700 "obj_dir/Vcache_simX__ver.d" +T 0 0 1574427193 858425500 1574427193 858425500 "obj_dir/Vcache_simX__verFiles.dat" +T 1489 13792273859091055 1574427193 843885600 1574427193 843885600 "obj_dir/Vcache_simX_classes.mk" diff --git a/simX/obj_dir/Vcache_simX_classes.mk b/simX/obj_dir/Vcache_simX_classes.mk new file mode 100644 index 00000000..23dad847 --- /dev/null +++ b/simX/obj_dir/Vcache_simX_classes.mk @@ -0,0 +1,47 @@ +# Verilated -*- Makefile -*- +# DESCRIPTION: Verilator output: Make include file with class lists +# +# This file lists generated Verilated files, for including in higher level makefiles. +# See Vcache_simX.mk for the caller. + +### Switches... +# Coverage output mode? 0/1 (from --coverage) +VM_COVERAGE = 0 +# Threaded output mode? 0/1/N threads (from --threads) +VM_THREADS = 0 +# Tracing output mode? 0/1 (from --trace) +VM_TRACE = 1 +# Tracing threadeds output mode? 0/1 (from --trace-fst-thread) +VM_TRACE_THREADED = 0 + +### Object file lists... +# Generated module classes, fast-path, compile with highest optimization +VM_CLASSES_FAST += \ + Vcache_simX \ + Vcache_simX_VX_dram_req_rsp_inter__N4_NB4 \ + Vcache_simX_VX_dram_req_rsp_inter__N1_NB4 \ + Vcache_simX_VX_dcache_request_inter \ + Vcache_simX_VX_Cache_Bank__pi7 \ + +# Generated module classes, non-fast-path, compile with low/medium optimization +VM_CLASSES_SLOW += \ + +# Generated support classes, fast-path, compile with highest optimization +VM_SUPPORT_FAST += \ + Vcache_simX__Trace \ + +# Generated support classes, non-fast-path, compile with low/medium optimization +VM_SUPPORT_SLOW += \ + Vcache_simX__Syms \ + Vcache_simX__Trace__Slow \ + +# Global classes, need linked once per executable, fast-path, compile with highest optimization +VM_GLOBAL_FAST += \ + verilated \ + verilated_vcd_c \ + +# Global classes, need linked once per executable, non-fast-path, compile with low/medium optimization +VM_GLOBAL_SLOW += \ + + +# Verilated -*- Makefile -*- diff --git a/simX/obj_dir/args.d b/simX/obj_dir/args.d new file mode 100644 index 00000000..bef545e5 --- /dev/null +++ b/simX/obj_dir/args.d @@ -0,0 +1 @@ +args.o: ../args.cpp ../include/args.h diff --git a/simX/obj_dir/args.o b/simX/obj_dir/args.o new file mode 100644 index 00000000..4c156f8c Binary files /dev/null and b/simX/obj_dir/args.o differ diff --git a/simX/obj_dir/core.d b/simX/obj_dir/core.d new file mode 100644 index 00000000..b3eda74b --- /dev/null +++ b/simX/obj_dir/core.d @@ -0,0 +1,10 @@ +core.o: ../core.cpp ../include/types.h ../include/util.h \ + ../include/types.h ../include/archdef.h ../include/mem.h \ + ../include/enc.h ../include/instruction.h ../include/trace.h \ + ../include/obj.h ../include/archdef.h ../include/enc.h \ + ../include/asm-tokens.h ../include/core.h ../include/mem.h \ + ../include/debug.h Vcache_simX.h \ + /usr/local/share/verilator/include/verilated.h \ + /usr/local/share/verilator/include/verilatedos.h \ + /usr/local/share/verilator/include/verilated_vcd_c.h \ + /usr/local/share/verilator/include/verilated.h ../include/debug.h diff --git a/simX/obj_dir/core.o b/simX/obj_dir/core.o new file mode 100644 index 00000000..f531e8c4 Binary files /dev/null and b/simX/obj_dir/core.o differ diff --git a/simX/obj_dir/emulator.debug b/simX/obj_dir/emulator.debug new file mode 100644 index 00000000..a1675d60 --- /dev/null +++ b/simX/obj_dir/emulator.debug @@ -0,0 +1,47768 @@ +DEBUG ../core.cpp:645: Creating a new thread with PC: 80000000 + +DEBUG ../core.cpp:645: Creating a new thread with PC: 80000000 + +DEBUG ../core.cpp:645: Creating a new thread with PC: 80000000 + +DEBUG ../core.cpp:645: Creating a new thread with PC: 80000000 + +DEBUG ../core.cpp:645: Creating a new thread with PC: 80000000 + +DEBUG ../core.cpp:645: Creating a new thread with PC: 80000000 + +DEBUG ../core.cpp:645: Creating a new thread with PC: 80000000 + +DEBUG ../core.cpp:645: Creating a new thread with PC: 80000000 + +ABOUT TO START +Warp ID 0 is running + + + +------------------------------------------------------ +CYCLE: 5 +Stalled Warps: +0 0 0 0 0 0 0 0 + +********************************** Writeback ********************************* +valid: 0 +PC: 0 +wid: 0 +rd: -1 rs1: -1 rs2: -1 +is_lw: 0 +is_sw: 0 +fetch_stall_cycles: 0 +mem_stall_cycles: 0 +stall_warp: 0 +wspawn: 0 +stalled: 0 +********************************** LSU ********************************* +valid: 0 +PC: 0 +wid: 0 +rd: -1 rs1: -1 rs2: -1 +is_lw: 0 +is_sw: 0 +fetch_stall_cycles: 0 +mem_stall_cycles: 0 +stall_warp: 0 +wspawn: 0 +stalled: 0 +********************************** execute_unit ********************************* +valid: 0 +PC: 0 +wid: 0 +rd: -1 rs1: -1 rs2: -1 +is_lw: 0 +is_sw: 0 +fetch_stall_cycles: 0 +mem_stall_cycles: 0 +stall_warp: 0 +wspawn: 0 +stalled: 0 +********************************** scheduler ********************************* +valid: 0 +PC: 0 +wid: 0 +rd: -1 rs1: -1 rs2: -1 +is_lw: 0 +is_sw: 0 +fetch_stall_cycles: 0 +mem_stall_cycles: 0 +stall_warp: 0 +wspawn: 0 +stalled: 0 +********************************** Decode ********************************* +valid: 0 +PC: 0 +wid: 0 +rd: -1 rs1: -1 rs2: -1 +is_lw: 0 +is_sw: 0 +fetch_stall_cycles: 0 +mem_stall_cycles: 0 +stall_warp: 0 +wspawn: 0 +stalled: 0 +DEBUG ../core.cpp:386: Core step stepping warp 0[1] +DEBUG ../core.cpp:683: in step pc=0x80000000 +help: in PC: 80000000 +CUrrent CODE: 597 +DEBUG ../core.cpp:703: Fetched at 0x80000000 +DEBUG ../core.cpp:704: 0x80000000: auipc; +DEBUG ../instruction.cpp:350: Begin instruction execute. +DEBUG ../instruction.cpp:2117: End instruction execute. +DEBUG ../core.cpp:717: Register state: + %r 0: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r 1: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r 2: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r 3: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r 4: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r 5: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r 6: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r 7: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r 8: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r 9: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r10: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r11: 80000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r12: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r13: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r14: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r15: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r16: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r17: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r18: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r19: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r20: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r21: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r22: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r23: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r24: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r25: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r26: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r27: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r28: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r29: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r30: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r31: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) +DEBUG ../core.cpp:726: Thread mask: + 1 0 0 0 0 0 0 0 + + +DEBUG ../core.cpp:388: Now 1 active threads in 0 +********************************** Fetch ********************************* +valid: 1 +PC: 80000000 +wid: 0 +rd: 11 rs1: -1 rs2: -1 +is_lw: 0 +is_sw: 0 +fetch_stall_cycles: 3 +mem_stall_cycles: 0 +stall_warp: 0 +wspawn: 0 +stalled: 0 + + + +------------------------------------------------------ +CYCLE: 6 +Stalled Warps: +0 0 0 0 0 0 0 0 + +********************************** Writeback ********************************* +valid: 0 +PC: 0 +wid: 0 +rd: -1 rs1: -1 rs2: -1 +is_lw: 0 +is_sw: 0 +fetch_stall_cycles: 0 +mem_stall_cycles: 0 +stall_warp: 0 +wspawn: 0 +stalled: 0 +********************************** LSU ********************************* +valid: 0 +PC: 0 +wid: 0 +rd: -1 rs1: -1 rs2: -1 +is_lw: 0 +is_sw: 0 +fetch_stall_cycles: 0 +mem_stall_cycles: 0 +stall_warp: 0 +wspawn: 0 +stalled: 0 +********************************** execute_unit ********************************* +valid: 0 +PC: 0 +wid: 0 +rd: -1 rs1: -1 rs2: -1 +is_lw: 0 +is_sw: 0 +fetch_stall_cycles: 0 +mem_stall_cycles: 0 +stall_warp: 0 +wspawn: 0 +stalled: 0 +********************************** scheduler ********************************* +valid: 0 +PC: 0 +wid: 0 +rd: -1 rs1: -1 rs2: -1 +is_lw: 0 +is_sw: 0 +fetch_stall_cycles: 0 +mem_stall_cycles: 0 +stall_warp: 0 +wspawn: 0 +stalled: 0 +********************************** Decode ********************************* +valid: 0 +PC: 0 +wid: 0 +rd: -1 rs1: -1 rs2: -1 +is_lw: 0 +is_sw: 0 +fetch_stall_cycles: 0 +mem_stall_cycles: 0 +stall_warp: 0 +wspawn: 0 +stalled: 0 +********************************** Fetch ********************************* +valid: 1 +PC: 80000000 +wid: 0 +rd: 11 rs1: -1 rs2: -1 +is_lw: 0 +is_sw: 0 +fetch_stall_cycles: 2 +mem_stall_cycles: 0 +stall_warp: 0 +wspawn: 0 +stalled: 0 + + + +------------------------------------------------------ +CYCLE: 7 +Stalled Warps: +0 0 0 0 0 0 0 0 + +********************************** Writeback ********************************* +valid: 0 +PC: 0 +wid: 0 +rd: -1 rs1: -1 rs2: -1 +is_lw: 0 +is_sw: 0 +fetch_stall_cycles: 0 +mem_stall_cycles: 0 +stall_warp: 0 +wspawn: 0 +stalled: 0 +********************************** LSU ********************************* +valid: 0 +PC: 0 +wid: 0 +rd: -1 rs1: -1 rs2: -1 +is_lw: 0 +is_sw: 0 +fetch_stall_cycles: 0 +mem_stall_cycles: 0 +stall_warp: 0 +wspawn: 0 +stalled: 0 +********************************** execute_unit ********************************* +valid: 0 +PC: 0 +wid: 0 +rd: -1 rs1: -1 rs2: -1 +is_lw: 0 +is_sw: 0 +fetch_stall_cycles: 0 +mem_stall_cycles: 0 +stall_warp: 0 +wspawn: 0 +stalled: 0 +********************************** scheduler ********************************* +valid: 0 +PC: 0 +wid: 0 +rd: -1 rs1: -1 rs2: -1 +is_lw: 0 +is_sw: 0 +fetch_stall_cycles: 0 +mem_stall_cycles: 0 +stall_warp: 0 +wspawn: 0 +stalled: 0 +********************************** Decode ********************************* +valid: 0 +PC: 0 +wid: 0 +rd: -1 rs1: -1 rs2: -1 +is_lw: 0 +is_sw: 0 +fetch_stall_cycles: 0 +mem_stall_cycles: 0 +stall_warp: 0 +wspawn: 0 +stalled: 0 +********************************** Fetch ********************************* +valid: 1 +PC: 80000000 +wid: 0 +rd: 11 rs1: -1 rs2: -1 +is_lw: 0 +is_sw: 0 +fetch_stall_cycles: 1 +mem_stall_cycles: 0 +stall_warp: 0 +wspawn: 0 +stalled: 0 + + + +------------------------------------------------------ +CYCLE: 8 +Stalled Warps: +0 0 0 0 0 0 0 0 + +********************************** Writeback ********************************* +valid: 0 +PC: 0 +wid: 0 +rd: -1 rs1: -1 rs2: -1 +is_lw: 0 +is_sw: 0 +fetch_stall_cycles: 0 +mem_stall_cycles: 0 +stall_warp: 0 +wspawn: 0 +stalled: 0 +********************************** LSU ********************************* +valid: 0 +PC: 0 +wid: 0 +rd: -1 rs1: -1 rs2: -1 +is_lw: 0 +is_sw: 0 +fetch_stall_cycles: 0 +mem_stall_cycles: 0 +stall_warp: 0 +wspawn: 0 +stalled: 0 +********************************** execute_unit ********************************* +valid: 0 +PC: 0 +wid: 0 +rd: -1 rs1: -1 rs2: -1 +is_lw: 0 +is_sw: 0 +fetch_stall_cycles: 0 +mem_stall_cycles: 0 +stall_warp: 0 +wspawn: 0 +stalled: 0 +********************************** scheduler ********************************* +valid: 0 +PC: 0 +wid: 0 +rd: -1 rs1: -1 rs2: -1 +is_lw: 0 +is_sw: 0 +fetch_stall_cycles: 0 +mem_stall_cycles: 0 +stall_warp: 0 +wspawn: 0 +stalled: 0 +********************************** Decode ********************************* +valid: 0 +PC: 0 +wid: 0 +rd: -1 rs1: -1 rs2: -1 +is_lw: 0 +is_sw: 0 +fetch_stall_cycles: 0 +mem_stall_cycles: 0 +stall_warp: 0 +wspawn: 0 +stalled: 0 +********************************** Fetch ********************************* +valid: 1 +PC: 80000000 +wid: 0 +rd: 11 rs1: -1 rs2: -1 +is_lw: 0 +is_sw: 0 +fetch_stall_cycles: 0 +mem_stall_cycles: 0 +stall_warp: 0 +wspawn: 0 +stalled: 0 + + + +------------------------------------------------------ +CYCLE: 9 +Stalled Warps: +0 0 0 0 0 0 0 0 + +********************************** Writeback ********************************* +valid: 0 +PC: 0 +wid: 0 +rd: -1 rs1: -1 rs2: -1 +is_lw: 0 +is_sw: 0 +fetch_stall_cycles: 0 +mem_stall_cycles: 0 +stall_warp: 0 +wspawn: 0 +stalled: 0 +********************************** LSU ********************************* +valid: 0 +PC: 0 +wid: 0 +rd: -1 rs1: -1 rs2: -1 +is_lw: 0 +is_sw: 0 +fetch_stall_cycles: 0 +mem_stall_cycles: 0 +stall_warp: 0 +wspawn: 0 +stalled: 0 +********************************** execute_unit ********************************* +valid: 0 +PC: 0 +wid: 0 +rd: -1 rs1: -1 rs2: -1 +is_lw: 0 +is_sw: 0 +fetch_stall_cycles: 0 +mem_stall_cycles: 0 +stall_warp: 0 +wspawn: 0 +stalled: 0 +********************************** scheduler ********************************* +valid: 0 +PC: 0 +wid: 0 +rd: -1 rs1: -1 rs2: -1 +is_lw: 0 +is_sw: 0 +fetch_stall_cycles: 0 +mem_stall_cycles: 0 +stall_warp: 0 +wspawn: 0 +stalled: 0 +********************************** Decode ********************************* +valid: 1 +PC: 80000000 +wid: 0 +rd: 11 rs1: -1 rs2: -1 +is_lw: 0 +is_sw: 0 +fetch_stall_cycles: 0 +mem_stall_cycles: 0 +stall_warp: 0 +wspawn: 0 +stalled: 0 +DEBUG ../core.cpp:386: Core step stepping warp 0[1] +DEBUG ../core.cpp:683: in step pc=0x80000004 +help: in PC: 80000004 +CUrrent CODE: 6c58593 +DEBUG ../core.cpp:703: Fetched at 0x80000004 +DEBUG ../core.cpp:704: 0x80000004: i_type; +DEBUG ../instruction.cpp:350: Begin instruction execute. +DEBUG ../instruction.cpp:2117: End instruction execute. +DEBUG ../core.cpp:717: Register state: + %r 0: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r 1: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r 2: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r 3: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r 4: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r 5: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r 6: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r 7: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r 8: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r 9: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r10: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r11: 8000006c 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r12: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r13: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r14: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r15: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r16: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r17: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r18: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r19: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r20: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r21: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r22: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r23: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r24: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r25: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r26: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r27: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r28: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r29: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r30: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r31: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) +DEBUG ../core.cpp:726: Thread mask: + 1 0 0 0 0 0 0 0 + + +DEBUG ../core.cpp:388: Now 1 active threads in 0 +********************************** Fetch ********************************* +valid: 1 +PC: 80000004 +wid: 0 +rd: 11 rs1: 11 rs2: -1 +is_lw: 0 +is_sw: 0 +fetch_stall_cycles: 0 +mem_stall_cycles: 0 +stall_warp: 0 +wspawn: 0 +stalled: 0 + + + +------------------------------------------------------ +CYCLE: 10 +Stalled Warps: +0 0 0 0 0 0 0 0 + +********************************** Writeback ********************************* +valid: 0 +PC: 0 +wid: 0 +rd: -1 rs1: -1 rs2: -1 +is_lw: 0 +is_sw: 0 +fetch_stall_cycles: 0 +mem_stall_cycles: 0 +stall_warp: 0 +wspawn: 0 +stalled: 0 +********************************** LSU ********************************* +valid: 0 +PC: 0 +wid: 0 +rd: -1 rs1: -1 rs2: -1 +is_lw: 0 +is_sw: 0 +fetch_stall_cycles: 0 +mem_stall_cycles: 0 +stall_warp: 0 +wspawn: 0 +stalled: 0 +********************************** execute_unit ********************************* +valid: 0 +PC: 0 +wid: 0 +rd: -1 rs1: -1 rs2: -1 +is_lw: 0 +is_sw: 0 +fetch_stall_cycles: 0 +mem_stall_cycles: 0 +stall_warp: 0 +wspawn: 0 +stalled: 0 +********************************** scheduler ********************************* +valid: 1 +PC: 80000000 +wid: 0 +rd: 11 rs1: -1 rs2: -1 +is_lw: 0 +is_sw: 0 +fetch_stall_cycles: 0 +mem_stall_cycles: 0 +stall_warp: 0 +wspawn: 0 +stalled: 0 +********************************** Decode ********************************* +valid: 1 +PC: 80000004 +wid: 0 +rd: 11 rs1: 11 rs2: -1 +is_lw: 0 +is_sw: 0 +fetch_stall_cycles: 0 +mem_stall_cycles: 0 +stall_warp: 0 +wspawn: 0 +stalled: 0 +DEBUG ../core.cpp:386: Core step stepping warp 0[1] +DEBUG ../core.cpp:683: in step pc=0x80000008 +help: in PC: 80000008 +CUrrent CODE: 400513 +DEBUG ../core.cpp:703: Fetched at 0x80000008 +DEBUG ../core.cpp:704: 0x80000008: i_type; +DEBUG ../instruction.cpp:350: Begin instruction execute. +DEBUG ../instruction.cpp:2117: End instruction execute. +DEBUG ../core.cpp:717: Register state: + %r 0: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r 1: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r 2: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r 3: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r 4: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r 5: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r 6: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r 7: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r 8: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r 9: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r10: 00000004 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r11: 8000006c 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r12: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r13: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r14: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r15: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r16: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r17: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r18: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r19: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r20: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r21: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r22: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r23: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r24: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r25: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r26: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r27: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r28: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r29: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r30: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r31: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) +DEBUG ../core.cpp:726: Thread mask: + 1 0 0 0 0 0 0 0 + + +DEBUG ../core.cpp:388: Now 1 active threads in 0 +********************************** Fetch ********************************* +valid: 1 +PC: 80000008 +wid: 0 +rd: 10 rs1: 0 rs2: -1 +is_lw: 0 +is_sw: 0 +fetch_stall_cycles: 0 +mem_stall_cycles: 0 +stall_warp: 0 +wspawn: 0 +stalled: 0 + + + +------------------------------------------------------ +CYCLE: 11 +Stalled Warps: +0 0 0 0 0 0 0 0 + +********************************** Writeback ********************************* +valid: 0 +PC: 0 +wid: 0 +rd: -1 rs1: -1 rs2: -1 +is_lw: 0 +is_sw: 0 +fetch_stall_cycles: 0 +mem_stall_cycles: 0 +stall_warp: 0 +wspawn: 0 +stalled: 0 +********************************** LSU ********************************* +valid: 0 +PC: 0 +wid: 0 +rd: -1 rs1: -1 rs2: -1 +is_lw: 0 +is_sw: 0 +fetch_stall_cycles: 0 +mem_stall_cycles: 0 +stall_warp: 0 +wspawn: 0 +stalled: 0 +********************************** execute_unit ********************************* +valid: 1 +PC: 80000000 +wid: 0 +rd: 11 rs1: -1 rs2: -1 +is_lw: 0 +is_sw: 0 +fetch_stall_cycles: 0 +mem_stall_cycles: 0 +stall_warp: 0 +wspawn: 0 +stalled: 0 +********************************** scheduler ********************************* +valid: 1 +PC: 80000004 +wid: 0 +rd: 11 rs1: 11 rs2: -1 +is_lw: 0 +is_sw: 0 +fetch_stall_cycles: 0 +mem_stall_cycles: 0 +stall_warp: 0 +wspawn: 0 +stalled: 0 +********************************** Decode ********************************* +valid: 1 +PC: 80000008 +wid: 0 +rd: 10 rs1: 0 rs2: -1 +is_lw: 0 +is_sw: 0 +fetch_stall_cycles: 0 +mem_stall_cycles: 0 +stall_warp: 0 +wspawn: 0 +stalled: 0 +DEBUG ../core.cpp:386: Core step stepping warp 0[1] +DEBUG ../core.cpp:683: in step pc=0x8000000c +help: in PC: 8000000c +CUrrent CODE: b5106b +DEBUG ../core.cpp:703: Fetched at 0x8000000c +DEBUG ../core.cpp:704: 0x8000000c: gpgpu; +DEBUG ../instruction.cpp:350: Begin instruction execute. +WSPAWN +DEBUG ../instruction.cpp:2117: End instruction execute. +DEBUG ../core.cpp:717: Register state: + %r 0: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r 1: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r 2: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r 3: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r 4: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r 5: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r 6: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r 7: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r 8: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r 9: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r10: 00000004 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r11: 8000006c 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r12: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r13: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r14: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r15: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r16: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r17: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r18: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r19: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r20: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r21: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r22: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r23: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r24: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r25: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r26: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r27: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r28: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r29: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r30: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r31: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) +DEBUG ../core.cpp:726: Thread mask: + 1 0 0 0 0 0 0 0 + + +DEBUG ../core.cpp:388: Now 1 active threads in 0 +********************************** Fetch ********************************* +valid: 1 +PC: 8000000c +wid: 0 +rd: 0 rs1: 10 rs2: 11 +is_lw: 0 +is_sw: 0 +fetch_stall_cycles: 0 +mem_stall_cycles: 0 +stall_warp: 0 +wspawn: 1 +stalled: 0 + + + +------------------------------------------------------ +CYCLE: 12 +Stalled Warps: +0 0 0 0 0 0 0 0 + +********************************** Writeback ********************************* +valid: 1 +PC: 80000000 +wid: 0 +rd: 11 rs1: -1 rs2: -1 +is_lw: 0 +is_sw: 0 +fetch_stall_cycles: 0 +mem_stall_cycles: 0 +stall_warp: 0 +wspawn: 0 +stalled: 0 +********************************** LSU ********************************* +valid: 0 +PC: 0 +wid: 0 +rd: -1 rs1: -1 rs2: -1 +is_lw: 0 +is_sw: 0 +fetch_stall_cycles: 0 +mem_stall_cycles: 0 +stall_warp: 0 +wspawn: 0 +stalled: 0 +&&&&&&&&&&&&&&&&&&&&&&&& EXECUTE SRCS NOT READY +********************************** execute_unit ********************************* +valid: 0 +PC: 0 +wid: 1 +rd: -1 rs1: -1 rs2: -1 +is_lw: 0 +is_sw: 0 +fetch_stall_cycles: 0 +mem_stall_cycles: 0 +stall_warp: 0 +wspawn: 0 +stalled: 0 +********************************** scheduler ********************************* +valid: 1 +PC: 80000004 +wid: 0 +rd: 11 rs1: 11 rs2: -1 +is_lw: 0 +is_sw: 0 +fetch_stall_cycles: 0 +mem_stall_cycles: 0 +stall_warp: 0 +wspawn: 0 +stalled: 1 +********************************** Decode ********************************* +valid: 1 +PC: 80000008 +wid: 0 +rd: 10 rs1: 0 rs2: -1 +is_lw: 0 +is_sw: 0 +fetch_stall_cycles: 0 +mem_stall_cycles: 0 +stall_warp: 0 +wspawn: 0 +stalled: 0 +********************************** Fetch ********************************* +valid: 1 +PC: 8000000c +wid: 0 +rd: 0 rs1: 10 rs2: 11 +is_lw: 0 +is_sw: 0 +fetch_stall_cycles: 0 +mem_stall_cycles: 0 +stall_warp: 0 +wspawn: 1 +stalled: 0 + + + +------------------------------------------------------ +CYCLE: 13 +Stalled Warps: +0 0 0 0 0 0 0 0 + +********************************** Writeback ********************************* +valid: 0 +PC: 0 +wid: 1 +rd: -1 rs1: -1 rs2: -1 +is_lw: 0 +is_sw: 0 +fetch_stall_cycles: 0 +mem_stall_cycles: 0 +stall_warp: 0 +wspawn: 0 +stalled: 0 +********************************** LSU ********************************* +valid: 0 +PC: 0 +wid: 0 +rd: -1 rs1: -1 rs2: -1 +is_lw: 0 +is_sw: 0 +fetch_stall_cycles: 0 +mem_stall_cycles: 0 +stall_warp: 0 +wspawn: 0 +stalled: 0 +********************************** execute_unit ********************************* +valid: 1 +PC: 80000004 +wid: 0 +rd: 11 rs1: 11 rs2: -1 +is_lw: 0 +is_sw: 0 +fetch_stall_cycles: 0 +mem_stall_cycles: 0 +stall_warp: 0 +wspawn: 0 +stalled: 0 +********************************** scheduler ********************************* +valid: 1 +PC: 80000008 +wid: 0 +rd: 10 rs1: 0 rs2: -1 +is_lw: 0 +is_sw: 0 +fetch_stall_cycles: 0 +mem_stall_cycles: 0 +stall_warp: 0 +wspawn: 0 +stalled: 0 +********************************** Decode ********************************* +valid: 1 +PC: 8000000c +wid: 0 +rd: 0 rs1: 10 rs2: 11 +is_lw: 0 +is_sw: 0 +fetch_stall_cycles: 0 +mem_stall_cycles: 0 +stall_warp: 0 +wspawn: 1 +stalled: 0 +DEBUG ../core.cpp:386: Core step stepping warp 1[1] +DEBUG ../core.cpp:683: in step pc=0x8000006c +help: in PC: 8000006c +CUrrent CODE: 400513 +DEBUG ../core.cpp:703: Fetched at 0x8000006c +DEBUG ../core.cpp:704: 0x8000006c: i_type; +DEBUG ../instruction.cpp:350: Begin instruction execute. +DEBUG ../instruction.cpp:2117: End instruction execute. +DEBUG ../core.cpp:717: Register state: + %r 0: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r 1: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r 2: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r 3: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r 4: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r 5: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r 6: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r 7: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r 8: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r 9: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r10: 00000004 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r11: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r12: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r13: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r14: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r15: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r16: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r17: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r18: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r19: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r20: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r21: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r22: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r23: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r24: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r25: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r26: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r27: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r28: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r29: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r30: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r31: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) +DEBUG ../core.cpp:726: Thread mask: + 1 0 0 0 0 0 0 0 + + +DEBUG ../core.cpp:388: Now 1 active threads in 1 +********************************** Fetch ********************************* +valid: 1 +PC: 8000006c +wid: 1 +rd: 10 rs1: 0 rs2: -1 +is_lw: 0 +is_sw: 0 +fetch_stall_cycles: 3 +mem_stall_cycles: 0 +stall_warp: 0 +wspawn: 0 +stalled: 0 + + + +------------------------------------------------------ +CYCLE: 14 +Stalled Warps: +0 0 0 0 0 0 0 0 + +********************************** Writeback ********************************* +valid: 1 +PC: 80000004 +wid: 0 +rd: 11 rs1: 11 rs2: -1 +is_lw: 0 +is_sw: 0 +fetch_stall_cycles: 0 +mem_stall_cycles: 0 +stall_warp: 0 +wspawn: 0 +stalled: 0 +********************************** LSU ********************************* +valid: 0 +PC: 0 +wid: 0 +rd: -1 rs1: -1 rs2: -1 +is_lw: 0 +is_sw: 0 +fetch_stall_cycles: 0 +mem_stall_cycles: 0 +stall_warp: 0 +wspawn: 0 +stalled: 0 +********************************** execute_unit ********************************* +valid: 1 +PC: 80000008 +wid: 0 +rd: 10 rs1: 0 rs2: -1 +is_lw: 0 +is_sw: 0 +fetch_stall_cycles: 0 +mem_stall_cycles: 0 +stall_warp: 0 +wspawn: 0 +stalled: 0 +********************************** scheduler ********************************* +valid: 1 +PC: 8000000c +wid: 0 +rd: 0 rs1: 10 rs2: 11 +is_lw: 0 +is_sw: 0 +fetch_stall_cycles: 0 +mem_stall_cycles: 0 +stall_warp: 0 +wspawn: 1 +stalled: 0 +********************************** Decode ********************************* +valid: 0 +PC: 0 +wid: 2 +rd: -1 rs1: -1 rs2: -1 +is_lw: 0 +is_sw: 0 +fetch_stall_cycles: 0 +mem_stall_cycles: 0 +stall_warp: 0 +wspawn: 0 +stalled: 0 +********************************** Fetch ********************************* +valid: 1 +PC: 8000006c +wid: 1 +rd: 10 rs1: 0 rs2: -1 +is_lw: 0 +is_sw: 0 +fetch_stall_cycles: 2 +mem_stall_cycles: 0 +stall_warp: 0 +wspawn: 0 +stalled: 0 + + + +------------------------------------------------------ +CYCLE: 15 +Stalled Warps: +0 0 0 0 0 0 0 0 + +********************************** Writeback ********************************* +valid: 1 +PC: 80000008 +wid: 0 +rd: 10 rs1: 0 rs2: -1 +is_lw: 0 +is_sw: 0 +fetch_stall_cycles: 0 +mem_stall_cycles: 0 +stall_warp: 0 +wspawn: 0 +stalled: 0 +********************************** LSU ********************************* +valid: 0 +PC: 0 +wid: 0 +rd: -1 rs1: -1 rs2: -1 +is_lw: 0 +is_sw: 0 +fetch_stall_cycles: 0 +mem_stall_cycles: 0 +stall_warp: 0 +wspawn: 0 +stalled: 0 +&&&&&&&&&&&&&&&&&&&&&&&& EXECUTE SRCS NOT READY +********************************** execute_unit ********************************* +valid: 0 +PC: 0 +wid: 2 +rd: -1 rs1: -1 rs2: -1 +is_lw: 0 +is_sw: 0 +fetch_stall_cycles: 0 +mem_stall_cycles: 0 +stall_warp: 0 +wspawn: 0 +stalled: 0 +********************************** scheduler ********************************* +valid: 1 +PC: 8000000c +wid: 0 +rd: 0 rs1: 10 rs2: 11 +is_lw: 0 +is_sw: 0 +fetch_stall_cycles: 0 +mem_stall_cycles: 0 +stall_warp: 0 +wspawn: 1 +stalled: 1 +********************************** Decode ********************************* +valid: 0 +PC: 0 +wid: 2 +rd: -1 rs1: -1 rs2: -1 +is_lw: 0 +is_sw: 0 +fetch_stall_cycles: 0 +mem_stall_cycles: 0 +stall_warp: 0 +wspawn: 0 +stalled: 0 +********************************** Fetch ********************************* +valid: 1 +PC: 8000006c +wid: 1 +rd: 10 rs1: 0 rs2: -1 +is_lw: 0 +is_sw: 0 +fetch_stall_cycles: 1 +mem_stall_cycles: 0 +stall_warp: 0 +wspawn: 0 +stalled: 0 + + + +------------------------------------------------------ +CYCLE: 16 +Stalled Warps: +0 0 0 0 0 0 0 0 + +********************************** Writeback ********************************* +valid: 0 +PC: 0 +wid: 2 +rd: -1 rs1: -1 rs2: -1 +is_lw: 0 +is_sw: 0 +fetch_stall_cycles: 0 +mem_stall_cycles: 0 +stall_warp: 0 +wspawn: 0 +stalled: 0 +********************************** LSU ********************************* +valid: 0 +PC: 0 +wid: 0 +rd: -1 rs1: -1 rs2: -1 +is_lw: 0 +is_sw: 0 +fetch_stall_cycles: 0 +mem_stall_cycles: 0 +stall_warp: 0 +wspawn: 0 +stalled: 0 +********************************** execute_unit ********************************* +valid: 1 +PC: 8000000c +wid: 0 +rd: 0 rs1: 10 rs2: 11 +is_lw: 0 +is_sw: 0 +fetch_stall_cycles: 0 +mem_stall_cycles: 0 +stall_warp: 0 +wspawn: 1 +stalled: 0 +********************************** scheduler ********************************* +valid: 0 +PC: 0 +wid: 2 +rd: -1 rs1: -1 rs2: -1 +is_lw: 0 +is_sw: 0 +fetch_stall_cycles: 0 +mem_stall_cycles: 0 +stall_warp: 0 +wspawn: 0 +stalled: 0 +********************************** Decode ********************************* +valid: 0 +PC: 0 +wid: 2 +rd: -1 rs1: -1 rs2: -1 +is_lw: 0 +is_sw: 0 +fetch_stall_cycles: 0 +mem_stall_cycles: 0 +stall_warp: 0 +wspawn: 0 +stalled: 0 +********************************** Fetch ********************************* +valid: 1 +PC: 8000006c +wid: 1 +rd: 10 rs1: 0 rs2: -1 +is_lw: 0 +is_sw: 0 +fetch_stall_cycles: 0 +mem_stall_cycles: 0 +stall_warp: 0 +wspawn: 0 +stalled: 0 + + + +------------------------------------------------------ +CYCLE: 17 +Stalled Warps: +0 0 0 0 0 0 0 0 + +********************************** Writeback ********************************* +valid: 0 +PC: 0 +wid: 2 +rd: -1 rs1: -1 rs2: -1 +is_lw: 0 +is_sw: 0 +fetch_stall_cycles: 0 +mem_stall_cycles: 0 +stall_warp: 0 +wspawn: 0 +stalled: 0 +********************************** LSU ********************************* +valid: 0 +PC: 0 +wid: 0 +rd: -1 rs1: -1 rs2: -1 +is_lw: 0 +is_sw: 0 +fetch_stall_cycles: 0 +mem_stall_cycles: 0 +stall_warp: 0 +wspawn: 0 +stalled: 0 +********************************** execute_unit ********************************* +valid: 0 +PC: 0 +wid: 2 +rd: -1 rs1: -1 rs2: -1 +is_lw: 0 +is_sw: 0 +fetch_stall_cycles: 0 +mem_stall_cycles: 0 +stall_warp: 0 +wspawn: 0 +stalled: 0 +********************************** scheduler ********************************* +valid: 0 +PC: 0 +wid: 2 +rd: -1 rs1: -1 rs2: -1 +is_lw: 0 +is_sw: 0 +fetch_stall_cycles: 0 +mem_stall_cycles: 0 +stall_warp: 0 +wspawn: 0 +stalled: 0 +********************************** Decode ********************************* +valid: 1 +PC: 8000006c +wid: 1 +rd: 10 rs1: 0 rs2: -1 +is_lw: 0 +is_sw: 0 +fetch_stall_cycles: 0 +mem_stall_cycles: 0 +stall_warp: 0 +wspawn: 0 +stalled: 0 +DEBUG ../core.cpp:386: Core step stepping warp 2[1] +DEBUG ../core.cpp:683: in step pc=0x8000006c +help: in PC: 8000006c +CUrrent CODE: 400513 +DEBUG ../core.cpp:703: Fetched at 0x8000006c +DEBUG ../core.cpp:704: 0x8000006c: i_type; +DEBUG ../instruction.cpp:350: Begin instruction execute. +DEBUG ../instruction.cpp:2117: End instruction execute. +DEBUG ../core.cpp:717: Register state: + %r 0: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r 1: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r 2: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r 3: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r 4: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r 5: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r 6: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r 7: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r 8: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r 9: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r10: 00000004 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r11: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r12: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r13: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r14: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r15: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r16: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r17: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r18: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r19: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r20: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r21: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r22: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r23: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r24: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r25: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r26: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r27: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r28: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r29: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r30: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r31: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) +DEBUG ../core.cpp:726: Thread mask: + 1 0 0 0 0 0 0 0 + + +DEBUG ../core.cpp:388: Now 1 active threads in 2 +********************************** Fetch ********************************* +valid: 1 +PC: 8000006c +wid: 2 +rd: 10 rs1: 0 rs2: -1 +is_lw: 0 +is_sw: 0 +fetch_stall_cycles: 0 +mem_stall_cycles: 0 +stall_warp: 0 +wspawn: 0 +stalled: 0 + + + +------------------------------------------------------ +CYCLE: 18 +Stalled Warps: +0 0 0 0 0 0 0 0 + +********************************** Writeback ********************************* +valid: 0 +PC: 0 +wid: 3 +rd: -1 rs1: -1 rs2: -1 +is_lw: 0 +is_sw: 0 +fetch_stall_cycles: 0 +mem_stall_cycles: 0 +stall_warp: 0 +wspawn: 0 +stalled: 0 +********************************** LSU ********************************* +valid: 0 +PC: 0 +wid: 0 +rd: -1 rs1: -1 rs2: -1 +is_lw: 0 +is_sw: 0 +fetch_stall_cycles: 0 +mem_stall_cycles: 0 +stall_warp: 0 +wspawn: 0 +stalled: 0 +********************************** execute_unit ********************************* +valid: 0 +PC: 0 +wid: 2 +rd: -1 rs1: -1 rs2: -1 +is_lw: 0 +is_sw: 0 +fetch_stall_cycles: 0 +mem_stall_cycles: 0 +stall_warp: 0 +wspawn: 0 +stalled: 0 +********************************** scheduler ********************************* +valid: 1 +PC: 8000006c +wid: 1 +rd: 10 rs1: 0 rs2: -1 +is_lw: 0 +is_sw: 0 +fetch_stall_cycles: 0 +mem_stall_cycles: 0 +stall_warp: 0 +wspawn: 0 +stalled: 0 +********************************** Decode ********************************* +valid: 1 +PC: 8000006c +wid: 2 +rd: 10 rs1: 0 rs2: -1 +is_lw: 0 +is_sw: 0 +fetch_stall_cycles: 0 +mem_stall_cycles: 0 +stall_warp: 0 +wspawn: 0 +stalled: 0 +DEBUG ../core.cpp:386: Core step stepping warp 3[1] +DEBUG ../core.cpp:683: in step pc=0x8000006c +help: in PC: 8000006c +CUrrent CODE: 400513 +DEBUG ../core.cpp:703: Fetched at 0x8000006c +DEBUG ../core.cpp:704: 0x8000006c: i_type; +DEBUG ../instruction.cpp:350: Begin instruction execute. +DEBUG ../instruction.cpp:2117: End instruction execute. +DEBUG ../core.cpp:717: Register state: + %r 0: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r 1: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r 2: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r 3: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r 4: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r 5: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r 6: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r 7: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r 8: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r 9: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r10: 00000004 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r11: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r12: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r13: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r14: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r15: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r16: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r17: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r18: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r19: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r20: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r21: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r22: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r23: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r24: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r25: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r26: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r27: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r28: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r29: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r30: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r31: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) +DEBUG ../core.cpp:726: Thread mask: + 1 0 0 0 0 0 0 0 + + +DEBUG ../core.cpp:388: Now 1 active threads in 3 +********************************** Fetch ********************************* +valid: 1 +PC: 8000006c +wid: 3 +rd: 10 rs1: 0 rs2: -1 +is_lw: 0 +is_sw: 0 +fetch_stall_cycles: 0 +mem_stall_cycles: 0 +stall_warp: 0 +wspawn: 0 +stalled: 0 + + + +------------------------------------------------------ +CYCLE: 19 +Stalled Warps: +0 0 0 0 0 0 0 0 + +********************************** Writeback ********************************* +valid: 0 +PC: 0 +wid: 0 +rd: -1 rs1: -1 rs2: -1 +is_lw: 0 +is_sw: 0 +fetch_stall_cycles: 0 +mem_stall_cycles: 0 +stall_warp: 0 +wspawn: 0 +stalled: 0 +********************************** LSU ********************************* +valid: 0 +PC: 0 +wid: 0 +rd: -1 rs1: -1 rs2: -1 +is_lw: 0 +is_sw: 0 +fetch_stall_cycles: 0 +mem_stall_cycles: 0 +stall_warp: 0 +wspawn: 0 +stalled: 0 +********************************** execute_unit ********************************* +valid: 1 +PC: 8000006c +wid: 1 +rd: 10 rs1: 0 rs2: -1 +is_lw: 0 +is_sw: 0 +fetch_stall_cycles: 0 +mem_stall_cycles: 0 +stall_warp: 0 +wspawn: 0 +stalled: 0 +********************************** scheduler ********************************* +valid: 1 +PC: 8000006c +wid: 2 +rd: 10 rs1: 0 rs2: -1 +is_lw: 0 +is_sw: 0 +fetch_stall_cycles: 0 +mem_stall_cycles: 0 +stall_warp: 0 +wspawn: 0 +stalled: 0 +********************************** Decode ********************************* +valid: 1 +PC: 8000006c +wid: 3 +rd: 10 rs1: 0 rs2: -1 +is_lw: 0 +is_sw: 0 +fetch_stall_cycles: 0 +mem_stall_cycles: 0 +stall_warp: 0 +wspawn: 0 +stalled: 0 +DEBUG ../core.cpp:386: Core step stepping warp 0[1] +DEBUG ../core.cpp:683: in step pc=0x80000010 +help: in PC: 80000010 +CUrrent CODE: 5c000ef +DEBUG ../core.cpp:703: Fetched at 0x80000010 +DEBUG ../core.cpp:704: 0x80000010: jal; +DEBUG ../instruction.cpp:350: Begin instruction execute. +DEBUG ../instruction.cpp:2117: End instruction execute. +Next PC: 8000006c +DEBUG ../core.cpp:717: Register state: + %r 0: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r 1: 80000014 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r 2: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r 3: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r 4: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r 5: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r 6: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r 7: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r 8: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r 9: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r10: 00000004 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r11: 8000006c 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r12: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r13: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r14: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r15: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r16: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r17: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r18: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r19: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r20: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r21: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r22: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r23: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r24: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r25: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r26: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r27: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r28: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r29: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r30: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r31: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) +DEBUG ../core.cpp:726: Thread mask: + 1 0 0 0 0 0 0 0 + + +DEBUG ../core.cpp:388: Now 1 active threads in 0 +********************************** Fetch ********************************* +valid: 1 +PC: 80000010 +wid: 0 +rd: 1 rs1: -1 rs2: -1 +is_lw: 0 +is_sw: 0 +fetch_stall_cycles: 3 +mem_stall_cycles: 0 +stall_warp: 1 +wspawn: 0 +stalled: 0 + + + +------------------------------------------------------ +CYCLE: 20 +Stalled Warps: +1 0 0 0 0 0 0 0 + +********************************** Writeback ********************************* +valid: 1 +PC: 8000006c +wid: 1 +rd: 10 rs1: 0 rs2: -1 +is_lw: 0 +is_sw: 0 +fetch_stall_cycles: 0 +mem_stall_cycles: 0 +stall_warp: 0 +wspawn: 0 +stalled: 0 +********************************** LSU ********************************* +valid: 0 +PC: 0 +wid: 0 +rd: -1 rs1: -1 rs2: -1 +is_lw: 0 +is_sw: 0 +fetch_stall_cycles: 0 +mem_stall_cycles: 0 +stall_warp: 0 +wspawn: 0 +stalled: 0 +********************************** execute_unit ********************************* +valid: 1 +PC: 8000006c +wid: 2 +rd: 10 rs1: 0 rs2: -1 +is_lw: 0 +is_sw: 0 +fetch_stall_cycles: 0 +mem_stall_cycles: 0 +stall_warp: 0 +wspawn: 0 +stalled: 0 +********************************** scheduler ********************************* +valid: 1 +PC: 8000006c +wid: 3 +rd: 10 rs1: 0 rs2: -1 +is_lw: 0 +is_sw: 0 +fetch_stall_cycles: 0 +mem_stall_cycles: 0 +stall_warp: 0 +wspawn: 0 +stalled: 0 +********************************** Decode ********************************* +valid: 0 +PC: 0 +wid: 1 +rd: -1 rs1: -1 rs2: -1 +is_lw: 0 +is_sw: 0 +fetch_stall_cycles: 0 +mem_stall_cycles: 0 +stall_warp: 0 +wspawn: 0 +stalled: 0 +********************************** Fetch ********************************* +valid: 1 +PC: 80000010 +wid: 0 +rd: 1 rs1: -1 rs2: -1 +is_lw: 0 +is_sw: 0 +fetch_stall_cycles: 2 +mem_stall_cycles: 0 +stall_warp: 1 +wspawn: 0 +stalled: 0 + + + +------------------------------------------------------ +CYCLE: 21 +Stalled Warps: +1 0 0 0 0 0 0 0 + +********************************** Writeback ********************************* +valid: 1 +PC: 8000006c +wid: 2 +rd: 10 rs1: 0 rs2: -1 +is_lw: 0 +is_sw: 0 +fetch_stall_cycles: 0 +mem_stall_cycles: 0 +stall_warp: 0 +wspawn: 0 +stalled: 0 +********************************** LSU ********************************* +valid: 0 +PC: 0 +wid: 0 +rd: -1 rs1: -1 rs2: -1 +is_lw: 0 +is_sw: 0 +fetch_stall_cycles: 0 +mem_stall_cycles: 0 +stall_warp: 0 +wspawn: 0 +stalled: 0 +********************************** execute_unit ********************************* +valid: 1 +PC: 8000006c +wid: 3 +rd: 10 rs1: 0 rs2: -1 +is_lw: 0 +is_sw: 0 +fetch_stall_cycles: 0 +mem_stall_cycles: 0 +stall_warp: 0 +wspawn: 0 +stalled: 0 +********************************** scheduler ********************************* +valid: 0 +PC: 0 +wid: 1 +rd: -1 rs1: -1 rs2: -1 +is_lw: 0 +is_sw: 0 +fetch_stall_cycles: 0 +mem_stall_cycles: 0 +stall_warp: 0 +wspawn: 0 +stalled: 0 +********************************** Decode ********************************* +valid: 0 +PC: 0 +wid: 1 +rd: -1 rs1: -1 rs2: -1 +is_lw: 0 +is_sw: 0 +fetch_stall_cycles: 0 +mem_stall_cycles: 0 +stall_warp: 0 +wspawn: 0 +stalled: 0 +********************************** Fetch ********************************* +valid: 1 +PC: 80000010 +wid: 0 +rd: 1 rs1: -1 rs2: -1 +is_lw: 0 +is_sw: 0 +fetch_stall_cycles: 1 +mem_stall_cycles: 0 +stall_warp: 1 +wspawn: 0 +stalled: 0 + + + +------------------------------------------------------ +CYCLE: 22 +Stalled Warps: +1 0 0 0 0 0 0 0 + +********************************** Writeback ********************************* +valid: 1 +PC: 8000006c +wid: 3 +rd: 10 rs1: 0 rs2: -1 +is_lw: 0 +is_sw: 0 +fetch_stall_cycles: 0 +mem_stall_cycles: 0 +stall_warp: 0 +wspawn: 0 +stalled: 0 +********************************** LSU ********************************* +valid: 0 +PC: 0 +wid: 0 +rd: -1 rs1: -1 rs2: -1 +is_lw: 0 +is_sw: 0 +fetch_stall_cycles: 0 +mem_stall_cycles: 0 +stall_warp: 0 +wspawn: 0 +stalled: 0 +********************************** execute_unit ********************************* +valid: 0 +PC: 0 +wid: 1 +rd: -1 rs1: -1 rs2: -1 +is_lw: 0 +is_sw: 0 +fetch_stall_cycles: 0 +mem_stall_cycles: 0 +stall_warp: 0 +wspawn: 0 +stalled: 0 +********************************** scheduler ********************************* +valid: 0 +PC: 0 +wid: 1 +rd: -1 rs1: -1 rs2: -1 +is_lw: 0 +is_sw: 0 +fetch_stall_cycles: 0 +mem_stall_cycles: 0 +stall_warp: 0 +wspawn: 0 +stalled: 0 +********************************** Decode ********************************* +valid: 0 +PC: 0 +wid: 1 +rd: -1 rs1: -1 rs2: -1 +is_lw: 0 +is_sw: 0 +fetch_stall_cycles: 0 +mem_stall_cycles: 0 +stall_warp: 0 +wspawn: 0 +stalled: 0 +********************************** Fetch ********************************* +valid: 1 +PC: 80000010 +wid: 0 +rd: 1 rs1: -1 rs2: -1 +is_lw: 0 +is_sw: 0 +fetch_stall_cycles: 0 +mem_stall_cycles: 0 +stall_warp: 1 +wspawn: 0 +stalled: 0 + + + +------------------------------------------------------ +CYCLE: 23 +Stalled Warps: +1 0 0 0 0 0 0 0 + +********************************** Writeback ********************************* +valid: 0 +PC: 0 +wid: 1 +rd: -1 rs1: -1 rs2: -1 +is_lw: 0 +is_sw: 0 +fetch_stall_cycles: 0 +mem_stall_cycles: 0 +stall_warp: 0 +wspawn: 0 +stalled: 0 +********************************** LSU ********************************* +valid: 0 +PC: 0 +wid: 0 +rd: -1 rs1: -1 rs2: -1 +is_lw: 0 +is_sw: 0 +fetch_stall_cycles: 0 +mem_stall_cycles: 0 +stall_warp: 0 +wspawn: 0 +stalled: 0 +********************************** execute_unit ********************************* +valid: 0 +PC: 0 +wid: 1 +rd: -1 rs1: -1 rs2: -1 +is_lw: 0 +is_sw: 0 +fetch_stall_cycles: 0 +mem_stall_cycles: 0 +stall_warp: 0 +wspawn: 0 +stalled: 0 +********************************** scheduler ********************************* +valid: 0 +PC: 0 +wid: 1 +rd: -1 rs1: -1 rs2: -1 +is_lw: 0 +is_sw: 0 +fetch_stall_cycles: 0 +mem_stall_cycles: 0 +stall_warp: 0 +wspawn: 0 +stalled: 0 +********************************** Decode ********************************* +valid: 1 +PC: 80000010 +wid: 0 +rd: 1 rs1: -1 rs2: -1 +is_lw: 0 +is_sw: 0 +fetch_stall_cycles: 0 +mem_stall_cycles: 0 +stall_warp: 1 +wspawn: 0 +stalled: 0 +DEBUG ../core.cpp:386: Core step stepping warp 1[1] +DEBUG ../core.cpp:683: in step pc=0x80000070 +help: in PC: 80000070 +CUrrent CODE: 5006b +DEBUG ../core.cpp:703: Fetched at 0x80000070 +DEBUG ../core.cpp:704: 0x80000070: gpgpu; +DEBUG ../instruction.cpp:350: Begin instruction execute. +DEBUG ../instruction.cpp:2117: End instruction execute. +DEBUG ../core.cpp:717: Register state: + %r 0: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r 1: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r 2: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r 3: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r 4: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r 5: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r 6: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r 7: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r 8: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r 9: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r10: 00000004 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r11: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r12: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r13: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r14: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r15: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r16: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r17: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r18: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r19: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r20: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r21: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r22: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r23: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r24: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r25: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r26: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r27: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r28: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r29: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r30: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r31: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) +DEBUG ../core.cpp:726: Thread mask: + 1 1 1 1 0 0 0 0 + + +DEBUG ../core.cpp:388: Now 4 active threads in 1 +********************************** Fetch ********************************* +valid: 1 +PC: 80000070 +wid: 1 +rd: 0 rs1: 10 rs2: 0 +is_lw: 0 +is_sw: 0 +fetch_stall_cycles: 3 +mem_stall_cycles: 0 +stall_warp: 1 +wspawn: 0 +stalled: 0 + + + +------------------------------------------------------ +CYCLE: 24 +Stalled Warps: +1 1 0 0 0 0 0 0 + +********************************** Writeback ********************************* +valid: 0 +PC: 0 +wid: 2 +rd: -1 rs1: -1 rs2: -1 +is_lw: 0 +is_sw: 0 +fetch_stall_cycles: 0 +mem_stall_cycles: 0 +stall_warp: 0 +wspawn: 0 +stalled: 0 +********************************** LSU ********************************* +valid: 0 +PC: 0 +wid: 0 +rd: -1 rs1: -1 rs2: -1 +is_lw: 0 +is_sw: 0 +fetch_stall_cycles: 0 +mem_stall_cycles: 0 +stall_warp: 0 +wspawn: 0 +stalled: 0 +********************************** execute_unit ********************************* +valid: 0 +PC: 0 +wid: 1 +rd: -1 rs1: -1 rs2: -1 +is_lw: 0 +is_sw: 0 +fetch_stall_cycles: 0 +mem_stall_cycles: 0 +stall_warp: 0 +wspawn: 0 +stalled: 0 +********************************** scheduler ********************************* +valid: 1 +PC: 80000010 +wid: 0 +rd: 1 rs1: -1 rs2: -1 +is_lw: 0 +is_sw: 0 +fetch_stall_cycles: 0 +mem_stall_cycles: 0 +stall_warp: 1 +wspawn: 0 +stalled: 0 +********************************** Decode ********************************* +valid: 0 +PC: 0 +wid: 2 +rd: -1 rs1: -1 rs2: -1 +is_lw: 0 +is_sw: 0 +fetch_stall_cycles: 0 +mem_stall_cycles: 0 +stall_warp: 0 +wspawn: 0 +stalled: 0 +********************************** Fetch ********************************* +valid: 1 +PC: 80000070 +wid: 1 +rd: 0 rs1: 10 rs2: 0 +is_lw: 0 +is_sw: 0 +fetch_stall_cycles: 2 +mem_stall_cycles: 0 +stall_warp: 1 +wspawn: 0 +stalled: 0 + + + +------------------------------------------------------ +CYCLE: 25 +Stalled Warps: +1 1 0 0 0 0 0 0 + +********************************** Writeback ********************************* +valid: 0 +PC: 0 +wid: 2 +rd: -1 rs1: -1 rs2: -1 +is_lw: 0 +is_sw: 0 +fetch_stall_cycles: 0 +mem_stall_cycles: 0 +stall_warp: 0 +wspawn: 0 +stalled: 0 +********************************** LSU ********************************* +valid: 0 +PC: 0 +wid: 0 +rd: -1 rs1: -1 rs2: -1 +is_lw: 0 +is_sw: 0 +fetch_stall_cycles: 0 +mem_stall_cycles: 0 +stall_warp: 0 +wspawn: 0 +stalled: 0 +********************************** execute_unit ********************************* +valid: 1 +PC: 80000010 +wid: 0 +rd: 1 rs1: -1 rs2: -1 +is_lw: 0 +is_sw: 0 +fetch_stall_cycles: 0 +mem_stall_cycles: 0 +stall_warp: 1 +wspawn: 0 +stalled: 0 +********************************** scheduler ********************************* +valid: 0 +PC: 0 +wid: 2 +rd: -1 rs1: -1 rs2: -1 +is_lw: 0 +is_sw: 0 +fetch_stall_cycles: 0 +mem_stall_cycles: 0 +stall_warp: 0 +wspawn: 0 +stalled: 0 +********************************** Decode ********************************* +valid: 0 +PC: 0 +wid: 2 +rd: -1 rs1: -1 rs2: -1 +is_lw: 0 +is_sw: 0 +fetch_stall_cycles: 0 +mem_stall_cycles: 0 +stall_warp: 0 +wspawn: 0 +stalled: 0 +********************************** Fetch ********************************* +valid: 1 +PC: 80000070 +wid: 1 +rd: 0 rs1: 10 rs2: 0 +is_lw: 0 +is_sw: 0 +fetch_stall_cycles: 1 +mem_stall_cycles: 0 +stall_warp: 1 +wspawn: 0 +stalled: 0 + + + +------------------------------------------------------ +CYCLE: 26 +Stalled Warps: +1 1 0 0 0 0 0 0 + +********************************** Writeback ********************************* +valid: 1 +PC: 80000010 +wid: 0 +rd: 1 rs1: -1 rs2: -1 +is_lw: 0 +is_sw: 0 +fetch_stall_cycles: 0 +mem_stall_cycles: 0 +stall_warp: 1 +wspawn: 0 +stalled: 0 +********************************** LSU ********************************* +valid: 0 +PC: 0 +wid: 0 +rd: -1 rs1: -1 rs2: -1 +is_lw: 0 +is_sw: 0 +fetch_stall_cycles: 0 +mem_stall_cycles: 0 +stall_warp: 0 +wspawn: 0 +stalled: 0 +********************************** execute_unit ********************************* +valid: 0 +PC: 0 +wid: 2 +rd: -1 rs1: -1 rs2: -1 +is_lw: 0 +is_sw: 0 +fetch_stall_cycles: 0 +mem_stall_cycles: 0 +stall_warp: 0 +wspawn: 0 +stalled: 0 +********************************** scheduler ********************************* +valid: 0 +PC: 0 +wid: 2 +rd: -1 rs1: -1 rs2: -1 +is_lw: 0 +is_sw: 0 +fetch_stall_cycles: 0 +mem_stall_cycles: 0 +stall_warp: 0 +wspawn: 0 +stalled: 0 +********************************** Decode ********************************* +valid: 0 +PC: 0 +wid: 2 +rd: -1 rs1: -1 rs2: -1 +is_lw: 0 +is_sw: 0 +fetch_stall_cycles: 0 +mem_stall_cycles: 0 +stall_warp: 0 +wspawn: 0 +stalled: 0 +********************************** Fetch ********************************* +valid: 1 +PC: 80000070 +wid: 1 +rd: 0 rs1: 10 rs2: 0 +is_lw: 0 +is_sw: 0 +fetch_stall_cycles: 0 +mem_stall_cycles: 0 +stall_warp: 1 +wspawn: 0 +stalled: 0 + + + +------------------------------------------------------ +CYCLE: 27 +Stalled Warps: +1 1 0 0 0 0 0 0 + +********************************** Writeback ********************************* +valid: 0 +PC: 0 +wid: 2 +rd: -1 rs1: -1 rs2: -1 +is_lw: 0 +is_sw: 0 +fetch_stall_cycles: 0 +mem_stall_cycles: 0 +stall_warp: 0 +wspawn: 0 +stalled: 0 +********************************** LSU ********************************* +valid: 0 +PC: 0 +wid: 0 +rd: -1 rs1: -1 rs2: -1 +is_lw: 0 +is_sw: 0 +fetch_stall_cycles: 0 +mem_stall_cycles: 0 +stall_warp: 0 +wspawn: 0 +stalled: 0 +********************************** execute_unit ********************************* +valid: 0 +PC: 0 +wid: 2 +rd: -1 rs1: -1 rs2: -1 +is_lw: 0 +is_sw: 0 +fetch_stall_cycles: 0 +mem_stall_cycles: 0 +stall_warp: 0 +wspawn: 0 +stalled: 0 +********************************** scheduler ********************************* +valid: 0 +PC: 0 +wid: 2 +rd: -1 rs1: -1 rs2: -1 +is_lw: 0 +is_sw: 0 +fetch_stall_cycles: 0 +mem_stall_cycles: 0 +stall_warp: 0 +wspawn: 0 +stalled: 0 +********************************** Decode ********************************* +valid: 1 +PC: 80000070 +wid: 1 +rd: 0 rs1: 10 rs2: 0 +is_lw: 0 +is_sw: 0 +fetch_stall_cycles: 0 +mem_stall_cycles: 0 +stall_warp: 1 +wspawn: 0 +stalled: 0 +DEBUG ../core.cpp:386: Core step stepping warp 2[1] +DEBUG ../core.cpp:683: in step pc=0x80000070 +help: in PC: 80000070 +CUrrent CODE: 5006b +DEBUG ../core.cpp:703: Fetched at 0x80000070 +DEBUG ../core.cpp:704: 0x80000070: gpgpu; +DEBUG ../instruction.cpp:350: Begin instruction execute. +DEBUG ../instruction.cpp:2117: End instruction execute. +DEBUG ../core.cpp:717: Register state: + %r 0: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r 1: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r 2: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r 3: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r 4: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r 5: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r 6: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r 7: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r 8: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r 9: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r10: 00000004 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r11: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r12: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r13: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r14: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r15: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r16: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r17: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r18: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r19: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r20: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r21: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r22: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r23: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r24: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r25: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r26: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r27: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r28: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r29: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r30: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r31: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) +DEBUG ../core.cpp:726: Thread mask: + 1 1 1 1 0 0 0 0 + + +DEBUG ../core.cpp:388: Now 4 active threads in 2 +********************************** Fetch ********************************* +valid: 1 +PC: 80000070 +wid: 2 +rd: 0 rs1: 10 rs2: 0 +is_lw: 0 +is_sw: 0 +fetch_stall_cycles: 0 +mem_stall_cycles: 0 +stall_warp: 1 +wspawn: 0 +stalled: 0 + + + +------------------------------------------------------ +CYCLE: 28 +Stalled Warps: +0 1 1 0 0 0 0 0 + +********************************** Writeback ********************************* +valid: 0 +PC: 0 +wid: 3 +rd: -1 rs1: -1 rs2: -1 +is_lw: 0 +is_sw: 0 +fetch_stall_cycles: 0 +mem_stall_cycles: 0 +stall_warp: 0 +wspawn: 0 +stalled: 0 +********************************** LSU ********************************* +valid: 0 +PC: 0 +wid: 0 +rd: -1 rs1: -1 rs2: -1 +is_lw: 0 +is_sw: 0 +fetch_stall_cycles: 0 +mem_stall_cycles: 0 +stall_warp: 0 +wspawn: 0 +stalled: 0 +********************************** execute_unit ********************************* +valid: 0 +PC: 0 +wid: 2 +rd: -1 rs1: -1 rs2: -1 +is_lw: 0 +is_sw: 0 +fetch_stall_cycles: 0 +mem_stall_cycles: 0 +stall_warp: 0 +wspawn: 0 +stalled: 0 +********************************** scheduler ********************************* +valid: 1 +PC: 80000070 +wid: 1 +rd: 0 rs1: 10 rs2: 0 +is_lw: 0 +is_sw: 0 +fetch_stall_cycles: 0 +mem_stall_cycles: 0 +stall_warp: 1 +wspawn: 0 +stalled: 0 +********************************** Decode ********************************* +valid: 1 +PC: 80000070 +wid: 2 +rd: 0 rs1: 10 rs2: 0 +is_lw: 0 +is_sw: 0 +fetch_stall_cycles: 0 +mem_stall_cycles: 0 +stall_warp: 1 +wspawn: 0 +stalled: 0 +DEBUG ../core.cpp:386: Core step stepping warp 3[1] +DEBUG ../core.cpp:683: in step pc=0x80000070 +help: in PC: 80000070 +CUrrent CODE: 5006b +DEBUG ../core.cpp:703: Fetched at 0x80000070 +DEBUG ../core.cpp:704: 0x80000070: gpgpu; +DEBUG ../instruction.cpp:350: Begin instruction execute. +DEBUG ../instruction.cpp:2117: End instruction execute. +DEBUG ../core.cpp:717: Register state: + %r 0: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r 1: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r 2: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r 3: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r 4: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r 5: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r 6: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r 7: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r 8: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r 9: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r10: 00000004 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r11: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r12: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r13: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r14: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r15: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r16: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r17: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r18: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r19: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r20: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r21: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r22: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r23: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r24: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r25: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r26: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r27: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r28: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r29: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r30: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r31: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) +DEBUG ../core.cpp:726: Thread mask: + 1 1 1 1 0 0 0 0 + + +DEBUG ../core.cpp:388: Now 4 active threads in 3 +********************************** Fetch ********************************* +valid: 1 +PC: 80000070 +wid: 3 +rd: 0 rs1: 10 rs2: 0 +is_lw: 0 +is_sw: 0 +fetch_stall_cycles: 0 +mem_stall_cycles: 0 +stall_warp: 1 +wspawn: 0 +stalled: 0 + + + +------------------------------------------------------ +CYCLE: 29 +Stalled Warps: +0 1 1 1 0 0 0 0 + +********************************** Writeback ********************************* +valid: 0 +PC: 0 +wid: 0 +rd: -1 rs1: -1 rs2: -1 +is_lw: 0 +is_sw: 0 +fetch_stall_cycles: 0 +mem_stall_cycles: 0 +stall_warp: 0 +wspawn: 0 +stalled: 0 +********************************** LSU ********************************* +valid: 0 +PC: 0 +wid: 0 +rd: -1 rs1: -1 rs2: -1 +is_lw: 0 +is_sw: 0 +fetch_stall_cycles: 0 +mem_stall_cycles: 0 +stall_warp: 0 +wspawn: 0 +stalled: 0 +********************************** execute_unit ********************************* +valid: 1 +PC: 80000070 +wid: 1 +rd: 0 rs1: 10 rs2: 0 +is_lw: 0 +is_sw: 0 +fetch_stall_cycles: 0 +mem_stall_cycles: 0 +stall_warp: 1 +wspawn: 0 +stalled: 0 +********************************** scheduler ********************************* +valid: 1 +PC: 80000070 +wid: 2 +rd: 0 rs1: 10 rs2: 0 +is_lw: 0 +is_sw: 0 +fetch_stall_cycles: 0 +mem_stall_cycles: 0 +stall_warp: 1 +wspawn: 0 +stalled: 0 +********************************** Decode ********************************* +valid: 1 +PC: 80000070 +wid: 3 +rd: 0 rs1: 10 rs2: 0 +is_lw: 0 +is_sw: 0 +fetch_stall_cycles: 0 +mem_stall_cycles: 0 +stall_warp: 1 +wspawn: 0 +stalled: 0 +DEBUG ../core.cpp:386: Core step stepping warp 0[1] +DEBUG ../core.cpp:683: in step pc=0x8000006c +help: in PC: 8000006c +CUrrent CODE: 400513 +DEBUG ../core.cpp:703: Fetched at 0x8000006c +DEBUG ../core.cpp:704: 0x8000006c: i_type; +DEBUG ../instruction.cpp:350: Begin instruction execute. +DEBUG ../instruction.cpp:2117: End instruction execute. +DEBUG ../core.cpp:717: Register state: + %r 0: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r 1: 80000014 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r 2: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r 3: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r 4: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r 5: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r 6: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r 7: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r 8: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r 9: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r10: 00000004 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r11: 8000006c 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r12: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r13: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r14: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r15: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r16: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r17: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r18: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r19: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r20: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r21: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r22: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r23: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r24: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r25: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r26: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r27: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r28: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r29: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r30: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r31: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) +DEBUG ../core.cpp:726: Thread mask: + 1 0 0 0 0 0 0 0 + + +DEBUG ../core.cpp:388: Now 1 active threads in 0 +********************************** Fetch ********************************* +valid: 1 +PC: 8000006c +wid: 0 +rd: 10 rs1: 0 rs2: -1 +is_lw: 0 +is_sw: 0 +fetch_stall_cycles: 0 +mem_stall_cycles: 0 +stall_warp: 0 +wspawn: 0 +stalled: 0 + + + +------------------------------------------------------ +CYCLE: 30 +Stalled Warps: +0 1 1 1 0 0 0 0 + +********************************** Writeback ********************************* +valid: 1 +PC: 80000070 +wid: 1 +rd: 0 rs1: 10 rs2: 0 +is_lw: 0 +is_sw: 0 +fetch_stall_cycles: 0 +mem_stall_cycles: 0 +stall_warp: 1 +wspawn: 0 +stalled: 0 +********************************** LSU ********************************* +valid: 0 +PC: 0 +wid: 0 +rd: -1 rs1: -1 rs2: -1 +is_lw: 0 +is_sw: 0 +fetch_stall_cycles: 0 +mem_stall_cycles: 0 +stall_warp: 0 +wspawn: 0 +stalled: 0 +********************************** execute_unit ********************************* +valid: 1 +PC: 80000070 +wid: 2 +rd: 0 rs1: 10 rs2: 0 +is_lw: 0 +is_sw: 0 +fetch_stall_cycles: 0 +mem_stall_cycles: 0 +stall_warp: 1 +wspawn: 0 +stalled: 0 +********************************** scheduler ********************************* +valid: 1 +PC: 80000070 +wid: 3 +rd: 0 rs1: 10 rs2: 0 +is_lw: 0 +is_sw: 0 +fetch_stall_cycles: 0 +mem_stall_cycles: 0 +stall_warp: 1 +wspawn: 0 +stalled: 0 +********************************** Decode ********************************* +valid: 1 +PC: 8000006c +wid: 0 +rd: 10 rs1: 0 rs2: -1 +is_lw: 0 +is_sw: 0 +fetch_stall_cycles: 0 +mem_stall_cycles: 0 +stall_warp: 0 +wspawn: 0 +stalled: 0 +DEBUG ../core.cpp:386: Core step stepping warp 0[1] +DEBUG ../core.cpp:683: in step pc=0x80000070 +help: in PC: 80000070 +CUrrent CODE: 5006b +DEBUG ../core.cpp:703: Fetched at 0x80000070 +DEBUG ../core.cpp:704: 0x80000070: gpgpu; +DEBUG ../instruction.cpp:350: Begin instruction execute. +DEBUG ../instruction.cpp:2117: End instruction execute. +DEBUG ../core.cpp:717: Register state: + %r 0: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r 1: 80000014 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r 2: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r 3: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r 4: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r 5: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r 6: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r 7: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r 8: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r 9: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r10: 00000004 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r11: 8000006c 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r12: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r13: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r14: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r15: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r16: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r17: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r18: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r19: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r20: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r21: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r22: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r23: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r24: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r25: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r26: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r27: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r28: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r29: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r30: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r31: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) +DEBUG ../core.cpp:726: Thread mask: + 1 1 1 1 0 0 0 0 + + +DEBUG ../core.cpp:388: Now 4 active threads in 0 +********************************** Fetch ********************************* +valid: 1 +PC: 80000070 +wid: 0 +rd: 0 rs1: 10 rs2: 0 +is_lw: 0 +is_sw: 0 +fetch_stall_cycles: 0 +mem_stall_cycles: 0 +stall_warp: 1 +wspawn: 0 +stalled: 0 + + + +------------------------------------------------------ +CYCLE: 31 +Stalled Warps: +1 1 1 1 0 0 0 0 + +********************************** Writeback ********************************* +valid: 1 +PC: 80000070 +wid: 2 +rd: 0 rs1: 10 rs2: 0 +is_lw: 0 +is_sw: 0 +fetch_stall_cycles: 0 +mem_stall_cycles: 0 +stall_warp: 1 +wspawn: 0 +stalled: 0 +********************************** LSU ********************************* +valid: 0 +PC: 0 +wid: 0 +rd: -1 rs1: -1 rs2: -1 +is_lw: 0 +is_sw: 0 +fetch_stall_cycles: 0 +mem_stall_cycles: 0 +stall_warp: 0 +wspawn: 0 +stalled: 0 +********************************** execute_unit ********************************* +valid: 1 +PC: 80000070 +wid: 3 +rd: 0 rs1: 10 rs2: 0 +is_lw: 0 +is_sw: 0 +fetch_stall_cycles: 0 +mem_stall_cycles: 0 +stall_warp: 1 +wspawn: 0 +stalled: 0 +********************************** scheduler ********************************* +valid: 1 +PC: 8000006c +wid: 0 +rd: 10 rs1: 0 rs2: -1 +is_lw: 0 +is_sw: 0 +fetch_stall_cycles: 0 +mem_stall_cycles: 0 +stall_warp: 0 +wspawn: 0 +stalled: 0 +********************************** Decode ********************************* +valid: 1 +PC: 80000070 +wid: 0 +rd: 0 rs1: 10 rs2: 0 +is_lw: 0 +is_sw: 0 +fetch_stall_cycles: 0 +mem_stall_cycles: 0 +stall_warp: 1 +wspawn: 0 +stalled: 0 +********************************** Fetch ********************************* +valid: 0 +PC: 0 +wid: 1 +rd: -1 rs1: -1 rs2: -1 +is_lw: 0 +is_sw: 0 +fetch_stall_cycles: 0 +mem_stall_cycles: 0 +stall_warp: 0 +wspawn: 0 +stalled: 0 + + + +------------------------------------------------------ +CYCLE: 32 +Stalled Warps: +1 0 1 1 0 0 0 0 + +********************************** Writeback ********************************* +valid: 1 +PC: 80000070 +wid: 3 +rd: 0 rs1: 10 rs2: 0 +is_lw: 0 +is_sw: 0 +fetch_stall_cycles: 0 +mem_stall_cycles: 0 +stall_warp: 1 +wspawn: 0 +stalled: 0 +********************************** LSU ********************************* +valid: 0 +PC: 0 +wid: 0 +rd: -1 rs1: -1 rs2: -1 +is_lw: 0 +is_sw: 0 +fetch_stall_cycles: 0 +mem_stall_cycles: 0 +stall_warp: 0 +wspawn: 0 +stalled: 0 +********************************** execute_unit ********************************* +valid: 1 +PC: 8000006c +wid: 0 +rd: 10 rs1: 0 rs2: -1 +is_lw: 0 +is_sw: 0 +fetch_stall_cycles: 0 +mem_stall_cycles: 0 +stall_warp: 0 +wspawn: 0 +stalled: 0 +********************************** scheduler ********************************* +valid: 1 +PC: 80000070 +wid: 0 +rd: 0 rs1: 10 rs2: 0 +is_lw: 0 +is_sw: 0 +fetch_stall_cycles: 0 +mem_stall_cycles: 0 +stall_warp: 1 +wspawn: 0 +stalled: 0 +********************************** Decode ********************************* +valid: 0 +PC: 0 +wid: 1 +rd: -1 rs1: -1 rs2: -1 +is_lw: 0 +is_sw: 0 +fetch_stall_cycles: 0 +mem_stall_cycles: 0 +stall_warp: 0 +wspawn: 0 +stalled: 0 +DEBUG ../core.cpp:386: Core step stepping warp 1[4] +DEBUG ../core.cpp:683: in step pc=0x80000074 +help: in PC: 80000074 +CUrrent CODE: 1197 +DEBUG ../core.cpp:703: Fetched at 0x80000074 +DEBUG ../core.cpp:704: 0x80000074: auipc; +DEBUG ../instruction.cpp:350: Begin instruction execute. +DEBUG ../instruction.cpp:2117: End instruction execute. +DEBUG ../core.cpp:717: Register state: + %r 0: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r 1: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r 2: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r 3: 80001074 80001074 80001074 80001074 00000000 00000000 00000000 00000000 (0) + %r 4: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r 5: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r 6: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r 7: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r 8: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r 9: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r10: 00000004 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r11: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r12: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r13: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r14: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r15: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r16: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r17: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r18: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r19: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r20: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r21: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r22: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r23: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r24: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r25: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r26: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r27: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r28: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r29: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r30: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r31: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) +DEBUG ../core.cpp:726: Thread mask: + 1 1 1 1 0 0 0 0 + + +DEBUG ../core.cpp:388: Now 4 active threads in 1 +********************************** Fetch ********************************* +valid: 1 +PC: 80000074 +wid: 1 +rd: 3 rs1: -1 rs2: -1 +is_lw: 0 +is_sw: 0 +fetch_stall_cycles: 0 +mem_stall_cycles: 0 +stall_warp: 0 +wspawn: 0 +stalled: 0 + + + +------------------------------------------------------ +CYCLE: 33 +Stalled Warps: +1 0 0 1 0 0 0 0 + +********************************** Writeback ********************************* +valid: 1 +PC: 8000006c +wid: 0 +rd: 10 rs1: 0 rs2: -1 +is_lw: 0 +is_sw: 0 +fetch_stall_cycles: 0 +mem_stall_cycles: 0 +stall_warp: 0 +wspawn: 0 +stalled: 0 +********************************** LSU ********************************* +valid: 0 +PC: 0 +wid: 0 +rd: -1 rs1: -1 rs2: -1 +is_lw: 0 +is_sw: 0 +fetch_stall_cycles: 0 +mem_stall_cycles: 0 +stall_warp: 0 +wspawn: 0 +stalled: 0 +&&&&&&&&&&&&&&&&&&&&&&&& EXECUTE SRCS NOT READY +********************************** execute_unit ********************************* +valid: 0 +PC: 0 +wid: 2 +rd: -1 rs1: -1 rs2: -1 +is_lw: 0 +is_sw: 0 +fetch_stall_cycles: 0 +mem_stall_cycles: 0 +stall_warp: 0 +wspawn: 0 +stalled: 0 +********************************** scheduler ********************************* +valid: 1 +PC: 80000070 +wid: 0 +rd: 0 rs1: 10 rs2: 0 +is_lw: 0 +is_sw: 0 +fetch_stall_cycles: 0 +mem_stall_cycles: 0 +stall_warp: 1 +wspawn: 0 +stalled: 1 +********************************** Decode ********************************* +valid: 0 +PC: 0 +wid: 1 +rd: -1 rs1: -1 rs2: -1 +is_lw: 0 +is_sw: 0 +fetch_stall_cycles: 0 +mem_stall_cycles: 0 +stall_warp: 0 +wspawn: 0 +stalled: 0 +********************************** Fetch ********************************* +valid: 1 +PC: 80000074 +wid: 1 +rd: 3 rs1: -1 rs2: -1 +is_lw: 0 +is_sw: 0 +fetch_stall_cycles: 0 +mem_stall_cycles: 0 +stall_warp: 0 +wspawn: 0 +stalled: 0 + + + +------------------------------------------------------ +CYCLE: 34 +Stalled Warps: +1 0 0 0 0 0 0 0 + +********************************** Writeback ********************************* +valid: 0 +PC: 0 +wid: 2 +rd: -1 rs1: -1 rs2: -1 +is_lw: 0 +is_sw: 0 +fetch_stall_cycles: 0 +mem_stall_cycles: 0 +stall_warp: 0 +wspawn: 0 +stalled: 0 +********************************** LSU ********************************* +valid: 0 +PC: 0 +wid: 0 +rd: -1 rs1: -1 rs2: -1 +is_lw: 0 +is_sw: 0 +fetch_stall_cycles: 0 +mem_stall_cycles: 0 +stall_warp: 0 +wspawn: 0 +stalled: 0 +********************************** execute_unit ********************************* +valid: 1 +PC: 80000070 +wid: 0 +rd: 0 rs1: 10 rs2: 0 +is_lw: 0 +is_sw: 0 +fetch_stall_cycles: 0 +mem_stall_cycles: 0 +stall_warp: 1 +wspawn: 0 +stalled: 0 +********************************** scheduler ********************************* +valid: 0 +PC: 0 +wid: 1 +rd: -1 rs1: -1 rs2: -1 +is_lw: 0 +is_sw: 0 +fetch_stall_cycles: 0 +mem_stall_cycles: 0 +stall_warp: 0 +wspawn: 0 +stalled: 0 +********************************** Decode ********************************* +valid: 1 +PC: 80000074 +wid: 1 +rd: 3 rs1: -1 rs2: -1 +is_lw: 0 +is_sw: 0 +fetch_stall_cycles: 0 +mem_stall_cycles: 0 +stall_warp: 0 +wspawn: 0 +stalled: 0 +DEBUG ../core.cpp:386: Core step stepping warp 2[4] +DEBUG ../core.cpp:683: in step pc=0x80000074 +help: in PC: 80000074 +CUrrent CODE: 1197 +DEBUG ../core.cpp:703: Fetched at 0x80000074 +DEBUG ../core.cpp:704: 0x80000074: auipc; +DEBUG ../instruction.cpp:350: Begin instruction execute. +DEBUG ../instruction.cpp:2117: End instruction execute. +DEBUG ../core.cpp:717: Register state: + %r 0: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r 1: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r 2: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r 3: 80001074 80001074 80001074 80001074 00000000 00000000 00000000 00000000 (0) + %r 4: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r 5: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r 6: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r 7: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r 8: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r 9: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r10: 00000004 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r11: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r12: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r13: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r14: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r15: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r16: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r17: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r18: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r19: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r20: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r21: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r22: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r23: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r24: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r25: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r26: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r27: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r28: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r29: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r30: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r31: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) +DEBUG ../core.cpp:726: Thread mask: + 1 1 1 1 0 0 0 0 + + +DEBUG ../core.cpp:388: Now 4 active threads in 2 +********************************** Fetch ********************************* +valid: 1 +PC: 80000074 +wid: 2 +rd: 3 rs1: -1 rs2: -1 +is_lw: 0 +is_sw: 0 +fetch_stall_cycles: 0 +mem_stall_cycles: 0 +stall_warp: 0 +wspawn: 0 +stalled: 0 + + + +------------------------------------------------------ +CYCLE: 35 +Stalled Warps: +1 0 0 0 0 0 0 0 + +********************************** Writeback ********************************* +valid: 1 +PC: 80000070 +wid: 0 +rd: 0 rs1: 10 rs2: 0 +is_lw: 0 +is_sw: 0 +fetch_stall_cycles: 0 +mem_stall_cycles: 0 +stall_warp: 1 +wspawn: 0 +stalled: 0 +********************************** LSU ********************************* +valid: 0 +PC: 0 +wid: 0 +rd: -1 rs1: -1 rs2: -1 +is_lw: 0 +is_sw: 0 +fetch_stall_cycles: 0 +mem_stall_cycles: 0 +stall_warp: 0 +wspawn: 0 +stalled: 0 +********************************** execute_unit ********************************* +valid: 0 +PC: 0 +wid: 1 +rd: -1 rs1: -1 rs2: -1 +is_lw: 0 +is_sw: 0 +fetch_stall_cycles: 0 +mem_stall_cycles: 0 +stall_warp: 0 +wspawn: 0 +stalled: 0 +********************************** scheduler ********************************* +valid: 1 +PC: 80000074 +wid: 1 +rd: 3 rs1: -1 rs2: -1 +is_lw: 0 +is_sw: 0 +fetch_stall_cycles: 0 +mem_stall_cycles: 0 +stall_warp: 0 +wspawn: 0 +stalled: 0 +********************************** Decode ********************************* +valid: 1 +PC: 80000074 +wid: 2 +rd: 3 rs1: -1 rs2: -1 +is_lw: 0 +is_sw: 0 +fetch_stall_cycles: 0 +mem_stall_cycles: 0 +stall_warp: 0 +wspawn: 0 +stalled: 0 +DEBUG ../core.cpp:386: Core step stepping warp 3[4] +DEBUG ../core.cpp:683: in step pc=0x80000074 +help: in PC: 80000074 +CUrrent CODE: 1197 +DEBUG ../core.cpp:703: Fetched at 0x80000074 +DEBUG ../core.cpp:704: 0x80000074: auipc; +DEBUG ../instruction.cpp:350: Begin instruction execute. +DEBUG ../instruction.cpp:2117: End instruction execute. +DEBUG ../core.cpp:717: Register state: + %r 0: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r 1: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r 2: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r 3: 80001074 80001074 80001074 80001074 00000000 00000000 00000000 00000000 (0) + %r 4: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r 5: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r 6: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r 7: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r 8: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r 9: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r10: 00000004 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r11: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r12: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r13: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r14: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r15: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r16: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r17: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r18: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r19: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r20: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r21: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r22: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r23: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r24: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r25: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r26: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r27: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r28: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r29: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r30: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r31: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) +DEBUG ../core.cpp:726: Thread mask: + 1 1 1 1 0 0 0 0 + + +DEBUG ../core.cpp:388: Now 4 active threads in 3 +********************************** Fetch ********************************* +valid: 1 +PC: 80000074 +wid: 3 +rd: 3 rs1: -1 rs2: -1 +is_lw: 0 +is_sw: 0 +fetch_stall_cycles: 0 +mem_stall_cycles: 0 +stall_warp: 0 +wspawn: 0 +stalled: 0 + + + +------------------------------------------------------ +CYCLE: 36 +Stalled Warps: +1 0 0 0 0 0 0 0 + +********************************** Writeback ********************************* +valid: 0 +PC: 0 +wid: 1 +rd: -1 rs1: -1 rs2: -1 +is_lw: 0 +is_sw: 0 +fetch_stall_cycles: 0 +mem_stall_cycles: 0 +stall_warp: 0 +wspawn: 0 +stalled: 0 +********************************** LSU ********************************* +valid: 0 +PC: 0 +wid: 0 +rd: -1 rs1: -1 rs2: -1 +is_lw: 0 +is_sw: 0 +fetch_stall_cycles: 0 +mem_stall_cycles: 0 +stall_warp: 0 +wspawn: 0 +stalled: 0 +********************************** execute_unit ********************************* +valid: 1 +PC: 80000074 +wid: 1 +rd: 3 rs1: -1 rs2: -1 +is_lw: 0 +is_sw: 0 +fetch_stall_cycles: 0 +mem_stall_cycles: 0 +stall_warp: 0 +wspawn: 0 +stalled: 0 +********************************** scheduler ********************************* +valid: 1 +PC: 80000074 +wid: 2 +rd: 3 rs1: -1 rs2: -1 +is_lw: 0 +is_sw: 0 +fetch_stall_cycles: 0 +mem_stall_cycles: 0 +stall_warp: 0 +wspawn: 0 +stalled: 0 +********************************** Decode ********************************* +valid: 1 +PC: 80000074 +wid: 3 +rd: 3 rs1: -1 rs2: -1 +is_lw: 0 +is_sw: 0 +fetch_stall_cycles: 0 +mem_stall_cycles: 0 +stall_warp: 0 +wspawn: 0 +stalled: 0 +DEBUG ../core.cpp:386: Core step stepping warp 1[4] +DEBUG ../core.cpp:683: in step pc=0x80000078 +help: in PC: 80000078 +CUrrent CODE: 79418193 +DEBUG ../core.cpp:703: Fetched at 0x80000078 +DEBUG ../core.cpp:704: 0x80000078: i_type; +DEBUG ../instruction.cpp:350: Begin instruction execute. +DEBUG ../instruction.cpp:2117: End instruction execute. +DEBUG ../core.cpp:717: Register state: + %r 0: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r 1: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r 2: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r 3: 80001808 80001808 80001808 80001808 00000000 00000000 00000000 00000000 (0) + %r 4: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r 5: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r 6: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r 7: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r 8: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r 9: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r10: 00000004 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r11: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r12: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r13: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r14: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r15: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r16: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r17: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r18: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r19: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r20: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r21: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r22: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r23: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r24: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r25: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r26: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r27: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r28: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r29: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r30: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r31: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) +DEBUG ../core.cpp:726: Thread mask: + 1 1 1 1 0 0 0 0 + + +DEBUG ../core.cpp:388: Now 4 active threads in 1 +********************************** Fetch ********************************* +valid: 1 +PC: 80000078 +wid: 1 +rd: 3 rs1: 3 rs2: -1 +is_lw: 0 +is_sw: 0 +fetch_stall_cycles: 0 +mem_stall_cycles: 0 +stall_warp: 0 +wspawn: 0 +stalled: 0 + + + +------------------------------------------------------ +CYCLE: 37 +Stalled Warps: +0 0 0 0 0 0 0 0 + +********************************** Writeback ********************************* +valid: 1 +PC: 80000074 +wid: 1 +rd: 3 rs1: -1 rs2: -1 +is_lw: 0 +is_sw: 0 +fetch_stall_cycles: 0 +mem_stall_cycles: 0 +stall_warp: 0 +wspawn: 0 +stalled: 0 +********************************** LSU ********************************* +valid: 0 +PC: 0 +wid: 0 +rd: -1 rs1: -1 rs2: -1 +is_lw: 0 +is_sw: 0 +fetch_stall_cycles: 0 +mem_stall_cycles: 0 +stall_warp: 0 +wspawn: 0 +stalled: 0 +********************************** execute_unit ********************************* +valid: 1 +PC: 80000074 +wid: 2 +rd: 3 rs1: -1 rs2: -1 +is_lw: 0 +is_sw: 0 +fetch_stall_cycles: 0 +mem_stall_cycles: 0 +stall_warp: 0 +wspawn: 0 +stalled: 0 +********************************** scheduler ********************************* +valid: 1 +PC: 80000074 +wid: 3 +rd: 3 rs1: -1 rs2: -1 +is_lw: 0 +is_sw: 0 +fetch_stall_cycles: 0 +mem_stall_cycles: 0 +stall_warp: 0 +wspawn: 0 +stalled: 0 +********************************** Decode ********************************* +valid: 1 +PC: 80000078 +wid: 1 +rd: 3 rs1: 3 rs2: -1 +is_lw: 0 +is_sw: 0 +fetch_stall_cycles: 0 +mem_stall_cycles: 0 +stall_warp: 0 +wspawn: 0 +stalled: 0 +DEBUG ../core.cpp:386: Core step stepping warp 2[4] +DEBUG ../core.cpp:683: in step pc=0x80000078 +help: in PC: 80000078 +CUrrent CODE: 79418193 +DEBUG ../core.cpp:703: Fetched at 0x80000078 +DEBUG ../core.cpp:704: 0x80000078: i_type; +DEBUG ../instruction.cpp:350: Begin instruction execute. +DEBUG ../instruction.cpp:2117: End instruction execute. +DEBUG ../core.cpp:717: Register state: + %r 0: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r 1: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r 2: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r 3: 80001808 80001808 80001808 80001808 00000000 00000000 00000000 00000000 (0) + %r 4: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r 5: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r 6: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r 7: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r 8: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r 9: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r10: 00000004 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r11: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r12: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r13: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r14: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r15: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r16: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r17: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r18: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r19: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r20: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r21: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r22: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r23: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r24: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r25: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r26: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r27: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r28: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r29: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r30: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r31: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) +DEBUG ../core.cpp:726: Thread mask: + 1 1 1 1 0 0 0 0 + + +DEBUG ../core.cpp:388: Now 4 active threads in 2 +********************************** Fetch ********************************* +valid: 1 +PC: 80000078 +wid: 2 +rd: 3 rs1: 3 rs2: -1 +is_lw: 0 +is_sw: 0 +fetch_stall_cycles: 0 +mem_stall_cycles: 0 +stall_warp: 0 +wspawn: 0 +stalled: 0 + + + +------------------------------------------------------ +CYCLE: 38 +Stalled Warps: +0 0 0 0 0 0 0 0 + +********************************** Writeback ********************************* +valid: 1 +PC: 80000074 +wid: 2 +rd: 3 rs1: -1 rs2: -1 +is_lw: 0 +is_sw: 0 +fetch_stall_cycles: 0 +mem_stall_cycles: 0 +stall_warp: 0 +wspawn: 0 +stalled: 0 +********************************** LSU ********************************* +valid: 0 +PC: 0 +wid: 0 +rd: -1 rs1: -1 rs2: -1 +is_lw: 0 +is_sw: 0 +fetch_stall_cycles: 0 +mem_stall_cycles: 0 +stall_warp: 0 +wspawn: 0 +stalled: 0 +********************************** execute_unit ********************************* +valid: 1 +PC: 80000074 +wid: 3 +rd: 3 rs1: -1 rs2: -1 +is_lw: 0 +is_sw: 0 +fetch_stall_cycles: 0 +mem_stall_cycles: 0 +stall_warp: 0 +wspawn: 0 +stalled: 0 +********************************** scheduler ********************************* +valid: 1 +PC: 80000078 +wid: 1 +rd: 3 rs1: 3 rs2: -1 +is_lw: 0 +is_sw: 0 +fetch_stall_cycles: 0 +mem_stall_cycles: 0 +stall_warp: 0 +wspawn: 0 +stalled: 0 +********************************** Decode ********************************* +valid: 1 +PC: 80000078 +wid: 2 +rd: 3 rs1: 3 rs2: -1 +is_lw: 0 +is_sw: 0 +fetch_stall_cycles: 0 +mem_stall_cycles: 0 +stall_warp: 0 +wspawn: 0 +stalled: 0 +DEBUG ../core.cpp:386: Core step stepping warp 3[4] +DEBUG ../core.cpp:683: in step pc=0x80000078 +help: in PC: 80000078 +CUrrent CODE: 79418193 +DEBUG ../core.cpp:703: Fetched at 0x80000078 +DEBUG ../core.cpp:704: 0x80000078: i_type; +DEBUG ../instruction.cpp:350: Begin instruction execute. +DEBUG ../instruction.cpp:2117: End instruction execute. +DEBUG ../core.cpp:717: Register state: + %r 0: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r 1: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r 2: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r 3: 80001808 80001808 80001808 80001808 00000000 00000000 00000000 00000000 (0) + %r 4: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r 5: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r 6: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r 7: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r 8: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r 9: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r10: 00000004 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r11: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r12: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r13: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r14: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r15: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r16: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r17: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r18: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r19: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r20: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r21: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r22: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r23: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r24: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r25: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r26: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r27: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r28: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r29: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r30: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r31: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) +DEBUG ../core.cpp:726: Thread mask: + 1 1 1 1 0 0 0 0 + + +DEBUG ../core.cpp:388: Now 4 active threads in 3 +********************************** Fetch ********************************* +valid: 1 +PC: 80000078 +wid: 3 +rd: 3 rs1: 3 rs2: -1 +is_lw: 0 +is_sw: 0 +fetch_stall_cycles: 0 +mem_stall_cycles: 0 +stall_warp: 0 +wspawn: 0 +stalled: 0 + + + +------------------------------------------------------ +CYCLE: 39 +Stalled Warps: +0 0 0 0 0 0 0 0 + +********************************** Writeback ********************************* +valid: 1 +PC: 80000074 +wid: 3 +rd: 3 rs1: -1 rs2: -1 +is_lw: 0 +is_sw: 0 +fetch_stall_cycles: 0 +mem_stall_cycles: 0 +stall_warp: 0 +wspawn: 0 +stalled: 0 +********************************** LSU ********************************* +valid: 0 +PC: 0 +wid: 0 +rd: -1 rs1: -1 rs2: -1 +is_lw: 0 +is_sw: 0 +fetch_stall_cycles: 0 +mem_stall_cycles: 0 +stall_warp: 0 +wspawn: 0 +stalled: 0 +********************************** execute_unit ********************************* +valid: 1 +PC: 80000078 +wid: 1 +rd: 3 rs1: 3 rs2: -1 +is_lw: 0 +is_sw: 0 +fetch_stall_cycles: 0 +mem_stall_cycles: 0 +stall_warp: 0 +wspawn: 0 +stalled: 0 +********************************** scheduler ********************************* +valid: 1 +PC: 80000078 +wid: 2 +rd: 3 rs1: 3 rs2: -1 +is_lw: 0 +is_sw: 0 +fetch_stall_cycles: 0 +mem_stall_cycles: 0 +stall_warp: 0 +wspawn: 0 +stalled: 0 +********************************** Decode ********************************* +valid: 1 +PC: 80000078 +wid: 3 +rd: 3 rs1: 3 rs2: -1 +is_lw: 0 +is_sw: 0 +fetch_stall_cycles: 0 +mem_stall_cycles: 0 +stall_warp: 0 +wspawn: 0 +stalled: 0 +DEBUG ../core.cpp:386: Core step stepping warp 0[4] +DEBUG ../core.cpp:683: in step pc=0x80000074 +help: in PC: 80000074 +CUrrent CODE: 1197 +DEBUG ../core.cpp:703: Fetched at 0x80000074 +DEBUG ../core.cpp:704: 0x80000074: auipc; +DEBUG ../instruction.cpp:350: Begin instruction execute. +DEBUG ../instruction.cpp:2117: End instruction execute. +DEBUG ../core.cpp:717: Register state: + %r 0: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r 1: 80000014 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r 2: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r 3: 80001074 80001074 80001074 80001074 00000000 00000000 00000000 00000000 (0) + %r 4: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r 5: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r 6: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r 7: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r 8: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r 9: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r10: 00000004 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r11: 8000006c 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r12: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r13: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r14: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r15: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r16: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r17: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r18: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r19: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r20: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r21: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r22: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r23: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r24: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r25: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r26: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r27: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r28: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r29: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r30: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r31: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) +DEBUG ../core.cpp:726: Thread mask: + 1 1 1 1 0 0 0 0 + + +DEBUG ../core.cpp:388: Now 4 active threads in 0 +********************************** Fetch ********************************* +valid: 1 +PC: 80000074 +wid: 0 +rd: 3 rs1: -1 rs2: -1 +is_lw: 0 +is_sw: 0 +fetch_stall_cycles: 0 +mem_stall_cycles: 0 +stall_warp: 0 +wspawn: 0 +stalled: 0 + + + +------------------------------------------------------ +CYCLE: 40 +Stalled Warps: +0 0 0 0 0 0 0 0 + +********************************** Writeback ********************************* +valid: 1 +PC: 80000078 +wid: 1 +rd: 3 rs1: 3 rs2: -1 +is_lw: 0 +is_sw: 0 +fetch_stall_cycles: 0 +mem_stall_cycles: 0 +stall_warp: 0 +wspawn: 0 +stalled: 0 +********************************** LSU ********************************* +valid: 0 +PC: 0 +wid: 0 +rd: -1 rs1: -1 rs2: -1 +is_lw: 0 +is_sw: 0 +fetch_stall_cycles: 0 +mem_stall_cycles: 0 +stall_warp: 0 +wspawn: 0 +stalled: 0 +********************************** execute_unit ********************************* +valid: 1 +PC: 80000078 +wid: 2 +rd: 3 rs1: 3 rs2: -1 +is_lw: 0 +is_sw: 0 +fetch_stall_cycles: 0 +mem_stall_cycles: 0 +stall_warp: 0 +wspawn: 0 +stalled: 0 +********************************** scheduler ********************************* +valid: 1 +PC: 80000078 +wid: 3 +rd: 3 rs1: 3 rs2: -1 +is_lw: 0 +is_sw: 0 +fetch_stall_cycles: 0 +mem_stall_cycles: 0 +stall_warp: 0 +wspawn: 0 +stalled: 0 +********************************** Decode ********************************* +valid: 1 +PC: 80000074 +wid: 0 +rd: 3 rs1: -1 rs2: -1 +is_lw: 0 +is_sw: 0 +fetch_stall_cycles: 0 +mem_stall_cycles: 0 +stall_warp: 0 +wspawn: 0 +stalled: 0 +DEBUG ../core.cpp:386: Core step stepping warp 1[4] +DEBUG ../core.cpp:683: in step pc=0x8000007c +help: in PC: 8000007c +CUrrent CODE: 21026f3 +DEBUG ../core.cpp:703: Fetched at 0x8000007c +DEBUG ../core.cpp:704: 0x8000007c: SYS; +DEBUG ../instruction.cpp:350: Begin instruction execute. +DEBUG ../instruction.cpp:2117: End instruction execute. +DEBUG ../core.cpp:717: Register state: + %r 0: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r 1: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r 2: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r 3: 80001808 80001808 80001808 80001808 00000000 00000000 00000000 00000000 (0) + %r 4: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r 5: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r 6: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r 7: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r 8: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r 9: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r10: 00000004 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r11: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r12: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r13: 00000001 00000001 00000001 00000001 00000000 00000000 00000000 00000000 (0) + %r14: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r15: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r16: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r17: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r18: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r19: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r20: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r21: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r22: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r23: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r24: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r25: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r26: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r27: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r28: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r29: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r30: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r31: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) +DEBUG ../core.cpp:726: Thread mask: + 1 1 1 1 0 0 0 0 + + +DEBUG ../core.cpp:388: Now 4 active threads in 1 +********************************** Fetch ********************************* +valid: 1 +PC: 8000007c +wid: 1 +rd: 13 rs1: 0 rs2: -1 +is_lw: 0 +is_sw: 0 +fetch_stall_cycles: 0 +mem_stall_cycles: 0 +stall_warp: 0 +wspawn: 0 +stalled: 0 + + + +------------------------------------------------------ +CYCLE: 41 +Stalled Warps: +0 0 0 0 0 0 0 0 + +********************************** Writeback ********************************* +valid: 1 +PC: 80000078 +wid: 2 +rd: 3 rs1: 3 rs2: -1 +is_lw: 0 +is_sw: 0 +fetch_stall_cycles: 0 +mem_stall_cycles: 0 +stall_warp: 0 +wspawn: 0 +stalled: 0 +********************************** LSU ********************************* +valid: 0 +PC: 0 +wid: 0 +rd: -1 rs1: -1 rs2: -1 +is_lw: 0 +is_sw: 0 +fetch_stall_cycles: 0 +mem_stall_cycles: 0 +stall_warp: 0 +wspawn: 0 +stalled: 0 +********************************** execute_unit ********************************* +valid: 1 +PC: 80000078 +wid: 3 +rd: 3 rs1: 3 rs2: -1 +is_lw: 0 +is_sw: 0 +fetch_stall_cycles: 0 +mem_stall_cycles: 0 +stall_warp: 0 +wspawn: 0 +stalled: 0 +********************************** scheduler ********************************* +valid: 1 +PC: 80000074 +wid: 0 +rd: 3 rs1: -1 rs2: -1 +is_lw: 0 +is_sw: 0 +fetch_stall_cycles: 0 +mem_stall_cycles: 0 +stall_warp: 0 +wspawn: 0 +stalled: 0 +********************************** Decode ********************************* +valid: 1 +PC: 8000007c +wid: 1 +rd: 13 rs1: 0 rs2: -1 +is_lw: 0 +is_sw: 0 +fetch_stall_cycles: 0 +mem_stall_cycles: 0 +stall_warp: 0 +wspawn: 0 +stalled: 0 +DEBUG ../core.cpp:386: Core step stepping warp 2[4] +DEBUG ../core.cpp:683: in step pc=0x8000007c +help: in PC: 8000007c +CUrrent CODE: 21026f3 +DEBUG ../core.cpp:703: Fetched at 0x8000007c +DEBUG ../core.cpp:704: 0x8000007c: SYS; +DEBUG ../instruction.cpp:350: Begin instruction execute. +DEBUG ../instruction.cpp:2117: End instruction execute. +DEBUG ../core.cpp:717: Register state: + %r 0: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r 1: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r 2: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r 3: 80001808 80001808 80001808 80001808 00000000 00000000 00000000 00000000 (0) + %r 4: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r 5: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r 6: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r 7: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r 8: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r 9: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r10: 00000004 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r11: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r12: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r13: 00000002 00000002 00000002 00000002 00000000 00000000 00000000 00000000 (0) + %r14: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r15: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r16: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r17: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r18: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r19: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r20: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r21: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r22: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r23: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r24: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r25: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r26: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r27: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r28: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r29: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r30: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r31: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) +DEBUG ../core.cpp:726: Thread mask: + 1 1 1 1 0 0 0 0 + + +DEBUG ../core.cpp:388: Now 4 active threads in 2 +********************************** Fetch ********************************* +valid: 1 +PC: 8000007c +wid: 2 +rd: 13 rs1: 0 rs2: -1 +is_lw: 0 +is_sw: 0 +fetch_stall_cycles: 0 +mem_stall_cycles: 0 +stall_warp: 0 +wspawn: 0 +stalled: 0 + + + +------------------------------------------------------ +CYCLE: 42 +Stalled Warps: +0 0 0 0 0 0 0 0 + +********************************** Writeback ********************************* +valid: 1 +PC: 80000078 +wid: 3 +rd: 3 rs1: 3 rs2: -1 +is_lw: 0 +is_sw: 0 +fetch_stall_cycles: 0 +mem_stall_cycles: 0 +stall_warp: 0 +wspawn: 0 +stalled: 0 +********************************** LSU ********************************* +valid: 0 +PC: 0 +wid: 0 +rd: -1 rs1: -1 rs2: -1 +is_lw: 0 +is_sw: 0 +fetch_stall_cycles: 0 +mem_stall_cycles: 0 +stall_warp: 0 +wspawn: 0 +stalled: 0 +********************************** execute_unit ********************************* +valid: 1 +PC: 80000074 +wid: 0 +rd: 3 rs1: -1 rs2: -1 +is_lw: 0 +is_sw: 0 +fetch_stall_cycles: 0 +mem_stall_cycles: 0 +stall_warp: 0 +wspawn: 0 +stalled: 0 +********************************** scheduler ********************************* +valid: 1 +PC: 8000007c +wid: 1 +rd: 13 rs1: 0 rs2: -1 +is_lw: 0 +is_sw: 0 +fetch_stall_cycles: 0 +mem_stall_cycles: 0 +stall_warp: 0 +wspawn: 0 +stalled: 0 +********************************** Decode ********************************* +valid: 1 +PC: 8000007c +wid: 2 +rd: 13 rs1: 0 rs2: -1 +is_lw: 0 +is_sw: 0 +fetch_stall_cycles: 0 +mem_stall_cycles: 0 +stall_warp: 0 +wspawn: 0 +stalled: 0 +DEBUG ../core.cpp:386: Core step stepping warp 3[4] +DEBUG ../core.cpp:683: in step pc=0x8000007c +help: in PC: 8000007c +CUrrent CODE: 21026f3 +DEBUG ../core.cpp:703: Fetched at 0x8000007c +DEBUG ../core.cpp:704: 0x8000007c: SYS; +DEBUG ../instruction.cpp:350: Begin instruction execute. +DEBUG ../instruction.cpp:2117: End instruction execute. +DEBUG ../core.cpp:717: Register state: + %r 0: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r 1: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r 2: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r 3: 80001808 80001808 80001808 80001808 00000000 00000000 00000000 00000000 (0) + %r 4: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r 5: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r 6: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r 7: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r 8: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r 9: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r10: 00000004 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r11: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r12: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r13: 00000003 00000003 00000003 00000003 00000000 00000000 00000000 00000000 (0) + %r14: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r15: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r16: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r17: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r18: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r19: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r20: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r21: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r22: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r23: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r24: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r25: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r26: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r27: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r28: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r29: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r30: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r31: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) +DEBUG ../core.cpp:726: Thread mask: + 1 1 1 1 0 0 0 0 + + +DEBUG ../core.cpp:388: Now 4 active threads in 3 +********************************** Fetch ********************************* +valid: 1 +PC: 8000007c +wid: 3 +rd: 13 rs1: 0 rs2: -1 +is_lw: 0 +is_sw: 0 +fetch_stall_cycles: 0 +mem_stall_cycles: 0 +stall_warp: 0 +wspawn: 0 +stalled: 0 + + + +------------------------------------------------------ +CYCLE: 43 +Stalled Warps: +0 0 0 0 0 0 0 0 + +********************************** Writeback ********************************* +valid: 1 +PC: 80000074 +wid: 0 +rd: 3 rs1: -1 rs2: -1 +is_lw: 0 +is_sw: 0 +fetch_stall_cycles: 0 +mem_stall_cycles: 0 +stall_warp: 0 +wspawn: 0 +stalled: 0 +********************************** LSU ********************************* +valid: 0 +PC: 0 +wid: 0 +rd: -1 rs1: -1 rs2: -1 +is_lw: 0 +is_sw: 0 +fetch_stall_cycles: 0 +mem_stall_cycles: 0 +stall_warp: 0 +wspawn: 0 +stalled: 0 +********************************** execute_unit ********************************* +valid: 1 +PC: 8000007c +wid: 1 +rd: 13 rs1: 0 rs2: -1 +is_lw: 0 +is_sw: 0 +fetch_stall_cycles: 0 +mem_stall_cycles: 0 +stall_warp: 0 +wspawn: 0 +stalled: 0 +********************************** scheduler ********************************* +valid: 1 +PC: 8000007c +wid: 2 +rd: 13 rs1: 0 rs2: -1 +is_lw: 0 +is_sw: 0 +fetch_stall_cycles: 0 +mem_stall_cycles: 0 +stall_warp: 0 +wspawn: 0 +stalled: 0 +********************************** Decode ********************************* +valid: 1 +PC: 8000007c +wid: 3 +rd: 13 rs1: 0 rs2: -1 +is_lw: 0 +is_sw: 0 +fetch_stall_cycles: 0 +mem_stall_cycles: 0 +stall_warp: 0 +wspawn: 0 +stalled: 0 +DEBUG ../core.cpp:386: Core step stepping warp 0[4] +DEBUG ../core.cpp:683: in step pc=0x80000078 +help: in PC: 80000078 +CUrrent CODE: 79418193 +DEBUG ../core.cpp:703: Fetched at 0x80000078 +DEBUG ../core.cpp:704: 0x80000078: i_type; +DEBUG ../instruction.cpp:350: Begin instruction execute. +DEBUG ../instruction.cpp:2117: End instruction execute. +DEBUG ../core.cpp:717: Register state: + %r 0: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r 1: 80000014 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r 2: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r 3: 80001808 80001808 80001808 80001808 00000000 00000000 00000000 00000000 (0) + %r 4: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r 5: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r 6: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r 7: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r 8: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r 9: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r10: 00000004 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r11: 8000006c 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r12: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r13: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r14: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r15: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r16: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r17: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r18: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r19: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r20: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r21: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r22: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r23: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r24: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r25: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r26: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r27: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r28: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r29: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r30: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r31: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) +DEBUG ../core.cpp:726: Thread mask: + 1 1 1 1 0 0 0 0 + + +DEBUG ../core.cpp:388: Now 4 active threads in 0 +********************************** Fetch ********************************* +valid: 1 +PC: 80000078 +wid: 0 +rd: 3 rs1: 3 rs2: -1 +is_lw: 0 +is_sw: 0 +fetch_stall_cycles: 0 +mem_stall_cycles: 0 +stall_warp: 0 +wspawn: 0 +stalled: 0 + + + +------------------------------------------------------ +CYCLE: 44 +Stalled Warps: +0 0 0 0 0 0 0 0 + +********************************** Writeback ********************************* +valid: 1 +PC: 8000007c +wid: 1 +rd: 13 rs1: 0 rs2: -1 +is_lw: 0 +is_sw: 0 +fetch_stall_cycles: 0 +mem_stall_cycles: 0 +stall_warp: 0 +wspawn: 0 +stalled: 0 +********************************** LSU ********************************* +valid: 0 +PC: 0 +wid: 0 +rd: -1 rs1: -1 rs2: -1 +is_lw: 0 +is_sw: 0 +fetch_stall_cycles: 0 +mem_stall_cycles: 0 +stall_warp: 0 +wspawn: 0 +stalled: 0 +********************************** execute_unit ********************************* +valid: 1 +PC: 8000007c +wid: 2 +rd: 13 rs1: 0 rs2: -1 +is_lw: 0 +is_sw: 0 +fetch_stall_cycles: 0 +mem_stall_cycles: 0 +stall_warp: 0 +wspawn: 0 +stalled: 0 +********************************** scheduler ********************************* +valid: 1 +PC: 8000007c +wid: 3 +rd: 13 rs1: 0 rs2: -1 +is_lw: 0 +is_sw: 0 +fetch_stall_cycles: 0 +mem_stall_cycles: 0 +stall_warp: 0 +wspawn: 0 +stalled: 0 +********************************** Decode ********************************* +valid: 1 +PC: 80000078 +wid: 0 +rd: 3 rs1: 3 rs2: -1 +is_lw: 0 +is_sw: 0 +fetch_stall_cycles: 0 +mem_stall_cycles: 0 +stall_warp: 0 +wspawn: 0 +stalled: 0 +DEBUG ../core.cpp:386: Core step stepping warp 1[4] +DEBUG ../core.cpp:683: in step pc=0x80000080 +help: in PC: 80000080 +CUrrent CODE: 1a69693 +DEBUG ../core.cpp:703: Fetched at 0x80000080 +DEBUG ../core.cpp:704: 0x80000080: i_type; +DEBUG ../instruction.cpp:350: Begin instruction execute. +DEBUG ../instruction.cpp:2117: End instruction execute. +DEBUG ../core.cpp:717: Register state: + %r 0: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r 1: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r 2: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r 3: 80001808 80001808 80001808 80001808 00000000 00000000 00000000 00000000 (0) + %r 4: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r 5: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r 6: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r 7: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r 8: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r 9: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r10: 00000004 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r11: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r12: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r13: 04000000 04000000 04000000 04000000 00000000 00000000 00000000 00000000 (0) + %r14: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r15: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r16: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r17: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r18: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r19: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r20: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r21: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r22: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r23: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r24: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r25: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r26: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r27: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r28: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r29: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r30: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r31: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) +DEBUG ../core.cpp:726: Thread mask: + 1 1 1 1 0 0 0 0 + + +DEBUG ../core.cpp:388: Now 4 active threads in 1 +********************************** Fetch ********************************* +valid: 1 +PC: 80000080 +wid: 1 +rd: 13 rs1: 13 rs2: -1 +is_lw: 0 +is_sw: 0 +fetch_stall_cycles: 3 +mem_stall_cycles: 0 +stall_warp: 0 +wspawn: 0 +stalled: 0 + + + +------------------------------------------------------ +CYCLE: 45 +Stalled Warps: +0 0 0 0 0 0 0 0 + +********************************** Writeback ********************************* +valid: 1 +PC: 8000007c +wid: 2 +rd: 13 rs1: 0 rs2: -1 +is_lw: 0 +is_sw: 0 +fetch_stall_cycles: 0 +mem_stall_cycles: 0 +stall_warp: 0 +wspawn: 0 +stalled: 0 +********************************** LSU ********************************* +valid: 0 +PC: 0 +wid: 0 +rd: -1 rs1: -1 rs2: -1 +is_lw: 0 +is_sw: 0 +fetch_stall_cycles: 0 +mem_stall_cycles: 0 +stall_warp: 0 +wspawn: 0 +stalled: 0 +********************************** execute_unit ********************************* +valid: 1 +PC: 8000007c +wid: 3 +rd: 13 rs1: 0 rs2: -1 +is_lw: 0 +is_sw: 0 +fetch_stall_cycles: 0 +mem_stall_cycles: 0 +stall_warp: 0 +wspawn: 0 +stalled: 0 +********************************** scheduler ********************************* +valid: 1 +PC: 80000078 +wid: 0 +rd: 3 rs1: 3 rs2: -1 +is_lw: 0 +is_sw: 0 +fetch_stall_cycles: 0 +mem_stall_cycles: 0 +stall_warp: 0 +wspawn: 0 +stalled: 0 +********************************** Decode ********************************* +valid: 0 +PC: 0 +wid: 2 +rd: -1 rs1: -1 rs2: -1 +is_lw: 0 +is_sw: 0 +fetch_stall_cycles: 0 +mem_stall_cycles: 0 +stall_warp: 0 +wspawn: 0 +stalled: 0 +********************************** Fetch ********************************* +valid: 1 +PC: 80000080 +wid: 1 +rd: 13 rs1: 13 rs2: -1 +is_lw: 0 +is_sw: 0 +fetch_stall_cycles: 2 +mem_stall_cycles: 0 +stall_warp: 0 +wspawn: 0 +stalled: 0 + + + +------------------------------------------------------ +CYCLE: 46 +Stalled Warps: +0 0 0 0 0 0 0 0 + +********************************** Writeback ********************************* +valid: 1 +PC: 8000007c +wid: 3 +rd: 13 rs1: 0 rs2: -1 +is_lw: 0 +is_sw: 0 +fetch_stall_cycles: 0 +mem_stall_cycles: 0 +stall_warp: 0 +wspawn: 0 +stalled: 0 +********************************** LSU ********************************* +valid: 0 +PC: 0 +wid: 0 +rd: -1 rs1: -1 rs2: -1 +is_lw: 0 +is_sw: 0 +fetch_stall_cycles: 0 +mem_stall_cycles: 0 +stall_warp: 0 +wspawn: 0 +stalled: 0 +********************************** execute_unit ********************************* +valid: 1 +PC: 80000078 +wid: 0 +rd: 3 rs1: 3 rs2: -1 +is_lw: 0 +is_sw: 0 +fetch_stall_cycles: 0 +mem_stall_cycles: 0 +stall_warp: 0 +wspawn: 0 +stalled: 0 +********************************** scheduler ********************************* +valid: 0 +PC: 0 +wid: 2 +rd: -1 rs1: -1 rs2: -1 +is_lw: 0 +is_sw: 0 +fetch_stall_cycles: 0 +mem_stall_cycles: 0 +stall_warp: 0 +wspawn: 0 +stalled: 0 +********************************** Decode ********************************* +valid: 0 +PC: 0 +wid: 2 +rd: -1 rs1: -1 rs2: -1 +is_lw: 0 +is_sw: 0 +fetch_stall_cycles: 0 +mem_stall_cycles: 0 +stall_warp: 0 +wspawn: 0 +stalled: 0 +********************************** Fetch ********************************* +valid: 1 +PC: 80000080 +wid: 1 +rd: 13 rs1: 13 rs2: -1 +is_lw: 0 +is_sw: 0 +fetch_stall_cycles: 1 +mem_stall_cycles: 0 +stall_warp: 0 +wspawn: 0 +stalled: 0 + + + +------------------------------------------------------ +CYCLE: 47 +Stalled Warps: +0 0 0 0 0 0 0 0 + +********************************** Writeback ********************************* +valid: 1 +PC: 80000078 +wid: 0 +rd: 3 rs1: 3 rs2: -1 +is_lw: 0 +is_sw: 0 +fetch_stall_cycles: 0 +mem_stall_cycles: 0 +stall_warp: 0 +wspawn: 0 +stalled: 0 +********************************** LSU ********************************* +valid: 0 +PC: 0 +wid: 0 +rd: -1 rs1: -1 rs2: -1 +is_lw: 0 +is_sw: 0 +fetch_stall_cycles: 0 +mem_stall_cycles: 0 +stall_warp: 0 +wspawn: 0 +stalled: 0 +********************************** execute_unit ********************************* +valid: 0 +PC: 0 +wid: 2 +rd: -1 rs1: -1 rs2: -1 +is_lw: 0 +is_sw: 0 +fetch_stall_cycles: 0 +mem_stall_cycles: 0 +stall_warp: 0 +wspawn: 0 +stalled: 0 +********************************** scheduler ********************************* +valid: 0 +PC: 0 +wid: 2 +rd: -1 rs1: -1 rs2: -1 +is_lw: 0 +is_sw: 0 +fetch_stall_cycles: 0 +mem_stall_cycles: 0 +stall_warp: 0 +wspawn: 0 +stalled: 0 +********************************** Decode ********************************* +valid: 0 +PC: 0 +wid: 2 +rd: -1 rs1: -1 rs2: -1 +is_lw: 0 +is_sw: 0 +fetch_stall_cycles: 0 +mem_stall_cycles: 0 +stall_warp: 0 +wspawn: 0 +stalled: 0 +********************************** Fetch ********************************* +valid: 1 +PC: 80000080 +wid: 1 +rd: 13 rs1: 13 rs2: -1 +is_lw: 0 +is_sw: 0 +fetch_stall_cycles: 0 +mem_stall_cycles: 0 +stall_warp: 0 +wspawn: 0 +stalled: 0 + + + +------------------------------------------------------ +CYCLE: 48 +Stalled Warps: +0 0 0 0 0 0 0 0 + +********************************** Writeback ********************************* +valid: 0 +PC: 0 +wid: 2 +rd: -1 rs1: -1 rs2: -1 +is_lw: 0 +is_sw: 0 +fetch_stall_cycles: 0 +mem_stall_cycles: 0 +stall_warp: 0 +wspawn: 0 +stalled: 0 +********************************** LSU ********************************* +valid: 0 +PC: 0 +wid: 0 +rd: -1 rs1: -1 rs2: -1 +is_lw: 0 +is_sw: 0 +fetch_stall_cycles: 0 +mem_stall_cycles: 0 +stall_warp: 0 +wspawn: 0 +stalled: 0 +********************************** execute_unit ********************************* +valid: 0 +PC: 0 +wid: 2 +rd: -1 rs1: -1 rs2: -1 +is_lw: 0 +is_sw: 0 +fetch_stall_cycles: 0 +mem_stall_cycles: 0 +stall_warp: 0 +wspawn: 0 +stalled: 0 +********************************** scheduler ********************************* +valid: 0 +PC: 0 +wid: 2 +rd: -1 rs1: -1 rs2: -1 +is_lw: 0 +is_sw: 0 +fetch_stall_cycles: 0 +mem_stall_cycles: 0 +stall_warp: 0 +wspawn: 0 +stalled: 0 +********************************** Decode ********************************* +valid: 1 +PC: 80000080 +wid: 1 +rd: 13 rs1: 13 rs2: -1 +is_lw: 0 +is_sw: 0 +fetch_stall_cycles: 0 +mem_stall_cycles: 0 +stall_warp: 0 +wspawn: 0 +stalled: 0 +DEBUG ../core.cpp:386: Core step stepping warp 2[4] +DEBUG ../core.cpp:683: in step pc=0x80000080 +help: in PC: 80000080 +CUrrent CODE: 1a69693 +DEBUG ../core.cpp:703: Fetched at 0x80000080 +DEBUG ../core.cpp:704: 0x80000080: i_type; +DEBUG ../instruction.cpp:350: Begin instruction execute. +DEBUG ../instruction.cpp:2117: End instruction execute. +DEBUG ../core.cpp:717: Register state: + %r 0: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r 1: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r 2: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r 3: 80001808 80001808 80001808 80001808 00000000 00000000 00000000 00000000 (0) + %r 4: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r 5: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r 6: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r 7: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r 8: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r 9: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r10: 00000004 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r11: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r12: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r13: 08000000 08000000 08000000 08000000 00000000 00000000 00000000 00000000 (0) + %r14: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r15: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r16: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r17: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r18: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r19: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r20: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r21: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r22: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r23: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r24: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r25: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r26: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r27: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r28: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r29: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r30: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r31: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) +DEBUG ../core.cpp:726: Thread mask: + 1 1 1 1 0 0 0 0 + + +DEBUG ../core.cpp:388: Now 4 active threads in 2 +********************************** Fetch ********************************* +valid: 1 +PC: 80000080 +wid: 2 +rd: 13 rs1: 13 rs2: -1 +is_lw: 0 +is_sw: 0 +fetch_stall_cycles: 0 +mem_stall_cycles: 0 +stall_warp: 0 +wspawn: 0 +stalled: 0 + + + +------------------------------------------------------ +CYCLE: 49 +Stalled Warps: +0 0 0 0 0 0 0 0 + +********************************** Writeback ********************************* +valid: 0 +PC: 0 +wid: 3 +rd: -1 rs1: -1 rs2: -1 +is_lw: 0 +is_sw: 0 +fetch_stall_cycles: 0 +mem_stall_cycles: 0 +stall_warp: 0 +wspawn: 0 +stalled: 0 +********************************** LSU ********************************* +valid: 0 +PC: 0 +wid: 0 +rd: -1 rs1: -1 rs2: -1 +is_lw: 0 +is_sw: 0 +fetch_stall_cycles: 0 +mem_stall_cycles: 0 +stall_warp: 0 +wspawn: 0 +stalled: 0 +********************************** execute_unit ********************************* +valid: 0 +PC: 0 +wid: 2 +rd: -1 rs1: -1 rs2: -1 +is_lw: 0 +is_sw: 0 +fetch_stall_cycles: 0 +mem_stall_cycles: 0 +stall_warp: 0 +wspawn: 0 +stalled: 0 +********************************** scheduler ********************************* +valid: 1 +PC: 80000080 +wid: 1 +rd: 13 rs1: 13 rs2: -1 +is_lw: 0 +is_sw: 0 +fetch_stall_cycles: 0 +mem_stall_cycles: 0 +stall_warp: 0 +wspawn: 0 +stalled: 0 +********************************** Decode ********************************* +valid: 1 +PC: 80000080 +wid: 2 +rd: 13 rs1: 13 rs2: -1 +is_lw: 0 +is_sw: 0 +fetch_stall_cycles: 0 +mem_stall_cycles: 0 +stall_warp: 0 +wspawn: 0 +stalled: 0 +DEBUG ../core.cpp:386: Core step stepping warp 3[4] +DEBUG ../core.cpp:683: in step pc=0x80000080 +help: in PC: 80000080 +CUrrent CODE: 1a69693 +DEBUG ../core.cpp:703: Fetched at 0x80000080 +DEBUG ../core.cpp:704: 0x80000080: i_type; +DEBUG ../instruction.cpp:350: Begin instruction execute. +DEBUG ../instruction.cpp:2117: End instruction execute. +DEBUG ../core.cpp:717: Register state: + %r 0: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r 1: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r 2: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r 3: 80001808 80001808 80001808 80001808 00000000 00000000 00000000 00000000 (0) + %r 4: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r 5: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r 6: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r 7: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r 8: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r 9: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r10: 00000004 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r11: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r12: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r13: 0c000000 0c000000 0c000000 0c000000 00000000 00000000 00000000 00000000 (0) + %r14: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r15: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r16: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r17: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r18: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r19: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r20: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r21: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r22: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r23: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r24: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r25: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r26: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r27: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r28: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r29: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r30: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r31: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) +DEBUG ../core.cpp:726: Thread mask: + 1 1 1 1 0 0 0 0 + + +DEBUG ../core.cpp:388: Now 4 active threads in 3 +********************************** Fetch ********************************* +valid: 1 +PC: 80000080 +wid: 3 +rd: 13 rs1: 13 rs2: -1 +is_lw: 0 +is_sw: 0 +fetch_stall_cycles: 0 +mem_stall_cycles: 0 +stall_warp: 0 +wspawn: 0 +stalled: 0 + + + +------------------------------------------------------ +CYCLE: 50 +Stalled Warps: +0 0 0 0 0 0 0 0 + +********************************** Writeback ********************************* +valid: 0 +PC: 0 +wid: 0 +rd: -1 rs1: -1 rs2: -1 +is_lw: 0 +is_sw: 0 +fetch_stall_cycles: 0 +mem_stall_cycles: 0 +stall_warp: 0 +wspawn: 0 +stalled: 0 +********************************** LSU ********************************* +valid: 0 +PC: 0 +wid: 0 +rd: -1 rs1: -1 rs2: -1 +is_lw: 0 +is_sw: 0 +fetch_stall_cycles: 0 +mem_stall_cycles: 0 +stall_warp: 0 +wspawn: 0 +stalled: 0 +********************************** execute_unit ********************************* +valid: 1 +PC: 80000080 +wid: 1 +rd: 13 rs1: 13 rs2: -1 +is_lw: 0 +is_sw: 0 +fetch_stall_cycles: 0 +mem_stall_cycles: 0 +stall_warp: 0 +wspawn: 0 +stalled: 0 +********************************** scheduler ********************************* +valid: 1 +PC: 80000080 +wid: 2 +rd: 13 rs1: 13 rs2: -1 +is_lw: 0 +is_sw: 0 +fetch_stall_cycles: 0 +mem_stall_cycles: 0 +stall_warp: 0 +wspawn: 0 +stalled: 0 +********************************** Decode ********************************* +valid: 1 +PC: 80000080 +wid: 3 +rd: 13 rs1: 13 rs2: -1 +is_lw: 0 +is_sw: 0 +fetch_stall_cycles: 0 +mem_stall_cycles: 0 +stall_warp: 0 +wspawn: 0 +stalled: 0 +DEBUG ../core.cpp:386: Core step stepping warp 0[4] +DEBUG ../core.cpp:683: in step pc=0x8000007c +help: in PC: 8000007c +CUrrent CODE: 21026f3 +DEBUG ../core.cpp:703: Fetched at 0x8000007c +DEBUG ../core.cpp:704: 0x8000007c: SYS; +DEBUG ../instruction.cpp:350: Begin instruction execute. +DEBUG ../instruction.cpp:2117: End instruction execute. +DEBUG ../core.cpp:717: Register state: + %r 0: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r 1: 80000014 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r 2: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r 3: 80001808 80001808 80001808 80001808 00000000 00000000 00000000 00000000 (0) + %r 4: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r 5: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r 6: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r 7: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r 8: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r 9: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r10: 00000004 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r11: 8000006c 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r12: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r13: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r14: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r15: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r16: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r17: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r18: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r19: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r20: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r21: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r22: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r23: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r24: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r25: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r26: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r27: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r28: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r29: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r30: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r31: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) +DEBUG ../core.cpp:726: Thread mask: + 1 1 1 1 0 0 0 0 + + +DEBUG ../core.cpp:388: Now 4 active threads in 0 +********************************** Fetch ********************************* +valid: 1 +PC: 8000007c +wid: 0 +rd: 13 rs1: 0 rs2: -1 +is_lw: 0 +is_sw: 0 +fetch_stall_cycles: 0 +mem_stall_cycles: 0 +stall_warp: 0 +wspawn: 0 +stalled: 0 + + + +------------------------------------------------------ +CYCLE: 51 +Stalled Warps: +0 0 0 0 0 0 0 0 + +********************************** Writeback ********************************* +valid: 1 +PC: 80000080 +wid: 1 +rd: 13 rs1: 13 rs2: -1 +is_lw: 0 +is_sw: 0 +fetch_stall_cycles: 0 +mem_stall_cycles: 0 +stall_warp: 0 +wspawn: 0 +stalled: 0 +********************************** LSU ********************************* +valid: 0 +PC: 0 +wid: 0 +rd: -1 rs1: -1 rs2: -1 +is_lw: 0 +is_sw: 0 +fetch_stall_cycles: 0 +mem_stall_cycles: 0 +stall_warp: 0 +wspawn: 0 +stalled: 0 +********************************** execute_unit ********************************* +valid: 1 +PC: 80000080 +wid: 2 +rd: 13 rs1: 13 rs2: -1 +is_lw: 0 +is_sw: 0 +fetch_stall_cycles: 0 +mem_stall_cycles: 0 +stall_warp: 0 +wspawn: 0 +stalled: 0 +********************************** scheduler ********************************* +valid: 1 +PC: 80000080 +wid: 3 +rd: 13 rs1: 13 rs2: -1 +is_lw: 0 +is_sw: 0 +fetch_stall_cycles: 0 +mem_stall_cycles: 0 +stall_warp: 0 +wspawn: 0 +stalled: 0 +********************************** Decode ********************************* +valid: 1 +PC: 8000007c +wid: 0 +rd: 13 rs1: 0 rs2: -1 +is_lw: 0 +is_sw: 0 +fetch_stall_cycles: 0 +mem_stall_cycles: 0 +stall_warp: 0 +wspawn: 0 +stalled: 0 +DEBUG ../core.cpp:386: Core step stepping warp 1[4] +DEBUG ../core.cpp:683: in step pc=0x80000084 +help: in PC: 80000084 +CUrrent CODE: 2002673 +DEBUG ../core.cpp:703: Fetched at 0x80000084 +DEBUG ../core.cpp:704: 0x80000084: SYS; +DEBUG ../instruction.cpp:350: Begin instruction execute. +DEBUG ../instruction.cpp:2117: End instruction execute. +DEBUG ../core.cpp:717: Register state: + %r 0: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r 1: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r 2: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r 3: 80001808 80001808 80001808 80001808 00000000 00000000 00000000 00000000 (0) + %r 4: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r 5: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r 6: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r 7: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r 8: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r 9: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r10: 00000004 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r11: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r12: 00000000 00000001 00000002 00000003 00000000 00000000 00000000 00000000 (0) + %r13: 04000000 04000000 04000000 04000000 00000000 00000000 00000000 00000000 (0) + %r14: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r15: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r16: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r17: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r18: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r19: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r20: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r21: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r22: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r23: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r24: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r25: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r26: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r27: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r28: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r29: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r30: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r31: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) +DEBUG ../core.cpp:726: Thread mask: + 1 1 1 1 0 0 0 0 + + +DEBUG ../core.cpp:388: Now 4 active threads in 1 +********************************** Fetch ********************************* +valid: 1 +PC: 80000084 +wid: 1 +rd: 12 rs1: 0 rs2: -1 +is_lw: 0 +is_sw: 0 +fetch_stall_cycles: 0 +mem_stall_cycles: 0 +stall_warp: 0 +wspawn: 0 +stalled: 0 + + + +------------------------------------------------------ +CYCLE: 52 +Stalled Warps: +0 0 0 0 0 0 0 0 + +********************************** Writeback ********************************* +valid: 1 +PC: 80000080 +wid: 2 +rd: 13 rs1: 13 rs2: -1 +is_lw: 0 +is_sw: 0 +fetch_stall_cycles: 0 +mem_stall_cycles: 0 +stall_warp: 0 +wspawn: 0 +stalled: 0 +********************************** LSU ********************************* +valid: 0 +PC: 0 +wid: 0 +rd: -1 rs1: -1 rs2: -1 +is_lw: 0 +is_sw: 0 +fetch_stall_cycles: 0 +mem_stall_cycles: 0 +stall_warp: 0 +wspawn: 0 +stalled: 0 +********************************** execute_unit ********************************* +valid: 1 +PC: 80000080 +wid: 3 +rd: 13 rs1: 13 rs2: -1 +is_lw: 0 +is_sw: 0 +fetch_stall_cycles: 0 +mem_stall_cycles: 0 +stall_warp: 0 +wspawn: 0 +stalled: 0 +********************************** scheduler ********************************* +valid: 1 +PC: 8000007c +wid: 0 +rd: 13 rs1: 0 rs2: -1 +is_lw: 0 +is_sw: 0 +fetch_stall_cycles: 0 +mem_stall_cycles: 0 +stall_warp: 0 +wspawn: 0 +stalled: 0 +********************************** Decode ********************************* +valid: 1 +PC: 80000084 +wid: 1 +rd: 12 rs1: 0 rs2: -1 +is_lw: 0 +is_sw: 0 +fetch_stall_cycles: 0 +mem_stall_cycles: 0 +stall_warp: 0 +wspawn: 0 +stalled: 0 +DEBUG ../core.cpp:386: Core step stepping warp 2[4] +DEBUG ../core.cpp:683: in step pc=0x80000084 +help: in PC: 80000084 +CUrrent CODE: 2002673 +DEBUG ../core.cpp:703: Fetched at 0x80000084 +DEBUG ../core.cpp:704: 0x80000084: SYS; +DEBUG ../instruction.cpp:350: Begin instruction execute. +DEBUG ../instruction.cpp:2117: End instruction execute. +DEBUG ../core.cpp:717: Register state: + %r 0: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r 1: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r 2: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r 3: 80001808 80001808 80001808 80001808 00000000 00000000 00000000 00000000 (0) + %r 4: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r 5: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r 6: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r 7: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r 8: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r 9: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r10: 00000004 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r11: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r12: 00000000 00000001 00000002 00000003 00000000 00000000 00000000 00000000 (0) + %r13: 08000000 08000000 08000000 08000000 00000000 00000000 00000000 00000000 (0) + %r14: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r15: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r16: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r17: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r18: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r19: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r20: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r21: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r22: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r23: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r24: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r25: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r26: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r27: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r28: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r29: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r30: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r31: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) +DEBUG ../core.cpp:726: Thread mask: + 1 1 1 1 0 0 0 0 + + +DEBUG ../core.cpp:388: Now 4 active threads in 2 +********************************** Fetch ********************************* +valid: 1 +PC: 80000084 +wid: 2 +rd: 12 rs1: 0 rs2: -1 +is_lw: 0 +is_sw: 0 +fetch_stall_cycles: 0 +mem_stall_cycles: 0 +stall_warp: 0 +wspawn: 0 +stalled: 0 + + + +------------------------------------------------------ +CYCLE: 53 +Stalled Warps: +0 0 0 0 0 0 0 0 + +********************************** Writeback ********************************* +valid: 1 +PC: 80000080 +wid: 3 +rd: 13 rs1: 13 rs2: -1 +is_lw: 0 +is_sw: 0 +fetch_stall_cycles: 0 +mem_stall_cycles: 0 +stall_warp: 0 +wspawn: 0 +stalled: 0 +********************************** LSU ********************************* +valid: 0 +PC: 0 +wid: 0 +rd: -1 rs1: -1 rs2: -1 +is_lw: 0 +is_sw: 0 +fetch_stall_cycles: 0 +mem_stall_cycles: 0 +stall_warp: 0 +wspawn: 0 +stalled: 0 +********************************** execute_unit ********************************* +valid: 1 +PC: 8000007c +wid: 0 +rd: 13 rs1: 0 rs2: -1 +is_lw: 0 +is_sw: 0 +fetch_stall_cycles: 0 +mem_stall_cycles: 0 +stall_warp: 0 +wspawn: 0 +stalled: 0 +********************************** scheduler ********************************* +valid: 1 +PC: 80000084 +wid: 1 +rd: 12 rs1: 0 rs2: -1 +is_lw: 0 +is_sw: 0 +fetch_stall_cycles: 0 +mem_stall_cycles: 0 +stall_warp: 0 +wspawn: 0 +stalled: 0 +********************************** Decode ********************************* +valid: 1 +PC: 80000084 +wid: 2 +rd: 12 rs1: 0 rs2: -1 +is_lw: 0 +is_sw: 0 +fetch_stall_cycles: 0 +mem_stall_cycles: 0 +stall_warp: 0 +wspawn: 0 +stalled: 0 +DEBUG ../core.cpp:386: Core step stepping warp 3[4] +DEBUG ../core.cpp:683: in step pc=0x80000084 +help: in PC: 80000084 +CUrrent CODE: 2002673 +DEBUG ../core.cpp:703: Fetched at 0x80000084 +DEBUG ../core.cpp:704: 0x80000084: SYS; +DEBUG ../instruction.cpp:350: Begin instruction execute. +DEBUG ../instruction.cpp:2117: End instruction execute. +DEBUG ../core.cpp:717: Register state: + %r 0: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r 1: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r 2: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r 3: 80001808 80001808 80001808 80001808 00000000 00000000 00000000 00000000 (0) + %r 4: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r 5: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r 6: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r 7: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r 8: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r 9: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r10: 00000004 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r11: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r12: 00000000 00000001 00000002 00000003 00000000 00000000 00000000 00000000 (0) + %r13: 0c000000 0c000000 0c000000 0c000000 00000000 00000000 00000000 00000000 (0) + %r14: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r15: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r16: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r17: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r18: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r19: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r20: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r21: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r22: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r23: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r24: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r25: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r26: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r27: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r28: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r29: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r30: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r31: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) +DEBUG ../core.cpp:726: Thread mask: + 1 1 1 1 0 0 0 0 + + +DEBUG ../core.cpp:388: Now 4 active threads in 3 +********************************** Fetch ********************************* +valid: 1 +PC: 80000084 +wid: 3 +rd: 12 rs1: 0 rs2: -1 +is_lw: 0 +is_sw: 0 +fetch_stall_cycles: 0 +mem_stall_cycles: 0 +stall_warp: 0 +wspawn: 0 +stalled: 0 + + + +------------------------------------------------------ +CYCLE: 54 +Stalled Warps: +0 0 0 0 0 0 0 0 + +********************************** Writeback ********************************* +valid: 1 +PC: 8000007c +wid: 0 +rd: 13 rs1: 0 rs2: -1 +is_lw: 0 +is_sw: 0 +fetch_stall_cycles: 0 +mem_stall_cycles: 0 +stall_warp: 0 +wspawn: 0 +stalled: 0 +********************************** LSU ********************************* +valid: 0 +PC: 0 +wid: 0 +rd: -1 rs1: -1 rs2: -1 +is_lw: 0 +is_sw: 0 +fetch_stall_cycles: 0 +mem_stall_cycles: 0 +stall_warp: 0 +wspawn: 0 +stalled: 0 +********************************** execute_unit ********************************* +valid: 1 +PC: 80000084 +wid: 1 +rd: 12 rs1: 0 rs2: -1 +is_lw: 0 +is_sw: 0 +fetch_stall_cycles: 0 +mem_stall_cycles: 0 +stall_warp: 0 +wspawn: 0 +stalled: 0 +********************************** scheduler ********************************* +valid: 1 +PC: 80000084 +wid: 2 +rd: 12 rs1: 0 rs2: -1 +is_lw: 0 +is_sw: 0 +fetch_stall_cycles: 0 +mem_stall_cycles: 0 +stall_warp: 0 +wspawn: 0 +stalled: 0 +********************************** Decode ********************************* +valid: 1 +PC: 80000084 +wid: 3 +rd: 12 rs1: 0 rs2: -1 +is_lw: 0 +is_sw: 0 +fetch_stall_cycles: 0 +mem_stall_cycles: 0 +stall_warp: 0 +wspawn: 0 +stalled: 0 +DEBUG ../core.cpp:386: Core step stepping warp 0[4] +DEBUG ../core.cpp:683: in step pc=0x80000080 +help: in PC: 80000080 +CUrrent CODE: 1a69693 +DEBUG ../core.cpp:703: Fetched at 0x80000080 +DEBUG ../core.cpp:704: 0x80000080: i_type; +DEBUG ../instruction.cpp:350: Begin instruction execute. +DEBUG ../instruction.cpp:2117: End instruction execute. +DEBUG ../core.cpp:717: Register state: + %r 0: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r 1: 80000014 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r 2: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r 3: 80001808 80001808 80001808 80001808 00000000 00000000 00000000 00000000 (0) + %r 4: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r 5: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r 6: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r 7: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r 8: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r 9: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r10: 00000004 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r11: 8000006c 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r12: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r13: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r14: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r15: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r16: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r17: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r18: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r19: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r20: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r21: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r22: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r23: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r24: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r25: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r26: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r27: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r28: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r29: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r30: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r31: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) +DEBUG ../core.cpp:726: Thread mask: + 1 1 1 1 0 0 0 0 + + +DEBUG ../core.cpp:388: Now 4 active threads in 0 +********************************** Fetch ********************************* +valid: 1 +PC: 80000080 +wid: 0 +rd: 13 rs1: 13 rs2: -1 +is_lw: 0 +is_sw: 0 +fetch_stall_cycles: 0 +mem_stall_cycles: 0 +stall_warp: 0 +wspawn: 0 +stalled: 0 + + + +------------------------------------------------------ +CYCLE: 55 +Stalled Warps: +0 0 0 0 0 0 0 0 + +********************************** Writeback ********************************* +valid: 1 +PC: 80000084 +wid: 1 +rd: 12 rs1: 0 rs2: -1 +is_lw: 0 +is_sw: 0 +fetch_stall_cycles: 0 +mem_stall_cycles: 0 +stall_warp: 0 +wspawn: 0 +stalled: 0 +********************************** LSU ********************************* +valid: 0 +PC: 0 +wid: 0 +rd: -1 rs1: -1 rs2: -1 +is_lw: 0 +is_sw: 0 +fetch_stall_cycles: 0 +mem_stall_cycles: 0 +stall_warp: 0 +wspawn: 0 +stalled: 0 +********************************** execute_unit ********************************* +valid: 1 +PC: 80000084 +wid: 2 +rd: 12 rs1: 0 rs2: -1 +is_lw: 0 +is_sw: 0 +fetch_stall_cycles: 0 +mem_stall_cycles: 0 +stall_warp: 0 +wspawn: 0 +stalled: 0 +********************************** scheduler ********************************* +valid: 1 +PC: 80000084 +wid: 3 +rd: 12 rs1: 0 rs2: -1 +is_lw: 0 +is_sw: 0 +fetch_stall_cycles: 0 +mem_stall_cycles: 0 +stall_warp: 0 +wspawn: 0 +stalled: 0 +********************************** Decode ********************************* +valid: 1 +PC: 80000080 +wid: 0 +rd: 13 rs1: 13 rs2: -1 +is_lw: 0 +is_sw: 0 +fetch_stall_cycles: 0 +mem_stall_cycles: 0 +stall_warp: 0 +wspawn: 0 +stalled: 0 +DEBUG ../core.cpp:386: Core step stepping warp 1[4] +DEBUG ../core.cpp:683: in step pc=0x80000088 +help: in PC: 80000088 +CUrrent CODE: a61593 +DEBUG ../core.cpp:703: Fetched at 0x80000088 +DEBUG ../core.cpp:704: 0x80000088: i_type; +DEBUG ../instruction.cpp:350: Begin instruction execute. +DEBUG ../instruction.cpp:2117: End instruction execute. +DEBUG ../core.cpp:717: Register state: + %r 0: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r 1: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r 2: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r 3: 80001808 80001808 80001808 80001808 00000000 00000000 00000000 00000000 (0) + %r 4: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r 5: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r 6: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r 7: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r 8: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r 9: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r10: 00000004 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r11: 00000000 00000400 00000800 00000c00 00000000 00000000 00000000 00000000 (0) + %r12: 00000000 00000001 00000002 00000003 00000000 00000000 00000000 00000000 (0) + %r13: 04000000 04000000 04000000 04000000 00000000 00000000 00000000 00000000 (0) + %r14: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r15: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r16: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r17: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r18: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r19: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r20: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r21: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r22: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r23: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r24: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r25: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r26: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r27: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r28: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r29: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r30: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r31: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) +DEBUG ../core.cpp:726: Thread mask: + 1 1 1 1 0 0 0 0 + + +DEBUG ../core.cpp:388: Now 4 active threads in 1 +********************************** Fetch ********************************* +valid: 1 +PC: 80000088 +wid: 1 +rd: 11 rs1: 12 rs2: -1 +is_lw: 0 +is_sw: 0 +fetch_stall_cycles: 0 +mem_stall_cycles: 0 +stall_warp: 0 +wspawn: 0 +stalled: 0 + + + +------------------------------------------------------ +CYCLE: 56 +Stalled Warps: +0 0 0 0 0 0 0 0 + +********************************** Writeback ********************************* +valid: 1 +PC: 80000084 +wid: 2 +rd: 12 rs1: 0 rs2: -1 +is_lw: 0 +is_sw: 0 +fetch_stall_cycles: 0 +mem_stall_cycles: 0 +stall_warp: 0 +wspawn: 0 +stalled: 0 +********************************** LSU ********************************* +valid: 0 +PC: 0 +wid: 0 +rd: -1 rs1: -1 rs2: -1 +is_lw: 0 +is_sw: 0 +fetch_stall_cycles: 0 +mem_stall_cycles: 0 +stall_warp: 0 +wspawn: 0 +stalled: 0 +********************************** execute_unit ********************************* +valid: 1 +PC: 80000084 +wid: 3 +rd: 12 rs1: 0 rs2: -1 +is_lw: 0 +is_sw: 0 +fetch_stall_cycles: 0 +mem_stall_cycles: 0 +stall_warp: 0 +wspawn: 0 +stalled: 0 +********************************** scheduler ********************************* +valid: 1 +PC: 80000080 +wid: 0 +rd: 13 rs1: 13 rs2: -1 +is_lw: 0 +is_sw: 0 +fetch_stall_cycles: 0 +mem_stall_cycles: 0 +stall_warp: 0 +wspawn: 0 +stalled: 0 +********************************** Decode ********************************* +valid: 1 +PC: 80000088 +wid: 1 +rd: 11 rs1: 12 rs2: -1 +is_lw: 0 +is_sw: 0 +fetch_stall_cycles: 0 +mem_stall_cycles: 0 +stall_warp: 0 +wspawn: 0 +stalled: 0 +DEBUG ../core.cpp:386: Core step stepping warp 2[4] +DEBUG ../core.cpp:683: in step pc=0x80000088 +help: in PC: 80000088 +CUrrent CODE: a61593 +DEBUG ../core.cpp:703: Fetched at 0x80000088 +DEBUG ../core.cpp:704: 0x80000088: i_type; +DEBUG ../instruction.cpp:350: Begin instruction execute. +DEBUG ../instruction.cpp:2117: End instruction execute. +DEBUG ../core.cpp:717: Register state: + %r 0: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r 1: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r 2: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r 3: 80001808 80001808 80001808 80001808 00000000 00000000 00000000 00000000 (0) + %r 4: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r 5: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r 6: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r 7: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r 8: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r 9: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r10: 00000004 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r11: 00000000 00000400 00000800 00000c00 00000000 00000000 00000000 00000000 (0) + %r12: 00000000 00000001 00000002 00000003 00000000 00000000 00000000 00000000 (0) + %r13: 08000000 08000000 08000000 08000000 00000000 00000000 00000000 00000000 (0) + %r14: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r15: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r16: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r17: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r18: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r19: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r20: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r21: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r22: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r23: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r24: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r25: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r26: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r27: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r28: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r29: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r30: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r31: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) +DEBUG ../core.cpp:726: Thread mask: + 1 1 1 1 0 0 0 0 + + +DEBUG ../core.cpp:388: Now 4 active threads in 2 +********************************** Fetch ********************************* +valid: 1 +PC: 80000088 +wid: 2 +rd: 11 rs1: 12 rs2: -1 +is_lw: 0 +is_sw: 0 +fetch_stall_cycles: 0 +mem_stall_cycles: 0 +stall_warp: 0 +wspawn: 0 +stalled: 0 + + + +------------------------------------------------------ +CYCLE: 57 +Stalled Warps: +0 0 0 0 0 0 0 0 + +********************************** Writeback ********************************* +valid: 1 +PC: 80000084 +wid: 3 +rd: 12 rs1: 0 rs2: -1 +is_lw: 0 +is_sw: 0 +fetch_stall_cycles: 0 +mem_stall_cycles: 0 +stall_warp: 0 +wspawn: 0 +stalled: 0 +********************************** LSU ********************************* +valid: 0 +PC: 0 +wid: 0 +rd: -1 rs1: -1 rs2: -1 +is_lw: 0 +is_sw: 0 +fetch_stall_cycles: 0 +mem_stall_cycles: 0 +stall_warp: 0 +wspawn: 0 +stalled: 0 +********************************** execute_unit ********************************* +valid: 1 +PC: 80000080 +wid: 0 +rd: 13 rs1: 13 rs2: -1 +is_lw: 0 +is_sw: 0 +fetch_stall_cycles: 0 +mem_stall_cycles: 0 +stall_warp: 0 +wspawn: 0 +stalled: 0 +********************************** scheduler ********************************* +valid: 1 +PC: 80000088 +wid: 1 +rd: 11 rs1: 12 rs2: -1 +is_lw: 0 +is_sw: 0 +fetch_stall_cycles: 0 +mem_stall_cycles: 0 +stall_warp: 0 +wspawn: 0 +stalled: 0 +********************************** Decode ********************************* +valid: 1 +PC: 80000088 +wid: 2 +rd: 11 rs1: 12 rs2: -1 +is_lw: 0 +is_sw: 0 +fetch_stall_cycles: 0 +mem_stall_cycles: 0 +stall_warp: 0 +wspawn: 0 +stalled: 0 +DEBUG ../core.cpp:386: Core step stepping warp 3[4] +DEBUG ../core.cpp:683: in step pc=0x80000088 +help: in PC: 80000088 +CUrrent CODE: a61593 +DEBUG ../core.cpp:703: Fetched at 0x80000088 +DEBUG ../core.cpp:704: 0x80000088: i_type; +DEBUG ../instruction.cpp:350: Begin instruction execute. +DEBUG ../instruction.cpp:2117: End instruction execute. +DEBUG ../core.cpp:717: Register state: + %r 0: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r 1: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r 2: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r 3: 80001808 80001808 80001808 80001808 00000000 00000000 00000000 00000000 (0) + %r 4: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r 5: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r 6: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r 7: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r 8: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r 9: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r10: 00000004 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r11: 00000000 00000400 00000800 00000c00 00000000 00000000 00000000 00000000 (0) + %r12: 00000000 00000001 00000002 00000003 00000000 00000000 00000000 00000000 (0) + %r13: 0c000000 0c000000 0c000000 0c000000 00000000 00000000 00000000 00000000 (0) + %r14: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r15: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r16: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r17: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r18: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r19: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r20: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r21: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r22: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r23: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r24: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r25: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r26: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r27: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r28: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r29: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r30: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r31: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) +DEBUG ../core.cpp:726: Thread mask: + 1 1 1 1 0 0 0 0 + + +DEBUG ../core.cpp:388: Now 4 active threads in 3 +********************************** Fetch ********************************* +valid: 1 +PC: 80000088 +wid: 3 +rd: 11 rs1: 12 rs2: -1 +is_lw: 0 +is_sw: 0 +fetch_stall_cycles: 0 +mem_stall_cycles: 0 +stall_warp: 0 +wspawn: 0 +stalled: 0 + + + +------------------------------------------------------ +CYCLE: 58 +Stalled Warps: +0 0 0 0 0 0 0 0 + +********************************** Writeback ********************************* +valid: 1 +PC: 80000080 +wid: 0 +rd: 13 rs1: 13 rs2: -1 +is_lw: 0 +is_sw: 0 +fetch_stall_cycles: 0 +mem_stall_cycles: 0 +stall_warp: 0 +wspawn: 0 +stalled: 0 +********************************** LSU ********************************* +valid: 0 +PC: 0 +wid: 0 +rd: -1 rs1: -1 rs2: -1 +is_lw: 0 +is_sw: 0 +fetch_stall_cycles: 0 +mem_stall_cycles: 0 +stall_warp: 0 +wspawn: 0 +stalled: 0 +********************************** execute_unit ********************************* +valid: 1 +PC: 80000088 +wid: 1 +rd: 11 rs1: 12 rs2: -1 +is_lw: 0 +is_sw: 0 +fetch_stall_cycles: 0 +mem_stall_cycles: 0 +stall_warp: 0 +wspawn: 0 +stalled: 0 +********************************** scheduler ********************************* +valid: 1 +PC: 80000088 +wid: 2 +rd: 11 rs1: 12 rs2: -1 +is_lw: 0 +is_sw: 0 +fetch_stall_cycles: 0 +mem_stall_cycles: 0 +stall_warp: 0 +wspawn: 0 +stalled: 0 +********************************** Decode ********************************* +valid: 1 +PC: 80000088 +wid: 3 +rd: 11 rs1: 12 rs2: -1 +is_lw: 0 +is_sw: 0 +fetch_stall_cycles: 0 +mem_stall_cycles: 0 +stall_warp: 0 +wspawn: 0 +stalled: 0 +DEBUG ../core.cpp:386: Core step stepping warp 0[4] +DEBUG ../core.cpp:683: in step pc=0x80000084 +help: in PC: 80000084 +CUrrent CODE: 2002673 +DEBUG ../core.cpp:703: Fetched at 0x80000084 +DEBUG ../core.cpp:704: 0x80000084: SYS; +DEBUG ../instruction.cpp:350: Begin instruction execute. +DEBUG ../instruction.cpp:2117: End instruction execute. +DEBUG ../core.cpp:717: Register state: + %r 0: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r 1: 80000014 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r 2: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r 3: 80001808 80001808 80001808 80001808 00000000 00000000 00000000 00000000 (0) + %r 4: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r 5: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r 6: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r 7: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r 8: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r 9: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r10: 00000004 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r11: 8000006c 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r12: 00000000 00000001 00000002 00000003 00000000 00000000 00000000 00000000 (0) + %r13: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r14: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r15: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r16: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r17: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r18: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r19: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r20: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r21: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r22: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r23: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r24: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r25: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r26: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r27: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r28: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r29: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r30: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r31: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) +DEBUG ../core.cpp:726: Thread mask: + 1 1 1 1 0 0 0 0 + + +DEBUG ../core.cpp:388: Now 4 active threads in 0 +********************************** Fetch ********************************* +valid: 1 +PC: 80000084 +wid: 0 +rd: 12 rs1: 0 rs2: -1 +is_lw: 0 +is_sw: 0 +fetch_stall_cycles: 0 +mem_stall_cycles: 0 +stall_warp: 0 +wspawn: 0 +stalled: 0 + + + +------------------------------------------------------ +CYCLE: 59 +Stalled Warps: +0 0 0 0 0 0 0 0 + +********************************** Writeback ********************************* +valid: 1 +PC: 80000088 +wid: 1 +rd: 11 rs1: 12 rs2: -1 +is_lw: 0 +is_sw: 0 +fetch_stall_cycles: 0 +mem_stall_cycles: 0 +stall_warp: 0 +wspawn: 0 +stalled: 0 +********************************** LSU ********************************* +valid: 0 +PC: 0 +wid: 0 +rd: -1 rs1: -1 rs2: -1 +is_lw: 0 +is_sw: 0 +fetch_stall_cycles: 0 +mem_stall_cycles: 0 +stall_warp: 0 +wspawn: 0 +stalled: 0 +********************************** execute_unit ********************************* +valid: 1 +PC: 80000088 +wid: 2 +rd: 11 rs1: 12 rs2: -1 +is_lw: 0 +is_sw: 0 +fetch_stall_cycles: 0 +mem_stall_cycles: 0 +stall_warp: 0 +wspawn: 0 +stalled: 0 +********************************** scheduler ********************************* +valid: 1 +PC: 80000088 +wid: 3 +rd: 11 rs1: 12 rs2: -1 +is_lw: 0 +is_sw: 0 +fetch_stall_cycles: 0 +mem_stall_cycles: 0 +stall_warp: 0 +wspawn: 0 +stalled: 0 +********************************** Decode ********************************* +valid: 1 +PC: 80000084 +wid: 0 +rd: 12 rs1: 0 rs2: -1 +is_lw: 0 +is_sw: 0 +fetch_stall_cycles: 0 +mem_stall_cycles: 0 +stall_warp: 0 +wspawn: 0 +stalled: 0 +DEBUG ../core.cpp:386: Core step stepping warp 1[4] +DEBUG ../core.cpp:683: in step pc=0x8000008c +help: in PC: 8000008c +CUrrent CODE: 261613 +DEBUG ../core.cpp:703: Fetched at 0x8000008c +DEBUG ../core.cpp:704: 0x8000008c: i_type; +DEBUG ../instruction.cpp:350: Begin instruction execute. +DEBUG ../instruction.cpp:2117: End instruction execute. +DEBUG ../core.cpp:717: Register state: + %r 0: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r 1: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r 2: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r 3: 80001808 80001808 80001808 80001808 00000000 00000000 00000000 00000000 (0) + %r 4: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r 5: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r 6: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r 7: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r 8: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r 9: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r10: 00000004 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r11: 00000000 00000400 00000800 00000c00 00000000 00000000 00000000 00000000 (0) + %r12: 00000000 00000004 00000008 0000000c 00000000 00000000 00000000 00000000 (0) + %r13: 04000000 04000000 04000000 04000000 00000000 00000000 00000000 00000000 (0) + %r14: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r15: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r16: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r17: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r18: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r19: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r20: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r21: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r22: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r23: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r24: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r25: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r26: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r27: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r28: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r29: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r30: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r31: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) +DEBUG ../core.cpp:726: Thread mask: + 1 1 1 1 0 0 0 0 + + +DEBUG ../core.cpp:388: Now 4 active threads in 1 +********************************** Fetch ********************************* +valid: 1 +PC: 8000008c +wid: 1 +rd: 12 rs1: 12 rs2: -1 +is_lw: 0 +is_sw: 0 +fetch_stall_cycles: 0 +mem_stall_cycles: 0 +stall_warp: 0 +wspawn: 0 +stalled: 0 + + + +------------------------------------------------------ +CYCLE: 60 +Stalled Warps: +0 0 0 0 0 0 0 0 + +********************************** Writeback ********************************* +valid: 1 +PC: 80000088 +wid: 2 +rd: 11 rs1: 12 rs2: -1 +is_lw: 0 +is_sw: 0 +fetch_stall_cycles: 0 +mem_stall_cycles: 0 +stall_warp: 0 +wspawn: 0 +stalled: 0 +********************************** LSU ********************************* +valid: 0 +PC: 0 +wid: 0 +rd: -1 rs1: -1 rs2: -1 +is_lw: 0 +is_sw: 0 +fetch_stall_cycles: 0 +mem_stall_cycles: 0 +stall_warp: 0 +wspawn: 0 +stalled: 0 +********************************** execute_unit ********************************* +valid: 1 +PC: 80000088 +wid: 3 +rd: 11 rs1: 12 rs2: -1 +is_lw: 0 +is_sw: 0 +fetch_stall_cycles: 0 +mem_stall_cycles: 0 +stall_warp: 0 +wspawn: 0 +stalled: 0 +********************************** scheduler ********************************* +valid: 1 +PC: 80000084 +wid: 0 +rd: 12 rs1: 0 rs2: -1 +is_lw: 0 +is_sw: 0 +fetch_stall_cycles: 0 +mem_stall_cycles: 0 +stall_warp: 0 +wspawn: 0 +stalled: 0 +********************************** Decode ********************************* +valid: 1 +PC: 8000008c +wid: 1 +rd: 12 rs1: 12 rs2: -1 +is_lw: 0 +is_sw: 0 +fetch_stall_cycles: 0 +mem_stall_cycles: 0 +stall_warp: 0 +wspawn: 0 +stalled: 0 +DEBUG ../core.cpp:386: Core step stepping warp 2[4] +DEBUG ../core.cpp:683: in step pc=0x8000008c +help: in PC: 8000008c +CUrrent CODE: 261613 +DEBUG ../core.cpp:703: Fetched at 0x8000008c +DEBUG ../core.cpp:704: 0x8000008c: i_type; +DEBUG ../instruction.cpp:350: Begin instruction execute. +DEBUG ../instruction.cpp:2117: End instruction execute. +DEBUG ../core.cpp:717: Register state: + %r 0: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r 1: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r 2: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r 3: 80001808 80001808 80001808 80001808 00000000 00000000 00000000 00000000 (0) + %r 4: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r 5: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r 6: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r 7: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r 8: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r 9: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r10: 00000004 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r11: 00000000 00000400 00000800 00000c00 00000000 00000000 00000000 00000000 (0) + %r12: 00000000 00000004 00000008 0000000c 00000000 00000000 00000000 00000000 (0) + %r13: 08000000 08000000 08000000 08000000 00000000 00000000 00000000 00000000 (0) + %r14: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r15: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r16: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r17: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r18: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r19: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r20: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r21: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r22: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r23: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r24: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r25: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r26: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r27: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r28: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r29: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r30: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r31: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) +DEBUG ../core.cpp:726: Thread mask: + 1 1 1 1 0 0 0 0 + + +DEBUG ../core.cpp:388: Now 4 active threads in 2 +********************************** Fetch ********************************* +valid: 1 +PC: 8000008c +wid: 2 +rd: 12 rs1: 12 rs2: -1 +is_lw: 0 +is_sw: 0 +fetch_stall_cycles: 0 +mem_stall_cycles: 0 +stall_warp: 0 +wspawn: 0 +stalled: 0 + + + +------------------------------------------------------ +CYCLE: 61 +Stalled Warps: +0 0 0 0 0 0 0 0 + +********************************** Writeback ********************************* +valid: 1 +PC: 80000088 +wid: 3 +rd: 11 rs1: 12 rs2: -1 +is_lw: 0 +is_sw: 0 +fetch_stall_cycles: 0 +mem_stall_cycles: 0 +stall_warp: 0 +wspawn: 0 +stalled: 0 +********************************** LSU ********************************* +valid: 0 +PC: 0 +wid: 0 +rd: -1 rs1: -1 rs2: -1 +is_lw: 0 +is_sw: 0 +fetch_stall_cycles: 0 +mem_stall_cycles: 0 +stall_warp: 0 +wspawn: 0 +stalled: 0 +********************************** execute_unit ********************************* +valid: 1 +PC: 80000084 +wid: 0 +rd: 12 rs1: 0 rs2: -1 +is_lw: 0 +is_sw: 0 +fetch_stall_cycles: 0 +mem_stall_cycles: 0 +stall_warp: 0 +wspawn: 0 +stalled: 0 +********************************** scheduler ********************************* +valid: 1 +PC: 8000008c +wid: 1 +rd: 12 rs1: 12 rs2: -1 +is_lw: 0 +is_sw: 0 +fetch_stall_cycles: 0 +mem_stall_cycles: 0 +stall_warp: 0 +wspawn: 0 +stalled: 0 +********************************** Decode ********************************* +valid: 1 +PC: 8000008c +wid: 2 +rd: 12 rs1: 12 rs2: -1 +is_lw: 0 +is_sw: 0 +fetch_stall_cycles: 0 +mem_stall_cycles: 0 +stall_warp: 0 +wspawn: 0 +stalled: 0 +DEBUG ../core.cpp:386: Core step stepping warp 3[4] +DEBUG ../core.cpp:683: in step pc=0x8000008c +help: in PC: 8000008c +CUrrent CODE: 261613 +DEBUG ../core.cpp:703: Fetched at 0x8000008c +DEBUG ../core.cpp:704: 0x8000008c: i_type; +DEBUG ../instruction.cpp:350: Begin instruction execute. +DEBUG ../instruction.cpp:2117: End instruction execute. +DEBUG ../core.cpp:717: Register state: + %r 0: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r 1: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r 2: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r 3: 80001808 80001808 80001808 80001808 00000000 00000000 00000000 00000000 (0) + %r 4: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r 5: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r 6: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r 7: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r 8: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r 9: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r10: 00000004 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r11: 00000000 00000400 00000800 00000c00 00000000 00000000 00000000 00000000 (0) + %r12: 00000000 00000004 00000008 0000000c 00000000 00000000 00000000 00000000 (0) + %r13: 0c000000 0c000000 0c000000 0c000000 00000000 00000000 00000000 00000000 (0) + %r14: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r15: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r16: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r17: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r18: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r19: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r20: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r21: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r22: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r23: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r24: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r25: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r26: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r27: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r28: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r29: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r30: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r31: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) +DEBUG ../core.cpp:726: Thread mask: + 1 1 1 1 0 0 0 0 + + +DEBUG ../core.cpp:388: Now 4 active threads in 3 +********************************** Fetch ********************************* +valid: 1 +PC: 8000008c +wid: 3 +rd: 12 rs1: 12 rs2: -1 +is_lw: 0 +is_sw: 0 +fetch_stall_cycles: 0 +mem_stall_cycles: 0 +stall_warp: 0 +wspawn: 0 +stalled: 0 + + + +------------------------------------------------------ +CYCLE: 62 +Stalled Warps: +0 0 0 0 0 0 0 0 + +********************************** Writeback ********************************* +valid: 1 +PC: 80000084 +wid: 0 +rd: 12 rs1: 0 rs2: -1 +is_lw: 0 +is_sw: 0 +fetch_stall_cycles: 0 +mem_stall_cycles: 0 +stall_warp: 0 +wspawn: 0 +stalled: 0 +********************************** LSU ********************************* +valid: 0 +PC: 0 +wid: 0 +rd: -1 rs1: -1 rs2: -1 +is_lw: 0 +is_sw: 0 +fetch_stall_cycles: 0 +mem_stall_cycles: 0 +stall_warp: 0 +wspawn: 0 +stalled: 0 +********************************** execute_unit ********************************* +valid: 1 +PC: 8000008c +wid: 1 +rd: 12 rs1: 12 rs2: -1 +is_lw: 0 +is_sw: 0 +fetch_stall_cycles: 0 +mem_stall_cycles: 0 +stall_warp: 0 +wspawn: 0 +stalled: 0 +********************************** scheduler ********************************* +valid: 1 +PC: 8000008c +wid: 2 +rd: 12 rs1: 12 rs2: -1 +is_lw: 0 +is_sw: 0 +fetch_stall_cycles: 0 +mem_stall_cycles: 0 +stall_warp: 0 +wspawn: 0 +stalled: 0 +********************************** Decode ********************************* +valid: 1 +PC: 8000008c +wid: 3 +rd: 12 rs1: 12 rs2: -1 +is_lw: 0 +is_sw: 0 +fetch_stall_cycles: 0 +mem_stall_cycles: 0 +stall_warp: 0 +wspawn: 0 +stalled: 0 +DEBUG ../core.cpp:386: Core step stepping warp 0[4] +DEBUG ../core.cpp:683: in step pc=0x80000088 +help: in PC: 80000088 +CUrrent CODE: a61593 +DEBUG ../core.cpp:703: Fetched at 0x80000088 +DEBUG ../core.cpp:704: 0x80000088: i_type; +DEBUG ../instruction.cpp:350: Begin instruction execute. +DEBUG ../instruction.cpp:2117: End instruction execute. +DEBUG ../core.cpp:717: Register state: + %r 0: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r 1: 80000014 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r 2: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r 3: 80001808 80001808 80001808 80001808 00000000 00000000 00000000 00000000 (0) + %r 4: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r 5: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r 6: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r 7: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r 8: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r 9: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r10: 00000004 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r11: 00000000 00000400 00000800 00000c00 00000000 00000000 00000000 00000000 (0) + %r12: 00000000 00000001 00000002 00000003 00000000 00000000 00000000 00000000 (0) + %r13: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r14: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r15: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r16: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r17: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r18: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r19: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r20: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r21: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r22: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r23: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r24: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r25: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r26: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r27: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r28: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r29: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r30: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r31: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) +DEBUG ../core.cpp:726: Thread mask: + 1 1 1 1 0 0 0 0 + + +DEBUG ../core.cpp:388: Now 4 active threads in 0 +********************************** Fetch ********************************* +valid: 1 +PC: 80000088 +wid: 0 +rd: 11 rs1: 12 rs2: -1 +is_lw: 0 +is_sw: 0 +fetch_stall_cycles: 0 +mem_stall_cycles: 0 +stall_warp: 0 +wspawn: 0 +stalled: 0 + + + +------------------------------------------------------ +CYCLE: 63 +Stalled Warps: +0 0 0 0 0 0 0 0 + +********************************** Writeback ********************************* +valid: 1 +PC: 8000008c +wid: 1 +rd: 12 rs1: 12 rs2: -1 +is_lw: 0 +is_sw: 0 +fetch_stall_cycles: 0 +mem_stall_cycles: 0 +stall_warp: 0 +wspawn: 0 +stalled: 0 +********************************** LSU ********************************* +valid: 0 +PC: 0 +wid: 0 +rd: -1 rs1: -1 rs2: -1 +is_lw: 0 +is_sw: 0 +fetch_stall_cycles: 0 +mem_stall_cycles: 0 +stall_warp: 0 +wspawn: 0 +stalled: 0 +********************************** execute_unit ********************************* +valid: 1 +PC: 8000008c +wid: 2 +rd: 12 rs1: 12 rs2: -1 +is_lw: 0 +is_sw: 0 +fetch_stall_cycles: 0 +mem_stall_cycles: 0 +stall_warp: 0 +wspawn: 0 +stalled: 0 +********************************** scheduler ********************************* +valid: 1 +PC: 8000008c +wid: 3 +rd: 12 rs1: 12 rs2: -1 +is_lw: 0 +is_sw: 0 +fetch_stall_cycles: 0 +mem_stall_cycles: 0 +stall_warp: 0 +wspawn: 0 +stalled: 0 +********************************** Decode ********************************* +valid: 1 +PC: 80000088 +wid: 0 +rd: 11 rs1: 12 rs2: -1 +is_lw: 0 +is_sw: 0 +fetch_stall_cycles: 0 +mem_stall_cycles: 0 +stall_warp: 0 +wspawn: 0 +stalled: 0 +DEBUG ../core.cpp:386: Core step stepping warp 1[4] +DEBUG ../core.cpp:683: in step pc=0x80000090 +help: in PC: 80000090 +CUrrent CODE: 6ffff137 +DEBUG ../core.cpp:703: Fetched at 0x80000090 +DEBUG ../core.cpp:704: 0x80000090: lui; +DEBUG ../instruction.cpp:350: Begin instruction execute. +DEBUG ../instruction.cpp:2117: End instruction execute. +DEBUG ../core.cpp:717: Register state: + %r 0: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r 1: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r 2: 6ffff000 6ffff000 6ffff000 6ffff000 00000000 00000000 00000000 00000000 (0) + %r 3: 80001808 80001808 80001808 80001808 00000000 00000000 00000000 00000000 (0) + %r 4: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r 5: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r 6: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r 7: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r 8: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r 9: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r10: 00000004 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r11: 00000000 00000400 00000800 00000c00 00000000 00000000 00000000 00000000 (0) + %r12: 00000000 00000004 00000008 0000000c 00000000 00000000 00000000 00000000 (0) + %r13: 04000000 04000000 04000000 04000000 00000000 00000000 00000000 00000000 (0) + %r14: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r15: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r16: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r17: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r18: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r19: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r20: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r21: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r22: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r23: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r24: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r25: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r26: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r27: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r28: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r29: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r30: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r31: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) +DEBUG ../core.cpp:726: Thread mask: + 1 1 1 1 0 0 0 0 + + +DEBUG ../core.cpp:388: Now 4 active threads in 1 +********************************** Fetch ********************************* +valid: 1 +PC: 80000090 +wid: 1 +rd: 2 rs1: -1 rs2: -1 +is_lw: 0 +is_sw: 0 +fetch_stall_cycles: 3 +mem_stall_cycles: 0 +stall_warp: 0 +wspawn: 0 +stalled: 0 + + + +------------------------------------------------------ +CYCLE: 64 +Stalled Warps: +0 0 0 0 0 0 0 0 + +********************************** Writeback ********************************* +valid: 1 +PC: 8000008c +wid: 2 +rd: 12 rs1: 12 rs2: -1 +is_lw: 0 +is_sw: 0 +fetch_stall_cycles: 0 +mem_stall_cycles: 0 +stall_warp: 0 +wspawn: 0 +stalled: 0 +********************************** LSU ********************************* +valid: 0 +PC: 0 +wid: 0 +rd: -1 rs1: -1 rs2: -1 +is_lw: 0 +is_sw: 0 +fetch_stall_cycles: 0 +mem_stall_cycles: 0 +stall_warp: 0 +wspawn: 0 +stalled: 0 +********************************** execute_unit ********************************* +valid: 1 +PC: 8000008c +wid: 3 +rd: 12 rs1: 12 rs2: -1 +is_lw: 0 +is_sw: 0 +fetch_stall_cycles: 0 +mem_stall_cycles: 0 +stall_warp: 0 +wspawn: 0 +stalled: 0 +********************************** scheduler ********************************* +valid: 1 +PC: 80000088 +wid: 0 +rd: 11 rs1: 12 rs2: -1 +is_lw: 0 +is_sw: 0 +fetch_stall_cycles: 0 +mem_stall_cycles: 0 +stall_warp: 0 +wspawn: 0 +stalled: 0 +********************************** Decode ********************************* +valid: 0 +PC: 0 +wid: 2 +rd: -1 rs1: -1 rs2: -1 +is_lw: 0 +is_sw: 0 +fetch_stall_cycles: 0 +mem_stall_cycles: 0 +stall_warp: 0 +wspawn: 0 +stalled: 0 +********************************** Fetch ********************************* +valid: 1 +PC: 80000090 +wid: 1 +rd: 2 rs1: -1 rs2: -1 +is_lw: 0 +is_sw: 0 +fetch_stall_cycles: 2 +mem_stall_cycles: 0 +stall_warp: 0 +wspawn: 0 +stalled: 0 + + + +------------------------------------------------------ +CYCLE: 65 +Stalled Warps: +0 0 0 0 0 0 0 0 + +********************************** Writeback ********************************* +valid: 1 +PC: 8000008c +wid: 3 +rd: 12 rs1: 12 rs2: -1 +is_lw: 0 +is_sw: 0 +fetch_stall_cycles: 0 +mem_stall_cycles: 0 +stall_warp: 0 +wspawn: 0 +stalled: 0 +********************************** LSU ********************************* +valid: 0 +PC: 0 +wid: 0 +rd: -1 rs1: -1 rs2: -1 +is_lw: 0 +is_sw: 0 +fetch_stall_cycles: 0 +mem_stall_cycles: 0 +stall_warp: 0 +wspawn: 0 +stalled: 0 +********************************** execute_unit ********************************* +valid: 1 +PC: 80000088 +wid: 0 +rd: 11 rs1: 12 rs2: -1 +is_lw: 0 +is_sw: 0 +fetch_stall_cycles: 0 +mem_stall_cycles: 0 +stall_warp: 0 +wspawn: 0 +stalled: 0 +********************************** scheduler ********************************* +valid: 0 +PC: 0 +wid: 2 +rd: -1 rs1: -1 rs2: -1 +is_lw: 0 +is_sw: 0 +fetch_stall_cycles: 0 +mem_stall_cycles: 0 +stall_warp: 0 +wspawn: 0 +stalled: 0 +********************************** Decode ********************************* +valid: 0 +PC: 0 +wid: 2 +rd: -1 rs1: -1 rs2: -1 +is_lw: 0 +is_sw: 0 +fetch_stall_cycles: 0 +mem_stall_cycles: 0 +stall_warp: 0 +wspawn: 0 +stalled: 0 +********************************** Fetch ********************************* +valid: 1 +PC: 80000090 +wid: 1 +rd: 2 rs1: -1 rs2: -1 +is_lw: 0 +is_sw: 0 +fetch_stall_cycles: 1 +mem_stall_cycles: 0 +stall_warp: 0 +wspawn: 0 +stalled: 0 + + + +------------------------------------------------------ +CYCLE: 66 +Stalled Warps: +0 0 0 0 0 0 0 0 + +********************************** Writeback ********************************* +valid: 1 +PC: 80000088 +wid: 0 +rd: 11 rs1: 12 rs2: -1 +is_lw: 0 +is_sw: 0 +fetch_stall_cycles: 0 +mem_stall_cycles: 0 +stall_warp: 0 +wspawn: 0 +stalled: 0 +********************************** LSU ********************************* +valid: 0 +PC: 0 +wid: 0 +rd: -1 rs1: -1 rs2: -1 +is_lw: 0 +is_sw: 0 +fetch_stall_cycles: 0 +mem_stall_cycles: 0 +stall_warp: 0 +wspawn: 0 +stalled: 0 +********************************** execute_unit ********************************* +valid: 0 +PC: 0 +wid: 2 +rd: -1 rs1: -1 rs2: -1 +is_lw: 0 +is_sw: 0 +fetch_stall_cycles: 0 +mem_stall_cycles: 0 +stall_warp: 0 +wspawn: 0 +stalled: 0 +********************************** scheduler ********************************* +valid: 0 +PC: 0 +wid: 2 +rd: -1 rs1: -1 rs2: -1 +is_lw: 0 +is_sw: 0 +fetch_stall_cycles: 0 +mem_stall_cycles: 0 +stall_warp: 0 +wspawn: 0 +stalled: 0 +********************************** Decode ********************************* +valid: 0 +PC: 0 +wid: 2 +rd: -1 rs1: -1 rs2: -1 +is_lw: 0 +is_sw: 0 +fetch_stall_cycles: 0 +mem_stall_cycles: 0 +stall_warp: 0 +wspawn: 0 +stalled: 0 +********************************** Fetch ********************************* +valid: 1 +PC: 80000090 +wid: 1 +rd: 2 rs1: -1 rs2: -1 +is_lw: 0 +is_sw: 0 +fetch_stall_cycles: 0 +mem_stall_cycles: 0 +stall_warp: 0 +wspawn: 0 +stalled: 0 + + + +------------------------------------------------------ +CYCLE: 67 +Stalled Warps: +0 0 0 0 0 0 0 0 + +********************************** Writeback ********************************* +valid: 0 +PC: 0 +wid: 2 +rd: -1 rs1: -1 rs2: -1 +is_lw: 0 +is_sw: 0 +fetch_stall_cycles: 0 +mem_stall_cycles: 0 +stall_warp: 0 +wspawn: 0 +stalled: 0 +********************************** LSU ********************************* +valid: 0 +PC: 0 +wid: 0 +rd: -1 rs1: -1 rs2: -1 +is_lw: 0 +is_sw: 0 +fetch_stall_cycles: 0 +mem_stall_cycles: 0 +stall_warp: 0 +wspawn: 0 +stalled: 0 +********************************** execute_unit ********************************* +valid: 0 +PC: 0 +wid: 2 +rd: -1 rs1: -1 rs2: -1 +is_lw: 0 +is_sw: 0 +fetch_stall_cycles: 0 +mem_stall_cycles: 0 +stall_warp: 0 +wspawn: 0 +stalled: 0 +********************************** scheduler ********************************* +valid: 0 +PC: 0 +wid: 2 +rd: -1 rs1: -1 rs2: -1 +is_lw: 0 +is_sw: 0 +fetch_stall_cycles: 0 +mem_stall_cycles: 0 +stall_warp: 0 +wspawn: 0 +stalled: 0 +********************************** Decode ********************************* +valid: 1 +PC: 80000090 +wid: 1 +rd: 2 rs1: -1 rs2: -1 +is_lw: 0 +is_sw: 0 +fetch_stall_cycles: 0 +mem_stall_cycles: 0 +stall_warp: 0 +wspawn: 0 +stalled: 0 +DEBUG ../core.cpp:386: Core step stepping warp 2[4] +DEBUG ../core.cpp:683: in step pc=0x80000090 +help: in PC: 80000090 +CUrrent CODE: 6ffff137 +DEBUG ../core.cpp:703: Fetched at 0x80000090 +DEBUG ../core.cpp:704: 0x80000090: lui; +DEBUG ../instruction.cpp:350: Begin instruction execute. +DEBUG ../instruction.cpp:2117: End instruction execute. +DEBUG ../core.cpp:717: Register state: + %r 0: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r 1: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r 2: 6ffff000 6ffff000 6ffff000 6ffff000 00000000 00000000 00000000 00000000 (0) + %r 3: 80001808 80001808 80001808 80001808 00000000 00000000 00000000 00000000 (0) + %r 4: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r 5: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r 6: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r 7: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r 8: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r 9: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r10: 00000004 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r11: 00000000 00000400 00000800 00000c00 00000000 00000000 00000000 00000000 (0) + %r12: 00000000 00000004 00000008 0000000c 00000000 00000000 00000000 00000000 (0) + %r13: 08000000 08000000 08000000 08000000 00000000 00000000 00000000 00000000 (0) + %r14: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r15: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r16: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r17: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r18: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r19: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r20: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r21: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r22: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r23: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r24: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r25: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r26: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r27: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r28: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r29: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r30: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r31: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) +DEBUG ../core.cpp:726: Thread mask: + 1 1 1 1 0 0 0 0 + + +DEBUG ../core.cpp:388: Now 4 active threads in 2 +********************************** Fetch ********************************* +valid: 1 +PC: 80000090 +wid: 2 +rd: 2 rs1: -1 rs2: -1 +is_lw: 0 +is_sw: 0 +fetch_stall_cycles: 0 +mem_stall_cycles: 0 +stall_warp: 0 +wspawn: 0 +stalled: 0 + + + +------------------------------------------------------ +CYCLE: 68 +Stalled Warps: +0 0 0 0 0 0 0 0 + +********************************** Writeback ********************************* +valid: 0 +PC: 0 +wid: 3 +rd: -1 rs1: -1 rs2: -1 +is_lw: 0 +is_sw: 0 +fetch_stall_cycles: 0 +mem_stall_cycles: 0 +stall_warp: 0 +wspawn: 0 +stalled: 0 +********************************** LSU ********************************* +valid: 0 +PC: 0 +wid: 0 +rd: -1 rs1: -1 rs2: -1 +is_lw: 0 +is_sw: 0 +fetch_stall_cycles: 0 +mem_stall_cycles: 0 +stall_warp: 0 +wspawn: 0 +stalled: 0 +********************************** execute_unit ********************************* +valid: 0 +PC: 0 +wid: 2 +rd: -1 rs1: -1 rs2: -1 +is_lw: 0 +is_sw: 0 +fetch_stall_cycles: 0 +mem_stall_cycles: 0 +stall_warp: 0 +wspawn: 0 +stalled: 0 +********************************** scheduler ********************************* +valid: 1 +PC: 80000090 +wid: 1 +rd: 2 rs1: -1 rs2: -1 +is_lw: 0 +is_sw: 0 +fetch_stall_cycles: 0 +mem_stall_cycles: 0 +stall_warp: 0 +wspawn: 0 +stalled: 0 +********************************** Decode ********************************* +valid: 1 +PC: 80000090 +wid: 2 +rd: 2 rs1: -1 rs2: -1 +is_lw: 0 +is_sw: 0 +fetch_stall_cycles: 0 +mem_stall_cycles: 0 +stall_warp: 0 +wspawn: 0 +stalled: 0 +DEBUG ../core.cpp:386: Core step stepping warp 3[4] +DEBUG ../core.cpp:683: in step pc=0x80000090 +help: in PC: 80000090 +CUrrent CODE: 6ffff137 +DEBUG ../core.cpp:703: Fetched at 0x80000090 +DEBUG ../core.cpp:704: 0x80000090: lui; +DEBUG ../instruction.cpp:350: Begin instruction execute. +DEBUG ../instruction.cpp:2117: End instruction execute. +DEBUG ../core.cpp:717: Register state: + %r 0: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r 1: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r 2: 6ffff000 6ffff000 6ffff000 6ffff000 00000000 00000000 00000000 00000000 (0) + %r 3: 80001808 80001808 80001808 80001808 00000000 00000000 00000000 00000000 (0) + %r 4: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r 5: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r 6: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r 7: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r 8: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r 9: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r10: 00000004 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r11: 00000000 00000400 00000800 00000c00 00000000 00000000 00000000 00000000 (0) + %r12: 00000000 00000004 00000008 0000000c 00000000 00000000 00000000 00000000 (0) + %r13: 0c000000 0c000000 0c000000 0c000000 00000000 00000000 00000000 00000000 (0) + %r14: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r15: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r16: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r17: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r18: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r19: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r20: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r21: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r22: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r23: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r24: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r25: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r26: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r27: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r28: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r29: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r30: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r31: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) +DEBUG ../core.cpp:726: Thread mask: + 1 1 1 1 0 0 0 0 + + +DEBUG ../core.cpp:388: Now 4 active threads in 3 +********************************** Fetch ********************************* +valid: 1 +PC: 80000090 +wid: 3 +rd: 2 rs1: -1 rs2: -1 +is_lw: 0 +is_sw: 0 +fetch_stall_cycles: 0 +mem_stall_cycles: 0 +stall_warp: 0 +wspawn: 0 +stalled: 0 + + + +------------------------------------------------------ +CYCLE: 69 +Stalled Warps: +0 0 0 0 0 0 0 0 + +********************************** Writeback ********************************* +valid: 0 +PC: 0 +wid: 0 +rd: -1 rs1: -1 rs2: -1 +is_lw: 0 +is_sw: 0 +fetch_stall_cycles: 0 +mem_stall_cycles: 0 +stall_warp: 0 +wspawn: 0 +stalled: 0 +********************************** LSU ********************************* +valid: 0 +PC: 0 +wid: 0 +rd: -1 rs1: -1 rs2: -1 +is_lw: 0 +is_sw: 0 +fetch_stall_cycles: 0 +mem_stall_cycles: 0 +stall_warp: 0 +wspawn: 0 +stalled: 0 +********************************** execute_unit ********************************* +valid: 1 +PC: 80000090 +wid: 1 +rd: 2 rs1: -1 rs2: -1 +is_lw: 0 +is_sw: 0 +fetch_stall_cycles: 0 +mem_stall_cycles: 0 +stall_warp: 0 +wspawn: 0 +stalled: 0 +********************************** scheduler ********************************* +valid: 1 +PC: 80000090 +wid: 2 +rd: 2 rs1: -1 rs2: -1 +is_lw: 0 +is_sw: 0 +fetch_stall_cycles: 0 +mem_stall_cycles: 0 +stall_warp: 0 +wspawn: 0 +stalled: 0 +********************************** Decode ********************************* +valid: 1 +PC: 80000090 +wid: 3 +rd: 2 rs1: -1 rs2: -1 +is_lw: 0 +is_sw: 0 +fetch_stall_cycles: 0 +mem_stall_cycles: 0 +stall_warp: 0 +wspawn: 0 +stalled: 0 +DEBUG ../core.cpp:386: Core step stepping warp 0[4] +DEBUG ../core.cpp:683: in step pc=0x8000008c +help: in PC: 8000008c +CUrrent CODE: 261613 +DEBUG ../core.cpp:703: Fetched at 0x8000008c +DEBUG ../core.cpp:704: 0x8000008c: i_type; +DEBUG ../instruction.cpp:350: Begin instruction execute. +DEBUG ../instruction.cpp:2117: End instruction execute. +DEBUG ../core.cpp:717: Register state: + %r 0: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r 1: 80000014 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r 2: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r 3: 80001808 80001808 80001808 80001808 00000000 00000000 00000000 00000000 (0) + %r 4: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r 5: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r 6: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r 7: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r 8: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r 9: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r10: 00000004 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r11: 00000000 00000400 00000800 00000c00 00000000 00000000 00000000 00000000 (0) + %r12: 00000000 00000004 00000008 0000000c 00000000 00000000 00000000 00000000 (0) + %r13: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r14: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r15: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r16: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r17: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r18: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r19: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r20: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r21: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r22: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r23: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r24: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r25: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r26: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r27: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r28: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r29: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r30: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r31: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) +DEBUG ../core.cpp:726: Thread mask: + 1 1 1 1 0 0 0 0 + + +DEBUG ../core.cpp:388: Now 4 active threads in 0 +********************************** Fetch ********************************* +valid: 1 +PC: 8000008c +wid: 0 +rd: 12 rs1: 12 rs2: -1 +is_lw: 0 +is_sw: 0 +fetch_stall_cycles: 0 +mem_stall_cycles: 0 +stall_warp: 0 +wspawn: 0 +stalled: 0 + + + +------------------------------------------------------ +CYCLE: 70 +Stalled Warps: +0 0 0 0 0 0 0 0 + +********************************** Writeback ********************************* +valid: 1 +PC: 80000090 +wid: 1 +rd: 2 rs1: -1 rs2: -1 +is_lw: 0 +is_sw: 0 +fetch_stall_cycles: 0 +mem_stall_cycles: 0 +stall_warp: 0 +wspawn: 0 +stalled: 0 +********************************** LSU ********************************* +valid: 0 +PC: 0 +wid: 0 +rd: -1 rs1: -1 rs2: -1 +is_lw: 0 +is_sw: 0 +fetch_stall_cycles: 0 +mem_stall_cycles: 0 +stall_warp: 0 +wspawn: 0 +stalled: 0 +********************************** execute_unit ********************************* +valid: 1 +PC: 80000090 +wid: 2 +rd: 2 rs1: -1 rs2: -1 +is_lw: 0 +is_sw: 0 +fetch_stall_cycles: 0 +mem_stall_cycles: 0 +stall_warp: 0 +wspawn: 0 +stalled: 0 +********************************** scheduler ********************************* +valid: 1 +PC: 80000090 +wid: 3 +rd: 2 rs1: -1 rs2: -1 +is_lw: 0 +is_sw: 0 +fetch_stall_cycles: 0 +mem_stall_cycles: 0 +stall_warp: 0 +wspawn: 0 +stalled: 0 +********************************** Decode ********************************* +valid: 1 +PC: 8000008c +wid: 0 +rd: 12 rs1: 12 rs2: -1 +is_lw: 0 +is_sw: 0 +fetch_stall_cycles: 0 +mem_stall_cycles: 0 +stall_warp: 0 +wspawn: 0 +stalled: 0 +DEBUG ../core.cpp:386: Core step stepping warp 1[4] +DEBUG ../core.cpp:683: in step pc=0x80000094 +help: in PC: 80000094 +CUrrent CODE: 40b10133 +DEBUG ../core.cpp:703: Fetched at 0x80000094 +DEBUG ../core.cpp:704: 0x80000094: r_type; +DEBUG ../instruction.cpp:350: Begin instruction execute. +DEBUG ../instruction.cpp:2117: End instruction execute. +DEBUG ../core.cpp:717: Register state: + %r 0: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r 1: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r 2: 6ffff000 6fffec00 6fffe800 6fffe400 00000000 00000000 00000000 00000000 (0) + %r 3: 80001808 80001808 80001808 80001808 00000000 00000000 00000000 00000000 (0) + %r 4: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r 5: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r 6: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r 7: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r 8: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r 9: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r10: 00000004 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r11: 00000000 00000400 00000800 00000c00 00000000 00000000 00000000 00000000 (0) + %r12: 00000000 00000004 00000008 0000000c 00000000 00000000 00000000 00000000 (0) + %r13: 04000000 04000000 04000000 04000000 00000000 00000000 00000000 00000000 (0) + %r14: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r15: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r16: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r17: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r18: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r19: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r20: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r21: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r22: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r23: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r24: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r25: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r26: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r27: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r28: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r29: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r30: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r31: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) +DEBUG ../core.cpp:726: Thread mask: + 1 1 1 1 0 0 0 0 + + +DEBUG ../core.cpp:388: Now 4 active threads in 1 +********************************** Fetch ********************************* +valid: 1 +PC: 80000094 +wid: 1 +rd: 2 rs1: 2 rs2: 11 +is_lw: 0 +is_sw: 0 +fetch_stall_cycles: 0 +mem_stall_cycles: 0 +stall_warp: 0 +wspawn: 0 +stalled: 0 + + + +------------------------------------------------------ +CYCLE: 71 +Stalled Warps: +0 0 0 0 0 0 0 0 + +********************************** Writeback ********************************* +valid: 1 +PC: 80000090 +wid: 2 +rd: 2 rs1: -1 rs2: -1 +is_lw: 0 +is_sw: 0 +fetch_stall_cycles: 0 +mem_stall_cycles: 0 +stall_warp: 0 +wspawn: 0 +stalled: 0 +********************************** LSU ********************************* +valid: 0 +PC: 0 +wid: 0 +rd: -1 rs1: -1 rs2: -1 +is_lw: 0 +is_sw: 0 +fetch_stall_cycles: 0 +mem_stall_cycles: 0 +stall_warp: 0 +wspawn: 0 +stalled: 0 +********************************** execute_unit ********************************* +valid: 1 +PC: 80000090 +wid: 3 +rd: 2 rs1: -1 rs2: -1 +is_lw: 0 +is_sw: 0 +fetch_stall_cycles: 0 +mem_stall_cycles: 0 +stall_warp: 0 +wspawn: 0 +stalled: 0 +********************************** scheduler ********************************* +valid: 1 +PC: 8000008c +wid: 0 +rd: 12 rs1: 12 rs2: -1 +is_lw: 0 +is_sw: 0 +fetch_stall_cycles: 0 +mem_stall_cycles: 0 +stall_warp: 0 +wspawn: 0 +stalled: 0 +********************************** Decode ********************************* +valid: 1 +PC: 80000094 +wid: 1 +rd: 2 rs1: 2 rs2: 11 +is_lw: 0 +is_sw: 0 +fetch_stall_cycles: 0 +mem_stall_cycles: 0 +stall_warp: 0 +wspawn: 0 +stalled: 0 +DEBUG ../core.cpp:386: Core step stepping warp 2[4] +DEBUG ../core.cpp:683: in step pc=0x80000094 +help: in PC: 80000094 +CUrrent CODE: 40b10133 +DEBUG ../core.cpp:703: Fetched at 0x80000094 +DEBUG ../core.cpp:704: 0x80000094: r_type; +DEBUG ../instruction.cpp:350: Begin instruction execute. +DEBUG ../instruction.cpp:2117: End instruction execute. +DEBUG ../core.cpp:717: Register state: + %r 0: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r 1: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r 2: 6ffff000 6fffec00 6fffe800 6fffe400 00000000 00000000 00000000 00000000 (0) + %r 3: 80001808 80001808 80001808 80001808 00000000 00000000 00000000 00000000 (0) + %r 4: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r 5: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r 6: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r 7: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r 8: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r 9: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r10: 00000004 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r11: 00000000 00000400 00000800 00000c00 00000000 00000000 00000000 00000000 (0) + %r12: 00000000 00000004 00000008 0000000c 00000000 00000000 00000000 00000000 (0) + %r13: 08000000 08000000 08000000 08000000 00000000 00000000 00000000 00000000 (0) + %r14: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r15: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r16: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r17: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r18: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r19: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r20: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r21: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r22: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r23: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r24: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r25: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r26: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r27: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r28: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r29: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r30: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r31: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) +DEBUG ../core.cpp:726: Thread mask: + 1 1 1 1 0 0 0 0 + + +DEBUG ../core.cpp:388: Now 4 active threads in 2 +********************************** Fetch ********************************* +valid: 1 +PC: 80000094 +wid: 2 +rd: 2 rs1: 2 rs2: 11 +is_lw: 0 +is_sw: 0 +fetch_stall_cycles: 0 +mem_stall_cycles: 0 +stall_warp: 0 +wspawn: 0 +stalled: 0 + + + +------------------------------------------------------ +CYCLE: 72 +Stalled Warps: +0 0 0 0 0 0 0 0 + +********************************** Writeback ********************************* +valid: 1 +PC: 80000090 +wid: 3 +rd: 2 rs1: -1 rs2: -1 +is_lw: 0 +is_sw: 0 +fetch_stall_cycles: 0 +mem_stall_cycles: 0 +stall_warp: 0 +wspawn: 0 +stalled: 0 +********************************** LSU ********************************* +valid: 0 +PC: 0 +wid: 0 +rd: -1 rs1: -1 rs2: -1 +is_lw: 0 +is_sw: 0 +fetch_stall_cycles: 0 +mem_stall_cycles: 0 +stall_warp: 0 +wspawn: 0 +stalled: 0 +********************************** execute_unit ********************************* +valid: 1 +PC: 8000008c +wid: 0 +rd: 12 rs1: 12 rs2: -1 +is_lw: 0 +is_sw: 0 +fetch_stall_cycles: 0 +mem_stall_cycles: 0 +stall_warp: 0 +wspawn: 0 +stalled: 0 +********************************** scheduler ********************************* +valid: 1 +PC: 80000094 +wid: 1 +rd: 2 rs1: 2 rs2: 11 +is_lw: 0 +is_sw: 0 +fetch_stall_cycles: 0 +mem_stall_cycles: 0 +stall_warp: 0 +wspawn: 0 +stalled: 0 +********************************** Decode ********************************* +valid: 1 +PC: 80000094 +wid: 2 +rd: 2 rs1: 2 rs2: 11 +is_lw: 0 +is_sw: 0 +fetch_stall_cycles: 0 +mem_stall_cycles: 0 +stall_warp: 0 +wspawn: 0 +stalled: 0 +DEBUG ../core.cpp:386: Core step stepping warp 3[4] +DEBUG ../core.cpp:683: in step pc=0x80000094 +help: in PC: 80000094 +CUrrent CODE: 40b10133 +DEBUG ../core.cpp:703: Fetched at 0x80000094 +DEBUG ../core.cpp:704: 0x80000094: r_type; +DEBUG ../instruction.cpp:350: Begin instruction execute. +DEBUG ../instruction.cpp:2117: End instruction execute. +DEBUG ../core.cpp:717: Register state: + %r 0: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r 1: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r 2: 6ffff000 6fffec00 6fffe800 6fffe400 00000000 00000000 00000000 00000000 (0) + %r 3: 80001808 80001808 80001808 80001808 00000000 00000000 00000000 00000000 (0) + %r 4: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r 5: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r 6: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r 7: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r 8: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r 9: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r10: 00000004 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r11: 00000000 00000400 00000800 00000c00 00000000 00000000 00000000 00000000 (0) + %r12: 00000000 00000004 00000008 0000000c 00000000 00000000 00000000 00000000 (0) + %r13: 0c000000 0c000000 0c000000 0c000000 00000000 00000000 00000000 00000000 (0) + %r14: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r15: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r16: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r17: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r18: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r19: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r20: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r21: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r22: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r23: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r24: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r25: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r26: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r27: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r28: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r29: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r30: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r31: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) +DEBUG ../core.cpp:726: Thread mask: + 1 1 1 1 0 0 0 0 + + +DEBUG ../core.cpp:388: Now 4 active threads in 3 +********************************** Fetch ********************************* +valid: 1 +PC: 80000094 +wid: 3 +rd: 2 rs1: 2 rs2: 11 +is_lw: 0 +is_sw: 0 +fetch_stall_cycles: 0 +mem_stall_cycles: 0 +stall_warp: 0 +wspawn: 0 +stalled: 0 + + + +------------------------------------------------------ +CYCLE: 73 +Stalled Warps: +0 0 0 0 0 0 0 0 + +********************************** Writeback ********************************* +valid: 1 +PC: 8000008c +wid: 0 +rd: 12 rs1: 12 rs2: -1 +is_lw: 0 +is_sw: 0 +fetch_stall_cycles: 0 +mem_stall_cycles: 0 +stall_warp: 0 +wspawn: 0 +stalled: 0 +********************************** LSU ********************************* +valid: 0 +PC: 0 +wid: 0 +rd: -1 rs1: -1 rs2: -1 +is_lw: 0 +is_sw: 0 +fetch_stall_cycles: 0 +mem_stall_cycles: 0 +stall_warp: 0 +wspawn: 0 +stalled: 0 +********************************** execute_unit ********************************* +valid: 1 +PC: 80000094 +wid: 1 +rd: 2 rs1: 2 rs2: 11 +is_lw: 0 +is_sw: 0 +fetch_stall_cycles: 0 +mem_stall_cycles: 0 +stall_warp: 0 +wspawn: 0 +stalled: 0 +********************************** scheduler ********************************* +valid: 1 +PC: 80000094 +wid: 2 +rd: 2 rs1: 2 rs2: 11 +is_lw: 0 +is_sw: 0 +fetch_stall_cycles: 0 +mem_stall_cycles: 0 +stall_warp: 0 +wspawn: 0 +stalled: 0 +********************************** Decode ********************************* +valid: 1 +PC: 80000094 +wid: 3 +rd: 2 rs1: 2 rs2: 11 +is_lw: 0 +is_sw: 0 +fetch_stall_cycles: 0 +mem_stall_cycles: 0 +stall_warp: 0 +wspawn: 0 +stalled: 0 +DEBUG ../core.cpp:386: Core step stepping warp 0[4] +DEBUG ../core.cpp:683: in step pc=0x80000090 +help: in PC: 80000090 +CUrrent CODE: 6ffff137 +DEBUG ../core.cpp:703: Fetched at 0x80000090 +DEBUG ../core.cpp:704: 0x80000090: lui; +DEBUG ../instruction.cpp:350: Begin instruction execute. +DEBUG ../instruction.cpp:2117: End instruction execute. +DEBUG ../core.cpp:717: Register state: + %r 0: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r 1: 80000014 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r 2: 6ffff000 6ffff000 6ffff000 6ffff000 00000000 00000000 00000000 00000000 (0) + %r 3: 80001808 80001808 80001808 80001808 00000000 00000000 00000000 00000000 (0) + %r 4: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r 5: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r 6: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r 7: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r 8: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r 9: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r10: 00000004 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r11: 00000000 00000400 00000800 00000c00 00000000 00000000 00000000 00000000 (0) + %r12: 00000000 00000004 00000008 0000000c 00000000 00000000 00000000 00000000 (0) + %r13: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r14: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r15: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r16: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r17: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r18: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r19: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r20: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r21: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r22: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r23: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r24: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r25: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r26: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r27: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r28: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r29: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r30: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r31: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) +DEBUG ../core.cpp:726: Thread mask: + 1 1 1 1 0 0 0 0 + + +DEBUG ../core.cpp:388: Now 4 active threads in 0 +********************************** Fetch ********************************* +valid: 1 +PC: 80000090 +wid: 0 +rd: 2 rs1: -1 rs2: -1 +is_lw: 0 +is_sw: 0 +fetch_stall_cycles: 0 +mem_stall_cycles: 0 +stall_warp: 0 +wspawn: 0 +stalled: 0 + + + +------------------------------------------------------ +CYCLE: 74 +Stalled Warps: +0 0 0 0 0 0 0 0 + +********************************** Writeback ********************************* +valid: 1 +PC: 80000094 +wid: 1 +rd: 2 rs1: 2 rs2: 11 +is_lw: 0 +is_sw: 0 +fetch_stall_cycles: 0 +mem_stall_cycles: 0 +stall_warp: 0 +wspawn: 0 +stalled: 0 +********************************** LSU ********************************* +valid: 0 +PC: 0 +wid: 0 +rd: -1 rs1: -1 rs2: -1 +is_lw: 0 +is_sw: 0 +fetch_stall_cycles: 0 +mem_stall_cycles: 0 +stall_warp: 0 +wspawn: 0 +stalled: 0 +********************************** execute_unit ********************************* +valid: 1 +PC: 80000094 +wid: 2 +rd: 2 rs1: 2 rs2: 11 +is_lw: 0 +is_sw: 0 +fetch_stall_cycles: 0 +mem_stall_cycles: 0 +stall_warp: 0 +wspawn: 0 +stalled: 0 +********************************** scheduler ********************************* +valid: 1 +PC: 80000094 +wid: 3 +rd: 2 rs1: 2 rs2: 11 +is_lw: 0 +is_sw: 0 +fetch_stall_cycles: 0 +mem_stall_cycles: 0 +stall_warp: 0 +wspawn: 0 +stalled: 0 +********************************** Decode ********************************* +valid: 1 +PC: 80000090 +wid: 0 +rd: 2 rs1: -1 rs2: -1 +is_lw: 0 +is_sw: 0 +fetch_stall_cycles: 0 +mem_stall_cycles: 0 +stall_warp: 0 +wspawn: 0 +stalled: 0 +DEBUG ../core.cpp:386: Core step stepping warp 1[4] +DEBUG ../core.cpp:683: in step pc=0x80000098 +help: in PC: 80000098 +CUrrent CODE: 40d10133 +DEBUG ../core.cpp:703: Fetched at 0x80000098 +DEBUG ../core.cpp:704: 0x80000098: r_type; +DEBUG ../instruction.cpp:350: Begin instruction execute. +DEBUG ../instruction.cpp:2117: End instruction execute. +DEBUG ../core.cpp:717: Register state: + %r 0: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r 1: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r 2: 6bfff000 6bffec00 6bffe800 6bffe400 00000000 00000000 00000000 00000000 (0) + %r 3: 80001808 80001808 80001808 80001808 00000000 00000000 00000000 00000000 (0) + %r 4: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r 5: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r 6: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r 7: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r 8: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r 9: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r10: 00000004 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r11: 00000000 00000400 00000800 00000c00 00000000 00000000 00000000 00000000 (0) + %r12: 00000000 00000004 00000008 0000000c 00000000 00000000 00000000 00000000 (0) + %r13: 04000000 04000000 04000000 04000000 00000000 00000000 00000000 00000000 (0) + %r14: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r15: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r16: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r17: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r18: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r19: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r20: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r21: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r22: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r23: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r24: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r25: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r26: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r27: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r28: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r29: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r30: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r31: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) +DEBUG ../core.cpp:726: Thread mask: + 1 1 1 1 0 0 0 0 + + +DEBUG ../core.cpp:388: Now 4 active threads in 1 +********************************** Fetch ********************************* +valid: 1 +PC: 80000098 +wid: 1 +rd: 2 rs1: 2 rs2: 13 +is_lw: 0 +is_sw: 0 +fetch_stall_cycles: 0 +mem_stall_cycles: 0 +stall_warp: 0 +wspawn: 0 +stalled: 0 + + + +------------------------------------------------------ +CYCLE: 75 +Stalled Warps: +0 0 0 0 0 0 0 0 + +********************************** Writeback ********************************* +valid: 1 +PC: 80000094 +wid: 2 +rd: 2 rs1: 2 rs2: 11 +is_lw: 0 +is_sw: 0 +fetch_stall_cycles: 0 +mem_stall_cycles: 0 +stall_warp: 0 +wspawn: 0 +stalled: 0 +********************************** LSU ********************************* +valid: 0 +PC: 0 +wid: 0 +rd: -1 rs1: -1 rs2: -1 +is_lw: 0 +is_sw: 0 +fetch_stall_cycles: 0 +mem_stall_cycles: 0 +stall_warp: 0 +wspawn: 0 +stalled: 0 +********************************** execute_unit ********************************* +valid: 1 +PC: 80000094 +wid: 3 +rd: 2 rs1: 2 rs2: 11 +is_lw: 0 +is_sw: 0 +fetch_stall_cycles: 0 +mem_stall_cycles: 0 +stall_warp: 0 +wspawn: 0 +stalled: 0 +********************************** scheduler ********************************* +valid: 1 +PC: 80000090 +wid: 0 +rd: 2 rs1: -1 rs2: -1 +is_lw: 0 +is_sw: 0 +fetch_stall_cycles: 0 +mem_stall_cycles: 0 +stall_warp: 0 +wspawn: 0 +stalled: 0 +********************************** Decode ********************************* +valid: 1 +PC: 80000098 +wid: 1 +rd: 2 rs1: 2 rs2: 13 +is_lw: 0 +is_sw: 0 +fetch_stall_cycles: 0 +mem_stall_cycles: 0 +stall_warp: 0 +wspawn: 0 +stalled: 0 +DEBUG ../core.cpp:386: Core step stepping warp 2[4] +DEBUG ../core.cpp:683: in step pc=0x80000098 +help: in PC: 80000098 +CUrrent CODE: 40d10133 +DEBUG ../core.cpp:703: Fetched at 0x80000098 +DEBUG ../core.cpp:704: 0x80000098: r_type; +DEBUG ../instruction.cpp:350: Begin instruction execute. +DEBUG ../instruction.cpp:2117: End instruction execute. +DEBUG ../core.cpp:717: Register state: + %r 0: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r 1: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r 2: 67fff000 67ffec00 67ffe800 67ffe400 00000000 00000000 00000000 00000000 (0) + %r 3: 80001808 80001808 80001808 80001808 00000000 00000000 00000000 00000000 (0) + %r 4: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r 5: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r 6: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r 7: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r 8: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r 9: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r10: 00000004 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r11: 00000000 00000400 00000800 00000c00 00000000 00000000 00000000 00000000 (0) + %r12: 00000000 00000004 00000008 0000000c 00000000 00000000 00000000 00000000 (0) + %r13: 08000000 08000000 08000000 08000000 00000000 00000000 00000000 00000000 (0) + %r14: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r15: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r16: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r17: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r18: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r19: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r20: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r21: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r22: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r23: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r24: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r25: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r26: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r27: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r28: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r29: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r30: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r31: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) +DEBUG ../core.cpp:726: Thread mask: + 1 1 1 1 0 0 0 0 + + +DEBUG ../core.cpp:388: Now 4 active threads in 2 +********************************** Fetch ********************************* +valid: 1 +PC: 80000098 +wid: 2 +rd: 2 rs1: 2 rs2: 13 +is_lw: 0 +is_sw: 0 +fetch_stall_cycles: 0 +mem_stall_cycles: 0 +stall_warp: 0 +wspawn: 0 +stalled: 0 + + + +------------------------------------------------------ +CYCLE: 76 +Stalled Warps: +0 0 0 0 0 0 0 0 + +********************************** Writeback ********************************* +valid: 1 +PC: 80000094 +wid: 3 +rd: 2 rs1: 2 rs2: 11 +is_lw: 0 +is_sw: 0 +fetch_stall_cycles: 0 +mem_stall_cycles: 0 +stall_warp: 0 +wspawn: 0 +stalled: 0 +********************************** LSU ********************************* +valid: 0 +PC: 0 +wid: 0 +rd: -1 rs1: -1 rs2: -1 +is_lw: 0 +is_sw: 0 +fetch_stall_cycles: 0 +mem_stall_cycles: 0 +stall_warp: 0 +wspawn: 0 +stalled: 0 +********************************** execute_unit ********************************* +valid: 1 +PC: 80000090 +wid: 0 +rd: 2 rs1: -1 rs2: -1 +is_lw: 0 +is_sw: 0 +fetch_stall_cycles: 0 +mem_stall_cycles: 0 +stall_warp: 0 +wspawn: 0 +stalled: 0 +********************************** scheduler ********************************* +valid: 1 +PC: 80000098 +wid: 1 +rd: 2 rs1: 2 rs2: 13 +is_lw: 0 +is_sw: 0 +fetch_stall_cycles: 0 +mem_stall_cycles: 0 +stall_warp: 0 +wspawn: 0 +stalled: 0 +********************************** Decode ********************************* +valid: 1 +PC: 80000098 +wid: 2 +rd: 2 rs1: 2 rs2: 13 +is_lw: 0 +is_sw: 0 +fetch_stall_cycles: 0 +mem_stall_cycles: 0 +stall_warp: 0 +wspawn: 0 +stalled: 0 +DEBUG ../core.cpp:386: Core step stepping warp 3[4] +DEBUG ../core.cpp:683: in step pc=0x80000098 +help: in PC: 80000098 +CUrrent CODE: 40d10133 +DEBUG ../core.cpp:703: Fetched at 0x80000098 +DEBUG ../core.cpp:704: 0x80000098: r_type; +DEBUG ../instruction.cpp:350: Begin instruction execute. +DEBUG ../instruction.cpp:2117: End instruction execute. +DEBUG ../core.cpp:717: Register state: + %r 0: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r 1: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r 2: 63fff000 63ffec00 63ffe800 63ffe400 00000000 00000000 00000000 00000000 (0) + %r 3: 80001808 80001808 80001808 80001808 00000000 00000000 00000000 00000000 (0) + %r 4: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r 5: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r 6: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r 7: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r 8: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r 9: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r10: 00000004 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r11: 00000000 00000400 00000800 00000c00 00000000 00000000 00000000 00000000 (0) + %r12: 00000000 00000004 00000008 0000000c 00000000 00000000 00000000 00000000 (0) + %r13: 0c000000 0c000000 0c000000 0c000000 00000000 00000000 00000000 00000000 (0) + %r14: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r15: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r16: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r17: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r18: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r19: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r20: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r21: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r22: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r23: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r24: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r25: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r26: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r27: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r28: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r29: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r30: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r31: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) +DEBUG ../core.cpp:726: Thread mask: + 1 1 1 1 0 0 0 0 + + +DEBUG ../core.cpp:388: Now 4 active threads in 3 +********************************** Fetch ********************************* +valid: 1 +PC: 80000098 +wid: 3 +rd: 2 rs1: 2 rs2: 13 +is_lw: 0 +is_sw: 0 +fetch_stall_cycles: 0 +mem_stall_cycles: 0 +stall_warp: 0 +wspawn: 0 +stalled: 0 + + + +------------------------------------------------------ +CYCLE: 77 +Stalled Warps: +0 0 0 0 0 0 0 0 + +********************************** Writeback ********************************* +valid: 1 +PC: 80000090 +wid: 0 +rd: 2 rs1: -1 rs2: -1 +is_lw: 0 +is_sw: 0 +fetch_stall_cycles: 0 +mem_stall_cycles: 0 +stall_warp: 0 +wspawn: 0 +stalled: 0 +********************************** LSU ********************************* +valid: 0 +PC: 0 +wid: 0 +rd: -1 rs1: -1 rs2: -1 +is_lw: 0 +is_sw: 0 +fetch_stall_cycles: 0 +mem_stall_cycles: 0 +stall_warp: 0 +wspawn: 0 +stalled: 0 +********************************** execute_unit ********************************* +valid: 1 +PC: 80000098 +wid: 1 +rd: 2 rs1: 2 rs2: 13 +is_lw: 0 +is_sw: 0 +fetch_stall_cycles: 0 +mem_stall_cycles: 0 +stall_warp: 0 +wspawn: 0 +stalled: 0 +********************************** scheduler ********************************* +valid: 1 +PC: 80000098 +wid: 2 +rd: 2 rs1: 2 rs2: 13 +is_lw: 0 +is_sw: 0 +fetch_stall_cycles: 0 +mem_stall_cycles: 0 +stall_warp: 0 +wspawn: 0 +stalled: 0 +********************************** Decode ********************************* +valid: 1 +PC: 80000098 +wid: 3 +rd: 2 rs1: 2 rs2: 13 +is_lw: 0 +is_sw: 0 +fetch_stall_cycles: 0 +mem_stall_cycles: 0 +stall_warp: 0 +wspawn: 0 +stalled: 0 +DEBUG ../core.cpp:386: Core step stepping warp 0[4] +DEBUG ../core.cpp:683: in step pc=0x80000094 +help: in PC: 80000094 +CUrrent CODE: 40b10133 +DEBUG ../core.cpp:703: Fetched at 0x80000094 +DEBUG ../core.cpp:704: 0x80000094: r_type; +DEBUG ../instruction.cpp:350: Begin instruction execute. +DEBUG ../instruction.cpp:2117: End instruction execute. +DEBUG ../core.cpp:717: Register state: + %r 0: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r 1: 80000014 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r 2: 6ffff000 6fffec00 6fffe800 6fffe400 00000000 00000000 00000000 00000000 (0) + %r 3: 80001808 80001808 80001808 80001808 00000000 00000000 00000000 00000000 (0) + %r 4: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r 5: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r 6: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r 7: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r 8: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r 9: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r10: 00000004 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r11: 00000000 00000400 00000800 00000c00 00000000 00000000 00000000 00000000 (0) + %r12: 00000000 00000004 00000008 0000000c 00000000 00000000 00000000 00000000 (0) + %r13: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r14: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r15: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r16: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r17: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r18: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r19: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r20: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r21: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r22: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r23: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r24: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r25: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r26: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r27: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r28: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r29: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r30: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r31: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) +DEBUG ../core.cpp:726: Thread mask: + 1 1 1 1 0 0 0 0 + + +DEBUG ../core.cpp:388: Now 4 active threads in 0 +********************************** Fetch ********************************* +valid: 1 +PC: 80000094 +wid: 0 +rd: 2 rs1: 2 rs2: 11 +is_lw: 0 +is_sw: 0 +fetch_stall_cycles: 0 +mem_stall_cycles: 0 +stall_warp: 0 +wspawn: 0 +stalled: 0 + + + +------------------------------------------------------ +CYCLE: 78 +Stalled Warps: +0 0 0 0 0 0 0 0 + +********************************** Writeback ********************************* +valid: 1 +PC: 80000098 +wid: 1 +rd: 2 rs1: 2 rs2: 13 +is_lw: 0 +is_sw: 0 +fetch_stall_cycles: 0 +mem_stall_cycles: 0 +stall_warp: 0 +wspawn: 0 +stalled: 0 +********************************** LSU ********************************* +valid: 0 +PC: 0 +wid: 0 +rd: -1 rs1: -1 rs2: -1 +is_lw: 0 +is_sw: 0 +fetch_stall_cycles: 0 +mem_stall_cycles: 0 +stall_warp: 0 +wspawn: 0 +stalled: 0 +********************************** execute_unit ********************************* +valid: 1 +PC: 80000098 +wid: 2 +rd: 2 rs1: 2 rs2: 13 +is_lw: 0 +is_sw: 0 +fetch_stall_cycles: 0 +mem_stall_cycles: 0 +stall_warp: 0 +wspawn: 0 +stalled: 0 +********************************** scheduler ********************************* +valid: 1 +PC: 80000098 +wid: 3 +rd: 2 rs1: 2 rs2: 13 +is_lw: 0 +is_sw: 0 +fetch_stall_cycles: 0 +mem_stall_cycles: 0 +stall_warp: 0 +wspawn: 0 +stalled: 0 +********************************** Decode ********************************* +valid: 1 +PC: 80000094 +wid: 0 +rd: 2 rs1: 2 rs2: 11 +is_lw: 0 +is_sw: 0 +fetch_stall_cycles: 0 +mem_stall_cycles: 0 +stall_warp: 0 +wspawn: 0 +stalled: 0 +DEBUG ../core.cpp:386: Core step stepping warp 1[4] +DEBUG ../core.cpp:683: in step pc=0x8000009c +help: in PC: 8000009c +CUrrent CODE: c10133 +DEBUG ../core.cpp:703: Fetched at 0x8000009c +DEBUG ../core.cpp:704: 0x8000009c: r_type; +DEBUG ../instruction.cpp:350: Begin instruction execute. +DEBUG ../instruction.cpp:2117: End instruction execute. +DEBUG ../core.cpp:717: Register state: + %r 0: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r 1: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r 2: 6bfff000 6bffec04 6bffe808 6bffe40c 00000000 00000000 00000000 00000000 (0) + %r 3: 80001808 80001808 80001808 80001808 00000000 00000000 00000000 00000000 (0) + %r 4: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r 5: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r 6: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r 7: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r 8: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r 9: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r10: 00000004 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r11: 00000000 00000400 00000800 00000c00 00000000 00000000 00000000 00000000 (0) + %r12: 00000000 00000004 00000008 0000000c 00000000 00000000 00000000 00000000 (0) + %r13: 04000000 04000000 04000000 04000000 00000000 00000000 00000000 00000000 (0) + %r14: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r15: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r16: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r17: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r18: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r19: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r20: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r21: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r22: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r23: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r24: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r25: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r26: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r27: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r28: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r29: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r30: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r31: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) +DEBUG ../core.cpp:726: Thread mask: + 1 1 1 1 0 0 0 0 + + +DEBUG ../core.cpp:388: Now 4 active threads in 1 +********************************** Fetch ********************************* +valid: 1 +PC: 8000009c +wid: 1 +rd: 2 rs1: 2 rs2: 12 +is_lw: 0 +is_sw: 0 +fetch_stall_cycles: 0 +mem_stall_cycles: 0 +stall_warp: 0 +wspawn: 0 +stalled: 0 + + + +------------------------------------------------------ +CYCLE: 79 +Stalled Warps: +0 0 0 0 0 0 0 0 + +********************************** Writeback ********************************* +valid: 1 +PC: 80000098 +wid: 2 +rd: 2 rs1: 2 rs2: 13 +is_lw: 0 +is_sw: 0 +fetch_stall_cycles: 0 +mem_stall_cycles: 0 +stall_warp: 0 +wspawn: 0 +stalled: 0 +********************************** LSU ********************************* +valid: 0 +PC: 0 +wid: 0 +rd: -1 rs1: -1 rs2: -1 +is_lw: 0 +is_sw: 0 +fetch_stall_cycles: 0 +mem_stall_cycles: 0 +stall_warp: 0 +wspawn: 0 +stalled: 0 +********************************** execute_unit ********************************* +valid: 1 +PC: 80000098 +wid: 3 +rd: 2 rs1: 2 rs2: 13 +is_lw: 0 +is_sw: 0 +fetch_stall_cycles: 0 +mem_stall_cycles: 0 +stall_warp: 0 +wspawn: 0 +stalled: 0 +********************************** scheduler ********************************* +valid: 1 +PC: 80000094 +wid: 0 +rd: 2 rs1: 2 rs2: 11 +is_lw: 0 +is_sw: 0 +fetch_stall_cycles: 0 +mem_stall_cycles: 0 +stall_warp: 0 +wspawn: 0 +stalled: 0 +********************************** Decode ********************************* +valid: 1 +PC: 8000009c +wid: 1 +rd: 2 rs1: 2 rs2: 12 +is_lw: 0 +is_sw: 0 +fetch_stall_cycles: 0 +mem_stall_cycles: 0 +stall_warp: 0 +wspawn: 0 +stalled: 0 +DEBUG ../core.cpp:386: Core step stepping warp 2[4] +DEBUG ../core.cpp:683: in step pc=0x8000009c +help: in PC: 8000009c +CUrrent CODE: c10133 +DEBUG ../core.cpp:703: Fetched at 0x8000009c +DEBUG ../core.cpp:704: 0x8000009c: r_type; +DEBUG ../instruction.cpp:350: Begin instruction execute. +DEBUG ../instruction.cpp:2117: End instruction execute. +DEBUG ../core.cpp:717: Register state: + %r 0: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r 1: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r 2: 67fff000 67ffec04 67ffe808 67ffe40c 00000000 00000000 00000000 00000000 (0) + %r 3: 80001808 80001808 80001808 80001808 00000000 00000000 00000000 00000000 (0) + %r 4: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r 5: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r 6: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r 7: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r 8: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r 9: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r10: 00000004 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r11: 00000000 00000400 00000800 00000c00 00000000 00000000 00000000 00000000 (0) + %r12: 00000000 00000004 00000008 0000000c 00000000 00000000 00000000 00000000 (0) + %r13: 08000000 08000000 08000000 08000000 00000000 00000000 00000000 00000000 (0) + %r14: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r15: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r16: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r17: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r18: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r19: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r20: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r21: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r22: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r23: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r24: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r25: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r26: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r27: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r28: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r29: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r30: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r31: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) +DEBUG ../core.cpp:726: Thread mask: + 1 1 1 1 0 0 0 0 + + +DEBUG ../core.cpp:388: Now 4 active threads in 2 +********************************** Fetch ********************************* +valid: 1 +PC: 8000009c +wid: 2 +rd: 2 rs1: 2 rs2: 12 +is_lw: 0 +is_sw: 0 +fetch_stall_cycles: 0 +mem_stall_cycles: 0 +stall_warp: 0 +wspawn: 0 +stalled: 0 + + + +------------------------------------------------------ +CYCLE: 80 +Stalled Warps: +0 0 0 0 0 0 0 0 + +********************************** Writeback ********************************* +valid: 1 +PC: 80000098 +wid: 3 +rd: 2 rs1: 2 rs2: 13 +is_lw: 0 +is_sw: 0 +fetch_stall_cycles: 0 +mem_stall_cycles: 0 +stall_warp: 0 +wspawn: 0 +stalled: 0 +********************************** LSU ********************************* +valid: 0 +PC: 0 +wid: 0 +rd: -1 rs1: -1 rs2: -1 +is_lw: 0 +is_sw: 0 +fetch_stall_cycles: 0 +mem_stall_cycles: 0 +stall_warp: 0 +wspawn: 0 +stalled: 0 +********************************** execute_unit ********************************* +valid: 1 +PC: 80000094 +wid: 0 +rd: 2 rs1: 2 rs2: 11 +is_lw: 0 +is_sw: 0 +fetch_stall_cycles: 0 +mem_stall_cycles: 0 +stall_warp: 0 +wspawn: 0 +stalled: 0 +********************************** scheduler ********************************* +valid: 1 +PC: 8000009c +wid: 1 +rd: 2 rs1: 2 rs2: 12 +is_lw: 0 +is_sw: 0 +fetch_stall_cycles: 0 +mem_stall_cycles: 0 +stall_warp: 0 +wspawn: 0 +stalled: 0 +********************************** Decode ********************************* +valid: 1 +PC: 8000009c +wid: 2 +rd: 2 rs1: 2 rs2: 12 +is_lw: 0 +is_sw: 0 +fetch_stall_cycles: 0 +mem_stall_cycles: 0 +stall_warp: 0 +wspawn: 0 +stalled: 0 +DEBUG ../core.cpp:386: Core step stepping warp 3[4] +DEBUG ../core.cpp:683: in step pc=0x8000009c +help: in PC: 8000009c +CUrrent CODE: c10133 +DEBUG ../core.cpp:703: Fetched at 0x8000009c +DEBUG ../core.cpp:704: 0x8000009c: r_type; +DEBUG ../instruction.cpp:350: Begin instruction execute. +DEBUG ../instruction.cpp:2117: End instruction execute. +DEBUG ../core.cpp:717: Register state: + %r 0: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r 1: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r 2: 63fff000 63ffec04 63ffe808 63ffe40c 00000000 00000000 00000000 00000000 (0) + %r 3: 80001808 80001808 80001808 80001808 00000000 00000000 00000000 00000000 (0) + %r 4: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r 5: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r 6: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r 7: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r 8: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r 9: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r10: 00000004 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r11: 00000000 00000400 00000800 00000c00 00000000 00000000 00000000 00000000 (0) + %r12: 00000000 00000004 00000008 0000000c 00000000 00000000 00000000 00000000 (0) + %r13: 0c000000 0c000000 0c000000 0c000000 00000000 00000000 00000000 00000000 (0) + %r14: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r15: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r16: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r17: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r18: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r19: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r20: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r21: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r22: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r23: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r24: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r25: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r26: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r27: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r28: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r29: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r30: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r31: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) +DEBUG ../core.cpp:726: Thread mask: + 1 1 1 1 0 0 0 0 + + +DEBUG ../core.cpp:388: Now 4 active threads in 3 +********************************** Fetch ********************************* +valid: 1 +PC: 8000009c +wid: 3 +rd: 2 rs1: 2 rs2: 12 +is_lw: 0 +is_sw: 0 +fetch_stall_cycles: 0 +mem_stall_cycles: 0 +stall_warp: 0 +wspawn: 0 +stalled: 0 + + + +------------------------------------------------------ +CYCLE: 81 +Stalled Warps: +0 0 0 0 0 0 0 0 + +********************************** Writeback ********************************* +valid: 1 +PC: 80000094 +wid: 0 +rd: 2 rs1: 2 rs2: 11 +is_lw: 0 +is_sw: 0 +fetch_stall_cycles: 0 +mem_stall_cycles: 0 +stall_warp: 0 +wspawn: 0 +stalled: 0 +********************************** LSU ********************************* +valid: 0 +PC: 0 +wid: 0 +rd: -1 rs1: -1 rs2: -1 +is_lw: 0 +is_sw: 0 +fetch_stall_cycles: 0 +mem_stall_cycles: 0 +stall_warp: 0 +wspawn: 0 +stalled: 0 +********************************** execute_unit ********************************* +valid: 1 +PC: 8000009c +wid: 1 +rd: 2 rs1: 2 rs2: 12 +is_lw: 0 +is_sw: 0 +fetch_stall_cycles: 0 +mem_stall_cycles: 0 +stall_warp: 0 +wspawn: 0 +stalled: 0 +********************************** scheduler ********************************* +valid: 1 +PC: 8000009c +wid: 2 +rd: 2 rs1: 2 rs2: 12 +is_lw: 0 +is_sw: 0 +fetch_stall_cycles: 0 +mem_stall_cycles: 0 +stall_warp: 0 +wspawn: 0 +stalled: 0 +********************************** Decode ********************************* +valid: 1 +PC: 8000009c +wid: 3 +rd: 2 rs1: 2 rs2: 12 +is_lw: 0 +is_sw: 0 +fetch_stall_cycles: 0 +mem_stall_cycles: 0 +stall_warp: 0 +wspawn: 0 +stalled: 0 +DEBUG ../core.cpp:386: Core step stepping warp 0[4] +DEBUG ../core.cpp:683: in step pc=0x80000098 +help: in PC: 80000098 +CUrrent CODE: 40d10133 +DEBUG ../core.cpp:703: Fetched at 0x80000098 +DEBUG ../core.cpp:704: 0x80000098: r_type; +DEBUG ../instruction.cpp:350: Begin instruction execute. +DEBUG ../instruction.cpp:2117: End instruction execute. +DEBUG ../core.cpp:717: Register state: + %r 0: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r 1: 80000014 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r 2: 6ffff000 6fffec00 6fffe800 6fffe400 00000000 00000000 00000000 00000000 (0) + %r 3: 80001808 80001808 80001808 80001808 00000000 00000000 00000000 00000000 (0) + %r 4: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r 5: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r 6: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r 7: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r 8: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r 9: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r10: 00000004 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r11: 00000000 00000400 00000800 00000c00 00000000 00000000 00000000 00000000 (0) + %r12: 00000000 00000004 00000008 0000000c 00000000 00000000 00000000 00000000 (0) + %r13: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r14: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r15: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r16: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r17: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r18: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r19: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r20: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r21: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r22: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r23: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r24: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r25: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r26: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r27: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r28: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r29: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r30: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r31: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) +DEBUG ../core.cpp:726: Thread mask: + 1 1 1 1 0 0 0 0 + + +DEBUG ../core.cpp:388: Now 4 active threads in 0 +********************************** Fetch ********************************* +valid: 1 +PC: 80000098 +wid: 0 +rd: 2 rs1: 2 rs2: 13 +is_lw: 0 +is_sw: 0 +fetch_stall_cycles: 0 +mem_stall_cycles: 0 +stall_warp: 0 +wspawn: 0 +stalled: 0 + + + +------------------------------------------------------ +CYCLE: 82 +Stalled Warps: +0 0 0 0 0 0 0 0 + +********************************** Writeback ********************************* +valid: 1 +PC: 8000009c +wid: 1 +rd: 2 rs1: 2 rs2: 12 +is_lw: 0 +is_sw: 0 +fetch_stall_cycles: 0 +mem_stall_cycles: 0 +stall_warp: 0 +wspawn: 0 +stalled: 0 +********************************** LSU ********************************* +valid: 0 +PC: 0 +wid: 0 +rd: -1 rs1: -1 rs2: -1 +is_lw: 0 +is_sw: 0 +fetch_stall_cycles: 0 +mem_stall_cycles: 0 +stall_warp: 0 +wspawn: 0 +stalled: 0 +********************************** execute_unit ********************************* +valid: 1 +PC: 8000009c +wid: 2 +rd: 2 rs1: 2 rs2: 12 +is_lw: 0 +is_sw: 0 +fetch_stall_cycles: 0 +mem_stall_cycles: 0 +stall_warp: 0 +wspawn: 0 +stalled: 0 +********************************** scheduler ********************************* +valid: 1 +PC: 8000009c +wid: 3 +rd: 2 rs1: 2 rs2: 12 +is_lw: 0 +is_sw: 0 +fetch_stall_cycles: 0 +mem_stall_cycles: 0 +stall_warp: 0 +wspawn: 0 +stalled: 0 +********************************** Decode ********************************* +valid: 1 +PC: 80000098 +wid: 0 +rd: 2 rs1: 2 rs2: 13 +is_lw: 0 +is_sw: 0 +fetch_stall_cycles: 0 +mem_stall_cycles: 0 +stall_warp: 0 +wspawn: 0 +stalled: 0 +DEBUG ../core.cpp:386: Core step stepping warp 1[4] +DEBUG ../core.cpp:683: in step pc=0x800000a0 +help: in PC: 800000a0 +CUrrent CODE: 21026f3 +DEBUG ../core.cpp:703: Fetched at 0x800000a0 +DEBUG ../core.cpp:704: 0x800000a0: SYS; +DEBUG ../instruction.cpp:350: Begin instruction execute. +DEBUG ../instruction.cpp:2117: End instruction execute. +DEBUG ../core.cpp:717: Register state: + %r 0: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r 1: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r 2: 6bfff000 6bffec04 6bffe808 6bffe40c 00000000 00000000 00000000 00000000 (0) + %r 3: 80001808 80001808 80001808 80001808 00000000 00000000 00000000 00000000 (0) + %r 4: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r 5: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r 6: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r 7: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r 8: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r 9: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r10: 00000004 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r11: 00000000 00000400 00000800 00000c00 00000000 00000000 00000000 00000000 (0) + %r12: 00000000 00000004 00000008 0000000c 00000000 00000000 00000000 00000000 (0) + %r13: 00000001 00000001 00000001 00000001 00000000 00000000 00000000 00000000 (0) + %r14: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r15: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r16: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r17: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r18: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r19: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r20: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r21: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r22: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r23: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r24: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r25: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r26: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r27: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r28: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r29: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r30: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r31: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) +DEBUG ../core.cpp:726: Thread mask: + 1 1 1 1 0 0 0 0 + + +DEBUG ../core.cpp:388: Now 4 active threads in 1 +********************************** Fetch ********************************* +valid: 1 +PC: 800000a0 +wid: 1 +rd: 13 rs1: 0 rs2: -1 +is_lw: 0 +is_sw: 0 +fetch_stall_cycles: 3 +mem_stall_cycles: 0 +stall_warp: 0 +wspawn: 0 +stalled: 0 + + + +------------------------------------------------------ +CYCLE: 83 +Stalled Warps: +0 0 0 0 0 0 0 0 + +********************************** Writeback ********************************* +valid: 1 +PC: 8000009c +wid: 2 +rd: 2 rs1: 2 rs2: 12 +is_lw: 0 +is_sw: 0 +fetch_stall_cycles: 0 +mem_stall_cycles: 0 +stall_warp: 0 +wspawn: 0 +stalled: 0 +********************************** LSU ********************************* +valid: 0 +PC: 0 +wid: 0 +rd: -1 rs1: -1 rs2: -1 +is_lw: 0 +is_sw: 0 +fetch_stall_cycles: 0 +mem_stall_cycles: 0 +stall_warp: 0 +wspawn: 0 +stalled: 0 +********************************** execute_unit ********************************* +valid: 1 +PC: 8000009c +wid: 3 +rd: 2 rs1: 2 rs2: 12 +is_lw: 0 +is_sw: 0 +fetch_stall_cycles: 0 +mem_stall_cycles: 0 +stall_warp: 0 +wspawn: 0 +stalled: 0 +********************************** scheduler ********************************* +valid: 1 +PC: 80000098 +wid: 0 +rd: 2 rs1: 2 rs2: 13 +is_lw: 0 +is_sw: 0 +fetch_stall_cycles: 0 +mem_stall_cycles: 0 +stall_warp: 0 +wspawn: 0 +stalled: 0 +********************************** Decode ********************************* +valid: 0 +PC: 0 +wid: 2 +rd: -1 rs1: -1 rs2: -1 +is_lw: 0 +is_sw: 0 +fetch_stall_cycles: 0 +mem_stall_cycles: 0 +stall_warp: 0 +wspawn: 0 +stalled: 0 +********************************** Fetch ********************************* +valid: 1 +PC: 800000a0 +wid: 1 +rd: 13 rs1: 0 rs2: -1 +is_lw: 0 +is_sw: 0 +fetch_stall_cycles: 2 +mem_stall_cycles: 0 +stall_warp: 0 +wspawn: 0 +stalled: 0 + + + +------------------------------------------------------ +CYCLE: 84 +Stalled Warps: +0 0 0 0 0 0 0 0 + +********************************** Writeback ********************************* +valid: 1 +PC: 8000009c +wid: 3 +rd: 2 rs1: 2 rs2: 12 +is_lw: 0 +is_sw: 0 +fetch_stall_cycles: 0 +mem_stall_cycles: 0 +stall_warp: 0 +wspawn: 0 +stalled: 0 +********************************** LSU ********************************* +valid: 0 +PC: 0 +wid: 0 +rd: -1 rs1: -1 rs2: -1 +is_lw: 0 +is_sw: 0 +fetch_stall_cycles: 0 +mem_stall_cycles: 0 +stall_warp: 0 +wspawn: 0 +stalled: 0 +********************************** execute_unit ********************************* +valid: 1 +PC: 80000098 +wid: 0 +rd: 2 rs1: 2 rs2: 13 +is_lw: 0 +is_sw: 0 +fetch_stall_cycles: 0 +mem_stall_cycles: 0 +stall_warp: 0 +wspawn: 0 +stalled: 0 +********************************** scheduler ********************************* +valid: 0 +PC: 0 +wid: 2 +rd: -1 rs1: -1 rs2: -1 +is_lw: 0 +is_sw: 0 +fetch_stall_cycles: 0 +mem_stall_cycles: 0 +stall_warp: 0 +wspawn: 0 +stalled: 0 +********************************** Decode ********************************* +valid: 0 +PC: 0 +wid: 2 +rd: -1 rs1: -1 rs2: -1 +is_lw: 0 +is_sw: 0 +fetch_stall_cycles: 0 +mem_stall_cycles: 0 +stall_warp: 0 +wspawn: 0 +stalled: 0 +********************************** Fetch ********************************* +valid: 1 +PC: 800000a0 +wid: 1 +rd: 13 rs1: 0 rs2: -1 +is_lw: 0 +is_sw: 0 +fetch_stall_cycles: 1 +mem_stall_cycles: 0 +stall_warp: 0 +wspawn: 0 +stalled: 0 + + + +------------------------------------------------------ +CYCLE: 85 +Stalled Warps: +0 0 0 0 0 0 0 0 + +********************************** Writeback ********************************* +valid: 1 +PC: 80000098 +wid: 0 +rd: 2 rs1: 2 rs2: 13 +is_lw: 0 +is_sw: 0 +fetch_stall_cycles: 0 +mem_stall_cycles: 0 +stall_warp: 0 +wspawn: 0 +stalled: 0 +********************************** LSU ********************************* +valid: 0 +PC: 0 +wid: 0 +rd: -1 rs1: -1 rs2: -1 +is_lw: 0 +is_sw: 0 +fetch_stall_cycles: 0 +mem_stall_cycles: 0 +stall_warp: 0 +wspawn: 0 +stalled: 0 +********************************** execute_unit ********************************* +valid: 0 +PC: 0 +wid: 2 +rd: -1 rs1: -1 rs2: -1 +is_lw: 0 +is_sw: 0 +fetch_stall_cycles: 0 +mem_stall_cycles: 0 +stall_warp: 0 +wspawn: 0 +stalled: 0 +********************************** scheduler ********************************* +valid: 0 +PC: 0 +wid: 2 +rd: -1 rs1: -1 rs2: -1 +is_lw: 0 +is_sw: 0 +fetch_stall_cycles: 0 +mem_stall_cycles: 0 +stall_warp: 0 +wspawn: 0 +stalled: 0 +********************************** Decode ********************************* +valid: 0 +PC: 0 +wid: 2 +rd: -1 rs1: -1 rs2: -1 +is_lw: 0 +is_sw: 0 +fetch_stall_cycles: 0 +mem_stall_cycles: 0 +stall_warp: 0 +wspawn: 0 +stalled: 0 +********************************** Fetch ********************************* +valid: 1 +PC: 800000a0 +wid: 1 +rd: 13 rs1: 0 rs2: -1 +is_lw: 0 +is_sw: 0 +fetch_stall_cycles: 0 +mem_stall_cycles: 0 +stall_warp: 0 +wspawn: 0 +stalled: 0 + + + +------------------------------------------------------ +CYCLE: 86 +Stalled Warps: +0 0 0 0 0 0 0 0 + +********************************** Writeback ********************************* +valid: 0 +PC: 0 +wid: 2 +rd: -1 rs1: -1 rs2: -1 +is_lw: 0 +is_sw: 0 +fetch_stall_cycles: 0 +mem_stall_cycles: 0 +stall_warp: 0 +wspawn: 0 +stalled: 0 +********************************** LSU ********************************* +valid: 0 +PC: 0 +wid: 0 +rd: -1 rs1: -1 rs2: -1 +is_lw: 0 +is_sw: 0 +fetch_stall_cycles: 0 +mem_stall_cycles: 0 +stall_warp: 0 +wspawn: 0 +stalled: 0 +********************************** execute_unit ********************************* +valid: 0 +PC: 0 +wid: 2 +rd: -1 rs1: -1 rs2: -1 +is_lw: 0 +is_sw: 0 +fetch_stall_cycles: 0 +mem_stall_cycles: 0 +stall_warp: 0 +wspawn: 0 +stalled: 0 +********************************** scheduler ********************************* +valid: 0 +PC: 0 +wid: 2 +rd: -1 rs1: -1 rs2: -1 +is_lw: 0 +is_sw: 0 +fetch_stall_cycles: 0 +mem_stall_cycles: 0 +stall_warp: 0 +wspawn: 0 +stalled: 0 +********************************** Decode ********************************* +valid: 1 +PC: 800000a0 +wid: 1 +rd: 13 rs1: 0 rs2: -1 +is_lw: 0 +is_sw: 0 +fetch_stall_cycles: 0 +mem_stall_cycles: 0 +stall_warp: 0 +wspawn: 0 +stalled: 0 +DEBUG ../core.cpp:386: Core step stepping warp 2[4] +DEBUG ../core.cpp:683: in step pc=0x800000a0 +help: in PC: 800000a0 +CUrrent CODE: 21026f3 +DEBUG ../core.cpp:703: Fetched at 0x800000a0 +DEBUG ../core.cpp:704: 0x800000a0: SYS; +DEBUG ../instruction.cpp:350: Begin instruction execute. +DEBUG ../instruction.cpp:2117: End instruction execute. +DEBUG ../core.cpp:717: Register state: + %r 0: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r 1: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r 2: 67fff000 67ffec04 67ffe808 67ffe40c 00000000 00000000 00000000 00000000 (0) + %r 3: 80001808 80001808 80001808 80001808 00000000 00000000 00000000 00000000 (0) + %r 4: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r 5: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r 6: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r 7: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r 8: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r 9: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r10: 00000004 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r11: 00000000 00000400 00000800 00000c00 00000000 00000000 00000000 00000000 (0) + %r12: 00000000 00000004 00000008 0000000c 00000000 00000000 00000000 00000000 (0) + %r13: 00000002 00000002 00000002 00000002 00000000 00000000 00000000 00000000 (0) + %r14: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r15: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r16: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r17: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r18: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r19: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r20: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r21: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r22: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r23: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r24: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r25: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r26: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r27: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r28: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r29: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r30: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r31: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) +DEBUG ../core.cpp:726: Thread mask: + 1 1 1 1 0 0 0 0 + + +DEBUG ../core.cpp:388: Now 4 active threads in 2 +********************************** Fetch ********************************* +valid: 1 +PC: 800000a0 +wid: 2 +rd: 13 rs1: 0 rs2: -1 +is_lw: 0 +is_sw: 0 +fetch_stall_cycles: 0 +mem_stall_cycles: 0 +stall_warp: 0 +wspawn: 0 +stalled: 0 + + + +------------------------------------------------------ +CYCLE: 87 +Stalled Warps: +0 0 0 0 0 0 0 0 + +********************************** Writeback ********************************* +valid: 0 +PC: 0 +wid: 3 +rd: -1 rs1: -1 rs2: -1 +is_lw: 0 +is_sw: 0 +fetch_stall_cycles: 0 +mem_stall_cycles: 0 +stall_warp: 0 +wspawn: 0 +stalled: 0 +********************************** LSU ********************************* +valid: 0 +PC: 0 +wid: 0 +rd: -1 rs1: -1 rs2: -1 +is_lw: 0 +is_sw: 0 +fetch_stall_cycles: 0 +mem_stall_cycles: 0 +stall_warp: 0 +wspawn: 0 +stalled: 0 +********************************** execute_unit ********************************* +valid: 0 +PC: 0 +wid: 2 +rd: -1 rs1: -1 rs2: -1 +is_lw: 0 +is_sw: 0 +fetch_stall_cycles: 0 +mem_stall_cycles: 0 +stall_warp: 0 +wspawn: 0 +stalled: 0 +********************************** scheduler ********************************* +valid: 1 +PC: 800000a0 +wid: 1 +rd: 13 rs1: 0 rs2: -1 +is_lw: 0 +is_sw: 0 +fetch_stall_cycles: 0 +mem_stall_cycles: 0 +stall_warp: 0 +wspawn: 0 +stalled: 0 +********************************** Decode ********************************* +valid: 1 +PC: 800000a0 +wid: 2 +rd: 13 rs1: 0 rs2: -1 +is_lw: 0 +is_sw: 0 +fetch_stall_cycles: 0 +mem_stall_cycles: 0 +stall_warp: 0 +wspawn: 0 +stalled: 0 +DEBUG ../core.cpp:386: Core step stepping warp 3[4] +DEBUG ../core.cpp:683: in step pc=0x800000a0 +help: in PC: 800000a0 +CUrrent CODE: 21026f3 +DEBUG ../core.cpp:703: Fetched at 0x800000a0 +DEBUG ../core.cpp:704: 0x800000a0: SYS; +DEBUG ../instruction.cpp:350: Begin instruction execute. +DEBUG ../instruction.cpp:2117: End instruction execute. +DEBUG ../core.cpp:717: Register state: + %r 0: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r 1: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r 2: 63fff000 63ffec04 63ffe808 63ffe40c 00000000 00000000 00000000 00000000 (0) + %r 3: 80001808 80001808 80001808 80001808 00000000 00000000 00000000 00000000 (0) + %r 4: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r 5: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r 6: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r 7: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r 8: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r 9: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r10: 00000004 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r11: 00000000 00000400 00000800 00000c00 00000000 00000000 00000000 00000000 (0) + %r12: 00000000 00000004 00000008 0000000c 00000000 00000000 00000000 00000000 (0) + %r13: 00000003 00000003 00000003 00000003 00000000 00000000 00000000 00000000 (0) + %r14: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r15: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r16: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r17: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r18: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r19: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r20: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r21: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r22: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r23: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r24: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r25: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r26: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r27: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r28: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r29: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r30: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r31: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) +DEBUG ../core.cpp:726: Thread mask: + 1 1 1 1 0 0 0 0 + + +DEBUG ../core.cpp:388: Now 4 active threads in 3 +********************************** Fetch ********************************* +valid: 1 +PC: 800000a0 +wid: 3 +rd: 13 rs1: 0 rs2: -1 +is_lw: 0 +is_sw: 0 +fetch_stall_cycles: 0 +mem_stall_cycles: 0 +stall_warp: 0 +wspawn: 0 +stalled: 0 + + + +------------------------------------------------------ +CYCLE: 88 +Stalled Warps: +0 0 0 0 0 0 0 0 + +********************************** Writeback ********************************* +valid: 0 +PC: 0 +wid: 0 +rd: -1 rs1: -1 rs2: -1 +is_lw: 0 +is_sw: 0 +fetch_stall_cycles: 0 +mem_stall_cycles: 0 +stall_warp: 0 +wspawn: 0 +stalled: 0 +********************************** LSU ********************************* +valid: 0 +PC: 0 +wid: 0 +rd: -1 rs1: -1 rs2: -1 +is_lw: 0 +is_sw: 0 +fetch_stall_cycles: 0 +mem_stall_cycles: 0 +stall_warp: 0 +wspawn: 0 +stalled: 0 +********************************** execute_unit ********************************* +valid: 1 +PC: 800000a0 +wid: 1 +rd: 13 rs1: 0 rs2: -1 +is_lw: 0 +is_sw: 0 +fetch_stall_cycles: 0 +mem_stall_cycles: 0 +stall_warp: 0 +wspawn: 0 +stalled: 0 +********************************** scheduler ********************************* +valid: 1 +PC: 800000a0 +wid: 2 +rd: 13 rs1: 0 rs2: -1 +is_lw: 0 +is_sw: 0 +fetch_stall_cycles: 0 +mem_stall_cycles: 0 +stall_warp: 0 +wspawn: 0 +stalled: 0 +********************************** Decode ********************************* +valid: 1 +PC: 800000a0 +wid: 3 +rd: 13 rs1: 0 rs2: -1 +is_lw: 0 +is_sw: 0 +fetch_stall_cycles: 0 +mem_stall_cycles: 0 +stall_warp: 0 +wspawn: 0 +stalled: 0 +DEBUG ../core.cpp:386: Core step stepping warp 0[4] +DEBUG ../core.cpp:683: in step pc=0x8000009c +help: in PC: 8000009c +CUrrent CODE: c10133 +DEBUG ../core.cpp:703: Fetched at 0x8000009c +DEBUG ../core.cpp:704: 0x8000009c: r_type; +DEBUG ../instruction.cpp:350: Begin instruction execute. +DEBUG ../instruction.cpp:2117: End instruction execute. +DEBUG ../core.cpp:717: Register state: + %r 0: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r 1: 80000014 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r 2: 6ffff000 6fffec04 6fffe808 6fffe40c 00000000 00000000 00000000 00000000 (0) + %r 3: 80001808 80001808 80001808 80001808 00000000 00000000 00000000 00000000 (0) + %r 4: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r 5: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r 6: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r 7: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r 8: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r 9: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r10: 00000004 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r11: 00000000 00000400 00000800 00000c00 00000000 00000000 00000000 00000000 (0) + %r12: 00000000 00000004 00000008 0000000c 00000000 00000000 00000000 00000000 (0) + %r13: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r14: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r15: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r16: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r17: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r18: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r19: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r20: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r21: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r22: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r23: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r24: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r25: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r26: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r27: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r28: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r29: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r30: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r31: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) +DEBUG ../core.cpp:726: Thread mask: + 1 1 1 1 0 0 0 0 + + +DEBUG ../core.cpp:388: Now 4 active threads in 0 +********************************** Fetch ********************************* +valid: 1 +PC: 8000009c +wid: 0 +rd: 2 rs1: 2 rs2: 12 +is_lw: 0 +is_sw: 0 +fetch_stall_cycles: 0 +mem_stall_cycles: 0 +stall_warp: 0 +wspawn: 0 +stalled: 0 + + + +------------------------------------------------------ +CYCLE: 89 +Stalled Warps: +0 0 0 0 0 0 0 0 + +********************************** Writeback ********************************* +valid: 1 +PC: 800000a0 +wid: 1 +rd: 13 rs1: 0 rs2: -1 +is_lw: 0 +is_sw: 0 +fetch_stall_cycles: 0 +mem_stall_cycles: 0 +stall_warp: 0 +wspawn: 0 +stalled: 0 +********************************** LSU ********************************* +valid: 0 +PC: 0 +wid: 0 +rd: -1 rs1: -1 rs2: -1 +is_lw: 0 +is_sw: 0 +fetch_stall_cycles: 0 +mem_stall_cycles: 0 +stall_warp: 0 +wspawn: 0 +stalled: 0 +********************************** execute_unit ********************************* +valid: 1 +PC: 800000a0 +wid: 2 +rd: 13 rs1: 0 rs2: -1 +is_lw: 0 +is_sw: 0 +fetch_stall_cycles: 0 +mem_stall_cycles: 0 +stall_warp: 0 +wspawn: 0 +stalled: 0 +********************************** scheduler ********************************* +valid: 1 +PC: 800000a0 +wid: 3 +rd: 13 rs1: 0 rs2: -1 +is_lw: 0 +is_sw: 0 +fetch_stall_cycles: 0 +mem_stall_cycles: 0 +stall_warp: 0 +wspawn: 0 +stalled: 0 +********************************** Decode ********************************* +valid: 1 +PC: 8000009c +wid: 0 +rd: 2 rs1: 2 rs2: 12 +is_lw: 0 +is_sw: 0 +fetch_stall_cycles: 0 +mem_stall_cycles: 0 +stall_warp: 0 +wspawn: 0 +stalled: 0 +DEBUG ../core.cpp:386: Core step stepping warp 1[4] +DEBUG ../core.cpp:683: in step pc=0x800000a4 +help: in PC: 800000a4 +CUrrent CODE: 68663 +DEBUG ../core.cpp:703: Fetched at 0x800000a4 +DEBUG ../core.cpp:704: 0x800000a4: branch; +DEBUG ../instruction.cpp:350: Begin instruction execute. +DEBUG ../instruction.cpp:2117: End instruction execute. +DEBUG ../core.cpp:717: Register state: + %r 0: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r 1: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r 2: 6bfff000 6bffec04 6bffe808 6bffe40c 00000000 00000000 00000000 00000000 (0) + %r 3: 80001808 80001808 80001808 80001808 00000000 00000000 00000000 00000000 (0) + %r 4: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r 5: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r 6: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r 7: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r 8: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r 9: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r10: 00000004 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r11: 00000000 00000400 00000800 00000c00 00000000 00000000 00000000 00000000 (0) + %r12: 00000000 00000004 00000008 0000000c 00000000 00000000 00000000 00000000 (0) + %r13: 00000001 00000001 00000001 00000001 00000000 00000000 00000000 00000000 (0) + %r14: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r15: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r16: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r17: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r18: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r19: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r20: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r21: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r22: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r23: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r24: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r25: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r26: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r27: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r28: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r29: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r30: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r31: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) +DEBUG ../core.cpp:726: Thread mask: + 1 1 1 1 0 0 0 0 + + +DEBUG ../core.cpp:388: Now 4 active threads in 1 +********************************** Fetch ********************************* +valid: 1 +PC: 800000a4 +wid: 1 +rd: -1 rs1: 13 rs2: 0 +is_lw: 0 +is_sw: 0 +fetch_stall_cycles: 0 +mem_stall_cycles: 0 +stall_warp: 1 +wspawn: 0 +stalled: 0 + + + +------------------------------------------------------ +CYCLE: 90 +Stalled Warps: +0 1 0 0 0 0 0 0 + +********************************** Writeback ********************************* +valid: 1 +PC: 800000a0 +wid: 2 +rd: 13 rs1: 0 rs2: -1 +is_lw: 0 +is_sw: 0 +fetch_stall_cycles: 0 +mem_stall_cycles: 0 +stall_warp: 0 +wspawn: 0 +stalled: 0 +********************************** LSU ********************************* +valid: 0 +PC: 0 +wid: 0 +rd: -1 rs1: -1 rs2: -1 +is_lw: 0 +is_sw: 0 +fetch_stall_cycles: 0 +mem_stall_cycles: 0 +stall_warp: 0 +wspawn: 0 +stalled: 0 +********************************** execute_unit ********************************* +valid: 1 +PC: 800000a0 +wid: 3 +rd: 13 rs1: 0 rs2: -1 +is_lw: 0 +is_sw: 0 +fetch_stall_cycles: 0 +mem_stall_cycles: 0 +stall_warp: 0 +wspawn: 0 +stalled: 0 +********************************** scheduler ********************************* +valid: 1 +PC: 8000009c +wid: 0 +rd: 2 rs1: 2 rs2: 12 +is_lw: 0 +is_sw: 0 +fetch_stall_cycles: 0 +mem_stall_cycles: 0 +stall_warp: 0 +wspawn: 0 +stalled: 0 +********************************** Decode ********************************* +valid: 1 +PC: 800000a4 +wid: 1 +rd: -1 rs1: 13 rs2: 0 +is_lw: 0 +is_sw: 0 +fetch_stall_cycles: 0 +mem_stall_cycles: 0 +stall_warp: 1 +wspawn: 0 +stalled: 0 +DEBUG ../core.cpp:386: Core step stepping warp 2[4] +DEBUG ../core.cpp:683: in step pc=0x800000a4 +help: in PC: 800000a4 +CUrrent CODE: 68663 +DEBUG ../core.cpp:703: Fetched at 0x800000a4 +DEBUG ../core.cpp:704: 0x800000a4: branch; +DEBUG ../instruction.cpp:350: Begin instruction execute. +DEBUG ../instruction.cpp:2117: End instruction execute. +DEBUG ../core.cpp:717: Register state: + %r 0: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r 1: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r 2: 67fff000 67ffec04 67ffe808 67ffe40c 00000000 00000000 00000000 00000000 (0) + %r 3: 80001808 80001808 80001808 80001808 00000000 00000000 00000000 00000000 (0) + %r 4: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r 5: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r 6: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r 7: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r 8: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r 9: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r10: 00000004 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r11: 00000000 00000400 00000800 00000c00 00000000 00000000 00000000 00000000 (0) + %r12: 00000000 00000004 00000008 0000000c 00000000 00000000 00000000 00000000 (0) + %r13: 00000002 00000002 00000002 00000002 00000000 00000000 00000000 00000000 (0) + %r14: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r15: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r16: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r17: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r18: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r19: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r20: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r21: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r22: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r23: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r24: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r25: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r26: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r27: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r28: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r29: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r30: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r31: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) +DEBUG ../core.cpp:726: Thread mask: + 1 1 1 1 0 0 0 0 + + +DEBUG ../core.cpp:388: Now 4 active threads in 2 +********************************** Fetch ********************************* +valid: 1 +PC: 800000a4 +wid: 2 +rd: -1 rs1: 13 rs2: 0 +is_lw: 0 +is_sw: 0 +fetch_stall_cycles: 0 +mem_stall_cycles: 0 +stall_warp: 1 +wspawn: 0 +stalled: 0 + + + +------------------------------------------------------ +CYCLE: 91 +Stalled Warps: +0 1 1 0 0 0 0 0 + +********************************** Writeback ********************************* +valid: 1 +PC: 800000a0 +wid: 3 +rd: 13 rs1: 0 rs2: -1 +is_lw: 0 +is_sw: 0 +fetch_stall_cycles: 0 +mem_stall_cycles: 0 +stall_warp: 0 +wspawn: 0 +stalled: 0 +********************************** LSU ********************************* +valid: 0 +PC: 0 +wid: 0 +rd: -1 rs1: -1 rs2: -1 +is_lw: 0 +is_sw: 0 +fetch_stall_cycles: 0 +mem_stall_cycles: 0 +stall_warp: 0 +wspawn: 0 +stalled: 0 +********************************** execute_unit ********************************* +valid: 1 +PC: 8000009c +wid: 0 +rd: 2 rs1: 2 rs2: 12 +is_lw: 0 +is_sw: 0 +fetch_stall_cycles: 0 +mem_stall_cycles: 0 +stall_warp: 0 +wspawn: 0 +stalled: 0 +********************************** scheduler ********************************* +valid: 1 +PC: 800000a4 +wid: 1 +rd: -1 rs1: 13 rs2: 0 +is_lw: 0 +is_sw: 0 +fetch_stall_cycles: 0 +mem_stall_cycles: 0 +stall_warp: 1 +wspawn: 0 +stalled: 0 +********************************** Decode ********************************* +valid: 1 +PC: 800000a4 +wid: 2 +rd: -1 rs1: 13 rs2: 0 +is_lw: 0 +is_sw: 0 +fetch_stall_cycles: 0 +mem_stall_cycles: 0 +stall_warp: 1 +wspawn: 0 +stalled: 0 +DEBUG ../core.cpp:386: Core step stepping warp 3[4] +DEBUG ../core.cpp:683: in step pc=0x800000a4 +help: in PC: 800000a4 +CUrrent CODE: 68663 +DEBUG ../core.cpp:703: Fetched at 0x800000a4 +DEBUG ../core.cpp:704: 0x800000a4: branch; +DEBUG ../instruction.cpp:350: Begin instruction execute. +DEBUG ../instruction.cpp:2117: End instruction execute. +DEBUG ../core.cpp:717: Register state: + %r 0: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r 1: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r 2: 63fff000 63ffec04 63ffe808 63ffe40c 00000000 00000000 00000000 00000000 (0) + %r 3: 80001808 80001808 80001808 80001808 00000000 00000000 00000000 00000000 (0) + %r 4: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r 5: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r 6: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r 7: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r 8: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r 9: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r10: 00000004 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r11: 00000000 00000400 00000800 00000c00 00000000 00000000 00000000 00000000 (0) + %r12: 00000000 00000004 00000008 0000000c 00000000 00000000 00000000 00000000 (0) + %r13: 00000003 00000003 00000003 00000003 00000000 00000000 00000000 00000000 (0) + %r14: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r15: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r16: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r17: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r18: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r19: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r20: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r21: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r22: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r23: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r24: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r25: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r26: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r27: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r28: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r29: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r30: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r31: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) +DEBUG ../core.cpp:726: Thread mask: + 1 1 1 1 0 0 0 0 + + +DEBUG ../core.cpp:388: Now 4 active threads in 3 +********************************** Fetch ********************************* +valid: 1 +PC: 800000a4 +wid: 3 +rd: -1 rs1: 13 rs2: 0 +is_lw: 0 +is_sw: 0 +fetch_stall_cycles: 0 +mem_stall_cycles: 0 +stall_warp: 1 +wspawn: 0 +stalled: 0 + + + +------------------------------------------------------ +CYCLE: 92 +Stalled Warps: +0 1 1 1 0 0 0 0 + +********************************** Writeback ********************************* +valid: 1 +PC: 8000009c +wid: 0 +rd: 2 rs1: 2 rs2: 12 +is_lw: 0 +is_sw: 0 +fetch_stall_cycles: 0 +mem_stall_cycles: 0 +stall_warp: 0 +wspawn: 0 +stalled: 0 +********************************** LSU ********************************* +valid: 0 +PC: 0 +wid: 0 +rd: -1 rs1: -1 rs2: -1 +is_lw: 0 +is_sw: 0 +fetch_stall_cycles: 0 +mem_stall_cycles: 0 +stall_warp: 0 +wspawn: 0 +stalled: 0 +********************************** execute_unit ********************************* +valid: 1 +PC: 800000a4 +wid: 1 +rd: -1 rs1: 13 rs2: 0 +is_lw: 0 +is_sw: 0 +fetch_stall_cycles: 0 +mem_stall_cycles: 0 +stall_warp: 1 +wspawn: 0 +stalled: 0 +********************************** scheduler ********************************* +valid: 1 +PC: 800000a4 +wid: 2 +rd: -1 rs1: 13 rs2: 0 +is_lw: 0 +is_sw: 0 +fetch_stall_cycles: 0 +mem_stall_cycles: 0 +stall_warp: 1 +wspawn: 0 +stalled: 0 +********************************** Decode ********************************* +valid: 1 +PC: 800000a4 +wid: 3 +rd: -1 rs1: 13 rs2: 0 +is_lw: 0 +is_sw: 0 +fetch_stall_cycles: 0 +mem_stall_cycles: 0 +stall_warp: 1 +wspawn: 0 +stalled: 0 +DEBUG ../core.cpp:386: Core step stepping warp 0[4] +DEBUG ../core.cpp:683: in step pc=0x800000a0 +help: in PC: 800000a0 +CUrrent CODE: 21026f3 +DEBUG ../core.cpp:703: Fetched at 0x800000a0 +DEBUG ../core.cpp:704: 0x800000a0: SYS; +DEBUG ../instruction.cpp:350: Begin instruction execute. +DEBUG ../instruction.cpp:2117: End instruction execute. +DEBUG ../core.cpp:717: Register state: + %r 0: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r 1: 80000014 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r 2: 6ffff000 6fffec04 6fffe808 6fffe40c 00000000 00000000 00000000 00000000 (0) + %r 3: 80001808 80001808 80001808 80001808 00000000 00000000 00000000 00000000 (0) + %r 4: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r 5: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r 6: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r 7: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r 8: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r 9: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r10: 00000004 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r11: 00000000 00000400 00000800 00000c00 00000000 00000000 00000000 00000000 (0) + %r12: 00000000 00000004 00000008 0000000c 00000000 00000000 00000000 00000000 (0) + %r13: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r14: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r15: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r16: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r17: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r18: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r19: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r20: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r21: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r22: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r23: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r24: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r25: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r26: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r27: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r28: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r29: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r30: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r31: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) +DEBUG ../core.cpp:726: Thread mask: + 1 1 1 1 0 0 0 0 + + +DEBUG ../core.cpp:388: Now 4 active threads in 0 +********************************** Fetch ********************************* +valid: 1 +PC: 800000a0 +wid: 0 +rd: 13 rs1: 0 rs2: -1 +is_lw: 0 +is_sw: 0 +fetch_stall_cycles: 0 +mem_stall_cycles: 0 +stall_warp: 0 +wspawn: 0 +stalled: 0 + + + +------------------------------------------------------ +CYCLE: 93 +Stalled Warps: +0 1 1 1 0 0 0 0 + +********************************** Writeback ********************************* +valid: 1 +PC: 800000a4 +wid: 1 +rd: -1 rs1: 13 rs2: 0 +is_lw: 0 +is_sw: 0 +fetch_stall_cycles: 0 +mem_stall_cycles: 0 +stall_warp: 1 +wspawn: 0 +stalled: 0 +********************************** LSU ********************************* +valid: 0 +PC: 0 +wid: 0 +rd: -1 rs1: -1 rs2: -1 +is_lw: 0 +is_sw: 0 +fetch_stall_cycles: 0 +mem_stall_cycles: 0 +stall_warp: 0 +wspawn: 0 +stalled: 0 +********************************** execute_unit ********************************* +valid: 1 +PC: 800000a4 +wid: 2 +rd: -1 rs1: 13 rs2: 0 +is_lw: 0 +is_sw: 0 +fetch_stall_cycles: 0 +mem_stall_cycles: 0 +stall_warp: 1 +wspawn: 0 +stalled: 0 +********************************** scheduler ********************************* +valid: 1 +PC: 800000a4 +wid: 3 +rd: -1 rs1: 13 rs2: 0 +is_lw: 0 +is_sw: 0 +fetch_stall_cycles: 0 +mem_stall_cycles: 0 +stall_warp: 1 +wspawn: 0 +stalled: 0 +********************************** Decode ********************************* +valid: 1 +PC: 800000a0 +wid: 0 +rd: 13 rs1: 0 rs2: -1 +is_lw: 0 +is_sw: 0 +fetch_stall_cycles: 0 +mem_stall_cycles: 0 +stall_warp: 0 +wspawn: 0 +stalled: 0 +DEBUG ../core.cpp:386: Core step stepping warp 0[4] +DEBUG ../core.cpp:683: in step pc=0x800000a4 +help: in PC: 800000a4 +CUrrent CODE: 68663 +DEBUG ../core.cpp:703: Fetched at 0x800000a4 +DEBUG ../core.cpp:704: 0x800000a4: branch; +DEBUG ../instruction.cpp:350: Begin instruction execute. +DEBUG ../instruction.cpp:2117: End instruction execute. +Next PC: 800000b0 +DEBUG ../core.cpp:717: Register state: + %r 0: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r 1: 80000014 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r 2: 6ffff000 6fffec04 6fffe808 6fffe40c 00000000 00000000 00000000 00000000 (0) + %r 3: 80001808 80001808 80001808 80001808 00000000 00000000 00000000 00000000 (0) + %r 4: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r 5: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r 6: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r 7: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r 8: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r 9: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r10: 00000004 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r11: 00000000 00000400 00000800 00000c00 00000000 00000000 00000000 00000000 (0) + %r12: 00000000 00000004 00000008 0000000c 00000000 00000000 00000000 00000000 (0) + %r13: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r14: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r15: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r16: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r17: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r18: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r19: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r20: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r21: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r22: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r23: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r24: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r25: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r26: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r27: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r28: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r29: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r30: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r31: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) +DEBUG ../core.cpp:726: Thread mask: + 1 1 1 1 0 0 0 0 + + +DEBUG ../core.cpp:388: Now 4 active threads in 0 +********************************** Fetch ********************************* +valid: 1 +PC: 800000a4 +wid: 0 +rd: -1 rs1: 13 rs2: 0 +is_lw: 0 +is_sw: 0 +fetch_stall_cycles: 0 +mem_stall_cycles: 0 +stall_warp: 1 +wspawn: 0 +stalled: 0 + + + +------------------------------------------------------ +CYCLE: 94 +Stalled Warps: +1 1 1 1 0 0 0 0 + +********************************** Writeback ********************************* +valid: 1 +PC: 800000a4 +wid: 2 +rd: -1 rs1: 13 rs2: 0 +is_lw: 0 +is_sw: 0 +fetch_stall_cycles: 0 +mem_stall_cycles: 0 +stall_warp: 1 +wspawn: 0 +stalled: 0 +********************************** LSU ********************************* +valid: 0 +PC: 0 +wid: 0 +rd: -1 rs1: -1 rs2: -1 +is_lw: 0 +is_sw: 0 +fetch_stall_cycles: 0 +mem_stall_cycles: 0 +stall_warp: 0 +wspawn: 0 +stalled: 0 +********************************** execute_unit ********************************* +valid: 1 +PC: 800000a4 +wid: 3 +rd: -1 rs1: 13 rs2: 0 +is_lw: 0 +is_sw: 0 +fetch_stall_cycles: 0 +mem_stall_cycles: 0 +stall_warp: 1 +wspawn: 0 +stalled: 0 +********************************** scheduler ********************************* +valid: 1 +PC: 800000a0 +wid: 0 +rd: 13 rs1: 0 rs2: -1 +is_lw: 0 +is_sw: 0 +fetch_stall_cycles: 0 +mem_stall_cycles: 0 +stall_warp: 0 +wspawn: 0 +stalled: 0 +********************************** Decode ********************************* +valid: 1 +PC: 800000a4 +wid: 0 +rd: -1 rs1: 13 rs2: 0 +is_lw: 0 +is_sw: 0 +fetch_stall_cycles: 0 +mem_stall_cycles: 0 +stall_warp: 1 +wspawn: 0 +stalled: 0 +********************************** Fetch ********************************* +valid: 0 +PC: 0 +wid: 1 +rd: -1 rs1: -1 rs2: -1 +is_lw: 0 +is_sw: 0 +fetch_stall_cycles: 0 +mem_stall_cycles: 0 +stall_warp: 0 +wspawn: 0 +stalled: 0 + + + +------------------------------------------------------ +CYCLE: 95 +Stalled Warps: +1 0 1 1 0 0 0 0 + +********************************** Writeback ********************************* +valid: 1 +PC: 800000a4 +wid: 3 +rd: -1 rs1: 13 rs2: 0 +is_lw: 0 +is_sw: 0 +fetch_stall_cycles: 0 +mem_stall_cycles: 0 +stall_warp: 1 +wspawn: 0 +stalled: 0 +********************************** LSU ********************************* +valid: 0 +PC: 0 +wid: 0 +rd: -1 rs1: -1 rs2: -1 +is_lw: 0 +is_sw: 0 +fetch_stall_cycles: 0 +mem_stall_cycles: 0 +stall_warp: 0 +wspawn: 0 +stalled: 0 +********************************** execute_unit ********************************* +valid: 1 +PC: 800000a0 +wid: 0 +rd: 13 rs1: 0 rs2: -1 +is_lw: 0 +is_sw: 0 +fetch_stall_cycles: 0 +mem_stall_cycles: 0 +stall_warp: 0 +wspawn: 0 +stalled: 0 +********************************** scheduler ********************************* +valid: 1 +PC: 800000a4 +wid: 0 +rd: -1 rs1: 13 rs2: 0 +is_lw: 0 +is_sw: 0 +fetch_stall_cycles: 0 +mem_stall_cycles: 0 +stall_warp: 1 +wspawn: 0 +stalled: 0 +********************************** Decode ********************************* +valid: 0 +PC: 0 +wid: 1 +rd: -1 rs1: -1 rs2: -1 +is_lw: 0 +is_sw: 0 +fetch_stall_cycles: 0 +mem_stall_cycles: 0 +stall_warp: 0 +wspawn: 0 +stalled: 0 +DEBUG ../core.cpp:386: Core step stepping warp 1[4] +DEBUG ../core.cpp:683: in step pc=0x800000a8 +help: in PC: 800000a8 +CUrrent CODE: 513 +DEBUG ../core.cpp:703: Fetched at 0x800000a8 +DEBUG ../core.cpp:704: 0x800000a8: i_type; +DEBUG ../instruction.cpp:350: Begin instruction execute. +DEBUG ../instruction.cpp:2117: End instruction execute. +DEBUG ../core.cpp:717: Register state: + %r 0: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r 1: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r 2: 6bfff000 6bffec04 6bffe808 6bffe40c 00000000 00000000 00000000 00000000 (0) + %r 3: 80001808 80001808 80001808 80001808 00000000 00000000 00000000 00000000 (0) + %r 4: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r 5: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r 6: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r 7: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r 8: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r 9: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r10: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r11: 00000000 00000400 00000800 00000c00 00000000 00000000 00000000 00000000 (0) + %r12: 00000000 00000004 00000008 0000000c 00000000 00000000 00000000 00000000 (0) + %r13: 00000001 00000001 00000001 00000001 00000000 00000000 00000000 00000000 (0) + %r14: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r15: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r16: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r17: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r18: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r19: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r20: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r21: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r22: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r23: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r24: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r25: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r26: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r27: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r28: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r29: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r30: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r31: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) +DEBUG ../core.cpp:726: Thread mask: + 1 1 1 1 0 0 0 0 + + +DEBUG ../core.cpp:388: Now 4 active threads in 1 +********************************** Fetch ********************************* +valid: 1 +PC: 800000a8 +wid: 1 +rd: 10 rs1: 0 rs2: -1 +is_lw: 0 +is_sw: 0 +fetch_stall_cycles: 0 +mem_stall_cycles: 0 +stall_warp: 0 +wspawn: 0 +stalled: 0 + + + +------------------------------------------------------ +CYCLE: 96 +Stalled Warps: +1 0 0 1 0 0 0 0 + +********************************** Writeback ********************************* +valid: 1 +PC: 800000a0 +wid: 0 +rd: 13 rs1: 0 rs2: -1 +is_lw: 0 +is_sw: 0 +fetch_stall_cycles: 0 +mem_stall_cycles: 0 +stall_warp: 0 +wspawn: 0 +stalled: 0 +********************************** LSU ********************************* +valid: 0 +PC: 0 +wid: 0 +rd: -1 rs1: -1 rs2: -1 +is_lw: 0 +is_sw: 0 +fetch_stall_cycles: 0 +mem_stall_cycles: 0 +stall_warp: 0 +wspawn: 0 +stalled: 0 +&&&&&&&&&&&&&&&&&&&&&&&& EXECUTE SRCS NOT READY +********************************** execute_unit ********************************* +valid: 0 +PC: 0 +wid: 2 +rd: -1 rs1: -1 rs2: -1 +is_lw: 0 +is_sw: 0 +fetch_stall_cycles: 0 +mem_stall_cycles: 0 +stall_warp: 0 +wspawn: 0 +stalled: 0 +********************************** scheduler ********************************* +valid: 1 +PC: 800000a4 +wid: 0 +rd: -1 rs1: 13 rs2: 0 +is_lw: 0 +is_sw: 0 +fetch_stall_cycles: 0 +mem_stall_cycles: 0 +stall_warp: 1 +wspawn: 0 +stalled: 1 +********************************** Decode ********************************* +valid: 0 +PC: 0 +wid: 1 +rd: -1 rs1: -1 rs2: -1 +is_lw: 0 +is_sw: 0 +fetch_stall_cycles: 0 +mem_stall_cycles: 0 +stall_warp: 0 +wspawn: 0 +stalled: 0 +********************************** Fetch ********************************* +valid: 1 +PC: 800000a8 +wid: 1 +rd: 10 rs1: 0 rs2: -1 +is_lw: 0 +is_sw: 0 +fetch_stall_cycles: 0 +mem_stall_cycles: 0 +stall_warp: 0 +wspawn: 0 +stalled: 0 + + + +------------------------------------------------------ +CYCLE: 97 +Stalled Warps: +1 0 0 0 0 0 0 0 + +********************************** Writeback ********************************* +valid: 0 +PC: 0 +wid: 2 +rd: -1 rs1: -1 rs2: -1 +is_lw: 0 +is_sw: 0 +fetch_stall_cycles: 0 +mem_stall_cycles: 0 +stall_warp: 0 +wspawn: 0 +stalled: 0 +********************************** LSU ********************************* +valid: 0 +PC: 0 +wid: 0 +rd: -1 rs1: -1 rs2: -1 +is_lw: 0 +is_sw: 0 +fetch_stall_cycles: 0 +mem_stall_cycles: 0 +stall_warp: 0 +wspawn: 0 +stalled: 0 +********************************** execute_unit ********************************* +valid: 1 +PC: 800000a4 +wid: 0 +rd: -1 rs1: 13 rs2: 0 +is_lw: 0 +is_sw: 0 +fetch_stall_cycles: 0 +mem_stall_cycles: 0 +stall_warp: 1 +wspawn: 0 +stalled: 0 +********************************** scheduler ********************************* +valid: 0 +PC: 0 +wid: 1 +rd: -1 rs1: -1 rs2: -1 +is_lw: 0 +is_sw: 0 +fetch_stall_cycles: 0 +mem_stall_cycles: 0 +stall_warp: 0 +wspawn: 0 +stalled: 0 +********************************** Decode ********************************* +valid: 1 +PC: 800000a8 +wid: 1 +rd: 10 rs1: 0 rs2: -1 +is_lw: 0 +is_sw: 0 +fetch_stall_cycles: 0 +mem_stall_cycles: 0 +stall_warp: 0 +wspawn: 0 +stalled: 0 +DEBUG ../core.cpp:386: Core step stepping warp 2[4] +DEBUG ../core.cpp:683: in step pc=0x800000a8 +help: in PC: 800000a8 +CUrrent CODE: 513 +DEBUG ../core.cpp:703: Fetched at 0x800000a8 +DEBUG ../core.cpp:704: 0x800000a8: i_type; +DEBUG ../instruction.cpp:350: Begin instruction execute. +DEBUG ../instruction.cpp:2117: End instruction execute. +DEBUG ../core.cpp:717: Register state: + %r 0: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r 1: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r 2: 67fff000 67ffec04 67ffe808 67ffe40c 00000000 00000000 00000000 00000000 (0) + %r 3: 80001808 80001808 80001808 80001808 00000000 00000000 00000000 00000000 (0) + %r 4: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r 5: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r 6: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r 7: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r 8: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r 9: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r10: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r11: 00000000 00000400 00000800 00000c00 00000000 00000000 00000000 00000000 (0) + %r12: 00000000 00000004 00000008 0000000c 00000000 00000000 00000000 00000000 (0) + %r13: 00000002 00000002 00000002 00000002 00000000 00000000 00000000 00000000 (0) + %r14: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r15: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r16: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r17: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r18: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r19: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r20: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r21: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r22: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r23: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r24: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r25: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r26: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r27: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r28: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r29: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r30: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r31: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) +DEBUG ../core.cpp:726: Thread mask: + 1 1 1 1 0 0 0 0 + + +DEBUG ../core.cpp:388: Now 4 active threads in 2 +********************************** Fetch ********************************* +valid: 1 +PC: 800000a8 +wid: 2 +rd: 10 rs1: 0 rs2: -1 +is_lw: 0 +is_sw: 0 +fetch_stall_cycles: 0 +mem_stall_cycles: 0 +stall_warp: 0 +wspawn: 0 +stalled: 0 + + + +------------------------------------------------------ +CYCLE: 98 +Stalled Warps: +1 0 0 0 0 0 0 0 + +********************************** Writeback ********************************* +valid: 1 +PC: 800000a4 +wid: 0 +rd: -1 rs1: 13 rs2: 0 +is_lw: 0 +is_sw: 0 +fetch_stall_cycles: 0 +mem_stall_cycles: 0 +stall_warp: 1 +wspawn: 0 +stalled: 0 +********************************** LSU ********************************* +valid: 0 +PC: 0 +wid: 0 +rd: -1 rs1: -1 rs2: -1 +is_lw: 0 +is_sw: 0 +fetch_stall_cycles: 0 +mem_stall_cycles: 0 +stall_warp: 0 +wspawn: 0 +stalled: 0 +********************************** execute_unit ********************************* +valid: 0 +PC: 0 +wid: 1 +rd: -1 rs1: -1 rs2: -1 +is_lw: 0 +is_sw: 0 +fetch_stall_cycles: 0 +mem_stall_cycles: 0 +stall_warp: 0 +wspawn: 0 +stalled: 0 +********************************** scheduler ********************************* +valid: 1 +PC: 800000a8 +wid: 1 +rd: 10 rs1: 0 rs2: -1 +is_lw: 0 +is_sw: 0 +fetch_stall_cycles: 0 +mem_stall_cycles: 0 +stall_warp: 0 +wspawn: 0 +stalled: 0 +********************************** Decode ********************************* +valid: 1 +PC: 800000a8 +wid: 2 +rd: 10 rs1: 0 rs2: -1 +is_lw: 0 +is_sw: 0 +fetch_stall_cycles: 0 +mem_stall_cycles: 0 +stall_warp: 0 +wspawn: 0 +stalled: 0 +DEBUG ../core.cpp:386: Core step stepping warp 3[4] +DEBUG ../core.cpp:683: in step pc=0x800000a8 +help: in PC: 800000a8 +CUrrent CODE: 513 +DEBUG ../core.cpp:703: Fetched at 0x800000a8 +DEBUG ../core.cpp:704: 0x800000a8: i_type; +DEBUG ../instruction.cpp:350: Begin instruction execute. +DEBUG ../instruction.cpp:2117: End instruction execute. +DEBUG ../core.cpp:717: Register state: + %r 0: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r 1: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r 2: 63fff000 63ffec04 63ffe808 63ffe40c 00000000 00000000 00000000 00000000 (0) + %r 3: 80001808 80001808 80001808 80001808 00000000 00000000 00000000 00000000 (0) + %r 4: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r 5: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r 6: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r 7: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r 8: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r 9: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r10: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r11: 00000000 00000400 00000800 00000c00 00000000 00000000 00000000 00000000 (0) + %r12: 00000000 00000004 00000008 0000000c 00000000 00000000 00000000 00000000 (0) + %r13: 00000003 00000003 00000003 00000003 00000000 00000000 00000000 00000000 (0) + %r14: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r15: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r16: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r17: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r18: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r19: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r20: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r21: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r22: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r23: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r24: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r25: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r26: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r27: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r28: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r29: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r30: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r31: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) +DEBUG ../core.cpp:726: Thread mask: + 1 1 1 1 0 0 0 0 + + +DEBUG ../core.cpp:388: Now 4 active threads in 3 +********************************** Fetch ********************************* +valid: 1 +PC: 800000a8 +wid: 3 +rd: 10 rs1: 0 rs2: -1 +is_lw: 0 +is_sw: 0 +fetch_stall_cycles: 0 +mem_stall_cycles: 0 +stall_warp: 0 +wspawn: 0 +stalled: 0 + + + +------------------------------------------------------ +CYCLE: 99 +Stalled Warps: +1 0 0 0 0 0 0 0 + +********************************** Writeback ********************************* +valid: 0 +PC: 0 +wid: 1 +rd: -1 rs1: -1 rs2: -1 +is_lw: 0 +is_sw: 0 +fetch_stall_cycles: 0 +mem_stall_cycles: 0 +stall_warp: 0 +wspawn: 0 +stalled: 0 +********************************** LSU ********************************* +valid: 0 +PC: 0 +wid: 0 +rd: -1 rs1: -1 rs2: -1 +is_lw: 0 +is_sw: 0 +fetch_stall_cycles: 0 +mem_stall_cycles: 0 +stall_warp: 0 +wspawn: 0 +stalled: 0 +********************************** execute_unit ********************************* +valid: 1 +PC: 800000a8 +wid: 1 +rd: 10 rs1: 0 rs2: -1 +is_lw: 0 +is_sw: 0 +fetch_stall_cycles: 0 +mem_stall_cycles: 0 +stall_warp: 0 +wspawn: 0 +stalled: 0 +********************************** scheduler ********************************* +valid: 1 +PC: 800000a8 +wid: 2 +rd: 10 rs1: 0 rs2: -1 +is_lw: 0 +is_sw: 0 +fetch_stall_cycles: 0 +mem_stall_cycles: 0 +stall_warp: 0 +wspawn: 0 +stalled: 0 +********************************** Decode ********************************* +valid: 1 +PC: 800000a8 +wid: 3 +rd: 10 rs1: 0 rs2: -1 +is_lw: 0 +is_sw: 0 +fetch_stall_cycles: 0 +mem_stall_cycles: 0 +stall_warp: 0 +wspawn: 0 +stalled: 0 +DEBUG ../core.cpp:386: Core step stepping warp 1[4] +DEBUG ../core.cpp:683: in step pc=0x800000ac +help: in PC: 800000ac +CUrrent CODE: 5006b +DEBUG ../core.cpp:703: Fetched at 0x800000ac +DEBUG ../core.cpp:704: 0x800000ac: gpgpu; +DEBUG ../instruction.cpp:350: Begin instruction execute. +DEBUG ../instruction.cpp:2117: End instruction execute. +DEBUG ../core.cpp:717: Register state: + %r 0: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r 1: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r 2: 6bfff000 6bffec04 6bffe808 6bffe40c 00000000 00000000 00000000 00000000 (0) + %r 3: 80001808 80001808 80001808 80001808 00000000 00000000 00000000 00000000 (0) + %r 4: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r 5: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r 6: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r 7: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r 8: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r 9: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r10: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r11: 00000000 00000400 00000800 00000c00 00000000 00000000 00000000 00000000 (0) + %r12: 00000000 00000004 00000008 0000000c 00000000 00000000 00000000 00000000 (0) + %r13: 00000001 00000001 00000001 00000001 00000000 00000000 00000000 00000000 (0) + %r14: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r15: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r16: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r17: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r18: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r19: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r20: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r21: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r22: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r23: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r24: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r25: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r26: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r27: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r28: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r29: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r30: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r31: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) +DEBUG ../core.cpp:726: Thread mask: + 0 0 0 0 0 0 0 0 + + +DEBUG ../core.cpp:388: Now 0 active threads in 1 +********************************** Fetch ********************************* +valid: 1 +PC: 800000ac +wid: 1 +rd: 0 rs1: 10 rs2: 0 +is_lw: 0 +is_sw: 0 +fetch_stall_cycles: 0 +mem_stall_cycles: 0 +stall_warp: 1 +wspawn: 0 +stalled: 0 + + + +------------------------------------------------------ +CYCLE: 100 +Stalled Warps: +0 1 0 0 0 0 0 0 + +********************************** Writeback ********************************* +valid: 1 +PC: 800000a8 +wid: 1 +rd: 10 rs1: 0 rs2: -1 +is_lw: 0 +is_sw: 0 +fetch_stall_cycles: 0 +mem_stall_cycles: 0 +stall_warp: 0 +wspawn: 0 +stalled: 0 +********************************** LSU ********************************* +valid: 0 +PC: 0 +wid: 0 +rd: -1 rs1: -1 rs2: -1 +is_lw: 0 +is_sw: 0 +fetch_stall_cycles: 0 +mem_stall_cycles: 0 +stall_warp: 0 +wspawn: 0 +stalled: 0 +********************************** execute_unit ********************************* +valid: 1 +PC: 800000a8 +wid: 2 +rd: 10 rs1: 0 rs2: -1 +is_lw: 0 +is_sw: 0 +fetch_stall_cycles: 0 +mem_stall_cycles: 0 +stall_warp: 0 +wspawn: 0 +stalled: 0 +********************************** scheduler ********************************* +valid: 1 +PC: 800000a8 +wid: 3 +rd: 10 rs1: 0 rs2: -1 +is_lw: 0 +is_sw: 0 +fetch_stall_cycles: 0 +mem_stall_cycles: 0 +stall_warp: 0 +wspawn: 0 +stalled: 0 +********************************** Decode ********************************* +valid: 1 +PC: 800000ac +wid: 1 +rd: 0 rs1: 10 rs2: 0 +is_lw: 0 +is_sw: 0 +fetch_stall_cycles: 0 +mem_stall_cycles: 0 +stall_warp: 1 +wspawn: 0 +stalled: 0 +DEBUG ../core.cpp:386: Core step stepping warp 2[4] +DEBUG ../core.cpp:683: in step pc=0x800000ac +help: in PC: 800000ac +CUrrent CODE: 5006b +DEBUG ../core.cpp:703: Fetched at 0x800000ac +DEBUG ../core.cpp:704: 0x800000ac: gpgpu; +DEBUG ../instruction.cpp:350: Begin instruction execute. +DEBUG ../instruction.cpp:2117: End instruction execute. +DEBUG ../core.cpp:717: Register state: + %r 0: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r 1: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r 2: 67fff000 67ffec04 67ffe808 67ffe40c 00000000 00000000 00000000 00000000 (0) + %r 3: 80001808 80001808 80001808 80001808 00000000 00000000 00000000 00000000 (0) + %r 4: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r 5: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r 6: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r 7: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r 8: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r 9: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r10: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r11: 00000000 00000400 00000800 00000c00 00000000 00000000 00000000 00000000 (0) + %r12: 00000000 00000004 00000008 0000000c 00000000 00000000 00000000 00000000 (0) + %r13: 00000002 00000002 00000002 00000002 00000000 00000000 00000000 00000000 (0) + %r14: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r15: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r16: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r17: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r18: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r19: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r20: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r21: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r22: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r23: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r24: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r25: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r26: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r27: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r28: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r29: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r30: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r31: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) +DEBUG ../core.cpp:726: Thread mask: + 0 0 0 0 0 0 0 0 + + +DEBUG ../core.cpp:388: Now 0 active threads in 2 +********************************** Fetch ********************************* +valid: 1 +PC: 800000ac +wid: 2 +rd: 0 rs1: 10 rs2: 0 +is_lw: 0 +is_sw: 0 +fetch_stall_cycles: 0 +mem_stall_cycles: 0 +stall_warp: 1 +wspawn: 0 +stalled: 0 + + + +------------------------------------------------------ +CYCLE: 101 +Stalled Warps: +0 1 1 0 0 0 0 0 + +********************************** Writeback ********************************* +valid: 1 +PC: 800000a8 +wid: 2 +rd: 10 rs1: 0 rs2: -1 +is_lw: 0 +is_sw: 0 +fetch_stall_cycles: 0 +mem_stall_cycles: 0 +stall_warp: 0 +wspawn: 0 +stalled: 0 +********************************** LSU ********************************* +valid: 0 +PC: 0 +wid: 0 +rd: -1 rs1: -1 rs2: -1 +is_lw: 0 +is_sw: 0 +fetch_stall_cycles: 0 +mem_stall_cycles: 0 +stall_warp: 0 +wspawn: 0 +stalled: 0 +********************************** execute_unit ********************************* +valid: 1 +PC: 800000a8 +wid: 3 +rd: 10 rs1: 0 rs2: -1 +is_lw: 0 +is_sw: 0 +fetch_stall_cycles: 0 +mem_stall_cycles: 0 +stall_warp: 0 +wspawn: 0 +stalled: 0 +********************************** scheduler ********************************* +valid: 1 +PC: 800000ac +wid: 1 +rd: 0 rs1: 10 rs2: 0 +is_lw: 0 +is_sw: 0 +fetch_stall_cycles: 0 +mem_stall_cycles: 0 +stall_warp: 1 +wspawn: 0 +stalled: 0 +********************************** Decode ********************************* +valid: 1 +PC: 800000ac +wid: 2 +rd: 0 rs1: 10 rs2: 0 +is_lw: 0 +is_sw: 0 +fetch_stall_cycles: 0 +mem_stall_cycles: 0 +stall_warp: 1 +wspawn: 0 +stalled: 0 +DEBUG ../core.cpp:386: Core step stepping warp 3[4] +DEBUG ../core.cpp:683: in step pc=0x800000ac +help: in PC: 800000ac +CUrrent CODE: 5006b +DEBUG ../core.cpp:703: Fetched at 0x800000ac +DEBUG ../core.cpp:704: 0x800000ac: gpgpu; +DEBUG ../instruction.cpp:350: Begin instruction execute. +DEBUG ../instruction.cpp:2117: End instruction execute. +DEBUG ../core.cpp:717: Register state: + %r 0: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r 1: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r 2: 63fff000 63ffec04 63ffe808 63ffe40c 00000000 00000000 00000000 00000000 (0) + %r 3: 80001808 80001808 80001808 80001808 00000000 00000000 00000000 00000000 (0) + %r 4: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r 5: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r 6: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r 7: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r 8: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r 9: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r10: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r11: 00000000 00000400 00000800 00000c00 00000000 00000000 00000000 00000000 (0) + %r12: 00000000 00000004 00000008 0000000c 00000000 00000000 00000000 00000000 (0) + %r13: 00000003 00000003 00000003 00000003 00000000 00000000 00000000 00000000 (0) + %r14: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r15: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r16: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r17: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r18: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r19: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r20: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r21: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r22: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r23: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r24: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r25: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r26: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r27: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r28: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r29: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r30: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r31: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) +DEBUG ../core.cpp:726: Thread mask: + 0 0 0 0 0 0 0 0 + + +DEBUG ../core.cpp:388: Now 0 active threads in 3 +********************************** Fetch ********************************* +valid: 1 +PC: 800000ac +wid: 3 +rd: 0 rs1: 10 rs2: 0 +is_lw: 0 +is_sw: 0 +fetch_stall_cycles: 0 +mem_stall_cycles: 0 +stall_warp: 1 +wspawn: 0 +stalled: 0 + + + +------------------------------------------------------ +CYCLE: 102 +Stalled Warps: +0 1 1 1 0 0 0 0 + +********************************** Writeback ********************************* +valid: 1 +PC: 800000a8 +wid: 3 +rd: 10 rs1: 0 rs2: -1 +is_lw: 0 +is_sw: 0 +fetch_stall_cycles: 0 +mem_stall_cycles: 0 +stall_warp: 0 +wspawn: 0 +stalled: 0 +********************************** LSU ********************************* +valid: 0 +PC: 0 +wid: 0 +rd: -1 rs1: -1 rs2: -1 +is_lw: 0 +is_sw: 0 +fetch_stall_cycles: 0 +mem_stall_cycles: 0 +stall_warp: 0 +wspawn: 0 +stalled: 0 +********************************** execute_unit ********************************* +valid: 1 +PC: 800000ac +wid: 1 +rd: 0 rs1: 10 rs2: 0 +is_lw: 0 +is_sw: 0 +fetch_stall_cycles: 0 +mem_stall_cycles: 0 +stall_warp: 1 +wspawn: 0 +stalled: 0 +********************************** scheduler ********************************* +valid: 1 +PC: 800000ac +wid: 2 +rd: 0 rs1: 10 rs2: 0 +is_lw: 0 +is_sw: 0 +fetch_stall_cycles: 0 +mem_stall_cycles: 0 +stall_warp: 1 +wspawn: 0 +stalled: 0 +********************************** Decode ********************************* +valid: 1 +PC: 800000ac +wid: 3 +rd: 0 rs1: 10 rs2: 0 +is_lw: 0 +is_sw: 0 +fetch_stall_cycles: 0 +mem_stall_cycles: 0 +stall_warp: 1 +wspawn: 0 +stalled: 0 +DEBUG ../core.cpp:386: Core step stepping warp 0[4] +DEBUG ../core.cpp:683: in step pc=0x800000b0 +help: in PC: 800000b0 +CUrrent CODE: 8067 +DEBUG ../core.cpp:703: Fetched at 0x800000b0 +DEBUG ../core.cpp:704: 0x800000b0: jalr; +DEBUG ../instruction.cpp:350: Begin instruction execute. +JALR_INST +JALR_INST +JALR_INST +JALR_INST +DEBUG ../instruction.cpp:2117: End instruction execute. +Next PC: 80000014 +DEBUG ../core.cpp:717: Register state: + %r 0: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r 1: 80000014 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r 2: 6ffff000 6fffec04 6fffe808 6fffe40c 00000000 00000000 00000000 00000000 (0) + %r 3: 80001808 80001808 80001808 80001808 00000000 00000000 00000000 00000000 (0) + %r 4: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r 5: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r 6: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r 7: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r 8: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r 9: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r10: 00000004 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r11: 00000000 00000400 00000800 00000c00 00000000 00000000 00000000 00000000 (0) + %r12: 00000000 00000004 00000008 0000000c 00000000 00000000 00000000 00000000 (0) + %r13: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r14: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r15: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r16: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r17: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r18: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r19: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r20: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r21: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r22: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r23: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r24: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r25: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r26: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r27: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r28: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r29: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r30: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r31: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) +DEBUG ../core.cpp:726: Thread mask: + 1 1 1 1 0 0 0 0 + + +DEBUG ../core.cpp:388: Now 4 active threads in 0 +********************************** Fetch ********************************* +valid: 1 +PC: 800000b0 +wid: 0 +rd: 0 rs1: 1 rs2: -1 +is_lw: 0 +is_sw: 0 +fetch_stall_cycles: 3 +mem_stall_cycles: 0 +stall_warp: 1 +wspawn: 0 +stalled: 0 + + + +------------------------------------------------------ +CYCLE: 103 +Stalled Warps: +1 1 1 1 0 0 0 0 + +********************************** Writeback ********************************* +valid: 1 +PC: 800000ac +wid: 1 +rd: 0 rs1: 10 rs2: 0 +is_lw: 0 +is_sw: 0 +fetch_stall_cycles: 0 +mem_stall_cycles: 0 +stall_warp: 1 +wspawn: 0 +stalled: 0 +********************************** LSU ********************************* +valid: 0 +PC: 0 +wid: 0 +rd: -1 rs1: -1 rs2: -1 +is_lw: 0 +is_sw: 0 +fetch_stall_cycles: 0 +mem_stall_cycles: 0 +stall_warp: 0 +wspawn: 0 +stalled: 0 +********************************** execute_unit ********************************* +valid: 1 +PC: 800000ac +wid: 2 +rd: 0 rs1: 10 rs2: 0 +is_lw: 0 +is_sw: 0 +fetch_stall_cycles: 0 +mem_stall_cycles: 0 +stall_warp: 1 +wspawn: 0 +stalled: 0 +********************************** scheduler ********************************* +valid: 1 +PC: 800000ac +wid: 3 +rd: 0 rs1: 10 rs2: 0 +is_lw: 0 +is_sw: 0 +fetch_stall_cycles: 0 +mem_stall_cycles: 0 +stall_warp: 1 +wspawn: 0 +stalled: 0 +********************************** Decode ********************************* +valid: 0 +PC: 0 +wid: 1 +rd: -1 rs1: -1 rs2: -1 +is_lw: 0 +is_sw: 0 +fetch_stall_cycles: 0 +mem_stall_cycles: 0 +stall_warp: 0 +wspawn: 0 +stalled: 0 +********************************** Fetch ********************************* +valid: 1 +PC: 800000b0 +wid: 0 +rd: 0 rs1: 1 rs2: -1 +is_lw: 0 +is_sw: 0 +fetch_stall_cycles: 2 +mem_stall_cycles: 0 +stall_warp: 1 +wspawn: 0 +stalled: 0 + + + +------------------------------------------------------ +CYCLE: 104 +Stalled Warps: +1 1 1 1 0 0 0 0 + +********************************** Writeback ********************************* +valid: 1 +PC: 800000ac +wid: 2 +rd: 0 rs1: 10 rs2: 0 +is_lw: 0 +is_sw: 0 +fetch_stall_cycles: 0 +mem_stall_cycles: 0 +stall_warp: 1 +wspawn: 0 +stalled: 0 +********************************** LSU ********************************* +valid: 0 +PC: 0 +wid: 0 +rd: -1 rs1: -1 rs2: -1 +is_lw: 0 +is_sw: 0 +fetch_stall_cycles: 0 +mem_stall_cycles: 0 +stall_warp: 0 +wspawn: 0 +stalled: 0 +********************************** execute_unit ********************************* +valid: 1 +PC: 800000ac +wid: 3 +rd: 0 rs1: 10 rs2: 0 +is_lw: 0 +is_sw: 0 +fetch_stall_cycles: 0 +mem_stall_cycles: 0 +stall_warp: 1 +wspawn: 0 +stalled: 0 +********************************** scheduler ********************************* +valid: 0 +PC: 0 +wid: 1 +rd: -1 rs1: -1 rs2: -1 +is_lw: 0 +is_sw: 0 +fetch_stall_cycles: 0 +mem_stall_cycles: 0 +stall_warp: 0 +wspawn: 0 +stalled: 0 +********************************** Decode ********************************* +valid: 0 +PC: 0 +wid: 1 +rd: -1 rs1: -1 rs2: -1 +is_lw: 0 +is_sw: 0 +fetch_stall_cycles: 0 +mem_stall_cycles: 0 +stall_warp: 0 +wspawn: 0 +stalled: 0 +********************************** Fetch ********************************* +valid: 1 +PC: 800000b0 +wid: 0 +rd: 0 rs1: 1 rs2: -1 +is_lw: 0 +is_sw: 0 +fetch_stall_cycles: 1 +mem_stall_cycles: 0 +stall_warp: 1 +wspawn: 0 +stalled: 0 + + + +------------------------------------------------------ +CYCLE: 105 +Stalled Warps: +1 0 1 1 0 0 0 0 + +********************************** Writeback ********************************* +valid: 1 +PC: 800000ac +wid: 3 +rd: 0 rs1: 10 rs2: 0 +is_lw: 0 +is_sw: 0 +fetch_stall_cycles: 0 +mem_stall_cycles: 0 +stall_warp: 1 +wspawn: 0 +stalled: 0 +********************************** LSU ********************************* +valid: 0 +PC: 0 +wid: 0 +rd: -1 rs1: -1 rs2: -1 +is_lw: 0 +is_sw: 0 +fetch_stall_cycles: 0 +mem_stall_cycles: 0 +stall_warp: 0 +wspawn: 0 +stalled: 0 +********************************** execute_unit ********************************* +valid: 0 +PC: 0 +wid: 1 +rd: -1 rs1: -1 rs2: -1 +is_lw: 0 +is_sw: 0 +fetch_stall_cycles: 0 +mem_stall_cycles: 0 +stall_warp: 0 +wspawn: 0 +stalled: 0 +********************************** scheduler ********************************* +valid: 0 +PC: 0 +wid: 1 +rd: -1 rs1: -1 rs2: -1 +is_lw: 0 +is_sw: 0 +fetch_stall_cycles: 0 +mem_stall_cycles: 0 +stall_warp: 0 +wspawn: 0 +stalled: 0 +********************************** Decode ********************************* +valid: 0 +PC: 0 +wid: 1 +rd: -1 rs1: -1 rs2: -1 +is_lw: 0 +is_sw: 0 +fetch_stall_cycles: 0 +mem_stall_cycles: 0 +stall_warp: 0 +wspawn: 0 +stalled: 0 +********************************** Fetch ********************************* +valid: 1 +PC: 800000b0 +wid: 0 +rd: 0 rs1: 1 rs2: -1 +is_lw: 0 +is_sw: 0 +fetch_stall_cycles: 0 +mem_stall_cycles: 0 +stall_warp: 1 +wspawn: 0 +stalled: 0 + + + +------------------------------------------------------ +CYCLE: 106 +Stalled Warps: +1 0 0 1 0 0 0 0 + +********************************** Writeback ********************************* +valid: 0 +PC: 0 +wid: 1 +rd: -1 rs1: -1 rs2: -1 +is_lw: 0 +is_sw: 0 +fetch_stall_cycles: 0 +mem_stall_cycles: 0 +stall_warp: 0 +wspawn: 0 +stalled: 0 +********************************** LSU ********************************* +valid: 0 +PC: 0 +wid: 0 +rd: -1 rs1: -1 rs2: -1 +is_lw: 0 +is_sw: 0 +fetch_stall_cycles: 0 +mem_stall_cycles: 0 +stall_warp: 0 +wspawn: 0 +stalled: 0 +********************************** execute_unit ********************************* +valid: 0 +PC: 0 +wid: 1 +rd: -1 rs1: -1 rs2: -1 +is_lw: 0 +is_sw: 0 +fetch_stall_cycles: 0 +mem_stall_cycles: 0 +stall_warp: 0 +wspawn: 0 +stalled: 0 +********************************** scheduler ********************************* +valid: 0 +PC: 0 +wid: 1 +rd: -1 rs1: -1 rs2: -1 +is_lw: 0 +is_sw: 0 +fetch_stall_cycles: 0 +mem_stall_cycles: 0 +stall_warp: 0 +wspawn: 0 +stalled: 0 +********************************** Decode ********************************* +valid: 1 +PC: 800000b0 +wid: 0 +rd: 0 rs1: 1 rs2: -1 +is_lw: 0 +is_sw: 0 +fetch_stall_cycles: 0 +mem_stall_cycles: 0 +stall_warp: 1 +wspawn: 0 +stalled: 0 +********************************** Fetch ********************************* +valid: 0 +PC: 0 +wid: 1 +rd: -1 rs1: -1 rs2: -1 +is_lw: 0 +is_sw: 0 +fetch_stall_cycles: 0 +mem_stall_cycles: 0 +stall_warp: 0 +wspawn: 0 +stalled: 0 + + + +------------------------------------------------------ +CYCLE: 107 +Stalled Warps: +1 0 0 0 0 0 0 0 + +********************************** Writeback ********************************* +valid: 0 +PC: 0 +wid: 2 +rd: -1 rs1: -1 rs2: -1 +is_lw: 0 +is_sw: 0 +fetch_stall_cycles: 0 +mem_stall_cycles: 0 +stall_warp: 0 +wspawn: 0 +stalled: 0 +********************************** LSU ********************************* +valid: 0 +PC: 0 +wid: 0 +rd: -1 rs1: -1 rs2: -1 +is_lw: 0 +is_sw: 0 +fetch_stall_cycles: 0 +mem_stall_cycles: 0 +stall_warp: 0 +wspawn: 0 +stalled: 0 +********************************** execute_unit ********************************* +valid: 0 +PC: 0 +wid: 1 +rd: -1 rs1: -1 rs2: -1 +is_lw: 0 +is_sw: 0 +fetch_stall_cycles: 0 +mem_stall_cycles: 0 +stall_warp: 0 +wspawn: 0 +stalled: 0 +********************************** scheduler ********************************* +valid: 1 +PC: 800000b0 +wid: 0 +rd: 0 rs1: 1 rs2: -1 +is_lw: 0 +is_sw: 0 +fetch_stall_cycles: 0 +mem_stall_cycles: 0 +stall_warp: 1 +wspawn: 0 +stalled: 0 +********************************** Decode ********************************* +valid: 0 +PC: 0 +wid: 1 +rd: -1 rs1: -1 rs2: -1 +is_lw: 0 +is_sw: 0 +fetch_stall_cycles: 0 +mem_stall_cycles: 0 +stall_warp: 0 +wspawn: 0 +stalled: 0 +********************************** Fetch ********************************* +valid: 0 +PC: 0 +wid: 2 +rd: -1 rs1: -1 rs2: -1 +is_lw: 0 +is_sw: 0 +fetch_stall_cycles: 0 +mem_stall_cycles: 0 +stall_warp: 0 +wspawn: 0 +stalled: 0 + + + +------------------------------------------------------ +CYCLE: 108 +Stalled Warps: +1 0 0 0 0 0 0 0 + +********************************** Writeback ********************************* +valid: 0 +PC: 0 +wid: 3 +rd: -1 rs1: -1 rs2: -1 +is_lw: 0 +is_sw: 0 +fetch_stall_cycles: 0 +mem_stall_cycles: 0 +stall_warp: 0 +wspawn: 0 +stalled: 0 +********************************** LSU ********************************* +valid: 0 +PC: 0 +wid: 0 +rd: -1 rs1: -1 rs2: -1 +is_lw: 0 +is_sw: 0 +fetch_stall_cycles: 0 +mem_stall_cycles: 0 +stall_warp: 0 +wspawn: 0 +stalled: 0 +********************************** execute_unit ********************************* +valid: 1 +PC: 800000b0 +wid: 0 +rd: 0 rs1: 1 rs2: -1 +is_lw: 0 +is_sw: 0 +fetch_stall_cycles: 0 +mem_stall_cycles: 0 +stall_warp: 1 +wspawn: 0 +stalled: 0 +********************************** scheduler ********************************* +valid: 0 +PC: 0 +wid: 1 +rd: -1 rs1: -1 rs2: -1 +is_lw: 0 +is_sw: 0 +fetch_stall_cycles: 0 +mem_stall_cycles: 0 +stall_warp: 0 +wspawn: 0 +stalled: 0 +********************************** Decode ********************************* +valid: 0 +PC: 0 +wid: 2 +rd: -1 rs1: -1 rs2: -1 +is_lw: 0 +is_sw: 0 +fetch_stall_cycles: 0 +mem_stall_cycles: 0 +stall_warp: 0 +wspawn: 0 +stalled: 0 +********************************** Fetch ********************************* +valid: 0 +PC: 0 +wid: 3 +rd: -1 rs1: -1 rs2: -1 +is_lw: 0 +is_sw: 0 +fetch_stall_cycles: 0 +mem_stall_cycles: 0 +stall_warp: 0 +wspawn: 0 +stalled: 0 + + + +------------------------------------------------------ +CYCLE: 109 +Stalled Warps: +1 0 0 0 0 0 0 0 + +********************************** Writeback ********************************* +valid: 1 +PC: 800000b0 +wid: 0 +rd: 0 rs1: 1 rs2: -1 +is_lw: 0 +is_sw: 0 +fetch_stall_cycles: 0 +mem_stall_cycles: 0 +stall_warp: 1 +wspawn: 0 +stalled: 0 +********************************** LSU ********************************* +valid: 0 +PC: 0 +wid: 0 +rd: -1 rs1: -1 rs2: -1 +is_lw: 0 +is_sw: 0 +fetch_stall_cycles: 0 +mem_stall_cycles: 0 +stall_warp: 0 +wspawn: 0 +stalled: 0 +********************************** execute_unit ********************************* +valid: 0 +PC: 0 +wid: 1 +rd: -1 rs1: -1 rs2: -1 +is_lw: 0 +is_sw: 0 +fetch_stall_cycles: 0 +mem_stall_cycles: 0 +stall_warp: 0 +wspawn: 0 +stalled: 0 +********************************** scheduler ********************************* +valid: 0 +PC: 0 +wid: 2 +rd: -1 rs1: -1 rs2: -1 +is_lw: 0 +is_sw: 0 +fetch_stall_cycles: 0 +mem_stall_cycles: 0 +stall_warp: 0 +wspawn: 0 +stalled: 0 +********************************** Decode ********************************* +valid: 0 +PC: 0 +wid: 3 +rd: -1 rs1: -1 rs2: -1 +is_lw: 0 +is_sw: 0 +fetch_stall_cycles: 0 +mem_stall_cycles: 0 +stall_warp: 0 +wspawn: 0 +stalled: 0 +********************************** Fetch ********************************* +valid: 0 +PC: 0 +wid: 4 +rd: -1 rs1: -1 rs2: -1 +is_lw: 0 +is_sw: 0 +fetch_stall_cycles: 0 +mem_stall_cycles: 0 +stall_warp: 0 +wspawn: 0 +stalled: 0 + + + +------------------------------------------------------ +CYCLE: 110 +Stalled Warps: +1 0 0 0 0 0 0 0 + +********************************** Writeback ********************************* +valid: 0 +PC: 0 +wid: 5 +rd: -1 rs1: -1 rs2: -1 +is_lw: 0 +is_sw: 0 +fetch_stall_cycles: 0 +mem_stall_cycles: 0 +stall_warp: 0 +wspawn: 0 +stalled: 0 +********************************** LSU ********************************* +valid: 0 +PC: 0 +wid: 0 +rd: -1 rs1: -1 rs2: -1 +is_lw: 0 +is_sw: 0 +fetch_stall_cycles: 0 +mem_stall_cycles: 0 +stall_warp: 0 +wspawn: 0 +stalled: 0 +********************************** execute_unit ********************************* +valid: 0 +PC: 0 +wid: 2 +rd: -1 rs1: -1 rs2: -1 +is_lw: 0 +is_sw: 0 +fetch_stall_cycles: 0 +mem_stall_cycles: 0 +stall_warp: 0 +wspawn: 0 +stalled: 0 +********************************** scheduler ********************************* +valid: 0 +PC: 0 +wid: 3 +rd: -1 rs1: -1 rs2: -1 +is_lw: 0 +is_sw: 0 +fetch_stall_cycles: 0 +mem_stall_cycles: 0 +stall_warp: 0 +wspawn: 0 +stalled: 0 +********************************** Decode ********************************* +valid: 0 +PC: 0 +wid: 4 +rd: -1 rs1: -1 rs2: -1 +is_lw: 0 +is_sw: 0 +fetch_stall_cycles: 0 +mem_stall_cycles: 0 +stall_warp: 0 +wspawn: 0 +stalled: 0 +********************************** Fetch ********************************* +valid: 0 +PC: 0 +wid: 5 +rd: -1 rs1: -1 rs2: -1 +is_lw: 0 +is_sw: 0 +fetch_stall_cycles: 0 +mem_stall_cycles: 0 +stall_warp: 0 +wspawn: 0 +stalled: 0 +Warp ID 0 is running + + + +------------------------------------------------------ +CYCLE: 111 +Stalled Warps: +0 0 0 0 0 0 0 0 + +********************************** Writeback ********************************* +valid: 0 +PC: 0 +wid: 0 +rd: -1 rs1: -1 rs2: -1 +is_lw: 0 +is_sw: 0 +fetch_stall_cycles: 0 +mem_stall_cycles: 0 +stall_warp: 0 +wspawn: 0 +stalled: 0 +********************************** LSU ********************************* +valid: 0 +PC: 0 +wid: 0 +rd: -1 rs1: -1 rs2: -1 +is_lw: 0 +is_sw: 0 +fetch_stall_cycles: 0 +mem_stall_cycles: 0 +stall_warp: 0 +wspawn: 0 +stalled: 0 +********************************** execute_unit ********************************* +valid: 0 +PC: 0 +wid: 3 +rd: -1 rs1: -1 rs2: -1 +is_lw: 0 +is_sw: 0 +fetch_stall_cycles: 0 +mem_stall_cycles: 0 +stall_warp: 0 +wspawn: 0 +stalled: 0 +********************************** scheduler ********************************* +valid: 0 +PC: 0 +wid: 4 +rd: -1 rs1: -1 rs2: -1 +is_lw: 0 +is_sw: 0 +fetch_stall_cycles: 0 +mem_stall_cycles: 0 +stall_warp: 0 +wspawn: 0 +stalled: 0 +********************************** Decode ********************************* +valid: 0 +PC: 0 +wid: 5 +rd: -1 rs1: -1 rs2: -1 +is_lw: 0 +is_sw: 0 +fetch_stall_cycles: 0 +mem_stall_cycles: 0 +stall_warp: 0 +wspawn: 0 +stalled: 0 +DEBUG ../core.cpp:386: Core step stepping warp 0[4] +DEBUG ../core.cpp:683: in step pc=0x80000014 +help: in PC: 80000014 +CUrrent CODE: 100513 +DEBUG ../core.cpp:703: Fetched at 0x80000014 +DEBUG ../core.cpp:704: 0x80000014: i_type; +DEBUG ../instruction.cpp:350: Begin instruction execute. +DEBUG ../instruction.cpp:2117: End instruction execute. +DEBUG ../core.cpp:717: Register state: + %r 0: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r 1: 80000014 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r 2: 6ffff000 6fffec04 6fffe808 6fffe40c 00000000 00000000 00000000 00000000 (0) + %r 3: 80001808 80001808 80001808 80001808 00000000 00000000 00000000 00000000 (0) + %r 4: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r 5: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r 6: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r 7: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r 8: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r 9: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r10: 00000001 00000001 00000001 00000001 00000000 00000000 00000000 00000000 (0) + %r11: 00000000 00000400 00000800 00000c00 00000000 00000000 00000000 00000000 (0) + %r12: 00000000 00000004 00000008 0000000c 00000000 00000000 00000000 00000000 (0) + %r13: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r14: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r15: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r16: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r17: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r18: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r19: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r20: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r21: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r22: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r23: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r24: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r25: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r26: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r27: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r28: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r29: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r30: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r31: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) +DEBUG ../core.cpp:726: Thread mask: + 1 1 1 1 0 0 0 0 + + +DEBUG ../core.cpp:388: Now 4 active threads in 0 +********************************** Fetch ********************************* +valid: 1 +PC: 80000014 +wid: 0 +rd: 10 rs1: 0 rs2: -1 +is_lw: 0 +is_sw: 0 +fetch_stall_cycles: 0 +mem_stall_cycles: 0 +stall_warp: 0 +wspawn: 0 +stalled: 0 + + + +------------------------------------------------------ +CYCLE: 112 +Stalled Warps: +0 0 0 0 0 0 0 0 + +********************************** Writeback ********************************* +valid: 0 +PC: 0 +wid: 0 +rd: -1 rs1: -1 rs2: -1 +is_lw: 0 +is_sw: 0 +fetch_stall_cycles: 0 +mem_stall_cycles: 0 +stall_warp: 0 +wspawn: 0 +stalled: 0 +********************************** LSU ********************************* +valid: 0 +PC: 0 +wid: 0 +rd: -1 rs1: -1 rs2: -1 +is_lw: 0 +is_sw: 0 +fetch_stall_cycles: 0 +mem_stall_cycles: 0 +stall_warp: 0 +wspawn: 0 +stalled: 0 +********************************** execute_unit ********************************* +valid: 0 +PC: 0 +wid: 4 +rd: -1 rs1: -1 rs2: -1 +is_lw: 0 +is_sw: 0 +fetch_stall_cycles: 0 +mem_stall_cycles: 0 +stall_warp: 0 +wspawn: 0 +stalled: 0 +********************************** scheduler ********************************* +valid: 0 +PC: 0 +wid: 5 +rd: -1 rs1: -1 rs2: -1 +is_lw: 0 +is_sw: 0 +fetch_stall_cycles: 0 +mem_stall_cycles: 0 +stall_warp: 0 +wspawn: 0 +stalled: 0 +********************************** Decode ********************************* +valid: 1 +PC: 80000014 +wid: 0 +rd: 10 rs1: 0 rs2: -1 +is_lw: 0 +is_sw: 0 +fetch_stall_cycles: 0 +mem_stall_cycles: 0 +stall_warp: 0 +wspawn: 0 +stalled: 0 +DEBUG ../core.cpp:386: Core step stepping warp 0[4] +DEBUG ../core.cpp:683: in step pc=0x80000018 +help: in PC: 80000018 +CUrrent CODE: 5006b +DEBUG ../core.cpp:703: Fetched at 0x80000018 +DEBUG ../core.cpp:704: 0x80000018: gpgpu; +DEBUG ../instruction.cpp:350: Begin instruction execute. +DEBUG ../instruction.cpp:2117: End instruction execute. +DEBUG ../core.cpp:717: Register state: + %r 0: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r 1: 80000014 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r 2: 6ffff000 6fffec04 6fffe808 6fffe40c 00000000 00000000 00000000 00000000 (0) + %r 3: 80001808 80001808 80001808 80001808 00000000 00000000 00000000 00000000 (0) + %r 4: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r 5: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r 6: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r 7: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r 8: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r 9: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r10: 00000001 00000001 00000001 00000001 00000000 00000000 00000000 00000000 (0) + %r11: 00000000 00000400 00000800 00000c00 00000000 00000000 00000000 00000000 (0) + %r12: 00000000 00000004 00000008 0000000c 00000000 00000000 00000000 00000000 (0) + %r13: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r14: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r15: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r16: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r17: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r18: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r19: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r20: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r21: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r22: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r23: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r24: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r25: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r26: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r27: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r28: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r29: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r30: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r31: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) +DEBUG ../core.cpp:726: Thread mask: + 1 0 0 0 0 0 0 0 + + +DEBUG ../core.cpp:388: Now 1 active threads in 0 +********************************** Fetch ********************************* +valid: 1 +PC: 80000018 +wid: 0 +rd: 0 rs1: 10 rs2: 0 +is_lw: 0 +is_sw: 0 +fetch_stall_cycles: 0 +mem_stall_cycles: 0 +stall_warp: 1 +wspawn: 0 +stalled: 0 + + + +------------------------------------------------------ +CYCLE: 113 +Stalled Warps: +1 0 0 0 0 0 0 0 + +********************************** Writeback ********************************* +valid: 0 +PC: 0 +wid: 1 +rd: -1 rs1: -1 rs2: -1 +is_lw: 0 +is_sw: 0 +fetch_stall_cycles: 0 +mem_stall_cycles: 0 +stall_warp: 0 +wspawn: 0 +stalled: 0 +********************************** LSU ********************************* +valid: 0 +PC: 0 +wid: 0 +rd: -1 rs1: -1 rs2: -1 +is_lw: 0 +is_sw: 0 +fetch_stall_cycles: 0 +mem_stall_cycles: 0 +stall_warp: 0 +wspawn: 0 +stalled: 0 +********************************** execute_unit ********************************* +valid: 0 +PC: 0 +wid: 5 +rd: -1 rs1: -1 rs2: -1 +is_lw: 0 +is_sw: 0 +fetch_stall_cycles: 0 +mem_stall_cycles: 0 +stall_warp: 0 +wspawn: 0 +stalled: 0 +********************************** scheduler ********************************* +valid: 1 +PC: 80000014 +wid: 0 +rd: 10 rs1: 0 rs2: -1 +is_lw: 0 +is_sw: 0 +fetch_stall_cycles: 0 +mem_stall_cycles: 0 +stall_warp: 0 +wspawn: 0 +stalled: 0 +********************************** Decode ********************************* +valid: 1 +PC: 80000018 +wid: 0 +rd: 0 rs1: 10 rs2: 0 +is_lw: 0 +is_sw: 0 +fetch_stall_cycles: 0 +mem_stall_cycles: 0 +stall_warp: 1 +wspawn: 0 +stalled: 0 +********************************** Fetch ********************************* +valid: 0 +PC: 0 +wid: 1 +rd: -1 rs1: -1 rs2: -1 +is_lw: 0 +is_sw: 0 +fetch_stall_cycles: 0 +mem_stall_cycles: 0 +stall_warp: 0 +wspawn: 0 +stalled: 0 + + + +------------------------------------------------------ +CYCLE: 114 +Stalled Warps: +1 0 0 0 0 0 0 0 + +********************************** Writeback ********************************* +valid: 0 +PC: 0 +wid: 2 +rd: -1 rs1: -1 rs2: -1 +is_lw: 0 +is_sw: 0 +fetch_stall_cycles: 0 +mem_stall_cycles: 0 +stall_warp: 0 +wspawn: 0 +stalled: 0 +********************************** LSU ********************************* +valid: 0 +PC: 0 +wid: 0 +rd: -1 rs1: -1 rs2: -1 +is_lw: 0 +is_sw: 0 +fetch_stall_cycles: 0 +mem_stall_cycles: 0 +stall_warp: 0 +wspawn: 0 +stalled: 0 +********************************** execute_unit ********************************* +valid: 1 +PC: 80000014 +wid: 0 +rd: 10 rs1: 0 rs2: -1 +is_lw: 0 +is_sw: 0 +fetch_stall_cycles: 0 +mem_stall_cycles: 0 +stall_warp: 0 +wspawn: 0 +stalled: 0 +********************************** scheduler ********************************* +valid: 1 +PC: 80000018 +wid: 0 +rd: 0 rs1: 10 rs2: 0 +is_lw: 0 +is_sw: 0 +fetch_stall_cycles: 0 +mem_stall_cycles: 0 +stall_warp: 1 +wspawn: 0 +stalled: 0 +********************************** Decode ********************************* +valid: 0 +PC: 0 +wid: 1 +rd: -1 rs1: -1 rs2: -1 +is_lw: 0 +is_sw: 0 +fetch_stall_cycles: 0 +mem_stall_cycles: 0 +stall_warp: 0 +wspawn: 0 +stalled: 0 +********************************** Fetch ********************************* +valid: 0 +PC: 0 +wid: 2 +rd: -1 rs1: -1 rs2: -1 +is_lw: 0 +is_sw: 0 +fetch_stall_cycles: 0 +mem_stall_cycles: 0 +stall_warp: 0 +wspawn: 0 +stalled: 0 + + + +------------------------------------------------------ +CYCLE: 115 +Stalled Warps: +1 0 0 0 0 0 0 0 + +********************************** Writeback ********************************* +valid: 1 +PC: 80000014 +wid: 0 +rd: 10 rs1: 0 rs2: -1 +is_lw: 0 +is_sw: 0 +fetch_stall_cycles: 0 +mem_stall_cycles: 0 +stall_warp: 0 +wspawn: 0 +stalled: 0 +********************************** LSU ********************************* +valid: 0 +PC: 0 +wid: 0 +rd: -1 rs1: -1 rs2: -1 +is_lw: 0 +is_sw: 0 +fetch_stall_cycles: 0 +mem_stall_cycles: 0 +stall_warp: 0 +wspawn: 0 +stalled: 0 +&&&&&&&&&&&&&&&&&&&&&&&& EXECUTE SRCS NOT READY +********************************** execute_unit ********************************* +valid: 0 +PC: 0 +wid: 3 +rd: -1 rs1: -1 rs2: -1 +is_lw: 0 +is_sw: 0 +fetch_stall_cycles: 0 +mem_stall_cycles: 0 +stall_warp: 0 +wspawn: 0 +stalled: 0 +********************************** scheduler ********************************* +valid: 1 +PC: 80000018 +wid: 0 +rd: 0 rs1: 10 rs2: 0 +is_lw: 0 +is_sw: 0 +fetch_stall_cycles: 0 +mem_stall_cycles: 0 +stall_warp: 1 +wspawn: 0 +stalled: 1 +********************************** Decode ********************************* +valid: 0 +PC: 0 +wid: 1 +rd: -1 rs1: -1 rs2: -1 +is_lw: 0 +is_sw: 0 +fetch_stall_cycles: 0 +mem_stall_cycles: 0 +stall_warp: 0 +wspawn: 0 +stalled: 0 +********************************** Fetch ********************************* +valid: 0 +PC: 0 +wid: 2 +rd: -1 rs1: -1 rs2: -1 +is_lw: 0 +is_sw: 0 +fetch_stall_cycles: 0 +mem_stall_cycles: 0 +stall_warp: 0 +wspawn: 0 +stalled: 0 + + + +------------------------------------------------------ +CYCLE: 116 +Stalled Warps: +1 0 0 0 0 0 0 0 + +********************************** Writeback ********************************* +valid: 0 +PC: 0 +wid: 3 +rd: -1 rs1: -1 rs2: -1 +is_lw: 0 +is_sw: 0 +fetch_stall_cycles: 0 +mem_stall_cycles: 0 +stall_warp: 0 +wspawn: 0 +stalled: 0 +********************************** LSU ********************************* +valid: 0 +PC: 0 +wid: 0 +rd: -1 rs1: -1 rs2: -1 +is_lw: 0 +is_sw: 0 +fetch_stall_cycles: 0 +mem_stall_cycles: 0 +stall_warp: 0 +wspawn: 0 +stalled: 0 +********************************** execute_unit ********************************* +valid: 1 +PC: 80000018 +wid: 0 +rd: 0 rs1: 10 rs2: 0 +is_lw: 0 +is_sw: 0 +fetch_stall_cycles: 0 +mem_stall_cycles: 0 +stall_warp: 1 +wspawn: 0 +stalled: 0 +********************************** scheduler ********************************* +valid: 0 +PC: 0 +wid: 1 +rd: -1 rs1: -1 rs2: -1 +is_lw: 0 +is_sw: 0 +fetch_stall_cycles: 0 +mem_stall_cycles: 0 +stall_warp: 0 +wspawn: 0 +stalled: 0 +********************************** Decode ********************************* +valid: 0 +PC: 0 +wid: 2 +rd: -1 rs1: -1 rs2: -1 +is_lw: 0 +is_sw: 0 +fetch_stall_cycles: 0 +mem_stall_cycles: 0 +stall_warp: 0 +wspawn: 0 +stalled: 0 +********************************** Fetch ********************************* +valid: 0 +PC: 0 +wid: 3 +rd: -1 rs1: -1 rs2: -1 +is_lw: 0 +is_sw: 0 +fetch_stall_cycles: 0 +mem_stall_cycles: 0 +stall_warp: 0 +wspawn: 0 +stalled: 0 + + + +------------------------------------------------------ +CYCLE: 117 +Stalled Warps: +1 0 0 0 0 0 0 0 + +********************************** Writeback ********************************* +valid: 1 +PC: 80000018 +wid: 0 +rd: 0 rs1: 10 rs2: 0 +is_lw: 0 +is_sw: 0 +fetch_stall_cycles: 0 +mem_stall_cycles: 0 +stall_warp: 1 +wspawn: 0 +stalled: 0 +********************************** LSU ********************************* +valid: 0 +PC: 0 +wid: 0 +rd: -1 rs1: -1 rs2: -1 +is_lw: 0 +is_sw: 0 +fetch_stall_cycles: 0 +mem_stall_cycles: 0 +stall_warp: 0 +wspawn: 0 +stalled: 0 +********************************** execute_unit ********************************* +valid: 0 +PC: 0 +wid: 1 +rd: -1 rs1: -1 rs2: -1 +is_lw: 0 +is_sw: 0 +fetch_stall_cycles: 0 +mem_stall_cycles: 0 +stall_warp: 0 +wspawn: 0 +stalled: 0 +********************************** scheduler ********************************* +valid: 0 +PC: 0 +wid: 2 +rd: -1 rs1: -1 rs2: -1 +is_lw: 0 +is_sw: 0 +fetch_stall_cycles: 0 +mem_stall_cycles: 0 +stall_warp: 0 +wspawn: 0 +stalled: 0 +********************************** Decode ********************************* +valid: 0 +PC: 0 +wid: 3 +rd: -1 rs1: -1 rs2: -1 +is_lw: 0 +is_sw: 0 +fetch_stall_cycles: 0 +mem_stall_cycles: 0 +stall_warp: 0 +wspawn: 0 +stalled: 0 +********************************** Fetch ********************************* +valid: 0 +PC: 0 +wid: 4 +rd: -1 rs1: -1 rs2: -1 +is_lw: 0 +is_sw: 0 +fetch_stall_cycles: 0 +mem_stall_cycles: 0 +stall_warp: 0 +wspawn: 0 +stalled: 0 + + + +------------------------------------------------------ +CYCLE: 118 +Stalled Warps: +1 0 0 0 0 0 0 0 + +********************************** Writeback ********************************* +valid: 0 +PC: 0 +wid: 5 +rd: -1 rs1: -1 rs2: -1 +is_lw: 0 +is_sw: 0 +fetch_stall_cycles: 0 +mem_stall_cycles: 0 +stall_warp: 0 +wspawn: 0 +stalled: 0 +********************************** LSU ********************************* +valid: 0 +PC: 0 +wid: 0 +rd: -1 rs1: -1 rs2: -1 +is_lw: 0 +is_sw: 0 +fetch_stall_cycles: 0 +mem_stall_cycles: 0 +stall_warp: 0 +wspawn: 0 +stalled: 0 +********************************** execute_unit ********************************* +valid: 0 +PC: 0 +wid: 2 +rd: -1 rs1: -1 rs2: -1 +is_lw: 0 +is_sw: 0 +fetch_stall_cycles: 0 +mem_stall_cycles: 0 +stall_warp: 0 +wspawn: 0 +stalled: 0 +********************************** scheduler ********************************* +valid: 0 +PC: 0 +wid: 3 +rd: -1 rs1: -1 rs2: -1 +is_lw: 0 +is_sw: 0 +fetch_stall_cycles: 0 +mem_stall_cycles: 0 +stall_warp: 0 +wspawn: 0 +stalled: 0 +********************************** Decode ********************************* +valid: 0 +PC: 0 +wid: 4 +rd: -1 rs1: -1 rs2: -1 +is_lw: 0 +is_sw: 0 +fetch_stall_cycles: 0 +mem_stall_cycles: 0 +stall_warp: 0 +wspawn: 0 +stalled: 0 +********************************** Fetch ********************************* +valid: 0 +PC: 0 +wid: 5 +rd: -1 rs1: -1 rs2: -1 +is_lw: 0 +is_sw: 0 +fetch_stall_cycles: 0 +mem_stall_cycles: 0 +stall_warp: 0 +wspawn: 0 +stalled: 0 +Warp ID 0 is running + + + +------------------------------------------------------ +CYCLE: 119 +Stalled Warps: +0 0 0 0 0 0 0 0 + +********************************** Writeback ********************************* +valid: 0 +PC: 0 +wid: 0 +rd: -1 rs1: -1 rs2: -1 +is_lw: 0 +is_sw: 0 +fetch_stall_cycles: 0 +mem_stall_cycles: 0 +stall_warp: 0 +wspawn: 0 +stalled: 0 +********************************** LSU ********************************* +valid: 0 +PC: 0 +wid: 0 +rd: -1 rs1: -1 rs2: -1 +is_lw: 0 +is_sw: 0 +fetch_stall_cycles: 0 +mem_stall_cycles: 0 +stall_warp: 0 +wspawn: 0 +stalled: 0 +********************************** execute_unit ********************************* +valid: 0 +PC: 0 +wid: 3 +rd: -1 rs1: -1 rs2: -1 +is_lw: 0 +is_sw: 0 +fetch_stall_cycles: 0 +mem_stall_cycles: 0 +stall_warp: 0 +wspawn: 0 +stalled: 0 +********************************** scheduler ********************************* +valid: 0 +PC: 0 +wid: 4 +rd: -1 rs1: -1 rs2: -1 +is_lw: 0 +is_sw: 0 +fetch_stall_cycles: 0 +mem_stall_cycles: 0 +stall_warp: 0 +wspawn: 0 +stalled: 0 +********************************** Decode ********************************* +valid: 0 +PC: 0 +wid: 5 +rd: -1 rs1: -1 rs2: -1 +is_lw: 0 +is_sw: 0 +fetch_stall_cycles: 0 +mem_stall_cycles: 0 +stall_warp: 0 +wspawn: 0 +stalled: 0 +DEBUG ../core.cpp:386: Core step stepping warp 0[1] +DEBUG ../core.cpp:683: in step pc=0x8000001c +help: in PC: 8000001c +CUrrent CODE: c3818513 +DEBUG ../core.cpp:703: Fetched at 0x8000001c +DEBUG ../core.cpp:704: 0x8000001c: i_type; +DEBUG ../instruction.cpp:350: Begin instruction execute. +DEBUG ../instruction.cpp:2117: End instruction execute. +DEBUG ../core.cpp:717: Register state: + %r 0: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r 1: 80000014 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r 2: 6ffff000 6fffec04 6fffe808 6fffe40c 00000000 00000000 00000000 00000000 (0) + %r 3: 80001808 80001808 80001808 80001808 00000000 00000000 00000000 00000000 (0) + %r 4: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r 5: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r 6: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r 7: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r 8: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r 9: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r10: 80001440 00000001 00000001 00000001 00000000 00000000 00000000 00000000 (0) + %r11: 00000000 00000400 00000800 00000c00 00000000 00000000 00000000 00000000 (0) + %r12: 00000000 00000004 00000008 0000000c 00000000 00000000 00000000 00000000 (0) + %r13: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r14: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r15: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r16: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r17: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r18: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r19: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r20: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r21: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r22: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r23: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r24: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r25: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r26: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r27: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r28: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r29: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r30: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r31: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) +DEBUG ../core.cpp:726: Thread mask: + 1 0 0 0 0 0 0 0 + + +DEBUG ../core.cpp:388: Now 1 active threads in 0 +********************************** Fetch ********************************* +valid: 1 +PC: 8000001c +wid: 0 +rd: 10 rs1: 3 rs2: -1 +is_lw: 0 +is_sw: 0 +fetch_stall_cycles: 0 +mem_stall_cycles: 0 +stall_warp: 0 +wspawn: 0 +stalled: 0 + + + +------------------------------------------------------ +CYCLE: 120 +Stalled Warps: +0 0 0 0 0 0 0 0 + +********************************** Writeback ********************************* +valid: 0 +PC: 0 +wid: 0 +rd: -1 rs1: -1 rs2: -1 +is_lw: 0 +is_sw: 0 +fetch_stall_cycles: 0 +mem_stall_cycles: 0 +stall_warp: 0 +wspawn: 0 +stalled: 0 +********************************** LSU ********************************* +valid: 0 +PC: 0 +wid: 0 +rd: -1 rs1: -1 rs2: -1 +is_lw: 0 +is_sw: 0 +fetch_stall_cycles: 0 +mem_stall_cycles: 0 +stall_warp: 0 +wspawn: 0 +stalled: 0 +********************************** execute_unit ********************************* +valid: 0 +PC: 0 +wid: 4 +rd: -1 rs1: -1 rs2: -1 +is_lw: 0 +is_sw: 0 +fetch_stall_cycles: 0 +mem_stall_cycles: 0 +stall_warp: 0 +wspawn: 0 +stalled: 0 +********************************** scheduler ********************************* +valid: 0 +PC: 0 +wid: 5 +rd: -1 rs1: -1 rs2: -1 +is_lw: 0 +is_sw: 0 +fetch_stall_cycles: 0 +mem_stall_cycles: 0 +stall_warp: 0 +wspawn: 0 +stalled: 0 +********************************** Decode ********************************* +valid: 1 +PC: 8000001c +wid: 0 +rd: 10 rs1: 3 rs2: -1 +is_lw: 0 +is_sw: 0 +fetch_stall_cycles: 0 +mem_stall_cycles: 0 +stall_warp: 0 +wspawn: 0 +stalled: 0 +DEBUG ../core.cpp:386: Core step stepping warp 0[1] +DEBUG ../core.cpp:683: in step pc=0x80000020 +help: in PC: 80000020 +CUrrent CODE: c3c18613 +DEBUG ../core.cpp:703: Fetched at 0x80000020 +DEBUG ../core.cpp:704: 0x80000020: i_type; +DEBUG ../instruction.cpp:350: Begin instruction execute. +DEBUG ../instruction.cpp:2117: End instruction execute. +DEBUG ../core.cpp:717: Register state: + %r 0: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r 1: 80000014 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r 2: 6ffff000 6fffec04 6fffe808 6fffe40c 00000000 00000000 00000000 00000000 (0) + %r 3: 80001808 80001808 80001808 80001808 00000000 00000000 00000000 00000000 (0) + %r 4: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r 5: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r 6: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r 7: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r 8: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r 9: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r10: 80001440 00000001 00000001 00000001 00000000 00000000 00000000 00000000 (0) + %r11: 00000000 00000400 00000800 00000c00 00000000 00000000 00000000 00000000 (0) + %r12: 80001444 00000004 00000008 0000000c 00000000 00000000 00000000 00000000 (0) + %r13: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r14: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r15: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r16: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r17: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r18: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r19: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r20: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r21: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r22: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r23: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r24: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r25: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r26: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r27: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r28: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r29: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r30: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r31: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) +DEBUG ../core.cpp:726: Thread mask: + 1 0 0 0 0 0 0 0 + + +DEBUG ../core.cpp:388: Now 1 active threads in 0 +********************************** Fetch ********************************* +valid: 1 +PC: 80000020 +wid: 0 +rd: 12 rs1: 3 rs2: -1 +is_lw: 0 +is_sw: 0 +fetch_stall_cycles: 3 +mem_stall_cycles: 0 +stall_warp: 0 +wspawn: 0 +stalled: 0 + + + +------------------------------------------------------ +CYCLE: 121 +Stalled Warps: +0 0 0 0 0 0 0 0 + +********************************** Writeback ********************************* +valid: 0 +PC: 0 +wid: 0 +rd: -1 rs1: -1 rs2: -1 +is_lw: 0 +is_sw: 0 +fetch_stall_cycles: 0 +mem_stall_cycles: 0 +stall_warp: 0 +wspawn: 0 +stalled: 0 +********************************** LSU ********************************* +valid: 0 +PC: 0 +wid: 0 +rd: -1 rs1: -1 rs2: -1 +is_lw: 0 +is_sw: 0 +fetch_stall_cycles: 0 +mem_stall_cycles: 0 +stall_warp: 0 +wspawn: 0 +stalled: 0 +********************************** execute_unit ********************************* +valid: 0 +PC: 0 +wid: 5 +rd: -1 rs1: -1 rs2: -1 +is_lw: 0 +is_sw: 0 +fetch_stall_cycles: 0 +mem_stall_cycles: 0 +stall_warp: 0 +wspawn: 0 +stalled: 0 +********************************** scheduler ********************************* +valid: 1 +PC: 8000001c +wid: 0 +rd: 10 rs1: 3 rs2: -1 +is_lw: 0 +is_sw: 0 +fetch_stall_cycles: 0 +mem_stall_cycles: 0 +stall_warp: 0 +wspawn: 0 +stalled: 0 +********************************** Decode ********************************* +valid: 0 +PC: 0 +wid: 0 +rd: -1 rs1: -1 rs2: -1 +is_lw: 0 +is_sw: 0 +fetch_stall_cycles: 0 +mem_stall_cycles: 0 +stall_warp: 0 +wspawn: 0 +stalled: 0 +********************************** Fetch ********************************* +valid: 1 +PC: 80000020 +wid: 0 +rd: 12 rs1: 3 rs2: -1 +is_lw: 0 +is_sw: 0 +fetch_stall_cycles: 2 +mem_stall_cycles: 0 +stall_warp: 0 +wspawn: 0 +stalled: 0 + + + +------------------------------------------------------ +CYCLE: 122 +Stalled Warps: +0 0 0 0 0 0 0 0 + +********************************** Writeback ********************************* +valid: 0 +PC: 0 +wid: 0 +rd: -1 rs1: -1 rs2: -1 +is_lw: 0 +is_sw: 0 +fetch_stall_cycles: 0 +mem_stall_cycles: 0 +stall_warp: 0 +wspawn: 0 +stalled: 0 +********************************** LSU ********************************* +valid: 0 +PC: 0 +wid: 0 +rd: -1 rs1: -1 rs2: -1 +is_lw: 0 +is_sw: 0 +fetch_stall_cycles: 0 +mem_stall_cycles: 0 +stall_warp: 0 +wspawn: 0 +stalled: 0 +********************************** execute_unit ********************************* +valid: 1 +PC: 8000001c +wid: 0 +rd: 10 rs1: 3 rs2: -1 +is_lw: 0 +is_sw: 0 +fetch_stall_cycles: 0 +mem_stall_cycles: 0 +stall_warp: 0 +wspawn: 0 +stalled: 0 +********************************** scheduler ********************************* +valid: 0 +PC: 0 +wid: 0 +rd: -1 rs1: -1 rs2: -1 +is_lw: 0 +is_sw: 0 +fetch_stall_cycles: 0 +mem_stall_cycles: 0 +stall_warp: 0 +wspawn: 0 +stalled: 0 +********************************** Decode ********************************* +valid: 0 +PC: 0 +wid: 0 +rd: -1 rs1: -1 rs2: -1 +is_lw: 0 +is_sw: 0 +fetch_stall_cycles: 0 +mem_stall_cycles: 0 +stall_warp: 0 +wspawn: 0 +stalled: 0 +********************************** Fetch ********************************* +valid: 1 +PC: 80000020 +wid: 0 +rd: 12 rs1: 3 rs2: -1 +is_lw: 0 +is_sw: 0 +fetch_stall_cycles: 1 +mem_stall_cycles: 0 +stall_warp: 0 +wspawn: 0 +stalled: 0 + + + +------------------------------------------------------ +CYCLE: 123 +Stalled Warps: +0 0 0 0 0 0 0 0 + +********************************** Writeback ********************************* +valid: 1 +PC: 8000001c +wid: 0 +rd: 10 rs1: 3 rs2: -1 +is_lw: 0 +is_sw: 0 +fetch_stall_cycles: 0 +mem_stall_cycles: 0 +stall_warp: 0 +wspawn: 0 +stalled: 0 +********************************** LSU ********************************* +valid: 0 +PC: 0 +wid: 0 +rd: -1 rs1: -1 rs2: -1 +is_lw: 0 +is_sw: 0 +fetch_stall_cycles: 0 +mem_stall_cycles: 0 +stall_warp: 0 +wspawn: 0 +stalled: 0 +********************************** execute_unit ********************************* +valid: 0 +PC: 0 +wid: 0 +rd: -1 rs1: -1 rs2: -1 +is_lw: 0 +is_sw: 0 +fetch_stall_cycles: 0 +mem_stall_cycles: 0 +stall_warp: 0 +wspawn: 0 +stalled: 0 +********************************** scheduler ********************************* +valid: 0 +PC: 0 +wid: 0 +rd: -1 rs1: -1 rs2: -1 +is_lw: 0 +is_sw: 0 +fetch_stall_cycles: 0 +mem_stall_cycles: 0 +stall_warp: 0 +wspawn: 0 +stalled: 0 +********************************** Decode ********************************* +valid: 0 +PC: 0 +wid: 0 +rd: -1 rs1: -1 rs2: -1 +is_lw: 0 +is_sw: 0 +fetch_stall_cycles: 0 +mem_stall_cycles: 0 +stall_warp: 0 +wspawn: 0 +stalled: 0 +********************************** Fetch ********************************* +valid: 1 +PC: 80000020 +wid: 0 +rd: 12 rs1: 3 rs2: -1 +is_lw: 0 +is_sw: 0 +fetch_stall_cycles: 0 +mem_stall_cycles: 0 +stall_warp: 0 +wspawn: 0 +stalled: 0 + + + +------------------------------------------------------ +CYCLE: 124 +Stalled Warps: +0 0 0 0 0 0 0 0 + +********************************** Writeback ********************************* +valid: 0 +PC: 0 +wid: 0 +rd: -1 rs1: -1 rs2: -1 +is_lw: 0 +is_sw: 0 +fetch_stall_cycles: 0 +mem_stall_cycles: 0 +stall_warp: 0 +wspawn: 0 +stalled: 0 +********************************** LSU ********************************* +valid: 0 +PC: 0 +wid: 0 +rd: -1 rs1: -1 rs2: -1 +is_lw: 0 +is_sw: 0 +fetch_stall_cycles: 0 +mem_stall_cycles: 0 +stall_warp: 0 +wspawn: 0 +stalled: 0 +********************************** execute_unit ********************************* +valid: 0 +PC: 0 +wid: 0 +rd: -1 rs1: -1 rs2: -1 +is_lw: 0 +is_sw: 0 +fetch_stall_cycles: 0 +mem_stall_cycles: 0 +stall_warp: 0 +wspawn: 0 +stalled: 0 +********************************** scheduler ********************************* +valid: 0 +PC: 0 +wid: 0 +rd: -1 rs1: -1 rs2: -1 +is_lw: 0 +is_sw: 0 +fetch_stall_cycles: 0 +mem_stall_cycles: 0 +stall_warp: 0 +wspawn: 0 +stalled: 0 +********************************** Decode ********************************* +valid: 1 +PC: 80000020 +wid: 0 +rd: 12 rs1: 3 rs2: -1 +is_lw: 0 +is_sw: 0 +fetch_stall_cycles: 0 +mem_stall_cycles: 0 +stall_warp: 0 +wspawn: 0 +stalled: 0 +DEBUG ../core.cpp:386: Core step stepping warp 0[1] +DEBUG ../core.cpp:683: in step pc=0x80000024 +help: in PC: 80000024 +CUrrent CODE: 40a60633 +DEBUG ../core.cpp:703: Fetched at 0x80000024 +DEBUG ../core.cpp:704: 0x80000024: r_type; +DEBUG ../instruction.cpp:350: Begin instruction execute. +DEBUG ../instruction.cpp:2117: End instruction execute. +DEBUG ../core.cpp:717: Register state: + %r 0: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r 1: 80000014 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r 2: 6ffff000 6fffec04 6fffe808 6fffe40c 00000000 00000000 00000000 00000000 (0) + %r 3: 80001808 80001808 80001808 80001808 00000000 00000000 00000000 00000000 (0) + %r 4: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r 5: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r 6: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r 7: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r 8: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r 9: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r10: 80001440 00000001 00000001 00000001 00000000 00000000 00000000 00000000 (0) + %r11: 00000000 00000400 00000800 00000c00 00000000 00000000 00000000 00000000 (0) + %r12: 00000004 00000004 00000008 0000000c 00000000 00000000 00000000 00000000 (0) + %r13: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r14: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r15: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r16: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r17: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r18: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r19: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r20: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r21: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r22: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r23: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r24: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r25: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r26: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r27: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r28: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r29: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r30: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r31: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) +DEBUG ../core.cpp:726: Thread mask: + 1 0 0 0 0 0 0 0 + + +DEBUG ../core.cpp:388: Now 1 active threads in 0 +********************************** Fetch ********************************* +valid: 1 +PC: 80000024 +wid: 0 +rd: 12 rs1: 12 rs2: 10 +is_lw: 0 +is_sw: 0 +fetch_stall_cycles: 0 +mem_stall_cycles: 0 +stall_warp: 0 +wspawn: 0 +stalled: 0 + + + +------------------------------------------------------ +CYCLE: 125 +Stalled Warps: +0 0 0 0 0 0 0 0 + +********************************** Writeback ********************************* +valid: 0 +PC: 0 +wid: 0 +rd: -1 rs1: -1 rs2: -1 +is_lw: 0 +is_sw: 0 +fetch_stall_cycles: 0 +mem_stall_cycles: 0 +stall_warp: 0 +wspawn: 0 +stalled: 0 +********************************** LSU ********************************* +valid: 0 +PC: 0 +wid: 0 +rd: -1 rs1: -1 rs2: -1 +is_lw: 0 +is_sw: 0 +fetch_stall_cycles: 0 +mem_stall_cycles: 0 +stall_warp: 0 +wspawn: 0 +stalled: 0 +********************************** execute_unit ********************************* +valid: 0 +PC: 0 +wid: 0 +rd: -1 rs1: -1 rs2: -1 +is_lw: 0 +is_sw: 0 +fetch_stall_cycles: 0 +mem_stall_cycles: 0 +stall_warp: 0 +wspawn: 0 +stalled: 0 +********************************** scheduler ********************************* +valid: 1 +PC: 80000020 +wid: 0 +rd: 12 rs1: 3 rs2: -1 +is_lw: 0 +is_sw: 0 +fetch_stall_cycles: 0 +mem_stall_cycles: 0 +stall_warp: 0 +wspawn: 0 +stalled: 0 +********************************** Decode ********************************* +valid: 1 +PC: 80000024 +wid: 0 +rd: 12 rs1: 12 rs2: 10 +is_lw: 0 +is_sw: 0 +fetch_stall_cycles: 0 +mem_stall_cycles: 0 +stall_warp: 0 +wspawn: 0 +stalled: 0 +DEBUG ../core.cpp:386: Core step stepping warp 0[1] +DEBUG ../core.cpp:683: in step pc=0x80000028 +help: in PC: 80000028 +CUrrent CODE: 593 +DEBUG ../core.cpp:703: Fetched at 0x80000028 +DEBUG ../core.cpp:704: 0x80000028: i_type; +DEBUG ../instruction.cpp:350: Begin instruction execute. +DEBUG ../instruction.cpp:2117: End instruction execute. +DEBUG ../core.cpp:717: Register state: + %r 0: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r 1: 80000014 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r 2: 6ffff000 6fffec04 6fffe808 6fffe40c 00000000 00000000 00000000 00000000 (0) + %r 3: 80001808 80001808 80001808 80001808 00000000 00000000 00000000 00000000 (0) + %r 4: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r 5: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r 6: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r 7: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r 8: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r 9: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r10: 80001440 00000001 00000001 00000001 00000000 00000000 00000000 00000000 (0) + %r11: 00000000 00000400 00000800 00000c00 00000000 00000000 00000000 00000000 (0) + %r12: 00000004 00000004 00000008 0000000c 00000000 00000000 00000000 00000000 (0) + %r13: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r14: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r15: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r16: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r17: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r18: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r19: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r20: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r21: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r22: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r23: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r24: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r25: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r26: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r27: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r28: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r29: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r30: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r31: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) +DEBUG ../core.cpp:726: Thread mask: + 1 0 0 0 0 0 0 0 + + +DEBUG ../core.cpp:388: Now 1 active threads in 0 +********************************** Fetch ********************************* +valid: 1 +PC: 80000028 +wid: 0 +rd: 11 rs1: 0 rs2: -1 +is_lw: 0 +is_sw: 0 +fetch_stall_cycles: 0 +mem_stall_cycles: 0 +stall_warp: 0 +wspawn: 0 +stalled: 0 + + + +------------------------------------------------------ +CYCLE: 126 +Stalled Warps: +0 0 0 0 0 0 0 0 + +********************************** Writeback ********************************* +valid: 0 +PC: 0 +wid: 0 +rd: -1 rs1: -1 rs2: -1 +is_lw: 0 +is_sw: 0 +fetch_stall_cycles: 0 +mem_stall_cycles: 0 +stall_warp: 0 +wspawn: 0 +stalled: 0 +********************************** LSU ********************************* +valid: 0 +PC: 0 +wid: 0 +rd: -1 rs1: -1 rs2: -1 +is_lw: 0 +is_sw: 0 +fetch_stall_cycles: 0 +mem_stall_cycles: 0 +stall_warp: 0 +wspawn: 0 +stalled: 0 +********************************** execute_unit ********************************* +valid: 1 +PC: 80000020 +wid: 0 +rd: 12 rs1: 3 rs2: -1 +is_lw: 0 +is_sw: 0 +fetch_stall_cycles: 0 +mem_stall_cycles: 0 +stall_warp: 0 +wspawn: 0 +stalled: 0 +********************************** scheduler ********************************* +valid: 1 +PC: 80000024 +wid: 0 +rd: 12 rs1: 12 rs2: 10 +is_lw: 0 +is_sw: 0 +fetch_stall_cycles: 0 +mem_stall_cycles: 0 +stall_warp: 0 +wspawn: 0 +stalled: 0 +********************************** Decode ********************************* +valid: 1 +PC: 80000028 +wid: 0 +rd: 11 rs1: 0 rs2: -1 +is_lw: 0 +is_sw: 0 +fetch_stall_cycles: 0 +mem_stall_cycles: 0 +stall_warp: 0 +wspawn: 0 +stalled: 0 +DEBUG ../core.cpp:386: Core step stepping warp 0[1] +DEBUG ../core.cpp:683: in step pc=0x8000002c +help: in PC: 8000002c +CUrrent CODE: 1f5000ef +DEBUG ../core.cpp:703: Fetched at 0x8000002c +DEBUG ../core.cpp:704: 0x8000002c: jal; +DEBUG ../instruction.cpp:350: Begin instruction execute. +DEBUG ../instruction.cpp:2117: End instruction execute. +Next PC: 80000a20 +DEBUG ../core.cpp:717: Register state: + %r 0: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r 1: 80000030 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r 2: 6ffff000 6fffec04 6fffe808 6fffe40c 00000000 00000000 00000000 00000000 (0) + %r 3: 80001808 80001808 80001808 80001808 00000000 00000000 00000000 00000000 (0) + %r 4: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r 5: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r 6: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r 7: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r 8: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r 9: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r10: 80001440 00000001 00000001 00000001 00000000 00000000 00000000 00000000 (0) + %r11: 00000000 00000400 00000800 00000c00 00000000 00000000 00000000 00000000 (0) + %r12: 00000004 00000004 00000008 0000000c 00000000 00000000 00000000 00000000 (0) + %r13: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r14: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r15: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r16: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r17: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r18: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r19: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r20: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r21: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r22: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r23: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r24: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r25: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r26: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r27: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r28: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r29: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r30: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r31: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) +DEBUG ../core.cpp:726: Thread mask: + 1 0 0 0 0 0 0 0 + + +DEBUG ../core.cpp:388: Now 1 active threads in 0 +********************************** Fetch ********************************* +valid: 1 +PC: 8000002c +wid: 0 +rd: 1 rs1: -1 rs2: -1 +is_lw: 0 +is_sw: 0 +fetch_stall_cycles: 0 +mem_stall_cycles: 0 +stall_warp: 1 +wspawn: 0 +stalled: 0 + + + +------------------------------------------------------ +CYCLE: 127 +Stalled Warps: +1 0 0 0 0 0 0 0 + +********************************** Writeback ********************************* +valid: 1 +PC: 80000020 +wid: 0 +rd: 12 rs1: 3 rs2: -1 +is_lw: 0 +is_sw: 0 +fetch_stall_cycles: 0 +mem_stall_cycles: 0 +stall_warp: 0 +wspawn: 0 +stalled: 0 +********************************** LSU ********************************* +valid: 0 +PC: 0 +wid: 0 +rd: -1 rs1: -1 rs2: -1 +is_lw: 0 +is_sw: 0 +fetch_stall_cycles: 0 +mem_stall_cycles: 0 +stall_warp: 0 +wspawn: 0 +stalled: 0 +&&&&&&&&&&&&&&&&&&&&&&&& EXECUTE SRCS NOT READY +********************************** execute_unit ********************************* +valid: 0 +PC: 0 +wid: 1 +rd: -1 rs1: -1 rs2: -1 +is_lw: 0 +is_sw: 0 +fetch_stall_cycles: 0 +mem_stall_cycles: 0 +stall_warp: 0 +wspawn: 0 +stalled: 0 +********************************** scheduler ********************************* +valid: 1 +PC: 80000024 +wid: 0 +rd: 12 rs1: 12 rs2: 10 +is_lw: 0 +is_sw: 0 +fetch_stall_cycles: 0 +mem_stall_cycles: 0 +stall_warp: 0 +wspawn: 0 +stalled: 1 +********************************** Decode ********************************* +valid: 1 +PC: 80000028 +wid: 0 +rd: 11 rs1: 0 rs2: -1 +is_lw: 0 +is_sw: 0 +fetch_stall_cycles: 0 +mem_stall_cycles: 0 +stall_warp: 0 +wspawn: 0 +stalled: 0 +********************************** Fetch ********************************* +valid: 1 +PC: 8000002c +wid: 0 +rd: 1 rs1: -1 rs2: -1 +is_lw: 0 +is_sw: 0 +fetch_stall_cycles: 0 +mem_stall_cycles: 0 +stall_warp: 1 +wspawn: 0 +stalled: 0 + + + +------------------------------------------------------ +CYCLE: 128 +Stalled Warps: +1 0 0 0 0 0 0 0 + +********************************** Writeback ********************************* +valid: 0 +PC: 0 +wid: 1 +rd: -1 rs1: -1 rs2: -1 +is_lw: 0 +is_sw: 0 +fetch_stall_cycles: 0 +mem_stall_cycles: 0 +stall_warp: 0 +wspawn: 0 +stalled: 0 +********************************** LSU ********************************* +valid: 0 +PC: 0 +wid: 0 +rd: -1 rs1: -1 rs2: -1 +is_lw: 0 +is_sw: 0 +fetch_stall_cycles: 0 +mem_stall_cycles: 0 +stall_warp: 0 +wspawn: 0 +stalled: 0 +********************************** execute_unit ********************************* +valid: 1 +PC: 80000024 +wid: 0 +rd: 12 rs1: 12 rs2: 10 +is_lw: 0 +is_sw: 0 +fetch_stall_cycles: 0 +mem_stall_cycles: 0 +stall_warp: 0 +wspawn: 0 +stalled: 0 +********************************** scheduler ********************************* +valid: 1 +PC: 80000028 +wid: 0 +rd: 11 rs1: 0 rs2: -1 +is_lw: 0 +is_sw: 0 +fetch_stall_cycles: 0 +mem_stall_cycles: 0 +stall_warp: 0 +wspawn: 0 +stalled: 0 +********************************** Decode ********************************* +valid: 1 +PC: 8000002c +wid: 0 +rd: 1 rs1: -1 rs2: -1 +is_lw: 0 +is_sw: 0 +fetch_stall_cycles: 0 +mem_stall_cycles: 0 +stall_warp: 1 +wspawn: 0 +stalled: 0 +********************************** Fetch ********************************* +valid: 0 +PC: 0 +wid: 1 +rd: -1 rs1: -1 rs2: -1 +is_lw: 0 +is_sw: 0 +fetch_stall_cycles: 0 +mem_stall_cycles: 0 +stall_warp: 0 +wspawn: 0 +stalled: 0 + + + +------------------------------------------------------ +CYCLE: 129 +Stalled Warps: +1 0 0 0 0 0 0 0 + +********************************** Writeback ********************************* +valid: 1 +PC: 80000024 +wid: 0 +rd: 12 rs1: 12 rs2: 10 +is_lw: 0 +is_sw: 0 +fetch_stall_cycles: 0 +mem_stall_cycles: 0 +stall_warp: 0 +wspawn: 0 +stalled: 0 +********************************** LSU ********************************* +valid: 0 +PC: 0 +wid: 0 +rd: -1 rs1: -1 rs2: -1 +is_lw: 0 +is_sw: 0 +fetch_stall_cycles: 0 +mem_stall_cycles: 0 +stall_warp: 0 +wspawn: 0 +stalled: 0 +********************************** execute_unit ********************************* +valid: 1 +PC: 80000028 +wid: 0 +rd: 11 rs1: 0 rs2: -1 +is_lw: 0 +is_sw: 0 +fetch_stall_cycles: 0 +mem_stall_cycles: 0 +stall_warp: 0 +wspawn: 0 +stalled: 0 +********************************** scheduler ********************************* +valid: 1 +PC: 8000002c +wid: 0 +rd: 1 rs1: -1 rs2: -1 +is_lw: 0 +is_sw: 0 +fetch_stall_cycles: 0 +mem_stall_cycles: 0 +stall_warp: 1 +wspawn: 0 +stalled: 0 +********************************** Decode ********************************* +valid: 0 +PC: 0 +wid: 1 +rd: -1 rs1: -1 rs2: -1 +is_lw: 0 +is_sw: 0 +fetch_stall_cycles: 0 +mem_stall_cycles: 0 +stall_warp: 0 +wspawn: 0 +stalled: 0 +********************************** Fetch ********************************* +valid: 0 +PC: 0 +wid: 2 +rd: -1 rs1: -1 rs2: -1 +is_lw: 0 +is_sw: 0 +fetch_stall_cycles: 0 +mem_stall_cycles: 0 +stall_warp: 0 +wspawn: 0 +stalled: 0 + + + +------------------------------------------------------ +CYCLE: 130 +Stalled Warps: +1 0 0 0 0 0 0 0 + +********************************** Writeback ********************************* +valid: 1 +PC: 80000028 +wid: 0 +rd: 11 rs1: 0 rs2: -1 +is_lw: 0 +is_sw: 0 +fetch_stall_cycles: 0 +mem_stall_cycles: 0 +stall_warp: 0 +wspawn: 0 +stalled: 0 +********************************** LSU ********************************* +valid: 0 +PC: 0 +wid: 0 +rd: -1 rs1: -1 rs2: -1 +is_lw: 0 +is_sw: 0 +fetch_stall_cycles: 0 +mem_stall_cycles: 0 +stall_warp: 0 +wspawn: 0 +stalled: 0 +********************************** execute_unit ********************************* +valid: 1 +PC: 8000002c +wid: 0 +rd: 1 rs1: -1 rs2: -1 +is_lw: 0 +is_sw: 0 +fetch_stall_cycles: 0 +mem_stall_cycles: 0 +stall_warp: 1 +wspawn: 0 +stalled: 0 +********************************** scheduler ********************************* +valid: 0 +PC: 0 +wid: 1 +rd: -1 rs1: -1 rs2: -1 +is_lw: 0 +is_sw: 0 +fetch_stall_cycles: 0 +mem_stall_cycles: 0 +stall_warp: 0 +wspawn: 0 +stalled: 0 +********************************** Decode ********************************* +valid: 0 +PC: 0 +wid: 2 +rd: -1 rs1: -1 rs2: -1 +is_lw: 0 +is_sw: 0 +fetch_stall_cycles: 0 +mem_stall_cycles: 0 +stall_warp: 0 +wspawn: 0 +stalled: 0 +********************************** Fetch ********************************* +valid: 0 +PC: 0 +wid: 3 +rd: -1 rs1: -1 rs2: -1 +is_lw: 0 +is_sw: 0 +fetch_stall_cycles: 0 +mem_stall_cycles: 0 +stall_warp: 0 +wspawn: 0 +stalled: 0 + + + +------------------------------------------------------ +CYCLE: 131 +Stalled Warps: +1 0 0 0 0 0 0 0 + +********************************** Writeback ********************************* +valid: 1 +PC: 8000002c +wid: 0 +rd: 1 rs1: -1 rs2: -1 +is_lw: 0 +is_sw: 0 +fetch_stall_cycles: 0 +mem_stall_cycles: 0 +stall_warp: 1 +wspawn: 0 +stalled: 0 +********************************** LSU ********************************* +valid: 0 +PC: 0 +wid: 0 +rd: -1 rs1: -1 rs2: -1 +is_lw: 0 +is_sw: 0 +fetch_stall_cycles: 0 +mem_stall_cycles: 0 +stall_warp: 0 +wspawn: 0 +stalled: 0 +********************************** execute_unit ********************************* +valid: 0 +PC: 0 +wid: 1 +rd: -1 rs1: -1 rs2: -1 +is_lw: 0 +is_sw: 0 +fetch_stall_cycles: 0 +mem_stall_cycles: 0 +stall_warp: 0 +wspawn: 0 +stalled: 0 +********************************** scheduler ********************************* +valid: 0 +PC: 0 +wid: 2 +rd: -1 rs1: -1 rs2: -1 +is_lw: 0 +is_sw: 0 +fetch_stall_cycles: 0 +mem_stall_cycles: 0 +stall_warp: 0 +wspawn: 0 +stalled: 0 +********************************** Decode ********************************* +valid: 0 +PC: 0 +wid: 3 +rd: -1 rs1: -1 rs2: -1 +is_lw: 0 +is_sw: 0 +fetch_stall_cycles: 0 +mem_stall_cycles: 0 +stall_warp: 0 +wspawn: 0 +stalled: 0 +********************************** Fetch ********************************* +valid: 0 +PC: 0 +wid: 4 +rd: -1 rs1: -1 rs2: -1 +is_lw: 0 +is_sw: 0 +fetch_stall_cycles: 0 +mem_stall_cycles: 0 +stall_warp: 0 +wspawn: 0 +stalled: 0 + + + +------------------------------------------------------ +CYCLE: 132 +Stalled Warps: +1 0 0 0 0 0 0 0 + +********************************** Writeback ********************************* +valid: 0 +PC: 0 +wid: 5 +rd: -1 rs1: -1 rs2: -1 +is_lw: 0 +is_sw: 0 +fetch_stall_cycles: 0 +mem_stall_cycles: 0 +stall_warp: 0 +wspawn: 0 +stalled: 0 +********************************** LSU ********************************* +valid: 0 +PC: 0 +wid: 0 +rd: -1 rs1: -1 rs2: -1 +is_lw: 0 +is_sw: 0 +fetch_stall_cycles: 0 +mem_stall_cycles: 0 +stall_warp: 0 +wspawn: 0 +stalled: 0 +********************************** execute_unit ********************************* +valid: 0 +PC: 0 +wid: 2 +rd: -1 rs1: -1 rs2: -1 +is_lw: 0 +is_sw: 0 +fetch_stall_cycles: 0 +mem_stall_cycles: 0 +stall_warp: 0 +wspawn: 0 +stalled: 0 +********************************** scheduler ********************************* +valid: 0 +PC: 0 +wid: 3 +rd: -1 rs1: -1 rs2: -1 +is_lw: 0 +is_sw: 0 +fetch_stall_cycles: 0 +mem_stall_cycles: 0 +stall_warp: 0 +wspawn: 0 +stalled: 0 +********************************** Decode ********************************* +valid: 0 +PC: 0 +wid: 4 +rd: -1 rs1: -1 rs2: -1 +is_lw: 0 +is_sw: 0 +fetch_stall_cycles: 0 +mem_stall_cycles: 0 +stall_warp: 0 +wspawn: 0 +stalled: 0 +********************************** Fetch ********************************* +valid: 0 +PC: 0 +wid: 5 +rd: -1 rs1: -1 rs2: -1 +is_lw: 0 +is_sw: 0 +fetch_stall_cycles: 0 +mem_stall_cycles: 0 +stall_warp: 0 +wspawn: 0 +stalled: 0 +Warp ID 0 is running + + + +------------------------------------------------------ +CYCLE: 133 +Stalled Warps: +0 0 0 0 0 0 0 0 + +********************************** Writeback ********************************* +valid: 0 +PC: 0 +wid: 0 +rd: -1 rs1: -1 rs2: -1 +is_lw: 0 +is_sw: 0 +fetch_stall_cycles: 0 +mem_stall_cycles: 0 +stall_warp: 0 +wspawn: 0 +stalled: 0 +********************************** LSU ********************************* +valid: 0 +PC: 0 +wid: 0 +rd: -1 rs1: -1 rs2: -1 +is_lw: 0 +is_sw: 0 +fetch_stall_cycles: 0 +mem_stall_cycles: 0 +stall_warp: 0 +wspawn: 0 +stalled: 0 +********************************** execute_unit ********************************* +valid: 0 +PC: 0 +wid: 3 +rd: -1 rs1: -1 rs2: -1 +is_lw: 0 +is_sw: 0 +fetch_stall_cycles: 0 +mem_stall_cycles: 0 +stall_warp: 0 +wspawn: 0 +stalled: 0 +********************************** scheduler ********************************* +valid: 0 +PC: 0 +wid: 4 +rd: -1 rs1: -1 rs2: -1 +is_lw: 0 +is_sw: 0 +fetch_stall_cycles: 0 +mem_stall_cycles: 0 +stall_warp: 0 +wspawn: 0 +stalled: 0 +********************************** Decode ********************************* +valid: 0 +PC: 0 +wid: 5 +rd: -1 rs1: -1 rs2: -1 +is_lw: 0 +is_sw: 0 +fetch_stall_cycles: 0 +mem_stall_cycles: 0 +stall_warp: 0 +wspawn: 0 +stalled: 0 +DEBUG ../core.cpp:386: Core step stepping warp 0[1] +DEBUG ../core.cpp:683: in step pc=0x80000a20 +help: in PC: 80000a20 +CUrrent CODE: f00313 +DEBUG ../core.cpp:703: Fetched at 0x80000a20 +DEBUG ../core.cpp:704: 0x80000a20: i_type; +DEBUG ../instruction.cpp:350: Begin instruction execute. +DEBUG ../instruction.cpp:2117: End instruction execute. +DEBUG ../core.cpp:717: Register state: + %r 0: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r 1: 80000030 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r 2: 6ffff000 6fffec04 6fffe808 6fffe40c 00000000 00000000 00000000 00000000 (0) + %r 3: 80001808 80001808 80001808 80001808 00000000 00000000 00000000 00000000 (0) + %r 4: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r 5: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r 6: 0000000f 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r 7: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r 8: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r 9: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r10: 80001440 00000001 00000001 00000001 00000000 00000000 00000000 00000000 (0) + %r11: 00000000 00000400 00000800 00000c00 00000000 00000000 00000000 00000000 (0) + %r12: 00000004 00000004 00000008 0000000c 00000000 00000000 00000000 00000000 (0) + %r13: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r14: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r15: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r16: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r17: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r18: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r19: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r20: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r21: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r22: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r23: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r24: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r25: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r26: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r27: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r28: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r29: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r30: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r31: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) +DEBUG ../core.cpp:726: Thread mask: + 1 0 0 0 0 0 0 0 + + +DEBUG ../core.cpp:388: Now 1 active threads in 0 +********************************** Fetch ********************************* +valid: 1 +PC: 80000a20 +wid: 0 +rd: 6 rs1: 0 rs2: -1 +is_lw: 0 +is_sw: 0 +fetch_stall_cycles: 3 +mem_stall_cycles: 0 +stall_warp: 0 +wspawn: 0 +stalled: 0 + + + +------------------------------------------------------ +CYCLE: 134 +Stalled Warps: +0 0 0 0 0 0 0 0 + +********************************** Writeback ********************************* +valid: 0 +PC: 0 +wid: 0 +rd: -1 rs1: -1 rs2: -1 +is_lw: 0 +is_sw: 0 +fetch_stall_cycles: 0 +mem_stall_cycles: 0 +stall_warp: 0 +wspawn: 0 +stalled: 0 +********************************** LSU ********************************* +valid: 0 +PC: 0 +wid: 0 +rd: -1 rs1: -1 rs2: -1 +is_lw: 0 +is_sw: 0 +fetch_stall_cycles: 0 +mem_stall_cycles: 0 +stall_warp: 0 +wspawn: 0 +stalled: 0 +********************************** execute_unit ********************************* +valid: 0 +PC: 0 +wid: 4 +rd: -1 rs1: -1 rs2: -1 +is_lw: 0 +is_sw: 0 +fetch_stall_cycles: 0 +mem_stall_cycles: 0 +stall_warp: 0 +wspawn: 0 +stalled: 0 +********************************** scheduler ********************************* +valid: 0 +PC: 0 +wid: 5 +rd: -1 rs1: -1 rs2: -1 +is_lw: 0 +is_sw: 0 +fetch_stall_cycles: 0 +mem_stall_cycles: 0 +stall_warp: 0 +wspawn: 0 +stalled: 0 +********************************** Decode ********************************* +valid: 0 +PC: 0 +wid: 0 +rd: -1 rs1: -1 rs2: -1 +is_lw: 0 +is_sw: 0 +fetch_stall_cycles: 0 +mem_stall_cycles: 0 +stall_warp: 0 +wspawn: 0 +stalled: 0 +********************************** Fetch ********************************* +valid: 1 +PC: 80000a20 +wid: 0 +rd: 6 rs1: 0 rs2: -1 +is_lw: 0 +is_sw: 0 +fetch_stall_cycles: 2 +mem_stall_cycles: 0 +stall_warp: 0 +wspawn: 0 +stalled: 0 + + + +------------------------------------------------------ +CYCLE: 135 +Stalled Warps: +0 0 0 0 0 0 0 0 + +********************************** Writeback ********************************* +valid: 0 +PC: 0 +wid: 0 +rd: -1 rs1: -1 rs2: -1 +is_lw: 0 +is_sw: 0 +fetch_stall_cycles: 0 +mem_stall_cycles: 0 +stall_warp: 0 +wspawn: 0 +stalled: 0 +********************************** LSU ********************************* +valid: 0 +PC: 0 +wid: 0 +rd: -1 rs1: -1 rs2: -1 +is_lw: 0 +is_sw: 0 +fetch_stall_cycles: 0 +mem_stall_cycles: 0 +stall_warp: 0 +wspawn: 0 +stalled: 0 +********************************** execute_unit ********************************* +valid: 0 +PC: 0 +wid: 5 +rd: -1 rs1: -1 rs2: -1 +is_lw: 0 +is_sw: 0 +fetch_stall_cycles: 0 +mem_stall_cycles: 0 +stall_warp: 0 +wspawn: 0 +stalled: 0 +********************************** scheduler ********************************* +valid: 0 +PC: 0 +wid: 0 +rd: -1 rs1: -1 rs2: -1 +is_lw: 0 +is_sw: 0 +fetch_stall_cycles: 0 +mem_stall_cycles: 0 +stall_warp: 0 +wspawn: 0 +stalled: 0 +********************************** Decode ********************************* +valid: 0 +PC: 0 +wid: 0 +rd: -1 rs1: -1 rs2: -1 +is_lw: 0 +is_sw: 0 +fetch_stall_cycles: 0 +mem_stall_cycles: 0 +stall_warp: 0 +wspawn: 0 +stalled: 0 +********************************** Fetch ********************************* +valid: 1 +PC: 80000a20 +wid: 0 +rd: 6 rs1: 0 rs2: -1 +is_lw: 0 +is_sw: 0 +fetch_stall_cycles: 1 +mem_stall_cycles: 0 +stall_warp: 0 +wspawn: 0 +stalled: 0 + + + +------------------------------------------------------ +CYCLE: 136 +Stalled Warps: +0 0 0 0 0 0 0 0 + +********************************** Writeback ********************************* +valid: 0 +PC: 0 +wid: 0 +rd: -1 rs1: -1 rs2: -1 +is_lw: 0 +is_sw: 0 +fetch_stall_cycles: 0 +mem_stall_cycles: 0 +stall_warp: 0 +wspawn: 0 +stalled: 0 +********************************** LSU ********************************* +valid: 0 +PC: 0 +wid: 0 +rd: -1 rs1: -1 rs2: -1 +is_lw: 0 +is_sw: 0 +fetch_stall_cycles: 0 +mem_stall_cycles: 0 +stall_warp: 0 +wspawn: 0 +stalled: 0 +********************************** execute_unit ********************************* +valid: 0 +PC: 0 +wid: 0 +rd: -1 rs1: -1 rs2: -1 +is_lw: 0 +is_sw: 0 +fetch_stall_cycles: 0 +mem_stall_cycles: 0 +stall_warp: 0 +wspawn: 0 +stalled: 0 +********************************** scheduler ********************************* +valid: 0 +PC: 0 +wid: 0 +rd: -1 rs1: -1 rs2: -1 +is_lw: 0 +is_sw: 0 +fetch_stall_cycles: 0 +mem_stall_cycles: 0 +stall_warp: 0 +wspawn: 0 +stalled: 0 +********************************** Decode ********************************* +valid: 0 +PC: 0 +wid: 0 +rd: -1 rs1: -1 rs2: -1 +is_lw: 0 +is_sw: 0 +fetch_stall_cycles: 0 +mem_stall_cycles: 0 +stall_warp: 0 +wspawn: 0 +stalled: 0 +********************************** Fetch ********************************* +valid: 1 +PC: 80000a20 +wid: 0 +rd: 6 rs1: 0 rs2: -1 +is_lw: 0 +is_sw: 0 +fetch_stall_cycles: 0 +mem_stall_cycles: 0 +stall_warp: 0 +wspawn: 0 +stalled: 0 + + + +------------------------------------------------------ +CYCLE: 137 +Stalled Warps: +0 0 0 0 0 0 0 0 + +********************************** Writeback ********************************* +valid: 0 +PC: 0 +wid: 0 +rd: -1 rs1: -1 rs2: -1 +is_lw: 0 +is_sw: 0 +fetch_stall_cycles: 0 +mem_stall_cycles: 0 +stall_warp: 0 +wspawn: 0 +stalled: 0 +********************************** LSU ********************************* +valid: 0 +PC: 0 +wid: 0 +rd: -1 rs1: -1 rs2: -1 +is_lw: 0 +is_sw: 0 +fetch_stall_cycles: 0 +mem_stall_cycles: 0 +stall_warp: 0 +wspawn: 0 +stalled: 0 +********************************** execute_unit ********************************* +valid: 0 +PC: 0 +wid: 0 +rd: -1 rs1: -1 rs2: -1 +is_lw: 0 +is_sw: 0 +fetch_stall_cycles: 0 +mem_stall_cycles: 0 +stall_warp: 0 +wspawn: 0 +stalled: 0 +********************************** scheduler ********************************* +valid: 0 +PC: 0 +wid: 0 +rd: -1 rs1: -1 rs2: -1 +is_lw: 0 +is_sw: 0 +fetch_stall_cycles: 0 +mem_stall_cycles: 0 +stall_warp: 0 +wspawn: 0 +stalled: 0 +********************************** Decode ********************************* +valid: 1 +PC: 80000a20 +wid: 0 +rd: 6 rs1: 0 rs2: -1 +is_lw: 0 +is_sw: 0 +fetch_stall_cycles: 0 +mem_stall_cycles: 0 +stall_warp: 0 +wspawn: 0 +stalled: 0 +DEBUG ../core.cpp:386: Core step stepping warp 0[1] +DEBUG ../core.cpp:683: in step pc=0x80000a24 +help: in PC: 80000a24 +CUrrent CODE: 50713 +DEBUG ../core.cpp:703: Fetched at 0x80000a24 +DEBUG ../core.cpp:704: 0x80000a24: i_type; +DEBUG ../instruction.cpp:350: Begin instruction execute. +DEBUG ../instruction.cpp:2117: End instruction execute. +DEBUG ../core.cpp:717: Register state: + %r 0: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r 1: 80000030 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r 2: 6ffff000 6fffec04 6fffe808 6fffe40c 00000000 00000000 00000000 00000000 (0) + %r 3: 80001808 80001808 80001808 80001808 00000000 00000000 00000000 00000000 (0) + %r 4: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r 5: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r 6: 0000000f 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r 7: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r 8: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r 9: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r10: 80001440 00000001 00000001 00000001 00000000 00000000 00000000 00000000 (0) + %r11: 00000000 00000400 00000800 00000c00 00000000 00000000 00000000 00000000 (0) + %r12: 00000004 00000004 00000008 0000000c 00000000 00000000 00000000 00000000 (0) + %r13: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r14: 80001440 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r15: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r16: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r17: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r18: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r19: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r20: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r21: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r22: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r23: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r24: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r25: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r26: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r27: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r28: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r29: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r30: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r31: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) +DEBUG ../core.cpp:726: Thread mask: + 1 0 0 0 0 0 0 0 + + +DEBUG ../core.cpp:388: Now 1 active threads in 0 +********************************** Fetch ********************************* +valid: 1 +PC: 80000a24 +wid: 0 +rd: 14 rs1: 10 rs2: -1 +is_lw: 0 +is_sw: 0 +fetch_stall_cycles: 0 +mem_stall_cycles: 0 +stall_warp: 0 +wspawn: 0 +stalled: 0 + + + +------------------------------------------------------ +CYCLE: 138 +Stalled Warps: +0 0 0 0 0 0 0 0 + +********************************** Writeback ********************************* +valid: 0 +PC: 0 +wid: 0 +rd: -1 rs1: -1 rs2: -1 +is_lw: 0 +is_sw: 0 +fetch_stall_cycles: 0 +mem_stall_cycles: 0 +stall_warp: 0 +wspawn: 0 +stalled: 0 +********************************** LSU ********************************* +valid: 0 +PC: 0 +wid: 0 +rd: -1 rs1: -1 rs2: -1 +is_lw: 0 +is_sw: 0 +fetch_stall_cycles: 0 +mem_stall_cycles: 0 +stall_warp: 0 +wspawn: 0 +stalled: 0 +********************************** execute_unit ********************************* +valid: 0 +PC: 0 +wid: 0 +rd: -1 rs1: -1 rs2: -1 +is_lw: 0 +is_sw: 0 +fetch_stall_cycles: 0 +mem_stall_cycles: 0 +stall_warp: 0 +wspawn: 0 +stalled: 0 +********************************** scheduler ********************************* +valid: 1 +PC: 80000a20 +wid: 0 +rd: 6 rs1: 0 rs2: -1 +is_lw: 0 +is_sw: 0 +fetch_stall_cycles: 0 +mem_stall_cycles: 0 +stall_warp: 0 +wspawn: 0 +stalled: 0 +********************************** Decode ********************************* +valid: 1 +PC: 80000a24 +wid: 0 +rd: 14 rs1: 10 rs2: -1 +is_lw: 0 +is_sw: 0 +fetch_stall_cycles: 0 +mem_stall_cycles: 0 +stall_warp: 0 +wspawn: 0 +stalled: 0 +DEBUG ../core.cpp:386: Core step stepping warp 0[1] +DEBUG ../core.cpp:683: in step pc=0x80000a28 +help: in PC: 80000a28 +CUrrent CODE: 2c37e63 +DEBUG ../core.cpp:703: Fetched at 0x80000a28 +DEBUG ../core.cpp:704: 0x80000a28: branch; +DEBUG ../instruction.cpp:350: Begin instruction execute. +DEBUG ../instruction.cpp:2117: End instruction execute. +Next PC: 80000a64 +DEBUG ../core.cpp:717: Register state: + %r 0: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r 1: 80000030 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r 2: 6ffff000 6fffec04 6fffe808 6fffe40c 00000000 00000000 00000000 00000000 (0) + %r 3: 80001808 80001808 80001808 80001808 00000000 00000000 00000000 00000000 (0) + %r 4: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r 5: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r 6: 0000000f 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r 7: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r 8: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r 9: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r10: 80001440 00000001 00000001 00000001 00000000 00000000 00000000 00000000 (0) + %r11: 00000000 00000400 00000800 00000c00 00000000 00000000 00000000 00000000 (0) + %r12: 00000004 00000004 00000008 0000000c 00000000 00000000 00000000 00000000 (0) + %r13: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r14: 80001440 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r15: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r16: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r17: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r18: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r19: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r20: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r21: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r22: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r23: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r24: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r25: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r26: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r27: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r28: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r29: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r30: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r31: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) +DEBUG ../core.cpp:726: Thread mask: + 1 0 0 0 0 0 0 0 + + +DEBUG ../core.cpp:388: Now 1 active threads in 0 +********************************** Fetch ********************************* +valid: 1 +PC: 80000a28 +wid: 0 +rd: -1 rs1: 6 rs2: 12 +is_lw: 0 +is_sw: 0 +fetch_stall_cycles: 0 +mem_stall_cycles: 0 +stall_warp: 1 +wspawn: 0 +stalled: 0 + + + +------------------------------------------------------ +CYCLE: 139 +Stalled Warps: +1 0 0 0 0 0 0 0 + +********************************** Writeback ********************************* +valid: 0 +PC: 0 +wid: 1 +rd: -1 rs1: -1 rs2: -1 +is_lw: 0 +is_sw: 0 +fetch_stall_cycles: 0 +mem_stall_cycles: 0 +stall_warp: 0 +wspawn: 0 +stalled: 0 +********************************** LSU ********************************* +valid: 0 +PC: 0 +wid: 0 +rd: -1 rs1: -1 rs2: -1 +is_lw: 0 +is_sw: 0 +fetch_stall_cycles: 0 +mem_stall_cycles: 0 +stall_warp: 0 +wspawn: 0 +stalled: 0 +********************************** execute_unit ********************************* +valid: 1 +PC: 80000a20 +wid: 0 +rd: 6 rs1: 0 rs2: -1 +is_lw: 0 +is_sw: 0 +fetch_stall_cycles: 0 +mem_stall_cycles: 0 +stall_warp: 0 +wspawn: 0 +stalled: 0 +********************************** scheduler ********************************* +valid: 1 +PC: 80000a24 +wid: 0 +rd: 14 rs1: 10 rs2: -1 +is_lw: 0 +is_sw: 0 +fetch_stall_cycles: 0 +mem_stall_cycles: 0 +stall_warp: 0 +wspawn: 0 +stalled: 0 +********************************** Decode ********************************* +valid: 1 +PC: 80000a28 +wid: 0 +rd: -1 rs1: 6 rs2: 12 +is_lw: 0 +is_sw: 0 +fetch_stall_cycles: 0 +mem_stall_cycles: 0 +stall_warp: 1 +wspawn: 0 +stalled: 0 +********************************** Fetch ********************************* +valid: 0 +PC: 0 +wid: 1 +rd: -1 rs1: -1 rs2: -1 +is_lw: 0 +is_sw: 0 +fetch_stall_cycles: 0 +mem_stall_cycles: 0 +stall_warp: 0 +wspawn: 0 +stalled: 0 + + + +------------------------------------------------------ +CYCLE: 140 +Stalled Warps: +1 0 0 0 0 0 0 0 + +********************************** Writeback ********************************* +valid: 1 +PC: 80000a20 +wid: 0 +rd: 6 rs1: 0 rs2: -1 +is_lw: 0 +is_sw: 0 +fetch_stall_cycles: 0 +mem_stall_cycles: 0 +stall_warp: 0 +wspawn: 0 +stalled: 0 +********************************** LSU ********************************* +valid: 0 +PC: 0 +wid: 0 +rd: -1 rs1: -1 rs2: -1 +is_lw: 0 +is_sw: 0 +fetch_stall_cycles: 0 +mem_stall_cycles: 0 +stall_warp: 0 +wspawn: 0 +stalled: 0 +********************************** execute_unit ********************************* +valid: 1 +PC: 80000a24 +wid: 0 +rd: 14 rs1: 10 rs2: -1 +is_lw: 0 +is_sw: 0 +fetch_stall_cycles: 0 +mem_stall_cycles: 0 +stall_warp: 0 +wspawn: 0 +stalled: 0 +********************************** scheduler ********************************* +valid: 1 +PC: 80000a28 +wid: 0 +rd: -1 rs1: 6 rs2: 12 +is_lw: 0 +is_sw: 0 +fetch_stall_cycles: 0 +mem_stall_cycles: 0 +stall_warp: 1 +wspawn: 0 +stalled: 0 +********************************** Decode ********************************* +valid: 0 +PC: 0 +wid: 1 +rd: -1 rs1: -1 rs2: -1 +is_lw: 0 +is_sw: 0 +fetch_stall_cycles: 0 +mem_stall_cycles: 0 +stall_warp: 0 +wspawn: 0 +stalled: 0 +********************************** Fetch ********************************* +valid: 0 +PC: 0 +wid: 2 +rd: -1 rs1: -1 rs2: -1 +is_lw: 0 +is_sw: 0 +fetch_stall_cycles: 0 +mem_stall_cycles: 0 +stall_warp: 0 +wspawn: 0 +stalled: 0 + + + +------------------------------------------------------ +CYCLE: 141 +Stalled Warps: +1 0 0 0 0 0 0 0 + +********************************** Writeback ********************************* +valid: 1 +PC: 80000a24 +wid: 0 +rd: 14 rs1: 10 rs2: -1 +is_lw: 0 +is_sw: 0 +fetch_stall_cycles: 0 +mem_stall_cycles: 0 +stall_warp: 0 +wspawn: 0 +stalled: 0 +********************************** LSU ********************************* +valid: 0 +PC: 0 +wid: 0 +rd: -1 rs1: -1 rs2: -1 +is_lw: 0 +is_sw: 0 +fetch_stall_cycles: 0 +mem_stall_cycles: 0 +stall_warp: 0 +wspawn: 0 +stalled: 0 +********************************** execute_unit ********************************* +valid: 1 +PC: 80000a28 +wid: 0 +rd: -1 rs1: 6 rs2: 12 +is_lw: 0 +is_sw: 0 +fetch_stall_cycles: 0 +mem_stall_cycles: 0 +stall_warp: 1 +wspawn: 0 +stalled: 0 +********************************** scheduler ********************************* +valid: 0 +PC: 0 +wid: 1 +rd: -1 rs1: -1 rs2: -1 +is_lw: 0 +is_sw: 0 +fetch_stall_cycles: 0 +mem_stall_cycles: 0 +stall_warp: 0 +wspawn: 0 +stalled: 0 +********************************** Decode ********************************* +valid: 0 +PC: 0 +wid: 2 +rd: -1 rs1: -1 rs2: -1 +is_lw: 0 +is_sw: 0 +fetch_stall_cycles: 0 +mem_stall_cycles: 0 +stall_warp: 0 +wspawn: 0 +stalled: 0 +********************************** Fetch ********************************* +valid: 0 +PC: 0 +wid: 3 +rd: -1 rs1: -1 rs2: -1 +is_lw: 0 +is_sw: 0 +fetch_stall_cycles: 0 +mem_stall_cycles: 0 +stall_warp: 0 +wspawn: 0 +stalled: 0 + + + +------------------------------------------------------ +CYCLE: 142 +Stalled Warps: +1 0 0 0 0 0 0 0 + +********************************** Writeback ********************************* +valid: 1 +PC: 80000a28 +wid: 0 +rd: -1 rs1: 6 rs2: 12 +is_lw: 0 +is_sw: 0 +fetch_stall_cycles: 0 +mem_stall_cycles: 0 +stall_warp: 1 +wspawn: 0 +stalled: 0 +********************************** LSU ********************************* +valid: 0 +PC: 0 +wid: 0 +rd: -1 rs1: -1 rs2: -1 +is_lw: 0 +is_sw: 0 +fetch_stall_cycles: 0 +mem_stall_cycles: 0 +stall_warp: 0 +wspawn: 0 +stalled: 0 +********************************** execute_unit ********************************* +valid: 0 +PC: 0 +wid: 1 +rd: -1 rs1: -1 rs2: -1 +is_lw: 0 +is_sw: 0 +fetch_stall_cycles: 0 +mem_stall_cycles: 0 +stall_warp: 0 +wspawn: 0 +stalled: 0 +********************************** scheduler ********************************* +valid: 0 +PC: 0 +wid: 2 +rd: -1 rs1: -1 rs2: -1 +is_lw: 0 +is_sw: 0 +fetch_stall_cycles: 0 +mem_stall_cycles: 0 +stall_warp: 0 +wspawn: 0 +stalled: 0 +********************************** Decode ********************************* +valid: 0 +PC: 0 +wid: 3 +rd: -1 rs1: -1 rs2: -1 +is_lw: 0 +is_sw: 0 +fetch_stall_cycles: 0 +mem_stall_cycles: 0 +stall_warp: 0 +wspawn: 0 +stalled: 0 +********************************** Fetch ********************************* +valid: 0 +PC: 0 +wid: 4 +rd: -1 rs1: -1 rs2: -1 +is_lw: 0 +is_sw: 0 +fetch_stall_cycles: 0 +mem_stall_cycles: 0 +stall_warp: 0 +wspawn: 0 +stalled: 0 + + + +------------------------------------------------------ +CYCLE: 143 +Stalled Warps: +1 0 0 0 0 0 0 0 + +********************************** Writeback ********************************* +valid: 0 +PC: 0 +wid: 5 +rd: -1 rs1: -1 rs2: -1 +is_lw: 0 +is_sw: 0 +fetch_stall_cycles: 0 +mem_stall_cycles: 0 +stall_warp: 0 +wspawn: 0 +stalled: 0 +********************************** LSU ********************************* +valid: 0 +PC: 0 +wid: 0 +rd: -1 rs1: -1 rs2: -1 +is_lw: 0 +is_sw: 0 +fetch_stall_cycles: 0 +mem_stall_cycles: 0 +stall_warp: 0 +wspawn: 0 +stalled: 0 +********************************** execute_unit ********************************* +valid: 0 +PC: 0 +wid: 2 +rd: -1 rs1: -1 rs2: -1 +is_lw: 0 +is_sw: 0 +fetch_stall_cycles: 0 +mem_stall_cycles: 0 +stall_warp: 0 +wspawn: 0 +stalled: 0 +********************************** scheduler ********************************* +valid: 0 +PC: 0 +wid: 3 +rd: -1 rs1: -1 rs2: -1 +is_lw: 0 +is_sw: 0 +fetch_stall_cycles: 0 +mem_stall_cycles: 0 +stall_warp: 0 +wspawn: 0 +stalled: 0 +********************************** Decode ********************************* +valid: 0 +PC: 0 +wid: 4 +rd: -1 rs1: -1 rs2: -1 +is_lw: 0 +is_sw: 0 +fetch_stall_cycles: 0 +mem_stall_cycles: 0 +stall_warp: 0 +wspawn: 0 +stalled: 0 +********************************** Fetch ********************************* +valid: 0 +PC: 0 +wid: 5 +rd: -1 rs1: -1 rs2: -1 +is_lw: 0 +is_sw: 0 +fetch_stall_cycles: 0 +mem_stall_cycles: 0 +stall_warp: 0 +wspawn: 0 +stalled: 0 +Warp ID 0 is running + + + +------------------------------------------------------ +CYCLE: 144 +Stalled Warps: +0 0 0 0 0 0 0 0 + +********************************** Writeback ********************************* +valid: 0 +PC: 0 +wid: 0 +rd: -1 rs1: -1 rs2: -1 +is_lw: 0 +is_sw: 0 +fetch_stall_cycles: 0 +mem_stall_cycles: 0 +stall_warp: 0 +wspawn: 0 +stalled: 0 +********************************** LSU ********************************* +valid: 0 +PC: 0 +wid: 0 +rd: -1 rs1: -1 rs2: -1 +is_lw: 0 +is_sw: 0 +fetch_stall_cycles: 0 +mem_stall_cycles: 0 +stall_warp: 0 +wspawn: 0 +stalled: 0 +********************************** execute_unit ********************************* +valid: 0 +PC: 0 +wid: 3 +rd: -1 rs1: -1 rs2: -1 +is_lw: 0 +is_sw: 0 +fetch_stall_cycles: 0 +mem_stall_cycles: 0 +stall_warp: 0 +wspawn: 0 +stalled: 0 +********************************** scheduler ********************************* +valid: 0 +PC: 0 +wid: 4 +rd: -1 rs1: -1 rs2: -1 +is_lw: 0 +is_sw: 0 +fetch_stall_cycles: 0 +mem_stall_cycles: 0 +stall_warp: 0 +wspawn: 0 +stalled: 0 +********************************** Decode ********************************* +valid: 0 +PC: 0 +wid: 5 +rd: -1 rs1: -1 rs2: -1 +is_lw: 0 +is_sw: 0 +fetch_stall_cycles: 0 +mem_stall_cycles: 0 +stall_warp: 0 +wspawn: 0 +stalled: 0 +DEBUG ../core.cpp:386: Core step stepping warp 0[1] +DEBUG ../core.cpp:683: in step pc=0x80000a64 +help: in PC: 80000a64 +CUrrent CODE: 40c306b3 +DEBUG ../core.cpp:703: Fetched at 0x80000a64 +DEBUG ../core.cpp:704: 0x80000a64: r_type; +DEBUG ../instruction.cpp:350: Begin instruction execute. +DEBUG ../instruction.cpp:2117: End instruction execute. +DEBUG ../core.cpp:717: Register state: + %r 0: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r 1: 80000030 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r 2: 6ffff000 6fffec04 6fffe808 6fffe40c 00000000 00000000 00000000 00000000 (0) + %r 3: 80001808 80001808 80001808 80001808 00000000 00000000 00000000 00000000 (0) + %r 4: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r 5: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r 6: 0000000f 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r 7: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r 8: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r 9: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r10: 80001440 00000001 00000001 00000001 00000000 00000000 00000000 00000000 (0) + %r11: 00000000 00000400 00000800 00000c00 00000000 00000000 00000000 00000000 (0) + %r12: 00000004 00000004 00000008 0000000c 00000000 00000000 00000000 00000000 (0) + %r13: 0000000b 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r14: 80001440 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r15: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r16: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r17: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r18: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r19: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r20: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r21: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r22: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r23: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r24: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r25: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r26: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r27: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r28: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r29: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r30: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r31: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) +DEBUG ../core.cpp:726: Thread mask: + 1 0 0 0 0 0 0 0 + + +DEBUG ../core.cpp:388: Now 1 active threads in 0 +********************************** Fetch ********************************* +valid: 1 +PC: 80000a64 +wid: 0 +rd: 13 rs1: 6 rs2: 12 +is_lw: 0 +is_sw: 0 +fetch_stall_cycles: 3 +mem_stall_cycles: 0 +stall_warp: 0 +wspawn: 0 +stalled: 0 + + + +------------------------------------------------------ +CYCLE: 145 +Stalled Warps: +0 0 0 0 0 0 0 0 + +********************************** Writeback ********************************* +valid: 0 +PC: 0 +wid: 0 +rd: -1 rs1: -1 rs2: -1 +is_lw: 0 +is_sw: 0 +fetch_stall_cycles: 0 +mem_stall_cycles: 0 +stall_warp: 0 +wspawn: 0 +stalled: 0 +********************************** LSU ********************************* +valid: 0 +PC: 0 +wid: 0 +rd: -1 rs1: -1 rs2: -1 +is_lw: 0 +is_sw: 0 +fetch_stall_cycles: 0 +mem_stall_cycles: 0 +stall_warp: 0 +wspawn: 0 +stalled: 0 +********************************** execute_unit ********************************* +valid: 0 +PC: 0 +wid: 4 +rd: -1 rs1: -1 rs2: -1 +is_lw: 0 +is_sw: 0 +fetch_stall_cycles: 0 +mem_stall_cycles: 0 +stall_warp: 0 +wspawn: 0 +stalled: 0 +********************************** scheduler ********************************* +valid: 0 +PC: 0 +wid: 5 +rd: -1 rs1: -1 rs2: -1 +is_lw: 0 +is_sw: 0 +fetch_stall_cycles: 0 +mem_stall_cycles: 0 +stall_warp: 0 +wspawn: 0 +stalled: 0 +********************************** Decode ********************************* +valid: 0 +PC: 0 +wid: 0 +rd: -1 rs1: -1 rs2: -1 +is_lw: 0 +is_sw: 0 +fetch_stall_cycles: 0 +mem_stall_cycles: 0 +stall_warp: 0 +wspawn: 0 +stalled: 0 +********************************** Fetch ********************************* +valid: 1 +PC: 80000a64 +wid: 0 +rd: 13 rs1: 6 rs2: 12 +is_lw: 0 +is_sw: 0 +fetch_stall_cycles: 2 +mem_stall_cycles: 0 +stall_warp: 0 +wspawn: 0 +stalled: 0 + + + +------------------------------------------------------ +CYCLE: 146 +Stalled Warps: +0 0 0 0 0 0 0 0 + +********************************** Writeback ********************************* +valid: 0 +PC: 0 +wid: 0 +rd: -1 rs1: -1 rs2: -1 +is_lw: 0 +is_sw: 0 +fetch_stall_cycles: 0 +mem_stall_cycles: 0 +stall_warp: 0 +wspawn: 0 +stalled: 0 +********************************** LSU ********************************* +valid: 0 +PC: 0 +wid: 0 +rd: -1 rs1: -1 rs2: -1 +is_lw: 0 +is_sw: 0 +fetch_stall_cycles: 0 +mem_stall_cycles: 0 +stall_warp: 0 +wspawn: 0 +stalled: 0 +********************************** execute_unit ********************************* +valid: 0 +PC: 0 +wid: 5 +rd: -1 rs1: -1 rs2: -1 +is_lw: 0 +is_sw: 0 +fetch_stall_cycles: 0 +mem_stall_cycles: 0 +stall_warp: 0 +wspawn: 0 +stalled: 0 +********************************** scheduler ********************************* +valid: 0 +PC: 0 +wid: 0 +rd: -1 rs1: -1 rs2: -1 +is_lw: 0 +is_sw: 0 +fetch_stall_cycles: 0 +mem_stall_cycles: 0 +stall_warp: 0 +wspawn: 0 +stalled: 0 +********************************** Decode ********************************* +valid: 0 +PC: 0 +wid: 0 +rd: -1 rs1: -1 rs2: -1 +is_lw: 0 +is_sw: 0 +fetch_stall_cycles: 0 +mem_stall_cycles: 0 +stall_warp: 0 +wspawn: 0 +stalled: 0 +********************************** Fetch ********************************* +valid: 1 +PC: 80000a64 +wid: 0 +rd: 13 rs1: 6 rs2: 12 +is_lw: 0 +is_sw: 0 +fetch_stall_cycles: 1 +mem_stall_cycles: 0 +stall_warp: 0 +wspawn: 0 +stalled: 0 + + + +------------------------------------------------------ +CYCLE: 147 +Stalled Warps: +0 0 0 0 0 0 0 0 + +********************************** Writeback ********************************* +valid: 0 +PC: 0 +wid: 0 +rd: -1 rs1: -1 rs2: -1 +is_lw: 0 +is_sw: 0 +fetch_stall_cycles: 0 +mem_stall_cycles: 0 +stall_warp: 0 +wspawn: 0 +stalled: 0 +********************************** LSU ********************************* +valid: 0 +PC: 0 +wid: 0 +rd: -1 rs1: -1 rs2: -1 +is_lw: 0 +is_sw: 0 +fetch_stall_cycles: 0 +mem_stall_cycles: 0 +stall_warp: 0 +wspawn: 0 +stalled: 0 +********************************** execute_unit ********************************* +valid: 0 +PC: 0 +wid: 0 +rd: -1 rs1: -1 rs2: -1 +is_lw: 0 +is_sw: 0 +fetch_stall_cycles: 0 +mem_stall_cycles: 0 +stall_warp: 0 +wspawn: 0 +stalled: 0 +********************************** scheduler ********************************* +valid: 0 +PC: 0 +wid: 0 +rd: -1 rs1: -1 rs2: -1 +is_lw: 0 +is_sw: 0 +fetch_stall_cycles: 0 +mem_stall_cycles: 0 +stall_warp: 0 +wspawn: 0 +stalled: 0 +********************************** Decode ********************************* +valid: 0 +PC: 0 +wid: 0 +rd: -1 rs1: -1 rs2: -1 +is_lw: 0 +is_sw: 0 +fetch_stall_cycles: 0 +mem_stall_cycles: 0 +stall_warp: 0 +wspawn: 0 +stalled: 0 +********************************** Fetch ********************************* +valid: 1 +PC: 80000a64 +wid: 0 +rd: 13 rs1: 6 rs2: 12 +is_lw: 0 +is_sw: 0 +fetch_stall_cycles: 0 +mem_stall_cycles: 0 +stall_warp: 0 +wspawn: 0 +stalled: 0 + + + +------------------------------------------------------ +CYCLE: 148 +Stalled Warps: +0 0 0 0 0 0 0 0 + +********************************** Writeback ********************************* +valid: 0 +PC: 0 +wid: 0 +rd: -1 rs1: -1 rs2: -1 +is_lw: 0 +is_sw: 0 +fetch_stall_cycles: 0 +mem_stall_cycles: 0 +stall_warp: 0 +wspawn: 0 +stalled: 0 +********************************** LSU ********************************* +valid: 0 +PC: 0 +wid: 0 +rd: -1 rs1: -1 rs2: -1 +is_lw: 0 +is_sw: 0 +fetch_stall_cycles: 0 +mem_stall_cycles: 0 +stall_warp: 0 +wspawn: 0 +stalled: 0 +********************************** execute_unit ********************************* +valid: 0 +PC: 0 +wid: 0 +rd: -1 rs1: -1 rs2: -1 +is_lw: 0 +is_sw: 0 +fetch_stall_cycles: 0 +mem_stall_cycles: 0 +stall_warp: 0 +wspawn: 0 +stalled: 0 +********************************** scheduler ********************************* +valid: 0 +PC: 0 +wid: 0 +rd: -1 rs1: -1 rs2: -1 +is_lw: 0 +is_sw: 0 +fetch_stall_cycles: 0 +mem_stall_cycles: 0 +stall_warp: 0 +wspawn: 0 +stalled: 0 +********************************** Decode ********************************* +valid: 1 +PC: 80000a64 +wid: 0 +rd: 13 rs1: 6 rs2: 12 +is_lw: 0 +is_sw: 0 +fetch_stall_cycles: 0 +mem_stall_cycles: 0 +stall_warp: 0 +wspawn: 0 +stalled: 0 +DEBUG ../core.cpp:386: Core step stepping warp 0[1] +DEBUG ../core.cpp:683: in step pc=0x80000a68 +help: in PC: 80000a68 +CUrrent CODE: 269693 +DEBUG ../core.cpp:703: Fetched at 0x80000a68 +DEBUG ../core.cpp:704: 0x80000a68: i_type; +DEBUG ../instruction.cpp:350: Begin instruction execute. +DEBUG ../instruction.cpp:2117: End instruction execute. +DEBUG ../core.cpp:717: Register state: + %r 0: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r 1: 80000030 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r 2: 6ffff000 6fffec04 6fffe808 6fffe40c 00000000 00000000 00000000 00000000 (0) + %r 3: 80001808 80001808 80001808 80001808 00000000 00000000 00000000 00000000 (0) + %r 4: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r 5: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r 6: 0000000f 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r 7: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r 8: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r 9: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r10: 80001440 00000001 00000001 00000001 00000000 00000000 00000000 00000000 (0) + %r11: 00000000 00000400 00000800 00000c00 00000000 00000000 00000000 00000000 (0) + %r12: 00000004 00000004 00000008 0000000c 00000000 00000000 00000000 00000000 (0) + %r13: 0000002c 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r14: 80001440 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r15: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r16: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r17: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r18: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r19: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r20: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r21: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r22: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r23: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r24: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r25: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r26: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r27: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r28: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r29: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r30: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r31: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) +DEBUG ../core.cpp:726: Thread mask: + 1 0 0 0 0 0 0 0 + + +DEBUG ../core.cpp:388: Now 1 active threads in 0 +********************************** Fetch ********************************* +valid: 1 +PC: 80000a68 +wid: 0 +rd: 13 rs1: 13 rs2: -1 +is_lw: 0 +is_sw: 0 +fetch_stall_cycles: 0 +mem_stall_cycles: 0 +stall_warp: 0 +wspawn: 0 +stalled: 0 + + + +------------------------------------------------------ +CYCLE: 149 +Stalled Warps: +0 0 0 0 0 0 0 0 + +********************************** Writeback ********************************* +valid: 0 +PC: 0 +wid: 0 +rd: -1 rs1: -1 rs2: -1 +is_lw: 0 +is_sw: 0 +fetch_stall_cycles: 0 +mem_stall_cycles: 0 +stall_warp: 0 +wspawn: 0 +stalled: 0 +********************************** LSU ********************************* +valid: 0 +PC: 0 +wid: 0 +rd: -1 rs1: -1 rs2: -1 +is_lw: 0 +is_sw: 0 +fetch_stall_cycles: 0 +mem_stall_cycles: 0 +stall_warp: 0 +wspawn: 0 +stalled: 0 +********************************** execute_unit ********************************* +valid: 0 +PC: 0 +wid: 0 +rd: -1 rs1: -1 rs2: -1 +is_lw: 0 +is_sw: 0 +fetch_stall_cycles: 0 +mem_stall_cycles: 0 +stall_warp: 0 +wspawn: 0 +stalled: 0 +********************************** scheduler ********************************* +valid: 1 +PC: 80000a64 +wid: 0 +rd: 13 rs1: 6 rs2: 12 +is_lw: 0 +is_sw: 0 +fetch_stall_cycles: 0 +mem_stall_cycles: 0 +stall_warp: 0 +wspawn: 0 +stalled: 0 +********************************** Decode ********************************* +valid: 1 +PC: 80000a68 +wid: 0 +rd: 13 rs1: 13 rs2: -1 +is_lw: 0 +is_sw: 0 +fetch_stall_cycles: 0 +mem_stall_cycles: 0 +stall_warp: 0 +wspawn: 0 +stalled: 0 +DEBUG ../core.cpp:386: Core step stepping warp 0[1] +DEBUG ../core.cpp:683: in step pc=0x80000a6c +help: in PC: 80000a6c +CUrrent CODE: 297 +DEBUG ../core.cpp:703: Fetched at 0x80000a6c +DEBUG ../core.cpp:704: 0x80000a6c: auipc; +DEBUG ../instruction.cpp:350: Begin instruction execute. +DEBUG ../instruction.cpp:2117: End instruction execute. +DEBUG ../core.cpp:717: Register state: + %r 0: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r 1: 80000030 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r 2: 6ffff000 6fffec04 6fffe808 6fffe40c 00000000 00000000 00000000 00000000 (0) + %r 3: 80001808 80001808 80001808 80001808 00000000 00000000 00000000 00000000 (0) + %r 4: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r 5: 80000a6c 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r 6: 0000000f 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r 7: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r 8: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r 9: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r10: 80001440 00000001 00000001 00000001 00000000 00000000 00000000 00000000 (0) + %r11: 00000000 00000400 00000800 00000c00 00000000 00000000 00000000 00000000 (0) + %r12: 00000004 00000004 00000008 0000000c 00000000 00000000 00000000 00000000 (0) + %r13: 0000002c 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r14: 80001440 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r15: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r16: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r17: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r18: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r19: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r20: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r21: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r22: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r23: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r24: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r25: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r26: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r27: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r28: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r29: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r30: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r31: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) +DEBUG ../core.cpp:726: Thread mask: + 1 0 0 0 0 0 0 0 + + +DEBUG ../core.cpp:388: Now 1 active threads in 0 +********************************** Fetch ********************************* +valid: 1 +PC: 80000a6c +wid: 0 +rd: 5 rs1: -1 rs2: -1 +is_lw: 0 +is_sw: 0 +fetch_stall_cycles: 0 +mem_stall_cycles: 0 +stall_warp: 0 +wspawn: 0 +stalled: 0 + + + +------------------------------------------------------ +CYCLE: 150 +Stalled Warps: +0 0 0 0 0 0 0 0 + +********************************** Writeback ********************************* +valid: 0 +PC: 0 +wid: 0 +rd: -1 rs1: -1 rs2: -1 +is_lw: 0 +is_sw: 0 +fetch_stall_cycles: 0 +mem_stall_cycles: 0 +stall_warp: 0 +wspawn: 0 +stalled: 0 +********************************** LSU ********************************* +valid: 0 +PC: 0 +wid: 0 +rd: -1 rs1: -1 rs2: -1 +is_lw: 0 +is_sw: 0 +fetch_stall_cycles: 0 +mem_stall_cycles: 0 +stall_warp: 0 +wspawn: 0 +stalled: 0 +********************************** execute_unit ********************************* +valid: 1 +PC: 80000a64 +wid: 0 +rd: 13 rs1: 6 rs2: 12 +is_lw: 0 +is_sw: 0 +fetch_stall_cycles: 0 +mem_stall_cycles: 0 +stall_warp: 0 +wspawn: 0 +stalled: 0 +********************************** scheduler ********************************* +valid: 1 +PC: 80000a68 +wid: 0 +rd: 13 rs1: 13 rs2: -1 +is_lw: 0 +is_sw: 0 +fetch_stall_cycles: 0 +mem_stall_cycles: 0 +stall_warp: 0 +wspawn: 0 +stalled: 0 +********************************** Decode ********************************* +valid: 1 +PC: 80000a6c +wid: 0 +rd: 5 rs1: -1 rs2: -1 +is_lw: 0 +is_sw: 0 +fetch_stall_cycles: 0 +mem_stall_cycles: 0 +stall_warp: 0 +wspawn: 0 +stalled: 0 +DEBUG ../core.cpp:386: Core step stepping warp 0[1] +DEBUG ../core.cpp:683: in step pc=0x80000a70 +help: in PC: 80000a70 +CUrrent CODE: 5686b3 +DEBUG ../core.cpp:703: Fetched at 0x80000a70 +DEBUG ../core.cpp:704: 0x80000a70: r_type; +DEBUG ../instruction.cpp:350: Begin instruction execute. +DEBUG ../instruction.cpp:2117: End instruction execute. +DEBUG ../core.cpp:717: Register state: + %r 0: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r 1: 80000030 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r 2: 6ffff000 6fffec04 6fffe808 6fffe40c 00000000 00000000 00000000 00000000 (0) + %r 3: 80001808 80001808 80001808 80001808 00000000 00000000 00000000 00000000 (0) + %r 4: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r 5: 80000a6c 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r 6: 0000000f 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r 7: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r 8: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r 9: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r10: 80001440 00000001 00000001 00000001 00000000 00000000 00000000 00000000 (0) + %r11: 00000000 00000400 00000800 00000c00 00000000 00000000 00000000 00000000 (0) + %r12: 00000004 00000004 00000008 0000000c 00000000 00000000 00000000 00000000 (0) + %r13: 80000a98 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r14: 80001440 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r15: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r16: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r17: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r18: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r19: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r20: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r21: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r22: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r23: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r24: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r25: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r26: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r27: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r28: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r29: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r30: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r31: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) +DEBUG ../core.cpp:726: Thread mask: + 1 0 0 0 0 0 0 0 + + +DEBUG ../core.cpp:388: Now 1 active threads in 0 +********************************** Fetch ********************************* +valid: 1 +PC: 80000a70 +wid: 0 +rd: 13 rs1: 13 rs2: 5 +is_lw: 0 +is_sw: 0 +fetch_stall_cycles: 3 +mem_stall_cycles: 0 +stall_warp: 0 +wspawn: 0 +stalled: 0 + + + +------------------------------------------------------ +CYCLE: 151 +Stalled Warps: +0 0 0 0 0 0 0 0 + +********************************** Writeback ********************************* +valid: 1 +PC: 80000a64 +wid: 0 +rd: 13 rs1: 6 rs2: 12 +is_lw: 0 +is_sw: 0 +fetch_stall_cycles: 0 +mem_stall_cycles: 0 +stall_warp: 0 +wspawn: 0 +stalled: 0 +********************************** LSU ********************************* +valid: 0 +PC: 0 +wid: 0 +rd: -1 rs1: -1 rs2: -1 +is_lw: 0 +is_sw: 0 +fetch_stall_cycles: 0 +mem_stall_cycles: 0 +stall_warp: 0 +wspawn: 0 +stalled: 0 +&&&&&&&&&&&&&&&&&&&&&&&& EXECUTE SRCS NOT READY +********************************** execute_unit ********************************* +valid: 0 +PC: 0 +wid: 0 +rd: -1 rs1: -1 rs2: -1 +is_lw: 0 +is_sw: 0 +fetch_stall_cycles: 0 +mem_stall_cycles: 0 +stall_warp: 0 +wspawn: 0 +stalled: 0 +********************************** scheduler ********************************* +valid: 1 +PC: 80000a68 +wid: 0 +rd: 13 rs1: 13 rs2: -1 +is_lw: 0 +is_sw: 0 +fetch_stall_cycles: 0 +mem_stall_cycles: 0 +stall_warp: 0 +wspawn: 0 +stalled: 1 +********************************** Decode ********************************* +valid: 1 +PC: 80000a6c +wid: 0 +rd: 5 rs1: -1 rs2: -1 +is_lw: 0 +is_sw: 0 +fetch_stall_cycles: 0 +mem_stall_cycles: 0 +stall_warp: 0 +wspawn: 0 +stalled: 0 +********************************** Fetch ********************************* +valid: 1 +PC: 80000a70 +wid: 0 +rd: 13 rs1: 13 rs2: 5 +is_lw: 0 +is_sw: 0 +fetch_stall_cycles: 2 +mem_stall_cycles: 0 +stall_warp: 0 +wspawn: 0 +stalled: 0 + + + +------------------------------------------------------ +CYCLE: 152 +Stalled Warps: +0 0 0 0 0 0 0 0 + +********************************** Writeback ********************************* +valid: 0 +PC: 0 +wid: 0 +rd: -1 rs1: -1 rs2: -1 +is_lw: 0 +is_sw: 0 +fetch_stall_cycles: 0 +mem_stall_cycles: 0 +stall_warp: 0 +wspawn: 0 +stalled: 0 +********************************** LSU ********************************* +valid: 0 +PC: 0 +wid: 0 +rd: -1 rs1: -1 rs2: -1 +is_lw: 0 +is_sw: 0 +fetch_stall_cycles: 0 +mem_stall_cycles: 0 +stall_warp: 0 +wspawn: 0 +stalled: 0 +********************************** execute_unit ********************************* +valid: 1 +PC: 80000a68 +wid: 0 +rd: 13 rs1: 13 rs2: -1 +is_lw: 0 +is_sw: 0 +fetch_stall_cycles: 0 +mem_stall_cycles: 0 +stall_warp: 0 +wspawn: 0 +stalled: 0 +********************************** scheduler ********************************* +valid: 1 +PC: 80000a6c +wid: 0 +rd: 5 rs1: -1 rs2: -1 +is_lw: 0 +is_sw: 0 +fetch_stall_cycles: 0 +mem_stall_cycles: 0 +stall_warp: 0 +wspawn: 0 +stalled: 0 +********************************** Decode ********************************* +valid: 0 +PC: 0 +wid: 0 +rd: -1 rs1: -1 rs2: -1 +is_lw: 0 +is_sw: 0 +fetch_stall_cycles: 0 +mem_stall_cycles: 0 +stall_warp: 0 +wspawn: 0 +stalled: 0 +********************************** Fetch ********************************* +valid: 1 +PC: 80000a70 +wid: 0 +rd: 13 rs1: 13 rs2: 5 +is_lw: 0 +is_sw: 0 +fetch_stall_cycles: 1 +mem_stall_cycles: 0 +stall_warp: 0 +wspawn: 0 +stalled: 0 + + + +------------------------------------------------------ +CYCLE: 153 +Stalled Warps: +0 0 0 0 0 0 0 0 + +********************************** Writeback ********************************* +valid: 1 +PC: 80000a68 +wid: 0 +rd: 13 rs1: 13 rs2: -1 +is_lw: 0 +is_sw: 0 +fetch_stall_cycles: 0 +mem_stall_cycles: 0 +stall_warp: 0 +wspawn: 0 +stalled: 0 +********************************** LSU ********************************* +valid: 0 +PC: 0 +wid: 0 +rd: -1 rs1: -1 rs2: -1 +is_lw: 0 +is_sw: 0 +fetch_stall_cycles: 0 +mem_stall_cycles: 0 +stall_warp: 0 +wspawn: 0 +stalled: 0 +********************************** execute_unit ********************************* +valid: 1 +PC: 80000a6c +wid: 0 +rd: 5 rs1: -1 rs2: -1 +is_lw: 0 +is_sw: 0 +fetch_stall_cycles: 0 +mem_stall_cycles: 0 +stall_warp: 0 +wspawn: 0 +stalled: 0 +********************************** scheduler ********************************* +valid: 0 +PC: 0 +wid: 0 +rd: -1 rs1: -1 rs2: -1 +is_lw: 0 +is_sw: 0 +fetch_stall_cycles: 0 +mem_stall_cycles: 0 +stall_warp: 0 +wspawn: 0 +stalled: 0 +********************************** Decode ********************************* +valid: 0 +PC: 0 +wid: 0 +rd: -1 rs1: -1 rs2: -1 +is_lw: 0 +is_sw: 0 +fetch_stall_cycles: 0 +mem_stall_cycles: 0 +stall_warp: 0 +wspawn: 0 +stalled: 0 +********************************** Fetch ********************************* +valid: 1 +PC: 80000a70 +wid: 0 +rd: 13 rs1: 13 rs2: 5 +is_lw: 0 +is_sw: 0 +fetch_stall_cycles: 0 +mem_stall_cycles: 0 +stall_warp: 0 +wspawn: 0 +stalled: 0 + + + +------------------------------------------------------ +CYCLE: 154 +Stalled Warps: +0 0 0 0 0 0 0 0 + +********************************** Writeback ********************************* +valid: 1 +PC: 80000a6c +wid: 0 +rd: 5 rs1: -1 rs2: -1 +is_lw: 0 +is_sw: 0 +fetch_stall_cycles: 0 +mem_stall_cycles: 0 +stall_warp: 0 +wspawn: 0 +stalled: 0 +********************************** LSU ********************************* +valid: 0 +PC: 0 +wid: 0 +rd: -1 rs1: -1 rs2: -1 +is_lw: 0 +is_sw: 0 +fetch_stall_cycles: 0 +mem_stall_cycles: 0 +stall_warp: 0 +wspawn: 0 +stalled: 0 +********************************** execute_unit ********************************* +valid: 0 +PC: 0 +wid: 0 +rd: -1 rs1: -1 rs2: -1 +is_lw: 0 +is_sw: 0 +fetch_stall_cycles: 0 +mem_stall_cycles: 0 +stall_warp: 0 +wspawn: 0 +stalled: 0 +********************************** scheduler ********************************* +valid: 0 +PC: 0 +wid: 0 +rd: -1 rs1: -1 rs2: -1 +is_lw: 0 +is_sw: 0 +fetch_stall_cycles: 0 +mem_stall_cycles: 0 +stall_warp: 0 +wspawn: 0 +stalled: 0 +********************************** Decode ********************************* +valid: 1 +PC: 80000a70 +wid: 0 +rd: 13 rs1: 13 rs2: 5 +is_lw: 0 +is_sw: 0 +fetch_stall_cycles: 0 +mem_stall_cycles: 0 +stall_warp: 0 +wspawn: 0 +stalled: 0 +DEBUG ../core.cpp:386: Core step stepping warp 0[1] +DEBUG ../core.cpp:683: in step pc=0x80000a74 +help: in PC: 80000a74 +CUrrent CODE: c68067 +DEBUG ../core.cpp:703: Fetched at 0x80000a74 +DEBUG ../core.cpp:704: 0x80000a74: jalr; +DEBUG ../instruction.cpp:350: Begin instruction execute. +JALR_INST +DEBUG ../instruction.cpp:2117: End instruction execute. +Next PC: 80000aa4 +DEBUG ../core.cpp:717: Register state: + %r 0: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r 1: 80000030 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r 2: 6ffff000 6fffec04 6fffe808 6fffe40c 00000000 00000000 00000000 00000000 (0) + %r 3: 80001808 80001808 80001808 80001808 00000000 00000000 00000000 00000000 (0) + %r 4: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r 5: 80000a6c 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r 6: 0000000f 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r 7: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r 8: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r 9: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r10: 80001440 00000001 00000001 00000001 00000000 00000000 00000000 00000000 (0) + %r11: 00000000 00000400 00000800 00000c00 00000000 00000000 00000000 00000000 (0) + %r12: 00000004 00000004 00000008 0000000c 00000000 00000000 00000000 00000000 (0) + %r13: 80000a98 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r14: 80001440 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r15: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r16: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r17: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r18: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r19: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r20: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r21: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r22: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r23: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r24: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r25: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r26: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r27: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r28: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r29: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r30: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r31: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) +DEBUG ../core.cpp:726: Thread mask: + 1 0 0 0 0 0 0 0 + + +DEBUG ../core.cpp:388: Now 1 active threads in 0 +********************************** Fetch ********************************* +valid: 1 +PC: 80000a74 +wid: 0 +rd: 0 rs1: 13 rs2: -1 +is_lw: 0 +is_sw: 0 +fetch_stall_cycles: 0 +mem_stall_cycles: 0 +stall_warp: 1 +wspawn: 0 +stalled: 0 + + + +------------------------------------------------------ +CYCLE: 155 +Stalled Warps: +1 0 0 0 0 0 0 0 + +********************************** Writeback ********************************* +valid: 0 +PC: 0 +wid: 1 +rd: -1 rs1: -1 rs2: -1 +is_lw: 0 +is_sw: 0 +fetch_stall_cycles: 0 +mem_stall_cycles: 0 +stall_warp: 0 +wspawn: 0 +stalled: 0 +********************************** LSU ********************************* +valid: 0 +PC: 0 +wid: 0 +rd: -1 rs1: -1 rs2: -1 +is_lw: 0 +is_sw: 0 +fetch_stall_cycles: 0 +mem_stall_cycles: 0 +stall_warp: 0 +wspawn: 0 +stalled: 0 +********************************** execute_unit ********************************* +valid: 0 +PC: 0 +wid: 0 +rd: -1 rs1: -1 rs2: -1 +is_lw: 0 +is_sw: 0 +fetch_stall_cycles: 0 +mem_stall_cycles: 0 +stall_warp: 0 +wspawn: 0 +stalled: 0 +********************************** scheduler ********************************* +valid: 1 +PC: 80000a70 +wid: 0 +rd: 13 rs1: 13 rs2: 5 +is_lw: 0 +is_sw: 0 +fetch_stall_cycles: 0 +mem_stall_cycles: 0 +stall_warp: 0 +wspawn: 0 +stalled: 0 +********************************** Decode ********************************* +valid: 1 +PC: 80000a74 +wid: 0 +rd: 0 rs1: 13 rs2: -1 +is_lw: 0 +is_sw: 0 +fetch_stall_cycles: 0 +mem_stall_cycles: 0 +stall_warp: 1 +wspawn: 0 +stalled: 0 +********************************** Fetch ********************************* +valid: 0 +PC: 0 +wid: 1 +rd: -1 rs1: -1 rs2: -1 +is_lw: 0 +is_sw: 0 +fetch_stall_cycles: 0 +mem_stall_cycles: 0 +stall_warp: 0 +wspawn: 0 +stalled: 0 + + + +------------------------------------------------------ +CYCLE: 156 +Stalled Warps: +1 0 0 0 0 0 0 0 + +********************************** Writeback ********************************* +valid: 0 +PC: 0 +wid: 2 +rd: -1 rs1: -1 rs2: -1 +is_lw: 0 +is_sw: 0 +fetch_stall_cycles: 0 +mem_stall_cycles: 0 +stall_warp: 0 +wspawn: 0 +stalled: 0 +********************************** LSU ********************************* +valid: 0 +PC: 0 +wid: 0 +rd: -1 rs1: -1 rs2: -1 +is_lw: 0 +is_sw: 0 +fetch_stall_cycles: 0 +mem_stall_cycles: 0 +stall_warp: 0 +wspawn: 0 +stalled: 0 +********************************** execute_unit ********************************* +valid: 1 +PC: 80000a70 +wid: 0 +rd: 13 rs1: 13 rs2: 5 +is_lw: 0 +is_sw: 0 +fetch_stall_cycles: 0 +mem_stall_cycles: 0 +stall_warp: 0 +wspawn: 0 +stalled: 0 +********************************** scheduler ********************************* +valid: 1 +PC: 80000a74 +wid: 0 +rd: 0 rs1: 13 rs2: -1 +is_lw: 0 +is_sw: 0 +fetch_stall_cycles: 0 +mem_stall_cycles: 0 +stall_warp: 1 +wspawn: 0 +stalled: 0 +********************************** Decode ********************************* +valid: 0 +PC: 0 +wid: 1 +rd: -1 rs1: -1 rs2: -1 +is_lw: 0 +is_sw: 0 +fetch_stall_cycles: 0 +mem_stall_cycles: 0 +stall_warp: 0 +wspawn: 0 +stalled: 0 +********************************** Fetch ********************************* +valid: 0 +PC: 0 +wid: 2 +rd: -1 rs1: -1 rs2: -1 +is_lw: 0 +is_sw: 0 +fetch_stall_cycles: 0 +mem_stall_cycles: 0 +stall_warp: 0 +wspawn: 0 +stalled: 0 + + + +------------------------------------------------------ +CYCLE: 157 +Stalled Warps: +1 0 0 0 0 0 0 0 + +********************************** Writeback ********************************* +valid: 1 +PC: 80000a70 +wid: 0 +rd: 13 rs1: 13 rs2: 5 +is_lw: 0 +is_sw: 0 +fetch_stall_cycles: 0 +mem_stall_cycles: 0 +stall_warp: 0 +wspawn: 0 +stalled: 0 +********************************** LSU ********************************* +valid: 0 +PC: 0 +wid: 0 +rd: -1 rs1: -1 rs2: -1 +is_lw: 0 +is_sw: 0 +fetch_stall_cycles: 0 +mem_stall_cycles: 0 +stall_warp: 0 +wspawn: 0 +stalled: 0 +&&&&&&&&&&&&&&&&&&&&&&&& EXECUTE SRCS NOT READY +********************************** execute_unit ********************************* +valid: 0 +PC: 0 +wid: 3 +rd: -1 rs1: -1 rs2: -1 +is_lw: 0 +is_sw: 0 +fetch_stall_cycles: 0 +mem_stall_cycles: 0 +stall_warp: 0 +wspawn: 0 +stalled: 0 +********************************** scheduler ********************************* +valid: 1 +PC: 80000a74 +wid: 0 +rd: 0 rs1: 13 rs2: -1 +is_lw: 0 +is_sw: 0 +fetch_stall_cycles: 0 +mem_stall_cycles: 0 +stall_warp: 1 +wspawn: 0 +stalled: 1 +********************************** Decode ********************************* +valid: 0 +PC: 0 +wid: 1 +rd: -1 rs1: -1 rs2: -1 +is_lw: 0 +is_sw: 0 +fetch_stall_cycles: 0 +mem_stall_cycles: 0 +stall_warp: 0 +wspawn: 0 +stalled: 0 +********************************** Fetch ********************************* +valid: 0 +PC: 0 +wid: 2 +rd: -1 rs1: -1 rs2: -1 +is_lw: 0 +is_sw: 0 +fetch_stall_cycles: 0 +mem_stall_cycles: 0 +stall_warp: 0 +wspawn: 0 +stalled: 0 + + + +------------------------------------------------------ +CYCLE: 158 +Stalled Warps: +1 0 0 0 0 0 0 0 + +********************************** Writeback ********************************* +valid: 0 +PC: 0 +wid: 3 +rd: -1 rs1: -1 rs2: -1 +is_lw: 0 +is_sw: 0 +fetch_stall_cycles: 0 +mem_stall_cycles: 0 +stall_warp: 0 +wspawn: 0 +stalled: 0 +********************************** LSU ********************************* +valid: 0 +PC: 0 +wid: 0 +rd: -1 rs1: -1 rs2: -1 +is_lw: 0 +is_sw: 0 +fetch_stall_cycles: 0 +mem_stall_cycles: 0 +stall_warp: 0 +wspawn: 0 +stalled: 0 +********************************** execute_unit ********************************* +valid: 1 +PC: 80000a74 +wid: 0 +rd: 0 rs1: 13 rs2: -1 +is_lw: 0 +is_sw: 0 +fetch_stall_cycles: 0 +mem_stall_cycles: 0 +stall_warp: 1 +wspawn: 0 +stalled: 0 +********************************** scheduler ********************************* +valid: 0 +PC: 0 +wid: 1 +rd: -1 rs1: -1 rs2: -1 +is_lw: 0 +is_sw: 0 +fetch_stall_cycles: 0 +mem_stall_cycles: 0 +stall_warp: 0 +wspawn: 0 +stalled: 0 +********************************** Decode ********************************* +valid: 0 +PC: 0 +wid: 2 +rd: -1 rs1: -1 rs2: -1 +is_lw: 0 +is_sw: 0 +fetch_stall_cycles: 0 +mem_stall_cycles: 0 +stall_warp: 0 +wspawn: 0 +stalled: 0 +********************************** Fetch ********************************* +valid: 0 +PC: 0 +wid: 3 +rd: -1 rs1: -1 rs2: -1 +is_lw: 0 +is_sw: 0 +fetch_stall_cycles: 0 +mem_stall_cycles: 0 +stall_warp: 0 +wspawn: 0 +stalled: 0 + + + +------------------------------------------------------ +CYCLE: 159 +Stalled Warps: +1 0 0 0 0 0 0 0 + +********************************** Writeback ********************************* +valid: 1 +PC: 80000a74 +wid: 0 +rd: 0 rs1: 13 rs2: -1 +is_lw: 0 +is_sw: 0 +fetch_stall_cycles: 0 +mem_stall_cycles: 0 +stall_warp: 1 +wspawn: 0 +stalled: 0 +********************************** LSU ********************************* +valid: 0 +PC: 0 +wid: 0 +rd: -1 rs1: -1 rs2: -1 +is_lw: 0 +is_sw: 0 +fetch_stall_cycles: 0 +mem_stall_cycles: 0 +stall_warp: 0 +wspawn: 0 +stalled: 0 +********************************** execute_unit ********************************* +valid: 0 +PC: 0 +wid: 1 +rd: -1 rs1: -1 rs2: -1 +is_lw: 0 +is_sw: 0 +fetch_stall_cycles: 0 +mem_stall_cycles: 0 +stall_warp: 0 +wspawn: 0 +stalled: 0 +********************************** scheduler ********************************* +valid: 0 +PC: 0 +wid: 2 +rd: -1 rs1: -1 rs2: -1 +is_lw: 0 +is_sw: 0 +fetch_stall_cycles: 0 +mem_stall_cycles: 0 +stall_warp: 0 +wspawn: 0 +stalled: 0 +********************************** Decode ********************************* +valid: 0 +PC: 0 +wid: 3 +rd: -1 rs1: -1 rs2: -1 +is_lw: 0 +is_sw: 0 +fetch_stall_cycles: 0 +mem_stall_cycles: 0 +stall_warp: 0 +wspawn: 0 +stalled: 0 +********************************** Fetch ********************************* +valid: 0 +PC: 0 +wid: 4 +rd: -1 rs1: -1 rs2: -1 +is_lw: 0 +is_sw: 0 +fetch_stall_cycles: 0 +mem_stall_cycles: 0 +stall_warp: 0 +wspawn: 0 +stalled: 0 + + + +------------------------------------------------------ +CYCLE: 160 +Stalled Warps: +1 0 0 0 0 0 0 0 + +********************************** Writeback ********************************* +valid: 0 +PC: 0 +wid: 5 +rd: -1 rs1: -1 rs2: -1 +is_lw: 0 +is_sw: 0 +fetch_stall_cycles: 0 +mem_stall_cycles: 0 +stall_warp: 0 +wspawn: 0 +stalled: 0 +********************************** LSU ********************************* +valid: 0 +PC: 0 +wid: 0 +rd: -1 rs1: -1 rs2: -1 +is_lw: 0 +is_sw: 0 +fetch_stall_cycles: 0 +mem_stall_cycles: 0 +stall_warp: 0 +wspawn: 0 +stalled: 0 +********************************** execute_unit ********************************* +valid: 0 +PC: 0 +wid: 2 +rd: -1 rs1: -1 rs2: -1 +is_lw: 0 +is_sw: 0 +fetch_stall_cycles: 0 +mem_stall_cycles: 0 +stall_warp: 0 +wspawn: 0 +stalled: 0 +********************************** scheduler ********************************* +valid: 0 +PC: 0 +wid: 3 +rd: -1 rs1: -1 rs2: -1 +is_lw: 0 +is_sw: 0 +fetch_stall_cycles: 0 +mem_stall_cycles: 0 +stall_warp: 0 +wspawn: 0 +stalled: 0 +********************************** Decode ********************************* +valid: 0 +PC: 0 +wid: 4 +rd: -1 rs1: -1 rs2: -1 +is_lw: 0 +is_sw: 0 +fetch_stall_cycles: 0 +mem_stall_cycles: 0 +stall_warp: 0 +wspawn: 0 +stalled: 0 +********************************** Fetch ********************************* +valid: 0 +PC: 0 +wid: 5 +rd: -1 rs1: -1 rs2: -1 +is_lw: 0 +is_sw: 0 +fetch_stall_cycles: 0 +mem_stall_cycles: 0 +stall_warp: 0 +wspawn: 0 +stalled: 0 +Warp ID 0 is running + + + +------------------------------------------------------ +CYCLE: 161 +Stalled Warps: +0 0 0 0 0 0 0 0 + +********************************** Writeback ********************************* +valid: 0 +PC: 0 +wid: 0 +rd: -1 rs1: -1 rs2: -1 +is_lw: 0 +is_sw: 0 +fetch_stall_cycles: 0 +mem_stall_cycles: 0 +stall_warp: 0 +wspawn: 0 +stalled: 0 +********************************** LSU ********************************* +valid: 0 +PC: 0 +wid: 0 +rd: -1 rs1: -1 rs2: -1 +is_lw: 0 +is_sw: 0 +fetch_stall_cycles: 0 +mem_stall_cycles: 0 +stall_warp: 0 +wspawn: 0 +stalled: 0 +********************************** execute_unit ********************************* +valid: 0 +PC: 0 +wid: 3 +rd: -1 rs1: -1 rs2: -1 +is_lw: 0 +is_sw: 0 +fetch_stall_cycles: 0 +mem_stall_cycles: 0 +stall_warp: 0 +wspawn: 0 +stalled: 0 +********************************** scheduler ********************************* +valid: 0 +PC: 0 +wid: 4 +rd: -1 rs1: -1 rs2: -1 +is_lw: 0 +is_sw: 0 +fetch_stall_cycles: 0 +mem_stall_cycles: 0 +stall_warp: 0 +wspawn: 0 +stalled: 0 +********************************** Decode ********************************* +valid: 0 +PC: 0 +wid: 5 +rd: -1 rs1: -1 rs2: -1 +is_lw: 0 +is_sw: 0 +fetch_stall_cycles: 0 +mem_stall_cycles: 0 +stall_warp: 0 +wspawn: 0 +stalled: 0 +DEBUG ../core.cpp:386: Core step stepping warp 0[1] +DEBUG ../core.cpp:683: in step pc=0x80000aa4 +help: in PC: 80000aa4 +CUrrent CODE: b701a3 +DEBUG ../core.cpp:703: Fetched at 0x80000aa4 +DEBUG ../core.cpp:704: 0x80000aa4: store; +DEBUG ../instruction.cpp:350: Begin instruction execute. +STORE MEM ADDRESS: 80001440 + 3 +DEBUG ../instruction.cpp:2117: End instruction execute. +DEBUG ../core.cpp:717: Register state: + %r 0: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r 1: 80000030 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r 2: 6ffff000 6fffec04 6fffe808 6fffe40c 00000000 00000000 00000000 00000000 (0) + %r 3: 80001808 80001808 80001808 80001808 00000000 00000000 00000000 00000000 (0) + %r 4: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r 5: 80000a6c 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r 6: 0000000f 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r 7: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r 8: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r 9: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r10: 80001440 00000001 00000001 00000001 00000000 00000000 00000000 00000000 (0) + %r11: 00000000 00000400 00000800 00000c00 00000000 00000000 00000000 00000000 (0) + %r12: 00000004 00000004 00000008 0000000c 00000000 00000000 00000000 00000000 (0) + %r13: 80000a98 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r14: 80001440 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r15: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r16: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r17: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r18: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r19: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r20: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r21: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r22: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r23: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r24: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r25: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r26: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r27: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r28: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r29: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r30: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r31: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) +DEBUG ../core.cpp:726: Thread mask: + 1 0 0 0 0 0 0 0 + + +DEBUG ../core.cpp:388: Now 1 active threads in 0 +********************************** Fetch ********************************* +valid: 1 +PC: 80000aa4 +wid: 0 +rd: -1 rs1: 14 rs2: 11 +is_lw: 0 +is_sw: 1 +fetch_stall_cycles: 3 +mem_stall_cycles: 3 +stall_warp: 0 +wspawn: 0 +stalled: 0 + + + +------------------------------------------------------ +CYCLE: 162 +Stalled Warps: +0 0 0 0 0 0 0 0 + +********************************** Writeback ********************************* +valid: 0 +PC: 0 +wid: 0 +rd: -1 rs1: -1 rs2: -1 +is_lw: 0 +is_sw: 0 +fetch_stall_cycles: 0 +mem_stall_cycles: 0 +stall_warp: 0 +wspawn: 0 +stalled: 0 +********************************** LSU ********************************* +valid: 0 +PC: 0 +wid: 0 +rd: -1 rs1: -1 rs2: -1 +is_lw: 0 +is_sw: 0 +fetch_stall_cycles: 0 +mem_stall_cycles: 0 +stall_warp: 0 +wspawn: 0 +stalled: 0 +********************************** execute_unit ********************************* +valid: 0 +PC: 0 +wid: 4 +rd: -1 rs1: -1 rs2: -1 +is_lw: 0 +is_sw: 0 +fetch_stall_cycles: 0 +mem_stall_cycles: 0 +stall_warp: 0 +wspawn: 0 +stalled: 0 +********************************** scheduler ********************************* +valid: 0 +PC: 0 +wid: 5 +rd: -1 rs1: -1 rs2: -1 +is_lw: 0 +is_sw: 0 +fetch_stall_cycles: 0 +mem_stall_cycles: 0 +stall_warp: 0 +wspawn: 0 +stalled: 0 +********************************** Decode ********************************* +valid: 0 +PC: 0 +wid: 0 +rd: -1 rs1: -1 rs2: -1 +is_lw: 0 +is_sw: 0 +fetch_stall_cycles: 0 +mem_stall_cycles: 0 +stall_warp: 0 +wspawn: 0 +stalled: 0 +********************************** Fetch ********************************* +valid: 1 +PC: 80000aa4 +wid: 0 +rd: -1 rs1: 14 rs2: 11 +is_lw: 0 +is_sw: 1 +fetch_stall_cycles: 2 +mem_stall_cycles: 3 +stall_warp: 0 +wspawn: 0 +stalled: 0 + + + +------------------------------------------------------ +CYCLE: 163 +Stalled Warps: +0 0 0 0 0 0 0 0 + +********************************** Writeback ********************************* +valid: 0 +PC: 0 +wid: 0 +rd: -1 rs1: -1 rs2: -1 +is_lw: 0 +is_sw: 0 +fetch_stall_cycles: 0 +mem_stall_cycles: 0 +stall_warp: 0 +wspawn: 0 +stalled: 0 +********************************** LSU ********************************* +valid: 0 +PC: 0 +wid: 0 +rd: -1 rs1: -1 rs2: -1 +is_lw: 0 +is_sw: 0 +fetch_stall_cycles: 0 +mem_stall_cycles: 0 +stall_warp: 0 +wspawn: 0 +stalled: 0 +********************************** execute_unit ********************************* +valid: 0 +PC: 0 +wid: 5 +rd: -1 rs1: -1 rs2: -1 +is_lw: 0 +is_sw: 0 +fetch_stall_cycles: 0 +mem_stall_cycles: 0 +stall_warp: 0 +wspawn: 0 +stalled: 0 +********************************** scheduler ********************************* +valid: 0 +PC: 0 +wid: 0 +rd: -1 rs1: -1 rs2: -1 +is_lw: 0 +is_sw: 0 +fetch_stall_cycles: 0 +mem_stall_cycles: 0 +stall_warp: 0 +wspawn: 0 +stalled: 0 +********************************** Decode ********************************* +valid: 0 +PC: 0 +wid: 0 +rd: -1 rs1: -1 rs2: -1 +is_lw: 0 +is_sw: 0 +fetch_stall_cycles: 0 +mem_stall_cycles: 0 +stall_warp: 0 +wspawn: 0 +stalled: 0 +********************************** Fetch ********************************* +valid: 1 +PC: 80000aa4 +wid: 0 +rd: -1 rs1: 14 rs2: 11 +is_lw: 0 +is_sw: 1 +fetch_stall_cycles: 1 +mem_stall_cycles: 3 +stall_warp: 0 +wspawn: 0 +stalled: 0 + + + +------------------------------------------------------ +CYCLE: 164 +Stalled Warps: +0 0 0 0 0 0 0 0 + +********************************** Writeback ********************************* +valid: 0 +PC: 0 +wid: 0 +rd: -1 rs1: -1 rs2: -1 +is_lw: 0 +is_sw: 0 +fetch_stall_cycles: 0 +mem_stall_cycles: 0 +stall_warp: 0 +wspawn: 0 +stalled: 0 +********************************** LSU ********************************* +valid: 0 +PC: 0 +wid: 0 +rd: -1 rs1: -1 rs2: -1 +is_lw: 0 +is_sw: 0 +fetch_stall_cycles: 0 +mem_stall_cycles: 0 +stall_warp: 0 +wspawn: 0 +stalled: 0 +********************************** execute_unit ********************************* +valid: 0 +PC: 0 +wid: 0 +rd: -1 rs1: -1 rs2: -1 +is_lw: 0 +is_sw: 0 +fetch_stall_cycles: 0 +mem_stall_cycles: 0 +stall_warp: 0 +wspawn: 0 +stalled: 0 +********************************** scheduler ********************************* +valid: 0 +PC: 0 +wid: 0 +rd: -1 rs1: -1 rs2: -1 +is_lw: 0 +is_sw: 0 +fetch_stall_cycles: 0 +mem_stall_cycles: 0 +stall_warp: 0 +wspawn: 0 +stalled: 0 +********************************** Decode ********************************* +valid: 0 +PC: 0 +wid: 0 +rd: -1 rs1: -1 rs2: -1 +is_lw: 0 +is_sw: 0 +fetch_stall_cycles: 0 +mem_stall_cycles: 0 +stall_warp: 0 +wspawn: 0 +stalled: 0 +********************************** Fetch ********************************* +valid: 1 +PC: 80000aa4 +wid: 0 +rd: -1 rs1: 14 rs2: 11 +is_lw: 0 +is_sw: 1 +fetch_stall_cycles: 0 +mem_stall_cycles: 3 +stall_warp: 0 +wspawn: 0 +stalled: 0 + + + +------------------------------------------------------ +CYCLE: 165 +Stalled Warps: +0 0 0 0 0 0 0 0 + +********************************** Writeback ********************************* +valid: 0 +PC: 0 +wid: 0 +rd: -1 rs1: -1 rs2: -1 +is_lw: 0 +is_sw: 0 +fetch_stall_cycles: 0 +mem_stall_cycles: 0 +stall_warp: 0 +wspawn: 0 +stalled: 0 +********************************** LSU ********************************* +valid: 0 +PC: 0 +wid: 0 +rd: -1 rs1: -1 rs2: -1 +is_lw: 0 +is_sw: 0 +fetch_stall_cycles: 0 +mem_stall_cycles: 0 +stall_warp: 0 +wspawn: 0 +stalled: 0 +********************************** execute_unit ********************************* +valid: 0 +PC: 0 +wid: 0 +rd: -1 rs1: -1 rs2: -1 +is_lw: 0 +is_sw: 0 +fetch_stall_cycles: 0 +mem_stall_cycles: 0 +stall_warp: 0 +wspawn: 0 +stalled: 0 +********************************** scheduler ********************************* +valid: 0 +PC: 0 +wid: 0 +rd: -1 rs1: -1 rs2: -1 +is_lw: 0 +is_sw: 0 +fetch_stall_cycles: 0 +mem_stall_cycles: 0 +stall_warp: 0 +wspawn: 0 +stalled: 0 +********************************** Decode ********************************* +valid: 1 +PC: 80000aa4 +wid: 0 +rd: -1 rs1: 14 rs2: 11 +is_lw: 0 +is_sw: 1 +fetch_stall_cycles: 0 +mem_stall_cycles: 3 +stall_warp: 0 +wspawn: 0 +stalled: 0 +DEBUG ../core.cpp:386: Core step stepping warp 0[1] +DEBUG ../core.cpp:683: in step pc=0x80000aa8 +help: in PC: 80000aa8 +CUrrent CODE: b70123 +DEBUG ../core.cpp:703: Fetched at 0x80000aa8 +DEBUG ../core.cpp:704: 0x80000aa8: store; +DEBUG ../instruction.cpp:350: Begin instruction execute. +STORE MEM ADDRESS: 80001440 + 2 +DEBUG ../instruction.cpp:2117: End instruction execute. +DEBUG ../core.cpp:717: Register state: + %r 0: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r 1: 80000030 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r 2: 6ffff000 6fffec04 6fffe808 6fffe40c 00000000 00000000 00000000 00000000 (0) + %r 3: 80001808 80001808 80001808 80001808 00000000 00000000 00000000 00000000 (0) + %r 4: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r 5: 80000a6c 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r 6: 0000000f 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r 7: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r 8: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r 9: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r10: 80001440 00000001 00000001 00000001 00000000 00000000 00000000 00000000 (0) + %r11: 00000000 00000400 00000800 00000c00 00000000 00000000 00000000 00000000 (0) + %r12: 00000004 00000004 00000008 0000000c 00000000 00000000 00000000 00000000 (0) + %r13: 80000a98 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r14: 80001440 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r15: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r16: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r17: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r18: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r19: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r20: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r21: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r22: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r23: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r24: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r25: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r26: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r27: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r28: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r29: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r30: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r31: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) +DEBUG ../core.cpp:726: Thread mask: + 1 0 0 0 0 0 0 0 + + +DEBUG ../core.cpp:388: Now 1 active threads in 0 +********************************** Fetch ********************************* +valid: 1 +PC: 80000aa8 +wid: 0 +rd: -1 rs1: 14 rs2: 11 +is_lw: 0 +is_sw: 1 +fetch_stall_cycles: 0 +mem_stall_cycles: 0 +stall_warp: 0 +wspawn: 0 +stalled: 0 + + + +------------------------------------------------------ +CYCLE: 166 +Stalled Warps: +0 0 0 0 0 0 0 0 + +********************************** Writeback ********************************* +valid: 0 +PC: 0 +wid: 0 +rd: -1 rs1: -1 rs2: -1 +is_lw: 0 +is_sw: 0 +fetch_stall_cycles: 0 +mem_stall_cycles: 0 +stall_warp: 0 +wspawn: 0 +stalled: 0 +********************************** LSU ********************************* +valid: 0 +PC: 0 +wid: 0 +rd: -1 rs1: -1 rs2: -1 +is_lw: 0 +is_sw: 0 +fetch_stall_cycles: 0 +mem_stall_cycles: 0 +stall_warp: 0 +wspawn: 0 +stalled: 0 +********************************** execute_unit ********************************* +valid: 0 +PC: 0 +wid: 0 +rd: -1 rs1: -1 rs2: -1 +is_lw: 0 +is_sw: 0 +fetch_stall_cycles: 0 +mem_stall_cycles: 0 +stall_warp: 0 +wspawn: 0 +stalled: 0 +********************************** scheduler ********************************* +valid: 1 +PC: 80000aa4 +wid: 0 +rd: -1 rs1: 14 rs2: 11 +is_lw: 0 +is_sw: 1 +fetch_stall_cycles: 0 +mem_stall_cycles: 3 +stall_warp: 0 +wspawn: 0 +stalled: 0 +********************************** Decode ********************************* +valid: 1 +PC: 80000aa8 +wid: 0 +rd: -1 rs1: 14 rs2: 11 +is_lw: 0 +is_sw: 1 +fetch_stall_cycles: 0 +mem_stall_cycles: 0 +stall_warp: 0 +wspawn: 0 +stalled: 0 +DEBUG ../core.cpp:386: Core step stepping warp 0[1] +DEBUG ../core.cpp:683: in step pc=0x80000aac +help: in PC: 80000aac +CUrrent CODE: b700a3 +DEBUG ../core.cpp:703: Fetched at 0x80000aac +DEBUG ../core.cpp:704: 0x80000aac: store; +DEBUG ../instruction.cpp:350: Begin instruction execute. +STORE MEM ADDRESS: 80001440 + 1 +DEBUG ../instruction.cpp:2117: End instruction execute. +DEBUG ../core.cpp:717: Register state: + %r 0: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r 1: 80000030 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r 2: 6ffff000 6fffec04 6fffe808 6fffe40c 00000000 00000000 00000000 00000000 (0) + %r 3: 80001808 80001808 80001808 80001808 00000000 00000000 00000000 00000000 (0) + %r 4: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r 5: 80000a6c 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r 6: 0000000f 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r 7: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r 8: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r 9: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r10: 80001440 00000001 00000001 00000001 00000000 00000000 00000000 00000000 (0) + %r11: 00000000 00000400 00000800 00000c00 00000000 00000000 00000000 00000000 (0) + %r12: 00000004 00000004 00000008 0000000c 00000000 00000000 00000000 00000000 (0) + %r13: 80000a98 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r14: 80001440 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r15: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r16: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r17: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r18: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r19: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r20: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r21: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r22: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r23: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r24: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r25: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r26: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r27: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r28: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r29: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r30: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r31: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) +DEBUG ../core.cpp:726: Thread mask: + 1 0 0 0 0 0 0 0 + + +DEBUG ../core.cpp:388: Now 1 active threads in 0 +********************************** Fetch ********************************* +valid: 1 +PC: 80000aac +wid: 0 +rd: -1 rs1: 14 rs2: 11 +is_lw: 0 +is_sw: 1 +fetch_stall_cycles: 0 +mem_stall_cycles: 0 +stall_warp: 0 +wspawn: 0 +stalled: 0 + + + +------------------------------------------------------ +CYCLE: 167 +Stalled Warps: +0 0 0 0 0 0 0 0 + +********************************** Writeback ********************************* +valid: 0 +PC: 0 +wid: 0 +rd: -1 rs1: -1 rs2: -1 +is_lw: 0 +is_sw: 0 +fetch_stall_cycles: 0 +mem_stall_cycles: 0 +stall_warp: 0 +wspawn: 0 +stalled: 0 +********************************** LSU ********************************* +valid: 1 +PC: 80000aa4 +wid: 0 +rd: -1 rs1: 14 rs2: 11 +is_lw: 0 +is_sw: 1 +fetch_stall_cycles: 0 +mem_stall_cycles: 2 +stall_warp: 0 +wspawn: 0 +stalled: 0 +********************************** execute_unit ********************************* +valid: 0 +PC: 0 +wid: 0 +rd: -1 rs1: -1 rs2: -1 +is_lw: 0 +is_sw: 0 +fetch_stall_cycles: 0 +mem_stall_cycles: 0 +stall_warp: 0 +wspawn: 0 +stalled: 0 +********************************** scheduler ********************************* +valid: 1 +PC: 80000aa8 +wid: 0 +rd: -1 rs1: 14 rs2: 11 +is_lw: 0 +is_sw: 1 +fetch_stall_cycles: 0 +mem_stall_cycles: 0 +stall_warp: 0 +wspawn: 0 +stalled: 0 +********************************** Decode ********************************* +valid: 1 +PC: 80000aac +wid: 0 +rd: -1 rs1: 14 rs2: 11 +is_lw: 0 +is_sw: 1 +fetch_stall_cycles: 0 +mem_stall_cycles: 0 +stall_warp: 0 +wspawn: 0 +stalled: 0 +DEBUG ../core.cpp:386: Core step stepping warp 0[1] +DEBUG ../core.cpp:683: in step pc=0x80000ab0 +help: in PC: 80000ab0 +CUrrent CODE: b70023 +DEBUG ../core.cpp:703: Fetched at 0x80000ab0 +DEBUG ../core.cpp:704: 0x80000ab0: store; +DEBUG ../instruction.cpp:350: Begin instruction execute. +STORE MEM ADDRESS: 80001440 + 0 +DEBUG ../instruction.cpp:2117: End instruction execute. +DEBUG ../core.cpp:717: Register state: + %r 0: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r 1: 80000030 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r 2: 6ffff000 6fffec04 6fffe808 6fffe40c 00000000 00000000 00000000 00000000 (0) + %r 3: 80001808 80001808 80001808 80001808 00000000 00000000 00000000 00000000 (0) + %r 4: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r 5: 80000a6c 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r 6: 0000000f 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r 7: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r 8: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r 9: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r10: 80001440 00000001 00000001 00000001 00000000 00000000 00000000 00000000 (0) + %r11: 00000000 00000400 00000800 00000c00 00000000 00000000 00000000 00000000 (0) + %r12: 00000004 00000004 00000008 0000000c 00000000 00000000 00000000 00000000 (0) + %r13: 80000a98 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r14: 80001440 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r15: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r16: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r17: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r18: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r19: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r20: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r21: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r22: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r23: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r24: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r25: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r26: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r27: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r28: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r29: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r30: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r31: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) +DEBUG ../core.cpp:726: Thread mask: + 1 0 0 0 0 0 0 0 + + +DEBUG ../core.cpp:388: Now 1 active threads in 0 +********************************** Fetch ********************************* +valid: 1 +PC: 80000ab0 +wid: 0 +rd: -1 rs1: 14 rs2: 11 +is_lw: 0 +is_sw: 1 +fetch_stall_cycles: 3 +mem_stall_cycles: 0 +stall_warp: 0 +wspawn: 0 +stalled: 0 + + + +------------------------------------------------------ +CYCLE: 168 +Stalled Warps: +0 0 0 0 0 0 0 0 + +********************************** Writeback ********************************* +valid: 0 +PC: 0 +wid: 0 +rd: -1 rs1: -1 rs2: -1 +is_lw: 0 +is_sw: 0 +fetch_stall_cycles: 0 +mem_stall_cycles: 0 +stall_warp: 0 +wspawn: 0 +stalled: 0 +********************************** LSU ********************************* +valid: 1 +PC: 80000aa8 +wid: 0 +rd: -1 rs1: 14 rs2: 11 +is_lw: 0 +is_sw: 1 +fetch_stall_cycles: 0 +mem_stall_cycles: 0 +stall_warp: 0 +wspawn: 0 +stalled: 0 +********************************** execute_unit ********************************* +valid: 0 +PC: 0 +wid: 0 +rd: -1 rs1: -1 rs2: -1 +is_lw: 0 +is_sw: 0 +fetch_stall_cycles: 0 +mem_stall_cycles: 0 +stall_warp: 0 +wspawn: 0 +stalled: 0 +********************************** scheduler ********************************* +valid: 1 +PC: 80000aac +wid: 0 +rd: -1 rs1: 14 rs2: 11 +is_lw: 0 +is_sw: 1 +fetch_stall_cycles: 0 +mem_stall_cycles: 0 +stall_warp: 0 +wspawn: 0 +stalled: 0 +********************************** Decode ********************************* +valid: 0 +PC: 0 +wid: 0 +rd: -1 rs1: -1 rs2: -1 +is_lw: 0 +is_sw: 0 +fetch_stall_cycles: 0 +mem_stall_cycles: 0 +stall_warp: 0 +wspawn: 0 +stalled: 0 +********************************** Fetch ********************************* +valid: 1 +PC: 80000ab0 +wid: 0 +rd: -1 rs1: 14 rs2: 11 +is_lw: 0 +is_sw: 1 +fetch_stall_cycles: 2 +mem_stall_cycles: 0 +stall_warp: 0 +wspawn: 0 +stalled: 0 + + + +------------------------------------------------------ +CYCLE: 169 +Stalled Warps: +0 0 0 0 0 0 0 0 + +********************************** Writeback ********************************* +valid: 0 +PC: 0 +wid: 0 +rd: -1 rs1: -1 rs2: -1 +is_lw: 0 +is_sw: 0 +fetch_stall_cycles: 0 +mem_stall_cycles: 0 +stall_warp: 0 +wspawn: 0 +stalled: 0 +********************************** LSU ********************************* +valid: 1 +PC: 80000aac +wid: 0 +rd: -1 rs1: 14 rs2: 11 +is_lw: 0 +is_sw: 1 +fetch_stall_cycles: 0 +mem_stall_cycles: 0 +stall_warp: 0 +wspawn: 0 +stalled: 0 +********************************** execute_unit ********************************* +valid: 0 +PC: 0 +wid: 0 +rd: -1 rs1: -1 rs2: -1 +is_lw: 0 +is_sw: 0 +fetch_stall_cycles: 0 +mem_stall_cycles: 0 +stall_warp: 0 +wspawn: 0 +stalled: 0 +********************************** scheduler ********************************* +valid: 0 +PC: 0 +wid: 0 +rd: -1 rs1: -1 rs2: -1 +is_lw: 0 +is_sw: 0 +fetch_stall_cycles: 0 +mem_stall_cycles: 0 +stall_warp: 0 +wspawn: 0 +stalled: 0 +********************************** Decode ********************************* +valid: 0 +PC: 0 +wid: 0 +rd: -1 rs1: -1 rs2: -1 +is_lw: 0 +is_sw: 0 +fetch_stall_cycles: 0 +mem_stall_cycles: 0 +stall_warp: 0 +wspawn: 0 +stalled: 0 +********************************** Fetch ********************************* +valid: 1 +PC: 80000ab0 +wid: 0 +rd: -1 rs1: 14 rs2: 11 +is_lw: 0 +is_sw: 1 +fetch_stall_cycles: 1 +mem_stall_cycles: 0 +stall_warp: 0 +wspawn: 0 +stalled: 0 + + + +------------------------------------------------------ +CYCLE: 170 +Stalled Warps: +0 0 0 0 0 0 0 0 + +********************************** Writeback ********************************* +valid: 0 +PC: 0 +wid: 0 +rd: -1 rs1: -1 rs2: -1 +is_lw: 0 +is_sw: 0 +fetch_stall_cycles: 0 +mem_stall_cycles: 0 +stall_warp: 0 +wspawn: 0 +stalled: 0 +********************************** LSU ********************************* +valid: 0 +PC: 0 +wid: 0 +rd: -1 rs1: -1 rs2: -1 +is_lw: 0 +is_sw: 0 +fetch_stall_cycles: 0 +mem_stall_cycles: 0 +stall_warp: 0 +wspawn: 0 +stalled: 0 +********************************** execute_unit ********************************* +valid: 0 +PC: 0 +wid: 0 +rd: -1 rs1: -1 rs2: -1 +is_lw: 0 +is_sw: 0 +fetch_stall_cycles: 0 +mem_stall_cycles: 0 +stall_warp: 0 +wspawn: 0 +stalled: 0 +********************************** scheduler ********************************* +valid: 0 +PC: 0 +wid: 0 +rd: -1 rs1: -1 rs2: -1 +is_lw: 0 +is_sw: 0 +fetch_stall_cycles: 0 +mem_stall_cycles: 0 +stall_warp: 0 +wspawn: 0 +stalled: 0 +********************************** Decode ********************************* +valid: 0 +PC: 0 +wid: 0 +rd: -1 rs1: -1 rs2: -1 +is_lw: 0 +is_sw: 0 +fetch_stall_cycles: 0 +mem_stall_cycles: 0 +stall_warp: 0 +wspawn: 0 +stalled: 0 +********************************** Fetch ********************************* +valid: 1 +PC: 80000ab0 +wid: 0 +rd: -1 rs1: 14 rs2: 11 +is_lw: 0 +is_sw: 1 +fetch_stall_cycles: 0 +mem_stall_cycles: 0 +stall_warp: 0 +wspawn: 0 +stalled: 0 + + + +------------------------------------------------------ +CYCLE: 171 +Stalled Warps: +0 0 0 0 0 0 0 0 + +********************************** Writeback ********************************* +valid: 0 +PC: 0 +wid: 0 +rd: -1 rs1: -1 rs2: -1 +is_lw: 0 +is_sw: 0 +fetch_stall_cycles: 0 +mem_stall_cycles: 0 +stall_warp: 0 +wspawn: 0 +stalled: 0 +********************************** LSU ********************************* +valid: 0 +PC: 0 +wid: 0 +rd: -1 rs1: -1 rs2: -1 +is_lw: 0 +is_sw: 0 +fetch_stall_cycles: 0 +mem_stall_cycles: 0 +stall_warp: 0 +wspawn: 0 +stalled: 0 +********************************** execute_unit ********************************* +valid: 0 +PC: 0 +wid: 0 +rd: -1 rs1: -1 rs2: -1 +is_lw: 0 +is_sw: 0 +fetch_stall_cycles: 0 +mem_stall_cycles: 0 +stall_warp: 0 +wspawn: 0 +stalled: 0 +********************************** scheduler ********************************* +valid: 0 +PC: 0 +wid: 0 +rd: -1 rs1: -1 rs2: -1 +is_lw: 0 +is_sw: 0 +fetch_stall_cycles: 0 +mem_stall_cycles: 0 +stall_warp: 0 +wspawn: 0 +stalled: 0 +********************************** Decode ********************************* +valid: 1 +PC: 80000ab0 +wid: 0 +rd: -1 rs1: 14 rs2: 11 +is_lw: 0 +is_sw: 1 +fetch_stall_cycles: 0 +mem_stall_cycles: 0 +stall_warp: 0 +wspawn: 0 +stalled: 0 +DEBUG ../core.cpp:386: Core step stepping warp 0[1] +DEBUG ../core.cpp:683: in step pc=0x80000ab4 +help: in PC: 80000ab4 +CUrrent CODE: 8067 +DEBUG ../core.cpp:703: Fetched at 0x80000ab4 +DEBUG ../core.cpp:704: 0x80000ab4: jalr; +DEBUG ../instruction.cpp:350: Begin instruction execute. +JALR_INST +DEBUG ../instruction.cpp:2117: End instruction execute. +Next PC: 80000030 +DEBUG ../core.cpp:717: Register state: + %r 0: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r 1: 80000030 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r 2: 6ffff000 6fffec04 6fffe808 6fffe40c 00000000 00000000 00000000 00000000 (0) + %r 3: 80001808 80001808 80001808 80001808 00000000 00000000 00000000 00000000 (0) + %r 4: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r 5: 80000a6c 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r 6: 0000000f 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r 7: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r 8: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r 9: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r10: 80001440 00000001 00000001 00000001 00000000 00000000 00000000 00000000 (0) + %r11: 00000000 00000400 00000800 00000c00 00000000 00000000 00000000 00000000 (0) + %r12: 00000004 00000004 00000008 0000000c 00000000 00000000 00000000 00000000 (0) + %r13: 80000a98 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r14: 80001440 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r15: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r16: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r17: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r18: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r19: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r20: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r21: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r22: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r23: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r24: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r25: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r26: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r27: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r28: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r29: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r30: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r31: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) +DEBUG ../core.cpp:726: Thread mask: + 1 0 0 0 0 0 0 0 + + +DEBUG ../core.cpp:388: Now 1 active threads in 0 +********************************** Fetch ********************************* +valid: 1 +PC: 80000ab4 +wid: 0 +rd: 0 rs1: 1 rs2: -1 +is_lw: 0 +is_sw: 0 +fetch_stall_cycles: 0 +mem_stall_cycles: 0 +stall_warp: 1 +wspawn: 0 +stalled: 0 + + + +------------------------------------------------------ +CYCLE: 172 +Stalled Warps: +1 0 0 0 0 0 0 0 + +********************************** Writeback ********************************* +valid: 0 +PC: 0 +wid: 1 +rd: -1 rs1: -1 rs2: -1 +is_lw: 0 +is_sw: 0 +fetch_stall_cycles: 0 +mem_stall_cycles: 0 +stall_warp: 0 +wspawn: 0 +stalled: 0 +********************************** LSU ********************************* +valid: 0 +PC: 0 +wid: 0 +rd: -1 rs1: -1 rs2: -1 +is_lw: 0 +is_sw: 0 +fetch_stall_cycles: 0 +mem_stall_cycles: 0 +stall_warp: 0 +wspawn: 0 +stalled: 0 +********************************** execute_unit ********************************* +valid: 0 +PC: 0 +wid: 0 +rd: -1 rs1: -1 rs2: -1 +is_lw: 0 +is_sw: 0 +fetch_stall_cycles: 0 +mem_stall_cycles: 0 +stall_warp: 0 +wspawn: 0 +stalled: 0 +********************************** scheduler ********************************* +valid: 1 +PC: 80000ab0 +wid: 0 +rd: -1 rs1: 14 rs2: 11 +is_lw: 0 +is_sw: 1 +fetch_stall_cycles: 0 +mem_stall_cycles: 0 +stall_warp: 0 +wspawn: 0 +stalled: 0 +********************************** Decode ********************************* +valid: 1 +PC: 80000ab4 +wid: 0 +rd: 0 rs1: 1 rs2: -1 +is_lw: 0 +is_sw: 0 +fetch_stall_cycles: 0 +mem_stall_cycles: 0 +stall_warp: 1 +wspawn: 0 +stalled: 0 +********************************** Fetch ********************************* +valid: 0 +PC: 0 +wid: 1 +rd: -1 rs1: -1 rs2: -1 +is_lw: 0 +is_sw: 0 +fetch_stall_cycles: 0 +mem_stall_cycles: 0 +stall_warp: 0 +wspawn: 0 +stalled: 0 + + + +------------------------------------------------------ +CYCLE: 173 +Stalled Warps: +1 0 0 0 0 0 0 0 + +********************************** Writeback ********************************* +valid: 0 +PC: 0 +wid: 2 +rd: -1 rs1: -1 rs2: -1 +is_lw: 0 +is_sw: 0 +fetch_stall_cycles: 0 +mem_stall_cycles: 0 +stall_warp: 0 +wspawn: 0 +stalled: 0 +********************************** LSU ********************************* +valid: 1 +PC: 80000ab0 +wid: 0 +rd: -1 rs1: 14 rs2: 11 +is_lw: 0 +is_sw: 1 +fetch_stall_cycles: 0 +mem_stall_cycles: 0 +stall_warp: 0 +wspawn: 0 +stalled: 0 +********************************** execute_unit ********************************* +valid: 0 +PC: 0 +wid: 2 +rd: -1 rs1: -1 rs2: -1 +is_lw: 0 +is_sw: 0 +fetch_stall_cycles: 0 +mem_stall_cycles: 0 +stall_warp: 0 +wspawn: 0 +stalled: 0 +********************************** scheduler ********************************* +valid: 1 +PC: 80000ab4 +wid: 0 +rd: 0 rs1: 1 rs2: -1 +is_lw: 0 +is_sw: 0 +fetch_stall_cycles: 0 +mem_stall_cycles: 0 +stall_warp: 1 +wspawn: 0 +stalled: 0 +********************************** Decode ********************************* +valid: 0 +PC: 0 +wid: 1 +rd: -1 rs1: -1 rs2: -1 +is_lw: 0 +is_sw: 0 +fetch_stall_cycles: 0 +mem_stall_cycles: 0 +stall_warp: 0 +wspawn: 0 +stalled: 0 +********************************** Fetch ********************************* +valid: 0 +PC: 0 +wid: 2 +rd: -1 rs1: -1 rs2: -1 +is_lw: 0 +is_sw: 0 +fetch_stall_cycles: 0 +mem_stall_cycles: 0 +stall_warp: 0 +wspawn: 0 +stalled: 0 + + + +------------------------------------------------------ +CYCLE: 174 +Stalled Warps: +1 0 0 0 0 0 0 0 + +********************************** Writeback ********************************* +valid: 0 +PC: 0 +wid: 3 +rd: -1 rs1: -1 rs2: -1 +is_lw: 0 +is_sw: 0 +fetch_stall_cycles: 0 +mem_stall_cycles: 0 +stall_warp: 0 +wspawn: 0 +stalled: 0 +********************************** LSU ********************************* +valid: 0 +PC: 0 +wid: 3 +rd: -1 rs1: -1 rs2: -1 +is_lw: 0 +is_sw: 0 +fetch_stall_cycles: 0 +mem_stall_cycles: 0 +stall_warp: 0 +wspawn: 0 +stalled: 0 +********************************** execute_unit ********************************* +valid: 1 +PC: 80000ab4 +wid: 0 +rd: 0 rs1: 1 rs2: -1 +is_lw: 0 +is_sw: 0 +fetch_stall_cycles: 0 +mem_stall_cycles: 0 +stall_warp: 1 +wspawn: 0 +stalled: 0 +********************************** scheduler ********************************* +valid: 0 +PC: 0 +wid: 1 +rd: -1 rs1: -1 rs2: -1 +is_lw: 0 +is_sw: 0 +fetch_stall_cycles: 0 +mem_stall_cycles: 0 +stall_warp: 0 +wspawn: 0 +stalled: 0 +********************************** Decode ********************************* +valid: 0 +PC: 0 +wid: 2 +rd: -1 rs1: -1 rs2: -1 +is_lw: 0 +is_sw: 0 +fetch_stall_cycles: 0 +mem_stall_cycles: 0 +stall_warp: 0 +wspawn: 0 +stalled: 0 +********************************** Fetch ********************************* +valid: 0 +PC: 0 +wid: 3 +rd: -1 rs1: -1 rs2: -1 +is_lw: 0 +is_sw: 0 +fetch_stall_cycles: 0 +mem_stall_cycles: 0 +stall_warp: 0 +wspawn: 0 +stalled: 0 + + + +------------------------------------------------------ +CYCLE: 175 +Stalled Warps: +1 0 0 0 0 0 0 0 + +********************************** Writeback ********************************* +valid: 1 +PC: 80000ab4 +wid: 0 +rd: 0 rs1: 1 rs2: -1 +is_lw: 0 +is_sw: 0 +fetch_stall_cycles: 0 +mem_stall_cycles: 0 +stall_warp: 1 +wspawn: 0 +stalled: 0 +********************************** LSU ********************************* +valid: 0 +PC: 0 +wid: 3 +rd: -1 rs1: -1 rs2: -1 +is_lw: 0 +is_sw: 0 +fetch_stall_cycles: 0 +mem_stall_cycles: 0 +stall_warp: 0 +wspawn: 0 +stalled: 0 +********************************** execute_unit ********************************* +valid: 0 +PC: 0 +wid: 1 +rd: -1 rs1: -1 rs2: -1 +is_lw: 0 +is_sw: 0 +fetch_stall_cycles: 0 +mem_stall_cycles: 0 +stall_warp: 0 +wspawn: 0 +stalled: 0 +********************************** scheduler ********************************* +valid: 0 +PC: 0 +wid: 2 +rd: -1 rs1: -1 rs2: -1 +is_lw: 0 +is_sw: 0 +fetch_stall_cycles: 0 +mem_stall_cycles: 0 +stall_warp: 0 +wspawn: 0 +stalled: 0 +********************************** Decode ********************************* +valid: 0 +PC: 0 +wid: 3 +rd: -1 rs1: -1 rs2: -1 +is_lw: 0 +is_sw: 0 +fetch_stall_cycles: 0 +mem_stall_cycles: 0 +stall_warp: 0 +wspawn: 0 +stalled: 0 +********************************** Fetch ********************************* +valid: 0 +PC: 0 +wid: 4 +rd: -1 rs1: -1 rs2: -1 +is_lw: 0 +is_sw: 0 +fetch_stall_cycles: 0 +mem_stall_cycles: 0 +stall_warp: 0 +wspawn: 0 +stalled: 0 + + + +------------------------------------------------------ +CYCLE: 176 +Stalled Warps: +1 0 0 0 0 0 0 0 + +********************************** Writeback ********************************* +valid: 0 +PC: 0 +wid: 5 +rd: -1 rs1: -1 rs2: -1 +is_lw: 0 +is_sw: 0 +fetch_stall_cycles: 0 +mem_stall_cycles: 0 +stall_warp: 0 +wspawn: 0 +stalled: 0 +********************************** LSU ********************************* +valid: 0 +PC: 0 +wid: 3 +rd: -1 rs1: -1 rs2: -1 +is_lw: 0 +is_sw: 0 +fetch_stall_cycles: 0 +mem_stall_cycles: 0 +stall_warp: 0 +wspawn: 0 +stalled: 0 +********************************** execute_unit ********************************* +valid: 0 +PC: 0 +wid: 2 +rd: -1 rs1: -1 rs2: -1 +is_lw: 0 +is_sw: 0 +fetch_stall_cycles: 0 +mem_stall_cycles: 0 +stall_warp: 0 +wspawn: 0 +stalled: 0 +********************************** scheduler ********************************* +valid: 0 +PC: 0 +wid: 3 +rd: -1 rs1: -1 rs2: -1 +is_lw: 0 +is_sw: 0 +fetch_stall_cycles: 0 +mem_stall_cycles: 0 +stall_warp: 0 +wspawn: 0 +stalled: 0 +********************************** Decode ********************************* +valid: 0 +PC: 0 +wid: 4 +rd: -1 rs1: -1 rs2: -1 +is_lw: 0 +is_sw: 0 +fetch_stall_cycles: 0 +mem_stall_cycles: 0 +stall_warp: 0 +wspawn: 0 +stalled: 0 +********************************** Fetch ********************************* +valid: 0 +PC: 0 +wid: 5 +rd: -1 rs1: -1 rs2: -1 +is_lw: 0 +is_sw: 0 +fetch_stall_cycles: 0 +mem_stall_cycles: 0 +stall_warp: 0 +wspawn: 0 +stalled: 0 +Warp ID 0 is running + + + +------------------------------------------------------ +CYCLE: 177 +Stalled Warps: +0 0 0 0 0 0 0 0 + +********************************** Writeback ********************************* +valid: 0 +PC: 0 +wid: 0 +rd: -1 rs1: -1 rs2: -1 +is_lw: 0 +is_sw: 0 +fetch_stall_cycles: 0 +mem_stall_cycles: 0 +stall_warp: 0 +wspawn: 0 +stalled: 0 +********************************** LSU ********************************* +valid: 0 +PC: 0 +wid: 3 +rd: -1 rs1: -1 rs2: -1 +is_lw: 0 +is_sw: 0 +fetch_stall_cycles: 0 +mem_stall_cycles: 0 +stall_warp: 0 +wspawn: 0 +stalled: 0 +********************************** execute_unit ********************************* +valid: 0 +PC: 0 +wid: 3 +rd: -1 rs1: -1 rs2: -1 +is_lw: 0 +is_sw: 0 +fetch_stall_cycles: 0 +mem_stall_cycles: 0 +stall_warp: 0 +wspawn: 0 +stalled: 0 +********************************** scheduler ********************************* +valid: 0 +PC: 0 +wid: 4 +rd: -1 rs1: -1 rs2: -1 +is_lw: 0 +is_sw: 0 +fetch_stall_cycles: 0 +mem_stall_cycles: 0 +stall_warp: 0 +wspawn: 0 +stalled: 0 +********************************** Decode ********************************* +valid: 0 +PC: 0 +wid: 5 +rd: -1 rs1: -1 rs2: -1 +is_lw: 0 +is_sw: 0 +fetch_stall_cycles: 0 +mem_stall_cycles: 0 +stall_warp: 0 +wspawn: 0 +stalled: 0 +DEBUG ../core.cpp:386: Core step stepping warp 0[1] +DEBUG ../core.cpp:683: in step pc=0x80000030 +help: in PC: 80000030 +CUrrent CODE: 1517 +DEBUG ../core.cpp:703: Fetched at 0x80000030 +DEBUG ../core.cpp:704: 0x80000030: auipc; +DEBUG ../instruction.cpp:350: Begin instruction execute. +DEBUG ../instruction.cpp:2117: End instruction execute. +DEBUG ../core.cpp:717: Register state: + %r 0: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r 1: 80000030 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r 2: 6ffff000 6fffec04 6fffe808 6fffe40c 00000000 00000000 00000000 00000000 (0) + %r 3: 80001808 80001808 80001808 80001808 00000000 00000000 00000000 00000000 (0) + %r 4: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r 5: 80000a6c 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r 6: 0000000f 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r 7: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r 8: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r 9: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r10: 80001030 00000001 00000001 00000001 00000000 00000000 00000000 00000000 (0) + %r11: 00000000 00000400 00000800 00000c00 00000000 00000000 00000000 00000000 (0) + %r12: 00000004 00000004 00000008 0000000c 00000000 00000000 00000000 00000000 (0) + %r13: 80000a98 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r14: 80001440 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r15: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r16: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r17: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r18: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r19: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r20: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r21: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r22: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r23: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r24: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r25: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r26: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r27: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r28: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r29: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r30: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r31: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) +DEBUG ../core.cpp:726: Thread mask: + 1 0 0 0 0 0 0 0 + + +DEBUG ../core.cpp:388: Now 1 active threads in 0 +********************************** Fetch ********************************* +valid: 1 +PC: 80000030 +wid: 0 +rd: 10 rs1: -1 rs2: -1 +is_lw: 0 +is_sw: 0 +fetch_stall_cycles: 3 +mem_stall_cycles: 0 +stall_warp: 0 +wspawn: 0 +stalled: 0 + + + +------------------------------------------------------ +CYCLE: 178 +Stalled Warps: +0 0 0 0 0 0 0 0 + +********************************** Writeback ********************************* +valid: 0 +PC: 0 +wid: 0 +rd: -1 rs1: -1 rs2: -1 +is_lw: 0 +is_sw: 0 +fetch_stall_cycles: 0 +mem_stall_cycles: 0 +stall_warp: 0 +wspawn: 0 +stalled: 0 +********************************** LSU ********************************* +valid: 0 +PC: 0 +wid: 3 +rd: -1 rs1: -1 rs2: -1 +is_lw: 0 +is_sw: 0 +fetch_stall_cycles: 0 +mem_stall_cycles: 0 +stall_warp: 0 +wspawn: 0 +stalled: 0 +********************************** execute_unit ********************************* +valid: 0 +PC: 0 +wid: 4 +rd: -1 rs1: -1 rs2: -1 +is_lw: 0 +is_sw: 0 +fetch_stall_cycles: 0 +mem_stall_cycles: 0 +stall_warp: 0 +wspawn: 0 +stalled: 0 +********************************** scheduler ********************************* +valid: 0 +PC: 0 +wid: 5 +rd: -1 rs1: -1 rs2: -1 +is_lw: 0 +is_sw: 0 +fetch_stall_cycles: 0 +mem_stall_cycles: 0 +stall_warp: 0 +wspawn: 0 +stalled: 0 +********************************** Decode ********************************* +valid: 0 +PC: 0 +wid: 0 +rd: -1 rs1: -1 rs2: -1 +is_lw: 0 +is_sw: 0 +fetch_stall_cycles: 0 +mem_stall_cycles: 0 +stall_warp: 0 +wspawn: 0 +stalled: 0 +********************************** Fetch ********************************* +valid: 1 +PC: 80000030 +wid: 0 +rd: 10 rs1: -1 rs2: -1 +is_lw: 0 +is_sw: 0 +fetch_stall_cycles: 2 +mem_stall_cycles: 0 +stall_warp: 0 +wspawn: 0 +stalled: 0 + + + +------------------------------------------------------ +CYCLE: 179 +Stalled Warps: +0 0 0 0 0 0 0 0 + +********************************** Writeback ********************************* +valid: 0 +PC: 0 +wid: 0 +rd: -1 rs1: -1 rs2: -1 +is_lw: 0 +is_sw: 0 +fetch_stall_cycles: 0 +mem_stall_cycles: 0 +stall_warp: 0 +wspawn: 0 +stalled: 0 +********************************** LSU ********************************* +valid: 0 +PC: 0 +wid: 3 +rd: -1 rs1: -1 rs2: -1 +is_lw: 0 +is_sw: 0 +fetch_stall_cycles: 0 +mem_stall_cycles: 0 +stall_warp: 0 +wspawn: 0 +stalled: 0 +********************************** execute_unit ********************************* +valid: 0 +PC: 0 +wid: 5 +rd: -1 rs1: -1 rs2: -1 +is_lw: 0 +is_sw: 0 +fetch_stall_cycles: 0 +mem_stall_cycles: 0 +stall_warp: 0 +wspawn: 0 +stalled: 0 +********************************** scheduler ********************************* +valid: 0 +PC: 0 +wid: 0 +rd: -1 rs1: -1 rs2: -1 +is_lw: 0 +is_sw: 0 +fetch_stall_cycles: 0 +mem_stall_cycles: 0 +stall_warp: 0 +wspawn: 0 +stalled: 0 +********************************** Decode ********************************* +valid: 0 +PC: 0 +wid: 0 +rd: -1 rs1: -1 rs2: -1 +is_lw: 0 +is_sw: 0 +fetch_stall_cycles: 0 +mem_stall_cycles: 0 +stall_warp: 0 +wspawn: 0 +stalled: 0 +********************************** Fetch ********************************* +valid: 1 +PC: 80000030 +wid: 0 +rd: 10 rs1: -1 rs2: -1 +is_lw: 0 +is_sw: 0 +fetch_stall_cycles: 1 +mem_stall_cycles: 0 +stall_warp: 0 +wspawn: 0 +stalled: 0 + + + +------------------------------------------------------ +CYCLE: 180 +Stalled Warps: +0 0 0 0 0 0 0 0 + +********************************** Writeback ********************************* +valid: 0 +PC: 0 +wid: 0 +rd: -1 rs1: -1 rs2: -1 +is_lw: 0 +is_sw: 0 +fetch_stall_cycles: 0 +mem_stall_cycles: 0 +stall_warp: 0 +wspawn: 0 +stalled: 0 +********************************** LSU ********************************* +valid: 0 +PC: 0 +wid: 3 +rd: -1 rs1: -1 rs2: -1 +is_lw: 0 +is_sw: 0 +fetch_stall_cycles: 0 +mem_stall_cycles: 0 +stall_warp: 0 +wspawn: 0 +stalled: 0 +********************************** execute_unit ********************************* +valid: 0 +PC: 0 +wid: 0 +rd: -1 rs1: -1 rs2: -1 +is_lw: 0 +is_sw: 0 +fetch_stall_cycles: 0 +mem_stall_cycles: 0 +stall_warp: 0 +wspawn: 0 +stalled: 0 +********************************** scheduler ********************************* +valid: 0 +PC: 0 +wid: 0 +rd: -1 rs1: -1 rs2: -1 +is_lw: 0 +is_sw: 0 +fetch_stall_cycles: 0 +mem_stall_cycles: 0 +stall_warp: 0 +wspawn: 0 +stalled: 0 +********************************** Decode ********************************* +valid: 0 +PC: 0 +wid: 0 +rd: -1 rs1: -1 rs2: -1 +is_lw: 0 +is_sw: 0 +fetch_stall_cycles: 0 +mem_stall_cycles: 0 +stall_warp: 0 +wspawn: 0 +stalled: 0 +********************************** Fetch ********************************* +valid: 1 +PC: 80000030 +wid: 0 +rd: 10 rs1: -1 rs2: -1 +is_lw: 0 +is_sw: 0 +fetch_stall_cycles: 0 +mem_stall_cycles: 0 +stall_warp: 0 +wspawn: 0 +stalled: 0 + + + +------------------------------------------------------ +CYCLE: 181 +Stalled Warps: +0 0 0 0 0 0 0 0 + +********************************** Writeback ********************************* +valid: 0 +PC: 0 +wid: 0 +rd: -1 rs1: -1 rs2: -1 +is_lw: 0 +is_sw: 0 +fetch_stall_cycles: 0 +mem_stall_cycles: 0 +stall_warp: 0 +wspawn: 0 +stalled: 0 +********************************** LSU ********************************* +valid: 0 +PC: 0 +wid: 3 +rd: -1 rs1: -1 rs2: -1 +is_lw: 0 +is_sw: 0 +fetch_stall_cycles: 0 +mem_stall_cycles: 0 +stall_warp: 0 +wspawn: 0 +stalled: 0 +********************************** execute_unit ********************************* +valid: 0 +PC: 0 +wid: 0 +rd: -1 rs1: -1 rs2: -1 +is_lw: 0 +is_sw: 0 +fetch_stall_cycles: 0 +mem_stall_cycles: 0 +stall_warp: 0 +wspawn: 0 +stalled: 0 +********************************** scheduler ********************************* +valid: 0 +PC: 0 +wid: 0 +rd: -1 rs1: -1 rs2: -1 +is_lw: 0 +is_sw: 0 +fetch_stall_cycles: 0 +mem_stall_cycles: 0 +stall_warp: 0 +wspawn: 0 +stalled: 0 +********************************** Decode ********************************* +valid: 1 +PC: 80000030 +wid: 0 +rd: 10 rs1: -1 rs2: -1 +is_lw: 0 +is_sw: 0 +fetch_stall_cycles: 0 +mem_stall_cycles: 0 +stall_warp: 0 +wspawn: 0 +stalled: 0 +DEBUG ../core.cpp:386: Core step stepping warp 0[1] +DEBUG ../core.cpp:683: in step pc=0x80000034 +help: in PC: 80000034 +CUrrent CODE: 8f450513 +DEBUG ../core.cpp:703: Fetched at 0x80000034 +DEBUG ../core.cpp:704: 0x80000034: i_type; +DEBUG ../instruction.cpp:350: Begin instruction execute. +DEBUG ../instruction.cpp:2117: End instruction execute. +DEBUG ../core.cpp:717: Register state: + %r 0: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r 1: 80000030 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r 2: 6ffff000 6fffec04 6fffe808 6fffe40c 00000000 00000000 00000000 00000000 (0) + %r 3: 80001808 80001808 80001808 80001808 00000000 00000000 00000000 00000000 (0) + %r 4: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r 5: 80000a6c 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r 6: 0000000f 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r 7: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r 8: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r 9: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r10: 80000924 00000001 00000001 00000001 00000000 00000000 00000000 00000000 (0) + %r11: 00000000 00000400 00000800 00000c00 00000000 00000000 00000000 00000000 (0) + %r12: 00000004 00000004 00000008 0000000c 00000000 00000000 00000000 00000000 (0) + %r13: 80000a98 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r14: 80001440 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r15: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r16: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r17: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r18: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r19: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r20: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r21: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r22: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r23: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r24: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r25: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r26: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r27: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r28: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r29: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r30: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r31: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) +DEBUG ../core.cpp:726: Thread mask: + 1 0 0 0 0 0 0 0 + + +DEBUG ../core.cpp:388: Now 1 active threads in 0 +********************************** Fetch ********************************* +valid: 1 +PC: 80000034 +wid: 0 +rd: 10 rs1: 10 rs2: -1 +is_lw: 0 +is_sw: 0 +fetch_stall_cycles: 0 +mem_stall_cycles: 0 +stall_warp: 0 +wspawn: 0 +stalled: 0 + + + +------------------------------------------------------ +CYCLE: 182 +Stalled Warps: +0 0 0 0 0 0 0 0 + +********************************** Writeback ********************************* +valid: 0 +PC: 0 +wid: 0 +rd: -1 rs1: -1 rs2: -1 +is_lw: 0 +is_sw: 0 +fetch_stall_cycles: 0 +mem_stall_cycles: 0 +stall_warp: 0 +wspawn: 0 +stalled: 0 +********************************** LSU ********************************* +valid: 0 +PC: 0 +wid: 3 +rd: -1 rs1: -1 rs2: -1 +is_lw: 0 +is_sw: 0 +fetch_stall_cycles: 0 +mem_stall_cycles: 0 +stall_warp: 0 +wspawn: 0 +stalled: 0 +********************************** execute_unit ********************************* +valid: 0 +PC: 0 +wid: 0 +rd: -1 rs1: -1 rs2: -1 +is_lw: 0 +is_sw: 0 +fetch_stall_cycles: 0 +mem_stall_cycles: 0 +stall_warp: 0 +wspawn: 0 +stalled: 0 +********************************** scheduler ********************************* +valid: 1 +PC: 80000030 +wid: 0 +rd: 10 rs1: -1 rs2: -1 +is_lw: 0 +is_sw: 0 +fetch_stall_cycles: 0 +mem_stall_cycles: 0 +stall_warp: 0 +wspawn: 0 +stalled: 0 +********************************** Decode ********************************* +valid: 1 +PC: 80000034 +wid: 0 +rd: 10 rs1: 10 rs2: -1 +is_lw: 0 +is_sw: 0 +fetch_stall_cycles: 0 +mem_stall_cycles: 0 +stall_warp: 0 +wspawn: 0 +stalled: 0 +DEBUG ../core.cpp:386: Core step stepping warp 0[1] +DEBUG ../core.cpp:683: in step pc=0x80000038 +help: in PC: 80000038 +CUrrent CODE: a9000ef +DEBUG ../core.cpp:703: Fetched at 0x80000038 +DEBUG ../core.cpp:704: 0x80000038: jal; +DEBUG ../instruction.cpp:350: Begin instruction execute. +DEBUG ../instruction.cpp:2117: End instruction execute. +Next PC: 800008e0 +DEBUG ../core.cpp:717: Register state: + %r 0: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r 1: 8000003c 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r 2: 6ffff000 6fffec04 6fffe808 6fffe40c 00000000 00000000 00000000 00000000 (0) + %r 3: 80001808 80001808 80001808 80001808 00000000 00000000 00000000 00000000 (0) + %r 4: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r 5: 80000a6c 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r 6: 0000000f 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r 7: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r 8: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r 9: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r10: 80000924 00000001 00000001 00000001 00000000 00000000 00000000 00000000 (0) + %r11: 00000000 00000400 00000800 00000c00 00000000 00000000 00000000 00000000 (0) + %r12: 00000004 00000004 00000008 0000000c 00000000 00000000 00000000 00000000 (0) + %r13: 80000a98 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r14: 80001440 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r15: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r16: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r17: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r18: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r19: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r20: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r21: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r22: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r23: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r24: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r25: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r26: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r27: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r28: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r29: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r30: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r31: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) +DEBUG ../core.cpp:726: Thread mask: + 1 0 0 0 0 0 0 0 + + +DEBUG ../core.cpp:388: Now 1 active threads in 0 +********************************** Fetch ********************************* +valid: 1 +PC: 80000038 +wid: 0 +rd: 1 rs1: -1 rs2: -1 +is_lw: 0 +is_sw: 0 +fetch_stall_cycles: 0 +mem_stall_cycles: 0 +stall_warp: 1 +wspawn: 0 +stalled: 0 + + + +------------------------------------------------------ +CYCLE: 183 +Stalled Warps: +1 0 0 0 0 0 0 0 + +********************************** Writeback ********************************* +valid: 0 +PC: 0 +wid: 1 +rd: -1 rs1: -1 rs2: -1 +is_lw: 0 +is_sw: 0 +fetch_stall_cycles: 0 +mem_stall_cycles: 0 +stall_warp: 0 +wspawn: 0 +stalled: 0 +********************************** LSU ********************************* +valid: 0 +PC: 0 +wid: 3 +rd: -1 rs1: -1 rs2: -1 +is_lw: 0 +is_sw: 0 +fetch_stall_cycles: 0 +mem_stall_cycles: 0 +stall_warp: 0 +wspawn: 0 +stalled: 0 +********************************** execute_unit ********************************* +valid: 1 +PC: 80000030 +wid: 0 +rd: 10 rs1: -1 rs2: -1 +is_lw: 0 +is_sw: 0 +fetch_stall_cycles: 0 +mem_stall_cycles: 0 +stall_warp: 0 +wspawn: 0 +stalled: 0 +********************************** scheduler ********************************* +valid: 1 +PC: 80000034 +wid: 0 +rd: 10 rs1: 10 rs2: -1 +is_lw: 0 +is_sw: 0 +fetch_stall_cycles: 0 +mem_stall_cycles: 0 +stall_warp: 0 +wspawn: 0 +stalled: 0 +********************************** Decode ********************************* +valid: 1 +PC: 80000038 +wid: 0 +rd: 1 rs1: -1 rs2: -1 +is_lw: 0 +is_sw: 0 +fetch_stall_cycles: 0 +mem_stall_cycles: 0 +stall_warp: 1 +wspawn: 0 +stalled: 0 +********************************** Fetch ********************************* +valid: 0 +PC: 0 +wid: 1 +rd: -1 rs1: -1 rs2: -1 +is_lw: 0 +is_sw: 0 +fetch_stall_cycles: 0 +mem_stall_cycles: 0 +stall_warp: 0 +wspawn: 0 +stalled: 0 + + + +------------------------------------------------------ +CYCLE: 184 +Stalled Warps: +1 0 0 0 0 0 0 0 + +********************************** Writeback ********************************* +valid: 1 +PC: 80000030 +wid: 0 +rd: 10 rs1: -1 rs2: -1 +is_lw: 0 +is_sw: 0 +fetch_stall_cycles: 0 +mem_stall_cycles: 0 +stall_warp: 0 +wspawn: 0 +stalled: 0 +********************************** LSU ********************************* +valid: 0 +PC: 0 +wid: 3 +rd: -1 rs1: -1 rs2: -1 +is_lw: 0 +is_sw: 0 +fetch_stall_cycles: 0 +mem_stall_cycles: 0 +stall_warp: 0 +wspawn: 0 +stalled: 0 +&&&&&&&&&&&&&&&&&&&&&&&& EXECUTE SRCS NOT READY +********************************** execute_unit ********************************* +valid: 0 +PC: 0 +wid: 2 +rd: -1 rs1: -1 rs2: -1 +is_lw: 0 +is_sw: 0 +fetch_stall_cycles: 0 +mem_stall_cycles: 0 +stall_warp: 0 +wspawn: 0 +stalled: 0 +********************************** scheduler ********************************* +valid: 1 +PC: 80000034 +wid: 0 +rd: 10 rs1: 10 rs2: -1 +is_lw: 0 +is_sw: 0 +fetch_stall_cycles: 0 +mem_stall_cycles: 0 +stall_warp: 0 +wspawn: 0 +stalled: 1 +********************************** Decode ********************************* +valid: 1 +PC: 80000038 +wid: 0 +rd: 1 rs1: -1 rs2: -1 +is_lw: 0 +is_sw: 0 +fetch_stall_cycles: 0 +mem_stall_cycles: 0 +stall_warp: 1 +wspawn: 0 +stalled: 0 +********************************** Fetch ********************************* +valid: 0 +PC: 0 +wid: 1 +rd: -1 rs1: -1 rs2: -1 +is_lw: 0 +is_sw: 0 +fetch_stall_cycles: 0 +mem_stall_cycles: 0 +stall_warp: 0 +wspawn: 0 +stalled: 0 + + + +------------------------------------------------------ +CYCLE: 185 +Stalled Warps: +1 0 0 0 0 0 0 0 + +********************************** Writeback ********************************* +valid: 0 +PC: 0 +wid: 2 +rd: -1 rs1: -1 rs2: -1 +is_lw: 0 +is_sw: 0 +fetch_stall_cycles: 0 +mem_stall_cycles: 0 +stall_warp: 0 +wspawn: 0 +stalled: 0 +********************************** LSU ********************************* +valid: 0 +PC: 0 +wid: 3 +rd: -1 rs1: -1 rs2: -1 +is_lw: 0 +is_sw: 0 +fetch_stall_cycles: 0 +mem_stall_cycles: 0 +stall_warp: 0 +wspawn: 0 +stalled: 0 +********************************** execute_unit ********************************* +valid: 1 +PC: 80000034 +wid: 0 +rd: 10 rs1: 10 rs2: -1 +is_lw: 0 +is_sw: 0 +fetch_stall_cycles: 0 +mem_stall_cycles: 0 +stall_warp: 0 +wspawn: 0 +stalled: 0 +********************************** scheduler ********************************* +valid: 1 +PC: 80000038 +wid: 0 +rd: 1 rs1: -1 rs2: -1 +is_lw: 0 +is_sw: 0 +fetch_stall_cycles: 0 +mem_stall_cycles: 0 +stall_warp: 1 +wspawn: 0 +stalled: 0 +********************************** Decode ********************************* +valid: 0 +PC: 0 +wid: 1 +rd: -1 rs1: -1 rs2: -1 +is_lw: 0 +is_sw: 0 +fetch_stall_cycles: 0 +mem_stall_cycles: 0 +stall_warp: 0 +wspawn: 0 +stalled: 0 +********************************** Fetch ********************************* +valid: 0 +PC: 0 +wid: 2 +rd: -1 rs1: -1 rs2: -1 +is_lw: 0 +is_sw: 0 +fetch_stall_cycles: 0 +mem_stall_cycles: 0 +stall_warp: 0 +wspawn: 0 +stalled: 0 + + + +------------------------------------------------------ +CYCLE: 186 +Stalled Warps: +1 0 0 0 0 0 0 0 + +********************************** Writeback ********************************* +valid: 1 +PC: 80000034 +wid: 0 +rd: 10 rs1: 10 rs2: -1 +is_lw: 0 +is_sw: 0 +fetch_stall_cycles: 0 +mem_stall_cycles: 0 +stall_warp: 0 +wspawn: 0 +stalled: 0 +********************************** LSU ********************************* +valid: 0 +PC: 0 +wid: 3 +rd: -1 rs1: -1 rs2: -1 +is_lw: 0 +is_sw: 0 +fetch_stall_cycles: 0 +mem_stall_cycles: 0 +stall_warp: 0 +wspawn: 0 +stalled: 0 +********************************** execute_unit ********************************* +valid: 1 +PC: 80000038 +wid: 0 +rd: 1 rs1: -1 rs2: -1 +is_lw: 0 +is_sw: 0 +fetch_stall_cycles: 0 +mem_stall_cycles: 0 +stall_warp: 1 +wspawn: 0 +stalled: 0 +********************************** scheduler ********************************* +valid: 0 +PC: 0 +wid: 1 +rd: -1 rs1: -1 rs2: -1 +is_lw: 0 +is_sw: 0 +fetch_stall_cycles: 0 +mem_stall_cycles: 0 +stall_warp: 0 +wspawn: 0 +stalled: 0 +********************************** Decode ********************************* +valid: 0 +PC: 0 +wid: 2 +rd: -1 rs1: -1 rs2: -1 +is_lw: 0 +is_sw: 0 +fetch_stall_cycles: 0 +mem_stall_cycles: 0 +stall_warp: 0 +wspawn: 0 +stalled: 0 +********************************** Fetch ********************************* +valid: 0 +PC: 0 +wid: 3 +rd: -1 rs1: -1 rs2: -1 +is_lw: 0 +is_sw: 0 +fetch_stall_cycles: 0 +mem_stall_cycles: 0 +stall_warp: 0 +wspawn: 0 +stalled: 0 + + + +------------------------------------------------------ +CYCLE: 187 +Stalled Warps: +1 0 0 0 0 0 0 0 + +********************************** Writeback ********************************* +valid: 1 +PC: 80000038 +wid: 0 +rd: 1 rs1: -1 rs2: -1 +is_lw: 0 +is_sw: 0 +fetch_stall_cycles: 0 +mem_stall_cycles: 0 +stall_warp: 1 +wspawn: 0 +stalled: 0 +********************************** LSU ********************************* +valid: 0 +PC: 0 +wid: 3 +rd: -1 rs1: -1 rs2: -1 +is_lw: 0 +is_sw: 0 +fetch_stall_cycles: 0 +mem_stall_cycles: 0 +stall_warp: 0 +wspawn: 0 +stalled: 0 +********************************** execute_unit ********************************* +valid: 0 +PC: 0 +wid: 1 +rd: -1 rs1: -1 rs2: -1 +is_lw: 0 +is_sw: 0 +fetch_stall_cycles: 0 +mem_stall_cycles: 0 +stall_warp: 0 +wspawn: 0 +stalled: 0 +********************************** scheduler ********************************* +valid: 0 +PC: 0 +wid: 2 +rd: -1 rs1: -1 rs2: -1 +is_lw: 0 +is_sw: 0 +fetch_stall_cycles: 0 +mem_stall_cycles: 0 +stall_warp: 0 +wspawn: 0 +stalled: 0 +********************************** Decode ********************************* +valid: 0 +PC: 0 +wid: 3 +rd: -1 rs1: -1 rs2: -1 +is_lw: 0 +is_sw: 0 +fetch_stall_cycles: 0 +mem_stall_cycles: 0 +stall_warp: 0 +wspawn: 0 +stalled: 0 +********************************** Fetch ********************************* +valid: 0 +PC: 0 +wid: 4 +rd: -1 rs1: -1 rs2: -1 +is_lw: 0 +is_sw: 0 +fetch_stall_cycles: 0 +mem_stall_cycles: 0 +stall_warp: 0 +wspawn: 0 +stalled: 0 + + + +------------------------------------------------------ +CYCLE: 188 +Stalled Warps: +1 0 0 0 0 0 0 0 + +********************************** Writeback ********************************* +valid: 0 +PC: 0 +wid: 5 +rd: -1 rs1: -1 rs2: -1 +is_lw: 0 +is_sw: 0 +fetch_stall_cycles: 0 +mem_stall_cycles: 0 +stall_warp: 0 +wspawn: 0 +stalled: 0 +********************************** LSU ********************************* +valid: 0 +PC: 0 +wid: 3 +rd: -1 rs1: -1 rs2: -1 +is_lw: 0 +is_sw: 0 +fetch_stall_cycles: 0 +mem_stall_cycles: 0 +stall_warp: 0 +wspawn: 0 +stalled: 0 +********************************** execute_unit ********************************* +valid: 0 +PC: 0 +wid: 2 +rd: -1 rs1: -1 rs2: -1 +is_lw: 0 +is_sw: 0 +fetch_stall_cycles: 0 +mem_stall_cycles: 0 +stall_warp: 0 +wspawn: 0 +stalled: 0 +********************************** scheduler ********************************* +valid: 0 +PC: 0 +wid: 3 +rd: -1 rs1: -1 rs2: -1 +is_lw: 0 +is_sw: 0 +fetch_stall_cycles: 0 +mem_stall_cycles: 0 +stall_warp: 0 +wspawn: 0 +stalled: 0 +********************************** Decode ********************************* +valid: 0 +PC: 0 +wid: 4 +rd: -1 rs1: -1 rs2: -1 +is_lw: 0 +is_sw: 0 +fetch_stall_cycles: 0 +mem_stall_cycles: 0 +stall_warp: 0 +wspawn: 0 +stalled: 0 +********************************** Fetch ********************************* +valid: 0 +PC: 0 +wid: 5 +rd: -1 rs1: -1 rs2: -1 +is_lw: 0 +is_sw: 0 +fetch_stall_cycles: 0 +mem_stall_cycles: 0 +stall_warp: 0 +wspawn: 0 +stalled: 0 +Warp ID 0 is running + + + +------------------------------------------------------ +CYCLE: 189 +Stalled Warps: +0 0 0 0 0 0 0 0 + +********************************** Writeback ********************************* +valid: 0 +PC: 0 +wid: 0 +rd: -1 rs1: -1 rs2: -1 +is_lw: 0 +is_sw: 0 +fetch_stall_cycles: 0 +mem_stall_cycles: 0 +stall_warp: 0 +wspawn: 0 +stalled: 0 +********************************** LSU ********************************* +valid: 0 +PC: 0 +wid: 3 +rd: -1 rs1: -1 rs2: -1 +is_lw: 0 +is_sw: 0 +fetch_stall_cycles: 0 +mem_stall_cycles: 0 +stall_warp: 0 +wspawn: 0 +stalled: 0 +********************************** execute_unit ********************************* +valid: 0 +PC: 0 +wid: 3 +rd: -1 rs1: -1 rs2: -1 +is_lw: 0 +is_sw: 0 +fetch_stall_cycles: 0 +mem_stall_cycles: 0 +stall_warp: 0 +wspawn: 0 +stalled: 0 +********************************** scheduler ********************************* +valid: 0 +PC: 0 +wid: 4 +rd: -1 rs1: -1 rs2: -1 +is_lw: 0 +is_sw: 0 +fetch_stall_cycles: 0 +mem_stall_cycles: 0 +stall_warp: 0 +wspawn: 0 +stalled: 0 +********************************** Decode ********************************* +valid: 0 +PC: 0 +wid: 5 +rd: -1 rs1: -1 rs2: -1 +is_lw: 0 +is_sw: 0 +fetch_stall_cycles: 0 +mem_stall_cycles: 0 +stall_warp: 0 +wspawn: 0 +stalled: 0 +DEBUG ../core.cpp:386: Core step stepping warp 0[1] +DEBUG ../core.cpp:683: in step pc=0x800008e0 +help: in PC: 800008e0 +CUrrent CODE: 50593 +DEBUG ../core.cpp:703: Fetched at 0x800008e0 +DEBUG ../core.cpp:704: 0x800008e0: i_type; +DEBUG ../instruction.cpp:350: Begin instruction execute. +DEBUG ../instruction.cpp:2117: End instruction execute. +DEBUG ../core.cpp:717: Register state: + %r 0: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r 1: 8000003c 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r 2: 6ffff000 6fffec04 6fffe808 6fffe40c 00000000 00000000 00000000 00000000 (0) + %r 3: 80001808 80001808 80001808 80001808 00000000 00000000 00000000 00000000 (0) + %r 4: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r 5: 80000a6c 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r 6: 0000000f 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r 7: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r 8: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r 9: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r10: 80000924 00000001 00000001 00000001 00000000 00000000 00000000 00000000 (0) + %r11: 80000924 00000400 00000800 00000c00 00000000 00000000 00000000 00000000 (0) + %r12: 00000004 00000004 00000008 0000000c 00000000 00000000 00000000 00000000 (0) + %r13: 80000a98 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r14: 80001440 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r15: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r16: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r17: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r18: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r19: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r20: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r21: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r22: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r23: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r24: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r25: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r26: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r27: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r28: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r29: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r30: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r31: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) +DEBUG ../core.cpp:726: Thread mask: + 1 0 0 0 0 0 0 0 + + +DEBUG ../core.cpp:388: Now 1 active threads in 0 +********************************** Fetch ********************************* +valid: 1 +PC: 800008e0 +wid: 0 +rd: 11 rs1: 10 rs2: -1 +is_lw: 0 +is_sw: 0 +fetch_stall_cycles: 3 +mem_stall_cycles: 0 +stall_warp: 0 +wspawn: 0 +stalled: 0 + + + +------------------------------------------------------ +CYCLE: 190 +Stalled Warps: +0 0 0 0 0 0 0 0 + +********************************** Writeback ********************************* +valid: 0 +PC: 0 +wid: 0 +rd: -1 rs1: -1 rs2: -1 +is_lw: 0 +is_sw: 0 +fetch_stall_cycles: 0 +mem_stall_cycles: 0 +stall_warp: 0 +wspawn: 0 +stalled: 0 +********************************** LSU ********************************* +valid: 0 +PC: 0 +wid: 3 +rd: -1 rs1: -1 rs2: -1 +is_lw: 0 +is_sw: 0 +fetch_stall_cycles: 0 +mem_stall_cycles: 0 +stall_warp: 0 +wspawn: 0 +stalled: 0 +********************************** execute_unit ********************************* +valid: 0 +PC: 0 +wid: 4 +rd: -1 rs1: -1 rs2: -1 +is_lw: 0 +is_sw: 0 +fetch_stall_cycles: 0 +mem_stall_cycles: 0 +stall_warp: 0 +wspawn: 0 +stalled: 0 +********************************** scheduler ********************************* +valid: 0 +PC: 0 +wid: 5 +rd: -1 rs1: -1 rs2: -1 +is_lw: 0 +is_sw: 0 +fetch_stall_cycles: 0 +mem_stall_cycles: 0 +stall_warp: 0 +wspawn: 0 +stalled: 0 +********************************** Decode ********************************* +valid: 0 +PC: 0 +wid: 0 +rd: -1 rs1: -1 rs2: -1 +is_lw: 0 +is_sw: 0 +fetch_stall_cycles: 0 +mem_stall_cycles: 0 +stall_warp: 0 +wspawn: 0 +stalled: 0 +********************************** Fetch ********************************* +valid: 1 +PC: 800008e0 +wid: 0 +rd: 11 rs1: 10 rs2: -1 +is_lw: 0 +is_sw: 0 +fetch_stall_cycles: 2 +mem_stall_cycles: 0 +stall_warp: 0 +wspawn: 0 +stalled: 0 + + + +------------------------------------------------------ +CYCLE: 191 +Stalled Warps: +0 0 0 0 0 0 0 0 + +********************************** Writeback ********************************* +valid: 0 +PC: 0 +wid: 0 +rd: -1 rs1: -1 rs2: -1 +is_lw: 0 +is_sw: 0 +fetch_stall_cycles: 0 +mem_stall_cycles: 0 +stall_warp: 0 +wspawn: 0 +stalled: 0 +********************************** LSU ********************************* +valid: 0 +PC: 0 +wid: 3 +rd: -1 rs1: -1 rs2: -1 +is_lw: 0 +is_sw: 0 +fetch_stall_cycles: 0 +mem_stall_cycles: 0 +stall_warp: 0 +wspawn: 0 +stalled: 0 +********************************** execute_unit ********************************* +valid: 0 +PC: 0 +wid: 5 +rd: -1 rs1: -1 rs2: -1 +is_lw: 0 +is_sw: 0 +fetch_stall_cycles: 0 +mem_stall_cycles: 0 +stall_warp: 0 +wspawn: 0 +stalled: 0 +********************************** scheduler ********************************* +valid: 0 +PC: 0 +wid: 0 +rd: -1 rs1: -1 rs2: -1 +is_lw: 0 +is_sw: 0 +fetch_stall_cycles: 0 +mem_stall_cycles: 0 +stall_warp: 0 +wspawn: 0 +stalled: 0 +********************************** Decode ********************************* +valid: 0 +PC: 0 +wid: 0 +rd: -1 rs1: -1 rs2: -1 +is_lw: 0 +is_sw: 0 +fetch_stall_cycles: 0 +mem_stall_cycles: 0 +stall_warp: 0 +wspawn: 0 +stalled: 0 +********************************** Fetch ********************************* +valid: 1 +PC: 800008e0 +wid: 0 +rd: 11 rs1: 10 rs2: -1 +is_lw: 0 +is_sw: 0 +fetch_stall_cycles: 1 +mem_stall_cycles: 0 +stall_warp: 0 +wspawn: 0 +stalled: 0 + + + +------------------------------------------------------ +CYCLE: 192 +Stalled Warps: +0 0 0 0 0 0 0 0 + +********************************** Writeback ********************************* +valid: 0 +PC: 0 +wid: 0 +rd: -1 rs1: -1 rs2: -1 +is_lw: 0 +is_sw: 0 +fetch_stall_cycles: 0 +mem_stall_cycles: 0 +stall_warp: 0 +wspawn: 0 +stalled: 0 +********************************** LSU ********************************* +valid: 0 +PC: 0 +wid: 3 +rd: -1 rs1: -1 rs2: -1 +is_lw: 0 +is_sw: 0 +fetch_stall_cycles: 0 +mem_stall_cycles: 0 +stall_warp: 0 +wspawn: 0 +stalled: 0 +********************************** execute_unit ********************************* +valid: 0 +PC: 0 +wid: 0 +rd: -1 rs1: -1 rs2: -1 +is_lw: 0 +is_sw: 0 +fetch_stall_cycles: 0 +mem_stall_cycles: 0 +stall_warp: 0 +wspawn: 0 +stalled: 0 +********************************** scheduler ********************************* +valid: 0 +PC: 0 +wid: 0 +rd: -1 rs1: -1 rs2: -1 +is_lw: 0 +is_sw: 0 +fetch_stall_cycles: 0 +mem_stall_cycles: 0 +stall_warp: 0 +wspawn: 0 +stalled: 0 +********************************** Decode ********************************* +valid: 0 +PC: 0 +wid: 0 +rd: -1 rs1: -1 rs2: -1 +is_lw: 0 +is_sw: 0 +fetch_stall_cycles: 0 +mem_stall_cycles: 0 +stall_warp: 0 +wspawn: 0 +stalled: 0 +********************************** Fetch ********************************* +valid: 1 +PC: 800008e0 +wid: 0 +rd: 11 rs1: 10 rs2: -1 +is_lw: 0 +is_sw: 0 +fetch_stall_cycles: 0 +mem_stall_cycles: 0 +stall_warp: 0 +wspawn: 0 +stalled: 0 + + + +------------------------------------------------------ +CYCLE: 193 +Stalled Warps: +0 0 0 0 0 0 0 0 + +********************************** Writeback ********************************* +valid: 0 +PC: 0 +wid: 0 +rd: -1 rs1: -1 rs2: -1 +is_lw: 0 +is_sw: 0 +fetch_stall_cycles: 0 +mem_stall_cycles: 0 +stall_warp: 0 +wspawn: 0 +stalled: 0 +********************************** LSU ********************************* +valid: 0 +PC: 0 +wid: 3 +rd: -1 rs1: -1 rs2: -1 +is_lw: 0 +is_sw: 0 +fetch_stall_cycles: 0 +mem_stall_cycles: 0 +stall_warp: 0 +wspawn: 0 +stalled: 0 +********************************** execute_unit ********************************* +valid: 0 +PC: 0 +wid: 0 +rd: -1 rs1: -1 rs2: -1 +is_lw: 0 +is_sw: 0 +fetch_stall_cycles: 0 +mem_stall_cycles: 0 +stall_warp: 0 +wspawn: 0 +stalled: 0 +********************************** scheduler ********************************* +valid: 0 +PC: 0 +wid: 0 +rd: -1 rs1: -1 rs2: -1 +is_lw: 0 +is_sw: 0 +fetch_stall_cycles: 0 +mem_stall_cycles: 0 +stall_warp: 0 +wspawn: 0 +stalled: 0 +********************************** Decode ********************************* +valid: 1 +PC: 800008e0 +wid: 0 +rd: 11 rs1: 10 rs2: -1 +is_lw: 0 +is_sw: 0 +fetch_stall_cycles: 0 +mem_stall_cycles: 0 +stall_warp: 0 +wspawn: 0 +stalled: 0 +DEBUG ../core.cpp:386: Core step stepping warp 0[1] +DEBUG ../core.cpp:683: in step pc=0x800008e4 +help: in PC: 800008e4 +CUrrent CODE: 693 +DEBUG ../core.cpp:703: Fetched at 0x800008e4 +DEBUG ../core.cpp:704: 0x800008e4: i_type; +DEBUG ../instruction.cpp:350: Begin instruction execute. +DEBUG ../instruction.cpp:2117: End instruction execute. +DEBUG ../core.cpp:717: Register state: + %r 0: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r 1: 8000003c 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r 2: 6ffff000 6fffec04 6fffe808 6fffe40c 00000000 00000000 00000000 00000000 (0) + %r 3: 80001808 80001808 80001808 80001808 00000000 00000000 00000000 00000000 (0) + %r 4: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r 5: 80000a6c 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r 6: 0000000f 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r 7: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r 8: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r 9: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r10: 80000924 00000001 00000001 00000001 00000000 00000000 00000000 00000000 (0) + %r11: 80000924 00000400 00000800 00000c00 00000000 00000000 00000000 00000000 (0) + %r12: 00000004 00000004 00000008 0000000c 00000000 00000000 00000000 00000000 (0) + %r13: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r14: 80001440 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r15: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r16: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r17: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r18: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r19: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r20: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r21: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r22: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r23: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r24: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r25: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r26: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r27: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r28: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r29: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r30: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r31: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) +DEBUG ../core.cpp:726: Thread mask: + 1 0 0 0 0 0 0 0 + + +DEBUG ../core.cpp:388: Now 1 active threads in 0 +********************************** Fetch ********************************* +valid: 1 +PC: 800008e4 +wid: 0 +rd: 13 rs1: 0 rs2: -1 +is_lw: 0 +is_sw: 0 +fetch_stall_cycles: 0 +mem_stall_cycles: 0 +stall_warp: 0 +wspawn: 0 +stalled: 0 + + + +------------------------------------------------------ +CYCLE: 194 +Stalled Warps: +0 0 0 0 0 0 0 0 + +********************************** Writeback ********************************* +valid: 0 +PC: 0 +wid: 0 +rd: -1 rs1: -1 rs2: -1 +is_lw: 0 +is_sw: 0 +fetch_stall_cycles: 0 +mem_stall_cycles: 0 +stall_warp: 0 +wspawn: 0 +stalled: 0 +********************************** LSU ********************************* +valid: 0 +PC: 0 +wid: 3 +rd: -1 rs1: -1 rs2: -1 +is_lw: 0 +is_sw: 0 +fetch_stall_cycles: 0 +mem_stall_cycles: 0 +stall_warp: 0 +wspawn: 0 +stalled: 0 +********************************** execute_unit ********************************* +valid: 0 +PC: 0 +wid: 0 +rd: -1 rs1: -1 rs2: -1 +is_lw: 0 +is_sw: 0 +fetch_stall_cycles: 0 +mem_stall_cycles: 0 +stall_warp: 0 +wspawn: 0 +stalled: 0 +********************************** scheduler ********************************* +valid: 1 +PC: 800008e0 +wid: 0 +rd: 11 rs1: 10 rs2: -1 +is_lw: 0 +is_sw: 0 +fetch_stall_cycles: 0 +mem_stall_cycles: 0 +stall_warp: 0 +wspawn: 0 +stalled: 0 +********************************** Decode ********************************* +valid: 1 +PC: 800008e4 +wid: 0 +rd: 13 rs1: 0 rs2: -1 +is_lw: 0 +is_sw: 0 +fetch_stall_cycles: 0 +mem_stall_cycles: 0 +stall_warp: 0 +wspawn: 0 +stalled: 0 +DEBUG ../core.cpp:386: Core step stepping warp 0[1] +DEBUG ../core.cpp:683: in step pc=0x800008e8 +help: in PC: 800008e8 +CUrrent CODE: 613 +DEBUG ../core.cpp:703: Fetched at 0x800008e8 +DEBUG ../core.cpp:704: 0x800008e8: i_type; +DEBUG ../instruction.cpp:350: Begin instruction execute. +DEBUG ../instruction.cpp:2117: End instruction execute. +DEBUG ../core.cpp:717: Register state: + %r 0: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r 1: 8000003c 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r 2: 6ffff000 6fffec04 6fffe808 6fffe40c 00000000 00000000 00000000 00000000 (0) + %r 3: 80001808 80001808 80001808 80001808 00000000 00000000 00000000 00000000 (0) + %r 4: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r 5: 80000a6c 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r 6: 0000000f 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r 7: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r 8: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r 9: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r10: 80000924 00000001 00000001 00000001 00000000 00000000 00000000 00000000 (0) + %r11: 80000924 00000400 00000800 00000c00 00000000 00000000 00000000 00000000 (0) + %r12: 00000000 00000004 00000008 0000000c 00000000 00000000 00000000 00000000 (0) + %r13: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r14: 80001440 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r15: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r16: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r17: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r18: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r19: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r20: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r21: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r22: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r23: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r24: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r25: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r26: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r27: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r28: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r29: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r30: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r31: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) +DEBUG ../core.cpp:726: Thread mask: + 1 0 0 0 0 0 0 0 + + +DEBUG ../core.cpp:388: Now 1 active threads in 0 +********************************** Fetch ********************************* +valid: 1 +PC: 800008e8 +wid: 0 +rd: 12 rs1: 0 rs2: -1 +is_lw: 0 +is_sw: 0 +fetch_stall_cycles: 0 +mem_stall_cycles: 0 +stall_warp: 0 +wspawn: 0 +stalled: 0 + + + +------------------------------------------------------ +CYCLE: 195 +Stalled Warps: +0 0 0 0 0 0 0 0 + +********************************** Writeback ********************************* +valid: 0 +PC: 0 +wid: 0 +rd: -1 rs1: -1 rs2: -1 +is_lw: 0 +is_sw: 0 +fetch_stall_cycles: 0 +mem_stall_cycles: 0 +stall_warp: 0 +wspawn: 0 +stalled: 0 +********************************** LSU ********************************* +valid: 0 +PC: 0 +wid: 3 +rd: -1 rs1: -1 rs2: -1 +is_lw: 0 +is_sw: 0 +fetch_stall_cycles: 0 +mem_stall_cycles: 0 +stall_warp: 0 +wspawn: 0 +stalled: 0 +********************************** execute_unit ********************************* +valid: 1 +PC: 800008e0 +wid: 0 +rd: 11 rs1: 10 rs2: -1 +is_lw: 0 +is_sw: 0 +fetch_stall_cycles: 0 +mem_stall_cycles: 0 +stall_warp: 0 +wspawn: 0 +stalled: 0 +********************************** scheduler ********************************* +valid: 1 +PC: 800008e4 +wid: 0 +rd: 13 rs1: 0 rs2: -1 +is_lw: 0 +is_sw: 0 +fetch_stall_cycles: 0 +mem_stall_cycles: 0 +stall_warp: 0 +wspawn: 0 +stalled: 0 +********************************** Decode ********************************* +valid: 1 +PC: 800008e8 +wid: 0 +rd: 12 rs1: 0 rs2: -1 +is_lw: 0 +is_sw: 0 +fetch_stall_cycles: 0 +mem_stall_cycles: 0 +stall_warp: 0 +wspawn: 0 +stalled: 0 +DEBUG ../core.cpp:386: Core step stepping warp 0[1] +DEBUG ../core.cpp:683: in step pc=0x800008ec +help: in PC: 800008ec +CUrrent CODE: 513 +DEBUG ../core.cpp:703: Fetched at 0x800008ec +DEBUG ../core.cpp:704: 0x800008ec: i_type; +DEBUG ../instruction.cpp:350: Begin instruction execute. +DEBUG ../instruction.cpp:2117: End instruction execute. +DEBUG ../core.cpp:717: Register state: + %r 0: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r 1: 8000003c 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r 2: 6ffff000 6fffec04 6fffe808 6fffe40c 00000000 00000000 00000000 00000000 (0) + %r 3: 80001808 80001808 80001808 80001808 00000000 00000000 00000000 00000000 (0) + %r 4: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r 5: 80000a6c 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r 6: 0000000f 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r 7: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r 8: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r 9: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r10: 00000000 00000001 00000001 00000001 00000000 00000000 00000000 00000000 (0) + %r11: 80000924 00000400 00000800 00000c00 00000000 00000000 00000000 00000000 (0) + %r12: 00000000 00000004 00000008 0000000c 00000000 00000000 00000000 00000000 (0) + %r13: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r14: 80001440 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r15: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r16: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r17: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r18: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r19: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r20: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r21: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r22: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r23: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r24: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r25: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r26: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r27: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r28: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r29: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r30: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r31: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) +DEBUG ../core.cpp:726: Thread mask: + 1 0 0 0 0 0 0 0 + + +DEBUG ../core.cpp:388: Now 1 active threads in 0 +********************************** Fetch ********************************* +valid: 1 +PC: 800008ec +wid: 0 +rd: 10 rs1: 0 rs2: -1 +is_lw: 0 +is_sw: 0 +fetch_stall_cycles: 0 +mem_stall_cycles: 0 +stall_warp: 0 +wspawn: 0 +stalled: 0 + + + +------------------------------------------------------ +CYCLE: 196 +Stalled Warps: +0 0 0 0 0 0 0 0 + +********************************** Writeback ********************************* +valid: 1 +PC: 800008e0 +wid: 0 +rd: 11 rs1: 10 rs2: -1 +is_lw: 0 +is_sw: 0 +fetch_stall_cycles: 0 +mem_stall_cycles: 0 +stall_warp: 0 +wspawn: 0 +stalled: 0 +********************************** LSU ********************************* +valid: 0 +PC: 0 +wid: 3 +rd: -1 rs1: -1 rs2: -1 +is_lw: 0 +is_sw: 0 +fetch_stall_cycles: 0 +mem_stall_cycles: 0 +stall_warp: 0 +wspawn: 0 +stalled: 0 +********************************** execute_unit ********************************* +valid: 1 +PC: 800008e4 +wid: 0 +rd: 13 rs1: 0 rs2: -1 +is_lw: 0 +is_sw: 0 +fetch_stall_cycles: 0 +mem_stall_cycles: 0 +stall_warp: 0 +wspawn: 0 +stalled: 0 +********************************** scheduler ********************************* +valid: 1 +PC: 800008e8 +wid: 0 +rd: 12 rs1: 0 rs2: -1 +is_lw: 0 +is_sw: 0 +fetch_stall_cycles: 0 +mem_stall_cycles: 0 +stall_warp: 0 +wspawn: 0 +stalled: 0 +********************************** Decode ********************************* +valid: 1 +PC: 800008ec +wid: 0 +rd: 10 rs1: 0 rs2: -1 +is_lw: 0 +is_sw: 0 +fetch_stall_cycles: 0 +mem_stall_cycles: 0 +stall_warp: 0 +wspawn: 0 +stalled: 0 +DEBUG ../core.cpp:386: Core step stepping warp 0[1] +DEBUG ../core.cpp:683: in step pc=0x800008f0 +help: in PC: 800008f0 +CUrrent CODE: 20c0006f +DEBUG ../core.cpp:703: Fetched at 0x800008f0 +DEBUG ../core.cpp:704: 0x800008f0: jal; +DEBUG ../instruction.cpp:350: Begin instruction execute. +DEBUG ../instruction.cpp:2117: End instruction execute. +Next PC: 80000afc +DEBUG ../core.cpp:717: Register state: + %r 0: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r 1: 8000003c 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r 2: 6ffff000 6fffec04 6fffe808 6fffe40c 00000000 00000000 00000000 00000000 (0) + %r 3: 80001808 80001808 80001808 80001808 00000000 00000000 00000000 00000000 (0) + %r 4: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r 5: 80000a6c 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r 6: 0000000f 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r 7: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r 8: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r 9: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r10: 00000000 00000001 00000001 00000001 00000000 00000000 00000000 00000000 (0) + %r11: 80000924 00000400 00000800 00000c00 00000000 00000000 00000000 00000000 (0) + %r12: 00000000 00000004 00000008 0000000c 00000000 00000000 00000000 00000000 (0) + %r13: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r14: 80001440 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r15: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r16: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r17: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r18: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r19: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r20: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r21: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r22: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r23: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r24: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r25: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r26: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r27: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r28: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r29: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r30: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r31: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) +DEBUG ../core.cpp:726: Thread mask: + 1 0 0 0 0 0 0 0 + + +DEBUG ../core.cpp:388: Now 1 active threads in 0 +********************************** Fetch ********************************* +valid: 1 +PC: 800008f0 +wid: 0 +rd: 0 rs1: -1 rs2: -1 +is_lw: 0 +is_sw: 0 +fetch_stall_cycles: 3 +mem_stall_cycles: 0 +stall_warp: 1 +wspawn: 0 +stalled: 0 + + + +------------------------------------------------------ +CYCLE: 197 +Stalled Warps: +1 0 0 0 0 0 0 0 + +********************************** Writeback ********************************* +valid: 1 +PC: 800008e4 +wid: 0 +rd: 13 rs1: 0 rs2: -1 +is_lw: 0 +is_sw: 0 +fetch_stall_cycles: 0 +mem_stall_cycles: 0 +stall_warp: 0 +wspawn: 0 +stalled: 0 +********************************** LSU ********************************* +valid: 0 +PC: 0 +wid: 3 +rd: -1 rs1: -1 rs2: -1 +is_lw: 0 +is_sw: 0 +fetch_stall_cycles: 0 +mem_stall_cycles: 0 +stall_warp: 0 +wspawn: 0 +stalled: 0 +********************************** execute_unit ********************************* +valid: 1 +PC: 800008e8 +wid: 0 +rd: 12 rs1: 0 rs2: -1 +is_lw: 0 +is_sw: 0 +fetch_stall_cycles: 0 +mem_stall_cycles: 0 +stall_warp: 0 +wspawn: 0 +stalled: 0 +********************************** scheduler ********************************* +valid: 1 +PC: 800008ec +wid: 0 +rd: 10 rs1: 0 rs2: -1 +is_lw: 0 +is_sw: 0 +fetch_stall_cycles: 0 +mem_stall_cycles: 0 +stall_warp: 0 +wspawn: 0 +stalled: 0 +********************************** Decode ********************************* +valid: 0 +PC: 0 +wid: 1 +rd: -1 rs1: -1 rs2: -1 +is_lw: 0 +is_sw: 0 +fetch_stall_cycles: 0 +mem_stall_cycles: 0 +stall_warp: 0 +wspawn: 0 +stalled: 0 +********************************** Fetch ********************************* +valid: 1 +PC: 800008f0 +wid: 0 +rd: 0 rs1: -1 rs2: -1 +is_lw: 0 +is_sw: 0 +fetch_stall_cycles: 2 +mem_stall_cycles: 0 +stall_warp: 1 +wspawn: 0 +stalled: 0 + + + +------------------------------------------------------ +CYCLE: 198 +Stalled Warps: +1 0 0 0 0 0 0 0 + +********************************** Writeback ********************************* +valid: 1 +PC: 800008e8 +wid: 0 +rd: 12 rs1: 0 rs2: -1 +is_lw: 0 +is_sw: 0 +fetch_stall_cycles: 0 +mem_stall_cycles: 0 +stall_warp: 0 +wspawn: 0 +stalled: 0 +********************************** LSU ********************************* +valid: 0 +PC: 0 +wid: 3 +rd: -1 rs1: -1 rs2: -1 +is_lw: 0 +is_sw: 0 +fetch_stall_cycles: 0 +mem_stall_cycles: 0 +stall_warp: 0 +wspawn: 0 +stalled: 0 +********************************** execute_unit ********************************* +valid: 1 +PC: 800008ec +wid: 0 +rd: 10 rs1: 0 rs2: -1 +is_lw: 0 +is_sw: 0 +fetch_stall_cycles: 0 +mem_stall_cycles: 0 +stall_warp: 0 +wspawn: 0 +stalled: 0 +********************************** scheduler ********************************* +valid: 0 +PC: 0 +wid: 1 +rd: -1 rs1: -1 rs2: -1 +is_lw: 0 +is_sw: 0 +fetch_stall_cycles: 0 +mem_stall_cycles: 0 +stall_warp: 0 +wspawn: 0 +stalled: 0 +********************************** Decode ********************************* +valid: 0 +PC: 0 +wid: 1 +rd: -1 rs1: -1 rs2: -1 +is_lw: 0 +is_sw: 0 +fetch_stall_cycles: 0 +mem_stall_cycles: 0 +stall_warp: 0 +wspawn: 0 +stalled: 0 +********************************** Fetch ********************************* +valid: 1 +PC: 800008f0 +wid: 0 +rd: 0 rs1: -1 rs2: -1 +is_lw: 0 +is_sw: 0 +fetch_stall_cycles: 1 +mem_stall_cycles: 0 +stall_warp: 1 +wspawn: 0 +stalled: 0 + + + +------------------------------------------------------ +CYCLE: 199 +Stalled Warps: +1 0 0 0 0 0 0 0 + +********************************** Writeback ********************************* +valid: 1 +PC: 800008ec +wid: 0 +rd: 10 rs1: 0 rs2: -1 +is_lw: 0 +is_sw: 0 +fetch_stall_cycles: 0 +mem_stall_cycles: 0 +stall_warp: 0 +wspawn: 0 +stalled: 0 +********************************** LSU ********************************* +valid: 0 +PC: 0 +wid: 3 +rd: -1 rs1: -1 rs2: -1 +is_lw: 0 +is_sw: 0 +fetch_stall_cycles: 0 +mem_stall_cycles: 0 +stall_warp: 0 +wspawn: 0 +stalled: 0 +********************************** execute_unit ********************************* +valid: 0 +PC: 0 +wid: 1 +rd: -1 rs1: -1 rs2: -1 +is_lw: 0 +is_sw: 0 +fetch_stall_cycles: 0 +mem_stall_cycles: 0 +stall_warp: 0 +wspawn: 0 +stalled: 0 +********************************** scheduler ********************************* +valid: 0 +PC: 0 +wid: 1 +rd: -1 rs1: -1 rs2: -1 +is_lw: 0 +is_sw: 0 +fetch_stall_cycles: 0 +mem_stall_cycles: 0 +stall_warp: 0 +wspawn: 0 +stalled: 0 +********************************** Decode ********************************* +valid: 0 +PC: 0 +wid: 1 +rd: -1 rs1: -1 rs2: -1 +is_lw: 0 +is_sw: 0 +fetch_stall_cycles: 0 +mem_stall_cycles: 0 +stall_warp: 0 +wspawn: 0 +stalled: 0 +********************************** Fetch ********************************* +valid: 1 +PC: 800008f0 +wid: 0 +rd: 0 rs1: -1 rs2: -1 +is_lw: 0 +is_sw: 0 +fetch_stall_cycles: 0 +mem_stall_cycles: 0 +stall_warp: 1 +wspawn: 0 +stalled: 0 + + + +------------------------------------------------------ +CYCLE: 200 +Stalled Warps: +1 0 0 0 0 0 0 0 + +********************************** Writeback ********************************* +valid: 0 +PC: 0 +wid: 1 +rd: -1 rs1: -1 rs2: -1 +is_lw: 0 +is_sw: 0 +fetch_stall_cycles: 0 +mem_stall_cycles: 0 +stall_warp: 0 +wspawn: 0 +stalled: 0 +********************************** LSU ********************************* +valid: 0 +PC: 0 +wid: 3 +rd: -1 rs1: -1 rs2: -1 +is_lw: 0 +is_sw: 0 +fetch_stall_cycles: 0 +mem_stall_cycles: 0 +stall_warp: 0 +wspawn: 0 +stalled: 0 +********************************** execute_unit ********************************* +valid: 0 +PC: 0 +wid: 1 +rd: -1 rs1: -1 rs2: -1 +is_lw: 0 +is_sw: 0 +fetch_stall_cycles: 0 +mem_stall_cycles: 0 +stall_warp: 0 +wspawn: 0 +stalled: 0 +********************************** scheduler ********************************* +valid: 0 +PC: 0 +wid: 1 +rd: -1 rs1: -1 rs2: -1 +is_lw: 0 +is_sw: 0 +fetch_stall_cycles: 0 +mem_stall_cycles: 0 +stall_warp: 0 +wspawn: 0 +stalled: 0 +********************************** Decode ********************************* +valid: 1 +PC: 800008f0 +wid: 0 +rd: 0 rs1: -1 rs2: -1 +is_lw: 0 +is_sw: 0 +fetch_stall_cycles: 0 +mem_stall_cycles: 0 +stall_warp: 1 +wspawn: 0 +stalled: 0 +********************************** Fetch ********************************* +valid: 0 +PC: 0 +wid: 1 +rd: -1 rs1: -1 rs2: -1 +is_lw: 0 +is_sw: 0 +fetch_stall_cycles: 0 +mem_stall_cycles: 0 +stall_warp: 0 +wspawn: 0 +stalled: 0 + + + +------------------------------------------------------ +CYCLE: 201 +Stalled Warps: +1 0 0 0 0 0 0 0 + +********************************** Writeback ********************************* +valid: 0 +PC: 0 +wid: 2 +rd: -1 rs1: -1 rs2: -1 +is_lw: 0 +is_sw: 0 +fetch_stall_cycles: 0 +mem_stall_cycles: 0 +stall_warp: 0 +wspawn: 0 +stalled: 0 +********************************** LSU ********************************* +valid: 0 +PC: 0 +wid: 3 +rd: -1 rs1: -1 rs2: -1 +is_lw: 0 +is_sw: 0 +fetch_stall_cycles: 0 +mem_stall_cycles: 0 +stall_warp: 0 +wspawn: 0 +stalled: 0 +********************************** execute_unit ********************************* +valid: 0 +PC: 0 +wid: 1 +rd: -1 rs1: -1 rs2: -1 +is_lw: 0 +is_sw: 0 +fetch_stall_cycles: 0 +mem_stall_cycles: 0 +stall_warp: 0 +wspawn: 0 +stalled: 0 +********************************** scheduler ********************************* +valid: 1 +PC: 800008f0 +wid: 0 +rd: 0 rs1: -1 rs2: -1 +is_lw: 0 +is_sw: 0 +fetch_stall_cycles: 0 +mem_stall_cycles: 0 +stall_warp: 1 +wspawn: 0 +stalled: 0 +********************************** Decode ********************************* +valid: 0 +PC: 0 +wid: 1 +rd: -1 rs1: -1 rs2: -1 +is_lw: 0 +is_sw: 0 +fetch_stall_cycles: 0 +mem_stall_cycles: 0 +stall_warp: 0 +wspawn: 0 +stalled: 0 +********************************** Fetch ********************************* +valid: 0 +PC: 0 +wid: 2 +rd: -1 rs1: -1 rs2: -1 +is_lw: 0 +is_sw: 0 +fetch_stall_cycles: 0 +mem_stall_cycles: 0 +stall_warp: 0 +wspawn: 0 +stalled: 0 + + + +------------------------------------------------------ +CYCLE: 202 +Stalled Warps: +1 0 0 0 0 0 0 0 + +********************************** Writeback ********************************* +valid: 0 +PC: 0 +wid: 3 +rd: -1 rs1: -1 rs2: -1 +is_lw: 0 +is_sw: 0 +fetch_stall_cycles: 0 +mem_stall_cycles: 0 +stall_warp: 0 +wspawn: 0 +stalled: 0 +********************************** LSU ********************************* +valid: 0 +PC: 0 +wid: 3 +rd: -1 rs1: -1 rs2: -1 +is_lw: 0 +is_sw: 0 +fetch_stall_cycles: 0 +mem_stall_cycles: 0 +stall_warp: 0 +wspawn: 0 +stalled: 0 +********************************** execute_unit ********************************* +valid: 1 +PC: 800008f0 +wid: 0 +rd: 0 rs1: -1 rs2: -1 +is_lw: 0 +is_sw: 0 +fetch_stall_cycles: 0 +mem_stall_cycles: 0 +stall_warp: 1 +wspawn: 0 +stalled: 0 +********************************** scheduler ********************************* +valid: 0 +PC: 0 +wid: 1 +rd: -1 rs1: -1 rs2: -1 +is_lw: 0 +is_sw: 0 +fetch_stall_cycles: 0 +mem_stall_cycles: 0 +stall_warp: 0 +wspawn: 0 +stalled: 0 +********************************** Decode ********************************* +valid: 0 +PC: 0 +wid: 2 +rd: -1 rs1: -1 rs2: -1 +is_lw: 0 +is_sw: 0 +fetch_stall_cycles: 0 +mem_stall_cycles: 0 +stall_warp: 0 +wspawn: 0 +stalled: 0 +********************************** Fetch ********************************* +valid: 0 +PC: 0 +wid: 3 +rd: -1 rs1: -1 rs2: -1 +is_lw: 0 +is_sw: 0 +fetch_stall_cycles: 0 +mem_stall_cycles: 0 +stall_warp: 0 +wspawn: 0 +stalled: 0 + + + +------------------------------------------------------ +CYCLE: 203 +Stalled Warps: +1 0 0 0 0 0 0 0 + +********************************** Writeback ********************************* +valid: 1 +PC: 800008f0 +wid: 0 +rd: 0 rs1: -1 rs2: -1 +is_lw: 0 +is_sw: 0 +fetch_stall_cycles: 0 +mem_stall_cycles: 0 +stall_warp: 1 +wspawn: 0 +stalled: 0 +********************************** LSU ********************************* +valid: 0 +PC: 0 +wid: 3 +rd: -1 rs1: -1 rs2: -1 +is_lw: 0 +is_sw: 0 +fetch_stall_cycles: 0 +mem_stall_cycles: 0 +stall_warp: 0 +wspawn: 0 +stalled: 0 +********************************** execute_unit ********************************* +valid: 0 +PC: 0 +wid: 1 +rd: -1 rs1: -1 rs2: -1 +is_lw: 0 +is_sw: 0 +fetch_stall_cycles: 0 +mem_stall_cycles: 0 +stall_warp: 0 +wspawn: 0 +stalled: 0 +********************************** scheduler ********************************* +valid: 0 +PC: 0 +wid: 2 +rd: -1 rs1: -1 rs2: -1 +is_lw: 0 +is_sw: 0 +fetch_stall_cycles: 0 +mem_stall_cycles: 0 +stall_warp: 0 +wspawn: 0 +stalled: 0 +********************************** Decode ********************************* +valid: 0 +PC: 0 +wid: 3 +rd: -1 rs1: -1 rs2: -1 +is_lw: 0 +is_sw: 0 +fetch_stall_cycles: 0 +mem_stall_cycles: 0 +stall_warp: 0 +wspawn: 0 +stalled: 0 +********************************** Fetch ********************************* +valid: 0 +PC: 0 +wid: 4 +rd: -1 rs1: -1 rs2: -1 +is_lw: 0 +is_sw: 0 +fetch_stall_cycles: 0 +mem_stall_cycles: 0 +stall_warp: 0 +wspawn: 0 +stalled: 0 + + + +------------------------------------------------------ +CYCLE: 204 +Stalled Warps: +1 0 0 0 0 0 0 0 + +********************************** Writeback ********************************* +valid: 0 +PC: 0 +wid: 5 +rd: -1 rs1: -1 rs2: -1 +is_lw: 0 +is_sw: 0 +fetch_stall_cycles: 0 +mem_stall_cycles: 0 +stall_warp: 0 +wspawn: 0 +stalled: 0 +********************************** LSU ********************************* +valid: 0 +PC: 0 +wid: 3 +rd: -1 rs1: -1 rs2: -1 +is_lw: 0 +is_sw: 0 +fetch_stall_cycles: 0 +mem_stall_cycles: 0 +stall_warp: 0 +wspawn: 0 +stalled: 0 +********************************** execute_unit ********************************* +valid: 0 +PC: 0 +wid: 2 +rd: -1 rs1: -1 rs2: -1 +is_lw: 0 +is_sw: 0 +fetch_stall_cycles: 0 +mem_stall_cycles: 0 +stall_warp: 0 +wspawn: 0 +stalled: 0 +********************************** scheduler ********************************* +valid: 0 +PC: 0 +wid: 3 +rd: -1 rs1: -1 rs2: -1 +is_lw: 0 +is_sw: 0 +fetch_stall_cycles: 0 +mem_stall_cycles: 0 +stall_warp: 0 +wspawn: 0 +stalled: 0 +********************************** Decode ********************************* +valid: 0 +PC: 0 +wid: 4 +rd: -1 rs1: -1 rs2: -1 +is_lw: 0 +is_sw: 0 +fetch_stall_cycles: 0 +mem_stall_cycles: 0 +stall_warp: 0 +wspawn: 0 +stalled: 0 +********************************** Fetch ********************************* +valid: 0 +PC: 0 +wid: 5 +rd: -1 rs1: -1 rs2: -1 +is_lw: 0 +is_sw: 0 +fetch_stall_cycles: 0 +mem_stall_cycles: 0 +stall_warp: 0 +wspawn: 0 +stalled: 0 +Warp ID 0 is running + + + +------------------------------------------------------ +CYCLE: 205 +Stalled Warps: +0 0 0 0 0 0 0 0 + +********************************** Writeback ********************************* +valid: 0 +PC: 0 +wid: 0 +rd: -1 rs1: -1 rs2: -1 +is_lw: 0 +is_sw: 0 +fetch_stall_cycles: 0 +mem_stall_cycles: 0 +stall_warp: 0 +wspawn: 0 +stalled: 0 +********************************** LSU ********************************* +valid: 0 +PC: 0 +wid: 3 +rd: -1 rs1: -1 rs2: -1 +is_lw: 0 +is_sw: 0 +fetch_stall_cycles: 0 +mem_stall_cycles: 0 +stall_warp: 0 +wspawn: 0 +stalled: 0 +********************************** execute_unit ********************************* +valid: 0 +PC: 0 +wid: 3 +rd: -1 rs1: -1 rs2: -1 +is_lw: 0 +is_sw: 0 +fetch_stall_cycles: 0 +mem_stall_cycles: 0 +stall_warp: 0 +wspawn: 0 +stalled: 0 +********************************** scheduler ********************************* +valid: 0 +PC: 0 +wid: 4 +rd: -1 rs1: -1 rs2: -1 +is_lw: 0 +is_sw: 0 +fetch_stall_cycles: 0 +mem_stall_cycles: 0 +stall_warp: 0 +wspawn: 0 +stalled: 0 +********************************** Decode ********************************* +valid: 0 +PC: 0 +wid: 5 +rd: -1 rs1: -1 rs2: -1 +is_lw: 0 +is_sw: 0 +fetch_stall_cycles: 0 +mem_stall_cycles: 0 +stall_warp: 0 +wspawn: 0 +stalled: 0 +DEBUG ../core.cpp:386: Core step stepping warp 0[1] +DEBUG ../core.cpp:683: in step pc=0x80000afc +help: in PC: 80000afc +CUrrent CODE: c281a703 +DEBUG ../core.cpp:703: Fetched at 0x80000afc +DEBUG ../core.cpp:704: 0x80000afc: load; +DEBUG ../instruction.cpp:350: Begin instruction execute. +DEBUG ../instruction.cpp:2117: End instruction execute. +DEBUG ../core.cpp:717: Register state: + %r 0: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r 1: 8000003c 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r 2: 6ffff000 6fffec04 6fffe808 6fffe40c 00000000 00000000 00000000 00000000 (0) + %r 3: 80001808 80001808 80001808 80001808 00000000 00000000 00000000 00000000 (0) + %r 4: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r 5: 80000a6c 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r 6: 0000000f 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r 7: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r 8: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r 9: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r10: 00000000 00000001 00000001 00000001 00000000 00000000 00000000 00000000 (0) + %r11: 80000924 00000400 00000800 00000c00 00000000 00000000 00000000 00000000 (0) + %r12: 00000000 00000004 00000008 0000000c 00000000 00000000 00000000 00000000 (0) + %r13: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r14: 80001008 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r15: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r16: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r17: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r18: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r19: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r20: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r21: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r22: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r23: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r24: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r25: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r26: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r27: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r28: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r29: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r30: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r31: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) +DEBUG ../core.cpp:726: Thread mask: + 1 0 0 0 0 0 0 0 + + +DEBUG ../core.cpp:388: Now 1 active threads in 0 +********************************** Fetch ********************************* +valid: 1 +PC: 80000afc +wid: 0 +rd: 14 rs1: 3 rs2: -1 +is_lw: 1 +is_sw: 0 +fetch_stall_cycles: 3 +mem_stall_cycles: 3 +stall_warp: 0 +wspawn: 0 +stalled: 0 + + + +------------------------------------------------------ +CYCLE: 206 +Stalled Warps: +0 0 0 0 0 0 0 0 + +********************************** Writeback ********************************* +valid: 0 +PC: 0 +wid: 0 +rd: -1 rs1: -1 rs2: -1 +is_lw: 0 +is_sw: 0 +fetch_stall_cycles: 0 +mem_stall_cycles: 0 +stall_warp: 0 +wspawn: 0 +stalled: 0 +********************************** LSU ********************************* +valid: 0 +PC: 0 +wid: 3 +rd: -1 rs1: -1 rs2: -1 +is_lw: 0 +is_sw: 0 +fetch_stall_cycles: 0 +mem_stall_cycles: 0 +stall_warp: 0 +wspawn: 0 +stalled: 0 +********************************** execute_unit ********************************* +valid: 0 +PC: 0 +wid: 4 +rd: -1 rs1: -1 rs2: -1 +is_lw: 0 +is_sw: 0 +fetch_stall_cycles: 0 +mem_stall_cycles: 0 +stall_warp: 0 +wspawn: 0 +stalled: 0 +********************************** scheduler ********************************* +valid: 0 +PC: 0 +wid: 5 +rd: -1 rs1: -1 rs2: -1 +is_lw: 0 +is_sw: 0 +fetch_stall_cycles: 0 +mem_stall_cycles: 0 +stall_warp: 0 +wspawn: 0 +stalled: 0 +********************************** Decode ********************************* +valid: 0 +PC: 0 +wid: 0 +rd: -1 rs1: -1 rs2: -1 +is_lw: 0 +is_sw: 0 +fetch_stall_cycles: 0 +mem_stall_cycles: 0 +stall_warp: 0 +wspawn: 0 +stalled: 0 +********************************** Fetch ********************************* +valid: 1 +PC: 80000afc +wid: 0 +rd: 14 rs1: 3 rs2: -1 +is_lw: 1 +is_sw: 0 +fetch_stall_cycles: 2 +mem_stall_cycles: 3 +stall_warp: 0 +wspawn: 0 +stalled: 0 + + + +------------------------------------------------------ +CYCLE: 207 +Stalled Warps: +0 0 0 0 0 0 0 0 + +********************************** Writeback ********************************* +valid: 0 +PC: 0 +wid: 0 +rd: -1 rs1: -1 rs2: -1 +is_lw: 0 +is_sw: 0 +fetch_stall_cycles: 0 +mem_stall_cycles: 0 +stall_warp: 0 +wspawn: 0 +stalled: 0 +********************************** LSU ********************************* +valid: 0 +PC: 0 +wid: 3 +rd: -1 rs1: -1 rs2: -1 +is_lw: 0 +is_sw: 0 +fetch_stall_cycles: 0 +mem_stall_cycles: 0 +stall_warp: 0 +wspawn: 0 +stalled: 0 +********************************** execute_unit ********************************* +valid: 0 +PC: 0 +wid: 5 +rd: -1 rs1: -1 rs2: -1 +is_lw: 0 +is_sw: 0 +fetch_stall_cycles: 0 +mem_stall_cycles: 0 +stall_warp: 0 +wspawn: 0 +stalled: 0 +********************************** scheduler ********************************* +valid: 0 +PC: 0 +wid: 0 +rd: -1 rs1: -1 rs2: -1 +is_lw: 0 +is_sw: 0 +fetch_stall_cycles: 0 +mem_stall_cycles: 0 +stall_warp: 0 +wspawn: 0 +stalled: 0 +********************************** Decode ********************************* +valid: 0 +PC: 0 +wid: 0 +rd: -1 rs1: -1 rs2: -1 +is_lw: 0 +is_sw: 0 +fetch_stall_cycles: 0 +mem_stall_cycles: 0 +stall_warp: 0 +wspawn: 0 +stalled: 0 +********************************** Fetch ********************************* +valid: 1 +PC: 80000afc +wid: 0 +rd: 14 rs1: 3 rs2: -1 +is_lw: 1 +is_sw: 0 +fetch_stall_cycles: 1 +mem_stall_cycles: 3 +stall_warp: 0 +wspawn: 0 +stalled: 0 + + + +------------------------------------------------------ +CYCLE: 208 +Stalled Warps: +0 0 0 0 0 0 0 0 + +********************************** Writeback ********************************* +valid: 0 +PC: 0 +wid: 0 +rd: -1 rs1: -1 rs2: -1 +is_lw: 0 +is_sw: 0 +fetch_stall_cycles: 0 +mem_stall_cycles: 0 +stall_warp: 0 +wspawn: 0 +stalled: 0 +********************************** LSU ********************************* +valid: 0 +PC: 0 +wid: 3 +rd: -1 rs1: -1 rs2: -1 +is_lw: 0 +is_sw: 0 +fetch_stall_cycles: 0 +mem_stall_cycles: 0 +stall_warp: 0 +wspawn: 0 +stalled: 0 +********************************** execute_unit ********************************* +valid: 0 +PC: 0 +wid: 0 +rd: -1 rs1: -1 rs2: -1 +is_lw: 0 +is_sw: 0 +fetch_stall_cycles: 0 +mem_stall_cycles: 0 +stall_warp: 0 +wspawn: 0 +stalled: 0 +********************************** scheduler ********************************* +valid: 0 +PC: 0 +wid: 0 +rd: -1 rs1: -1 rs2: -1 +is_lw: 0 +is_sw: 0 +fetch_stall_cycles: 0 +mem_stall_cycles: 0 +stall_warp: 0 +wspawn: 0 +stalled: 0 +********************************** Decode ********************************* +valid: 0 +PC: 0 +wid: 0 +rd: -1 rs1: -1 rs2: -1 +is_lw: 0 +is_sw: 0 +fetch_stall_cycles: 0 +mem_stall_cycles: 0 +stall_warp: 0 +wspawn: 0 +stalled: 0 +********************************** Fetch ********************************* +valid: 1 +PC: 80000afc +wid: 0 +rd: 14 rs1: 3 rs2: -1 +is_lw: 1 +is_sw: 0 +fetch_stall_cycles: 0 +mem_stall_cycles: 3 +stall_warp: 0 +wspawn: 0 +stalled: 0 + + + +------------------------------------------------------ +CYCLE: 209 +Stalled Warps: +0 0 0 0 0 0 0 0 + +********************************** Writeback ********************************* +valid: 0 +PC: 0 +wid: 0 +rd: -1 rs1: -1 rs2: -1 +is_lw: 0 +is_sw: 0 +fetch_stall_cycles: 0 +mem_stall_cycles: 0 +stall_warp: 0 +wspawn: 0 +stalled: 0 +********************************** LSU ********************************* +valid: 0 +PC: 0 +wid: 3 +rd: -1 rs1: -1 rs2: -1 +is_lw: 0 +is_sw: 0 +fetch_stall_cycles: 0 +mem_stall_cycles: 0 +stall_warp: 0 +wspawn: 0 +stalled: 0 +********************************** execute_unit ********************************* +valid: 0 +PC: 0 +wid: 0 +rd: -1 rs1: -1 rs2: -1 +is_lw: 0 +is_sw: 0 +fetch_stall_cycles: 0 +mem_stall_cycles: 0 +stall_warp: 0 +wspawn: 0 +stalled: 0 +********************************** scheduler ********************************* +valid: 0 +PC: 0 +wid: 0 +rd: -1 rs1: -1 rs2: -1 +is_lw: 0 +is_sw: 0 +fetch_stall_cycles: 0 +mem_stall_cycles: 0 +stall_warp: 0 +wspawn: 0 +stalled: 0 +********************************** Decode ********************************* +valid: 1 +PC: 80000afc +wid: 0 +rd: 14 rs1: 3 rs2: -1 +is_lw: 1 +is_sw: 0 +fetch_stall_cycles: 0 +mem_stall_cycles: 3 +stall_warp: 0 +wspawn: 0 +stalled: 0 +DEBUG ../core.cpp:386: Core step stepping warp 0[1] +DEBUG ../core.cpp:683: in step pc=0x80000b00 +help: in PC: 80000b00 +CUrrent CODE: 14872783 +DEBUG ../core.cpp:703: Fetched at 0x80000b00 +DEBUG ../core.cpp:704: 0x80000b00: load; +DEBUG ../instruction.cpp:350: Begin instruction execute. +DEBUG ../instruction.cpp:2117: End instruction execute. +DEBUG ../core.cpp:717: Register state: + %r 0: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r 1: 8000003c 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r 2: 6ffff000 6fffec04 6fffe808 6fffe40c 00000000 00000000 00000000 00000000 (0) + %r 3: 80001808 80001808 80001808 80001808 00000000 00000000 00000000 00000000 (0) + %r 4: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r 5: 80000a6c 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r 6: 0000000f 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r 7: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r 8: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r 9: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r10: 00000000 00000001 00000001 00000001 00000000 00000000 00000000 00000000 (0) + %r11: 80000924 00000400 00000800 00000c00 00000000 00000000 00000000 00000000 (0) + %r12: 00000000 00000004 00000008 0000000c 00000000 00000000 00000000 00000000 (0) + %r13: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r14: 80001008 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r15: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r16: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r17: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r18: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r19: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r20: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r21: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r22: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r23: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r24: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r25: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r26: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r27: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r28: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r29: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r30: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r31: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) +DEBUG ../core.cpp:726: Thread mask: + 1 0 0 0 0 0 0 0 + + +DEBUG ../core.cpp:388: Now 1 active threads in 0 +********************************** Fetch ********************************* +valid: 1 +PC: 80000b00 +wid: 0 +rd: 15 rs1: 14 rs2: -1 +is_lw: 1 +is_sw: 0 +fetch_stall_cycles: 3 +mem_stall_cycles: 3 +stall_warp: 0 +wspawn: 0 +stalled: 0 + + + +------------------------------------------------------ +CYCLE: 210 +Stalled Warps: +0 0 0 0 0 0 0 0 + +********************************** Writeback ********************************* +valid: 0 +PC: 0 +wid: 0 +rd: -1 rs1: -1 rs2: -1 +is_lw: 0 +is_sw: 0 +fetch_stall_cycles: 0 +mem_stall_cycles: 0 +stall_warp: 0 +wspawn: 0 +stalled: 0 +********************************** LSU ********************************* +valid: 0 +PC: 0 +wid: 3 +rd: -1 rs1: -1 rs2: -1 +is_lw: 0 +is_sw: 0 +fetch_stall_cycles: 0 +mem_stall_cycles: 0 +stall_warp: 0 +wspawn: 0 +stalled: 0 +********************************** execute_unit ********************************* +valid: 0 +PC: 0 +wid: 0 +rd: -1 rs1: -1 rs2: -1 +is_lw: 0 +is_sw: 0 +fetch_stall_cycles: 0 +mem_stall_cycles: 0 +stall_warp: 0 +wspawn: 0 +stalled: 0 +********************************** scheduler ********************************* +valid: 1 +PC: 80000afc +wid: 0 +rd: 14 rs1: 3 rs2: -1 +is_lw: 1 +is_sw: 0 +fetch_stall_cycles: 0 +mem_stall_cycles: 3 +stall_warp: 0 +wspawn: 0 +stalled: 0 +********************************** Decode ********************************* +valid: 0 +PC: 0 +wid: 0 +rd: -1 rs1: -1 rs2: -1 +is_lw: 0 +is_sw: 0 +fetch_stall_cycles: 0 +mem_stall_cycles: 0 +stall_warp: 0 +wspawn: 0 +stalled: 0 +********************************** Fetch ********************************* +valid: 1 +PC: 80000b00 +wid: 0 +rd: 15 rs1: 14 rs2: -1 +is_lw: 1 +is_sw: 0 +fetch_stall_cycles: 2 +mem_stall_cycles: 3 +stall_warp: 0 +wspawn: 0 +stalled: 0 + + + +------------------------------------------------------ +CYCLE: 211 +Stalled Warps: +0 0 0 0 0 0 0 0 + +********************************** Writeback ********************************* +valid: 0 +PC: 0 +wid: 0 +rd: -1 rs1: -1 rs2: -1 +is_lw: 0 +is_sw: 0 +fetch_stall_cycles: 0 +mem_stall_cycles: 0 +stall_warp: 0 +wspawn: 0 +stalled: 0 +********************************** LSU ********************************* +valid: 1 +PC: 80000afc +wid: 0 +rd: 14 rs1: 3 rs2: -1 +is_lw: 1 +is_sw: 0 +fetch_stall_cycles: 0 +mem_stall_cycles: 2 +stall_warp: 0 +wspawn: 0 +stalled: 0 +********************************** execute_unit ********************************* +valid: 0 +PC: 0 +wid: 0 +rd: -1 rs1: -1 rs2: -1 +is_lw: 0 +is_sw: 0 +fetch_stall_cycles: 0 +mem_stall_cycles: 0 +stall_warp: 0 +wspawn: 0 +stalled: 0 +********************************** scheduler ********************************* +valid: 0 +PC: 0 +wid: 0 +rd: -1 rs1: -1 rs2: -1 +is_lw: 0 +is_sw: 0 +fetch_stall_cycles: 0 +mem_stall_cycles: 0 +stall_warp: 0 +wspawn: 0 +stalled: 0 +********************************** Decode ********************************* +valid: 0 +PC: 0 +wid: 0 +rd: -1 rs1: -1 rs2: -1 +is_lw: 0 +is_sw: 0 +fetch_stall_cycles: 0 +mem_stall_cycles: 0 +stall_warp: 0 +wspawn: 0 +stalled: 0 +********************************** Fetch ********************************* +valid: 1 +PC: 80000b00 +wid: 0 +rd: 15 rs1: 14 rs2: -1 +is_lw: 1 +is_sw: 0 +fetch_stall_cycles: 1 +mem_stall_cycles: 3 +stall_warp: 0 +wspawn: 0 +stalled: 0 + + + +------------------------------------------------------ +CYCLE: 212 +Stalled Warps: +0 0 0 0 0 0 0 0 + +********************************** Writeback ********************************* +valid: 0 +PC: 0 +wid: 0 +rd: -1 rs1: -1 rs2: -1 +is_lw: 0 +is_sw: 0 +fetch_stall_cycles: 0 +mem_stall_cycles: 0 +stall_warp: 0 +wspawn: 0 +stalled: 0 +********************************** LSU ********************************* +valid: 1 +PC: 80000afc +wid: 0 +rd: 14 rs1: 3 rs2: -1 +is_lw: 1 +is_sw: 0 +fetch_stall_cycles: 0 +mem_stall_cycles: 1 +stall_warp: 0 +wspawn: 0 +stalled: 0 +********************************** execute_unit ********************************* +valid: 0 +PC: 0 +wid: 0 +rd: -1 rs1: -1 rs2: -1 +is_lw: 0 +is_sw: 0 +fetch_stall_cycles: 0 +mem_stall_cycles: 0 +stall_warp: 0 +wspawn: 0 +stalled: 0 +********************************** scheduler ********************************* +valid: 0 +PC: 0 +wid: 0 +rd: -1 rs1: -1 rs2: -1 +is_lw: 0 +is_sw: 0 +fetch_stall_cycles: 0 +mem_stall_cycles: 0 +stall_warp: 0 +wspawn: 0 +stalled: 0 +********************************** Decode ********************************* +valid: 0 +PC: 0 +wid: 0 +rd: -1 rs1: -1 rs2: -1 +is_lw: 0 +is_sw: 0 +fetch_stall_cycles: 0 +mem_stall_cycles: 0 +stall_warp: 0 +wspawn: 0 +stalled: 0 +********************************** Fetch ********************************* +valid: 1 +PC: 80000b00 +wid: 0 +rd: 15 rs1: 14 rs2: -1 +is_lw: 1 +is_sw: 0 +fetch_stall_cycles: 0 +mem_stall_cycles: 3 +stall_warp: 0 +wspawn: 0 +stalled: 0 + + + +------------------------------------------------------ +CYCLE: 213 +Stalled Warps: +0 0 0 0 0 0 0 0 + +********************************** Writeback ********************************* +valid: 0 +PC: 0 +wid: 0 +rd: -1 rs1: -1 rs2: -1 +is_lw: 0 +is_sw: 0 +fetch_stall_cycles: 0 +mem_stall_cycles: 0 +stall_warp: 0 +wspawn: 0 +stalled: 0 +********************************** LSU ********************************* +valid: 1 +PC: 80000afc +wid: 0 +rd: 14 rs1: 3 rs2: -1 +is_lw: 1 +is_sw: 0 +fetch_stall_cycles: 0 +mem_stall_cycles: 0 +stall_warp: 0 +wspawn: 0 +stalled: 0 +********************************** execute_unit ********************************* +valid: 0 +PC: 0 +wid: 0 +rd: -1 rs1: -1 rs2: -1 +is_lw: 0 +is_sw: 0 +fetch_stall_cycles: 0 +mem_stall_cycles: 0 +stall_warp: 0 +wspawn: 0 +stalled: 0 +********************************** scheduler ********************************* +valid: 0 +PC: 0 +wid: 0 +rd: -1 rs1: -1 rs2: -1 +is_lw: 0 +is_sw: 0 +fetch_stall_cycles: 0 +mem_stall_cycles: 0 +stall_warp: 0 +wspawn: 0 +stalled: 0 +********************************** Decode ********************************* +valid: 1 +PC: 80000b00 +wid: 0 +rd: 15 rs1: 14 rs2: -1 +is_lw: 1 +is_sw: 0 +fetch_stall_cycles: 0 +mem_stall_cycles: 3 +stall_warp: 0 +wspawn: 0 +stalled: 0 +DEBUG ../core.cpp:386: Core step stepping warp 0[1] +DEBUG ../core.cpp:683: in step pc=0x80000b04 +help: in PC: 80000b04 +CUrrent CODE: 4078c63 +DEBUG ../core.cpp:703: Fetched at 0x80000b04 +DEBUG ../core.cpp:704: 0x80000b04: branch; +DEBUG ../instruction.cpp:350: Begin instruction execute. +DEBUG ../instruction.cpp:2117: End instruction execute. +Next PC: 80000b5c +DEBUG ../core.cpp:717: Register state: + %r 0: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r 1: 8000003c 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r 2: 6ffff000 6fffec04 6fffe808 6fffe40c 00000000 00000000 00000000 00000000 (0) + %r 3: 80001808 80001808 80001808 80001808 00000000 00000000 00000000 00000000 (0) + %r 4: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r 5: 80000a6c 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r 6: 0000000f 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r 7: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r 8: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r 9: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r10: 00000000 00000001 00000001 00000001 00000000 00000000 00000000 00000000 (0) + %r11: 80000924 00000400 00000800 00000c00 00000000 00000000 00000000 00000000 (0) + %r12: 00000000 00000004 00000008 0000000c 00000000 00000000 00000000 00000000 (0) + %r13: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r14: 80001008 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r15: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r16: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r17: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r18: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r19: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r20: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r21: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r22: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r23: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r24: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r25: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r26: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r27: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r28: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r29: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r30: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r31: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) +DEBUG ../core.cpp:726: Thread mask: + 1 0 0 0 0 0 0 0 + + +DEBUG ../core.cpp:388: Now 1 active threads in 0 +********************************** Fetch ********************************* +valid: 1 +PC: 80000b04 +wid: 0 +rd: -1 rs1: 15 rs2: 0 +is_lw: 0 +is_sw: 0 +fetch_stall_cycles: 0 +mem_stall_cycles: 0 +stall_warp: 1 +wspawn: 0 +stalled: 0 + + + +------------------------------------------------------ +CYCLE: 214 +Stalled Warps: +1 0 0 0 0 0 0 0 + +********************************** Writeback ********************************* +valid: 1 +PC: 80000afc +wid: 0 +rd: 14 rs1: 3 rs2: -1 +is_lw: 1 +is_sw: 0 +fetch_stall_cycles: 0 +mem_stall_cycles: 0 +stall_warp: 0 +wspawn: 0 +stalled: 0 +********************************** LSU ********************************* +valid: 0 +PC: 0 +wid: 1 +rd: -1 rs1: -1 rs2: -1 +is_lw: 0 +is_sw: 0 +fetch_stall_cycles: 0 +mem_stall_cycles: 0 +stall_warp: 0 +wspawn: 0 +stalled: 0 +********************************** execute_unit ********************************* +valid: 0 +PC: 0 +wid: 0 +rd: -1 rs1: -1 rs2: -1 +is_lw: 0 +is_sw: 0 +fetch_stall_cycles: 0 +mem_stall_cycles: 0 +stall_warp: 0 +wspawn: 0 +stalled: 0 +********************************** scheduler ********************************* +valid: 1 +PC: 80000b00 +wid: 0 +rd: 15 rs1: 14 rs2: -1 +is_lw: 1 +is_sw: 0 +fetch_stall_cycles: 0 +mem_stall_cycles: 3 +stall_warp: 0 +wspawn: 0 +stalled: 0 +********************************** Decode ********************************* +valid: 1 +PC: 80000b04 +wid: 0 +rd: -1 rs1: 15 rs2: 0 +is_lw: 0 +is_sw: 0 +fetch_stall_cycles: 0 +mem_stall_cycles: 0 +stall_warp: 1 +wspawn: 0 +stalled: 0 +********************************** Fetch ********************************* +valid: 0 +PC: 0 +wid: 1 +rd: -1 rs1: -1 rs2: -1 +is_lw: 0 +is_sw: 0 +fetch_stall_cycles: 0 +mem_stall_cycles: 0 +stall_warp: 0 +wspawn: 0 +stalled: 0 + + + +------------------------------------------------------ +CYCLE: 215 +Stalled Warps: +1 0 0 0 0 0 0 0 + +********************************** Writeback ********************************* +valid: 0 +PC: 0 +wid: 2 +rd: -1 rs1: -1 rs2: -1 +is_lw: 0 +is_sw: 0 +fetch_stall_cycles: 0 +mem_stall_cycles: 0 +stall_warp: 0 +wspawn: 0 +stalled: 0 +********************************** LSU ********************************* +valid: 1 +PC: 80000b00 +wid: 0 +rd: 15 rs1: 14 rs2: -1 +is_lw: 1 +is_sw: 0 +fetch_stall_cycles: 0 +mem_stall_cycles: 2 +stall_warp: 0 +wspawn: 0 +stalled: 0 +********************************** execute_unit ********************************* +valid: 0 +PC: 0 +wid: 2 +rd: -1 rs1: -1 rs2: -1 +is_lw: 0 +is_sw: 0 +fetch_stall_cycles: 0 +mem_stall_cycles: 0 +stall_warp: 0 +wspawn: 0 +stalled: 0 +********************************** scheduler ********************************* +valid: 1 +PC: 80000b04 +wid: 0 +rd: -1 rs1: 15 rs2: 0 +is_lw: 0 +is_sw: 0 +fetch_stall_cycles: 0 +mem_stall_cycles: 0 +stall_warp: 1 +wspawn: 0 +stalled: 0 +********************************** Decode ********************************* +valid: 0 +PC: 0 +wid: 1 +rd: -1 rs1: -1 rs2: -1 +is_lw: 0 +is_sw: 0 +fetch_stall_cycles: 0 +mem_stall_cycles: 0 +stall_warp: 0 +wspawn: 0 +stalled: 0 +********************************** Fetch ********************************* +valid: 0 +PC: 0 +wid: 2 +rd: -1 rs1: -1 rs2: -1 +is_lw: 0 +is_sw: 0 +fetch_stall_cycles: 0 +mem_stall_cycles: 0 +stall_warp: 0 +wspawn: 0 +stalled: 0 + + + +------------------------------------------------------ +CYCLE: 216 +Stalled Warps: +1 0 0 0 0 0 0 0 + +********************************** Writeback ********************************* +valid: 0 +PC: 0 +wid: 3 +rd: -1 rs1: -1 rs2: -1 +is_lw: 0 +is_sw: 0 +fetch_stall_cycles: 0 +mem_stall_cycles: 0 +stall_warp: 0 +wspawn: 0 +stalled: 0 +********************************** LSU ********************************* +valid: 1 +PC: 80000b00 +wid: 0 +rd: 15 rs1: 14 rs2: -1 +is_lw: 1 +is_sw: 0 +fetch_stall_cycles: 0 +mem_stall_cycles: 1 +stall_warp: 0 +wspawn: 0 +stalled: 0 +&&&&&&&&&&&&&&&&&&&&&&&& EXECUTE SRCS NOT READY +********************************** execute_unit ********************************* +valid: 0 +PC: 0 +wid: 2 +rd: -1 rs1: -1 rs2: -1 +is_lw: 0 +is_sw: 0 +fetch_stall_cycles: 0 +mem_stall_cycles: 0 +stall_warp: 0 +wspawn: 0 +stalled: 0 +********************************** scheduler ********************************* +valid: 1 +PC: 80000b04 +wid: 0 +rd: -1 rs1: 15 rs2: 0 +is_lw: 0 +is_sw: 0 +fetch_stall_cycles: 0 +mem_stall_cycles: 0 +stall_warp: 1 +wspawn: 0 +stalled: 1 +********************************** Decode ********************************* +valid: 0 +PC: 0 +wid: 1 +rd: -1 rs1: -1 rs2: -1 +is_lw: 0 +is_sw: 0 +fetch_stall_cycles: 0 +mem_stall_cycles: 0 +stall_warp: 0 +wspawn: 0 +stalled: 0 +********************************** Fetch ********************************* +valid: 0 +PC: 0 +wid: 2 +rd: -1 rs1: -1 rs2: -1 +is_lw: 0 +is_sw: 0 +fetch_stall_cycles: 0 +mem_stall_cycles: 0 +stall_warp: 0 +wspawn: 0 +stalled: 0 + + + +------------------------------------------------------ +CYCLE: 217 +Stalled Warps: +1 0 0 0 0 0 0 0 + +********************************** Writeback ********************************* +valid: 0 +PC: 0 +wid: 3 +rd: -1 rs1: -1 rs2: -1 +is_lw: 0 +is_sw: 0 +fetch_stall_cycles: 0 +mem_stall_cycles: 0 +stall_warp: 0 +wspawn: 0 +stalled: 0 +********************************** LSU ********************************* +valid: 1 +PC: 80000b00 +wid: 0 +rd: 15 rs1: 14 rs2: -1 +is_lw: 1 +is_sw: 0 +fetch_stall_cycles: 0 +mem_stall_cycles: 0 +stall_warp: 0 +wspawn: 0 +stalled: 0 +&&&&&&&&&&&&&&&&&&&&&&&& EXECUTE SRCS NOT READY +********************************** execute_unit ********************************* +valid: 0 +PC: 0 +wid: 2 +rd: -1 rs1: -1 rs2: -1 +is_lw: 0 +is_sw: 0 +fetch_stall_cycles: 0 +mem_stall_cycles: 0 +stall_warp: 0 +wspawn: 0 +stalled: 0 +********************************** scheduler ********************************* +valid: 1 +PC: 80000b04 +wid: 0 +rd: -1 rs1: 15 rs2: 0 +is_lw: 0 +is_sw: 0 +fetch_stall_cycles: 0 +mem_stall_cycles: 0 +stall_warp: 1 +wspawn: 0 +stalled: 1 +********************************** Decode ********************************* +valid: 0 +PC: 0 +wid: 1 +rd: -1 rs1: -1 rs2: -1 +is_lw: 0 +is_sw: 0 +fetch_stall_cycles: 0 +mem_stall_cycles: 0 +stall_warp: 0 +wspawn: 0 +stalled: 0 +********************************** Fetch ********************************* +valid: 0 +PC: 0 +wid: 2 +rd: -1 rs1: -1 rs2: -1 +is_lw: 0 +is_sw: 0 +fetch_stall_cycles: 0 +mem_stall_cycles: 0 +stall_warp: 0 +wspawn: 0 +stalled: 0 + + + +------------------------------------------------------ +CYCLE: 218 +Stalled Warps: +1 0 0 0 0 0 0 0 + +********************************** Writeback ********************************* +valid: 1 +PC: 80000b00 +wid: 0 +rd: 15 rs1: 14 rs2: -1 +is_lw: 1 +is_sw: 0 +fetch_stall_cycles: 0 +mem_stall_cycles: 0 +stall_warp: 0 +wspawn: 0 +stalled: 0 +********************************** LSU ********************************* +valid: 0 +PC: 0 +wid: 3 +rd: -1 rs1: -1 rs2: -1 +is_lw: 0 +is_sw: 0 +fetch_stall_cycles: 0 +mem_stall_cycles: 0 +stall_warp: 0 +wspawn: 0 +stalled: 0 +&&&&&&&&&&&&&&&&&&&&&&&& EXECUTE SRCS NOT READY +********************************** execute_unit ********************************* +valid: 0 +PC: 0 +wid: 2 +rd: -1 rs1: -1 rs2: -1 +is_lw: 0 +is_sw: 0 +fetch_stall_cycles: 0 +mem_stall_cycles: 0 +stall_warp: 0 +wspawn: 0 +stalled: 0 +********************************** scheduler ********************************* +valid: 1 +PC: 80000b04 +wid: 0 +rd: -1 rs1: 15 rs2: 0 +is_lw: 0 +is_sw: 0 +fetch_stall_cycles: 0 +mem_stall_cycles: 0 +stall_warp: 1 +wspawn: 0 +stalled: 1 +********************************** Decode ********************************* +valid: 0 +PC: 0 +wid: 1 +rd: -1 rs1: -1 rs2: -1 +is_lw: 0 +is_sw: 0 +fetch_stall_cycles: 0 +mem_stall_cycles: 0 +stall_warp: 0 +wspawn: 0 +stalled: 0 +********************************** Fetch ********************************* +valid: 0 +PC: 0 +wid: 2 +rd: -1 rs1: -1 rs2: -1 +is_lw: 0 +is_sw: 0 +fetch_stall_cycles: 0 +mem_stall_cycles: 0 +stall_warp: 0 +wspawn: 0 +stalled: 0 + + + +------------------------------------------------------ +CYCLE: 219 +Stalled Warps: +1 0 0 0 0 0 0 0 + +********************************** Writeback ********************************* +valid: 0 +PC: 0 +wid: 3 +rd: -1 rs1: -1 rs2: -1 +is_lw: 0 +is_sw: 0 +fetch_stall_cycles: 0 +mem_stall_cycles: 0 +stall_warp: 0 +wspawn: 0 +stalled: 0 +********************************** LSU ********************************* +valid: 0 +PC: 0 +wid: 3 +rd: -1 rs1: -1 rs2: -1 +is_lw: 0 +is_sw: 0 +fetch_stall_cycles: 0 +mem_stall_cycles: 0 +stall_warp: 0 +wspawn: 0 +stalled: 0 +********************************** execute_unit ********************************* +valid: 1 +PC: 80000b04 +wid: 0 +rd: -1 rs1: 15 rs2: 0 +is_lw: 0 +is_sw: 0 +fetch_stall_cycles: 0 +mem_stall_cycles: 0 +stall_warp: 1 +wspawn: 0 +stalled: 0 +********************************** scheduler ********************************* +valid: 0 +PC: 0 +wid: 1 +rd: -1 rs1: -1 rs2: -1 +is_lw: 0 +is_sw: 0 +fetch_stall_cycles: 0 +mem_stall_cycles: 0 +stall_warp: 0 +wspawn: 0 +stalled: 0 +********************************** Decode ********************************* +valid: 0 +PC: 0 +wid: 2 +rd: -1 rs1: -1 rs2: -1 +is_lw: 0 +is_sw: 0 +fetch_stall_cycles: 0 +mem_stall_cycles: 0 +stall_warp: 0 +wspawn: 0 +stalled: 0 +********************************** Fetch ********************************* +valid: 0 +PC: 0 +wid: 3 +rd: -1 rs1: -1 rs2: -1 +is_lw: 0 +is_sw: 0 +fetch_stall_cycles: 0 +mem_stall_cycles: 0 +stall_warp: 0 +wspawn: 0 +stalled: 0 + + + +------------------------------------------------------ +CYCLE: 220 +Stalled Warps: +1 0 0 0 0 0 0 0 + +********************************** Writeback ********************************* +valid: 1 +PC: 80000b04 +wid: 0 +rd: -1 rs1: 15 rs2: 0 +is_lw: 0 +is_sw: 0 +fetch_stall_cycles: 0 +mem_stall_cycles: 0 +stall_warp: 1 +wspawn: 0 +stalled: 0 +********************************** LSU ********************************* +valid: 0 +PC: 0 +wid: 3 +rd: -1 rs1: -1 rs2: -1 +is_lw: 0 +is_sw: 0 +fetch_stall_cycles: 0 +mem_stall_cycles: 0 +stall_warp: 0 +wspawn: 0 +stalled: 0 +********************************** execute_unit ********************************* +valid: 0 +PC: 0 +wid: 1 +rd: -1 rs1: -1 rs2: -1 +is_lw: 0 +is_sw: 0 +fetch_stall_cycles: 0 +mem_stall_cycles: 0 +stall_warp: 0 +wspawn: 0 +stalled: 0 +********************************** scheduler ********************************* +valid: 0 +PC: 0 +wid: 2 +rd: -1 rs1: -1 rs2: -1 +is_lw: 0 +is_sw: 0 +fetch_stall_cycles: 0 +mem_stall_cycles: 0 +stall_warp: 0 +wspawn: 0 +stalled: 0 +********************************** Decode ********************************* +valid: 0 +PC: 0 +wid: 3 +rd: -1 rs1: -1 rs2: -1 +is_lw: 0 +is_sw: 0 +fetch_stall_cycles: 0 +mem_stall_cycles: 0 +stall_warp: 0 +wspawn: 0 +stalled: 0 +********************************** Fetch ********************************* +valid: 0 +PC: 0 +wid: 4 +rd: -1 rs1: -1 rs2: -1 +is_lw: 0 +is_sw: 0 +fetch_stall_cycles: 0 +mem_stall_cycles: 0 +stall_warp: 0 +wspawn: 0 +stalled: 0 + + + +------------------------------------------------------ +CYCLE: 221 +Stalled Warps: +1 0 0 0 0 0 0 0 + +********************************** Writeback ********************************* +valid: 0 +PC: 0 +wid: 5 +rd: -1 rs1: -1 rs2: -1 +is_lw: 0 +is_sw: 0 +fetch_stall_cycles: 0 +mem_stall_cycles: 0 +stall_warp: 0 +wspawn: 0 +stalled: 0 +********************************** LSU ********************************* +valid: 0 +PC: 0 +wid: 3 +rd: -1 rs1: -1 rs2: -1 +is_lw: 0 +is_sw: 0 +fetch_stall_cycles: 0 +mem_stall_cycles: 0 +stall_warp: 0 +wspawn: 0 +stalled: 0 +********************************** execute_unit ********************************* +valid: 0 +PC: 0 +wid: 2 +rd: -1 rs1: -1 rs2: -1 +is_lw: 0 +is_sw: 0 +fetch_stall_cycles: 0 +mem_stall_cycles: 0 +stall_warp: 0 +wspawn: 0 +stalled: 0 +********************************** scheduler ********************************* +valid: 0 +PC: 0 +wid: 3 +rd: -1 rs1: -1 rs2: -1 +is_lw: 0 +is_sw: 0 +fetch_stall_cycles: 0 +mem_stall_cycles: 0 +stall_warp: 0 +wspawn: 0 +stalled: 0 +********************************** Decode ********************************* +valid: 0 +PC: 0 +wid: 4 +rd: -1 rs1: -1 rs2: -1 +is_lw: 0 +is_sw: 0 +fetch_stall_cycles: 0 +mem_stall_cycles: 0 +stall_warp: 0 +wspawn: 0 +stalled: 0 +********************************** Fetch ********************************* +valid: 0 +PC: 0 +wid: 5 +rd: -1 rs1: -1 rs2: -1 +is_lw: 0 +is_sw: 0 +fetch_stall_cycles: 0 +mem_stall_cycles: 0 +stall_warp: 0 +wspawn: 0 +stalled: 0 +Warp ID 0 is running + + + +------------------------------------------------------ +CYCLE: 222 +Stalled Warps: +0 0 0 0 0 0 0 0 + +********************************** Writeback ********************************* +valid: 0 +PC: 0 +wid: 0 +rd: -1 rs1: -1 rs2: -1 +is_lw: 0 +is_sw: 0 +fetch_stall_cycles: 0 +mem_stall_cycles: 0 +stall_warp: 0 +wspawn: 0 +stalled: 0 +********************************** LSU ********************************* +valid: 0 +PC: 0 +wid: 3 +rd: -1 rs1: -1 rs2: -1 +is_lw: 0 +is_sw: 0 +fetch_stall_cycles: 0 +mem_stall_cycles: 0 +stall_warp: 0 +wspawn: 0 +stalled: 0 +********************************** execute_unit ********************************* +valid: 0 +PC: 0 +wid: 3 +rd: -1 rs1: -1 rs2: -1 +is_lw: 0 +is_sw: 0 +fetch_stall_cycles: 0 +mem_stall_cycles: 0 +stall_warp: 0 +wspawn: 0 +stalled: 0 +********************************** scheduler ********************************* +valid: 0 +PC: 0 +wid: 4 +rd: -1 rs1: -1 rs2: -1 +is_lw: 0 +is_sw: 0 +fetch_stall_cycles: 0 +mem_stall_cycles: 0 +stall_warp: 0 +wspawn: 0 +stalled: 0 +********************************** Decode ********************************* +valid: 0 +PC: 0 +wid: 5 +rd: -1 rs1: -1 rs2: -1 +is_lw: 0 +is_sw: 0 +fetch_stall_cycles: 0 +mem_stall_cycles: 0 +stall_warp: 0 +wspawn: 0 +stalled: 0 +DEBUG ../core.cpp:386: Core step stepping warp 0[1] +DEBUG ../core.cpp:683: in step pc=0x80000b5c +help: in PC: 80000b5c +CUrrent CODE: 14c70793 +DEBUG ../core.cpp:703: Fetched at 0x80000b5c +DEBUG ../core.cpp:704: 0x80000b5c: i_type; +DEBUG ../instruction.cpp:350: Begin instruction execute. +DEBUG ../instruction.cpp:2117: End instruction execute. +DEBUG ../core.cpp:717: Register state: + %r 0: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r 1: 8000003c 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r 2: 6ffff000 6fffec04 6fffe808 6fffe40c 00000000 00000000 00000000 00000000 (0) + %r 3: 80001808 80001808 80001808 80001808 00000000 00000000 00000000 00000000 (0) + %r 4: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r 5: 80000a6c 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r 6: 0000000f 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r 7: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r 8: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r 9: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r10: 00000000 00000001 00000001 00000001 00000000 00000000 00000000 00000000 (0) + %r11: 80000924 00000400 00000800 00000c00 00000000 00000000 00000000 00000000 (0) + %r12: 00000000 00000004 00000008 0000000c 00000000 00000000 00000000 00000000 (0) + %r13: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r14: 80001008 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r15: 80001154 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r16: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r17: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r18: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r19: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r20: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r21: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r22: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r23: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r24: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r25: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r26: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r27: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r28: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r29: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r30: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r31: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) +DEBUG ../core.cpp:726: Thread mask: + 1 0 0 0 0 0 0 0 + + +DEBUG ../core.cpp:388: Now 1 active threads in 0 +********************************** Fetch ********************************* +valid: 1 +PC: 80000b5c +wid: 0 +rd: 15 rs1: 14 rs2: -1 +is_lw: 0 +is_sw: 0 +fetch_stall_cycles: 3 +mem_stall_cycles: 0 +stall_warp: 0 +wspawn: 0 +stalled: 0 + + + +------------------------------------------------------ +CYCLE: 223 +Stalled Warps: +0 0 0 0 0 0 0 0 + +********************************** Writeback ********************************* +valid: 0 +PC: 0 +wid: 0 +rd: -1 rs1: -1 rs2: -1 +is_lw: 0 +is_sw: 0 +fetch_stall_cycles: 0 +mem_stall_cycles: 0 +stall_warp: 0 +wspawn: 0 +stalled: 0 +********************************** LSU ********************************* +valid: 0 +PC: 0 +wid: 3 +rd: -1 rs1: -1 rs2: -1 +is_lw: 0 +is_sw: 0 +fetch_stall_cycles: 0 +mem_stall_cycles: 0 +stall_warp: 0 +wspawn: 0 +stalled: 0 +********************************** execute_unit ********************************* +valid: 0 +PC: 0 +wid: 4 +rd: -1 rs1: -1 rs2: -1 +is_lw: 0 +is_sw: 0 +fetch_stall_cycles: 0 +mem_stall_cycles: 0 +stall_warp: 0 +wspawn: 0 +stalled: 0 +********************************** scheduler ********************************* +valid: 0 +PC: 0 +wid: 5 +rd: -1 rs1: -1 rs2: -1 +is_lw: 0 +is_sw: 0 +fetch_stall_cycles: 0 +mem_stall_cycles: 0 +stall_warp: 0 +wspawn: 0 +stalled: 0 +********************************** Decode ********************************* +valid: 0 +PC: 0 +wid: 0 +rd: -1 rs1: -1 rs2: -1 +is_lw: 0 +is_sw: 0 +fetch_stall_cycles: 0 +mem_stall_cycles: 0 +stall_warp: 0 +wspawn: 0 +stalled: 0 +********************************** Fetch ********************************* +valid: 1 +PC: 80000b5c +wid: 0 +rd: 15 rs1: 14 rs2: -1 +is_lw: 0 +is_sw: 0 +fetch_stall_cycles: 2 +mem_stall_cycles: 0 +stall_warp: 0 +wspawn: 0 +stalled: 0 + + + +------------------------------------------------------ +CYCLE: 224 +Stalled Warps: +0 0 0 0 0 0 0 0 + +********************************** Writeback ********************************* +valid: 0 +PC: 0 +wid: 0 +rd: -1 rs1: -1 rs2: -1 +is_lw: 0 +is_sw: 0 +fetch_stall_cycles: 0 +mem_stall_cycles: 0 +stall_warp: 0 +wspawn: 0 +stalled: 0 +********************************** LSU ********************************* +valid: 0 +PC: 0 +wid: 3 +rd: -1 rs1: -1 rs2: -1 +is_lw: 0 +is_sw: 0 +fetch_stall_cycles: 0 +mem_stall_cycles: 0 +stall_warp: 0 +wspawn: 0 +stalled: 0 +********************************** execute_unit ********************************* +valid: 0 +PC: 0 +wid: 5 +rd: -1 rs1: -1 rs2: -1 +is_lw: 0 +is_sw: 0 +fetch_stall_cycles: 0 +mem_stall_cycles: 0 +stall_warp: 0 +wspawn: 0 +stalled: 0 +********************************** scheduler ********************************* +valid: 0 +PC: 0 +wid: 0 +rd: -1 rs1: -1 rs2: -1 +is_lw: 0 +is_sw: 0 +fetch_stall_cycles: 0 +mem_stall_cycles: 0 +stall_warp: 0 +wspawn: 0 +stalled: 0 +********************************** Decode ********************************* +valid: 0 +PC: 0 +wid: 0 +rd: -1 rs1: -1 rs2: -1 +is_lw: 0 +is_sw: 0 +fetch_stall_cycles: 0 +mem_stall_cycles: 0 +stall_warp: 0 +wspawn: 0 +stalled: 0 +********************************** Fetch ********************************* +valid: 1 +PC: 80000b5c +wid: 0 +rd: 15 rs1: 14 rs2: -1 +is_lw: 0 +is_sw: 0 +fetch_stall_cycles: 1 +mem_stall_cycles: 0 +stall_warp: 0 +wspawn: 0 +stalled: 0 + + + +------------------------------------------------------ +CYCLE: 225 +Stalled Warps: +0 0 0 0 0 0 0 0 + +********************************** Writeback ********************************* +valid: 0 +PC: 0 +wid: 0 +rd: -1 rs1: -1 rs2: -1 +is_lw: 0 +is_sw: 0 +fetch_stall_cycles: 0 +mem_stall_cycles: 0 +stall_warp: 0 +wspawn: 0 +stalled: 0 +********************************** LSU ********************************* +valid: 0 +PC: 0 +wid: 3 +rd: -1 rs1: -1 rs2: -1 +is_lw: 0 +is_sw: 0 +fetch_stall_cycles: 0 +mem_stall_cycles: 0 +stall_warp: 0 +wspawn: 0 +stalled: 0 +********************************** execute_unit ********************************* +valid: 0 +PC: 0 +wid: 0 +rd: -1 rs1: -1 rs2: -1 +is_lw: 0 +is_sw: 0 +fetch_stall_cycles: 0 +mem_stall_cycles: 0 +stall_warp: 0 +wspawn: 0 +stalled: 0 +********************************** scheduler ********************************* +valid: 0 +PC: 0 +wid: 0 +rd: -1 rs1: -1 rs2: -1 +is_lw: 0 +is_sw: 0 +fetch_stall_cycles: 0 +mem_stall_cycles: 0 +stall_warp: 0 +wspawn: 0 +stalled: 0 +********************************** Decode ********************************* +valid: 0 +PC: 0 +wid: 0 +rd: -1 rs1: -1 rs2: -1 +is_lw: 0 +is_sw: 0 +fetch_stall_cycles: 0 +mem_stall_cycles: 0 +stall_warp: 0 +wspawn: 0 +stalled: 0 +********************************** Fetch ********************************* +valid: 1 +PC: 80000b5c +wid: 0 +rd: 15 rs1: 14 rs2: -1 +is_lw: 0 +is_sw: 0 +fetch_stall_cycles: 0 +mem_stall_cycles: 0 +stall_warp: 0 +wspawn: 0 +stalled: 0 + + + +------------------------------------------------------ +CYCLE: 226 +Stalled Warps: +0 0 0 0 0 0 0 0 + +********************************** Writeback ********************************* +valid: 0 +PC: 0 +wid: 0 +rd: -1 rs1: -1 rs2: -1 +is_lw: 0 +is_sw: 0 +fetch_stall_cycles: 0 +mem_stall_cycles: 0 +stall_warp: 0 +wspawn: 0 +stalled: 0 +********************************** LSU ********************************* +valid: 0 +PC: 0 +wid: 3 +rd: -1 rs1: -1 rs2: -1 +is_lw: 0 +is_sw: 0 +fetch_stall_cycles: 0 +mem_stall_cycles: 0 +stall_warp: 0 +wspawn: 0 +stalled: 0 +********************************** execute_unit ********************************* +valid: 0 +PC: 0 +wid: 0 +rd: -1 rs1: -1 rs2: -1 +is_lw: 0 +is_sw: 0 +fetch_stall_cycles: 0 +mem_stall_cycles: 0 +stall_warp: 0 +wspawn: 0 +stalled: 0 +********************************** scheduler ********************************* +valid: 0 +PC: 0 +wid: 0 +rd: -1 rs1: -1 rs2: -1 +is_lw: 0 +is_sw: 0 +fetch_stall_cycles: 0 +mem_stall_cycles: 0 +stall_warp: 0 +wspawn: 0 +stalled: 0 +********************************** Decode ********************************* +valid: 1 +PC: 80000b5c +wid: 0 +rd: 15 rs1: 14 rs2: -1 +is_lw: 0 +is_sw: 0 +fetch_stall_cycles: 0 +mem_stall_cycles: 0 +stall_warp: 0 +wspawn: 0 +stalled: 0 +DEBUG ../core.cpp:386: Core step stepping warp 0[1] +DEBUG ../core.cpp:683: in step pc=0x80000b60 +help: in PC: 80000b60 +CUrrent CODE: 14f72423 +DEBUG ../core.cpp:703: Fetched at 0x80000b60 +DEBUG ../core.cpp:704: 0x80000b60: store; +DEBUG ../instruction.cpp:350: Begin instruction execute. +STORE MEM ADDRESS: 80001008 + 148 +DEBUG ../instruction.cpp:2117: End instruction execute. +DEBUG ../core.cpp:717: Register state: + %r 0: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r 1: 8000003c 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r 2: 6ffff000 6fffec04 6fffe808 6fffe40c 00000000 00000000 00000000 00000000 (0) + %r 3: 80001808 80001808 80001808 80001808 00000000 00000000 00000000 00000000 (0) + %r 4: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r 5: 80000a6c 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r 6: 0000000f 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r 7: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r 8: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r 9: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r10: 00000000 00000001 00000001 00000001 00000000 00000000 00000000 00000000 (0) + %r11: 80000924 00000400 00000800 00000c00 00000000 00000000 00000000 00000000 (0) + %r12: 00000000 00000004 00000008 0000000c 00000000 00000000 00000000 00000000 (0) + %r13: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r14: 80001008 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r15: 80001154 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r16: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r17: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r18: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r19: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r20: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r21: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r22: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r23: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r24: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r25: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r26: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r27: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r28: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r29: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r30: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r31: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) +DEBUG ../core.cpp:726: Thread mask: + 1 0 0 0 0 0 0 0 + + +DEBUG ../core.cpp:388: Now 1 active threads in 0 +********************************** Fetch ********************************* +valid: 1 +PC: 80000b60 +wid: 0 +rd: -1 rs1: 14 rs2: 15 +is_lw: 0 +is_sw: 1 +fetch_stall_cycles: 3 +mem_stall_cycles: 0 +stall_warp: 0 +wspawn: 0 +stalled: 0 + + + +------------------------------------------------------ +CYCLE: 227 +Stalled Warps: +0 0 0 0 0 0 0 0 + +********************************** Writeback ********************************* +valid: 0 +PC: 0 +wid: 0 +rd: -1 rs1: -1 rs2: -1 +is_lw: 0 +is_sw: 0 +fetch_stall_cycles: 0 +mem_stall_cycles: 0 +stall_warp: 0 +wspawn: 0 +stalled: 0 +********************************** LSU ********************************* +valid: 0 +PC: 0 +wid: 3 +rd: -1 rs1: -1 rs2: -1 +is_lw: 0 +is_sw: 0 +fetch_stall_cycles: 0 +mem_stall_cycles: 0 +stall_warp: 0 +wspawn: 0 +stalled: 0 +********************************** execute_unit ********************************* +valid: 0 +PC: 0 +wid: 0 +rd: -1 rs1: -1 rs2: -1 +is_lw: 0 +is_sw: 0 +fetch_stall_cycles: 0 +mem_stall_cycles: 0 +stall_warp: 0 +wspawn: 0 +stalled: 0 +********************************** scheduler ********************************* +valid: 1 +PC: 80000b5c +wid: 0 +rd: 15 rs1: 14 rs2: -1 +is_lw: 0 +is_sw: 0 +fetch_stall_cycles: 0 +mem_stall_cycles: 0 +stall_warp: 0 +wspawn: 0 +stalled: 0 +********************************** Decode ********************************* +valid: 0 +PC: 0 +wid: 0 +rd: -1 rs1: -1 rs2: -1 +is_lw: 0 +is_sw: 0 +fetch_stall_cycles: 0 +mem_stall_cycles: 0 +stall_warp: 0 +wspawn: 0 +stalled: 0 +********************************** Fetch ********************************* +valid: 1 +PC: 80000b60 +wid: 0 +rd: -1 rs1: 14 rs2: 15 +is_lw: 0 +is_sw: 1 +fetch_stall_cycles: 2 +mem_stall_cycles: 0 +stall_warp: 0 +wspawn: 0 +stalled: 0 + + + +------------------------------------------------------ +CYCLE: 228 +Stalled Warps: +0 0 0 0 0 0 0 0 + +********************************** Writeback ********************************* +valid: 0 +PC: 0 +wid: 0 +rd: -1 rs1: -1 rs2: -1 +is_lw: 0 +is_sw: 0 +fetch_stall_cycles: 0 +mem_stall_cycles: 0 +stall_warp: 0 +wspawn: 0 +stalled: 0 +********************************** LSU ********************************* +valid: 0 +PC: 0 +wid: 3 +rd: -1 rs1: -1 rs2: -1 +is_lw: 0 +is_sw: 0 +fetch_stall_cycles: 0 +mem_stall_cycles: 0 +stall_warp: 0 +wspawn: 0 +stalled: 0 +********************************** execute_unit ********************************* +valid: 1 +PC: 80000b5c +wid: 0 +rd: 15 rs1: 14 rs2: -1 +is_lw: 0 +is_sw: 0 +fetch_stall_cycles: 0 +mem_stall_cycles: 0 +stall_warp: 0 +wspawn: 0 +stalled: 0 +********************************** scheduler ********************************* +valid: 0 +PC: 0 +wid: 0 +rd: -1 rs1: -1 rs2: -1 +is_lw: 0 +is_sw: 0 +fetch_stall_cycles: 0 +mem_stall_cycles: 0 +stall_warp: 0 +wspawn: 0 +stalled: 0 +********************************** Decode ********************************* +valid: 0 +PC: 0 +wid: 0 +rd: -1 rs1: -1 rs2: -1 +is_lw: 0 +is_sw: 0 +fetch_stall_cycles: 0 +mem_stall_cycles: 0 +stall_warp: 0 +wspawn: 0 +stalled: 0 +********************************** Fetch ********************************* +valid: 1 +PC: 80000b60 +wid: 0 +rd: -1 rs1: 14 rs2: 15 +is_lw: 0 +is_sw: 1 +fetch_stall_cycles: 1 +mem_stall_cycles: 0 +stall_warp: 0 +wspawn: 0 +stalled: 0 + + + +------------------------------------------------------ +CYCLE: 229 +Stalled Warps: +0 0 0 0 0 0 0 0 + +********************************** Writeback ********************************* +valid: 1 +PC: 80000b5c +wid: 0 +rd: 15 rs1: 14 rs2: -1 +is_lw: 0 +is_sw: 0 +fetch_stall_cycles: 0 +mem_stall_cycles: 0 +stall_warp: 0 +wspawn: 0 +stalled: 0 +********************************** LSU ********************************* +valid: 0 +PC: 0 +wid: 3 +rd: -1 rs1: -1 rs2: -1 +is_lw: 0 +is_sw: 0 +fetch_stall_cycles: 0 +mem_stall_cycles: 0 +stall_warp: 0 +wspawn: 0 +stalled: 0 +********************************** execute_unit ********************************* +valid: 0 +PC: 0 +wid: 0 +rd: -1 rs1: -1 rs2: -1 +is_lw: 0 +is_sw: 0 +fetch_stall_cycles: 0 +mem_stall_cycles: 0 +stall_warp: 0 +wspawn: 0 +stalled: 0 +********************************** scheduler ********************************* +valid: 0 +PC: 0 +wid: 0 +rd: -1 rs1: -1 rs2: -1 +is_lw: 0 +is_sw: 0 +fetch_stall_cycles: 0 +mem_stall_cycles: 0 +stall_warp: 0 +wspawn: 0 +stalled: 0 +********************************** Decode ********************************* +valid: 0 +PC: 0 +wid: 0 +rd: -1 rs1: -1 rs2: -1 +is_lw: 0 +is_sw: 0 +fetch_stall_cycles: 0 +mem_stall_cycles: 0 +stall_warp: 0 +wspawn: 0 +stalled: 0 +********************************** Fetch ********************************* +valid: 1 +PC: 80000b60 +wid: 0 +rd: -1 rs1: 14 rs2: 15 +is_lw: 0 +is_sw: 1 +fetch_stall_cycles: 0 +mem_stall_cycles: 0 +stall_warp: 0 +wspawn: 0 +stalled: 0 + + + +------------------------------------------------------ +CYCLE: 230 +Stalled Warps: +0 0 0 0 0 0 0 0 + +********************************** Writeback ********************************* +valid: 0 +PC: 0 +wid: 0 +rd: -1 rs1: -1 rs2: -1 +is_lw: 0 +is_sw: 0 +fetch_stall_cycles: 0 +mem_stall_cycles: 0 +stall_warp: 0 +wspawn: 0 +stalled: 0 +********************************** LSU ********************************* +valid: 0 +PC: 0 +wid: 3 +rd: -1 rs1: -1 rs2: -1 +is_lw: 0 +is_sw: 0 +fetch_stall_cycles: 0 +mem_stall_cycles: 0 +stall_warp: 0 +wspawn: 0 +stalled: 0 +********************************** execute_unit ********************************* +valid: 0 +PC: 0 +wid: 0 +rd: -1 rs1: -1 rs2: -1 +is_lw: 0 +is_sw: 0 +fetch_stall_cycles: 0 +mem_stall_cycles: 0 +stall_warp: 0 +wspawn: 0 +stalled: 0 +********************************** scheduler ********************************* +valid: 0 +PC: 0 +wid: 0 +rd: -1 rs1: -1 rs2: -1 +is_lw: 0 +is_sw: 0 +fetch_stall_cycles: 0 +mem_stall_cycles: 0 +stall_warp: 0 +wspawn: 0 +stalled: 0 +********************************** Decode ********************************* +valid: 1 +PC: 80000b60 +wid: 0 +rd: -1 rs1: 14 rs2: 15 +is_lw: 0 +is_sw: 1 +fetch_stall_cycles: 0 +mem_stall_cycles: 0 +stall_warp: 0 +wspawn: 0 +stalled: 0 +DEBUG ../core.cpp:386: Core step stepping warp 0[1] +DEBUG ../core.cpp:683: in step pc=0x80000b64 +help: in PC: 80000b64 +CUrrent CODE: fa5ff06f +DEBUG ../core.cpp:703: Fetched at 0x80000b64 +DEBUG ../core.cpp:704: 0x80000b64: jal; +DEBUG ../instruction.cpp:350: Begin instruction execute. +DEBUG ../instruction.cpp:2117: End instruction execute. +Next PC: 80000b08 +DEBUG ../core.cpp:717: Register state: + %r 0: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r 1: 8000003c 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r 2: 6ffff000 6fffec04 6fffe808 6fffe40c 00000000 00000000 00000000 00000000 (0) + %r 3: 80001808 80001808 80001808 80001808 00000000 00000000 00000000 00000000 (0) + %r 4: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r 5: 80000a6c 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r 6: 0000000f 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r 7: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r 8: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r 9: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r10: 00000000 00000001 00000001 00000001 00000000 00000000 00000000 00000000 (0) + %r11: 80000924 00000400 00000800 00000c00 00000000 00000000 00000000 00000000 (0) + %r12: 00000000 00000004 00000008 0000000c 00000000 00000000 00000000 00000000 (0) + %r13: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r14: 80001008 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r15: 80001154 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r16: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r17: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r18: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r19: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r20: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r21: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r22: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r23: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r24: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r25: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r26: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r27: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r28: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r29: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r30: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r31: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) +DEBUG ../core.cpp:726: Thread mask: + 1 0 0 0 0 0 0 0 + + +DEBUG ../core.cpp:388: Now 1 active threads in 0 +********************************** Fetch ********************************* +valid: 1 +PC: 80000b64 +wid: 0 +rd: 0 rs1: -1 rs2: -1 +is_lw: 0 +is_sw: 0 +fetch_stall_cycles: 0 +mem_stall_cycles: 0 +stall_warp: 1 +wspawn: 0 +stalled: 0 + + + +------------------------------------------------------ +CYCLE: 231 +Stalled Warps: +1 0 0 0 0 0 0 0 + +********************************** Writeback ********************************* +valid: 0 +PC: 0 +wid: 1 +rd: -1 rs1: -1 rs2: -1 +is_lw: 0 +is_sw: 0 +fetch_stall_cycles: 0 +mem_stall_cycles: 0 +stall_warp: 0 +wspawn: 0 +stalled: 0 +********************************** LSU ********************************* +valid: 0 +PC: 0 +wid: 3 +rd: -1 rs1: -1 rs2: -1 +is_lw: 0 +is_sw: 0 +fetch_stall_cycles: 0 +mem_stall_cycles: 0 +stall_warp: 0 +wspawn: 0 +stalled: 0 +********************************** execute_unit ********************************* +valid: 0 +PC: 0 +wid: 0 +rd: -1 rs1: -1 rs2: -1 +is_lw: 0 +is_sw: 0 +fetch_stall_cycles: 0 +mem_stall_cycles: 0 +stall_warp: 0 +wspawn: 0 +stalled: 0 +********************************** scheduler ********************************* +valid: 1 +PC: 80000b60 +wid: 0 +rd: -1 rs1: 14 rs2: 15 +is_lw: 0 +is_sw: 1 +fetch_stall_cycles: 0 +mem_stall_cycles: 0 +stall_warp: 0 +wspawn: 0 +stalled: 0 +********************************** Decode ********************************* +valid: 1 +PC: 80000b64 +wid: 0 +rd: 0 rs1: -1 rs2: -1 +is_lw: 0 +is_sw: 0 +fetch_stall_cycles: 0 +mem_stall_cycles: 0 +stall_warp: 1 +wspawn: 0 +stalled: 0 +********************************** Fetch ********************************* +valid: 0 +PC: 0 +wid: 1 +rd: -1 rs1: -1 rs2: -1 +is_lw: 0 +is_sw: 0 +fetch_stall_cycles: 0 +mem_stall_cycles: 0 +stall_warp: 0 +wspawn: 0 +stalled: 0 + + + +------------------------------------------------------ +CYCLE: 232 +Stalled Warps: +1 0 0 0 0 0 0 0 + +********************************** Writeback ********************************* +valid: 0 +PC: 0 +wid: 2 +rd: -1 rs1: -1 rs2: -1 +is_lw: 0 +is_sw: 0 +fetch_stall_cycles: 0 +mem_stall_cycles: 0 +stall_warp: 0 +wspawn: 0 +stalled: 0 +********************************** LSU ********************************* +valid: 1 +PC: 80000b60 +wid: 0 +rd: -1 rs1: 14 rs2: 15 +is_lw: 0 +is_sw: 1 +fetch_stall_cycles: 0 +mem_stall_cycles: 0 +stall_warp: 0 +wspawn: 0 +stalled: 0 +********************************** execute_unit ********************************* +valid: 0 +PC: 0 +wid: 2 +rd: -1 rs1: -1 rs2: -1 +is_lw: 0 +is_sw: 0 +fetch_stall_cycles: 0 +mem_stall_cycles: 0 +stall_warp: 0 +wspawn: 0 +stalled: 0 +********************************** scheduler ********************************* +valid: 1 +PC: 80000b64 +wid: 0 +rd: 0 rs1: -1 rs2: -1 +is_lw: 0 +is_sw: 0 +fetch_stall_cycles: 0 +mem_stall_cycles: 0 +stall_warp: 1 +wspawn: 0 +stalled: 0 +********************************** Decode ********************************* +valid: 0 +PC: 0 +wid: 1 +rd: -1 rs1: -1 rs2: -1 +is_lw: 0 +is_sw: 0 +fetch_stall_cycles: 0 +mem_stall_cycles: 0 +stall_warp: 0 +wspawn: 0 +stalled: 0 +********************************** Fetch ********************************* +valid: 0 +PC: 0 +wid: 2 +rd: -1 rs1: -1 rs2: -1 +is_lw: 0 +is_sw: 0 +fetch_stall_cycles: 0 +mem_stall_cycles: 0 +stall_warp: 0 +wspawn: 0 +stalled: 0 + + + +------------------------------------------------------ +CYCLE: 233 +Stalled Warps: +1 0 0 0 0 0 0 0 + +********************************** Writeback ********************************* +valid: 0 +PC: 0 +wid: 3 +rd: -1 rs1: -1 rs2: -1 +is_lw: 0 +is_sw: 0 +fetch_stall_cycles: 0 +mem_stall_cycles: 0 +stall_warp: 0 +wspawn: 0 +stalled: 0 +********************************** LSU ********************************* +valid: 0 +PC: 0 +wid: 3 +rd: -1 rs1: -1 rs2: -1 +is_lw: 0 +is_sw: 0 +fetch_stall_cycles: 0 +mem_stall_cycles: 0 +stall_warp: 0 +wspawn: 0 +stalled: 0 +********************************** execute_unit ********************************* +valid: 1 +PC: 80000b64 +wid: 0 +rd: 0 rs1: -1 rs2: -1 +is_lw: 0 +is_sw: 0 +fetch_stall_cycles: 0 +mem_stall_cycles: 0 +stall_warp: 1 +wspawn: 0 +stalled: 0 +********************************** scheduler ********************************* +valid: 0 +PC: 0 +wid: 1 +rd: -1 rs1: -1 rs2: -1 +is_lw: 0 +is_sw: 0 +fetch_stall_cycles: 0 +mem_stall_cycles: 0 +stall_warp: 0 +wspawn: 0 +stalled: 0 +********************************** Decode ********************************* +valid: 0 +PC: 0 +wid: 2 +rd: -1 rs1: -1 rs2: -1 +is_lw: 0 +is_sw: 0 +fetch_stall_cycles: 0 +mem_stall_cycles: 0 +stall_warp: 0 +wspawn: 0 +stalled: 0 +********************************** Fetch ********************************* +valid: 0 +PC: 0 +wid: 3 +rd: -1 rs1: -1 rs2: -1 +is_lw: 0 +is_sw: 0 +fetch_stall_cycles: 0 +mem_stall_cycles: 0 +stall_warp: 0 +wspawn: 0 +stalled: 0 + + + +------------------------------------------------------ +CYCLE: 234 +Stalled Warps: +1 0 0 0 0 0 0 0 + +********************************** Writeback ********************************* +valid: 1 +PC: 80000b64 +wid: 0 +rd: 0 rs1: -1 rs2: -1 +is_lw: 0 +is_sw: 0 +fetch_stall_cycles: 0 +mem_stall_cycles: 0 +stall_warp: 1 +wspawn: 0 +stalled: 0 +********************************** LSU ********************************* +valid: 0 +PC: 0 +wid: 3 +rd: -1 rs1: -1 rs2: -1 +is_lw: 0 +is_sw: 0 +fetch_stall_cycles: 0 +mem_stall_cycles: 0 +stall_warp: 0 +wspawn: 0 +stalled: 0 +********************************** execute_unit ********************************* +valid: 0 +PC: 0 +wid: 1 +rd: -1 rs1: -1 rs2: -1 +is_lw: 0 +is_sw: 0 +fetch_stall_cycles: 0 +mem_stall_cycles: 0 +stall_warp: 0 +wspawn: 0 +stalled: 0 +********************************** scheduler ********************************* +valid: 0 +PC: 0 +wid: 2 +rd: -1 rs1: -1 rs2: -1 +is_lw: 0 +is_sw: 0 +fetch_stall_cycles: 0 +mem_stall_cycles: 0 +stall_warp: 0 +wspawn: 0 +stalled: 0 +********************************** Decode ********************************* +valid: 0 +PC: 0 +wid: 3 +rd: -1 rs1: -1 rs2: -1 +is_lw: 0 +is_sw: 0 +fetch_stall_cycles: 0 +mem_stall_cycles: 0 +stall_warp: 0 +wspawn: 0 +stalled: 0 +********************************** Fetch ********************************* +valid: 0 +PC: 0 +wid: 4 +rd: -1 rs1: -1 rs2: -1 +is_lw: 0 +is_sw: 0 +fetch_stall_cycles: 0 +mem_stall_cycles: 0 +stall_warp: 0 +wspawn: 0 +stalled: 0 + + + +------------------------------------------------------ +CYCLE: 235 +Stalled Warps: +1 0 0 0 0 0 0 0 + +********************************** Writeback ********************************* +valid: 0 +PC: 0 +wid: 5 +rd: -1 rs1: -1 rs2: -1 +is_lw: 0 +is_sw: 0 +fetch_stall_cycles: 0 +mem_stall_cycles: 0 +stall_warp: 0 +wspawn: 0 +stalled: 0 +********************************** LSU ********************************* +valid: 0 +PC: 0 +wid: 3 +rd: -1 rs1: -1 rs2: -1 +is_lw: 0 +is_sw: 0 +fetch_stall_cycles: 0 +mem_stall_cycles: 0 +stall_warp: 0 +wspawn: 0 +stalled: 0 +********************************** execute_unit ********************************* +valid: 0 +PC: 0 +wid: 2 +rd: -1 rs1: -1 rs2: -1 +is_lw: 0 +is_sw: 0 +fetch_stall_cycles: 0 +mem_stall_cycles: 0 +stall_warp: 0 +wspawn: 0 +stalled: 0 +********************************** scheduler ********************************* +valid: 0 +PC: 0 +wid: 3 +rd: -1 rs1: -1 rs2: -1 +is_lw: 0 +is_sw: 0 +fetch_stall_cycles: 0 +mem_stall_cycles: 0 +stall_warp: 0 +wspawn: 0 +stalled: 0 +********************************** Decode ********************************* +valid: 0 +PC: 0 +wid: 4 +rd: -1 rs1: -1 rs2: -1 +is_lw: 0 +is_sw: 0 +fetch_stall_cycles: 0 +mem_stall_cycles: 0 +stall_warp: 0 +wspawn: 0 +stalled: 0 +********************************** Fetch ********************************* +valid: 0 +PC: 0 +wid: 5 +rd: -1 rs1: -1 rs2: -1 +is_lw: 0 +is_sw: 0 +fetch_stall_cycles: 0 +mem_stall_cycles: 0 +stall_warp: 0 +wspawn: 0 +stalled: 0 +Warp ID 0 is running + + + +------------------------------------------------------ +CYCLE: 236 +Stalled Warps: +0 0 0 0 0 0 0 0 + +********************************** Writeback ********************************* +valid: 0 +PC: 0 +wid: 0 +rd: -1 rs1: -1 rs2: -1 +is_lw: 0 +is_sw: 0 +fetch_stall_cycles: 0 +mem_stall_cycles: 0 +stall_warp: 0 +wspawn: 0 +stalled: 0 +********************************** LSU ********************************* +valid: 0 +PC: 0 +wid: 3 +rd: -1 rs1: -1 rs2: -1 +is_lw: 0 +is_sw: 0 +fetch_stall_cycles: 0 +mem_stall_cycles: 0 +stall_warp: 0 +wspawn: 0 +stalled: 0 +********************************** execute_unit ********************************* +valid: 0 +PC: 0 +wid: 3 +rd: -1 rs1: -1 rs2: -1 +is_lw: 0 +is_sw: 0 +fetch_stall_cycles: 0 +mem_stall_cycles: 0 +stall_warp: 0 +wspawn: 0 +stalled: 0 +********************************** scheduler ********************************* +valid: 0 +PC: 0 +wid: 4 +rd: -1 rs1: -1 rs2: -1 +is_lw: 0 +is_sw: 0 +fetch_stall_cycles: 0 +mem_stall_cycles: 0 +stall_warp: 0 +wspawn: 0 +stalled: 0 +********************************** Decode ********************************* +valid: 0 +PC: 0 +wid: 5 +rd: -1 rs1: -1 rs2: -1 +is_lw: 0 +is_sw: 0 +fetch_stall_cycles: 0 +mem_stall_cycles: 0 +stall_warp: 0 +wspawn: 0 +stalled: 0 +DEBUG ../core.cpp:386: Core step stepping warp 0[1] +DEBUG ../core.cpp:683: in step pc=0x80000b08 +help: in PC: 80000b08 +CUrrent CODE: 47a703 +DEBUG ../core.cpp:703: Fetched at 0x80000b08 +DEBUG ../core.cpp:704: 0x80000b08: load; +DEBUG ../instruction.cpp:350: Begin instruction execute. +DEBUG ../instruction.cpp:2117: End instruction execute. +DEBUG ../core.cpp:717: Register state: + %r 0: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r 1: 8000003c 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r 2: 6ffff000 6fffec04 6fffe808 6fffe40c 00000000 00000000 00000000 00000000 (0) + %r 3: 80001808 80001808 80001808 80001808 00000000 00000000 00000000 00000000 (0) + %r 4: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r 5: 80000a6c 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r 6: 0000000f 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r 7: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r 8: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r 9: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r10: 00000000 00000001 00000001 00000001 00000000 00000000 00000000 00000000 (0) + %r11: 80000924 00000400 00000800 00000c00 00000000 00000000 00000000 00000000 (0) + %r12: 00000000 00000004 00000008 0000000c 00000000 00000000 00000000 00000000 (0) + %r13: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r14: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r15: 80001154 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r16: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r17: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r18: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r19: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r20: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r21: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r22: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r23: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r24: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r25: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r26: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r27: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r28: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r29: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r30: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r31: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) +DEBUG ../core.cpp:726: Thread mask: + 1 0 0 0 0 0 0 0 + + +DEBUG ../core.cpp:388: Now 1 active threads in 0 +********************************** Fetch ********************************* +valid: 1 +PC: 80000b08 +wid: 0 +rd: 14 rs1: 15 rs2: -1 +is_lw: 1 +is_sw: 0 +fetch_stall_cycles: 0 +mem_stall_cycles: 0 +stall_warp: 0 +wspawn: 0 +stalled: 0 + + + +------------------------------------------------------ +CYCLE: 237 +Stalled Warps: +0 0 0 0 0 0 0 0 + +********************************** Writeback ********************************* +valid: 0 +PC: 0 +wid: 0 +rd: -1 rs1: -1 rs2: -1 +is_lw: 0 +is_sw: 0 +fetch_stall_cycles: 0 +mem_stall_cycles: 0 +stall_warp: 0 +wspawn: 0 +stalled: 0 +********************************** LSU ********************************* +valid: 0 +PC: 0 +wid: 3 +rd: -1 rs1: -1 rs2: -1 +is_lw: 0 +is_sw: 0 +fetch_stall_cycles: 0 +mem_stall_cycles: 0 +stall_warp: 0 +wspawn: 0 +stalled: 0 +********************************** execute_unit ********************************* +valid: 0 +PC: 0 +wid: 4 +rd: -1 rs1: -1 rs2: -1 +is_lw: 0 +is_sw: 0 +fetch_stall_cycles: 0 +mem_stall_cycles: 0 +stall_warp: 0 +wspawn: 0 +stalled: 0 +********************************** scheduler ********************************* +valid: 0 +PC: 0 +wid: 5 +rd: -1 rs1: -1 rs2: -1 +is_lw: 0 +is_sw: 0 +fetch_stall_cycles: 0 +mem_stall_cycles: 0 +stall_warp: 0 +wspawn: 0 +stalled: 0 +********************************** Decode ********************************* +valid: 1 +PC: 80000b08 +wid: 0 +rd: 14 rs1: 15 rs2: -1 +is_lw: 1 +is_sw: 0 +fetch_stall_cycles: 0 +mem_stall_cycles: 0 +stall_warp: 0 +wspawn: 0 +stalled: 0 +DEBUG ../core.cpp:386: Core step stepping warp 0[1] +DEBUG ../core.cpp:683: in step pc=0x80000b0c +help: in PC: 80000b0c +CUrrent CODE: 1f00813 +DEBUG ../core.cpp:703: Fetched at 0x80000b0c +DEBUG ../core.cpp:704: 0x80000b0c: i_type; +DEBUG ../instruction.cpp:350: Begin instruction execute. +DEBUG ../instruction.cpp:2117: End instruction execute. +DEBUG ../core.cpp:717: Register state: + %r 0: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r 1: 8000003c 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r 2: 6ffff000 6fffec04 6fffe808 6fffe40c 00000000 00000000 00000000 00000000 (0) + %r 3: 80001808 80001808 80001808 80001808 00000000 00000000 00000000 00000000 (0) + %r 4: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r 5: 80000a6c 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r 6: 0000000f 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r 7: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r 8: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r 9: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r10: 00000000 00000001 00000001 00000001 00000000 00000000 00000000 00000000 (0) + %r11: 80000924 00000400 00000800 00000c00 00000000 00000000 00000000 00000000 (0) + %r12: 00000000 00000004 00000008 0000000c 00000000 00000000 00000000 00000000 (0) + %r13: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r14: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r15: 80001154 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r16: 0000001f 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r17: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r18: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r19: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r20: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r21: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r22: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r23: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r24: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r25: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r26: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r27: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r28: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r29: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r30: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r31: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) +DEBUG ../core.cpp:726: Thread mask: + 1 0 0 0 0 0 0 0 + + +DEBUG ../core.cpp:388: Now 1 active threads in 0 +********************************** Fetch ********************************* +valid: 1 +PC: 80000b0c +wid: 0 +rd: 16 rs1: 0 rs2: -1 +is_lw: 0 +is_sw: 0 +fetch_stall_cycles: 0 +mem_stall_cycles: 0 +stall_warp: 0 +wspawn: 0 +stalled: 0 + + + +------------------------------------------------------ +CYCLE: 238 +Stalled Warps: +0 0 0 0 0 0 0 0 + +********************************** Writeback ********************************* +valid: 0 +PC: 0 +wid: 0 +rd: -1 rs1: -1 rs2: -1 +is_lw: 0 +is_sw: 0 +fetch_stall_cycles: 0 +mem_stall_cycles: 0 +stall_warp: 0 +wspawn: 0 +stalled: 0 +********************************** LSU ********************************* +valid: 0 +PC: 0 +wid: 3 +rd: -1 rs1: -1 rs2: -1 +is_lw: 0 +is_sw: 0 +fetch_stall_cycles: 0 +mem_stall_cycles: 0 +stall_warp: 0 +wspawn: 0 +stalled: 0 +********************************** execute_unit ********************************* +valid: 0 +PC: 0 +wid: 5 +rd: -1 rs1: -1 rs2: -1 +is_lw: 0 +is_sw: 0 +fetch_stall_cycles: 0 +mem_stall_cycles: 0 +stall_warp: 0 +wspawn: 0 +stalled: 0 +********************************** scheduler ********************************* +valid: 1 +PC: 80000b08 +wid: 0 +rd: 14 rs1: 15 rs2: -1 +is_lw: 1 +is_sw: 0 +fetch_stall_cycles: 0 +mem_stall_cycles: 0 +stall_warp: 0 +wspawn: 0 +stalled: 0 +********************************** Decode ********************************* +valid: 1 +PC: 80000b0c +wid: 0 +rd: 16 rs1: 0 rs2: -1 +is_lw: 0 +is_sw: 0 +fetch_stall_cycles: 0 +mem_stall_cycles: 0 +stall_warp: 0 +wspawn: 0 +stalled: 0 +DEBUG ../core.cpp:386: Core step stepping warp 0[1] +DEBUG ../core.cpp:683: in step pc=0x80000b10 +help: in PC: 80000b10 +CUrrent CODE: 6e84e63 +DEBUG ../core.cpp:703: Fetched at 0x80000b10 +DEBUG ../core.cpp:704: 0x80000b10: branch; +DEBUG ../instruction.cpp:350: Begin instruction execute. +DEBUG ../instruction.cpp:2117: End instruction execute. +DEBUG ../core.cpp:717: Register state: + %r 0: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r 1: 8000003c 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r 2: 6ffff000 6fffec04 6fffe808 6fffe40c 00000000 00000000 00000000 00000000 (0) + %r 3: 80001808 80001808 80001808 80001808 00000000 00000000 00000000 00000000 (0) + %r 4: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r 5: 80000a6c 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r 6: 0000000f 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r 7: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r 8: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r 9: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r10: 00000000 00000001 00000001 00000001 00000000 00000000 00000000 00000000 (0) + %r11: 80000924 00000400 00000800 00000c00 00000000 00000000 00000000 00000000 (0) + %r12: 00000000 00000004 00000008 0000000c 00000000 00000000 00000000 00000000 (0) + %r13: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r14: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r15: 80001154 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r16: 0000001f 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r17: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r18: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r19: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r20: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r21: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r22: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r23: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r24: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r25: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r26: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r27: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r28: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r29: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r30: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r31: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) +DEBUG ../core.cpp:726: Thread mask: + 1 0 0 0 0 0 0 0 + + +DEBUG ../core.cpp:388: Now 1 active threads in 0 +********************************** Fetch ********************************* +valid: 1 +PC: 80000b10 +wid: 0 +rd: -1 rs1: 16 rs2: 14 +is_lw: 0 +is_sw: 0 +fetch_stall_cycles: 3 +mem_stall_cycles: 0 +stall_warp: 1 +wspawn: 0 +stalled: 0 + + + +------------------------------------------------------ +CYCLE: 239 +Stalled Warps: +1 0 0 0 0 0 0 0 + +********************************** Writeback ********************************* +valid: 0 +PC: 0 +wid: 1 +rd: -1 rs1: -1 rs2: -1 +is_lw: 0 +is_sw: 0 +fetch_stall_cycles: 0 +mem_stall_cycles: 0 +stall_warp: 0 +wspawn: 0 +stalled: 0 +********************************** LSU ********************************* +valid: 1 +PC: 80000b08 +wid: 0 +rd: 14 rs1: 15 rs2: -1 +is_lw: 1 +is_sw: 0 +fetch_stall_cycles: 0 +mem_stall_cycles: 0 +stall_warp: 0 +wspawn: 0 +stalled: 0 +********************************** execute_unit ********************************* +valid: 0 +PC: 0 +wid: 1 +rd: -1 rs1: -1 rs2: -1 +is_lw: 0 +is_sw: 0 +fetch_stall_cycles: 0 +mem_stall_cycles: 0 +stall_warp: 0 +wspawn: 0 +stalled: 0 +********************************** scheduler ********************************* +valid: 1 +PC: 80000b0c +wid: 0 +rd: 16 rs1: 0 rs2: -1 +is_lw: 0 +is_sw: 0 +fetch_stall_cycles: 0 +mem_stall_cycles: 0 +stall_warp: 0 +wspawn: 0 +stalled: 0 +********************************** Decode ********************************* +valid: 0 +PC: 0 +wid: 1 +rd: -1 rs1: -1 rs2: -1 +is_lw: 0 +is_sw: 0 +fetch_stall_cycles: 0 +mem_stall_cycles: 0 +stall_warp: 0 +wspawn: 0 +stalled: 0 +********************************** Fetch ********************************* +valid: 1 +PC: 80000b10 +wid: 0 +rd: -1 rs1: 16 rs2: 14 +is_lw: 0 +is_sw: 0 +fetch_stall_cycles: 2 +mem_stall_cycles: 0 +stall_warp: 1 +wspawn: 0 +stalled: 0 + + + +------------------------------------------------------ +CYCLE: 240 +Stalled Warps: +1 0 0 0 0 0 0 0 + +********************************** Writeback ********************************* +valid: 1 +PC: 80000b08 +wid: 0 +rd: 14 rs1: 15 rs2: -1 +is_lw: 1 +is_sw: 0 +fetch_stall_cycles: 0 +mem_stall_cycles: 0 +stall_warp: 0 +wspawn: 0 +stalled: 0 +********************************** LSU ********************************* +valid: 0 +PC: 0 +wid: 1 +rd: -1 rs1: -1 rs2: -1 +is_lw: 0 +is_sw: 0 +fetch_stall_cycles: 0 +mem_stall_cycles: 0 +stall_warp: 0 +wspawn: 0 +stalled: 0 +********************************** execute_unit ********************************* +valid: 1 +PC: 80000b0c +wid: 0 +rd: 16 rs1: 0 rs2: -1 +is_lw: 0 +is_sw: 0 +fetch_stall_cycles: 0 +mem_stall_cycles: 0 +stall_warp: 0 +wspawn: 0 +stalled: 0 +********************************** scheduler ********************************* +valid: 0 +PC: 0 +wid: 1 +rd: -1 rs1: -1 rs2: -1 +is_lw: 0 +is_sw: 0 +fetch_stall_cycles: 0 +mem_stall_cycles: 0 +stall_warp: 0 +wspawn: 0 +stalled: 0 +********************************** Decode ********************************* +valid: 0 +PC: 0 +wid: 1 +rd: -1 rs1: -1 rs2: -1 +is_lw: 0 +is_sw: 0 +fetch_stall_cycles: 0 +mem_stall_cycles: 0 +stall_warp: 0 +wspawn: 0 +stalled: 0 +********************************** Fetch ********************************* +valid: 1 +PC: 80000b10 +wid: 0 +rd: -1 rs1: 16 rs2: 14 +is_lw: 0 +is_sw: 0 +fetch_stall_cycles: 1 +mem_stall_cycles: 0 +stall_warp: 1 +wspawn: 0 +stalled: 0 + + + +------------------------------------------------------ +CYCLE: 241 +Stalled Warps: +1 0 0 0 0 0 0 0 + +********************************** Writeback ********************************* +valid: 1 +PC: 80000b0c +wid: 0 +rd: 16 rs1: 0 rs2: -1 +is_lw: 0 +is_sw: 0 +fetch_stall_cycles: 0 +mem_stall_cycles: 0 +stall_warp: 0 +wspawn: 0 +stalled: 0 +********************************** LSU ********************************* +valid: 0 +PC: 0 +wid: 1 +rd: -1 rs1: -1 rs2: -1 +is_lw: 0 +is_sw: 0 +fetch_stall_cycles: 0 +mem_stall_cycles: 0 +stall_warp: 0 +wspawn: 0 +stalled: 0 +********************************** execute_unit ********************************* +valid: 0 +PC: 0 +wid: 1 +rd: -1 rs1: -1 rs2: -1 +is_lw: 0 +is_sw: 0 +fetch_stall_cycles: 0 +mem_stall_cycles: 0 +stall_warp: 0 +wspawn: 0 +stalled: 0 +********************************** scheduler ********************************* +valid: 0 +PC: 0 +wid: 1 +rd: -1 rs1: -1 rs2: -1 +is_lw: 0 +is_sw: 0 +fetch_stall_cycles: 0 +mem_stall_cycles: 0 +stall_warp: 0 +wspawn: 0 +stalled: 0 +********************************** Decode ********************************* +valid: 0 +PC: 0 +wid: 1 +rd: -1 rs1: -1 rs2: -1 +is_lw: 0 +is_sw: 0 +fetch_stall_cycles: 0 +mem_stall_cycles: 0 +stall_warp: 0 +wspawn: 0 +stalled: 0 +********************************** Fetch ********************************* +valid: 1 +PC: 80000b10 +wid: 0 +rd: -1 rs1: 16 rs2: 14 +is_lw: 0 +is_sw: 0 +fetch_stall_cycles: 0 +mem_stall_cycles: 0 +stall_warp: 1 +wspawn: 0 +stalled: 0 + + + +------------------------------------------------------ +CYCLE: 242 +Stalled Warps: +1 0 0 0 0 0 0 0 + +********************************** Writeback ********************************* +valid: 0 +PC: 0 +wid: 1 +rd: -1 rs1: -1 rs2: -1 +is_lw: 0 +is_sw: 0 +fetch_stall_cycles: 0 +mem_stall_cycles: 0 +stall_warp: 0 +wspawn: 0 +stalled: 0 +********************************** LSU ********************************* +valid: 0 +PC: 0 +wid: 1 +rd: -1 rs1: -1 rs2: -1 +is_lw: 0 +is_sw: 0 +fetch_stall_cycles: 0 +mem_stall_cycles: 0 +stall_warp: 0 +wspawn: 0 +stalled: 0 +********************************** execute_unit ********************************* +valid: 0 +PC: 0 +wid: 1 +rd: -1 rs1: -1 rs2: -1 +is_lw: 0 +is_sw: 0 +fetch_stall_cycles: 0 +mem_stall_cycles: 0 +stall_warp: 0 +wspawn: 0 +stalled: 0 +********************************** scheduler ********************************* +valid: 0 +PC: 0 +wid: 1 +rd: -1 rs1: -1 rs2: -1 +is_lw: 0 +is_sw: 0 +fetch_stall_cycles: 0 +mem_stall_cycles: 0 +stall_warp: 0 +wspawn: 0 +stalled: 0 +********************************** Decode ********************************* +valid: 1 +PC: 80000b10 +wid: 0 +rd: -1 rs1: 16 rs2: 14 +is_lw: 0 +is_sw: 0 +fetch_stall_cycles: 0 +mem_stall_cycles: 0 +stall_warp: 1 +wspawn: 0 +stalled: 0 +********************************** Fetch ********************************* +valid: 0 +PC: 0 +wid: 1 +rd: -1 rs1: -1 rs2: -1 +is_lw: 0 +is_sw: 0 +fetch_stall_cycles: 0 +mem_stall_cycles: 0 +stall_warp: 0 +wspawn: 0 +stalled: 0 + + + +------------------------------------------------------ +CYCLE: 243 +Stalled Warps: +1 0 0 0 0 0 0 0 + +********************************** Writeback ********************************* +valid: 0 +PC: 0 +wid: 2 +rd: -1 rs1: -1 rs2: -1 +is_lw: 0 +is_sw: 0 +fetch_stall_cycles: 0 +mem_stall_cycles: 0 +stall_warp: 0 +wspawn: 0 +stalled: 0 +********************************** LSU ********************************* +valid: 0 +PC: 0 +wid: 1 +rd: -1 rs1: -1 rs2: -1 +is_lw: 0 +is_sw: 0 +fetch_stall_cycles: 0 +mem_stall_cycles: 0 +stall_warp: 0 +wspawn: 0 +stalled: 0 +********************************** execute_unit ********************************* +valid: 0 +PC: 0 +wid: 1 +rd: -1 rs1: -1 rs2: -1 +is_lw: 0 +is_sw: 0 +fetch_stall_cycles: 0 +mem_stall_cycles: 0 +stall_warp: 0 +wspawn: 0 +stalled: 0 +********************************** scheduler ********************************* +valid: 1 +PC: 80000b10 +wid: 0 +rd: -1 rs1: 16 rs2: 14 +is_lw: 0 +is_sw: 0 +fetch_stall_cycles: 0 +mem_stall_cycles: 0 +stall_warp: 1 +wspawn: 0 +stalled: 0 +********************************** Decode ********************************* +valid: 0 +PC: 0 +wid: 1 +rd: -1 rs1: -1 rs2: -1 +is_lw: 0 +is_sw: 0 +fetch_stall_cycles: 0 +mem_stall_cycles: 0 +stall_warp: 0 +wspawn: 0 +stalled: 0 +********************************** Fetch ********************************* +valid: 0 +PC: 0 +wid: 2 +rd: -1 rs1: -1 rs2: -1 +is_lw: 0 +is_sw: 0 +fetch_stall_cycles: 0 +mem_stall_cycles: 0 +stall_warp: 0 +wspawn: 0 +stalled: 0 + + + +------------------------------------------------------ +CYCLE: 244 +Stalled Warps: +1 0 0 0 0 0 0 0 + +********************************** Writeback ********************************* +valid: 0 +PC: 0 +wid: 3 +rd: -1 rs1: -1 rs2: -1 +is_lw: 0 +is_sw: 0 +fetch_stall_cycles: 0 +mem_stall_cycles: 0 +stall_warp: 0 +wspawn: 0 +stalled: 0 +********************************** LSU ********************************* +valid: 0 +PC: 0 +wid: 1 +rd: -1 rs1: -1 rs2: -1 +is_lw: 0 +is_sw: 0 +fetch_stall_cycles: 0 +mem_stall_cycles: 0 +stall_warp: 0 +wspawn: 0 +stalled: 0 +********************************** execute_unit ********************************* +valid: 1 +PC: 80000b10 +wid: 0 +rd: -1 rs1: 16 rs2: 14 +is_lw: 0 +is_sw: 0 +fetch_stall_cycles: 0 +mem_stall_cycles: 0 +stall_warp: 1 +wspawn: 0 +stalled: 0 +********************************** scheduler ********************************* +valid: 0 +PC: 0 +wid: 1 +rd: -1 rs1: -1 rs2: -1 +is_lw: 0 +is_sw: 0 +fetch_stall_cycles: 0 +mem_stall_cycles: 0 +stall_warp: 0 +wspawn: 0 +stalled: 0 +********************************** Decode ********************************* +valid: 0 +PC: 0 +wid: 2 +rd: -1 rs1: -1 rs2: -1 +is_lw: 0 +is_sw: 0 +fetch_stall_cycles: 0 +mem_stall_cycles: 0 +stall_warp: 0 +wspawn: 0 +stalled: 0 +********************************** Fetch ********************************* +valid: 0 +PC: 0 +wid: 3 +rd: -1 rs1: -1 rs2: -1 +is_lw: 0 +is_sw: 0 +fetch_stall_cycles: 0 +mem_stall_cycles: 0 +stall_warp: 0 +wspawn: 0 +stalled: 0 + + + +------------------------------------------------------ +CYCLE: 245 +Stalled Warps: +1 0 0 0 0 0 0 0 + +********************************** Writeback ********************************* +valid: 1 +PC: 80000b10 +wid: 0 +rd: -1 rs1: 16 rs2: 14 +is_lw: 0 +is_sw: 0 +fetch_stall_cycles: 0 +mem_stall_cycles: 0 +stall_warp: 1 +wspawn: 0 +stalled: 0 +********************************** LSU ********************************* +valid: 0 +PC: 0 +wid: 1 +rd: -1 rs1: -1 rs2: -1 +is_lw: 0 +is_sw: 0 +fetch_stall_cycles: 0 +mem_stall_cycles: 0 +stall_warp: 0 +wspawn: 0 +stalled: 0 +********************************** execute_unit ********************************* +valid: 0 +PC: 0 +wid: 1 +rd: -1 rs1: -1 rs2: -1 +is_lw: 0 +is_sw: 0 +fetch_stall_cycles: 0 +mem_stall_cycles: 0 +stall_warp: 0 +wspawn: 0 +stalled: 0 +********************************** scheduler ********************************* +valid: 0 +PC: 0 +wid: 2 +rd: -1 rs1: -1 rs2: -1 +is_lw: 0 +is_sw: 0 +fetch_stall_cycles: 0 +mem_stall_cycles: 0 +stall_warp: 0 +wspawn: 0 +stalled: 0 +********************************** Decode ********************************* +valid: 0 +PC: 0 +wid: 3 +rd: -1 rs1: -1 rs2: -1 +is_lw: 0 +is_sw: 0 +fetch_stall_cycles: 0 +mem_stall_cycles: 0 +stall_warp: 0 +wspawn: 0 +stalled: 0 +********************************** Fetch ********************************* +valid: 0 +PC: 0 +wid: 4 +rd: -1 rs1: -1 rs2: -1 +is_lw: 0 +is_sw: 0 +fetch_stall_cycles: 0 +mem_stall_cycles: 0 +stall_warp: 0 +wspawn: 0 +stalled: 0 + + + +------------------------------------------------------ +CYCLE: 246 +Stalled Warps: +1 0 0 0 0 0 0 0 + +********************************** Writeback ********************************* +valid: 0 +PC: 0 +wid: 5 +rd: -1 rs1: -1 rs2: -1 +is_lw: 0 +is_sw: 0 +fetch_stall_cycles: 0 +mem_stall_cycles: 0 +stall_warp: 0 +wspawn: 0 +stalled: 0 +********************************** LSU ********************************* +valid: 0 +PC: 0 +wid: 1 +rd: -1 rs1: -1 rs2: -1 +is_lw: 0 +is_sw: 0 +fetch_stall_cycles: 0 +mem_stall_cycles: 0 +stall_warp: 0 +wspawn: 0 +stalled: 0 +********************************** execute_unit ********************************* +valid: 0 +PC: 0 +wid: 2 +rd: -1 rs1: -1 rs2: -1 +is_lw: 0 +is_sw: 0 +fetch_stall_cycles: 0 +mem_stall_cycles: 0 +stall_warp: 0 +wspawn: 0 +stalled: 0 +********************************** scheduler ********************************* +valid: 0 +PC: 0 +wid: 3 +rd: -1 rs1: -1 rs2: -1 +is_lw: 0 +is_sw: 0 +fetch_stall_cycles: 0 +mem_stall_cycles: 0 +stall_warp: 0 +wspawn: 0 +stalled: 0 +********************************** Decode ********************************* +valid: 0 +PC: 0 +wid: 4 +rd: -1 rs1: -1 rs2: -1 +is_lw: 0 +is_sw: 0 +fetch_stall_cycles: 0 +mem_stall_cycles: 0 +stall_warp: 0 +wspawn: 0 +stalled: 0 +********************************** Fetch ********************************* +valid: 0 +PC: 0 +wid: 5 +rd: -1 rs1: -1 rs2: -1 +is_lw: 0 +is_sw: 0 +fetch_stall_cycles: 0 +mem_stall_cycles: 0 +stall_warp: 0 +wspawn: 0 +stalled: 0 +Warp ID 0 is running + + + +------------------------------------------------------ +CYCLE: 247 +Stalled Warps: +0 0 0 0 0 0 0 0 + +********************************** Writeback ********************************* +valid: 0 +PC: 0 +wid: 0 +rd: -1 rs1: -1 rs2: -1 +is_lw: 0 +is_sw: 0 +fetch_stall_cycles: 0 +mem_stall_cycles: 0 +stall_warp: 0 +wspawn: 0 +stalled: 0 +********************************** LSU ********************************* +valid: 0 +PC: 0 +wid: 1 +rd: -1 rs1: -1 rs2: -1 +is_lw: 0 +is_sw: 0 +fetch_stall_cycles: 0 +mem_stall_cycles: 0 +stall_warp: 0 +wspawn: 0 +stalled: 0 +********************************** execute_unit ********************************* +valid: 0 +PC: 0 +wid: 3 +rd: -1 rs1: -1 rs2: -1 +is_lw: 0 +is_sw: 0 +fetch_stall_cycles: 0 +mem_stall_cycles: 0 +stall_warp: 0 +wspawn: 0 +stalled: 0 +********************************** scheduler ********************************* +valid: 0 +PC: 0 +wid: 4 +rd: -1 rs1: -1 rs2: -1 +is_lw: 0 +is_sw: 0 +fetch_stall_cycles: 0 +mem_stall_cycles: 0 +stall_warp: 0 +wspawn: 0 +stalled: 0 +********************************** Decode ********************************* +valid: 0 +PC: 0 +wid: 5 +rd: -1 rs1: -1 rs2: -1 +is_lw: 0 +is_sw: 0 +fetch_stall_cycles: 0 +mem_stall_cycles: 0 +stall_warp: 0 +wspawn: 0 +stalled: 0 +DEBUG ../core.cpp:386: Core step stepping warp 0[1] +DEBUG ../core.cpp:683: in step pc=0x80000b14 +help: in PC: 80000b14 +CUrrent CODE: 271813 +DEBUG ../core.cpp:703: Fetched at 0x80000b14 +DEBUG ../core.cpp:704: 0x80000b14: i_type; +DEBUG ../instruction.cpp:350: Begin instruction execute. +DEBUG ../instruction.cpp:2117: End instruction execute. +DEBUG ../core.cpp:717: Register state: + %r 0: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r 1: 8000003c 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r 2: 6ffff000 6fffec04 6fffe808 6fffe40c 00000000 00000000 00000000 00000000 (0) + %r 3: 80001808 80001808 80001808 80001808 00000000 00000000 00000000 00000000 (0) + %r 4: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r 5: 80000a6c 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r 6: 0000000f 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r 7: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r 8: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r 9: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r10: 00000000 00000001 00000001 00000001 00000000 00000000 00000000 00000000 (0) + %r11: 80000924 00000400 00000800 00000c00 00000000 00000000 00000000 00000000 (0) + %r12: 00000000 00000004 00000008 0000000c 00000000 00000000 00000000 00000000 (0) + %r13: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r14: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r15: 80001154 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r16: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r17: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r18: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r19: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r20: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r21: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r22: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r23: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r24: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r25: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r26: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r27: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r28: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r29: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r30: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r31: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) +DEBUG ../core.cpp:726: Thread mask: + 1 0 0 0 0 0 0 0 + + +DEBUG ../core.cpp:388: Now 1 active threads in 0 +********************************** Fetch ********************************* +valid: 1 +PC: 80000b14 +wid: 0 +rd: 16 rs1: 14 rs2: -1 +is_lw: 0 +is_sw: 0 +fetch_stall_cycles: 0 +mem_stall_cycles: 0 +stall_warp: 0 +wspawn: 0 +stalled: 0 + + + +------------------------------------------------------ +CYCLE: 248 +Stalled Warps: +0 0 0 0 0 0 0 0 + +********************************** Writeback ********************************* +valid: 0 +PC: 0 +wid: 0 +rd: -1 rs1: -1 rs2: -1 +is_lw: 0 +is_sw: 0 +fetch_stall_cycles: 0 +mem_stall_cycles: 0 +stall_warp: 0 +wspawn: 0 +stalled: 0 +********************************** LSU ********************************* +valid: 0 +PC: 0 +wid: 1 +rd: -1 rs1: -1 rs2: -1 +is_lw: 0 +is_sw: 0 +fetch_stall_cycles: 0 +mem_stall_cycles: 0 +stall_warp: 0 +wspawn: 0 +stalled: 0 +********************************** execute_unit ********************************* +valid: 0 +PC: 0 +wid: 4 +rd: -1 rs1: -1 rs2: -1 +is_lw: 0 +is_sw: 0 +fetch_stall_cycles: 0 +mem_stall_cycles: 0 +stall_warp: 0 +wspawn: 0 +stalled: 0 +********************************** scheduler ********************************* +valid: 0 +PC: 0 +wid: 5 +rd: -1 rs1: -1 rs2: -1 +is_lw: 0 +is_sw: 0 +fetch_stall_cycles: 0 +mem_stall_cycles: 0 +stall_warp: 0 +wspawn: 0 +stalled: 0 +********************************** Decode ********************************* +valid: 1 +PC: 80000b14 +wid: 0 +rd: 16 rs1: 14 rs2: -1 +is_lw: 0 +is_sw: 0 +fetch_stall_cycles: 0 +mem_stall_cycles: 0 +stall_warp: 0 +wspawn: 0 +stalled: 0 +DEBUG ../core.cpp:386: Core step stepping warp 0[1] +DEBUG ../core.cpp:683: in step pc=0x80000b18 +help: in PC: 80000b18 +CUrrent CODE: 2050663 +DEBUG ../core.cpp:703: Fetched at 0x80000b18 +DEBUG ../core.cpp:704: 0x80000b18: branch; +DEBUG ../instruction.cpp:350: Begin instruction execute. +DEBUG ../instruction.cpp:2117: End instruction execute. +Next PC: 80000b44 +DEBUG ../core.cpp:717: Register state: + %r 0: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r 1: 8000003c 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r 2: 6ffff000 6fffec04 6fffe808 6fffe40c 00000000 00000000 00000000 00000000 (0) + %r 3: 80001808 80001808 80001808 80001808 00000000 00000000 00000000 00000000 (0) + %r 4: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r 5: 80000a6c 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r 6: 0000000f 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r 7: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r 8: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r 9: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r10: 00000000 00000001 00000001 00000001 00000000 00000000 00000000 00000000 (0) + %r11: 80000924 00000400 00000800 00000c00 00000000 00000000 00000000 00000000 (0) + %r12: 00000000 00000004 00000008 0000000c 00000000 00000000 00000000 00000000 (0) + %r13: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r14: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r15: 80001154 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r16: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r17: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r18: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r19: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r20: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r21: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r22: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r23: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r24: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r25: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r26: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r27: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r28: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r29: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r30: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r31: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) +DEBUG ../core.cpp:726: Thread mask: + 1 0 0 0 0 0 0 0 + + +DEBUG ../core.cpp:388: Now 1 active threads in 0 +********************************** Fetch ********************************* +valid: 1 +PC: 80000b18 +wid: 0 +rd: -1 rs1: 10 rs2: 0 +is_lw: 0 +is_sw: 0 +fetch_stall_cycles: 0 +mem_stall_cycles: 0 +stall_warp: 1 +wspawn: 0 +stalled: 0 + + + +------------------------------------------------------ +CYCLE: 249 +Stalled Warps: +1 0 0 0 0 0 0 0 + +********************************** Writeback ********************************* +valid: 0 +PC: 0 +wid: 1 +rd: -1 rs1: -1 rs2: -1 +is_lw: 0 +is_sw: 0 +fetch_stall_cycles: 0 +mem_stall_cycles: 0 +stall_warp: 0 +wspawn: 0 +stalled: 0 +********************************** LSU ********************************* +valid: 0 +PC: 0 +wid: 1 +rd: -1 rs1: -1 rs2: -1 +is_lw: 0 +is_sw: 0 +fetch_stall_cycles: 0 +mem_stall_cycles: 0 +stall_warp: 0 +wspawn: 0 +stalled: 0 +********************************** execute_unit ********************************* +valid: 0 +PC: 0 +wid: 5 +rd: -1 rs1: -1 rs2: -1 +is_lw: 0 +is_sw: 0 +fetch_stall_cycles: 0 +mem_stall_cycles: 0 +stall_warp: 0 +wspawn: 0 +stalled: 0 +********************************** scheduler ********************************* +valid: 1 +PC: 80000b14 +wid: 0 +rd: 16 rs1: 14 rs2: -1 +is_lw: 0 +is_sw: 0 +fetch_stall_cycles: 0 +mem_stall_cycles: 0 +stall_warp: 0 +wspawn: 0 +stalled: 0 +********************************** Decode ********************************* +valid: 1 +PC: 80000b18 +wid: 0 +rd: -1 rs1: 10 rs2: 0 +is_lw: 0 +is_sw: 0 +fetch_stall_cycles: 0 +mem_stall_cycles: 0 +stall_warp: 1 +wspawn: 0 +stalled: 0 +********************************** Fetch ********************************* +valid: 0 +PC: 0 +wid: 1 +rd: -1 rs1: -1 rs2: -1 +is_lw: 0 +is_sw: 0 +fetch_stall_cycles: 0 +mem_stall_cycles: 0 +stall_warp: 0 +wspawn: 0 +stalled: 0 + + + +------------------------------------------------------ +CYCLE: 250 +Stalled Warps: +1 0 0 0 0 0 0 0 + +********************************** Writeback ********************************* +valid: 0 +PC: 0 +wid: 2 +rd: -1 rs1: -1 rs2: -1 +is_lw: 0 +is_sw: 0 +fetch_stall_cycles: 0 +mem_stall_cycles: 0 +stall_warp: 0 +wspawn: 0 +stalled: 0 +********************************** LSU ********************************* +valid: 0 +PC: 0 +wid: 1 +rd: -1 rs1: -1 rs2: -1 +is_lw: 0 +is_sw: 0 +fetch_stall_cycles: 0 +mem_stall_cycles: 0 +stall_warp: 0 +wspawn: 0 +stalled: 0 +********************************** execute_unit ********************************* +valid: 1 +PC: 80000b14 +wid: 0 +rd: 16 rs1: 14 rs2: -1 +is_lw: 0 +is_sw: 0 +fetch_stall_cycles: 0 +mem_stall_cycles: 0 +stall_warp: 0 +wspawn: 0 +stalled: 0 +********************************** scheduler ********************************* +valid: 1 +PC: 80000b18 +wid: 0 +rd: -1 rs1: 10 rs2: 0 +is_lw: 0 +is_sw: 0 +fetch_stall_cycles: 0 +mem_stall_cycles: 0 +stall_warp: 1 +wspawn: 0 +stalled: 0 +********************************** Decode ********************************* +valid: 0 +PC: 0 +wid: 1 +rd: -1 rs1: -1 rs2: -1 +is_lw: 0 +is_sw: 0 +fetch_stall_cycles: 0 +mem_stall_cycles: 0 +stall_warp: 0 +wspawn: 0 +stalled: 0 +********************************** Fetch ********************************* +valid: 0 +PC: 0 +wid: 2 +rd: -1 rs1: -1 rs2: -1 +is_lw: 0 +is_sw: 0 +fetch_stall_cycles: 0 +mem_stall_cycles: 0 +stall_warp: 0 +wspawn: 0 +stalled: 0 + + + +------------------------------------------------------ +CYCLE: 251 +Stalled Warps: +1 0 0 0 0 0 0 0 + +********************************** Writeback ********************************* +valid: 1 +PC: 80000b14 +wid: 0 +rd: 16 rs1: 14 rs2: -1 +is_lw: 0 +is_sw: 0 +fetch_stall_cycles: 0 +mem_stall_cycles: 0 +stall_warp: 0 +wspawn: 0 +stalled: 0 +********************************** LSU ********************************* +valid: 0 +PC: 0 +wid: 1 +rd: -1 rs1: -1 rs2: -1 +is_lw: 0 +is_sw: 0 +fetch_stall_cycles: 0 +mem_stall_cycles: 0 +stall_warp: 0 +wspawn: 0 +stalled: 0 +********************************** execute_unit ********************************* +valid: 1 +PC: 80000b18 +wid: 0 +rd: -1 rs1: 10 rs2: 0 +is_lw: 0 +is_sw: 0 +fetch_stall_cycles: 0 +mem_stall_cycles: 0 +stall_warp: 1 +wspawn: 0 +stalled: 0 +********************************** scheduler ********************************* +valid: 0 +PC: 0 +wid: 1 +rd: -1 rs1: -1 rs2: -1 +is_lw: 0 +is_sw: 0 +fetch_stall_cycles: 0 +mem_stall_cycles: 0 +stall_warp: 0 +wspawn: 0 +stalled: 0 +********************************** Decode ********************************* +valid: 0 +PC: 0 +wid: 2 +rd: -1 rs1: -1 rs2: -1 +is_lw: 0 +is_sw: 0 +fetch_stall_cycles: 0 +mem_stall_cycles: 0 +stall_warp: 0 +wspawn: 0 +stalled: 0 +********************************** Fetch ********************************* +valid: 0 +PC: 0 +wid: 3 +rd: -1 rs1: -1 rs2: -1 +is_lw: 0 +is_sw: 0 +fetch_stall_cycles: 0 +mem_stall_cycles: 0 +stall_warp: 0 +wspawn: 0 +stalled: 0 + + + +------------------------------------------------------ +CYCLE: 252 +Stalled Warps: +1 0 0 0 0 0 0 0 + +********************************** Writeback ********************************* +valid: 1 +PC: 80000b18 +wid: 0 +rd: -1 rs1: 10 rs2: 0 +is_lw: 0 +is_sw: 0 +fetch_stall_cycles: 0 +mem_stall_cycles: 0 +stall_warp: 1 +wspawn: 0 +stalled: 0 +********************************** LSU ********************************* +valid: 0 +PC: 0 +wid: 1 +rd: -1 rs1: -1 rs2: -1 +is_lw: 0 +is_sw: 0 +fetch_stall_cycles: 0 +mem_stall_cycles: 0 +stall_warp: 0 +wspawn: 0 +stalled: 0 +********************************** execute_unit ********************************* +valid: 0 +PC: 0 +wid: 1 +rd: -1 rs1: -1 rs2: -1 +is_lw: 0 +is_sw: 0 +fetch_stall_cycles: 0 +mem_stall_cycles: 0 +stall_warp: 0 +wspawn: 0 +stalled: 0 +********************************** scheduler ********************************* +valid: 0 +PC: 0 +wid: 2 +rd: -1 rs1: -1 rs2: -1 +is_lw: 0 +is_sw: 0 +fetch_stall_cycles: 0 +mem_stall_cycles: 0 +stall_warp: 0 +wspawn: 0 +stalled: 0 +********************************** Decode ********************************* +valid: 0 +PC: 0 +wid: 3 +rd: -1 rs1: -1 rs2: -1 +is_lw: 0 +is_sw: 0 +fetch_stall_cycles: 0 +mem_stall_cycles: 0 +stall_warp: 0 +wspawn: 0 +stalled: 0 +********************************** Fetch ********************************* +valid: 0 +PC: 0 +wid: 4 +rd: -1 rs1: -1 rs2: -1 +is_lw: 0 +is_sw: 0 +fetch_stall_cycles: 0 +mem_stall_cycles: 0 +stall_warp: 0 +wspawn: 0 +stalled: 0 + + + +------------------------------------------------------ +CYCLE: 253 +Stalled Warps: +1 0 0 0 0 0 0 0 + +********************************** Writeback ********************************* +valid: 0 +PC: 0 +wid: 5 +rd: -1 rs1: -1 rs2: -1 +is_lw: 0 +is_sw: 0 +fetch_stall_cycles: 0 +mem_stall_cycles: 0 +stall_warp: 0 +wspawn: 0 +stalled: 0 +********************************** LSU ********************************* +valid: 0 +PC: 0 +wid: 1 +rd: -1 rs1: -1 rs2: -1 +is_lw: 0 +is_sw: 0 +fetch_stall_cycles: 0 +mem_stall_cycles: 0 +stall_warp: 0 +wspawn: 0 +stalled: 0 +********************************** execute_unit ********************************* +valid: 0 +PC: 0 +wid: 2 +rd: -1 rs1: -1 rs2: -1 +is_lw: 0 +is_sw: 0 +fetch_stall_cycles: 0 +mem_stall_cycles: 0 +stall_warp: 0 +wspawn: 0 +stalled: 0 +********************************** scheduler ********************************* +valid: 0 +PC: 0 +wid: 3 +rd: -1 rs1: -1 rs2: -1 +is_lw: 0 +is_sw: 0 +fetch_stall_cycles: 0 +mem_stall_cycles: 0 +stall_warp: 0 +wspawn: 0 +stalled: 0 +********************************** Decode ********************************* +valid: 0 +PC: 0 +wid: 4 +rd: -1 rs1: -1 rs2: -1 +is_lw: 0 +is_sw: 0 +fetch_stall_cycles: 0 +mem_stall_cycles: 0 +stall_warp: 0 +wspawn: 0 +stalled: 0 +********************************** Fetch ********************************* +valid: 0 +PC: 0 +wid: 5 +rd: -1 rs1: -1 rs2: -1 +is_lw: 0 +is_sw: 0 +fetch_stall_cycles: 0 +mem_stall_cycles: 0 +stall_warp: 0 +wspawn: 0 +stalled: 0 +Warp ID 0 is running + + + +------------------------------------------------------ +CYCLE: 254 +Stalled Warps: +0 0 0 0 0 0 0 0 + +********************************** Writeback ********************************* +valid: 0 +PC: 0 +wid: 0 +rd: -1 rs1: -1 rs2: -1 +is_lw: 0 +is_sw: 0 +fetch_stall_cycles: 0 +mem_stall_cycles: 0 +stall_warp: 0 +wspawn: 0 +stalled: 0 +********************************** LSU ********************************* +valid: 0 +PC: 0 +wid: 1 +rd: -1 rs1: -1 rs2: -1 +is_lw: 0 +is_sw: 0 +fetch_stall_cycles: 0 +mem_stall_cycles: 0 +stall_warp: 0 +wspawn: 0 +stalled: 0 +********************************** execute_unit ********************************* +valid: 0 +PC: 0 +wid: 3 +rd: -1 rs1: -1 rs2: -1 +is_lw: 0 +is_sw: 0 +fetch_stall_cycles: 0 +mem_stall_cycles: 0 +stall_warp: 0 +wspawn: 0 +stalled: 0 +********************************** scheduler ********************************* +valid: 0 +PC: 0 +wid: 4 +rd: -1 rs1: -1 rs2: -1 +is_lw: 0 +is_sw: 0 +fetch_stall_cycles: 0 +mem_stall_cycles: 0 +stall_warp: 0 +wspawn: 0 +stalled: 0 +********************************** Decode ********************************* +valid: 0 +PC: 0 +wid: 5 +rd: -1 rs1: -1 rs2: -1 +is_lw: 0 +is_sw: 0 +fetch_stall_cycles: 0 +mem_stall_cycles: 0 +stall_warp: 0 +wspawn: 0 +stalled: 0 +DEBUG ../core.cpp:386: Core step stepping warp 0[1] +DEBUG ../core.cpp:683: in step pc=0x80000b44 +help: in PC: 80000b44 +CUrrent CODE: 170713 +DEBUG ../core.cpp:703: Fetched at 0x80000b44 +DEBUG ../core.cpp:704: 0x80000b44: i_type; +DEBUG ../instruction.cpp:350: Begin instruction execute. +DEBUG ../instruction.cpp:2117: End instruction execute. +DEBUG ../core.cpp:717: Register state: + %r 0: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r 1: 8000003c 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r 2: 6ffff000 6fffec04 6fffe808 6fffe40c 00000000 00000000 00000000 00000000 (0) + %r 3: 80001808 80001808 80001808 80001808 00000000 00000000 00000000 00000000 (0) + %r 4: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r 5: 80000a6c 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r 6: 0000000f 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r 7: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r 8: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r 9: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r10: 00000000 00000001 00000001 00000001 00000000 00000000 00000000 00000000 (0) + %r11: 80000924 00000400 00000800 00000c00 00000000 00000000 00000000 00000000 (0) + %r12: 00000000 00000004 00000008 0000000c 00000000 00000000 00000000 00000000 (0) + %r13: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r14: 00000001 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r15: 80001154 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r16: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r17: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r18: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r19: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r20: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r21: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r22: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r23: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r24: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r25: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r26: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r27: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r28: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r29: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r30: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r31: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) +DEBUG ../core.cpp:726: Thread mask: + 1 0 0 0 0 0 0 0 + + +DEBUG ../core.cpp:388: Now 1 active threads in 0 +********************************** Fetch ********************************* +valid: 1 +PC: 80000b44 +wid: 0 +rd: 14 rs1: 14 rs2: -1 +is_lw: 0 +is_sw: 0 +fetch_stall_cycles: 3 +mem_stall_cycles: 0 +stall_warp: 0 +wspawn: 0 +stalled: 0 + + + +------------------------------------------------------ +CYCLE: 255 +Stalled Warps: +0 0 0 0 0 0 0 0 + +********************************** Writeback ********************************* +valid: 0 +PC: 0 +wid: 0 +rd: -1 rs1: -1 rs2: -1 +is_lw: 0 +is_sw: 0 +fetch_stall_cycles: 0 +mem_stall_cycles: 0 +stall_warp: 0 +wspawn: 0 +stalled: 0 +********************************** LSU ********************************* +valid: 0 +PC: 0 +wid: 1 +rd: -1 rs1: -1 rs2: -1 +is_lw: 0 +is_sw: 0 +fetch_stall_cycles: 0 +mem_stall_cycles: 0 +stall_warp: 0 +wspawn: 0 +stalled: 0 +********************************** execute_unit ********************************* +valid: 0 +PC: 0 +wid: 4 +rd: -1 rs1: -1 rs2: -1 +is_lw: 0 +is_sw: 0 +fetch_stall_cycles: 0 +mem_stall_cycles: 0 +stall_warp: 0 +wspawn: 0 +stalled: 0 +********************************** scheduler ********************************* +valid: 0 +PC: 0 +wid: 5 +rd: -1 rs1: -1 rs2: -1 +is_lw: 0 +is_sw: 0 +fetch_stall_cycles: 0 +mem_stall_cycles: 0 +stall_warp: 0 +wspawn: 0 +stalled: 0 +********************************** Decode ********************************* +valid: 0 +PC: 0 +wid: 0 +rd: -1 rs1: -1 rs2: -1 +is_lw: 0 +is_sw: 0 +fetch_stall_cycles: 0 +mem_stall_cycles: 0 +stall_warp: 0 +wspawn: 0 +stalled: 0 +********************************** Fetch ********************************* +valid: 1 +PC: 80000b44 +wid: 0 +rd: 14 rs1: 14 rs2: -1 +is_lw: 0 +is_sw: 0 +fetch_stall_cycles: 2 +mem_stall_cycles: 0 +stall_warp: 0 +wspawn: 0 +stalled: 0 + + + +------------------------------------------------------ +CYCLE: 256 +Stalled Warps: +0 0 0 0 0 0 0 0 + +********************************** Writeback ********************************* +valid: 0 +PC: 0 +wid: 0 +rd: -1 rs1: -1 rs2: -1 +is_lw: 0 +is_sw: 0 +fetch_stall_cycles: 0 +mem_stall_cycles: 0 +stall_warp: 0 +wspawn: 0 +stalled: 0 +********************************** LSU ********************************* +valid: 0 +PC: 0 +wid: 1 +rd: -1 rs1: -1 rs2: -1 +is_lw: 0 +is_sw: 0 +fetch_stall_cycles: 0 +mem_stall_cycles: 0 +stall_warp: 0 +wspawn: 0 +stalled: 0 +********************************** execute_unit ********************************* +valid: 0 +PC: 0 +wid: 5 +rd: -1 rs1: -1 rs2: -1 +is_lw: 0 +is_sw: 0 +fetch_stall_cycles: 0 +mem_stall_cycles: 0 +stall_warp: 0 +wspawn: 0 +stalled: 0 +********************************** scheduler ********************************* +valid: 0 +PC: 0 +wid: 0 +rd: -1 rs1: -1 rs2: -1 +is_lw: 0 +is_sw: 0 +fetch_stall_cycles: 0 +mem_stall_cycles: 0 +stall_warp: 0 +wspawn: 0 +stalled: 0 +********************************** Decode ********************************* +valid: 0 +PC: 0 +wid: 0 +rd: -1 rs1: -1 rs2: -1 +is_lw: 0 +is_sw: 0 +fetch_stall_cycles: 0 +mem_stall_cycles: 0 +stall_warp: 0 +wspawn: 0 +stalled: 0 +********************************** Fetch ********************************* +valid: 1 +PC: 80000b44 +wid: 0 +rd: 14 rs1: 14 rs2: -1 +is_lw: 0 +is_sw: 0 +fetch_stall_cycles: 1 +mem_stall_cycles: 0 +stall_warp: 0 +wspawn: 0 +stalled: 0 + + + +------------------------------------------------------ +CYCLE: 257 +Stalled Warps: +0 0 0 0 0 0 0 0 + +********************************** Writeback ********************************* +valid: 0 +PC: 0 +wid: 0 +rd: -1 rs1: -1 rs2: -1 +is_lw: 0 +is_sw: 0 +fetch_stall_cycles: 0 +mem_stall_cycles: 0 +stall_warp: 0 +wspawn: 0 +stalled: 0 +********************************** LSU ********************************* +valid: 0 +PC: 0 +wid: 1 +rd: -1 rs1: -1 rs2: -1 +is_lw: 0 +is_sw: 0 +fetch_stall_cycles: 0 +mem_stall_cycles: 0 +stall_warp: 0 +wspawn: 0 +stalled: 0 +********************************** execute_unit ********************************* +valid: 0 +PC: 0 +wid: 0 +rd: -1 rs1: -1 rs2: -1 +is_lw: 0 +is_sw: 0 +fetch_stall_cycles: 0 +mem_stall_cycles: 0 +stall_warp: 0 +wspawn: 0 +stalled: 0 +********************************** scheduler ********************************* +valid: 0 +PC: 0 +wid: 0 +rd: -1 rs1: -1 rs2: -1 +is_lw: 0 +is_sw: 0 +fetch_stall_cycles: 0 +mem_stall_cycles: 0 +stall_warp: 0 +wspawn: 0 +stalled: 0 +********************************** Decode ********************************* +valid: 0 +PC: 0 +wid: 0 +rd: -1 rs1: -1 rs2: -1 +is_lw: 0 +is_sw: 0 +fetch_stall_cycles: 0 +mem_stall_cycles: 0 +stall_warp: 0 +wspawn: 0 +stalled: 0 +********************************** Fetch ********************************* +valid: 1 +PC: 80000b44 +wid: 0 +rd: 14 rs1: 14 rs2: -1 +is_lw: 0 +is_sw: 0 +fetch_stall_cycles: 0 +mem_stall_cycles: 0 +stall_warp: 0 +wspawn: 0 +stalled: 0 + + + +------------------------------------------------------ +CYCLE: 258 +Stalled Warps: +0 0 0 0 0 0 0 0 + +********************************** Writeback ********************************* +valid: 0 +PC: 0 +wid: 0 +rd: -1 rs1: -1 rs2: -1 +is_lw: 0 +is_sw: 0 +fetch_stall_cycles: 0 +mem_stall_cycles: 0 +stall_warp: 0 +wspawn: 0 +stalled: 0 +********************************** LSU ********************************* +valid: 0 +PC: 0 +wid: 1 +rd: -1 rs1: -1 rs2: -1 +is_lw: 0 +is_sw: 0 +fetch_stall_cycles: 0 +mem_stall_cycles: 0 +stall_warp: 0 +wspawn: 0 +stalled: 0 +********************************** execute_unit ********************************* +valid: 0 +PC: 0 +wid: 0 +rd: -1 rs1: -1 rs2: -1 +is_lw: 0 +is_sw: 0 +fetch_stall_cycles: 0 +mem_stall_cycles: 0 +stall_warp: 0 +wspawn: 0 +stalled: 0 +********************************** scheduler ********************************* +valid: 0 +PC: 0 +wid: 0 +rd: -1 rs1: -1 rs2: -1 +is_lw: 0 +is_sw: 0 +fetch_stall_cycles: 0 +mem_stall_cycles: 0 +stall_warp: 0 +wspawn: 0 +stalled: 0 +********************************** Decode ********************************* +valid: 1 +PC: 80000b44 +wid: 0 +rd: 14 rs1: 14 rs2: -1 +is_lw: 0 +is_sw: 0 +fetch_stall_cycles: 0 +mem_stall_cycles: 0 +stall_warp: 0 +wspawn: 0 +stalled: 0 +DEBUG ../core.cpp:386: Core step stepping warp 0[1] +DEBUG ../core.cpp:683: in step pc=0x80000b48 +help: in PC: 80000b48 +CUrrent CODE: e7a223 +DEBUG ../core.cpp:703: Fetched at 0x80000b48 +DEBUG ../core.cpp:704: 0x80000b48: store; +DEBUG ../instruction.cpp:350: Begin instruction execute. +STORE MEM ADDRESS: 80001154 + 4 +DEBUG ../instruction.cpp:2117: End instruction execute. +DEBUG ../core.cpp:717: Register state: + %r 0: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r 1: 8000003c 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r 2: 6ffff000 6fffec04 6fffe808 6fffe40c 00000000 00000000 00000000 00000000 (0) + %r 3: 80001808 80001808 80001808 80001808 00000000 00000000 00000000 00000000 (0) + %r 4: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r 5: 80000a6c 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r 6: 0000000f 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r 7: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r 8: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r 9: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r10: 00000000 00000001 00000001 00000001 00000000 00000000 00000000 00000000 (0) + %r11: 80000924 00000400 00000800 00000c00 00000000 00000000 00000000 00000000 (0) + %r12: 00000000 00000004 00000008 0000000c 00000000 00000000 00000000 00000000 (0) + %r13: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r14: 00000001 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r15: 80001154 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r16: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r17: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r18: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r19: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r20: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r21: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r22: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r23: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r24: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r25: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r26: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r27: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r28: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r29: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r30: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r31: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) +DEBUG ../core.cpp:726: Thread mask: + 1 0 0 0 0 0 0 0 + + +DEBUG ../core.cpp:388: Now 1 active threads in 0 +********************************** Fetch ********************************* +valid: 1 +PC: 80000b48 +wid: 0 +rd: -1 rs1: 15 rs2: 14 +is_lw: 0 +is_sw: 1 +fetch_stall_cycles: 0 +mem_stall_cycles: 0 +stall_warp: 0 +wspawn: 0 +stalled: 0 + + + +------------------------------------------------------ +CYCLE: 259 +Stalled Warps: +0 0 0 0 0 0 0 0 + +********************************** Writeback ********************************* +valid: 0 +PC: 0 +wid: 0 +rd: -1 rs1: -1 rs2: -1 +is_lw: 0 +is_sw: 0 +fetch_stall_cycles: 0 +mem_stall_cycles: 0 +stall_warp: 0 +wspawn: 0 +stalled: 0 +********************************** LSU ********************************* +valid: 0 +PC: 0 +wid: 1 +rd: -1 rs1: -1 rs2: -1 +is_lw: 0 +is_sw: 0 +fetch_stall_cycles: 0 +mem_stall_cycles: 0 +stall_warp: 0 +wspawn: 0 +stalled: 0 +********************************** execute_unit ********************************* +valid: 0 +PC: 0 +wid: 0 +rd: -1 rs1: -1 rs2: -1 +is_lw: 0 +is_sw: 0 +fetch_stall_cycles: 0 +mem_stall_cycles: 0 +stall_warp: 0 +wspawn: 0 +stalled: 0 +********************************** scheduler ********************************* +valid: 1 +PC: 80000b44 +wid: 0 +rd: 14 rs1: 14 rs2: -1 +is_lw: 0 +is_sw: 0 +fetch_stall_cycles: 0 +mem_stall_cycles: 0 +stall_warp: 0 +wspawn: 0 +stalled: 0 +********************************** Decode ********************************* +valid: 1 +PC: 80000b48 +wid: 0 +rd: -1 rs1: 15 rs2: 14 +is_lw: 0 +is_sw: 1 +fetch_stall_cycles: 0 +mem_stall_cycles: 0 +stall_warp: 0 +wspawn: 0 +stalled: 0 +DEBUG ../core.cpp:386: Core step stepping warp 0[1] +DEBUG ../core.cpp:683: in step pc=0x80000b4c +help: in PC: 80000b4c +CUrrent CODE: 10787b3 +DEBUG ../core.cpp:703: Fetched at 0x80000b4c +DEBUG ../core.cpp:704: 0x80000b4c: r_type; +DEBUG ../instruction.cpp:350: Begin instruction execute. +DEBUG ../instruction.cpp:2117: End instruction execute. +DEBUG ../core.cpp:717: Register state: + %r 0: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r 1: 8000003c 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r 2: 6ffff000 6fffec04 6fffe808 6fffe40c 00000000 00000000 00000000 00000000 (0) + %r 3: 80001808 80001808 80001808 80001808 00000000 00000000 00000000 00000000 (0) + %r 4: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r 5: 80000a6c 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r 6: 0000000f 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r 7: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r 8: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r 9: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r10: 00000000 00000001 00000001 00000001 00000000 00000000 00000000 00000000 (0) + %r11: 80000924 00000400 00000800 00000c00 00000000 00000000 00000000 00000000 (0) + %r12: 00000000 00000004 00000008 0000000c 00000000 00000000 00000000 00000000 (0) + %r13: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r14: 00000001 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r15: 80001154 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r16: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r17: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r18: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r19: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r20: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r21: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r22: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r23: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r24: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r25: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r26: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r27: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r28: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r29: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r30: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r31: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) +DEBUG ../core.cpp:726: Thread mask: + 1 0 0 0 0 0 0 0 + + +DEBUG ../core.cpp:388: Now 1 active threads in 0 +********************************** Fetch ********************************* +valid: 1 +PC: 80000b4c +wid: 0 +rd: 15 rs1: 15 rs2: 16 +is_lw: 0 +is_sw: 0 +fetch_stall_cycles: 0 +mem_stall_cycles: 0 +stall_warp: 0 +wspawn: 0 +stalled: 0 + + + +------------------------------------------------------ +CYCLE: 260 +Stalled Warps: +0 0 0 0 0 0 0 0 + +********************************** Writeback ********************************* +valid: 0 +PC: 0 +wid: 0 +rd: -1 rs1: -1 rs2: -1 +is_lw: 0 +is_sw: 0 +fetch_stall_cycles: 0 +mem_stall_cycles: 0 +stall_warp: 0 +wspawn: 0 +stalled: 0 +********************************** LSU ********************************* +valid: 0 +PC: 0 +wid: 1 +rd: -1 rs1: -1 rs2: -1 +is_lw: 0 +is_sw: 0 +fetch_stall_cycles: 0 +mem_stall_cycles: 0 +stall_warp: 0 +wspawn: 0 +stalled: 0 +********************************** execute_unit ********************************* +valid: 1 +PC: 80000b44 +wid: 0 +rd: 14 rs1: 14 rs2: -1 +is_lw: 0 +is_sw: 0 +fetch_stall_cycles: 0 +mem_stall_cycles: 0 +stall_warp: 0 +wspawn: 0 +stalled: 0 +********************************** scheduler ********************************* +valid: 1 +PC: 80000b48 +wid: 0 +rd: -1 rs1: 15 rs2: 14 +is_lw: 0 +is_sw: 1 +fetch_stall_cycles: 0 +mem_stall_cycles: 0 +stall_warp: 0 +wspawn: 0 +stalled: 0 +********************************** Decode ********************************* +valid: 1 +PC: 80000b4c +wid: 0 +rd: 15 rs1: 15 rs2: 16 +is_lw: 0 +is_sw: 0 +fetch_stall_cycles: 0 +mem_stall_cycles: 0 +stall_warp: 0 +wspawn: 0 +stalled: 0 +DEBUG ../core.cpp:386: Core step stepping warp 0[1] +DEBUG ../core.cpp:683: in step pc=0x80000b50 +help: in PC: 80000b50 +CUrrent CODE: b7a423 +DEBUG ../core.cpp:703: Fetched at 0x80000b50 +DEBUG ../core.cpp:704: 0x80000b50: store; +DEBUG ../instruction.cpp:350: Begin instruction execute. +STORE MEM ADDRESS: 80001154 + 8 +DEBUG ../instruction.cpp:2117: End instruction execute. +DEBUG ../core.cpp:717: Register state: + %r 0: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r 1: 8000003c 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r 2: 6ffff000 6fffec04 6fffe808 6fffe40c 00000000 00000000 00000000 00000000 (0) + %r 3: 80001808 80001808 80001808 80001808 00000000 00000000 00000000 00000000 (0) + %r 4: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r 5: 80000a6c 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r 6: 0000000f 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r 7: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r 8: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r 9: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r10: 00000000 00000001 00000001 00000001 00000000 00000000 00000000 00000000 (0) + %r11: 80000924 00000400 00000800 00000c00 00000000 00000000 00000000 00000000 (0) + %r12: 00000000 00000004 00000008 0000000c 00000000 00000000 00000000 00000000 (0) + %r13: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r14: 00000001 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r15: 80001154 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r16: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r17: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r18: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r19: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r20: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r21: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r22: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r23: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r24: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r25: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r26: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r27: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r28: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r29: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r30: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r31: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) +DEBUG ../core.cpp:726: Thread mask: + 1 0 0 0 0 0 0 0 + + +DEBUG ../core.cpp:388: Now 1 active threads in 0 +********************************** Fetch ********************************* +valid: 1 +PC: 80000b50 +wid: 0 +rd: -1 rs1: 15 rs2: 11 +is_lw: 0 +is_sw: 1 +fetch_stall_cycles: 0 +mem_stall_cycles: 0 +stall_warp: 0 +wspawn: 0 +stalled: 0 + + + +------------------------------------------------------ +CYCLE: 261 +Stalled Warps: +0 0 0 0 0 0 0 0 + +********************************** Writeback ********************************* +valid: 1 +PC: 80000b44 +wid: 0 +rd: 14 rs1: 14 rs2: -1 +is_lw: 0 +is_sw: 0 +fetch_stall_cycles: 0 +mem_stall_cycles: 0 +stall_warp: 0 +wspawn: 0 +stalled: 0 +********************************** LSU ********************************* +valid: 0 +PC: 0 +wid: 1 +rd: -1 rs1: -1 rs2: -1 +is_lw: 0 +is_sw: 0 +fetch_stall_cycles: 0 +mem_stall_cycles: 0 +stall_warp: 0 +wspawn: 0 +stalled: 0 +********************************** execute_unit ********************************* +valid: 0 +PC: 0 +wid: 0 +rd: -1 rs1: -1 rs2: -1 +is_lw: 0 +is_sw: 0 +fetch_stall_cycles: 0 +mem_stall_cycles: 0 +stall_warp: 0 +wspawn: 0 +stalled: 0 +********************************** scheduler ********************************* +valid: 1 +PC: 80000b48 +wid: 0 +rd: -1 rs1: 15 rs2: 14 +is_lw: 0 +is_sw: 1 +fetch_stall_cycles: 0 +mem_stall_cycles: 0 +stall_warp: 0 +wspawn: 0 +stalled: 1 +********************************** Decode ********************************* +valid: 1 +PC: 80000b4c +wid: 0 +rd: 15 rs1: 15 rs2: 16 +is_lw: 0 +is_sw: 0 +fetch_stall_cycles: 0 +mem_stall_cycles: 0 +stall_warp: 0 +wspawn: 0 +stalled: 0 +********************************** Fetch ********************************* +valid: 1 +PC: 80000b50 +wid: 0 +rd: -1 rs1: 15 rs2: 11 +is_lw: 0 +is_sw: 1 +fetch_stall_cycles: 0 +mem_stall_cycles: 0 +stall_warp: 0 +wspawn: 0 +stalled: 0 + + + +------------------------------------------------------ +CYCLE: 262 +Stalled Warps: +0 0 0 0 0 0 0 0 + +********************************** Writeback ********************************* +valid: 0 +PC: 0 +wid: 0 +rd: -1 rs1: -1 rs2: -1 +is_lw: 0 +is_sw: 0 +fetch_stall_cycles: 0 +mem_stall_cycles: 0 +stall_warp: 0 +wspawn: 0 +stalled: 0 +********************************** LSU ********************************* +valid: 1 +PC: 80000b48 +wid: 0 +rd: -1 rs1: 15 rs2: 14 +is_lw: 0 +is_sw: 1 +fetch_stall_cycles: 0 +mem_stall_cycles: 0 +stall_warp: 0 +wspawn: 0 +stalled: 0 +********************************** execute_unit ********************************* +valid: 0 +PC: 0 +wid: 0 +rd: -1 rs1: -1 rs2: -1 +is_lw: 0 +is_sw: 0 +fetch_stall_cycles: 0 +mem_stall_cycles: 0 +stall_warp: 0 +wspawn: 0 +stalled: 0 +********************************** scheduler ********************************* +valid: 1 +PC: 80000b4c +wid: 0 +rd: 15 rs1: 15 rs2: 16 +is_lw: 0 +is_sw: 0 +fetch_stall_cycles: 0 +mem_stall_cycles: 0 +stall_warp: 0 +wspawn: 0 +stalled: 0 +********************************** Decode ********************************* +valid: 1 +PC: 80000b50 +wid: 0 +rd: -1 rs1: 15 rs2: 11 +is_lw: 0 +is_sw: 1 +fetch_stall_cycles: 0 +mem_stall_cycles: 0 +stall_warp: 0 +wspawn: 0 +stalled: 0 +DEBUG ../core.cpp:386: Core step stepping warp 0[1] +DEBUG ../core.cpp:683: in step pc=0x80000b54 +help: in PC: 80000b54 +CUrrent CODE: 513 +DEBUG ../core.cpp:703: Fetched at 0x80000b54 +DEBUG ../core.cpp:704: 0x80000b54: i_type; +DEBUG ../instruction.cpp:350: Begin instruction execute. +DEBUG ../instruction.cpp:2117: End instruction execute. +DEBUG ../core.cpp:717: Register state: + %r 0: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r 1: 8000003c 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r 2: 6ffff000 6fffec04 6fffe808 6fffe40c 00000000 00000000 00000000 00000000 (0) + %r 3: 80001808 80001808 80001808 80001808 00000000 00000000 00000000 00000000 (0) + %r 4: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r 5: 80000a6c 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r 6: 0000000f 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r 7: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r 8: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r 9: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r10: 00000000 00000001 00000001 00000001 00000000 00000000 00000000 00000000 (0) + %r11: 80000924 00000400 00000800 00000c00 00000000 00000000 00000000 00000000 (0) + %r12: 00000000 00000004 00000008 0000000c 00000000 00000000 00000000 00000000 (0) + %r13: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r14: 00000001 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r15: 80001154 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r16: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r17: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r18: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r19: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r20: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r21: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r22: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r23: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r24: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r25: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r26: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r27: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r28: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r29: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r30: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r31: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) +DEBUG ../core.cpp:726: Thread mask: + 1 0 0 0 0 0 0 0 + + +DEBUG ../core.cpp:388: Now 1 active threads in 0 +********************************** Fetch ********************************* +valid: 1 +PC: 80000b54 +wid: 0 +rd: 10 rs1: 0 rs2: -1 +is_lw: 0 +is_sw: 0 +fetch_stall_cycles: 0 +mem_stall_cycles: 0 +stall_warp: 0 +wspawn: 0 +stalled: 0 + + + +------------------------------------------------------ +CYCLE: 263 +Stalled Warps: +0 0 0 0 0 0 0 0 + +********************************** Writeback ********************************* +valid: 0 +PC: 0 +wid: 0 +rd: -1 rs1: -1 rs2: -1 +is_lw: 0 +is_sw: 0 +fetch_stall_cycles: 0 +mem_stall_cycles: 0 +stall_warp: 0 +wspawn: 0 +stalled: 0 +********************************** LSU ********************************* +valid: 0 +PC: 0 +wid: 0 +rd: -1 rs1: -1 rs2: -1 +is_lw: 0 +is_sw: 0 +fetch_stall_cycles: 0 +mem_stall_cycles: 0 +stall_warp: 0 +wspawn: 0 +stalled: 0 +********************************** execute_unit ********************************* +valid: 1 +PC: 80000b4c +wid: 0 +rd: 15 rs1: 15 rs2: 16 +is_lw: 0 +is_sw: 0 +fetch_stall_cycles: 0 +mem_stall_cycles: 0 +stall_warp: 0 +wspawn: 0 +stalled: 0 +********************************** scheduler ********************************* +valid: 1 +PC: 80000b50 +wid: 0 +rd: -1 rs1: 15 rs2: 11 +is_lw: 0 +is_sw: 1 +fetch_stall_cycles: 0 +mem_stall_cycles: 0 +stall_warp: 0 +wspawn: 0 +stalled: 0 +********************************** Decode ********************************* +valid: 1 +PC: 80000b54 +wid: 0 +rd: 10 rs1: 0 rs2: -1 +is_lw: 0 +is_sw: 0 +fetch_stall_cycles: 0 +mem_stall_cycles: 0 +stall_warp: 0 +wspawn: 0 +stalled: 0 +DEBUG ../core.cpp:386: Core step stepping warp 0[1] +DEBUG ../core.cpp:683: in step pc=0x80000b58 +help: in PC: 80000b58 +CUrrent CODE: 8067 +DEBUG ../core.cpp:703: Fetched at 0x80000b58 +DEBUG ../core.cpp:704: 0x80000b58: jalr; +DEBUG ../instruction.cpp:350: Begin instruction execute. +JALR_INST +DEBUG ../instruction.cpp:2117: End instruction execute. +Next PC: 8000003c +DEBUG ../core.cpp:717: Register state: + %r 0: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r 1: 8000003c 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r 2: 6ffff000 6fffec04 6fffe808 6fffe40c 00000000 00000000 00000000 00000000 (0) + %r 3: 80001808 80001808 80001808 80001808 00000000 00000000 00000000 00000000 (0) + %r 4: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r 5: 80000a6c 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r 6: 0000000f 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r 7: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r 8: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r 9: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r10: 00000000 00000001 00000001 00000001 00000000 00000000 00000000 00000000 (0) + %r11: 80000924 00000400 00000800 00000c00 00000000 00000000 00000000 00000000 (0) + %r12: 00000000 00000004 00000008 0000000c 00000000 00000000 00000000 00000000 (0) + %r13: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r14: 00000001 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r15: 80001154 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r16: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r17: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r18: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r19: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r20: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r21: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r22: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r23: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r24: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r25: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r26: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r27: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r28: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r29: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r30: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r31: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) +DEBUG ../core.cpp:726: Thread mask: + 1 0 0 0 0 0 0 0 + + +DEBUG ../core.cpp:388: Now 1 active threads in 0 +********************************** Fetch ********************************* +valid: 1 +PC: 80000b58 +wid: 0 +rd: 0 rs1: 1 rs2: -1 +is_lw: 0 +is_sw: 0 +fetch_stall_cycles: 0 +mem_stall_cycles: 0 +stall_warp: 1 +wspawn: 0 +stalled: 0 + + + +------------------------------------------------------ +CYCLE: 264 +Stalled Warps: +1 0 0 0 0 0 0 0 + +********************************** Writeback ********************************* +valid: 1 +PC: 80000b4c +wid: 0 +rd: 15 rs1: 15 rs2: 16 +is_lw: 0 +is_sw: 0 +fetch_stall_cycles: 0 +mem_stall_cycles: 0 +stall_warp: 0 +wspawn: 0 +stalled: 0 +********************************** LSU ********************************* +valid: 0 +PC: 0 +wid: 0 +rd: -1 rs1: -1 rs2: -1 +is_lw: 0 +is_sw: 0 +fetch_stall_cycles: 0 +mem_stall_cycles: 0 +stall_warp: 0 +wspawn: 0 +stalled: 0 +********************************** execute_unit ********************************* +valid: 0 +PC: 0 +wid: 1 +rd: -1 rs1: -1 rs2: -1 +is_lw: 0 +is_sw: 0 +fetch_stall_cycles: 0 +mem_stall_cycles: 0 +stall_warp: 0 +wspawn: 0 +stalled: 0 +********************************** scheduler ********************************* +valid: 1 +PC: 80000b50 +wid: 0 +rd: -1 rs1: 15 rs2: 11 +is_lw: 0 +is_sw: 1 +fetch_stall_cycles: 0 +mem_stall_cycles: 0 +stall_warp: 0 +wspawn: 0 +stalled: 1 +********************************** Decode ********************************* +valid: 1 +PC: 80000b54 +wid: 0 +rd: 10 rs1: 0 rs2: -1 +is_lw: 0 +is_sw: 0 +fetch_stall_cycles: 0 +mem_stall_cycles: 0 +stall_warp: 0 +wspawn: 0 +stalled: 0 +********************************** Fetch ********************************* +valid: 1 +PC: 80000b58 +wid: 0 +rd: 0 rs1: 1 rs2: -1 +is_lw: 0 +is_sw: 0 +fetch_stall_cycles: 0 +mem_stall_cycles: 0 +stall_warp: 1 +wspawn: 0 +stalled: 0 + + + +------------------------------------------------------ +CYCLE: 265 +Stalled Warps: +1 0 0 0 0 0 0 0 + +********************************** Writeback ********************************* +valid: 0 +PC: 0 +wid: 1 +rd: -1 rs1: -1 rs2: -1 +is_lw: 0 +is_sw: 0 +fetch_stall_cycles: 0 +mem_stall_cycles: 0 +stall_warp: 0 +wspawn: 0 +stalled: 0 +********************************** LSU ********************************* +valid: 1 +PC: 80000b50 +wid: 0 +rd: -1 rs1: 15 rs2: 11 +is_lw: 0 +is_sw: 1 +fetch_stall_cycles: 0 +mem_stall_cycles: 0 +stall_warp: 0 +wspawn: 0 +stalled: 0 +********************************** execute_unit ********************************* +valid: 0 +PC: 0 +wid: 1 +rd: -1 rs1: -1 rs2: -1 +is_lw: 0 +is_sw: 0 +fetch_stall_cycles: 0 +mem_stall_cycles: 0 +stall_warp: 0 +wspawn: 0 +stalled: 0 +********************************** scheduler ********************************* +valid: 1 +PC: 80000b54 +wid: 0 +rd: 10 rs1: 0 rs2: -1 +is_lw: 0 +is_sw: 0 +fetch_stall_cycles: 0 +mem_stall_cycles: 0 +stall_warp: 0 +wspawn: 0 +stalled: 0 +********************************** Decode ********************************* +valid: 1 +PC: 80000b58 +wid: 0 +rd: 0 rs1: 1 rs2: -1 +is_lw: 0 +is_sw: 0 +fetch_stall_cycles: 0 +mem_stall_cycles: 0 +stall_warp: 1 +wspawn: 0 +stalled: 0 +********************************** Fetch ********************************* +valid: 0 +PC: 0 +wid: 1 +rd: -1 rs1: -1 rs2: -1 +is_lw: 0 +is_sw: 0 +fetch_stall_cycles: 0 +mem_stall_cycles: 0 +stall_warp: 0 +wspawn: 0 +stalled: 0 + + + +------------------------------------------------------ +CYCLE: 266 +Stalled Warps: +1 0 0 0 0 0 0 0 + +********************************** Writeback ********************************* +valid: 0 +PC: 0 +wid: 2 +rd: -1 rs1: -1 rs2: -1 +is_lw: 0 +is_sw: 0 +fetch_stall_cycles: 0 +mem_stall_cycles: 0 +stall_warp: 0 +wspawn: 0 +stalled: 0 +********************************** LSU ********************************* +valid: 0 +PC: 0 +wid: 2 +rd: -1 rs1: -1 rs2: -1 +is_lw: 0 +is_sw: 0 +fetch_stall_cycles: 0 +mem_stall_cycles: 0 +stall_warp: 0 +wspawn: 0 +stalled: 0 +********************************** execute_unit ********************************* +valid: 1 +PC: 80000b54 +wid: 0 +rd: 10 rs1: 0 rs2: -1 +is_lw: 0 +is_sw: 0 +fetch_stall_cycles: 0 +mem_stall_cycles: 0 +stall_warp: 0 +wspawn: 0 +stalled: 0 +********************************** scheduler ********************************* +valid: 1 +PC: 80000b58 +wid: 0 +rd: 0 rs1: 1 rs2: -1 +is_lw: 0 +is_sw: 0 +fetch_stall_cycles: 0 +mem_stall_cycles: 0 +stall_warp: 1 +wspawn: 0 +stalled: 0 +********************************** Decode ********************************* +valid: 0 +PC: 0 +wid: 1 +rd: -1 rs1: -1 rs2: -1 +is_lw: 0 +is_sw: 0 +fetch_stall_cycles: 0 +mem_stall_cycles: 0 +stall_warp: 0 +wspawn: 0 +stalled: 0 +********************************** Fetch ********************************* +valid: 0 +PC: 0 +wid: 2 +rd: -1 rs1: -1 rs2: -1 +is_lw: 0 +is_sw: 0 +fetch_stall_cycles: 0 +mem_stall_cycles: 0 +stall_warp: 0 +wspawn: 0 +stalled: 0 + + + +------------------------------------------------------ +CYCLE: 267 +Stalled Warps: +1 0 0 0 0 0 0 0 + +********************************** Writeback ********************************* +valid: 1 +PC: 80000b54 +wid: 0 +rd: 10 rs1: 0 rs2: -1 +is_lw: 0 +is_sw: 0 +fetch_stall_cycles: 0 +mem_stall_cycles: 0 +stall_warp: 0 +wspawn: 0 +stalled: 0 +********************************** LSU ********************************* +valid: 0 +PC: 0 +wid: 2 +rd: -1 rs1: -1 rs2: -1 +is_lw: 0 +is_sw: 0 +fetch_stall_cycles: 0 +mem_stall_cycles: 0 +stall_warp: 0 +wspawn: 0 +stalled: 0 +********************************** execute_unit ********************************* +valid: 1 +PC: 80000b58 +wid: 0 +rd: 0 rs1: 1 rs2: -1 +is_lw: 0 +is_sw: 0 +fetch_stall_cycles: 0 +mem_stall_cycles: 0 +stall_warp: 1 +wspawn: 0 +stalled: 0 +********************************** scheduler ********************************* +valid: 0 +PC: 0 +wid: 1 +rd: -1 rs1: -1 rs2: -1 +is_lw: 0 +is_sw: 0 +fetch_stall_cycles: 0 +mem_stall_cycles: 0 +stall_warp: 0 +wspawn: 0 +stalled: 0 +********************************** Decode ********************************* +valid: 0 +PC: 0 +wid: 2 +rd: -1 rs1: -1 rs2: -1 +is_lw: 0 +is_sw: 0 +fetch_stall_cycles: 0 +mem_stall_cycles: 0 +stall_warp: 0 +wspawn: 0 +stalled: 0 +********************************** Fetch ********************************* +valid: 0 +PC: 0 +wid: 3 +rd: -1 rs1: -1 rs2: -1 +is_lw: 0 +is_sw: 0 +fetch_stall_cycles: 0 +mem_stall_cycles: 0 +stall_warp: 0 +wspawn: 0 +stalled: 0 + + + +------------------------------------------------------ +CYCLE: 268 +Stalled Warps: +1 0 0 0 0 0 0 0 + +********************************** Writeback ********************************* +valid: 1 +PC: 80000b58 +wid: 0 +rd: 0 rs1: 1 rs2: -1 +is_lw: 0 +is_sw: 0 +fetch_stall_cycles: 0 +mem_stall_cycles: 0 +stall_warp: 1 +wspawn: 0 +stalled: 0 +********************************** LSU ********************************* +valid: 0 +PC: 0 +wid: 2 +rd: -1 rs1: -1 rs2: -1 +is_lw: 0 +is_sw: 0 +fetch_stall_cycles: 0 +mem_stall_cycles: 0 +stall_warp: 0 +wspawn: 0 +stalled: 0 +********************************** execute_unit ********************************* +valid: 0 +PC: 0 +wid: 1 +rd: -1 rs1: -1 rs2: -1 +is_lw: 0 +is_sw: 0 +fetch_stall_cycles: 0 +mem_stall_cycles: 0 +stall_warp: 0 +wspawn: 0 +stalled: 0 +********************************** scheduler ********************************* +valid: 0 +PC: 0 +wid: 2 +rd: -1 rs1: -1 rs2: -1 +is_lw: 0 +is_sw: 0 +fetch_stall_cycles: 0 +mem_stall_cycles: 0 +stall_warp: 0 +wspawn: 0 +stalled: 0 +********************************** Decode ********************************* +valid: 0 +PC: 0 +wid: 3 +rd: -1 rs1: -1 rs2: -1 +is_lw: 0 +is_sw: 0 +fetch_stall_cycles: 0 +mem_stall_cycles: 0 +stall_warp: 0 +wspawn: 0 +stalled: 0 +********************************** Fetch ********************************* +valid: 0 +PC: 0 +wid: 4 +rd: -1 rs1: -1 rs2: -1 +is_lw: 0 +is_sw: 0 +fetch_stall_cycles: 0 +mem_stall_cycles: 0 +stall_warp: 0 +wspawn: 0 +stalled: 0 + + + +------------------------------------------------------ +CYCLE: 269 +Stalled Warps: +1 0 0 0 0 0 0 0 + +********************************** Writeback ********************************* +valid: 0 +PC: 0 +wid: 5 +rd: -1 rs1: -1 rs2: -1 +is_lw: 0 +is_sw: 0 +fetch_stall_cycles: 0 +mem_stall_cycles: 0 +stall_warp: 0 +wspawn: 0 +stalled: 0 +********************************** LSU ********************************* +valid: 0 +PC: 0 +wid: 2 +rd: -1 rs1: -1 rs2: -1 +is_lw: 0 +is_sw: 0 +fetch_stall_cycles: 0 +mem_stall_cycles: 0 +stall_warp: 0 +wspawn: 0 +stalled: 0 +********************************** execute_unit ********************************* +valid: 0 +PC: 0 +wid: 2 +rd: -1 rs1: -1 rs2: -1 +is_lw: 0 +is_sw: 0 +fetch_stall_cycles: 0 +mem_stall_cycles: 0 +stall_warp: 0 +wspawn: 0 +stalled: 0 +********************************** scheduler ********************************* +valid: 0 +PC: 0 +wid: 3 +rd: -1 rs1: -1 rs2: -1 +is_lw: 0 +is_sw: 0 +fetch_stall_cycles: 0 +mem_stall_cycles: 0 +stall_warp: 0 +wspawn: 0 +stalled: 0 +********************************** Decode ********************************* +valid: 0 +PC: 0 +wid: 4 +rd: -1 rs1: -1 rs2: -1 +is_lw: 0 +is_sw: 0 +fetch_stall_cycles: 0 +mem_stall_cycles: 0 +stall_warp: 0 +wspawn: 0 +stalled: 0 +********************************** Fetch ********************************* +valid: 0 +PC: 0 +wid: 5 +rd: -1 rs1: -1 rs2: -1 +is_lw: 0 +is_sw: 0 +fetch_stall_cycles: 0 +mem_stall_cycles: 0 +stall_warp: 0 +wspawn: 0 +stalled: 0 +Warp ID 0 is running + + + +------------------------------------------------------ +CYCLE: 270 +Stalled Warps: +0 0 0 0 0 0 0 0 + +********************************** Writeback ********************************* +valid: 0 +PC: 0 +wid: 0 +rd: -1 rs1: -1 rs2: -1 +is_lw: 0 +is_sw: 0 +fetch_stall_cycles: 0 +mem_stall_cycles: 0 +stall_warp: 0 +wspawn: 0 +stalled: 0 +********************************** LSU ********************************* +valid: 0 +PC: 0 +wid: 2 +rd: -1 rs1: -1 rs2: -1 +is_lw: 0 +is_sw: 0 +fetch_stall_cycles: 0 +mem_stall_cycles: 0 +stall_warp: 0 +wspawn: 0 +stalled: 0 +********************************** execute_unit ********************************* +valid: 0 +PC: 0 +wid: 3 +rd: -1 rs1: -1 rs2: -1 +is_lw: 0 +is_sw: 0 +fetch_stall_cycles: 0 +mem_stall_cycles: 0 +stall_warp: 0 +wspawn: 0 +stalled: 0 +********************************** scheduler ********************************* +valid: 0 +PC: 0 +wid: 4 +rd: -1 rs1: -1 rs2: -1 +is_lw: 0 +is_sw: 0 +fetch_stall_cycles: 0 +mem_stall_cycles: 0 +stall_warp: 0 +wspawn: 0 +stalled: 0 +********************************** Decode ********************************* +valid: 0 +PC: 0 +wid: 5 +rd: -1 rs1: -1 rs2: -1 +is_lw: 0 +is_sw: 0 +fetch_stall_cycles: 0 +mem_stall_cycles: 0 +stall_warp: 0 +wspawn: 0 +stalled: 0 +DEBUG ../core.cpp:386: Core step stepping warp 0[1] +DEBUG ../core.cpp:683: in step pc=0x8000003c +help: in PC: 8000003c +CUrrent CODE: 149000ef +DEBUG ../core.cpp:703: Fetched at 0x8000003c +DEBUG ../core.cpp:704: 0x8000003c: jal; +DEBUG ../instruction.cpp:350: Begin instruction execute. +DEBUG ../instruction.cpp:2117: End instruction execute. +Next PC: 80000984 +DEBUG ../core.cpp:717: Register state: + %r 0: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r 1: 80000040 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r 2: 6ffff000 6fffec04 6fffe808 6fffe40c 00000000 00000000 00000000 00000000 (0) + %r 3: 80001808 80001808 80001808 80001808 00000000 00000000 00000000 00000000 (0) + %r 4: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r 5: 80000a6c 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r 6: 0000000f 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r 7: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r 8: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r 9: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r10: 00000000 00000001 00000001 00000001 00000000 00000000 00000000 00000000 (0) + %r11: 80000924 00000400 00000800 00000c00 00000000 00000000 00000000 00000000 (0) + %r12: 00000000 00000004 00000008 0000000c 00000000 00000000 00000000 00000000 (0) + %r13: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r14: 00000001 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r15: 80001154 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r16: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r17: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r18: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r19: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r20: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r21: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r22: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r23: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r24: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r25: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r26: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r27: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r28: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r29: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r30: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r31: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) +DEBUG ../core.cpp:726: Thread mask: + 1 0 0 0 0 0 0 0 + + +DEBUG ../core.cpp:388: Now 1 active threads in 0 +********************************** Fetch ********************************* +valid: 1 +PC: 8000003c +wid: 0 +rd: 1 rs1: -1 rs2: -1 +is_lw: 0 +is_sw: 0 +fetch_stall_cycles: 0 +mem_stall_cycles: 0 +stall_warp: 1 +wspawn: 0 +stalled: 0 + + + +------------------------------------------------------ +CYCLE: 271 +Stalled Warps: +1 0 0 0 0 0 0 0 + +********************************** Writeback ********************************* +valid: 0 +PC: 0 +wid: 1 +rd: -1 rs1: -1 rs2: -1 +is_lw: 0 +is_sw: 0 +fetch_stall_cycles: 0 +mem_stall_cycles: 0 +stall_warp: 0 +wspawn: 0 +stalled: 0 +********************************** LSU ********************************* +valid: 0 +PC: 0 +wid: 2 +rd: -1 rs1: -1 rs2: -1 +is_lw: 0 +is_sw: 0 +fetch_stall_cycles: 0 +mem_stall_cycles: 0 +stall_warp: 0 +wspawn: 0 +stalled: 0 +********************************** execute_unit ********************************* +valid: 0 +PC: 0 +wid: 4 +rd: -1 rs1: -1 rs2: -1 +is_lw: 0 +is_sw: 0 +fetch_stall_cycles: 0 +mem_stall_cycles: 0 +stall_warp: 0 +wspawn: 0 +stalled: 0 +********************************** scheduler ********************************* +valid: 0 +PC: 0 +wid: 5 +rd: -1 rs1: -1 rs2: -1 +is_lw: 0 +is_sw: 0 +fetch_stall_cycles: 0 +mem_stall_cycles: 0 +stall_warp: 0 +wspawn: 0 +stalled: 0 +********************************** Decode ********************************* +valid: 1 +PC: 8000003c +wid: 0 +rd: 1 rs1: -1 rs2: -1 +is_lw: 0 +is_sw: 0 +fetch_stall_cycles: 0 +mem_stall_cycles: 0 +stall_warp: 1 +wspawn: 0 +stalled: 0 +********************************** Fetch ********************************* +valid: 0 +PC: 0 +wid: 1 +rd: -1 rs1: -1 rs2: -1 +is_lw: 0 +is_sw: 0 +fetch_stall_cycles: 0 +mem_stall_cycles: 0 +stall_warp: 0 +wspawn: 0 +stalled: 0 + + + +------------------------------------------------------ +CYCLE: 272 +Stalled Warps: +1 0 0 0 0 0 0 0 + +********************************** Writeback ********************************* +valid: 0 +PC: 0 +wid: 2 +rd: -1 rs1: -1 rs2: -1 +is_lw: 0 +is_sw: 0 +fetch_stall_cycles: 0 +mem_stall_cycles: 0 +stall_warp: 0 +wspawn: 0 +stalled: 0 +********************************** LSU ********************************* +valid: 0 +PC: 0 +wid: 2 +rd: -1 rs1: -1 rs2: -1 +is_lw: 0 +is_sw: 0 +fetch_stall_cycles: 0 +mem_stall_cycles: 0 +stall_warp: 0 +wspawn: 0 +stalled: 0 +********************************** execute_unit ********************************* +valid: 0 +PC: 0 +wid: 5 +rd: -1 rs1: -1 rs2: -1 +is_lw: 0 +is_sw: 0 +fetch_stall_cycles: 0 +mem_stall_cycles: 0 +stall_warp: 0 +wspawn: 0 +stalled: 0 +********************************** scheduler ********************************* +valid: 1 +PC: 8000003c +wid: 0 +rd: 1 rs1: -1 rs2: -1 +is_lw: 0 +is_sw: 0 +fetch_stall_cycles: 0 +mem_stall_cycles: 0 +stall_warp: 1 +wspawn: 0 +stalled: 0 +********************************** Decode ********************************* +valid: 0 +PC: 0 +wid: 1 +rd: -1 rs1: -1 rs2: -1 +is_lw: 0 +is_sw: 0 +fetch_stall_cycles: 0 +mem_stall_cycles: 0 +stall_warp: 0 +wspawn: 0 +stalled: 0 +********************************** Fetch ********************************* +valid: 0 +PC: 0 +wid: 2 +rd: -1 rs1: -1 rs2: -1 +is_lw: 0 +is_sw: 0 +fetch_stall_cycles: 0 +mem_stall_cycles: 0 +stall_warp: 0 +wspawn: 0 +stalled: 0 + + + +------------------------------------------------------ +CYCLE: 273 +Stalled Warps: +1 0 0 0 0 0 0 0 + +********************************** Writeback ********************************* +valid: 0 +PC: 0 +wid: 3 +rd: -1 rs1: -1 rs2: -1 +is_lw: 0 +is_sw: 0 +fetch_stall_cycles: 0 +mem_stall_cycles: 0 +stall_warp: 0 +wspawn: 0 +stalled: 0 +********************************** LSU ********************************* +valid: 0 +PC: 0 +wid: 2 +rd: -1 rs1: -1 rs2: -1 +is_lw: 0 +is_sw: 0 +fetch_stall_cycles: 0 +mem_stall_cycles: 0 +stall_warp: 0 +wspawn: 0 +stalled: 0 +********************************** execute_unit ********************************* +valid: 1 +PC: 8000003c +wid: 0 +rd: 1 rs1: -1 rs2: -1 +is_lw: 0 +is_sw: 0 +fetch_stall_cycles: 0 +mem_stall_cycles: 0 +stall_warp: 1 +wspawn: 0 +stalled: 0 +********************************** scheduler ********************************* +valid: 0 +PC: 0 +wid: 1 +rd: -1 rs1: -1 rs2: -1 +is_lw: 0 +is_sw: 0 +fetch_stall_cycles: 0 +mem_stall_cycles: 0 +stall_warp: 0 +wspawn: 0 +stalled: 0 +********************************** Decode ********************************* +valid: 0 +PC: 0 +wid: 2 +rd: -1 rs1: -1 rs2: -1 +is_lw: 0 +is_sw: 0 +fetch_stall_cycles: 0 +mem_stall_cycles: 0 +stall_warp: 0 +wspawn: 0 +stalled: 0 +********************************** Fetch ********************************* +valid: 0 +PC: 0 +wid: 3 +rd: -1 rs1: -1 rs2: -1 +is_lw: 0 +is_sw: 0 +fetch_stall_cycles: 0 +mem_stall_cycles: 0 +stall_warp: 0 +wspawn: 0 +stalled: 0 + + + +------------------------------------------------------ +CYCLE: 274 +Stalled Warps: +1 0 0 0 0 0 0 0 + +********************************** Writeback ********************************* +valid: 1 +PC: 8000003c +wid: 0 +rd: 1 rs1: -1 rs2: -1 +is_lw: 0 +is_sw: 0 +fetch_stall_cycles: 0 +mem_stall_cycles: 0 +stall_warp: 1 +wspawn: 0 +stalled: 0 +********************************** LSU ********************************* +valid: 0 +PC: 0 +wid: 2 +rd: -1 rs1: -1 rs2: -1 +is_lw: 0 +is_sw: 0 +fetch_stall_cycles: 0 +mem_stall_cycles: 0 +stall_warp: 0 +wspawn: 0 +stalled: 0 +********************************** execute_unit ********************************* +valid: 0 +PC: 0 +wid: 1 +rd: -1 rs1: -1 rs2: -1 +is_lw: 0 +is_sw: 0 +fetch_stall_cycles: 0 +mem_stall_cycles: 0 +stall_warp: 0 +wspawn: 0 +stalled: 0 +********************************** scheduler ********************************* +valid: 0 +PC: 0 +wid: 2 +rd: -1 rs1: -1 rs2: -1 +is_lw: 0 +is_sw: 0 +fetch_stall_cycles: 0 +mem_stall_cycles: 0 +stall_warp: 0 +wspawn: 0 +stalled: 0 +********************************** Decode ********************************* +valid: 0 +PC: 0 +wid: 3 +rd: -1 rs1: -1 rs2: -1 +is_lw: 0 +is_sw: 0 +fetch_stall_cycles: 0 +mem_stall_cycles: 0 +stall_warp: 0 +wspawn: 0 +stalled: 0 +********************************** Fetch ********************************* +valid: 0 +PC: 0 +wid: 4 +rd: -1 rs1: -1 rs2: -1 +is_lw: 0 +is_sw: 0 +fetch_stall_cycles: 0 +mem_stall_cycles: 0 +stall_warp: 0 +wspawn: 0 +stalled: 0 + + + +------------------------------------------------------ +CYCLE: 275 +Stalled Warps: +1 0 0 0 0 0 0 0 + +********************************** Writeback ********************************* +valid: 0 +PC: 0 +wid: 5 +rd: -1 rs1: -1 rs2: -1 +is_lw: 0 +is_sw: 0 +fetch_stall_cycles: 0 +mem_stall_cycles: 0 +stall_warp: 0 +wspawn: 0 +stalled: 0 +********************************** LSU ********************************* +valid: 0 +PC: 0 +wid: 2 +rd: -1 rs1: -1 rs2: -1 +is_lw: 0 +is_sw: 0 +fetch_stall_cycles: 0 +mem_stall_cycles: 0 +stall_warp: 0 +wspawn: 0 +stalled: 0 +********************************** execute_unit ********************************* +valid: 0 +PC: 0 +wid: 2 +rd: -1 rs1: -1 rs2: -1 +is_lw: 0 +is_sw: 0 +fetch_stall_cycles: 0 +mem_stall_cycles: 0 +stall_warp: 0 +wspawn: 0 +stalled: 0 +********************************** scheduler ********************************* +valid: 0 +PC: 0 +wid: 3 +rd: -1 rs1: -1 rs2: -1 +is_lw: 0 +is_sw: 0 +fetch_stall_cycles: 0 +mem_stall_cycles: 0 +stall_warp: 0 +wspawn: 0 +stalled: 0 +********************************** Decode ********************************* +valid: 0 +PC: 0 +wid: 4 +rd: -1 rs1: -1 rs2: -1 +is_lw: 0 +is_sw: 0 +fetch_stall_cycles: 0 +mem_stall_cycles: 0 +stall_warp: 0 +wspawn: 0 +stalled: 0 +********************************** Fetch ********************************* +valid: 0 +PC: 0 +wid: 5 +rd: -1 rs1: -1 rs2: -1 +is_lw: 0 +is_sw: 0 +fetch_stall_cycles: 0 +mem_stall_cycles: 0 +stall_warp: 0 +wspawn: 0 +stalled: 0 +Warp ID 0 is running + + + +------------------------------------------------------ +CYCLE: 276 +Stalled Warps: +0 0 0 0 0 0 0 0 + +********************************** Writeback ********************************* +valid: 0 +PC: 0 +wid: 0 +rd: -1 rs1: -1 rs2: -1 +is_lw: 0 +is_sw: 0 +fetch_stall_cycles: 0 +mem_stall_cycles: 0 +stall_warp: 0 +wspawn: 0 +stalled: 0 +********************************** LSU ********************************* +valid: 0 +PC: 0 +wid: 2 +rd: -1 rs1: -1 rs2: -1 +is_lw: 0 +is_sw: 0 +fetch_stall_cycles: 0 +mem_stall_cycles: 0 +stall_warp: 0 +wspawn: 0 +stalled: 0 +********************************** execute_unit ********************************* +valid: 0 +PC: 0 +wid: 3 +rd: -1 rs1: -1 rs2: -1 +is_lw: 0 +is_sw: 0 +fetch_stall_cycles: 0 +mem_stall_cycles: 0 +stall_warp: 0 +wspawn: 0 +stalled: 0 +********************************** scheduler ********************************* +valid: 0 +PC: 0 +wid: 4 +rd: -1 rs1: -1 rs2: -1 +is_lw: 0 +is_sw: 0 +fetch_stall_cycles: 0 +mem_stall_cycles: 0 +stall_warp: 0 +wspawn: 0 +stalled: 0 +********************************** Decode ********************************* +valid: 0 +PC: 0 +wid: 5 +rd: -1 rs1: -1 rs2: -1 +is_lw: 0 +is_sw: 0 +fetch_stall_cycles: 0 +mem_stall_cycles: 0 +stall_warp: 0 +wspawn: 0 +stalled: 0 +DEBUG ../core.cpp:386: Core step stepping warp 0[1] +DEBUG ../core.cpp:683: in step pc=0x80000984 +help: in PC: 80000984 +CUrrent CODE: ff010113 +DEBUG ../core.cpp:703: Fetched at 0x80000984 +DEBUG ../core.cpp:704: 0x80000984: i_type; +DEBUG ../instruction.cpp:350: Begin instruction execute. +DEBUG ../instruction.cpp:2117: End instruction execute. +DEBUG ../core.cpp:717: Register state: + %r 0: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r 1: 80000040 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r 2: 6fffeff0 6fffec04 6fffe808 6fffe40c 00000000 00000000 00000000 00000000 (0) + %r 3: 80001808 80001808 80001808 80001808 00000000 00000000 00000000 00000000 (0) + %r 4: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r 5: 80000a6c 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r 6: 0000000f 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r 7: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r 8: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r 9: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r10: 00000000 00000001 00000001 00000001 00000000 00000000 00000000 00000000 (0) + %r11: 80000924 00000400 00000800 00000c00 00000000 00000000 00000000 00000000 (0) + %r12: 00000000 00000004 00000008 0000000c 00000000 00000000 00000000 00000000 (0) + %r13: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r14: 00000001 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r15: 80001154 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r16: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r17: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r18: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r19: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r20: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r21: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r22: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r23: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r24: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r25: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r26: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r27: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r28: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r29: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r30: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r31: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) +DEBUG ../core.cpp:726: Thread mask: + 1 0 0 0 0 0 0 0 + + +DEBUG ../core.cpp:388: Now 1 active threads in 0 +********************************** Fetch ********************************* +valid: 1 +PC: 80000984 +wid: 0 +rd: 2 rs1: 2 rs2: -1 +is_lw: 0 +is_sw: 0 +fetch_stall_cycles: 3 +mem_stall_cycles: 0 +stall_warp: 0 +wspawn: 0 +stalled: 0 + + + +------------------------------------------------------ +CYCLE: 277 +Stalled Warps: +0 0 0 0 0 0 0 0 + +********************************** Writeback ********************************* +valid: 0 +PC: 0 +wid: 0 +rd: -1 rs1: -1 rs2: -1 +is_lw: 0 +is_sw: 0 +fetch_stall_cycles: 0 +mem_stall_cycles: 0 +stall_warp: 0 +wspawn: 0 +stalled: 0 +********************************** LSU ********************************* +valid: 0 +PC: 0 +wid: 2 +rd: -1 rs1: -1 rs2: -1 +is_lw: 0 +is_sw: 0 +fetch_stall_cycles: 0 +mem_stall_cycles: 0 +stall_warp: 0 +wspawn: 0 +stalled: 0 +********************************** execute_unit ********************************* +valid: 0 +PC: 0 +wid: 4 +rd: -1 rs1: -1 rs2: -1 +is_lw: 0 +is_sw: 0 +fetch_stall_cycles: 0 +mem_stall_cycles: 0 +stall_warp: 0 +wspawn: 0 +stalled: 0 +********************************** scheduler ********************************* +valid: 0 +PC: 0 +wid: 5 +rd: -1 rs1: -1 rs2: -1 +is_lw: 0 +is_sw: 0 +fetch_stall_cycles: 0 +mem_stall_cycles: 0 +stall_warp: 0 +wspawn: 0 +stalled: 0 +********************************** Decode ********************************* +valid: 0 +PC: 0 +wid: 0 +rd: -1 rs1: -1 rs2: -1 +is_lw: 0 +is_sw: 0 +fetch_stall_cycles: 0 +mem_stall_cycles: 0 +stall_warp: 0 +wspawn: 0 +stalled: 0 +********************************** Fetch ********************************* +valid: 1 +PC: 80000984 +wid: 0 +rd: 2 rs1: 2 rs2: -1 +is_lw: 0 +is_sw: 0 +fetch_stall_cycles: 2 +mem_stall_cycles: 0 +stall_warp: 0 +wspawn: 0 +stalled: 0 + + + +------------------------------------------------------ +CYCLE: 278 +Stalled Warps: +0 0 0 0 0 0 0 0 + +********************************** Writeback ********************************* +valid: 0 +PC: 0 +wid: 0 +rd: -1 rs1: -1 rs2: -1 +is_lw: 0 +is_sw: 0 +fetch_stall_cycles: 0 +mem_stall_cycles: 0 +stall_warp: 0 +wspawn: 0 +stalled: 0 +********************************** LSU ********************************* +valid: 0 +PC: 0 +wid: 2 +rd: -1 rs1: -1 rs2: -1 +is_lw: 0 +is_sw: 0 +fetch_stall_cycles: 0 +mem_stall_cycles: 0 +stall_warp: 0 +wspawn: 0 +stalled: 0 +********************************** execute_unit ********************************* +valid: 0 +PC: 0 +wid: 5 +rd: -1 rs1: -1 rs2: -1 +is_lw: 0 +is_sw: 0 +fetch_stall_cycles: 0 +mem_stall_cycles: 0 +stall_warp: 0 +wspawn: 0 +stalled: 0 +********************************** scheduler ********************************* +valid: 0 +PC: 0 +wid: 0 +rd: -1 rs1: -1 rs2: -1 +is_lw: 0 +is_sw: 0 +fetch_stall_cycles: 0 +mem_stall_cycles: 0 +stall_warp: 0 +wspawn: 0 +stalled: 0 +********************************** Decode ********************************* +valid: 0 +PC: 0 +wid: 0 +rd: -1 rs1: -1 rs2: -1 +is_lw: 0 +is_sw: 0 +fetch_stall_cycles: 0 +mem_stall_cycles: 0 +stall_warp: 0 +wspawn: 0 +stalled: 0 +********************************** Fetch ********************************* +valid: 1 +PC: 80000984 +wid: 0 +rd: 2 rs1: 2 rs2: -1 +is_lw: 0 +is_sw: 0 +fetch_stall_cycles: 1 +mem_stall_cycles: 0 +stall_warp: 0 +wspawn: 0 +stalled: 0 + + + +------------------------------------------------------ +CYCLE: 279 +Stalled Warps: +0 0 0 0 0 0 0 0 + +********************************** Writeback ********************************* +valid: 0 +PC: 0 +wid: 0 +rd: -1 rs1: -1 rs2: -1 +is_lw: 0 +is_sw: 0 +fetch_stall_cycles: 0 +mem_stall_cycles: 0 +stall_warp: 0 +wspawn: 0 +stalled: 0 +********************************** LSU ********************************* +valid: 0 +PC: 0 +wid: 2 +rd: -1 rs1: -1 rs2: -1 +is_lw: 0 +is_sw: 0 +fetch_stall_cycles: 0 +mem_stall_cycles: 0 +stall_warp: 0 +wspawn: 0 +stalled: 0 +********************************** execute_unit ********************************* +valid: 0 +PC: 0 +wid: 0 +rd: -1 rs1: -1 rs2: -1 +is_lw: 0 +is_sw: 0 +fetch_stall_cycles: 0 +mem_stall_cycles: 0 +stall_warp: 0 +wspawn: 0 +stalled: 0 +********************************** scheduler ********************************* +valid: 0 +PC: 0 +wid: 0 +rd: -1 rs1: -1 rs2: -1 +is_lw: 0 +is_sw: 0 +fetch_stall_cycles: 0 +mem_stall_cycles: 0 +stall_warp: 0 +wspawn: 0 +stalled: 0 +********************************** Decode ********************************* +valid: 0 +PC: 0 +wid: 0 +rd: -1 rs1: -1 rs2: -1 +is_lw: 0 +is_sw: 0 +fetch_stall_cycles: 0 +mem_stall_cycles: 0 +stall_warp: 0 +wspawn: 0 +stalled: 0 +********************************** Fetch ********************************* +valid: 1 +PC: 80000984 +wid: 0 +rd: 2 rs1: 2 rs2: -1 +is_lw: 0 +is_sw: 0 +fetch_stall_cycles: 0 +mem_stall_cycles: 0 +stall_warp: 0 +wspawn: 0 +stalled: 0 + + + +------------------------------------------------------ +CYCLE: 280 +Stalled Warps: +0 0 0 0 0 0 0 0 + +********************************** Writeback ********************************* +valid: 0 +PC: 0 +wid: 0 +rd: -1 rs1: -1 rs2: -1 +is_lw: 0 +is_sw: 0 +fetch_stall_cycles: 0 +mem_stall_cycles: 0 +stall_warp: 0 +wspawn: 0 +stalled: 0 +********************************** LSU ********************************* +valid: 0 +PC: 0 +wid: 2 +rd: -1 rs1: -1 rs2: -1 +is_lw: 0 +is_sw: 0 +fetch_stall_cycles: 0 +mem_stall_cycles: 0 +stall_warp: 0 +wspawn: 0 +stalled: 0 +********************************** execute_unit ********************************* +valid: 0 +PC: 0 +wid: 0 +rd: -1 rs1: -1 rs2: -1 +is_lw: 0 +is_sw: 0 +fetch_stall_cycles: 0 +mem_stall_cycles: 0 +stall_warp: 0 +wspawn: 0 +stalled: 0 +********************************** scheduler ********************************* +valid: 0 +PC: 0 +wid: 0 +rd: -1 rs1: -1 rs2: -1 +is_lw: 0 +is_sw: 0 +fetch_stall_cycles: 0 +mem_stall_cycles: 0 +stall_warp: 0 +wspawn: 0 +stalled: 0 +********************************** Decode ********************************* +valid: 1 +PC: 80000984 +wid: 0 +rd: 2 rs1: 2 rs2: -1 +is_lw: 0 +is_sw: 0 +fetch_stall_cycles: 0 +mem_stall_cycles: 0 +stall_warp: 0 +wspawn: 0 +stalled: 0 +DEBUG ../core.cpp:386: Core step stepping warp 0[1] +DEBUG ../core.cpp:683: in step pc=0x80000988 +help: in PC: 80000988 +CUrrent CODE: 812423 +DEBUG ../core.cpp:703: Fetched at 0x80000988 +DEBUG ../core.cpp:704: 0x80000988: store; +DEBUG ../instruction.cpp:350: Begin instruction execute. +STORE MEM ADDRESS: 6fffeff0 + 8 +DEBUG ../instruction.cpp:2117: End instruction execute. +DEBUG ../core.cpp:717: Register state: + %r 0: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r 1: 80000040 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r 2: 6fffeff0 6fffec04 6fffe808 6fffe40c 00000000 00000000 00000000 00000000 (0) + %r 3: 80001808 80001808 80001808 80001808 00000000 00000000 00000000 00000000 (0) + %r 4: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r 5: 80000a6c 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r 6: 0000000f 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r 7: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r 8: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r 9: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r10: 00000000 00000001 00000001 00000001 00000000 00000000 00000000 00000000 (0) + %r11: 80000924 00000400 00000800 00000c00 00000000 00000000 00000000 00000000 (0) + %r12: 00000000 00000004 00000008 0000000c 00000000 00000000 00000000 00000000 (0) + %r13: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r14: 00000001 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r15: 80001154 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r16: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r17: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r18: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r19: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r20: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r21: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r22: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r23: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r24: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r25: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r26: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r27: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r28: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r29: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r30: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r31: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) +DEBUG ../core.cpp:726: Thread mask: + 1 0 0 0 0 0 0 0 + + +DEBUG ../core.cpp:388: Now 1 active threads in 0 +********************************** Fetch ********************************* +valid: 1 +PC: 80000988 +wid: 0 +rd: -1 rs1: 2 rs2: 8 +is_lw: 0 +is_sw: 1 +fetch_stall_cycles: 0 +mem_stall_cycles: 3 +stall_warp: 0 +wspawn: 0 +stalled: 0 + + + +------------------------------------------------------ +CYCLE: 281 +Stalled Warps: +0 0 0 0 0 0 0 0 + +********************************** Writeback ********************************* +valid: 0 +PC: 0 +wid: 0 +rd: -1 rs1: -1 rs2: -1 +is_lw: 0 +is_sw: 0 +fetch_stall_cycles: 0 +mem_stall_cycles: 0 +stall_warp: 0 +wspawn: 0 +stalled: 0 +********************************** LSU ********************************* +valid: 0 +PC: 0 +wid: 2 +rd: -1 rs1: -1 rs2: -1 +is_lw: 0 +is_sw: 0 +fetch_stall_cycles: 0 +mem_stall_cycles: 0 +stall_warp: 0 +wspawn: 0 +stalled: 0 +********************************** execute_unit ********************************* +valid: 0 +PC: 0 +wid: 0 +rd: -1 rs1: -1 rs2: -1 +is_lw: 0 +is_sw: 0 +fetch_stall_cycles: 0 +mem_stall_cycles: 0 +stall_warp: 0 +wspawn: 0 +stalled: 0 +********************************** scheduler ********************************* +valid: 1 +PC: 80000984 +wid: 0 +rd: 2 rs1: 2 rs2: -1 +is_lw: 0 +is_sw: 0 +fetch_stall_cycles: 0 +mem_stall_cycles: 0 +stall_warp: 0 +wspawn: 0 +stalled: 0 +********************************** Decode ********************************* +valid: 1 +PC: 80000988 +wid: 0 +rd: -1 rs1: 2 rs2: 8 +is_lw: 0 +is_sw: 1 +fetch_stall_cycles: 0 +mem_stall_cycles: 3 +stall_warp: 0 +wspawn: 0 +stalled: 0 +DEBUG ../core.cpp:386: Core step stepping warp 0[1] +DEBUG ../core.cpp:683: in step pc=0x8000098c +help: in PC: 8000098c +CUrrent CODE: 1212023 +DEBUG ../core.cpp:703: Fetched at 0x8000098c +DEBUG ../core.cpp:704: 0x8000098c: store; +DEBUG ../instruction.cpp:350: Begin instruction execute. +STORE MEM ADDRESS: 6fffeff0 + 0 +DEBUG ../instruction.cpp:2117: End instruction execute. +DEBUG ../core.cpp:717: Register state: + %r 0: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r 1: 80000040 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r 2: 6fffeff0 6fffec04 6fffe808 6fffe40c 00000000 00000000 00000000 00000000 (0) + %r 3: 80001808 80001808 80001808 80001808 00000000 00000000 00000000 00000000 (0) + %r 4: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r 5: 80000a6c 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r 6: 0000000f 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r 7: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r 8: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r 9: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r10: 00000000 00000001 00000001 00000001 00000000 00000000 00000000 00000000 (0) + %r11: 80000924 00000400 00000800 00000c00 00000000 00000000 00000000 00000000 (0) + %r12: 00000000 00000004 00000008 0000000c 00000000 00000000 00000000 00000000 (0) + %r13: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r14: 00000001 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r15: 80001154 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r16: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r17: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r18: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r19: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r20: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r21: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r22: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r23: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r24: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r25: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r26: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r27: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r28: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r29: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r30: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r31: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) +DEBUG ../core.cpp:726: Thread mask: + 1 0 0 0 0 0 0 0 + + +DEBUG ../core.cpp:388: Now 1 active threads in 0 +********************************** Fetch ********************************* +valid: 1 +PC: 8000098c +wid: 0 +rd: -1 rs1: 2 rs2: 18 +is_lw: 0 +is_sw: 1 +fetch_stall_cycles: 0 +mem_stall_cycles: 0 +stall_warp: 0 +wspawn: 0 +stalled: 0 + + + +------------------------------------------------------ +CYCLE: 282 +Stalled Warps: +0 0 0 0 0 0 0 0 + +********************************** Writeback ********************************* +valid: 0 +PC: 0 +wid: 0 +rd: -1 rs1: -1 rs2: -1 +is_lw: 0 +is_sw: 0 +fetch_stall_cycles: 0 +mem_stall_cycles: 0 +stall_warp: 0 +wspawn: 0 +stalled: 0 +********************************** LSU ********************************* +valid: 0 +PC: 0 +wid: 2 +rd: -1 rs1: -1 rs2: -1 +is_lw: 0 +is_sw: 0 +fetch_stall_cycles: 0 +mem_stall_cycles: 0 +stall_warp: 0 +wspawn: 0 +stalled: 0 +********************************** execute_unit ********************************* +valid: 1 +PC: 80000984 +wid: 0 +rd: 2 rs1: 2 rs2: -1 +is_lw: 0 +is_sw: 0 +fetch_stall_cycles: 0 +mem_stall_cycles: 0 +stall_warp: 0 +wspawn: 0 +stalled: 0 +********************************** scheduler ********************************* +valid: 1 +PC: 80000988 +wid: 0 +rd: -1 rs1: 2 rs2: 8 +is_lw: 0 +is_sw: 1 +fetch_stall_cycles: 0 +mem_stall_cycles: 3 +stall_warp: 0 +wspawn: 0 +stalled: 0 +********************************** Decode ********************************* +valid: 1 +PC: 8000098c +wid: 0 +rd: -1 rs1: 2 rs2: 18 +is_lw: 0 +is_sw: 1 +fetch_stall_cycles: 0 +mem_stall_cycles: 0 +stall_warp: 0 +wspawn: 0 +stalled: 0 +DEBUG ../core.cpp:386: Core step stepping warp 0[1] +DEBUG ../core.cpp:683: in step pc=0x80000990 +help: in PC: 80000990 +CUrrent CODE: 80001437 +DEBUG ../core.cpp:703: Fetched at 0x80000990 +DEBUG ../core.cpp:704: 0x80000990: lui; +DEBUG ../instruction.cpp:350: Begin instruction execute. +DEBUG ../instruction.cpp:2117: End instruction execute. +DEBUG ../core.cpp:717: Register state: + %r 0: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r 1: 80000040 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r 2: 6fffeff0 6fffec04 6fffe808 6fffe40c 00000000 00000000 00000000 00000000 (0) + %r 3: 80001808 80001808 80001808 80001808 00000000 00000000 00000000 00000000 (0) + %r 4: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r 5: 80000a6c 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r 6: 0000000f 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r 7: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r 8: 80001000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r 9: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r10: 00000000 00000001 00000001 00000001 00000000 00000000 00000000 00000000 (0) + %r11: 80000924 00000400 00000800 00000c00 00000000 00000000 00000000 00000000 (0) + %r12: 00000000 00000004 00000008 0000000c 00000000 00000000 00000000 00000000 (0) + %r13: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r14: 00000001 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r15: 80001154 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r16: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r17: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r18: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r19: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r20: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r21: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r22: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r23: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r24: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r25: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r26: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r27: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r28: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r29: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r30: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r31: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) +DEBUG ../core.cpp:726: Thread mask: + 1 0 0 0 0 0 0 0 + + +DEBUG ../core.cpp:388: Now 1 active threads in 0 +********************************** Fetch ********************************* +valid: 1 +PC: 80000990 +wid: 0 +rd: 8 rs1: -1 rs2: -1 +is_lw: 0 +is_sw: 0 +fetch_stall_cycles: 3 +mem_stall_cycles: 0 +stall_warp: 0 +wspawn: 0 +stalled: 0 + + + +------------------------------------------------------ +CYCLE: 283 +Stalled Warps: +0 0 0 0 0 0 0 0 + +********************************** Writeback ********************************* +valid: 1 +PC: 80000984 +wid: 0 +rd: 2 rs1: 2 rs2: -1 +is_lw: 0 +is_sw: 0 +fetch_stall_cycles: 0 +mem_stall_cycles: 0 +stall_warp: 0 +wspawn: 0 +stalled: 0 +********************************** LSU ********************************* +valid: 0 +PC: 0 +wid: 2 +rd: -1 rs1: -1 rs2: -1 +is_lw: 0 +is_sw: 0 +fetch_stall_cycles: 0 +mem_stall_cycles: 0 +stall_warp: 0 +wspawn: 0 +stalled: 0 +********************************** execute_unit ********************************* +valid: 0 +PC: 0 +wid: 0 +rd: -1 rs1: -1 rs2: -1 +is_lw: 0 +is_sw: 0 +fetch_stall_cycles: 0 +mem_stall_cycles: 0 +stall_warp: 0 +wspawn: 0 +stalled: 0 +********************************** scheduler ********************************* +valid: 1 +PC: 80000988 +wid: 0 +rd: -1 rs1: 2 rs2: 8 +is_lw: 0 +is_sw: 1 +fetch_stall_cycles: 0 +mem_stall_cycles: 3 +stall_warp: 0 +wspawn: 0 +stalled: 1 +********************************** Decode ********************************* +valid: 1 +PC: 8000098c +wid: 0 +rd: -1 rs1: 2 rs2: 18 +is_lw: 0 +is_sw: 1 +fetch_stall_cycles: 0 +mem_stall_cycles: 0 +stall_warp: 0 +wspawn: 0 +stalled: 0 +********************************** Fetch ********************************* +valid: 1 +PC: 80000990 +wid: 0 +rd: 8 rs1: -1 rs2: -1 +is_lw: 0 +is_sw: 0 +fetch_stall_cycles: 2 +mem_stall_cycles: 0 +stall_warp: 0 +wspawn: 0 +stalled: 0 + + + +------------------------------------------------------ +CYCLE: 284 +Stalled Warps: +0 0 0 0 0 0 0 0 + +********************************** Writeback ********************************* +valid: 0 +PC: 0 +wid: 0 +rd: -1 rs1: -1 rs2: -1 +is_lw: 0 +is_sw: 0 +fetch_stall_cycles: 0 +mem_stall_cycles: 0 +stall_warp: 0 +wspawn: 0 +stalled: 0 +********************************** LSU ********************************* +valid: 1 +PC: 80000988 +wid: 0 +rd: -1 rs1: 2 rs2: 8 +is_lw: 0 +is_sw: 1 +fetch_stall_cycles: 0 +mem_stall_cycles: 2 +stall_warp: 0 +wspawn: 0 +stalled: 0 +********************************** execute_unit ********************************* +valid: 0 +PC: 0 +wid: 0 +rd: -1 rs1: -1 rs2: -1 +is_lw: 0 +is_sw: 0 +fetch_stall_cycles: 0 +mem_stall_cycles: 0 +stall_warp: 0 +wspawn: 0 +stalled: 0 +********************************** scheduler ********************************* +valid: 1 +PC: 8000098c +wid: 0 +rd: -1 rs1: 2 rs2: 18 +is_lw: 0 +is_sw: 1 +fetch_stall_cycles: 0 +mem_stall_cycles: 0 +stall_warp: 0 +wspawn: 0 +stalled: 0 +********************************** Decode ********************************* +valid: 0 +PC: 0 +wid: 0 +rd: -1 rs1: -1 rs2: -1 +is_lw: 0 +is_sw: 0 +fetch_stall_cycles: 0 +mem_stall_cycles: 0 +stall_warp: 0 +wspawn: 0 +stalled: 0 +********************************** Fetch ********************************* +valid: 1 +PC: 80000990 +wid: 0 +rd: 8 rs1: -1 rs2: -1 +is_lw: 0 +is_sw: 0 +fetch_stall_cycles: 1 +mem_stall_cycles: 0 +stall_warp: 0 +wspawn: 0 +stalled: 0 + + + +------------------------------------------------------ +CYCLE: 285 +Stalled Warps: +0 0 0 0 0 0 0 0 + +********************************** Writeback ********************************* +valid: 0 +PC: 0 +wid: 0 +rd: -1 rs1: -1 rs2: -1 +is_lw: 0 +is_sw: 0 +fetch_stall_cycles: 0 +mem_stall_cycles: 0 +stall_warp: 0 +wspawn: 0 +stalled: 0 +********************************** LSU ********************************* +valid: 1 +PC: 8000098c +wid: 0 +rd: -1 rs1: 2 rs2: 18 +is_lw: 0 +is_sw: 1 +fetch_stall_cycles: 0 +mem_stall_cycles: 0 +stall_warp: 0 +wspawn: 0 +stalled: 0 +********************************** execute_unit ********************************* +valid: 0 +PC: 0 +wid: 0 +rd: -1 rs1: -1 rs2: -1 +is_lw: 0 +is_sw: 0 +fetch_stall_cycles: 0 +mem_stall_cycles: 0 +stall_warp: 0 +wspawn: 0 +stalled: 0 +********************************** scheduler ********************************* +valid: 0 +PC: 0 +wid: 0 +rd: -1 rs1: -1 rs2: -1 +is_lw: 0 +is_sw: 0 +fetch_stall_cycles: 0 +mem_stall_cycles: 0 +stall_warp: 0 +wspawn: 0 +stalled: 0 +********************************** Decode ********************************* +valid: 0 +PC: 0 +wid: 0 +rd: -1 rs1: -1 rs2: -1 +is_lw: 0 +is_sw: 0 +fetch_stall_cycles: 0 +mem_stall_cycles: 0 +stall_warp: 0 +wspawn: 0 +stalled: 0 +********************************** Fetch ********************************* +valid: 1 +PC: 80000990 +wid: 0 +rd: 8 rs1: -1 rs2: -1 +is_lw: 0 +is_sw: 0 +fetch_stall_cycles: 0 +mem_stall_cycles: 0 +stall_warp: 0 +wspawn: 0 +stalled: 0 + + + +------------------------------------------------------ +CYCLE: 286 +Stalled Warps: +0 0 0 0 0 0 0 0 + +********************************** Writeback ********************************* +valid: 0 +PC: 0 +wid: 0 +rd: -1 rs1: -1 rs2: -1 +is_lw: 0 +is_sw: 0 +fetch_stall_cycles: 0 +mem_stall_cycles: 0 +stall_warp: 0 +wspawn: 0 +stalled: 0 +********************************** LSU ********************************* +valid: 0 +PC: 0 +wid: 0 +rd: -1 rs1: -1 rs2: -1 +is_lw: 0 +is_sw: 0 +fetch_stall_cycles: 0 +mem_stall_cycles: 0 +stall_warp: 0 +wspawn: 0 +stalled: 0 +********************************** execute_unit ********************************* +valid: 0 +PC: 0 +wid: 0 +rd: -1 rs1: -1 rs2: -1 +is_lw: 0 +is_sw: 0 +fetch_stall_cycles: 0 +mem_stall_cycles: 0 +stall_warp: 0 +wspawn: 0 +stalled: 0 +********************************** scheduler ********************************* +valid: 0 +PC: 0 +wid: 0 +rd: -1 rs1: -1 rs2: -1 +is_lw: 0 +is_sw: 0 +fetch_stall_cycles: 0 +mem_stall_cycles: 0 +stall_warp: 0 +wspawn: 0 +stalled: 0 +********************************** Decode ********************************* +valid: 1 +PC: 80000990 +wid: 0 +rd: 8 rs1: -1 rs2: -1 +is_lw: 0 +is_sw: 0 +fetch_stall_cycles: 0 +mem_stall_cycles: 0 +stall_warp: 0 +wspawn: 0 +stalled: 0 +DEBUG ../core.cpp:386: Core step stepping warp 0[1] +DEBUG ../core.cpp:683: in step pc=0x80000994 +help: in PC: 80000994 +CUrrent CODE: 80001937 +DEBUG ../core.cpp:703: Fetched at 0x80000994 +DEBUG ../core.cpp:704: 0x80000994: lui; +DEBUG ../instruction.cpp:350: Begin instruction execute. +DEBUG ../instruction.cpp:2117: End instruction execute. +DEBUG ../core.cpp:717: Register state: + %r 0: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r 1: 80000040 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r 2: 6fffeff0 6fffec04 6fffe808 6fffe40c 00000000 00000000 00000000 00000000 (0) + %r 3: 80001808 80001808 80001808 80001808 00000000 00000000 00000000 00000000 (0) + %r 4: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r 5: 80000a6c 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r 6: 0000000f 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r 7: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r 8: 80001000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r 9: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r10: 00000000 00000001 00000001 00000001 00000000 00000000 00000000 00000000 (0) + %r11: 80000924 00000400 00000800 00000c00 00000000 00000000 00000000 00000000 (0) + %r12: 00000000 00000004 00000008 0000000c 00000000 00000000 00000000 00000000 (0) + %r13: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r14: 00000001 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r15: 80001154 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r16: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r17: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r18: 80001000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r19: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r20: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r21: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r22: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r23: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r24: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r25: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r26: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r27: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r28: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r29: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r30: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r31: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) +DEBUG ../core.cpp:726: Thread mask: + 1 0 0 0 0 0 0 0 + + +DEBUG ../core.cpp:388: Now 1 active threads in 0 +********************************** Fetch ********************************* +valid: 1 +PC: 80000994 +wid: 0 +rd: 18 rs1: -1 rs2: -1 +is_lw: 0 +is_sw: 0 +fetch_stall_cycles: 0 +mem_stall_cycles: 0 +stall_warp: 0 +wspawn: 0 +stalled: 0 + + + +------------------------------------------------------ +CYCLE: 287 +Stalled Warps: +0 0 0 0 0 0 0 0 + +********************************** Writeback ********************************* +valid: 0 +PC: 0 +wid: 0 +rd: -1 rs1: -1 rs2: -1 +is_lw: 0 +is_sw: 0 +fetch_stall_cycles: 0 +mem_stall_cycles: 0 +stall_warp: 0 +wspawn: 0 +stalled: 0 +********************************** LSU ********************************* +valid: 0 +PC: 0 +wid: 0 +rd: -1 rs1: -1 rs2: -1 +is_lw: 0 +is_sw: 0 +fetch_stall_cycles: 0 +mem_stall_cycles: 0 +stall_warp: 0 +wspawn: 0 +stalled: 0 +********************************** execute_unit ********************************* +valid: 0 +PC: 0 +wid: 0 +rd: -1 rs1: -1 rs2: -1 +is_lw: 0 +is_sw: 0 +fetch_stall_cycles: 0 +mem_stall_cycles: 0 +stall_warp: 0 +wspawn: 0 +stalled: 0 +********************************** scheduler ********************************* +valid: 1 +PC: 80000990 +wid: 0 +rd: 8 rs1: -1 rs2: -1 +is_lw: 0 +is_sw: 0 +fetch_stall_cycles: 0 +mem_stall_cycles: 0 +stall_warp: 0 +wspawn: 0 +stalled: 0 +********************************** Decode ********************************* +valid: 1 +PC: 80000994 +wid: 0 +rd: 18 rs1: -1 rs2: -1 +is_lw: 0 +is_sw: 0 +fetch_stall_cycles: 0 +mem_stall_cycles: 0 +stall_warp: 0 +wspawn: 0 +stalled: 0 +DEBUG ../core.cpp:386: Core step stepping warp 0[1] +DEBUG ../core.cpp:683: in step pc=0x80000998 +help: in PC: 80000998 +CUrrent CODE: 40793 +DEBUG ../core.cpp:703: Fetched at 0x80000998 +DEBUG ../core.cpp:704: 0x80000998: i_type; +DEBUG ../instruction.cpp:350: Begin instruction execute. +DEBUG ../instruction.cpp:2117: End instruction execute. +DEBUG ../core.cpp:717: Register state: + %r 0: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r 1: 80000040 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r 2: 6fffeff0 6fffec04 6fffe808 6fffe40c 00000000 00000000 00000000 00000000 (0) + %r 3: 80001808 80001808 80001808 80001808 00000000 00000000 00000000 00000000 (0) + %r 4: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r 5: 80000a6c 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r 6: 0000000f 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r 7: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r 8: 80001000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r 9: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r10: 00000000 00000001 00000001 00000001 00000000 00000000 00000000 00000000 (0) + %r11: 80000924 00000400 00000800 00000c00 00000000 00000000 00000000 00000000 (0) + %r12: 00000000 00000004 00000008 0000000c 00000000 00000000 00000000 00000000 (0) + %r13: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r14: 00000001 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r15: 80001000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r16: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r17: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r18: 80001000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r19: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r20: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r21: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r22: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r23: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r24: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r25: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r26: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r27: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r28: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r29: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r30: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r31: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) +DEBUG ../core.cpp:726: Thread mask: + 1 0 0 0 0 0 0 0 + + +DEBUG ../core.cpp:388: Now 1 active threads in 0 +********************************** Fetch ********************************* +valid: 1 +PC: 80000998 +wid: 0 +rd: 15 rs1: 8 rs2: -1 +is_lw: 0 +is_sw: 0 +fetch_stall_cycles: 0 +mem_stall_cycles: 0 +stall_warp: 0 +wspawn: 0 +stalled: 0 + + + +------------------------------------------------------ +CYCLE: 288 +Stalled Warps: +0 0 0 0 0 0 0 0 + +********************************** Writeback ********************************* +valid: 0 +PC: 0 +wid: 0 +rd: -1 rs1: -1 rs2: -1 +is_lw: 0 +is_sw: 0 +fetch_stall_cycles: 0 +mem_stall_cycles: 0 +stall_warp: 0 +wspawn: 0 +stalled: 0 +********************************** LSU ********************************* +valid: 0 +PC: 0 +wid: 0 +rd: -1 rs1: -1 rs2: -1 +is_lw: 0 +is_sw: 0 +fetch_stall_cycles: 0 +mem_stall_cycles: 0 +stall_warp: 0 +wspawn: 0 +stalled: 0 +********************************** execute_unit ********************************* +valid: 1 +PC: 80000990 +wid: 0 +rd: 8 rs1: -1 rs2: -1 +is_lw: 0 +is_sw: 0 +fetch_stall_cycles: 0 +mem_stall_cycles: 0 +stall_warp: 0 +wspawn: 0 +stalled: 0 +********************************** scheduler ********************************* +valid: 1 +PC: 80000994 +wid: 0 +rd: 18 rs1: -1 rs2: -1 +is_lw: 0 +is_sw: 0 +fetch_stall_cycles: 0 +mem_stall_cycles: 0 +stall_warp: 0 +wspawn: 0 +stalled: 0 +********************************** Decode ********************************* +valid: 1 +PC: 80000998 +wid: 0 +rd: 15 rs1: 8 rs2: -1 +is_lw: 0 +is_sw: 0 +fetch_stall_cycles: 0 +mem_stall_cycles: 0 +stall_warp: 0 +wspawn: 0 +stalled: 0 +DEBUG ../core.cpp:386: Core step stepping warp 0[1] +DEBUG ../core.cpp:683: in step pc=0x8000099c +help: in PC: 8000099c +CUrrent CODE: 90913 +DEBUG ../core.cpp:703: Fetched at 0x8000099c +DEBUG ../core.cpp:704: 0x8000099c: i_type; +DEBUG ../instruction.cpp:350: Begin instruction execute. +DEBUG ../instruction.cpp:2117: End instruction execute. +DEBUG ../core.cpp:717: Register state: + %r 0: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r 1: 80000040 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r 2: 6fffeff0 6fffec04 6fffe808 6fffe40c 00000000 00000000 00000000 00000000 (0) + %r 3: 80001808 80001808 80001808 80001808 00000000 00000000 00000000 00000000 (0) + %r 4: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r 5: 80000a6c 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r 6: 0000000f 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r 7: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r 8: 80001000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r 9: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r10: 00000000 00000001 00000001 00000001 00000000 00000000 00000000 00000000 (0) + %r11: 80000924 00000400 00000800 00000c00 00000000 00000000 00000000 00000000 (0) + %r12: 00000000 00000004 00000008 0000000c 00000000 00000000 00000000 00000000 (0) + %r13: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r14: 00000001 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r15: 80001000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r16: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r17: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r18: 80001000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r19: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r20: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r21: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r22: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r23: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r24: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r25: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r26: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r27: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r28: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r29: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r30: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r31: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) +DEBUG ../core.cpp:726: Thread mask: + 1 0 0 0 0 0 0 0 + + +DEBUG ../core.cpp:388: Now 1 active threads in 0 +********************************** Fetch ********************************* +valid: 1 +PC: 8000099c +wid: 0 +rd: 18 rs1: 18 rs2: -1 +is_lw: 0 +is_sw: 0 +fetch_stall_cycles: 0 +mem_stall_cycles: 0 +stall_warp: 0 +wspawn: 0 +stalled: 0 + + + +------------------------------------------------------ +CYCLE: 289 +Stalled Warps: +0 0 0 0 0 0 0 0 + +********************************** Writeback ********************************* +valid: 1 +PC: 80000990 +wid: 0 +rd: 8 rs1: -1 rs2: -1 +is_lw: 0 +is_sw: 0 +fetch_stall_cycles: 0 +mem_stall_cycles: 0 +stall_warp: 0 +wspawn: 0 +stalled: 0 +********************************** LSU ********************************* +valid: 0 +PC: 0 +wid: 0 +rd: -1 rs1: -1 rs2: -1 +is_lw: 0 +is_sw: 0 +fetch_stall_cycles: 0 +mem_stall_cycles: 0 +stall_warp: 0 +wspawn: 0 +stalled: 0 +********************************** execute_unit ********************************* +valid: 1 +PC: 80000994 +wid: 0 +rd: 18 rs1: -1 rs2: -1 +is_lw: 0 +is_sw: 0 +fetch_stall_cycles: 0 +mem_stall_cycles: 0 +stall_warp: 0 +wspawn: 0 +stalled: 0 +********************************** scheduler ********************************* +valid: 1 +PC: 80000998 +wid: 0 +rd: 15 rs1: 8 rs2: -1 +is_lw: 0 +is_sw: 0 +fetch_stall_cycles: 0 +mem_stall_cycles: 0 +stall_warp: 0 +wspawn: 0 +stalled: 0 +********************************** Decode ********************************* +valid: 1 +PC: 8000099c +wid: 0 +rd: 18 rs1: 18 rs2: -1 +is_lw: 0 +is_sw: 0 +fetch_stall_cycles: 0 +mem_stall_cycles: 0 +stall_warp: 0 +wspawn: 0 +stalled: 0 +DEBUG ../core.cpp:386: Core step stepping warp 0[1] +DEBUG ../core.cpp:683: in step pc=0x800009a0 +help: in PC: 800009a0 +CUrrent CODE: 40f90933 +DEBUG ../core.cpp:703: Fetched at 0x800009a0 +DEBUG ../core.cpp:704: 0x800009a0: r_type; +DEBUG ../instruction.cpp:350: Begin instruction execute. +DEBUG ../instruction.cpp:2117: End instruction execute. +DEBUG ../core.cpp:717: Register state: + %r 0: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r 1: 80000040 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r 2: 6fffeff0 6fffec04 6fffe808 6fffe40c 00000000 00000000 00000000 00000000 (0) + %r 3: 80001808 80001808 80001808 80001808 00000000 00000000 00000000 00000000 (0) + %r 4: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r 5: 80000a6c 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r 6: 0000000f 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r 7: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r 8: 80001000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r 9: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r10: 00000000 00000001 00000001 00000001 00000000 00000000 00000000 00000000 (0) + %r11: 80000924 00000400 00000800 00000c00 00000000 00000000 00000000 00000000 (0) + %r12: 00000000 00000004 00000008 0000000c 00000000 00000000 00000000 00000000 (0) + %r13: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r14: 00000001 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r15: 80001000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r16: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r17: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r18: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r19: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r20: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r21: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r22: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r23: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r24: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r25: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r26: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r27: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r28: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r29: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r30: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r31: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) +DEBUG ../core.cpp:726: Thread mask: + 1 0 0 0 0 0 0 0 + + +DEBUG ../core.cpp:388: Now 1 active threads in 0 +********************************** Fetch ********************************* +valid: 1 +PC: 800009a0 +wid: 0 +rd: 18 rs1: 18 rs2: 15 +is_lw: 0 +is_sw: 0 +fetch_stall_cycles: 3 +mem_stall_cycles: 0 +stall_warp: 0 +wspawn: 0 +stalled: 0 + + + +------------------------------------------------------ +CYCLE: 290 +Stalled Warps: +0 0 0 0 0 0 0 0 + +********************************** Writeback ********************************* +valid: 1 +PC: 80000994 +wid: 0 +rd: 18 rs1: -1 rs2: -1 +is_lw: 0 +is_sw: 0 +fetch_stall_cycles: 0 +mem_stall_cycles: 0 +stall_warp: 0 +wspawn: 0 +stalled: 0 +********************************** LSU ********************************* +valid: 0 +PC: 0 +wid: 0 +rd: -1 rs1: -1 rs2: -1 +is_lw: 0 +is_sw: 0 +fetch_stall_cycles: 0 +mem_stall_cycles: 0 +stall_warp: 0 +wspawn: 0 +stalled: 0 +********************************** execute_unit ********************************* +valid: 1 +PC: 80000998 +wid: 0 +rd: 15 rs1: 8 rs2: -1 +is_lw: 0 +is_sw: 0 +fetch_stall_cycles: 0 +mem_stall_cycles: 0 +stall_warp: 0 +wspawn: 0 +stalled: 0 +********************************** scheduler ********************************* +valid: 1 +PC: 8000099c +wid: 0 +rd: 18 rs1: 18 rs2: -1 +is_lw: 0 +is_sw: 0 +fetch_stall_cycles: 0 +mem_stall_cycles: 0 +stall_warp: 0 +wspawn: 0 +stalled: 0 +********************************** Decode ********************************* +valid: 0 +PC: 0 +wid: 0 +rd: -1 rs1: -1 rs2: -1 +is_lw: 0 +is_sw: 0 +fetch_stall_cycles: 0 +mem_stall_cycles: 0 +stall_warp: 0 +wspawn: 0 +stalled: 0 +********************************** Fetch ********************************* +valid: 1 +PC: 800009a0 +wid: 0 +rd: 18 rs1: 18 rs2: 15 +is_lw: 0 +is_sw: 0 +fetch_stall_cycles: 2 +mem_stall_cycles: 0 +stall_warp: 0 +wspawn: 0 +stalled: 0 + + + +------------------------------------------------------ +CYCLE: 291 +Stalled Warps: +0 0 0 0 0 0 0 0 + +********************************** Writeback ********************************* +valid: 1 +PC: 80000998 +wid: 0 +rd: 15 rs1: 8 rs2: -1 +is_lw: 0 +is_sw: 0 +fetch_stall_cycles: 0 +mem_stall_cycles: 0 +stall_warp: 0 +wspawn: 0 +stalled: 0 +********************************** LSU ********************************* +valid: 0 +PC: 0 +wid: 0 +rd: -1 rs1: -1 rs2: -1 +is_lw: 0 +is_sw: 0 +fetch_stall_cycles: 0 +mem_stall_cycles: 0 +stall_warp: 0 +wspawn: 0 +stalled: 0 +********************************** execute_unit ********************************* +valid: 1 +PC: 8000099c +wid: 0 +rd: 18 rs1: 18 rs2: -1 +is_lw: 0 +is_sw: 0 +fetch_stall_cycles: 0 +mem_stall_cycles: 0 +stall_warp: 0 +wspawn: 0 +stalled: 0 +********************************** scheduler ********************************* +valid: 0 +PC: 0 +wid: 0 +rd: -1 rs1: -1 rs2: -1 +is_lw: 0 +is_sw: 0 +fetch_stall_cycles: 0 +mem_stall_cycles: 0 +stall_warp: 0 +wspawn: 0 +stalled: 0 +********************************** Decode ********************************* +valid: 0 +PC: 0 +wid: 0 +rd: -1 rs1: -1 rs2: -1 +is_lw: 0 +is_sw: 0 +fetch_stall_cycles: 0 +mem_stall_cycles: 0 +stall_warp: 0 +wspawn: 0 +stalled: 0 +********************************** Fetch ********************************* +valid: 1 +PC: 800009a0 +wid: 0 +rd: 18 rs1: 18 rs2: 15 +is_lw: 0 +is_sw: 0 +fetch_stall_cycles: 1 +mem_stall_cycles: 0 +stall_warp: 0 +wspawn: 0 +stalled: 0 + + + +------------------------------------------------------ +CYCLE: 292 +Stalled Warps: +0 0 0 0 0 0 0 0 + +********************************** Writeback ********************************* +valid: 1 +PC: 8000099c +wid: 0 +rd: 18 rs1: 18 rs2: -1 +is_lw: 0 +is_sw: 0 +fetch_stall_cycles: 0 +mem_stall_cycles: 0 +stall_warp: 0 +wspawn: 0 +stalled: 0 +********************************** LSU ********************************* +valid: 0 +PC: 0 +wid: 0 +rd: -1 rs1: -1 rs2: -1 +is_lw: 0 +is_sw: 0 +fetch_stall_cycles: 0 +mem_stall_cycles: 0 +stall_warp: 0 +wspawn: 0 +stalled: 0 +********************************** execute_unit ********************************* +valid: 0 +PC: 0 +wid: 0 +rd: -1 rs1: -1 rs2: -1 +is_lw: 0 +is_sw: 0 +fetch_stall_cycles: 0 +mem_stall_cycles: 0 +stall_warp: 0 +wspawn: 0 +stalled: 0 +********************************** scheduler ********************************* +valid: 0 +PC: 0 +wid: 0 +rd: -1 rs1: -1 rs2: -1 +is_lw: 0 +is_sw: 0 +fetch_stall_cycles: 0 +mem_stall_cycles: 0 +stall_warp: 0 +wspawn: 0 +stalled: 0 +********************************** Decode ********************************* +valid: 0 +PC: 0 +wid: 0 +rd: -1 rs1: -1 rs2: -1 +is_lw: 0 +is_sw: 0 +fetch_stall_cycles: 0 +mem_stall_cycles: 0 +stall_warp: 0 +wspawn: 0 +stalled: 0 +********************************** Fetch ********************************* +valid: 1 +PC: 800009a0 +wid: 0 +rd: 18 rs1: 18 rs2: 15 +is_lw: 0 +is_sw: 0 +fetch_stall_cycles: 0 +mem_stall_cycles: 0 +stall_warp: 0 +wspawn: 0 +stalled: 0 + + + +------------------------------------------------------ +CYCLE: 293 +Stalled Warps: +0 0 0 0 0 0 0 0 + +********************************** Writeback ********************************* +valid: 0 +PC: 0 +wid: 0 +rd: -1 rs1: -1 rs2: -1 +is_lw: 0 +is_sw: 0 +fetch_stall_cycles: 0 +mem_stall_cycles: 0 +stall_warp: 0 +wspawn: 0 +stalled: 0 +********************************** LSU ********************************* +valid: 0 +PC: 0 +wid: 0 +rd: -1 rs1: -1 rs2: -1 +is_lw: 0 +is_sw: 0 +fetch_stall_cycles: 0 +mem_stall_cycles: 0 +stall_warp: 0 +wspawn: 0 +stalled: 0 +********************************** execute_unit ********************************* +valid: 0 +PC: 0 +wid: 0 +rd: -1 rs1: -1 rs2: -1 +is_lw: 0 +is_sw: 0 +fetch_stall_cycles: 0 +mem_stall_cycles: 0 +stall_warp: 0 +wspawn: 0 +stalled: 0 +********************************** scheduler ********************************* +valid: 0 +PC: 0 +wid: 0 +rd: -1 rs1: -1 rs2: -1 +is_lw: 0 +is_sw: 0 +fetch_stall_cycles: 0 +mem_stall_cycles: 0 +stall_warp: 0 +wspawn: 0 +stalled: 0 +********************************** Decode ********************************* +valid: 1 +PC: 800009a0 +wid: 0 +rd: 18 rs1: 18 rs2: 15 +is_lw: 0 +is_sw: 0 +fetch_stall_cycles: 0 +mem_stall_cycles: 0 +stall_warp: 0 +wspawn: 0 +stalled: 0 +DEBUG ../core.cpp:386: Core step stepping warp 0[1] +DEBUG ../core.cpp:683: in step pc=0x800009a4 +help: in PC: 800009a4 +CUrrent CODE: 112623 +DEBUG ../core.cpp:703: Fetched at 0x800009a4 +DEBUG ../core.cpp:704: 0x800009a4: store; +DEBUG ../instruction.cpp:350: Begin instruction execute. +STORE MEM ADDRESS: 6fffeff0 + c +DEBUG ../instruction.cpp:2117: End instruction execute. +DEBUG ../core.cpp:717: Register state: + %r 0: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r 1: 80000040 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r 2: 6fffeff0 6fffec04 6fffe808 6fffe40c 00000000 00000000 00000000 00000000 (0) + %r 3: 80001808 80001808 80001808 80001808 00000000 00000000 00000000 00000000 (0) + %r 4: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r 5: 80000a6c 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r 6: 0000000f 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r 7: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r 8: 80001000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r 9: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r10: 00000000 00000001 00000001 00000001 00000000 00000000 00000000 00000000 (0) + %r11: 80000924 00000400 00000800 00000c00 00000000 00000000 00000000 00000000 (0) + %r12: 00000000 00000004 00000008 0000000c 00000000 00000000 00000000 00000000 (0) + %r13: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r14: 00000001 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r15: 80001000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r16: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r17: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r18: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r19: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r20: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r21: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r22: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r23: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r24: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r25: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r26: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r27: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r28: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r29: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r30: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r31: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) +DEBUG ../core.cpp:726: Thread mask: + 1 0 0 0 0 0 0 0 + + +DEBUG ../core.cpp:388: Now 1 active threads in 0 +********************************** Fetch ********************************* +valid: 1 +PC: 800009a4 +wid: 0 +rd: -1 rs1: 2 rs2: 1 +is_lw: 0 +is_sw: 1 +fetch_stall_cycles: 0 +mem_stall_cycles: 0 +stall_warp: 0 +wspawn: 0 +stalled: 0 + + + +------------------------------------------------------ +CYCLE: 294 +Stalled Warps: +0 0 0 0 0 0 0 0 + +********************************** Writeback ********************************* +valid: 0 +PC: 0 +wid: 0 +rd: -1 rs1: -1 rs2: -1 +is_lw: 0 +is_sw: 0 +fetch_stall_cycles: 0 +mem_stall_cycles: 0 +stall_warp: 0 +wspawn: 0 +stalled: 0 +********************************** LSU ********************************* +valid: 0 +PC: 0 +wid: 0 +rd: -1 rs1: -1 rs2: -1 +is_lw: 0 +is_sw: 0 +fetch_stall_cycles: 0 +mem_stall_cycles: 0 +stall_warp: 0 +wspawn: 0 +stalled: 0 +********************************** execute_unit ********************************* +valid: 0 +PC: 0 +wid: 0 +rd: -1 rs1: -1 rs2: -1 +is_lw: 0 +is_sw: 0 +fetch_stall_cycles: 0 +mem_stall_cycles: 0 +stall_warp: 0 +wspawn: 0 +stalled: 0 +********************************** scheduler ********************************* +valid: 1 +PC: 800009a0 +wid: 0 +rd: 18 rs1: 18 rs2: 15 +is_lw: 0 +is_sw: 0 +fetch_stall_cycles: 0 +mem_stall_cycles: 0 +stall_warp: 0 +wspawn: 0 +stalled: 0 +********************************** Decode ********************************* +valid: 1 +PC: 800009a4 +wid: 0 +rd: -1 rs1: 2 rs2: 1 +is_lw: 0 +is_sw: 1 +fetch_stall_cycles: 0 +mem_stall_cycles: 0 +stall_warp: 0 +wspawn: 0 +stalled: 0 +DEBUG ../core.cpp:386: Core step stepping warp 0[1] +DEBUG ../core.cpp:683: in step pc=0x800009a8 +help: in PC: 800009a8 +CUrrent CODE: 912223 +DEBUG ../core.cpp:703: Fetched at 0x800009a8 +DEBUG ../core.cpp:704: 0x800009a8: store; +DEBUG ../instruction.cpp:350: Begin instruction execute. +STORE MEM ADDRESS: 6fffeff0 + 4 +DEBUG ../instruction.cpp:2117: End instruction execute. +DEBUG ../core.cpp:717: Register state: + %r 0: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r 1: 80000040 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r 2: 6fffeff0 6fffec04 6fffe808 6fffe40c 00000000 00000000 00000000 00000000 (0) + %r 3: 80001808 80001808 80001808 80001808 00000000 00000000 00000000 00000000 (0) + %r 4: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r 5: 80000a6c 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r 6: 0000000f 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r 7: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r 8: 80001000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r 9: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r10: 00000000 00000001 00000001 00000001 00000000 00000000 00000000 00000000 (0) + %r11: 80000924 00000400 00000800 00000c00 00000000 00000000 00000000 00000000 (0) + %r12: 00000000 00000004 00000008 0000000c 00000000 00000000 00000000 00000000 (0) + %r13: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r14: 00000001 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r15: 80001000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r16: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r17: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r18: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r19: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r20: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r21: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r22: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r23: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r24: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r25: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r26: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r27: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r28: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r29: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r30: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r31: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) +DEBUG ../core.cpp:726: Thread mask: + 1 0 0 0 0 0 0 0 + + +DEBUG ../core.cpp:388: Now 1 active threads in 0 +********************************** Fetch ********************************* +valid: 1 +PC: 800009a8 +wid: 0 +rd: -1 rs1: 2 rs2: 9 +is_lw: 0 +is_sw: 1 +fetch_stall_cycles: 0 +mem_stall_cycles: 0 +stall_warp: 0 +wspawn: 0 +stalled: 0 + + + +------------------------------------------------------ +CYCLE: 295 +Stalled Warps: +0 0 0 0 0 0 0 0 + +********************************** Writeback ********************************* +valid: 0 +PC: 0 +wid: 0 +rd: -1 rs1: -1 rs2: -1 +is_lw: 0 +is_sw: 0 +fetch_stall_cycles: 0 +mem_stall_cycles: 0 +stall_warp: 0 +wspawn: 0 +stalled: 0 +********************************** LSU ********************************* +valid: 0 +PC: 0 +wid: 0 +rd: -1 rs1: -1 rs2: -1 +is_lw: 0 +is_sw: 0 +fetch_stall_cycles: 0 +mem_stall_cycles: 0 +stall_warp: 0 +wspawn: 0 +stalled: 0 +********************************** execute_unit ********************************* +valid: 1 +PC: 800009a0 +wid: 0 +rd: 18 rs1: 18 rs2: 15 +is_lw: 0 +is_sw: 0 +fetch_stall_cycles: 0 +mem_stall_cycles: 0 +stall_warp: 0 +wspawn: 0 +stalled: 0 +********************************** scheduler ********************************* +valid: 1 +PC: 800009a4 +wid: 0 +rd: -1 rs1: 2 rs2: 1 +is_lw: 0 +is_sw: 1 +fetch_stall_cycles: 0 +mem_stall_cycles: 0 +stall_warp: 0 +wspawn: 0 +stalled: 0 +********************************** Decode ********************************* +valid: 1 +PC: 800009a8 +wid: 0 +rd: -1 rs1: 2 rs2: 9 +is_lw: 0 +is_sw: 1 +fetch_stall_cycles: 0 +mem_stall_cycles: 0 +stall_warp: 0 +wspawn: 0 +stalled: 0 +DEBUG ../core.cpp:386: Core step stepping warp 0[1] +DEBUG ../core.cpp:683: in step pc=0x800009ac +help: in PC: 800009ac +CUrrent CODE: 40295913 +DEBUG ../core.cpp:703: Fetched at 0x800009ac +DEBUG ../core.cpp:704: 0x800009ac: i_type; +DEBUG ../instruction.cpp:350: Begin instruction execute. +DEBUG ../instruction.cpp:2117: End instruction execute. +DEBUG ../core.cpp:717: Register state: + %r 0: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r 1: 80000040 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r 2: 6fffeff0 6fffec04 6fffe808 6fffe40c 00000000 00000000 00000000 00000000 (0) + %r 3: 80001808 80001808 80001808 80001808 00000000 00000000 00000000 00000000 (0) + %r 4: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r 5: 80000a6c 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r 6: 0000000f 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r 7: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r 8: 80001000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r 9: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r10: 00000000 00000001 00000001 00000001 00000000 00000000 00000000 00000000 (0) + %r11: 80000924 00000400 00000800 00000c00 00000000 00000000 00000000 00000000 (0) + %r12: 00000000 00000004 00000008 0000000c 00000000 00000000 00000000 00000000 (0) + %r13: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r14: 00000001 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r15: 80001000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r16: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r17: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r18: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r19: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r20: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r21: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r22: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r23: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r24: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r25: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r26: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r27: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r28: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r29: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r30: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r31: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) +DEBUG ../core.cpp:726: Thread mask: + 1 0 0 0 0 0 0 0 + + +DEBUG ../core.cpp:388: Now 1 active threads in 0 +********************************** Fetch ********************************* +valid: 1 +PC: 800009ac +wid: 0 +rd: 18 rs1: 18 rs2: -1 +is_lw: 0 +is_sw: 0 +fetch_stall_cycles: 0 +mem_stall_cycles: 0 +stall_warp: 0 +wspawn: 0 +stalled: 0 + + + +------------------------------------------------------ +CYCLE: 296 +Stalled Warps: +0 0 0 0 0 0 0 0 + +********************************** Writeback ********************************* +valid: 1 +PC: 800009a0 +wid: 0 +rd: 18 rs1: 18 rs2: 15 +is_lw: 0 +is_sw: 0 +fetch_stall_cycles: 0 +mem_stall_cycles: 0 +stall_warp: 0 +wspawn: 0 +stalled: 0 +********************************** LSU ********************************* +valid: 1 +PC: 800009a4 +wid: 0 +rd: -1 rs1: 2 rs2: 1 +is_lw: 0 +is_sw: 1 +fetch_stall_cycles: 0 +mem_stall_cycles: 0 +stall_warp: 0 +wspawn: 0 +stalled: 0 +********************************** execute_unit ********************************* +valid: 0 +PC: 0 +wid: 0 +rd: -1 rs1: -1 rs2: -1 +is_lw: 0 +is_sw: 0 +fetch_stall_cycles: 0 +mem_stall_cycles: 0 +stall_warp: 0 +wspawn: 0 +stalled: 0 +********************************** scheduler ********************************* +valid: 1 +PC: 800009a8 +wid: 0 +rd: -1 rs1: 2 rs2: 9 +is_lw: 0 +is_sw: 1 +fetch_stall_cycles: 0 +mem_stall_cycles: 0 +stall_warp: 0 +wspawn: 0 +stalled: 0 +********************************** Decode ********************************* +valid: 1 +PC: 800009ac +wid: 0 +rd: 18 rs1: 18 rs2: -1 +is_lw: 0 +is_sw: 0 +fetch_stall_cycles: 0 +mem_stall_cycles: 0 +stall_warp: 0 +wspawn: 0 +stalled: 0 +DEBUG ../core.cpp:386: Core step stepping warp 0[1] +DEBUG ../core.cpp:683: in step pc=0x800009b0 +help: in PC: 800009b0 +CUrrent CODE: 2090063 +DEBUG ../core.cpp:703: Fetched at 0x800009b0 +DEBUG ../core.cpp:704: 0x800009b0: branch; +DEBUG ../instruction.cpp:350: Begin instruction execute. +DEBUG ../instruction.cpp:2117: End instruction execute. +Next PC: 800009d0 +DEBUG ../core.cpp:717: Register state: + %r 0: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r 1: 80000040 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r 2: 6fffeff0 6fffec04 6fffe808 6fffe40c 00000000 00000000 00000000 00000000 (0) + %r 3: 80001808 80001808 80001808 80001808 00000000 00000000 00000000 00000000 (0) + %r 4: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r 5: 80000a6c 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r 6: 0000000f 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r 7: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r 8: 80001000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r 9: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r10: 00000000 00000001 00000001 00000001 00000000 00000000 00000000 00000000 (0) + %r11: 80000924 00000400 00000800 00000c00 00000000 00000000 00000000 00000000 (0) + %r12: 00000000 00000004 00000008 0000000c 00000000 00000000 00000000 00000000 (0) + %r13: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r14: 00000001 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r15: 80001000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r16: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r17: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r18: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r19: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r20: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r21: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r22: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r23: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r24: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r25: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r26: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r27: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r28: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r29: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r30: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r31: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) +DEBUG ../core.cpp:726: Thread mask: + 1 0 0 0 0 0 0 0 + + +DEBUG ../core.cpp:388: Now 1 active threads in 0 +********************************** Fetch ********************************* +valid: 1 +PC: 800009b0 +wid: 0 +rd: -1 rs1: 18 rs2: 0 +is_lw: 0 +is_sw: 0 +fetch_stall_cycles: 3 +mem_stall_cycles: 0 +stall_warp: 1 +wspawn: 0 +stalled: 0 + + + +------------------------------------------------------ +CYCLE: 297 +Stalled Warps: +1 0 0 0 0 0 0 0 + +********************************** Writeback ********************************* +valid: 0 +PC: 0 +wid: 1 +rd: -1 rs1: -1 rs2: -1 +is_lw: 0 +is_sw: 0 +fetch_stall_cycles: 0 +mem_stall_cycles: 0 +stall_warp: 0 +wspawn: 0 +stalled: 0 +********************************** LSU ********************************* +valid: 1 +PC: 800009a8 +wid: 0 +rd: -1 rs1: 2 rs2: 9 +is_lw: 0 +is_sw: 1 +fetch_stall_cycles: 0 +mem_stall_cycles: 0 +stall_warp: 0 +wspawn: 0 +stalled: 0 +********************************** execute_unit ********************************* +valid: 0 +PC: 0 +wid: 1 +rd: -1 rs1: -1 rs2: -1 +is_lw: 0 +is_sw: 0 +fetch_stall_cycles: 0 +mem_stall_cycles: 0 +stall_warp: 0 +wspawn: 0 +stalled: 0 +********************************** scheduler ********************************* +valid: 1 +PC: 800009ac +wid: 0 +rd: 18 rs1: 18 rs2: -1 +is_lw: 0 +is_sw: 0 +fetch_stall_cycles: 0 +mem_stall_cycles: 0 +stall_warp: 0 +wspawn: 0 +stalled: 0 +********************************** Decode ********************************* +valid: 0 +PC: 0 +wid: 1 +rd: -1 rs1: -1 rs2: -1 +is_lw: 0 +is_sw: 0 +fetch_stall_cycles: 0 +mem_stall_cycles: 0 +stall_warp: 0 +wspawn: 0 +stalled: 0 +********************************** Fetch ********************************* +valid: 1 +PC: 800009b0 +wid: 0 +rd: -1 rs1: 18 rs2: 0 +is_lw: 0 +is_sw: 0 +fetch_stall_cycles: 2 +mem_stall_cycles: 0 +stall_warp: 1 +wspawn: 0 +stalled: 0 + + + +------------------------------------------------------ +CYCLE: 298 +Stalled Warps: +1 0 0 0 0 0 0 0 + +********************************** Writeback ********************************* +valid: 0 +PC: 0 +wid: 1 +rd: -1 rs1: -1 rs2: -1 +is_lw: 0 +is_sw: 0 +fetch_stall_cycles: 0 +mem_stall_cycles: 0 +stall_warp: 0 +wspawn: 0 +stalled: 0 +********************************** LSU ********************************* +valid: 0 +PC: 0 +wid: 1 +rd: -1 rs1: -1 rs2: -1 +is_lw: 0 +is_sw: 0 +fetch_stall_cycles: 0 +mem_stall_cycles: 0 +stall_warp: 0 +wspawn: 0 +stalled: 0 +********************************** execute_unit ********************************* +valid: 1 +PC: 800009ac +wid: 0 +rd: 18 rs1: 18 rs2: -1 +is_lw: 0 +is_sw: 0 +fetch_stall_cycles: 0 +mem_stall_cycles: 0 +stall_warp: 0 +wspawn: 0 +stalled: 0 +********************************** scheduler ********************************* +valid: 0 +PC: 0 +wid: 1 +rd: -1 rs1: -1 rs2: -1 +is_lw: 0 +is_sw: 0 +fetch_stall_cycles: 0 +mem_stall_cycles: 0 +stall_warp: 0 +wspawn: 0 +stalled: 0 +********************************** Decode ********************************* +valid: 0 +PC: 0 +wid: 1 +rd: -1 rs1: -1 rs2: -1 +is_lw: 0 +is_sw: 0 +fetch_stall_cycles: 0 +mem_stall_cycles: 0 +stall_warp: 0 +wspawn: 0 +stalled: 0 +********************************** Fetch ********************************* +valid: 1 +PC: 800009b0 +wid: 0 +rd: -1 rs1: 18 rs2: 0 +is_lw: 0 +is_sw: 0 +fetch_stall_cycles: 1 +mem_stall_cycles: 0 +stall_warp: 1 +wspawn: 0 +stalled: 0 + + + +------------------------------------------------------ +CYCLE: 299 +Stalled Warps: +1 0 0 0 0 0 0 0 + +********************************** Writeback ********************************* +valid: 1 +PC: 800009ac +wid: 0 +rd: 18 rs1: 18 rs2: -1 +is_lw: 0 +is_sw: 0 +fetch_stall_cycles: 0 +mem_stall_cycles: 0 +stall_warp: 0 +wspawn: 0 +stalled: 0 +********************************** LSU ********************************* +valid: 0 +PC: 0 +wid: 1 +rd: -1 rs1: -1 rs2: -1 +is_lw: 0 +is_sw: 0 +fetch_stall_cycles: 0 +mem_stall_cycles: 0 +stall_warp: 0 +wspawn: 0 +stalled: 0 +********************************** execute_unit ********************************* +valid: 0 +PC: 0 +wid: 1 +rd: -1 rs1: -1 rs2: -1 +is_lw: 0 +is_sw: 0 +fetch_stall_cycles: 0 +mem_stall_cycles: 0 +stall_warp: 0 +wspawn: 0 +stalled: 0 +********************************** scheduler ********************************* +valid: 0 +PC: 0 +wid: 1 +rd: -1 rs1: -1 rs2: -1 +is_lw: 0 +is_sw: 0 +fetch_stall_cycles: 0 +mem_stall_cycles: 0 +stall_warp: 0 +wspawn: 0 +stalled: 0 +********************************** Decode ********************************* +valid: 0 +PC: 0 +wid: 1 +rd: -1 rs1: -1 rs2: -1 +is_lw: 0 +is_sw: 0 +fetch_stall_cycles: 0 +mem_stall_cycles: 0 +stall_warp: 0 +wspawn: 0 +stalled: 0 +********************************** Fetch ********************************* +valid: 1 +PC: 800009b0 +wid: 0 +rd: -1 rs1: 18 rs2: 0 +is_lw: 0 +is_sw: 0 +fetch_stall_cycles: 0 +mem_stall_cycles: 0 +stall_warp: 1 +wspawn: 0 +stalled: 0 + + + +------------------------------------------------------ +CYCLE: 300 +Stalled Warps: +1 0 0 0 0 0 0 0 + +********************************** Writeback ********************************* +valid: 0 +PC: 0 +wid: 1 +rd: -1 rs1: -1 rs2: -1 +is_lw: 0 +is_sw: 0 +fetch_stall_cycles: 0 +mem_stall_cycles: 0 +stall_warp: 0 +wspawn: 0 +stalled: 0 +********************************** LSU ********************************* +valid: 0 +PC: 0 +wid: 1 +rd: -1 rs1: -1 rs2: -1 +is_lw: 0 +is_sw: 0 +fetch_stall_cycles: 0 +mem_stall_cycles: 0 +stall_warp: 0 +wspawn: 0 +stalled: 0 +********************************** execute_unit ********************************* +valid: 0 +PC: 0 +wid: 1 +rd: -1 rs1: -1 rs2: -1 +is_lw: 0 +is_sw: 0 +fetch_stall_cycles: 0 +mem_stall_cycles: 0 +stall_warp: 0 +wspawn: 0 +stalled: 0 +********************************** scheduler ********************************* +valid: 0 +PC: 0 +wid: 1 +rd: -1 rs1: -1 rs2: -1 +is_lw: 0 +is_sw: 0 +fetch_stall_cycles: 0 +mem_stall_cycles: 0 +stall_warp: 0 +wspawn: 0 +stalled: 0 +********************************** Decode ********************************* +valid: 1 +PC: 800009b0 +wid: 0 +rd: -1 rs1: 18 rs2: 0 +is_lw: 0 +is_sw: 0 +fetch_stall_cycles: 0 +mem_stall_cycles: 0 +stall_warp: 1 +wspawn: 0 +stalled: 0 +********************************** Fetch ********************************* +valid: 0 +PC: 0 +wid: 1 +rd: -1 rs1: -1 rs2: -1 +is_lw: 0 +is_sw: 0 +fetch_stall_cycles: 0 +mem_stall_cycles: 0 +stall_warp: 0 +wspawn: 0 +stalled: 0 + + + +------------------------------------------------------ +CYCLE: 301 +Stalled Warps: +1 0 0 0 0 0 0 0 + +********************************** Writeback ********************************* +valid: 0 +PC: 0 +wid: 2 +rd: -1 rs1: -1 rs2: -1 +is_lw: 0 +is_sw: 0 +fetch_stall_cycles: 0 +mem_stall_cycles: 0 +stall_warp: 0 +wspawn: 0 +stalled: 0 +********************************** LSU ********************************* +valid: 0 +PC: 0 +wid: 1 +rd: -1 rs1: -1 rs2: -1 +is_lw: 0 +is_sw: 0 +fetch_stall_cycles: 0 +mem_stall_cycles: 0 +stall_warp: 0 +wspawn: 0 +stalled: 0 +********************************** execute_unit ********************************* +valid: 0 +PC: 0 +wid: 1 +rd: -1 rs1: -1 rs2: -1 +is_lw: 0 +is_sw: 0 +fetch_stall_cycles: 0 +mem_stall_cycles: 0 +stall_warp: 0 +wspawn: 0 +stalled: 0 +********************************** scheduler ********************************* +valid: 1 +PC: 800009b0 +wid: 0 +rd: -1 rs1: 18 rs2: 0 +is_lw: 0 +is_sw: 0 +fetch_stall_cycles: 0 +mem_stall_cycles: 0 +stall_warp: 1 +wspawn: 0 +stalled: 0 +********************************** Decode ********************************* +valid: 0 +PC: 0 +wid: 1 +rd: -1 rs1: -1 rs2: -1 +is_lw: 0 +is_sw: 0 +fetch_stall_cycles: 0 +mem_stall_cycles: 0 +stall_warp: 0 +wspawn: 0 +stalled: 0 +********************************** Fetch ********************************* +valid: 0 +PC: 0 +wid: 2 +rd: -1 rs1: -1 rs2: -1 +is_lw: 0 +is_sw: 0 +fetch_stall_cycles: 0 +mem_stall_cycles: 0 +stall_warp: 0 +wspawn: 0 +stalled: 0 + + + +------------------------------------------------------ +CYCLE: 302 +Stalled Warps: +1 0 0 0 0 0 0 0 + +********************************** Writeback ********************************* +valid: 0 +PC: 0 +wid: 3 +rd: -1 rs1: -1 rs2: -1 +is_lw: 0 +is_sw: 0 +fetch_stall_cycles: 0 +mem_stall_cycles: 0 +stall_warp: 0 +wspawn: 0 +stalled: 0 +********************************** LSU ********************************* +valid: 0 +PC: 0 +wid: 1 +rd: -1 rs1: -1 rs2: -1 +is_lw: 0 +is_sw: 0 +fetch_stall_cycles: 0 +mem_stall_cycles: 0 +stall_warp: 0 +wspawn: 0 +stalled: 0 +********************************** execute_unit ********************************* +valid: 1 +PC: 800009b0 +wid: 0 +rd: -1 rs1: 18 rs2: 0 +is_lw: 0 +is_sw: 0 +fetch_stall_cycles: 0 +mem_stall_cycles: 0 +stall_warp: 1 +wspawn: 0 +stalled: 0 +********************************** scheduler ********************************* +valid: 0 +PC: 0 +wid: 1 +rd: -1 rs1: -1 rs2: -1 +is_lw: 0 +is_sw: 0 +fetch_stall_cycles: 0 +mem_stall_cycles: 0 +stall_warp: 0 +wspawn: 0 +stalled: 0 +********************************** Decode ********************************* +valid: 0 +PC: 0 +wid: 2 +rd: -1 rs1: -1 rs2: -1 +is_lw: 0 +is_sw: 0 +fetch_stall_cycles: 0 +mem_stall_cycles: 0 +stall_warp: 0 +wspawn: 0 +stalled: 0 +********************************** Fetch ********************************* +valid: 0 +PC: 0 +wid: 3 +rd: -1 rs1: -1 rs2: -1 +is_lw: 0 +is_sw: 0 +fetch_stall_cycles: 0 +mem_stall_cycles: 0 +stall_warp: 0 +wspawn: 0 +stalled: 0 + + + +------------------------------------------------------ +CYCLE: 303 +Stalled Warps: +1 0 0 0 0 0 0 0 + +********************************** Writeback ********************************* +valid: 1 +PC: 800009b0 +wid: 0 +rd: -1 rs1: 18 rs2: 0 +is_lw: 0 +is_sw: 0 +fetch_stall_cycles: 0 +mem_stall_cycles: 0 +stall_warp: 1 +wspawn: 0 +stalled: 0 +********************************** LSU ********************************* +valid: 0 +PC: 0 +wid: 1 +rd: -1 rs1: -1 rs2: -1 +is_lw: 0 +is_sw: 0 +fetch_stall_cycles: 0 +mem_stall_cycles: 0 +stall_warp: 0 +wspawn: 0 +stalled: 0 +********************************** execute_unit ********************************* +valid: 0 +PC: 0 +wid: 1 +rd: -1 rs1: -1 rs2: -1 +is_lw: 0 +is_sw: 0 +fetch_stall_cycles: 0 +mem_stall_cycles: 0 +stall_warp: 0 +wspawn: 0 +stalled: 0 +********************************** scheduler ********************************* +valid: 0 +PC: 0 +wid: 2 +rd: -1 rs1: -1 rs2: -1 +is_lw: 0 +is_sw: 0 +fetch_stall_cycles: 0 +mem_stall_cycles: 0 +stall_warp: 0 +wspawn: 0 +stalled: 0 +********************************** Decode ********************************* +valid: 0 +PC: 0 +wid: 3 +rd: -1 rs1: -1 rs2: -1 +is_lw: 0 +is_sw: 0 +fetch_stall_cycles: 0 +mem_stall_cycles: 0 +stall_warp: 0 +wspawn: 0 +stalled: 0 +********************************** Fetch ********************************* +valid: 0 +PC: 0 +wid: 4 +rd: -1 rs1: -1 rs2: -1 +is_lw: 0 +is_sw: 0 +fetch_stall_cycles: 0 +mem_stall_cycles: 0 +stall_warp: 0 +wspawn: 0 +stalled: 0 + + + +------------------------------------------------------ +CYCLE: 304 +Stalled Warps: +1 0 0 0 0 0 0 0 + +********************************** Writeback ********************************* +valid: 0 +PC: 0 +wid: 5 +rd: -1 rs1: -1 rs2: -1 +is_lw: 0 +is_sw: 0 +fetch_stall_cycles: 0 +mem_stall_cycles: 0 +stall_warp: 0 +wspawn: 0 +stalled: 0 +********************************** LSU ********************************* +valid: 0 +PC: 0 +wid: 1 +rd: -1 rs1: -1 rs2: -1 +is_lw: 0 +is_sw: 0 +fetch_stall_cycles: 0 +mem_stall_cycles: 0 +stall_warp: 0 +wspawn: 0 +stalled: 0 +********************************** execute_unit ********************************* +valid: 0 +PC: 0 +wid: 2 +rd: -1 rs1: -1 rs2: -1 +is_lw: 0 +is_sw: 0 +fetch_stall_cycles: 0 +mem_stall_cycles: 0 +stall_warp: 0 +wspawn: 0 +stalled: 0 +********************************** scheduler ********************************* +valid: 0 +PC: 0 +wid: 3 +rd: -1 rs1: -1 rs2: -1 +is_lw: 0 +is_sw: 0 +fetch_stall_cycles: 0 +mem_stall_cycles: 0 +stall_warp: 0 +wspawn: 0 +stalled: 0 +********************************** Decode ********************************* +valid: 0 +PC: 0 +wid: 4 +rd: -1 rs1: -1 rs2: -1 +is_lw: 0 +is_sw: 0 +fetch_stall_cycles: 0 +mem_stall_cycles: 0 +stall_warp: 0 +wspawn: 0 +stalled: 0 +********************************** Fetch ********************************* +valid: 0 +PC: 0 +wid: 5 +rd: -1 rs1: -1 rs2: -1 +is_lw: 0 +is_sw: 0 +fetch_stall_cycles: 0 +mem_stall_cycles: 0 +stall_warp: 0 +wspawn: 0 +stalled: 0 +Warp ID 0 is running + + + +------------------------------------------------------ +CYCLE: 305 +Stalled Warps: +0 0 0 0 0 0 0 0 + +********************************** Writeback ********************************* +valid: 0 +PC: 0 +wid: 0 +rd: -1 rs1: -1 rs2: -1 +is_lw: 0 +is_sw: 0 +fetch_stall_cycles: 0 +mem_stall_cycles: 0 +stall_warp: 0 +wspawn: 0 +stalled: 0 +********************************** LSU ********************************* +valid: 0 +PC: 0 +wid: 1 +rd: -1 rs1: -1 rs2: -1 +is_lw: 0 +is_sw: 0 +fetch_stall_cycles: 0 +mem_stall_cycles: 0 +stall_warp: 0 +wspawn: 0 +stalled: 0 +********************************** execute_unit ********************************* +valid: 0 +PC: 0 +wid: 3 +rd: -1 rs1: -1 rs2: -1 +is_lw: 0 +is_sw: 0 +fetch_stall_cycles: 0 +mem_stall_cycles: 0 +stall_warp: 0 +wspawn: 0 +stalled: 0 +********************************** scheduler ********************************* +valid: 0 +PC: 0 +wid: 4 +rd: -1 rs1: -1 rs2: -1 +is_lw: 0 +is_sw: 0 +fetch_stall_cycles: 0 +mem_stall_cycles: 0 +stall_warp: 0 +wspawn: 0 +stalled: 0 +********************************** Decode ********************************* +valid: 0 +PC: 0 +wid: 5 +rd: -1 rs1: -1 rs2: -1 +is_lw: 0 +is_sw: 0 +fetch_stall_cycles: 0 +mem_stall_cycles: 0 +stall_warp: 0 +wspawn: 0 +stalled: 0 +DEBUG ../core.cpp:386: Core step stepping warp 0[1] +DEBUG ../core.cpp:683: in step pc=0x800009d0 +help: in PC: 800009d0 +CUrrent CODE: 80001437 +DEBUG ../core.cpp:703: Fetched at 0x800009d0 +DEBUG ../core.cpp:704: 0x800009d0: lui; +DEBUG ../instruction.cpp:350: Begin instruction execute. +DEBUG ../instruction.cpp:2117: End instruction execute. +DEBUG ../core.cpp:717: Register state: + %r 0: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r 1: 80000040 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r 2: 6fffeff0 6fffec04 6fffe808 6fffe40c 00000000 00000000 00000000 00000000 (0) + %r 3: 80001808 80001808 80001808 80001808 00000000 00000000 00000000 00000000 (0) + %r 4: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r 5: 80000a6c 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r 6: 0000000f 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r 7: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r 8: 80001000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r 9: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r10: 00000000 00000001 00000001 00000001 00000000 00000000 00000000 00000000 (0) + %r11: 80000924 00000400 00000800 00000c00 00000000 00000000 00000000 00000000 (0) + %r12: 00000000 00000004 00000008 0000000c 00000000 00000000 00000000 00000000 (0) + %r13: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r14: 00000001 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r15: 80001000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r16: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r17: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r18: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r19: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r20: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r21: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r22: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r23: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r24: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r25: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r26: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r27: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r28: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r29: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r30: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r31: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) +DEBUG ../core.cpp:726: Thread mask: + 1 0 0 0 0 0 0 0 + + +DEBUG ../core.cpp:388: Now 1 active threads in 0 +********************************** Fetch ********************************* +valid: 1 +PC: 800009d0 +wid: 0 +rd: 8 rs1: -1 rs2: -1 +is_lw: 0 +is_sw: 0 +fetch_stall_cycles: 3 +mem_stall_cycles: 0 +stall_warp: 0 +wspawn: 0 +stalled: 0 + + + +------------------------------------------------------ +CYCLE: 306 +Stalled Warps: +0 0 0 0 0 0 0 0 + +********************************** Writeback ********************************* +valid: 0 +PC: 0 +wid: 0 +rd: -1 rs1: -1 rs2: -1 +is_lw: 0 +is_sw: 0 +fetch_stall_cycles: 0 +mem_stall_cycles: 0 +stall_warp: 0 +wspawn: 0 +stalled: 0 +********************************** LSU ********************************* +valid: 0 +PC: 0 +wid: 1 +rd: -1 rs1: -1 rs2: -1 +is_lw: 0 +is_sw: 0 +fetch_stall_cycles: 0 +mem_stall_cycles: 0 +stall_warp: 0 +wspawn: 0 +stalled: 0 +********************************** execute_unit ********************************* +valid: 0 +PC: 0 +wid: 4 +rd: -1 rs1: -1 rs2: -1 +is_lw: 0 +is_sw: 0 +fetch_stall_cycles: 0 +mem_stall_cycles: 0 +stall_warp: 0 +wspawn: 0 +stalled: 0 +********************************** scheduler ********************************* +valid: 0 +PC: 0 +wid: 5 +rd: -1 rs1: -1 rs2: -1 +is_lw: 0 +is_sw: 0 +fetch_stall_cycles: 0 +mem_stall_cycles: 0 +stall_warp: 0 +wspawn: 0 +stalled: 0 +********************************** Decode ********************************* +valid: 0 +PC: 0 +wid: 0 +rd: -1 rs1: -1 rs2: -1 +is_lw: 0 +is_sw: 0 +fetch_stall_cycles: 0 +mem_stall_cycles: 0 +stall_warp: 0 +wspawn: 0 +stalled: 0 +********************************** Fetch ********************************* +valid: 1 +PC: 800009d0 +wid: 0 +rd: 8 rs1: -1 rs2: -1 +is_lw: 0 +is_sw: 0 +fetch_stall_cycles: 2 +mem_stall_cycles: 0 +stall_warp: 0 +wspawn: 0 +stalled: 0 + + + +------------------------------------------------------ +CYCLE: 307 +Stalled Warps: +0 0 0 0 0 0 0 0 + +********************************** Writeback ********************************* +valid: 0 +PC: 0 +wid: 0 +rd: -1 rs1: -1 rs2: -1 +is_lw: 0 +is_sw: 0 +fetch_stall_cycles: 0 +mem_stall_cycles: 0 +stall_warp: 0 +wspawn: 0 +stalled: 0 +********************************** LSU ********************************* +valid: 0 +PC: 0 +wid: 1 +rd: -1 rs1: -1 rs2: -1 +is_lw: 0 +is_sw: 0 +fetch_stall_cycles: 0 +mem_stall_cycles: 0 +stall_warp: 0 +wspawn: 0 +stalled: 0 +********************************** execute_unit ********************************* +valid: 0 +PC: 0 +wid: 5 +rd: -1 rs1: -1 rs2: -1 +is_lw: 0 +is_sw: 0 +fetch_stall_cycles: 0 +mem_stall_cycles: 0 +stall_warp: 0 +wspawn: 0 +stalled: 0 +********************************** scheduler ********************************* +valid: 0 +PC: 0 +wid: 0 +rd: -1 rs1: -1 rs2: -1 +is_lw: 0 +is_sw: 0 +fetch_stall_cycles: 0 +mem_stall_cycles: 0 +stall_warp: 0 +wspawn: 0 +stalled: 0 +********************************** Decode ********************************* +valid: 0 +PC: 0 +wid: 0 +rd: -1 rs1: -1 rs2: -1 +is_lw: 0 +is_sw: 0 +fetch_stall_cycles: 0 +mem_stall_cycles: 0 +stall_warp: 0 +wspawn: 0 +stalled: 0 +********************************** Fetch ********************************* +valid: 1 +PC: 800009d0 +wid: 0 +rd: 8 rs1: -1 rs2: -1 +is_lw: 0 +is_sw: 0 +fetch_stall_cycles: 1 +mem_stall_cycles: 0 +stall_warp: 0 +wspawn: 0 +stalled: 0 + + + +------------------------------------------------------ +CYCLE: 308 +Stalled Warps: +0 0 0 0 0 0 0 0 + +********************************** Writeback ********************************* +valid: 0 +PC: 0 +wid: 0 +rd: -1 rs1: -1 rs2: -1 +is_lw: 0 +is_sw: 0 +fetch_stall_cycles: 0 +mem_stall_cycles: 0 +stall_warp: 0 +wspawn: 0 +stalled: 0 +********************************** LSU ********************************* +valid: 0 +PC: 0 +wid: 1 +rd: -1 rs1: -1 rs2: -1 +is_lw: 0 +is_sw: 0 +fetch_stall_cycles: 0 +mem_stall_cycles: 0 +stall_warp: 0 +wspawn: 0 +stalled: 0 +********************************** execute_unit ********************************* +valid: 0 +PC: 0 +wid: 0 +rd: -1 rs1: -1 rs2: -1 +is_lw: 0 +is_sw: 0 +fetch_stall_cycles: 0 +mem_stall_cycles: 0 +stall_warp: 0 +wspawn: 0 +stalled: 0 +********************************** scheduler ********************************* +valid: 0 +PC: 0 +wid: 0 +rd: -1 rs1: -1 rs2: -1 +is_lw: 0 +is_sw: 0 +fetch_stall_cycles: 0 +mem_stall_cycles: 0 +stall_warp: 0 +wspawn: 0 +stalled: 0 +********************************** Decode ********************************* +valid: 0 +PC: 0 +wid: 0 +rd: -1 rs1: -1 rs2: -1 +is_lw: 0 +is_sw: 0 +fetch_stall_cycles: 0 +mem_stall_cycles: 0 +stall_warp: 0 +wspawn: 0 +stalled: 0 +********************************** Fetch ********************************* +valid: 1 +PC: 800009d0 +wid: 0 +rd: 8 rs1: -1 rs2: -1 +is_lw: 0 +is_sw: 0 +fetch_stall_cycles: 0 +mem_stall_cycles: 0 +stall_warp: 0 +wspawn: 0 +stalled: 0 + + + +------------------------------------------------------ +CYCLE: 309 +Stalled Warps: +0 0 0 0 0 0 0 0 + +********************************** Writeback ********************************* +valid: 0 +PC: 0 +wid: 0 +rd: -1 rs1: -1 rs2: -1 +is_lw: 0 +is_sw: 0 +fetch_stall_cycles: 0 +mem_stall_cycles: 0 +stall_warp: 0 +wspawn: 0 +stalled: 0 +********************************** LSU ********************************* +valid: 0 +PC: 0 +wid: 1 +rd: -1 rs1: -1 rs2: -1 +is_lw: 0 +is_sw: 0 +fetch_stall_cycles: 0 +mem_stall_cycles: 0 +stall_warp: 0 +wspawn: 0 +stalled: 0 +********************************** execute_unit ********************************* +valid: 0 +PC: 0 +wid: 0 +rd: -1 rs1: -1 rs2: -1 +is_lw: 0 +is_sw: 0 +fetch_stall_cycles: 0 +mem_stall_cycles: 0 +stall_warp: 0 +wspawn: 0 +stalled: 0 +********************************** scheduler ********************************* +valid: 0 +PC: 0 +wid: 0 +rd: -1 rs1: -1 rs2: -1 +is_lw: 0 +is_sw: 0 +fetch_stall_cycles: 0 +mem_stall_cycles: 0 +stall_warp: 0 +wspawn: 0 +stalled: 0 +********************************** Decode ********************************* +valid: 1 +PC: 800009d0 +wid: 0 +rd: 8 rs1: -1 rs2: -1 +is_lw: 0 +is_sw: 0 +fetch_stall_cycles: 0 +mem_stall_cycles: 0 +stall_warp: 0 +wspawn: 0 +stalled: 0 +DEBUG ../core.cpp:386: Core step stepping warp 0[1] +DEBUG ../core.cpp:683: in step pc=0x800009d4 +help: in PC: 800009d4 +CUrrent CODE: 80001937 +DEBUG ../core.cpp:703: Fetched at 0x800009d4 +DEBUG ../core.cpp:704: 0x800009d4: lui; +DEBUG ../instruction.cpp:350: Begin instruction execute. +DEBUG ../instruction.cpp:2117: End instruction execute. +DEBUG ../core.cpp:717: Register state: + %r 0: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r 1: 80000040 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r 2: 6fffeff0 6fffec04 6fffe808 6fffe40c 00000000 00000000 00000000 00000000 (0) + %r 3: 80001808 80001808 80001808 80001808 00000000 00000000 00000000 00000000 (0) + %r 4: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r 5: 80000a6c 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r 6: 0000000f 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r 7: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r 8: 80001000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r 9: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r10: 00000000 00000001 00000001 00000001 00000000 00000000 00000000 00000000 (0) + %r11: 80000924 00000400 00000800 00000c00 00000000 00000000 00000000 00000000 (0) + %r12: 00000000 00000004 00000008 0000000c 00000000 00000000 00000000 00000000 (0) + %r13: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r14: 00000001 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r15: 80001000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r16: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r17: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r18: 80001000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r19: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r20: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r21: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r22: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r23: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r24: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r25: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r26: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r27: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r28: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r29: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r30: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r31: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) +DEBUG ../core.cpp:726: Thread mask: + 1 0 0 0 0 0 0 0 + + +DEBUG ../core.cpp:388: Now 1 active threads in 0 +********************************** Fetch ********************************* +valid: 1 +PC: 800009d4 +wid: 0 +rd: 18 rs1: -1 rs2: -1 +is_lw: 0 +is_sw: 0 +fetch_stall_cycles: 0 +mem_stall_cycles: 0 +stall_warp: 0 +wspawn: 0 +stalled: 0 + + + +------------------------------------------------------ +CYCLE: 310 +Stalled Warps: +0 0 0 0 0 0 0 0 + +********************************** Writeback ********************************* +valid: 0 +PC: 0 +wid: 0 +rd: -1 rs1: -1 rs2: -1 +is_lw: 0 +is_sw: 0 +fetch_stall_cycles: 0 +mem_stall_cycles: 0 +stall_warp: 0 +wspawn: 0 +stalled: 0 +********************************** LSU ********************************* +valid: 0 +PC: 0 +wid: 1 +rd: -1 rs1: -1 rs2: -1 +is_lw: 0 +is_sw: 0 +fetch_stall_cycles: 0 +mem_stall_cycles: 0 +stall_warp: 0 +wspawn: 0 +stalled: 0 +********************************** execute_unit ********************************* +valid: 0 +PC: 0 +wid: 0 +rd: -1 rs1: -1 rs2: -1 +is_lw: 0 +is_sw: 0 +fetch_stall_cycles: 0 +mem_stall_cycles: 0 +stall_warp: 0 +wspawn: 0 +stalled: 0 +********************************** scheduler ********************************* +valid: 1 +PC: 800009d0 +wid: 0 +rd: 8 rs1: -1 rs2: -1 +is_lw: 0 +is_sw: 0 +fetch_stall_cycles: 0 +mem_stall_cycles: 0 +stall_warp: 0 +wspawn: 0 +stalled: 0 +********************************** Decode ********************************* +valid: 1 +PC: 800009d4 +wid: 0 +rd: 18 rs1: -1 rs2: -1 +is_lw: 0 +is_sw: 0 +fetch_stall_cycles: 0 +mem_stall_cycles: 0 +stall_warp: 0 +wspawn: 0 +stalled: 0 +DEBUG ../core.cpp:386: Core step stepping warp 0[1] +DEBUG ../core.cpp:683: in step pc=0x800009d8 +help: in PC: 800009d8 +CUrrent CODE: 40793 +DEBUG ../core.cpp:703: Fetched at 0x800009d8 +DEBUG ../core.cpp:704: 0x800009d8: i_type; +DEBUG ../instruction.cpp:350: Begin instruction execute. +DEBUG ../instruction.cpp:2117: End instruction execute. +DEBUG ../core.cpp:717: Register state: + %r 0: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r 1: 80000040 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r 2: 6fffeff0 6fffec04 6fffe808 6fffe40c 00000000 00000000 00000000 00000000 (0) + %r 3: 80001808 80001808 80001808 80001808 00000000 00000000 00000000 00000000 (0) + %r 4: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r 5: 80000a6c 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r 6: 0000000f 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r 7: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r 8: 80001000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r 9: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r10: 00000000 00000001 00000001 00000001 00000000 00000000 00000000 00000000 (0) + %r11: 80000924 00000400 00000800 00000c00 00000000 00000000 00000000 00000000 (0) + %r12: 00000000 00000004 00000008 0000000c 00000000 00000000 00000000 00000000 (0) + %r13: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r14: 00000001 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r15: 80001000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r16: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r17: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r18: 80001000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r19: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r20: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r21: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r22: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r23: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r24: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r25: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r26: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r27: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r28: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r29: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r30: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r31: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) +DEBUG ../core.cpp:726: Thread mask: + 1 0 0 0 0 0 0 0 + + +DEBUG ../core.cpp:388: Now 1 active threads in 0 +********************************** Fetch ********************************* +valid: 1 +PC: 800009d8 +wid: 0 +rd: 15 rs1: 8 rs2: -1 +is_lw: 0 +is_sw: 0 +fetch_stall_cycles: 0 +mem_stall_cycles: 0 +stall_warp: 0 +wspawn: 0 +stalled: 0 + + + +------------------------------------------------------ +CYCLE: 311 +Stalled Warps: +0 0 0 0 0 0 0 0 + +********************************** Writeback ********************************* +valid: 0 +PC: 0 +wid: 0 +rd: -1 rs1: -1 rs2: -1 +is_lw: 0 +is_sw: 0 +fetch_stall_cycles: 0 +mem_stall_cycles: 0 +stall_warp: 0 +wspawn: 0 +stalled: 0 +********************************** LSU ********************************* +valid: 0 +PC: 0 +wid: 1 +rd: -1 rs1: -1 rs2: -1 +is_lw: 0 +is_sw: 0 +fetch_stall_cycles: 0 +mem_stall_cycles: 0 +stall_warp: 0 +wspawn: 0 +stalled: 0 +********************************** execute_unit ********************************* +valid: 1 +PC: 800009d0 +wid: 0 +rd: 8 rs1: -1 rs2: -1 +is_lw: 0 +is_sw: 0 +fetch_stall_cycles: 0 +mem_stall_cycles: 0 +stall_warp: 0 +wspawn: 0 +stalled: 0 +********************************** scheduler ********************************* +valid: 1 +PC: 800009d4 +wid: 0 +rd: 18 rs1: -1 rs2: -1 +is_lw: 0 +is_sw: 0 +fetch_stall_cycles: 0 +mem_stall_cycles: 0 +stall_warp: 0 +wspawn: 0 +stalled: 0 +********************************** Decode ********************************* +valid: 1 +PC: 800009d8 +wid: 0 +rd: 15 rs1: 8 rs2: -1 +is_lw: 0 +is_sw: 0 +fetch_stall_cycles: 0 +mem_stall_cycles: 0 +stall_warp: 0 +wspawn: 0 +stalled: 0 +DEBUG ../core.cpp:386: Core step stepping warp 0[1] +DEBUG ../core.cpp:683: in step pc=0x800009dc +help: in PC: 800009dc +CUrrent CODE: 490913 +DEBUG ../core.cpp:703: Fetched at 0x800009dc +DEBUG ../core.cpp:704: 0x800009dc: i_type; +DEBUG ../instruction.cpp:350: Begin instruction execute. +DEBUG ../instruction.cpp:2117: End instruction execute. +DEBUG ../core.cpp:717: Register state: + %r 0: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r 1: 80000040 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r 2: 6fffeff0 6fffec04 6fffe808 6fffe40c 00000000 00000000 00000000 00000000 (0) + %r 3: 80001808 80001808 80001808 80001808 00000000 00000000 00000000 00000000 (0) + %r 4: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r 5: 80000a6c 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r 6: 0000000f 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r 7: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r 8: 80001000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r 9: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r10: 00000000 00000001 00000001 00000001 00000000 00000000 00000000 00000000 (0) + %r11: 80000924 00000400 00000800 00000c00 00000000 00000000 00000000 00000000 (0) + %r12: 00000000 00000004 00000008 0000000c 00000000 00000000 00000000 00000000 (0) + %r13: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r14: 00000001 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r15: 80001000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r16: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r17: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r18: 80001004 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r19: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r20: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r21: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r22: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r23: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r24: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r25: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r26: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r27: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r28: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r29: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r30: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r31: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) +DEBUG ../core.cpp:726: Thread mask: + 1 0 0 0 0 0 0 0 + + +DEBUG ../core.cpp:388: Now 1 active threads in 0 +********************************** Fetch ********************************* +valid: 1 +PC: 800009dc +wid: 0 +rd: 18 rs1: 18 rs2: -1 +is_lw: 0 +is_sw: 0 +fetch_stall_cycles: 0 +mem_stall_cycles: 0 +stall_warp: 0 +wspawn: 0 +stalled: 0 + + + +------------------------------------------------------ +CYCLE: 312 +Stalled Warps: +0 0 0 0 0 0 0 0 + +********************************** Writeback ********************************* +valid: 1 +PC: 800009d0 +wid: 0 +rd: 8 rs1: -1 rs2: -1 +is_lw: 0 +is_sw: 0 +fetch_stall_cycles: 0 +mem_stall_cycles: 0 +stall_warp: 0 +wspawn: 0 +stalled: 0 +********************************** LSU ********************************* +valid: 0 +PC: 0 +wid: 1 +rd: -1 rs1: -1 rs2: -1 +is_lw: 0 +is_sw: 0 +fetch_stall_cycles: 0 +mem_stall_cycles: 0 +stall_warp: 0 +wspawn: 0 +stalled: 0 +********************************** execute_unit ********************************* +valid: 1 +PC: 800009d4 +wid: 0 +rd: 18 rs1: -1 rs2: -1 +is_lw: 0 +is_sw: 0 +fetch_stall_cycles: 0 +mem_stall_cycles: 0 +stall_warp: 0 +wspawn: 0 +stalled: 0 +********************************** scheduler ********************************* +valid: 1 +PC: 800009d8 +wid: 0 +rd: 15 rs1: 8 rs2: -1 +is_lw: 0 +is_sw: 0 +fetch_stall_cycles: 0 +mem_stall_cycles: 0 +stall_warp: 0 +wspawn: 0 +stalled: 0 +********************************** Decode ********************************* +valid: 1 +PC: 800009dc +wid: 0 +rd: 18 rs1: 18 rs2: -1 +is_lw: 0 +is_sw: 0 +fetch_stall_cycles: 0 +mem_stall_cycles: 0 +stall_warp: 0 +wspawn: 0 +stalled: 0 +DEBUG ../core.cpp:386: Core step stepping warp 0[1] +DEBUG ../core.cpp:683: in step pc=0x800009e0 +help: in PC: 800009e0 +CUrrent CODE: 40f90933 +DEBUG ../core.cpp:703: Fetched at 0x800009e0 +DEBUG ../core.cpp:704: 0x800009e0: r_type; +DEBUG ../instruction.cpp:350: Begin instruction execute. +DEBUG ../instruction.cpp:2117: End instruction execute. +DEBUG ../core.cpp:717: Register state: + %r 0: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r 1: 80000040 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r 2: 6fffeff0 6fffec04 6fffe808 6fffe40c 00000000 00000000 00000000 00000000 (0) + %r 3: 80001808 80001808 80001808 80001808 00000000 00000000 00000000 00000000 (0) + %r 4: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r 5: 80000a6c 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r 6: 0000000f 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r 7: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r 8: 80001000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r 9: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r10: 00000000 00000001 00000001 00000001 00000000 00000000 00000000 00000000 (0) + %r11: 80000924 00000400 00000800 00000c00 00000000 00000000 00000000 00000000 (0) + %r12: 00000000 00000004 00000008 0000000c 00000000 00000000 00000000 00000000 (0) + %r13: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r14: 00000001 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r15: 80001000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r16: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r17: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r18: 00000004 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r19: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r20: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r21: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r22: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r23: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r24: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r25: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r26: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r27: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r28: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r29: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r30: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r31: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) +DEBUG ../core.cpp:726: Thread mask: + 1 0 0 0 0 0 0 0 + + +DEBUG ../core.cpp:388: Now 1 active threads in 0 +********************************** Fetch ********************************* +valid: 1 +PC: 800009e0 +wid: 0 +rd: 18 rs1: 18 rs2: 15 +is_lw: 0 +is_sw: 0 +fetch_stall_cycles: 3 +mem_stall_cycles: 0 +stall_warp: 0 +wspawn: 0 +stalled: 0 + + + +------------------------------------------------------ +CYCLE: 313 +Stalled Warps: +0 0 0 0 0 0 0 0 + +********************************** Writeback ********************************* +valid: 1 +PC: 800009d4 +wid: 0 +rd: 18 rs1: -1 rs2: -1 +is_lw: 0 +is_sw: 0 +fetch_stall_cycles: 0 +mem_stall_cycles: 0 +stall_warp: 0 +wspawn: 0 +stalled: 0 +********************************** LSU ********************************* +valid: 0 +PC: 0 +wid: 1 +rd: -1 rs1: -1 rs2: -1 +is_lw: 0 +is_sw: 0 +fetch_stall_cycles: 0 +mem_stall_cycles: 0 +stall_warp: 0 +wspawn: 0 +stalled: 0 +********************************** execute_unit ********************************* +valid: 1 +PC: 800009d8 +wid: 0 +rd: 15 rs1: 8 rs2: -1 +is_lw: 0 +is_sw: 0 +fetch_stall_cycles: 0 +mem_stall_cycles: 0 +stall_warp: 0 +wspawn: 0 +stalled: 0 +********************************** scheduler ********************************* +valid: 1 +PC: 800009dc +wid: 0 +rd: 18 rs1: 18 rs2: -1 +is_lw: 0 +is_sw: 0 +fetch_stall_cycles: 0 +mem_stall_cycles: 0 +stall_warp: 0 +wspawn: 0 +stalled: 0 +********************************** Decode ********************************* +valid: 0 +PC: 0 +wid: 0 +rd: -1 rs1: -1 rs2: -1 +is_lw: 0 +is_sw: 0 +fetch_stall_cycles: 0 +mem_stall_cycles: 0 +stall_warp: 0 +wspawn: 0 +stalled: 0 +********************************** Fetch ********************************* +valid: 1 +PC: 800009e0 +wid: 0 +rd: 18 rs1: 18 rs2: 15 +is_lw: 0 +is_sw: 0 +fetch_stall_cycles: 2 +mem_stall_cycles: 0 +stall_warp: 0 +wspawn: 0 +stalled: 0 + + + +------------------------------------------------------ +CYCLE: 314 +Stalled Warps: +0 0 0 0 0 0 0 0 + +********************************** Writeback ********************************* +valid: 1 +PC: 800009d8 +wid: 0 +rd: 15 rs1: 8 rs2: -1 +is_lw: 0 +is_sw: 0 +fetch_stall_cycles: 0 +mem_stall_cycles: 0 +stall_warp: 0 +wspawn: 0 +stalled: 0 +********************************** LSU ********************************* +valid: 0 +PC: 0 +wid: 1 +rd: -1 rs1: -1 rs2: -1 +is_lw: 0 +is_sw: 0 +fetch_stall_cycles: 0 +mem_stall_cycles: 0 +stall_warp: 0 +wspawn: 0 +stalled: 0 +********************************** execute_unit ********************************* +valid: 1 +PC: 800009dc +wid: 0 +rd: 18 rs1: 18 rs2: -1 +is_lw: 0 +is_sw: 0 +fetch_stall_cycles: 0 +mem_stall_cycles: 0 +stall_warp: 0 +wspawn: 0 +stalled: 0 +********************************** scheduler ********************************* +valid: 0 +PC: 0 +wid: 0 +rd: -1 rs1: -1 rs2: -1 +is_lw: 0 +is_sw: 0 +fetch_stall_cycles: 0 +mem_stall_cycles: 0 +stall_warp: 0 +wspawn: 0 +stalled: 0 +********************************** Decode ********************************* +valid: 0 +PC: 0 +wid: 0 +rd: -1 rs1: -1 rs2: -1 +is_lw: 0 +is_sw: 0 +fetch_stall_cycles: 0 +mem_stall_cycles: 0 +stall_warp: 0 +wspawn: 0 +stalled: 0 +********************************** Fetch ********************************* +valid: 1 +PC: 800009e0 +wid: 0 +rd: 18 rs1: 18 rs2: 15 +is_lw: 0 +is_sw: 0 +fetch_stall_cycles: 1 +mem_stall_cycles: 0 +stall_warp: 0 +wspawn: 0 +stalled: 0 + + + +------------------------------------------------------ +CYCLE: 315 +Stalled Warps: +0 0 0 0 0 0 0 0 + +********************************** Writeback ********************************* +valid: 1 +PC: 800009dc +wid: 0 +rd: 18 rs1: 18 rs2: -1 +is_lw: 0 +is_sw: 0 +fetch_stall_cycles: 0 +mem_stall_cycles: 0 +stall_warp: 0 +wspawn: 0 +stalled: 0 +********************************** LSU ********************************* +valid: 0 +PC: 0 +wid: 1 +rd: -1 rs1: -1 rs2: -1 +is_lw: 0 +is_sw: 0 +fetch_stall_cycles: 0 +mem_stall_cycles: 0 +stall_warp: 0 +wspawn: 0 +stalled: 0 +********************************** execute_unit ********************************* +valid: 0 +PC: 0 +wid: 0 +rd: -1 rs1: -1 rs2: -1 +is_lw: 0 +is_sw: 0 +fetch_stall_cycles: 0 +mem_stall_cycles: 0 +stall_warp: 0 +wspawn: 0 +stalled: 0 +********************************** scheduler ********************************* +valid: 0 +PC: 0 +wid: 0 +rd: -1 rs1: -1 rs2: -1 +is_lw: 0 +is_sw: 0 +fetch_stall_cycles: 0 +mem_stall_cycles: 0 +stall_warp: 0 +wspawn: 0 +stalled: 0 +********************************** Decode ********************************* +valid: 0 +PC: 0 +wid: 0 +rd: -1 rs1: -1 rs2: -1 +is_lw: 0 +is_sw: 0 +fetch_stall_cycles: 0 +mem_stall_cycles: 0 +stall_warp: 0 +wspawn: 0 +stalled: 0 +********************************** Fetch ********************************* +valid: 1 +PC: 800009e0 +wid: 0 +rd: 18 rs1: 18 rs2: 15 +is_lw: 0 +is_sw: 0 +fetch_stall_cycles: 0 +mem_stall_cycles: 0 +stall_warp: 0 +wspawn: 0 +stalled: 0 + + + +------------------------------------------------------ +CYCLE: 316 +Stalled Warps: +0 0 0 0 0 0 0 0 + +********************************** Writeback ********************************* +valid: 0 +PC: 0 +wid: 0 +rd: -1 rs1: -1 rs2: -1 +is_lw: 0 +is_sw: 0 +fetch_stall_cycles: 0 +mem_stall_cycles: 0 +stall_warp: 0 +wspawn: 0 +stalled: 0 +********************************** LSU ********************************* +valid: 0 +PC: 0 +wid: 1 +rd: -1 rs1: -1 rs2: -1 +is_lw: 0 +is_sw: 0 +fetch_stall_cycles: 0 +mem_stall_cycles: 0 +stall_warp: 0 +wspawn: 0 +stalled: 0 +********************************** execute_unit ********************************* +valid: 0 +PC: 0 +wid: 0 +rd: -1 rs1: -1 rs2: -1 +is_lw: 0 +is_sw: 0 +fetch_stall_cycles: 0 +mem_stall_cycles: 0 +stall_warp: 0 +wspawn: 0 +stalled: 0 +********************************** scheduler ********************************* +valid: 0 +PC: 0 +wid: 0 +rd: -1 rs1: -1 rs2: -1 +is_lw: 0 +is_sw: 0 +fetch_stall_cycles: 0 +mem_stall_cycles: 0 +stall_warp: 0 +wspawn: 0 +stalled: 0 +********************************** Decode ********************************* +valid: 1 +PC: 800009e0 +wid: 0 +rd: 18 rs1: 18 rs2: 15 +is_lw: 0 +is_sw: 0 +fetch_stall_cycles: 0 +mem_stall_cycles: 0 +stall_warp: 0 +wspawn: 0 +stalled: 0 +DEBUG ../core.cpp:386: Core step stepping warp 0[1] +DEBUG ../core.cpp:683: in step pc=0x800009e4 +help: in PC: 800009e4 +CUrrent CODE: 40295913 +DEBUG ../core.cpp:703: Fetched at 0x800009e4 +DEBUG ../core.cpp:704: 0x800009e4: i_type; +DEBUG ../instruction.cpp:350: Begin instruction execute. +DEBUG ../instruction.cpp:2117: End instruction execute. +DEBUG ../core.cpp:717: Register state: + %r 0: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r 1: 80000040 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r 2: 6fffeff0 6fffec04 6fffe808 6fffe40c 00000000 00000000 00000000 00000000 (0) + %r 3: 80001808 80001808 80001808 80001808 00000000 00000000 00000000 00000000 (0) + %r 4: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r 5: 80000a6c 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r 6: 0000000f 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r 7: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r 8: 80001000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r 9: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r10: 00000000 00000001 00000001 00000001 00000000 00000000 00000000 00000000 (0) + %r11: 80000924 00000400 00000800 00000c00 00000000 00000000 00000000 00000000 (0) + %r12: 00000000 00000004 00000008 0000000c 00000000 00000000 00000000 00000000 (0) + %r13: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r14: 00000001 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r15: 80001000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r16: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r17: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r18: 00000001 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r19: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r20: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r21: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r22: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r23: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r24: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r25: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r26: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r27: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r28: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r29: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r30: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r31: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) +DEBUG ../core.cpp:726: Thread mask: + 1 0 0 0 0 0 0 0 + + +DEBUG ../core.cpp:388: Now 1 active threads in 0 +********************************** Fetch ********************************* +valid: 1 +PC: 800009e4 +wid: 0 +rd: 18 rs1: 18 rs2: -1 +is_lw: 0 +is_sw: 0 +fetch_stall_cycles: 0 +mem_stall_cycles: 0 +stall_warp: 0 +wspawn: 0 +stalled: 0 + + + +------------------------------------------------------ +CYCLE: 317 +Stalled Warps: +0 0 0 0 0 0 0 0 + +********************************** Writeback ********************************* +valid: 0 +PC: 0 +wid: 0 +rd: -1 rs1: -1 rs2: -1 +is_lw: 0 +is_sw: 0 +fetch_stall_cycles: 0 +mem_stall_cycles: 0 +stall_warp: 0 +wspawn: 0 +stalled: 0 +********************************** LSU ********************************* +valid: 0 +PC: 0 +wid: 1 +rd: -1 rs1: -1 rs2: -1 +is_lw: 0 +is_sw: 0 +fetch_stall_cycles: 0 +mem_stall_cycles: 0 +stall_warp: 0 +wspawn: 0 +stalled: 0 +********************************** execute_unit ********************************* +valid: 0 +PC: 0 +wid: 0 +rd: -1 rs1: -1 rs2: -1 +is_lw: 0 +is_sw: 0 +fetch_stall_cycles: 0 +mem_stall_cycles: 0 +stall_warp: 0 +wspawn: 0 +stalled: 0 +********************************** scheduler ********************************* +valid: 1 +PC: 800009e0 +wid: 0 +rd: 18 rs1: 18 rs2: 15 +is_lw: 0 +is_sw: 0 +fetch_stall_cycles: 0 +mem_stall_cycles: 0 +stall_warp: 0 +wspawn: 0 +stalled: 0 +********************************** Decode ********************************* +valid: 1 +PC: 800009e4 +wid: 0 +rd: 18 rs1: 18 rs2: -1 +is_lw: 0 +is_sw: 0 +fetch_stall_cycles: 0 +mem_stall_cycles: 0 +stall_warp: 0 +wspawn: 0 +stalled: 0 +DEBUG ../core.cpp:386: Core step stepping warp 0[1] +DEBUG ../core.cpp:683: in step pc=0x800009e8 +help: in PC: 800009e8 +CUrrent CODE: 2090063 +DEBUG ../core.cpp:703: Fetched at 0x800009e8 +DEBUG ../core.cpp:704: 0x800009e8: branch; +DEBUG ../instruction.cpp:350: Begin instruction execute. +DEBUG ../instruction.cpp:2117: End instruction execute. +DEBUG ../core.cpp:717: Register state: + %r 0: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r 1: 80000040 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r 2: 6fffeff0 6fffec04 6fffe808 6fffe40c 00000000 00000000 00000000 00000000 (0) + %r 3: 80001808 80001808 80001808 80001808 00000000 00000000 00000000 00000000 (0) + %r 4: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r 5: 80000a6c 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r 6: 0000000f 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r 7: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r 8: 80001000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r 9: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r10: 00000000 00000001 00000001 00000001 00000000 00000000 00000000 00000000 (0) + %r11: 80000924 00000400 00000800 00000c00 00000000 00000000 00000000 00000000 (0) + %r12: 00000000 00000004 00000008 0000000c 00000000 00000000 00000000 00000000 (0) + %r13: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r14: 00000001 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r15: 80001000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r16: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r17: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r18: 00000001 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r19: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r20: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r21: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r22: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r23: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r24: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r25: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r26: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r27: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r28: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r29: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r30: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r31: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) +DEBUG ../core.cpp:726: Thread mask: + 1 0 0 0 0 0 0 0 + + +DEBUG ../core.cpp:388: Now 1 active threads in 0 +********************************** Fetch ********************************* +valid: 1 +PC: 800009e8 +wid: 0 +rd: -1 rs1: 18 rs2: 0 +is_lw: 0 +is_sw: 0 +fetch_stall_cycles: 0 +mem_stall_cycles: 0 +stall_warp: 1 +wspawn: 0 +stalled: 0 + + + +------------------------------------------------------ +CYCLE: 318 +Stalled Warps: +1 0 0 0 0 0 0 0 + +********************************** Writeback ********************************* +valid: 0 +PC: 0 +wid: 1 +rd: -1 rs1: -1 rs2: -1 +is_lw: 0 +is_sw: 0 +fetch_stall_cycles: 0 +mem_stall_cycles: 0 +stall_warp: 0 +wspawn: 0 +stalled: 0 +********************************** LSU ********************************* +valid: 0 +PC: 0 +wid: 1 +rd: -1 rs1: -1 rs2: -1 +is_lw: 0 +is_sw: 0 +fetch_stall_cycles: 0 +mem_stall_cycles: 0 +stall_warp: 0 +wspawn: 0 +stalled: 0 +********************************** execute_unit ********************************* +valid: 1 +PC: 800009e0 +wid: 0 +rd: 18 rs1: 18 rs2: 15 +is_lw: 0 +is_sw: 0 +fetch_stall_cycles: 0 +mem_stall_cycles: 0 +stall_warp: 0 +wspawn: 0 +stalled: 0 +********************************** scheduler ********************************* +valid: 1 +PC: 800009e4 +wid: 0 +rd: 18 rs1: 18 rs2: -1 +is_lw: 0 +is_sw: 0 +fetch_stall_cycles: 0 +mem_stall_cycles: 0 +stall_warp: 0 +wspawn: 0 +stalled: 0 +********************************** Decode ********************************* +valid: 1 +PC: 800009e8 +wid: 0 +rd: -1 rs1: 18 rs2: 0 +is_lw: 0 +is_sw: 0 +fetch_stall_cycles: 0 +mem_stall_cycles: 0 +stall_warp: 1 +wspawn: 0 +stalled: 0 +********************************** Fetch ********************************* +valid: 0 +PC: 0 +wid: 1 +rd: -1 rs1: -1 rs2: -1 +is_lw: 0 +is_sw: 0 +fetch_stall_cycles: 0 +mem_stall_cycles: 0 +stall_warp: 0 +wspawn: 0 +stalled: 0 + + + +------------------------------------------------------ +CYCLE: 319 +Stalled Warps: +1 0 0 0 0 0 0 0 + +********************************** Writeback ********************************* +valid: 1 +PC: 800009e0 +wid: 0 +rd: 18 rs1: 18 rs2: 15 +is_lw: 0 +is_sw: 0 +fetch_stall_cycles: 0 +mem_stall_cycles: 0 +stall_warp: 0 +wspawn: 0 +stalled: 0 +********************************** LSU ********************************* +valid: 0 +PC: 0 +wid: 1 +rd: -1 rs1: -1 rs2: -1 +is_lw: 0 +is_sw: 0 +fetch_stall_cycles: 0 +mem_stall_cycles: 0 +stall_warp: 0 +wspawn: 0 +stalled: 0 +&&&&&&&&&&&&&&&&&&&&&&&& EXECUTE SRCS NOT READY +********************************** execute_unit ********************************* +valid: 0 +PC: 0 +wid: 2 +rd: -1 rs1: -1 rs2: -1 +is_lw: 0 +is_sw: 0 +fetch_stall_cycles: 0 +mem_stall_cycles: 0 +stall_warp: 0 +wspawn: 0 +stalled: 0 +********************************** scheduler ********************************* +valid: 1 +PC: 800009e4 +wid: 0 +rd: 18 rs1: 18 rs2: -1 +is_lw: 0 +is_sw: 0 +fetch_stall_cycles: 0 +mem_stall_cycles: 0 +stall_warp: 0 +wspawn: 0 +stalled: 1 +********************************** Decode ********************************* +valid: 1 +PC: 800009e8 +wid: 0 +rd: -1 rs1: 18 rs2: 0 +is_lw: 0 +is_sw: 0 +fetch_stall_cycles: 0 +mem_stall_cycles: 0 +stall_warp: 1 +wspawn: 0 +stalled: 0 +********************************** Fetch ********************************* +valid: 0 +PC: 0 +wid: 1 +rd: -1 rs1: -1 rs2: -1 +is_lw: 0 +is_sw: 0 +fetch_stall_cycles: 0 +mem_stall_cycles: 0 +stall_warp: 0 +wspawn: 0 +stalled: 0 + + + +------------------------------------------------------ +CYCLE: 320 +Stalled Warps: +1 0 0 0 0 0 0 0 + +********************************** Writeback ********************************* +valid: 0 +PC: 0 +wid: 2 +rd: -1 rs1: -1 rs2: -1 +is_lw: 0 +is_sw: 0 +fetch_stall_cycles: 0 +mem_stall_cycles: 0 +stall_warp: 0 +wspawn: 0 +stalled: 0 +********************************** LSU ********************************* +valid: 0 +PC: 0 +wid: 1 +rd: -1 rs1: -1 rs2: -1 +is_lw: 0 +is_sw: 0 +fetch_stall_cycles: 0 +mem_stall_cycles: 0 +stall_warp: 0 +wspawn: 0 +stalled: 0 +********************************** execute_unit ********************************* +valid: 1 +PC: 800009e4 +wid: 0 +rd: 18 rs1: 18 rs2: -1 +is_lw: 0 +is_sw: 0 +fetch_stall_cycles: 0 +mem_stall_cycles: 0 +stall_warp: 0 +wspawn: 0 +stalled: 0 +********************************** scheduler ********************************* +valid: 1 +PC: 800009e8 +wid: 0 +rd: -1 rs1: 18 rs2: 0 +is_lw: 0 +is_sw: 0 +fetch_stall_cycles: 0 +mem_stall_cycles: 0 +stall_warp: 1 +wspawn: 0 +stalled: 0 +********************************** Decode ********************************* +valid: 0 +PC: 0 +wid: 1 +rd: -1 rs1: -1 rs2: -1 +is_lw: 0 +is_sw: 0 +fetch_stall_cycles: 0 +mem_stall_cycles: 0 +stall_warp: 0 +wspawn: 0 +stalled: 0 +********************************** Fetch ********************************* +valid: 0 +PC: 0 +wid: 2 +rd: -1 rs1: -1 rs2: -1 +is_lw: 0 +is_sw: 0 +fetch_stall_cycles: 0 +mem_stall_cycles: 0 +stall_warp: 0 +wspawn: 0 +stalled: 0 + + + +------------------------------------------------------ +CYCLE: 321 +Stalled Warps: +1 0 0 0 0 0 0 0 + +********************************** Writeback ********************************* +valid: 1 +PC: 800009e4 +wid: 0 +rd: 18 rs1: 18 rs2: -1 +is_lw: 0 +is_sw: 0 +fetch_stall_cycles: 0 +mem_stall_cycles: 0 +stall_warp: 0 +wspawn: 0 +stalled: 0 +********************************** LSU ********************************* +valid: 0 +PC: 0 +wid: 1 +rd: -1 rs1: -1 rs2: -1 +is_lw: 0 +is_sw: 0 +fetch_stall_cycles: 0 +mem_stall_cycles: 0 +stall_warp: 0 +wspawn: 0 +stalled: 0 +&&&&&&&&&&&&&&&&&&&&&&&& EXECUTE SRCS NOT READY +********************************** execute_unit ********************************* +valid: 0 +PC: 0 +wid: 3 +rd: -1 rs1: -1 rs2: -1 +is_lw: 0 +is_sw: 0 +fetch_stall_cycles: 0 +mem_stall_cycles: 0 +stall_warp: 0 +wspawn: 0 +stalled: 0 +********************************** scheduler ********************************* +valid: 1 +PC: 800009e8 +wid: 0 +rd: -1 rs1: 18 rs2: 0 +is_lw: 0 +is_sw: 0 +fetch_stall_cycles: 0 +mem_stall_cycles: 0 +stall_warp: 1 +wspawn: 0 +stalled: 1 +********************************** Decode ********************************* +valid: 0 +PC: 0 +wid: 1 +rd: -1 rs1: -1 rs2: -1 +is_lw: 0 +is_sw: 0 +fetch_stall_cycles: 0 +mem_stall_cycles: 0 +stall_warp: 0 +wspawn: 0 +stalled: 0 +********************************** Fetch ********************************* +valid: 0 +PC: 0 +wid: 2 +rd: -1 rs1: -1 rs2: -1 +is_lw: 0 +is_sw: 0 +fetch_stall_cycles: 0 +mem_stall_cycles: 0 +stall_warp: 0 +wspawn: 0 +stalled: 0 + + + +------------------------------------------------------ +CYCLE: 322 +Stalled Warps: +1 0 0 0 0 0 0 0 + +********************************** Writeback ********************************* +valid: 0 +PC: 0 +wid: 3 +rd: -1 rs1: -1 rs2: -1 +is_lw: 0 +is_sw: 0 +fetch_stall_cycles: 0 +mem_stall_cycles: 0 +stall_warp: 0 +wspawn: 0 +stalled: 0 +********************************** LSU ********************************* +valid: 0 +PC: 0 +wid: 1 +rd: -1 rs1: -1 rs2: -1 +is_lw: 0 +is_sw: 0 +fetch_stall_cycles: 0 +mem_stall_cycles: 0 +stall_warp: 0 +wspawn: 0 +stalled: 0 +********************************** execute_unit ********************************* +valid: 1 +PC: 800009e8 +wid: 0 +rd: -1 rs1: 18 rs2: 0 +is_lw: 0 +is_sw: 0 +fetch_stall_cycles: 0 +mem_stall_cycles: 0 +stall_warp: 1 +wspawn: 0 +stalled: 0 +********************************** scheduler ********************************* +valid: 0 +PC: 0 +wid: 1 +rd: -1 rs1: -1 rs2: -1 +is_lw: 0 +is_sw: 0 +fetch_stall_cycles: 0 +mem_stall_cycles: 0 +stall_warp: 0 +wspawn: 0 +stalled: 0 +********************************** Decode ********************************* +valid: 0 +PC: 0 +wid: 2 +rd: -1 rs1: -1 rs2: -1 +is_lw: 0 +is_sw: 0 +fetch_stall_cycles: 0 +mem_stall_cycles: 0 +stall_warp: 0 +wspawn: 0 +stalled: 0 +********************************** Fetch ********************************* +valid: 0 +PC: 0 +wid: 3 +rd: -1 rs1: -1 rs2: -1 +is_lw: 0 +is_sw: 0 +fetch_stall_cycles: 0 +mem_stall_cycles: 0 +stall_warp: 0 +wspawn: 0 +stalled: 0 + + + +------------------------------------------------------ +CYCLE: 323 +Stalled Warps: +1 0 0 0 0 0 0 0 + +********************************** Writeback ********************************* +valid: 1 +PC: 800009e8 +wid: 0 +rd: -1 rs1: 18 rs2: 0 +is_lw: 0 +is_sw: 0 +fetch_stall_cycles: 0 +mem_stall_cycles: 0 +stall_warp: 1 +wspawn: 0 +stalled: 0 +********************************** LSU ********************************* +valid: 0 +PC: 0 +wid: 1 +rd: -1 rs1: -1 rs2: -1 +is_lw: 0 +is_sw: 0 +fetch_stall_cycles: 0 +mem_stall_cycles: 0 +stall_warp: 0 +wspawn: 0 +stalled: 0 +********************************** execute_unit ********************************* +valid: 0 +PC: 0 +wid: 1 +rd: -1 rs1: -1 rs2: -1 +is_lw: 0 +is_sw: 0 +fetch_stall_cycles: 0 +mem_stall_cycles: 0 +stall_warp: 0 +wspawn: 0 +stalled: 0 +********************************** scheduler ********************************* +valid: 0 +PC: 0 +wid: 2 +rd: -1 rs1: -1 rs2: -1 +is_lw: 0 +is_sw: 0 +fetch_stall_cycles: 0 +mem_stall_cycles: 0 +stall_warp: 0 +wspawn: 0 +stalled: 0 +********************************** Decode ********************************* +valid: 0 +PC: 0 +wid: 3 +rd: -1 rs1: -1 rs2: -1 +is_lw: 0 +is_sw: 0 +fetch_stall_cycles: 0 +mem_stall_cycles: 0 +stall_warp: 0 +wspawn: 0 +stalled: 0 +********************************** Fetch ********************************* +valid: 0 +PC: 0 +wid: 4 +rd: -1 rs1: -1 rs2: -1 +is_lw: 0 +is_sw: 0 +fetch_stall_cycles: 0 +mem_stall_cycles: 0 +stall_warp: 0 +wspawn: 0 +stalled: 0 + + + +------------------------------------------------------ +CYCLE: 324 +Stalled Warps: +1 0 0 0 0 0 0 0 + +********************************** Writeback ********************************* +valid: 0 +PC: 0 +wid: 5 +rd: -1 rs1: -1 rs2: -1 +is_lw: 0 +is_sw: 0 +fetch_stall_cycles: 0 +mem_stall_cycles: 0 +stall_warp: 0 +wspawn: 0 +stalled: 0 +********************************** LSU ********************************* +valid: 0 +PC: 0 +wid: 1 +rd: -1 rs1: -1 rs2: -1 +is_lw: 0 +is_sw: 0 +fetch_stall_cycles: 0 +mem_stall_cycles: 0 +stall_warp: 0 +wspawn: 0 +stalled: 0 +********************************** execute_unit ********************************* +valid: 0 +PC: 0 +wid: 2 +rd: -1 rs1: -1 rs2: -1 +is_lw: 0 +is_sw: 0 +fetch_stall_cycles: 0 +mem_stall_cycles: 0 +stall_warp: 0 +wspawn: 0 +stalled: 0 +********************************** scheduler ********************************* +valid: 0 +PC: 0 +wid: 3 +rd: -1 rs1: -1 rs2: -1 +is_lw: 0 +is_sw: 0 +fetch_stall_cycles: 0 +mem_stall_cycles: 0 +stall_warp: 0 +wspawn: 0 +stalled: 0 +********************************** Decode ********************************* +valid: 0 +PC: 0 +wid: 4 +rd: -1 rs1: -1 rs2: -1 +is_lw: 0 +is_sw: 0 +fetch_stall_cycles: 0 +mem_stall_cycles: 0 +stall_warp: 0 +wspawn: 0 +stalled: 0 +********************************** Fetch ********************************* +valid: 0 +PC: 0 +wid: 5 +rd: -1 rs1: -1 rs2: -1 +is_lw: 0 +is_sw: 0 +fetch_stall_cycles: 0 +mem_stall_cycles: 0 +stall_warp: 0 +wspawn: 0 +stalled: 0 +Warp ID 0 is running + + + +------------------------------------------------------ +CYCLE: 325 +Stalled Warps: +0 0 0 0 0 0 0 0 + +********************************** Writeback ********************************* +valid: 0 +PC: 0 +wid: 0 +rd: -1 rs1: -1 rs2: -1 +is_lw: 0 +is_sw: 0 +fetch_stall_cycles: 0 +mem_stall_cycles: 0 +stall_warp: 0 +wspawn: 0 +stalled: 0 +********************************** LSU ********************************* +valid: 0 +PC: 0 +wid: 1 +rd: -1 rs1: -1 rs2: -1 +is_lw: 0 +is_sw: 0 +fetch_stall_cycles: 0 +mem_stall_cycles: 0 +stall_warp: 0 +wspawn: 0 +stalled: 0 +********************************** execute_unit ********************************* +valid: 0 +PC: 0 +wid: 3 +rd: -1 rs1: -1 rs2: -1 +is_lw: 0 +is_sw: 0 +fetch_stall_cycles: 0 +mem_stall_cycles: 0 +stall_warp: 0 +wspawn: 0 +stalled: 0 +********************************** scheduler ********************************* +valid: 0 +PC: 0 +wid: 4 +rd: -1 rs1: -1 rs2: -1 +is_lw: 0 +is_sw: 0 +fetch_stall_cycles: 0 +mem_stall_cycles: 0 +stall_warp: 0 +wspawn: 0 +stalled: 0 +********************************** Decode ********************************* +valid: 0 +PC: 0 +wid: 5 +rd: -1 rs1: -1 rs2: -1 +is_lw: 0 +is_sw: 0 +fetch_stall_cycles: 0 +mem_stall_cycles: 0 +stall_warp: 0 +wspawn: 0 +stalled: 0 +DEBUG ../core.cpp:386: Core step stepping warp 0[1] +DEBUG ../core.cpp:683: in step pc=0x800009ec +help: in PC: 800009ec +CUrrent CODE: 40413 +DEBUG ../core.cpp:703: Fetched at 0x800009ec +DEBUG ../core.cpp:704: 0x800009ec: i_type; +DEBUG ../instruction.cpp:350: Begin instruction execute. +DEBUG ../instruction.cpp:2117: End instruction execute. +DEBUG ../core.cpp:717: Register state: + %r 0: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r 1: 80000040 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r 2: 6fffeff0 6fffec04 6fffe808 6fffe40c 00000000 00000000 00000000 00000000 (0) + %r 3: 80001808 80001808 80001808 80001808 00000000 00000000 00000000 00000000 (0) + %r 4: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r 5: 80000a6c 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r 6: 0000000f 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r 7: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r 8: 80001000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r 9: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r10: 00000000 00000001 00000001 00000001 00000000 00000000 00000000 00000000 (0) + %r11: 80000924 00000400 00000800 00000c00 00000000 00000000 00000000 00000000 (0) + %r12: 00000000 00000004 00000008 0000000c 00000000 00000000 00000000 00000000 (0) + %r13: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r14: 00000001 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r15: 80001000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r16: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r17: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r18: 00000001 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r19: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r20: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r21: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r22: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r23: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r24: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r25: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r26: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r27: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r28: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r29: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r30: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r31: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) +DEBUG ../core.cpp:726: Thread mask: + 1 0 0 0 0 0 0 0 + + +DEBUG ../core.cpp:388: Now 1 active threads in 0 +********************************** Fetch ********************************* +valid: 1 +PC: 800009ec +wid: 0 +rd: 8 rs1: 8 rs2: -1 +is_lw: 0 +is_sw: 0 +fetch_stall_cycles: 0 +mem_stall_cycles: 0 +stall_warp: 0 +wspawn: 0 +stalled: 0 + + + +------------------------------------------------------ +CYCLE: 326 +Stalled Warps: +0 0 0 0 0 0 0 0 + +********************************** Writeback ********************************* +valid: 0 +PC: 0 +wid: 0 +rd: -1 rs1: -1 rs2: -1 +is_lw: 0 +is_sw: 0 +fetch_stall_cycles: 0 +mem_stall_cycles: 0 +stall_warp: 0 +wspawn: 0 +stalled: 0 +********************************** LSU ********************************* +valid: 0 +PC: 0 +wid: 1 +rd: -1 rs1: -1 rs2: -1 +is_lw: 0 +is_sw: 0 +fetch_stall_cycles: 0 +mem_stall_cycles: 0 +stall_warp: 0 +wspawn: 0 +stalled: 0 +********************************** execute_unit ********************************* +valid: 0 +PC: 0 +wid: 4 +rd: -1 rs1: -1 rs2: -1 +is_lw: 0 +is_sw: 0 +fetch_stall_cycles: 0 +mem_stall_cycles: 0 +stall_warp: 0 +wspawn: 0 +stalled: 0 +********************************** scheduler ********************************* +valid: 0 +PC: 0 +wid: 5 +rd: -1 rs1: -1 rs2: -1 +is_lw: 0 +is_sw: 0 +fetch_stall_cycles: 0 +mem_stall_cycles: 0 +stall_warp: 0 +wspawn: 0 +stalled: 0 +********************************** Decode ********************************* +valid: 1 +PC: 800009ec +wid: 0 +rd: 8 rs1: 8 rs2: -1 +is_lw: 0 +is_sw: 0 +fetch_stall_cycles: 0 +mem_stall_cycles: 0 +stall_warp: 0 +wspawn: 0 +stalled: 0 +DEBUG ../core.cpp:386: Core step stepping warp 0[1] +DEBUG ../core.cpp:683: in step pc=0x800009f0 +help: in PC: 800009f0 +CUrrent CODE: 493 +DEBUG ../core.cpp:703: Fetched at 0x800009f0 +DEBUG ../core.cpp:704: 0x800009f0: i_type; +DEBUG ../instruction.cpp:350: Begin instruction execute. +DEBUG ../instruction.cpp:2117: End instruction execute. +DEBUG ../core.cpp:717: Register state: + %r 0: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r 1: 80000040 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r 2: 6fffeff0 6fffec04 6fffe808 6fffe40c 00000000 00000000 00000000 00000000 (0) + %r 3: 80001808 80001808 80001808 80001808 00000000 00000000 00000000 00000000 (0) + %r 4: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r 5: 80000a6c 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r 6: 0000000f 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r 7: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r 8: 80001000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r 9: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r10: 00000000 00000001 00000001 00000001 00000000 00000000 00000000 00000000 (0) + %r11: 80000924 00000400 00000800 00000c00 00000000 00000000 00000000 00000000 (0) + %r12: 00000000 00000004 00000008 0000000c 00000000 00000000 00000000 00000000 (0) + %r13: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r14: 00000001 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r15: 80001000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r16: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r17: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r18: 00000001 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r19: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r20: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r21: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r22: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r23: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r24: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r25: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r26: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r27: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r28: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r29: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r30: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r31: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) +DEBUG ../core.cpp:726: Thread mask: + 1 0 0 0 0 0 0 0 + + +DEBUG ../core.cpp:388: Now 1 active threads in 0 +********************************** Fetch ********************************* +valid: 1 +PC: 800009f0 +wid: 0 +rd: 9 rs1: 0 rs2: -1 +is_lw: 0 +is_sw: 0 +fetch_stall_cycles: 3 +mem_stall_cycles: 0 +stall_warp: 0 +wspawn: 0 +stalled: 0 + + + +------------------------------------------------------ +CYCLE: 327 +Stalled Warps: +0 0 0 0 0 0 0 0 + +********************************** Writeback ********************************* +valid: 0 +PC: 0 +wid: 0 +rd: -1 rs1: -1 rs2: -1 +is_lw: 0 +is_sw: 0 +fetch_stall_cycles: 0 +mem_stall_cycles: 0 +stall_warp: 0 +wspawn: 0 +stalled: 0 +********************************** LSU ********************************* +valid: 0 +PC: 0 +wid: 1 +rd: -1 rs1: -1 rs2: -1 +is_lw: 0 +is_sw: 0 +fetch_stall_cycles: 0 +mem_stall_cycles: 0 +stall_warp: 0 +wspawn: 0 +stalled: 0 +********************************** execute_unit ********************************* +valid: 0 +PC: 0 +wid: 5 +rd: -1 rs1: -1 rs2: -1 +is_lw: 0 +is_sw: 0 +fetch_stall_cycles: 0 +mem_stall_cycles: 0 +stall_warp: 0 +wspawn: 0 +stalled: 0 +********************************** scheduler ********************************* +valid: 1 +PC: 800009ec +wid: 0 +rd: 8 rs1: 8 rs2: -1 +is_lw: 0 +is_sw: 0 +fetch_stall_cycles: 0 +mem_stall_cycles: 0 +stall_warp: 0 +wspawn: 0 +stalled: 0 +********************************** Decode ********************************* +valid: 0 +PC: 0 +wid: 0 +rd: -1 rs1: -1 rs2: -1 +is_lw: 0 +is_sw: 0 +fetch_stall_cycles: 0 +mem_stall_cycles: 0 +stall_warp: 0 +wspawn: 0 +stalled: 0 +********************************** Fetch ********************************* +valid: 1 +PC: 800009f0 +wid: 0 +rd: 9 rs1: 0 rs2: -1 +is_lw: 0 +is_sw: 0 +fetch_stall_cycles: 2 +mem_stall_cycles: 0 +stall_warp: 0 +wspawn: 0 +stalled: 0 + + + +------------------------------------------------------ +CYCLE: 328 +Stalled Warps: +0 0 0 0 0 0 0 0 + +********************************** Writeback ********************************* +valid: 0 +PC: 0 +wid: 0 +rd: -1 rs1: -1 rs2: -1 +is_lw: 0 +is_sw: 0 +fetch_stall_cycles: 0 +mem_stall_cycles: 0 +stall_warp: 0 +wspawn: 0 +stalled: 0 +********************************** LSU ********************************* +valid: 0 +PC: 0 +wid: 1 +rd: -1 rs1: -1 rs2: -1 +is_lw: 0 +is_sw: 0 +fetch_stall_cycles: 0 +mem_stall_cycles: 0 +stall_warp: 0 +wspawn: 0 +stalled: 0 +********************************** execute_unit ********************************* +valid: 1 +PC: 800009ec +wid: 0 +rd: 8 rs1: 8 rs2: -1 +is_lw: 0 +is_sw: 0 +fetch_stall_cycles: 0 +mem_stall_cycles: 0 +stall_warp: 0 +wspawn: 0 +stalled: 0 +********************************** scheduler ********************************* +valid: 0 +PC: 0 +wid: 0 +rd: -1 rs1: -1 rs2: -1 +is_lw: 0 +is_sw: 0 +fetch_stall_cycles: 0 +mem_stall_cycles: 0 +stall_warp: 0 +wspawn: 0 +stalled: 0 +********************************** Decode ********************************* +valid: 0 +PC: 0 +wid: 0 +rd: -1 rs1: -1 rs2: -1 +is_lw: 0 +is_sw: 0 +fetch_stall_cycles: 0 +mem_stall_cycles: 0 +stall_warp: 0 +wspawn: 0 +stalled: 0 +********************************** Fetch ********************************* +valid: 1 +PC: 800009f0 +wid: 0 +rd: 9 rs1: 0 rs2: -1 +is_lw: 0 +is_sw: 0 +fetch_stall_cycles: 1 +mem_stall_cycles: 0 +stall_warp: 0 +wspawn: 0 +stalled: 0 + + + +------------------------------------------------------ +CYCLE: 329 +Stalled Warps: +0 0 0 0 0 0 0 0 + +********************************** Writeback ********************************* +valid: 1 +PC: 800009ec +wid: 0 +rd: 8 rs1: 8 rs2: -1 +is_lw: 0 +is_sw: 0 +fetch_stall_cycles: 0 +mem_stall_cycles: 0 +stall_warp: 0 +wspawn: 0 +stalled: 0 +********************************** LSU ********************************* +valid: 0 +PC: 0 +wid: 1 +rd: -1 rs1: -1 rs2: -1 +is_lw: 0 +is_sw: 0 +fetch_stall_cycles: 0 +mem_stall_cycles: 0 +stall_warp: 0 +wspawn: 0 +stalled: 0 +********************************** execute_unit ********************************* +valid: 0 +PC: 0 +wid: 0 +rd: -1 rs1: -1 rs2: -1 +is_lw: 0 +is_sw: 0 +fetch_stall_cycles: 0 +mem_stall_cycles: 0 +stall_warp: 0 +wspawn: 0 +stalled: 0 +********************************** scheduler ********************************* +valid: 0 +PC: 0 +wid: 0 +rd: -1 rs1: -1 rs2: -1 +is_lw: 0 +is_sw: 0 +fetch_stall_cycles: 0 +mem_stall_cycles: 0 +stall_warp: 0 +wspawn: 0 +stalled: 0 +********************************** Decode ********************************* +valid: 0 +PC: 0 +wid: 0 +rd: -1 rs1: -1 rs2: -1 +is_lw: 0 +is_sw: 0 +fetch_stall_cycles: 0 +mem_stall_cycles: 0 +stall_warp: 0 +wspawn: 0 +stalled: 0 +********************************** Fetch ********************************* +valid: 1 +PC: 800009f0 +wid: 0 +rd: 9 rs1: 0 rs2: -1 +is_lw: 0 +is_sw: 0 +fetch_stall_cycles: 0 +mem_stall_cycles: 0 +stall_warp: 0 +wspawn: 0 +stalled: 0 + + + +------------------------------------------------------ +CYCLE: 330 +Stalled Warps: +0 0 0 0 0 0 0 0 + +********************************** Writeback ********************************* +valid: 0 +PC: 0 +wid: 0 +rd: -1 rs1: -1 rs2: -1 +is_lw: 0 +is_sw: 0 +fetch_stall_cycles: 0 +mem_stall_cycles: 0 +stall_warp: 0 +wspawn: 0 +stalled: 0 +********************************** LSU ********************************* +valid: 0 +PC: 0 +wid: 1 +rd: -1 rs1: -1 rs2: -1 +is_lw: 0 +is_sw: 0 +fetch_stall_cycles: 0 +mem_stall_cycles: 0 +stall_warp: 0 +wspawn: 0 +stalled: 0 +********************************** execute_unit ********************************* +valid: 0 +PC: 0 +wid: 0 +rd: -1 rs1: -1 rs2: -1 +is_lw: 0 +is_sw: 0 +fetch_stall_cycles: 0 +mem_stall_cycles: 0 +stall_warp: 0 +wspawn: 0 +stalled: 0 +********************************** scheduler ********************************* +valid: 0 +PC: 0 +wid: 0 +rd: -1 rs1: -1 rs2: -1 +is_lw: 0 +is_sw: 0 +fetch_stall_cycles: 0 +mem_stall_cycles: 0 +stall_warp: 0 +wspawn: 0 +stalled: 0 +********************************** Decode ********************************* +valid: 1 +PC: 800009f0 +wid: 0 +rd: 9 rs1: 0 rs2: -1 +is_lw: 0 +is_sw: 0 +fetch_stall_cycles: 0 +mem_stall_cycles: 0 +stall_warp: 0 +wspawn: 0 +stalled: 0 +DEBUG ../core.cpp:386: Core step stepping warp 0[1] +DEBUG ../core.cpp:683: in step pc=0x800009f4 +help: in PC: 800009f4 +CUrrent CODE: 42783 +DEBUG ../core.cpp:703: Fetched at 0x800009f4 +DEBUG ../core.cpp:704: 0x800009f4: load; +DEBUG ../instruction.cpp:350: Begin instruction execute. +DEBUG ../instruction.cpp:2117: End instruction execute. +DEBUG ../core.cpp:717: Register state: + %r 0: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r 1: 80000040 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r 2: 6fffeff0 6fffec04 6fffe808 6fffe40c 00000000 00000000 00000000 00000000 (0) + %r 3: 80001808 80001808 80001808 80001808 00000000 00000000 00000000 00000000 (0) + %r 4: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r 5: 80000a6c 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r 6: 0000000f 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r 7: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r 8: 80001000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r 9: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r10: 00000000 00000001 00000001 00000001 00000000 00000000 00000000 00000000 (0) + %r11: 80000924 00000400 00000800 00000c00 00000000 00000000 00000000 00000000 (0) + %r12: 00000000 00000004 00000008 0000000c 00000000 00000000 00000000 00000000 (0) + %r13: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r14: 00000001 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r15: 80000050 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r16: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r17: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r18: 00000001 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r19: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r20: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r21: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r22: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r23: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r24: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r25: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r26: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r27: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r28: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r29: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r30: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r31: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) +DEBUG ../core.cpp:726: Thread mask: + 1 0 0 0 0 0 0 0 + + +DEBUG ../core.cpp:388: Now 1 active threads in 0 +********************************** Fetch ********************************* +valid: 1 +PC: 800009f4 +wid: 0 +rd: 15 rs1: 8 rs2: -1 +is_lw: 1 +is_sw: 0 +fetch_stall_cycles: 0 +mem_stall_cycles: 3 +stall_warp: 0 +wspawn: 0 +stalled: 0 + + + +------------------------------------------------------ +CYCLE: 331 +Stalled Warps: +0 0 0 0 0 0 0 0 + +********************************** Writeback ********************************* +valid: 0 +PC: 0 +wid: 0 +rd: -1 rs1: -1 rs2: -1 +is_lw: 0 +is_sw: 0 +fetch_stall_cycles: 0 +mem_stall_cycles: 0 +stall_warp: 0 +wspawn: 0 +stalled: 0 +********************************** LSU ********************************* +valid: 0 +PC: 0 +wid: 1 +rd: -1 rs1: -1 rs2: -1 +is_lw: 0 +is_sw: 0 +fetch_stall_cycles: 0 +mem_stall_cycles: 0 +stall_warp: 0 +wspawn: 0 +stalled: 0 +********************************** execute_unit ********************************* +valid: 0 +PC: 0 +wid: 0 +rd: -1 rs1: -1 rs2: -1 +is_lw: 0 +is_sw: 0 +fetch_stall_cycles: 0 +mem_stall_cycles: 0 +stall_warp: 0 +wspawn: 0 +stalled: 0 +********************************** scheduler ********************************* +valid: 1 +PC: 800009f0 +wid: 0 +rd: 9 rs1: 0 rs2: -1 +is_lw: 0 +is_sw: 0 +fetch_stall_cycles: 0 +mem_stall_cycles: 0 +stall_warp: 0 +wspawn: 0 +stalled: 0 +********************************** Decode ********************************* +valid: 1 +PC: 800009f4 +wid: 0 +rd: 15 rs1: 8 rs2: -1 +is_lw: 1 +is_sw: 0 +fetch_stall_cycles: 0 +mem_stall_cycles: 3 +stall_warp: 0 +wspawn: 0 +stalled: 0 +DEBUG ../core.cpp:386: Core step stepping warp 0[1] +DEBUG ../core.cpp:683: in step pc=0x800009f8 +help: in PC: 800009f8 +CUrrent CODE: 148493 +DEBUG ../core.cpp:703: Fetched at 0x800009f8 +DEBUG ../core.cpp:704: 0x800009f8: i_type; +DEBUG ../instruction.cpp:350: Begin instruction execute. +DEBUG ../instruction.cpp:2117: End instruction execute. +DEBUG ../core.cpp:717: Register state: + %r 0: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r 1: 80000040 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r 2: 6fffeff0 6fffec04 6fffe808 6fffe40c 00000000 00000000 00000000 00000000 (0) + %r 3: 80001808 80001808 80001808 80001808 00000000 00000000 00000000 00000000 (0) + %r 4: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r 5: 80000a6c 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r 6: 0000000f 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r 7: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r 8: 80001000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r 9: 00000001 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r10: 00000000 00000001 00000001 00000001 00000000 00000000 00000000 00000000 (0) + %r11: 80000924 00000400 00000800 00000c00 00000000 00000000 00000000 00000000 (0) + %r12: 00000000 00000004 00000008 0000000c 00000000 00000000 00000000 00000000 (0) + %r13: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r14: 00000001 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r15: 80000050 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r16: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r17: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r18: 00000001 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r19: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r20: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r21: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r22: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r23: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r24: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r25: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r26: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r27: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r28: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r29: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r30: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r31: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) +DEBUG ../core.cpp:726: Thread mask: + 1 0 0 0 0 0 0 0 + + +DEBUG ../core.cpp:388: Now 1 active threads in 0 +********************************** Fetch ********************************* +valid: 1 +PC: 800009f8 +wid: 0 +rd: 9 rs1: 9 rs2: -1 +is_lw: 0 +is_sw: 0 +fetch_stall_cycles: 0 +mem_stall_cycles: 0 +stall_warp: 0 +wspawn: 0 +stalled: 0 + + + +------------------------------------------------------ +CYCLE: 332 +Stalled Warps: +0 0 0 0 0 0 0 0 + +********************************** Writeback ********************************* +valid: 0 +PC: 0 +wid: 0 +rd: -1 rs1: -1 rs2: -1 +is_lw: 0 +is_sw: 0 +fetch_stall_cycles: 0 +mem_stall_cycles: 0 +stall_warp: 0 +wspawn: 0 +stalled: 0 +********************************** LSU ********************************* +valid: 0 +PC: 0 +wid: 1 +rd: -1 rs1: -1 rs2: -1 +is_lw: 0 +is_sw: 0 +fetch_stall_cycles: 0 +mem_stall_cycles: 0 +stall_warp: 0 +wspawn: 0 +stalled: 0 +********************************** execute_unit ********************************* +valid: 1 +PC: 800009f0 +wid: 0 +rd: 9 rs1: 0 rs2: -1 +is_lw: 0 +is_sw: 0 +fetch_stall_cycles: 0 +mem_stall_cycles: 0 +stall_warp: 0 +wspawn: 0 +stalled: 0 +********************************** scheduler ********************************* +valid: 1 +PC: 800009f4 +wid: 0 +rd: 15 rs1: 8 rs2: -1 +is_lw: 1 +is_sw: 0 +fetch_stall_cycles: 0 +mem_stall_cycles: 3 +stall_warp: 0 +wspawn: 0 +stalled: 0 +********************************** Decode ********************************* +valid: 1 +PC: 800009f8 +wid: 0 +rd: 9 rs1: 9 rs2: -1 +is_lw: 0 +is_sw: 0 +fetch_stall_cycles: 0 +mem_stall_cycles: 0 +stall_warp: 0 +wspawn: 0 +stalled: 0 +DEBUG ../core.cpp:386: Core step stepping warp 0[1] +DEBUG ../core.cpp:683: in step pc=0x800009fc +help: in PC: 800009fc +CUrrent CODE: 440413 +DEBUG ../core.cpp:703: Fetched at 0x800009fc +DEBUG ../core.cpp:704: 0x800009fc: i_type; +DEBUG ../instruction.cpp:350: Begin instruction execute. +DEBUG ../instruction.cpp:2117: End instruction execute. +DEBUG ../core.cpp:717: Register state: + %r 0: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r 1: 80000040 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r 2: 6fffeff0 6fffec04 6fffe808 6fffe40c 00000000 00000000 00000000 00000000 (0) + %r 3: 80001808 80001808 80001808 80001808 00000000 00000000 00000000 00000000 (0) + %r 4: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r 5: 80000a6c 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r 6: 0000000f 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r 7: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r 8: 80001004 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r 9: 00000001 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r10: 00000000 00000001 00000001 00000001 00000000 00000000 00000000 00000000 (0) + %r11: 80000924 00000400 00000800 00000c00 00000000 00000000 00000000 00000000 (0) + %r12: 00000000 00000004 00000008 0000000c 00000000 00000000 00000000 00000000 (0) + %r13: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r14: 00000001 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r15: 80000050 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r16: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r17: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r18: 00000001 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r19: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r20: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r21: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r22: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r23: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r24: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r25: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r26: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r27: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r28: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r29: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r30: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r31: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) +DEBUG ../core.cpp:726: Thread mask: + 1 0 0 0 0 0 0 0 + + +DEBUG ../core.cpp:388: Now 1 active threads in 0 +********************************** Fetch ********************************* +valid: 1 +PC: 800009fc +wid: 0 +rd: 8 rs1: 8 rs2: -1 +is_lw: 0 +is_sw: 0 +fetch_stall_cycles: 0 +mem_stall_cycles: 0 +stall_warp: 0 +wspawn: 0 +stalled: 0 + + + +------------------------------------------------------ +CYCLE: 333 +Stalled Warps: +0 0 0 0 0 0 0 0 + +********************************** Writeback ********************************* +valid: 1 +PC: 800009f0 +wid: 0 +rd: 9 rs1: 0 rs2: -1 +is_lw: 0 +is_sw: 0 +fetch_stall_cycles: 0 +mem_stall_cycles: 0 +stall_warp: 0 +wspawn: 0 +stalled: 0 +********************************** LSU ********************************* +valid: 1 +PC: 800009f4 +wid: 0 +rd: 15 rs1: 8 rs2: -1 +is_lw: 1 +is_sw: 0 +fetch_stall_cycles: 0 +mem_stall_cycles: 2 +stall_warp: 0 +wspawn: 0 +stalled: 0 +********************************** execute_unit ********************************* +valid: 0 +PC: 0 +wid: 0 +rd: -1 rs1: -1 rs2: -1 +is_lw: 0 +is_sw: 0 +fetch_stall_cycles: 0 +mem_stall_cycles: 0 +stall_warp: 0 +wspawn: 0 +stalled: 0 +********************************** scheduler ********************************* +valid: 1 +PC: 800009f8 +wid: 0 +rd: 9 rs1: 9 rs2: -1 +is_lw: 0 +is_sw: 0 +fetch_stall_cycles: 0 +mem_stall_cycles: 0 +stall_warp: 0 +wspawn: 0 +stalled: 0 +********************************** Decode ********************************* +valid: 1 +PC: 800009fc +wid: 0 +rd: 8 rs1: 8 rs2: -1 +is_lw: 0 +is_sw: 0 +fetch_stall_cycles: 0 +mem_stall_cycles: 0 +stall_warp: 0 +wspawn: 0 +stalled: 0 +DEBUG ../core.cpp:386: Core step stepping warp 0[1] +DEBUG ../core.cpp:683: in step pc=0x80000a00 +help: in PC: 80000a00 +CUrrent CODE: 780e7 +DEBUG ../core.cpp:703: Fetched at 0x80000a00 +DEBUG ../core.cpp:704: 0x80000a00: jalr; +DEBUG ../instruction.cpp:350: Begin instruction execute. +JALR_INST +DEBUG ../instruction.cpp:2117: End instruction execute. +Next PC: 80000050 +DEBUG ../core.cpp:717: Register state: + %r 0: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r 1: 80000a04 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r 2: 6fffeff0 6fffec04 6fffe808 6fffe40c 00000000 00000000 00000000 00000000 (0) + %r 3: 80001808 80001808 80001808 80001808 00000000 00000000 00000000 00000000 (0) + %r 4: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r 5: 80000a6c 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r 6: 0000000f 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r 7: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r 8: 80001004 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r 9: 00000001 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r10: 00000000 00000001 00000001 00000001 00000000 00000000 00000000 00000000 (0) + %r11: 80000924 00000400 00000800 00000c00 00000000 00000000 00000000 00000000 (0) + %r12: 00000000 00000004 00000008 0000000c 00000000 00000000 00000000 00000000 (0) + %r13: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r14: 00000001 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r15: 80000050 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r16: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r17: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r18: 00000001 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r19: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r20: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r21: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r22: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r23: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r24: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r25: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r26: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r27: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r28: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r29: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r30: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r31: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) +DEBUG ../core.cpp:726: Thread mask: + 1 0 0 0 0 0 0 0 + + +DEBUG ../core.cpp:388: Now 1 active threads in 0 +********************************** Fetch ********************************* +valid: 1 +PC: 80000a00 +wid: 0 +rd: 1 rs1: 15 rs2: -1 +is_lw: 0 +is_sw: 0 +fetch_stall_cycles: 3 +mem_stall_cycles: 0 +stall_warp: 1 +wspawn: 0 +stalled: 0 + + + +------------------------------------------------------ +CYCLE: 334 +Stalled Warps: +1 0 0 0 0 0 0 0 + +********************************** Writeback ********************************* +valid: 0 +PC: 0 +wid: 1 +rd: -1 rs1: -1 rs2: -1 +is_lw: 0 +is_sw: 0 +fetch_stall_cycles: 0 +mem_stall_cycles: 0 +stall_warp: 0 +wspawn: 0 +stalled: 0 +********************************** LSU ********************************* +valid: 1 +PC: 800009f4 +wid: 0 +rd: 15 rs1: 8 rs2: -1 +is_lw: 1 +is_sw: 0 +fetch_stall_cycles: 0 +mem_stall_cycles: 1 +stall_warp: 0 +wspawn: 0 +stalled: 0 +********************************** execute_unit ********************************* +valid: 1 +PC: 800009f8 +wid: 0 +rd: 9 rs1: 9 rs2: -1 +is_lw: 0 +is_sw: 0 +fetch_stall_cycles: 0 +mem_stall_cycles: 0 +stall_warp: 0 +wspawn: 0 +stalled: 0 +********************************** scheduler ********************************* +valid: 1 +PC: 800009fc +wid: 0 +rd: 8 rs1: 8 rs2: -1 +is_lw: 0 +is_sw: 0 +fetch_stall_cycles: 0 +mem_stall_cycles: 0 +stall_warp: 0 +wspawn: 0 +stalled: 0 +********************************** Decode ********************************* +valid: 0 +PC: 0 +wid: 1 +rd: -1 rs1: -1 rs2: -1 +is_lw: 0 +is_sw: 0 +fetch_stall_cycles: 0 +mem_stall_cycles: 0 +stall_warp: 0 +wspawn: 0 +stalled: 0 +********************************** Fetch ********************************* +valid: 1 +PC: 80000a00 +wid: 0 +rd: 1 rs1: 15 rs2: -1 +is_lw: 0 +is_sw: 0 +fetch_stall_cycles: 2 +mem_stall_cycles: 0 +stall_warp: 1 +wspawn: 0 +stalled: 0 + + + +------------------------------------------------------ +CYCLE: 335 +Stalled Warps: +1 0 0 0 0 0 0 0 + +********************************** Writeback ********************************* +valid: 1 +PC: 800009f8 +wid: 0 +rd: 9 rs1: 9 rs2: -1 +is_lw: 0 +is_sw: 0 +fetch_stall_cycles: 0 +mem_stall_cycles: 0 +stall_warp: 0 +wspawn: 0 +stalled: 0 +********************************** LSU ********************************* +valid: 1 +PC: 800009f4 +wid: 0 +rd: 15 rs1: 8 rs2: -1 +is_lw: 1 +is_sw: 0 +fetch_stall_cycles: 0 +mem_stall_cycles: 0 +stall_warp: 0 +wspawn: 0 +stalled: 0 +********************************** execute_unit ********************************* +valid: 1 +PC: 800009fc +wid: 0 +rd: 8 rs1: 8 rs2: -1 +is_lw: 0 +is_sw: 0 +fetch_stall_cycles: 0 +mem_stall_cycles: 0 +stall_warp: 0 +wspawn: 0 +stalled: 0 +********************************** scheduler ********************************* +valid: 0 +PC: 0 +wid: 1 +rd: -1 rs1: -1 rs2: -1 +is_lw: 0 +is_sw: 0 +fetch_stall_cycles: 0 +mem_stall_cycles: 0 +stall_warp: 0 +wspawn: 0 +stalled: 0 +********************************** Decode ********************************* +valid: 0 +PC: 0 +wid: 1 +rd: -1 rs1: -1 rs2: -1 +is_lw: 0 +is_sw: 0 +fetch_stall_cycles: 0 +mem_stall_cycles: 0 +stall_warp: 0 +wspawn: 0 +stalled: 0 +********************************** Fetch ********************************* +valid: 1 +PC: 80000a00 +wid: 0 +rd: 1 rs1: 15 rs2: -1 +is_lw: 0 +is_sw: 0 +fetch_stall_cycles: 1 +mem_stall_cycles: 0 +stall_warp: 1 +wspawn: 0 +stalled: 0 + + + +------------------------------------------------------ +CYCLE: 336 +Stalled Warps: +1 0 0 0 0 0 0 0 + +$$$$$$$$$$$$$$$$$$$$ Stalling LSU because EXE is being used +********************************** Writeback ********************************* +valid: 1 +PC: 800009fc +wid: 0 +rd: 8 rs1: 8 rs2: -1 +is_lw: 0 +is_sw: 0 +fetch_stall_cycles: 0 +mem_stall_cycles: 0 +stall_warp: 0 +wspawn: 0 +stalled: 0 +********************************** LSU ********************************* +valid: 1 +PC: 800009f4 +wid: 0 +rd: 15 rs1: 8 rs2: -1 +is_lw: 1 +is_sw: 0 +fetch_stall_cycles: 0 +mem_stall_cycles: 0 +stall_warp: 0 +wspawn: 0 +stalled: 1 +********************************** execute_unit ********************************* +valid: 0 +PC: 0 +wid: 1 +rd: -1 rs1: -1 rs2: -1 +is_lw: 0 +is_sw: 0 +fetch_stall_cycles: 0 +mem_stall_cycles: 0 +stall_warp: 0 +wspawn: 0 +stalled: 0 +********************************** scheduler ********************************* +valid: 0 +PC: 0 +wid: 1 +rd: -1 rs1: -1 rs2: -1 +is_lw: 0 +is_sw: 0 +fetch_stall_cycles: 0 +mem_stall_cycles: 0 +stall_warp: 0 +wspawn: 0 +stalled: 0 +********************************** Decode ********************************* +valid: 0 +PC: 0 +wid: 1 +rd: -1 rs1: -1 rs2: -1 +is_lw: 0 +is_sw: 0 +fetch_stall_cycles: 0 +mem_stall_cycles: 0 +stall_warp: 0 +wspawn: 0 +stalled: 0 +********************************** Fetch ********************************* +valid: 1 +PC: 80000a00 +wid: 0 +rd: 1 rs1: 15 rs2: -1 +is_lw: 0 +is_sw: 0 +fetch_stall_cycles: 0 +mem_stall_cycles: 0 +stall_warp: 1 +wspawn: 0 +stalled: 0 + + + +------------------------------------------------------ +CYCLE: 337 +Stalled Warps: +1 0 0 0 0 0 0 0 + +********************************** Writeback ********************************* +valid: 1 +PC: 800009f4 +wid: 0 +rd: 15 rs1: 8 rs2: -1 +is_lw: 1 +is_sw: 0 +fetch_stall_cycles: 0 +mem_stall_cycles: 0 +stall_warp: 0 +wspawn: 0 +stalled: 0 +********************************** LSU ********************************* +valid: 0 +PC: 0 +wid: 1 +rd: -1 rs1: -1 rs2: -1 +is_lw: 0 +is_sw: 0 +fetch_stall_cycles: 0 +mem_stall_cycles: 0 +stall_warp: 0 +wspawn: 0 +stalled: 0 +********************************** execute_unit ********************************* +valid: 0 +PC: 0 +wid: 1 +rd: -1 rs1: -1 rs2: -1 +is_lw: 0 +is_sw: 0 +fetch_stall_cycles: 0 +mem_stall_cycles: 0 +stall_warp: 0 +wspawn: 0 +stalled: 0 +********************************** scheduler ********************************* +valid: 0 +PC: 0 +wid: 1 +rd: -1 rs1: -1 rs2: -1 +is_lw: 0 +is_sw: 0 +fetch_stall_cycles: 0 +mem_stall_cycles: 0 +stall_warp: 0 +wspawn: 0 +stalled: 0 +********************************** Decode ********************************* +valid: 1 +PC: 80000a00 +wid: 0 +rd: 1 rs1: 15 rs2: -1 +is_lw: 0 +is_sw: 0 +fetch_stall_cycles: 0 +mem_stall_cycles: 0 +stall_warp: 1 +wspawn: 0 +stalled: 0 +********************************** Fetch ********************************* +valid: 0 +PC: 0 +wid: 1 +rd: -1 rs1: -1 rs2: -1 +is_lw: 0 +is_sw: 0 +fetch_stall_cycles: 0 +mem_stall_cycles: 0 +stall_warp: 0 +wspawn: 0 +stalled: 0 + + + +------------------------------------------------------ +CYCLE: 338 +Stalled Warps: +1 0 0 0 0 0 0 0 + +********************************** Writeback ********************************* +valid: 0 +PC: 0 +wid: 2 +rd: -1 rs1: -1 rs2: -1 +is_lw: 0 +is_sw: 0 +fetch_stall_cycles: 0 +mem_stall_cycles: 0 +stall_warp: 0 +wspawn: 0 +stalled: 0 +********************************** LSU ********************************* +valid: 0 +PC: 0 +wid: 1 +rd: -1 rs1: -1 rs2: -1 +is_lw: 0 +is_sw: 0 +fetch_stall_cycles: 0 +mem_stall_cycles: 0 +stall_warp: 0 +wspawn: 0 +stalled: 0 +********************************** execute_unit ********************************* +valid: 0 +PC: 0 +wid: 1 +rd: -1 rs1: -1 rs2: -1 +is_lw: 0 +is_sw: 0 +fetch_stall_cycles: 0 +mem_stall_cycles: 0 +stall_warp: 0 +wspawn: 0 +stalled: 0 +********************************** scheduler ********************************* +valid: 1 +PC: 80000a00 +wid: 0 +rd: 1 rs1: 15 rs2: -1 +is_lw: 0 +is_sw: 0 +fetch_stall_cycles: 0 +mem_stall_cycles: 0 +stall_warp: 1 +wspawn: 0 +stalled: 0 +********************************** Decode ********************************* +valid: 0 +PC: 0 +wid: 1 +rd: -1 rs1: -1 rs2: -1 +is_lw: 0 +is_sw: 0 +fetch_stall_cycles: 0 +mem_stall_cycles: 0 +stall_warp: 0 +wspawn: 0 +stalled: 0 +********************************** Fetch ********************************* +valid: 0 +PC: 0 +wid: 2 +rd: -1 rs1: -1 rs2: -1 +is_lw: 0 +is_sw: 0 +fetch_stall_cycles: 0 +mem_stall_cycles: 0 +stall_warp: 0 +wspawn: 0 +stalled: 0 + + + +------------------------------------------------------ +CYCLE: 339 +Stalled Warps: +1 0 0 0 0 0 0 0 + +********************************** Writeback ********************************* +valid: 0 +PC: 0 +wid: 3 +rd: -1 rs1: -1 rs2: -1 +is_lw: 0 +is_sw: 0 +fetch_stall_cycles: 0 +mem_stall_cycles: 0 +stall_warp: 0 +wspawn: 0 +stalled: 0 +********************************** LSU ********************************* +valid: 0 +PC: 0 +wid: 1 +rd: -1 rs1: -1 rs2: -1 +is_lw: 0 +is_sw: 0 +fetch_stall_cycles: 0 +mem_stall_cycles: 0 +stall_warp: 0 +wspawn: 0 +stalled: 0 +********************************** execute_unit ********************************* +valid: 1 +PC: 80000a00 +wid: 0 +rd: 1 rs1: 15 rs2: -1 +is_lw: 0 +is_sw: 0 +fetch_stall_cycles: 0 +mem_stall_cycles: 0 +stall_warp: 1 +wspawn: 0 +stalled: 0 +********************************** scheduler ********************************* +valid: 0 +PC: 0 +wid: 1 +rd: -1 rs1: -1 rs2: -1 +is_lw: 0 +is_sw: 0 +fetch_stall_cycles: 0 +mem_stall_cycles: 0 +stall_warp: 0 +wspawn: 0 +stalled: 0 +********************************** Decode ********************************* +valid: 0 +PC: 0 +wid: 2 +rd: -1 rs1: -1 rs2: -1 +is_lw: 0 +is_sw: 0 +fetch_stall_cycles: 0 +mem_stall_cycles: 0 +stall_warp: 0 +wspawn: 0 +stalled: 0 +********************************** Fetch ********************************* +valid: 0 +PC: 0 +wid: 3 +rd: -1 rs1: -1 rs2: -1 +is_lw: 0 +is_sw: 0 +fetch_stall_cycles: 0 +mem_stall_cycles: 0 +stall_warp: 0 +wspawn: 0 +stalled: 0 + + + +------------------------------------------------------ +CYCLE: 340 +Stalled Warps: +1 0 0 0 0 0 0 0 + +********************************** Writeback ********************************* +valid: 1 +PC: 80000a00 +wid: 0 +rd: 1 rs1: 15 rs2: -1 +is_lw: 0 +is_sw: 0 +fetch_stall_cycles: 0 +mem_stall_cycles: 0 +stall_warp: 1 +wspawn: 0 +stalled: 0 +********************************** LSU ********************************* +valid: 0 +PC: 0 +wid: 1 +rd: -1 rs1: -1 rs2: -1 +is_lw: 0 +is_sw: 0 +fetch_stall_cycles: 0 +mem_stall_cycles: 0 +stall_warp: 0 +wspawn: 0 +stalled: 0 +********************************** execute_unit ********************************* +valid: 0 +PC: 0 +wid: 1 +rd: -1 rs1: -1 rs2: -1 +is_lw: 0 +is_sw: 0 +fetch_stall_cycles: 0 +mem_stall_cycles: 0 +stall_warp: 0 +wspawn: 0 +stalled: 0 +********************************** scheduler ********************************* +valid: 0 +PC: 0 +wid: 2 +rd: -1 rs1: -1 rs2: -1 +is_lw: 0 +is_sw: 0 +fetch_stall_cycles: 0 +mem_stall_cycles: 0 +stall_warp: 0 +wspawn: 0 +stalled: 0 +********************************** Decode ********************************* +valid: 0 +PC: 0 +wid: 3 +rd: -1 rs1: -1 rs2: -1 +is_lw: 0 +is_sw: 0 +fetch_stall_cycles: 0 +mem_stall_cycles: 0 +stall_warp: 0 +wspawn: 0 +stalled: 0 +********************************** Fetch ********************************* +valid: 0 +PC: 0 +wid: 4 +rd: -1 rs1: -1 rs2: -1 +is_lw: 0 +is_sw: 0 +fetch_stall_cycles: 0 +mem_stall_cycles: 0 +stall_warp: 0 +wspawn: 0 +stalled: 0 + + + +------------------------------------------------------ +CYCLE: 341 +Stalled Warps: +1 0 0 0 0 0 0 0 + +********************************** Writeback ********************************* +valid: 0 +PC: 0 +wid: 5 +rd: -1 rs1: -1 rs2: -1 +is_lw: 0 +is_sw: 0 +fetch_stall_cycles: 0 +mem_stall_cycles: 0 +stall_warp: 0 +wspawn: 0 +stalled: 0 +********************************** LSU ********************************* +valid: 0 +PC: 0 +wid: 1 +rd: -1 rs1: -1 rs2: -1 +is_lw: 0 +is_sw: 0 +fetch_stall_cycles: 0 +mem_stall_cycles: 0 +stall_warp: 0 +wspawn: 0 +stalled: 0 +********************************** execute_unit ********************************* +valid: 0 +PC: 0 +wid: 2 +rd: -1 rs1: -1 rs2: -1 +is_lw: 0 +is_sw: 0 +fetch_stall_cycles: 0 +mem_stall_cycles: 0 +stall_warp: 0 +wspawn: 0 +stalled: 0 +********************************** scheduler ********************************* +valid: 0 +PC: 0 +wid: 3 +rd: -1 rs1: -1 rs2: -1 +is_lw: 0 +is_sw: 0 +fetch_stall_cycles: 0 +mem_stall_cycles: 0 +stall_warp: 0 +wspawn: 0 +stalled: 0 +********************************** Decode ********************************* +valid: 0 +PC: 0 +wid: 4 +rd: -1 rs1: -1 rs2: -1 +is_lw: 0 +is_sw: 0 +fetch_stall_cycles: 0 +mem_stall_cycles: 0 +stall_warp: 0 +wspawn: 0 +stalled: 0 +********************************** Fetch ********************************* +valid: 0 +PC: 0 +wid: 5 +rd: -1 rs1: -1 rs2: -1 +is_lw: 0 +is_sw: 0 +fetch_stall_cycles: 0 +mem_stall_cycles: 0 +stall_warp: 0 +wspawn: 0 +stalled: 0 +Warp ID 0 is running + + + +------------------------------------------------------ +CYCLE: 342 +Stalled Warps: +0 0 0 0 0 0 0 0 + +********************************** Writeback ********************************* +valid: 0 +PC: 0 +wid: 0 +rd: -1 rs1: -1 rs2: -1 +is_lw: 0 +is_sw: 0 +fetch_stall_cycles: 0 +mem_stall_cycles: 0 +stall_warp: 0 +wspawn: 0 +stalled: 0 +********************************** LSU ********************************* +valid: 0 +PC: 0 +wid: 1 +rd: -1 rs1: -1 rs2: -1 +is_lw: 0 +is_sw: 0 +fetch_stall_cycles: 0 +mem_stall_cycles: 0 +stall_warp: 0 +wspawn: 0 +stalled: 0 +********************************** execute_unit ********************************* +valid: 0 +PC: 0 +wid: 3 +rd: -1 rs1: -1 rs2: -1 +is_lw: 0 +is_sw: 0 +fetch_stall_cycles: 0 +mem_stall_cycles: 0 +stall_warp: 0 +wspawn: 0 +stalled: 0 +********************************** scheduler ********************************* +valid: 0 +PC: 0 +wid: 4 +rd: -1 rs1: -1 rs2: -1 +is_lw: 0 +is_sw: 0 +fetch_stall_cycles: 0 +mem_stall_cycles: 0 +stall_warp: 0 +wspawn: 0 +stalled: 0 +********************************** Decode ********************************* +valid: 0 +PC: 0 +wid: 5 +rd: -1 rs1: -1 rs2: -1 +is_lw: 0 +is_sw: 0 +fetch_stall_cycles: 0 +mem_stall_cycles: 0 +stall_warp: 0 +wspawn: 0 +stalled: 0 +DEBUG ../core.cpp:386: Core step stepping warp 0[1] +DEBUG ../core.cpp:683: in step pc=0x80000050 +help: in PC: 80000050 +CUrrent CODE: 7b7 +DEBUG ../core.cpp:703: Fetched at 0x80000050 +DEBUG ../core.cpp:704: 0x80000050: lui; +DEBUG ../instruction.cpp:350: Begin instruction execute. +DEBUG ../instruction.cpp:2117: End instruction execute. +DEBUG ../core.cpp:717: Register state: + %r 0: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r 1: 80000a04 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r 2: 6fffeff0 6fffec04 6fffe808 6fffe40c 00000000 00000000 00000000 00000000 (0) + %r 3: 80001808 80001808 80001808 80001808 00000000 00000000 00000000 00000000 (0) + %r 4: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r 5: 80000a6c 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r 6: 0000000f 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r 7: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r 8: 80001004 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r 9: 00000001 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r10: 00000000 00000001 00000001 00000001 00000000 00000000 00000000 00000000 (0) + %r11: 80000924 00000400 00000800 00000c00 00000000 00000000 00000000 00000000 (0) + %r12: 00000000 00000004 00000008 0000000c 00000000 00000000 00000000 00000000 (0) + %r13: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r14: 00000001 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r15: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r16: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r17: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r18: 00000001 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r19: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r20: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r21: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r22: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r23: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r24: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r25: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r26: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r27: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r28: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r29: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r30: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r31: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) +DEBUG ../core.cpp:726: Thread mask: + 1 0 0 0 0 0 0 0 + + +DEBUG ../core.cpp:388: Now 1 active threads in 0 +********************************** Fetch ********************************* +valid: 1 +PC: 80000050 +wid: 0 +rd: 15 rs1: -1 rs2: -1 +is_lw: 0 +is_sw: 0 +fetch_stall_cycles: 3 +mem_stall_cycles: 0 +stall_warp: 0 +wspawn: 0 +stalled: 0 + + + +------------------------------------------------------ +CYCLE: 343 +Stalled Warps: +0 0 0 0 0 0 0 0 + +********************************** Writeback ********************************* +valid: 0 +PC: 0 +wid: 0 +rd: -1 rs1: -1 rs2: -1 +is_lw: 0 +is_sw: 0 +fetch_stall_cycles: 0 +mem_stall_cycles: 0 +stall_warp: 0 +wspawn: 0 +stalled: 0 +********************************** LSU ********************************* +valid: 0 +PC: 0 +wid: 1 +rd: -1 rs1: -1 rs2: -1 +is_lw: 0 +is_sw: 0 +fetch_stall_cycles: 0 +mem_stall_cycles: 0 +stall_warp: 0 +wspawn: 0 +stalled: 0 +********************************** execute_unit ********************************* +valid: 0 +PC: 0 +wid: 4 +rd: -1 rs1: -1 rs2: -1 +is_lw: 0 +is_sw: 0 +fetch_stall_cycles: 0 +mem_stall_cycles: 0 +stall_warp: 0 +wspawn: 0 +stalled: 0 +********************************** scheduler ********************************* +valid: 0 +PC: 0 +wid: 5 +rd: -1 rs1: -1 rs2: -1 +is_lw: 0 +is_sw: 0 +fetch_stall_cycles: 0 +mem_stall_cycles: 0 +stall_warp: 0 +wspawn: 0 +stalled: 0 +********************************** Decode ********************************* +valid: 0 +PC: 0 +wid: 0 +rd: -1 rs1: -1 rs2: -1 +is_lw: 0 +is_sw: 0 +fetch_stall_cycles: 0 +mem_stall_cycles: 0 +stall_warp: 0 +wspawn: 0 +stalled: 0 +********************************** Fetch ********************************* +valid: 1 +PC: 80000050 +wid: 0 +rd: 15 rs1: -1 rs2: -1 +is_lw: 0 +is_sw: 0 +fetch_stall_cycles: 2 +mem_stall_cycles: 0 +stall_warp: 0 +wspawn: 0 +stalled: 0 + + + +------------------------------------------------------ +CYCLE: 344 +Stalled Warps: +0 0 0 0 0 0 0 0 + +********************************** Writeback ********************************* +valid: 0 +PC: 0 +wid: 0 +rd: -1 rs1: -1 rs2: -1 +is_lw: 0 +is_sw: 0 +fetch_stall_cycles: 0 +mem_stall_cycles: 0 +stall_warp: 0 +wspawn: 0 +stalled: 0 +********************************** LSU ********************************* +valid: 0 +PC: 0 +wid: 1 +rd: -1 rs1: -1 rs2: -1 +is_lw: 0 +is_sw: 0 +fetch_stall_cycles: 0 +mem_stall_cycles: 0 +stall_warp: 0 +wspawn: 0 +stalled: 0 +********************************** execute_unit ********************************* +valid: 0 +PC: 0 +wid: 5 +rd: -1 rs1: -1 rs2: -1 +is_lw: 0 +is_sw: 0 +fetch_stall_cycles: 0 +mem_stall_cycles: 0 +stall_warp: 0 +wspawn: 0 +stalled: 0 +********************************** scheduler ********************************* +valid: 0 +PC: 0 +wid: 0 +rd: -1 rs1: -1 rs2: -1 +is_lw: 0 +is_sw: 0 +fetch_stall_cycles: 0 +mem_stall_cycles: 0 +stall_warp: 0 +wspawn: 0 +stalled: 0 +********************************** Decode ********************************* +valid: 0 +PC: 0 +wid: 0 +rd: -1 rs1: -1 rs2: -1 +is_lw: 0 +is_sw: 0 +fetch_stall_cycles: 0 +mem_stall_cycles: 0 +stall_warp: 0 +wspawn: 0 +stalled: 0 +********************************** Fetch ********************************* +valid: 1 +PC: 80000050 +wid: 0 +rd: 15 rs1: -1 rs2: -1 +is_lw: 0 +is_sw: 0 +fetch_stall_cycles: 1 +mem_stall_cycles: 0 +stall_warp: 0 +wspawn: 0 +stalled: 0 + + + +------------------------------------------------------ +CYCLE: 345 +Stalled Warps: +0 0 0 0 0 0 0 0 + +********************************** Writeback ********************************* +valid: 0 +PC: 0 +wid: 0 +rd: -1 rs1: -1 rs2: -1 +is_lw: 0 +is_sw: 0 +fetch_stall_cycles: 0 +mem_stall_cycles: 0 +stall_warp: 0 +wspawn: 0 +stalled: 0 +********************************** LSU ********************************* +valid: 0 +PC: 0 +wid: 1 +rd: -1 rs1: -1 rs2: -1 +is_lw: 0 +is_sw: 0 +fetch_stall_cycles: 0 +mem_stall_cycles: 0 +stall_warp: 0 +wspawn: 0 +stalled: 0 +********************************** execute_unit ********************************* +valid: 0 +PC: 0 +wid: 0 +rd: -1 rs1: -1 rs2: -1 +is_lw: 0 +is_sw: 0 +fetch_stall_cycles: 0 +mem_stall_cycles: 0 +stall_warp: 0 +wspawn: 0 +stalled: 0 +********************************** scheduler ********************************* +valid: 0 +PC: 0 +wid: 0 +rd: -1 rs1: -1 rs2: -1 +is_lw: 0 +is_sw: 0 +fetch_stall_cycles: 0 +mem_stall_cycles: 0 +stall_warp: 0 +wspawn: 0 +stalled: 0 +********************************** Decode ********************************* +valid: 0 +PC: 0 +wid: 0 +rd: -1 rs1: -1 rs2: -1 +is_lw: 0 +is_sw: 0 +fetch_stall_cycles: 0 +mem_stall_cycles: 0 +stall_warp: 0 +wspawn: 0 +stalled: 0 +********************************** Fetch ********************************* +valid: 1 +PC: 80000050 +wid: 0 +rd: 15 rs1: -1 rs2: -1 +is_lw: 0 +is_sw: 0 +fetch_stall_cycles: 0 +mem_stall_cycles: 0 +stall_warp: 0 +wspawn: 0 +stalled: 0 + + + +------------------------------------------------------ +CYCLE: 346 +Stalled Warps: +0 0 0 0 0 0 0 0 + +********************************** Writeback ********************************* +valid: 0 +PC: 0 +wid: 0 +rd: -1 rs1: -1 rs2: -1 +is_lw: 0 +is_sw: 0 +fetch_stall_cycles: 0 +mem_stall_cycles: 0 +stall_warp: 0 +wspawn: 0 +stalled: 0 +********************************** LSU ********************************* +valid: 0 +PC: 0 +wid: 1 +rd: -1 rs1: -1 rs2: -1 +is_lw: 0 +is_sw: 0 +fetch_stall_cycles: 0 +mem_stall_cycles: 0 +stall_warp: 0 +wspawn: 0 +stalled: 0 +********************************** execute_unit ********************************* +valid: 0 +PC: 0 +wid: 0 +rd: -1 rs1: -1 rs2: -1 +is_lw: 0 +is_sw: 0 +fetch_stall_cycles: 0 +mem_stall_cycles: 0 +stall_warp: 0 +wspawn: 0 +stalled: 0 +********************************** scheduler ********************************* +valid: 0 +PC: 0 +wid: 0 +rd: -1 rs1: -1 rs2: -1 +is_lw: 0 +is_sw: 0 +fetch_stall_cycles: 0 +mem_stall_cycles: 0 +stall_warp: 0 +wspawn: 0 +stalled: 0 +********************************** Decode ********************************* +valid: 1 +PC: 80000050 +wid: 0 +rd: 15 rs1: -1 rs2: -1 +is_lw: 0 +is_sw: 0 +fetch_stall_cycles: 0 +mem_stall_cycles: 0 +stall_warp: 0 +wspawn: 0 +stalled: 0 +DEBUG ../core.cpp:386: Core step stepping warp 0[1] +DEBUG ../core.cpp:683: in step pc=0x80000054 +help: in PC: 80000054 +CUrrent CODE: 78793 +DEBUG ../core.cpp:703: Fetched at 0x80000054 +DEBUG ../core.cpp:704: 0x80000054: i_type; +DEBUG ../instruction.cpp:350: Begin instruction execute. +DEBUG ../instruction.cpp:2117: End instruction execute. +DEBUG ../core.cpp:717: Register state: + %r 0: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r 1: 80000a04 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r 2: 6fffeff0 6fffec04 6fffe808 6fffe40c 00000000 00000000 00000000 00000000 (0) + %r 3: 80001808 80001808 80001808 80001808 00000000 00000000 00000000 00000000 (0) + %r 4: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r 5: 80000a6c 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r 6: 0000000f 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r 7: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r 8: 80001004 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r 9: 00000001 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r10: 00000000 00000001 00000001 00000001 00000000 00000000 00000000 00000000 (0) + %r11: 80000924 00000400 00000800 00000c00 00000000 00000000 00000000 00000000 (0) + %r12: 00000000 00000004 00000008 0000000c 00000000 00000000 00000000 00000000 (0) + %r13: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r14: 00000001 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r15: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r16: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r17: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r18: 00000001 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r19: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r20: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r21: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r22: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r23: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r24: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r25: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r26: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r27: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r28: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r29: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r30: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r31: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) +DEBUG ../core.cpp:726: Thread mask: + 1 0 0 0 0 0 0 0 + + +DEBUG ../core.cpp:388: Now 1 active threads in 0 +********************************** Fetch ********************************* +valid: 1 +PC: 80000054 +wid: 0 +rd: 15 rs1: 15 rs2: -1 +is_lw: 0 +is_sw: 0 +fetch_stall_cycles: 0 +mem_stall_cycles: 0 +stall_warp: 0 +wspawn: 0 +stalled: 0 + + + +------------------------------------------------------ +CYCLE: 347 +Stalled Warps: +0 0 0 0 0 0 0 0 + +********************************** Writeback ********************************* +valid: 0 +PC: 0 +wid: 0 +rd: -1 rs1: -1 rs2: -1 +is_lw: 0 +is_sw: 0 +fetch_stall_cycles: 0 +mem_stall_cycles: 0 +stall_warp: 0 +wspawn: 0 +stalled: 0 +********************************** LSU ********************************* +valid: 0 +PC: 0 +wid: 1 +rd: -1 rs1: -1 rs2: -1 +is_lw: 0 +is_sw: 0 +fetch_stall_cycles: 0 +mem_stall_cycles: 0 +stall_warp: 0 +wspawn: 0 +stalled: 0 +********************************** execute_unit ********************************* +valid: 0 +PC: 0 +wid: 0 +rd: -1 rs1: -1 rs2: -1 +is_lw: 0 +is_sw: 0 +fetch_stall_cycles: 0 +mem_stall_cycles: 0 +stall_warp: 0 +wspawn: 0 +stalled: 0 +********************************** scheduler ********************************* +valid: 1 +PC: 80000050 +wid: 0 +rd: 15 rs1: -1 rs2: -1 +is_lw: 0 +is_sw: 0 +fetch_stall_cycles: 0 +mem_stall_cycles: 0 +stall_warp: 0 +wspawn: 0 +stalled: 0 +********************************** Decode ********************************* +valid: 1 +PC: 80000054 +wid: 0 +rd: 15 rs1: 15 rs2: -1 +is_lw: 0 +is_sw: 0 +fetch_stall_cycles: 0 +mem_stall_cycles: 0 +stall_warp: 0 +wspawn: 0 +stalled: 0 +DEBUG ../core.cpp:386: Core step stepping warp 0[1] +DEBUG ../core.cpp:683: in step pc=0x80000058 +help: in PC: 80000058 +CUrrent CODE: 78863 +DEBUG ../core.cpp:703: Fetched at 0x80000058 +DEBUG ../core.cpp:704: 0x80000058: branch; +DEBUG ../instruction.cpp:350: Begin instruction execute. +DEBUG ../instruction.cpp:2117: End instruction execute. +Next PC: 80000068 +DEBUG ../core.cpp:717: Register state: + %r 0: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r 1: 80000a04 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r 2: 6fffeff0 6fffec04 6fffe808 6fffe40c 00000000 00000000 00000000 00000000 (0) + %r 3: 80001808 80001808 80001808 80001808 00000000 00000000 00000000 00000000 (0) + %r 4: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r 5: 80000a6c 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r 6: 0000000f 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r 7: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r 8: 80001004 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r 9: 00000001 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r10: 00000000 00000001 00000001 00000001 00000000 00000000 00000000 00000000 (0) + %r11: 80000924 00000400 00000800 00000c00 00000000 00000000 00000000 00000000 (0) + %r12: 00000000 00000004 00000008 0000000c 00000000 00000000 00000000 00000000 (0) + %r13: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r14: 00000001 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r15: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r16: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r17: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r18: 00000001 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r19: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r20: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r21: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r22: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r23: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r24: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r25: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r26: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r27: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r28: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r29: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r30: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r31: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) +DEBUG ../core.cpp:726: Thread mask: + 1 0 0 0 0 0 0 0 + + +DEBUG ../core.cpp:388: Now 1 active threads in 0 +********************************** Fetch ********************************* +valid: 1 +PC: 80000058 +wid: 0 +rd: -1 rs1: 15 rs2: 0 +is_lw: 0 +is_sw: 0 +fetch_stall_cycles: 0 +mem_stall_cycles: 0 +stall_warp: 1 +wspawn: 0 +stalled: 0 + + + +------------------------------------------------------ +CYCLE: 348 +Stalled Warps: +1 0 0 0 0 0 0 0 + +********************************** Writeback ********************************* +valid: 0 +PC: 0 +wid: 1 +rd: -1 rs1: -1 rs2: -1 +is_lw: 0 +is_sw: 0 +fetch_stall_cycles: 0 +mem_stall_cycles: 0 +stall_warp: 0 +wspawn: 0 +stalled: 0 +********************************** LSU ********************************* +valid: 0 +PC: 0 +wid: 1 +rd: -1 rs1: -1 rs2: -1 +is_lw: 0 +is_sw: 0 +fetch_stall_cycles: 0 +mem_stall_cycles: 0 +stall_warp: 0 +wspawn: 0 +stalled: 0 +********************************** execute_unit ********************************* +valid: 1 +PC: 80000050 +wid: 0 +rd: 15 rs1: -1 rs2: -1 +is_lw: 0 +is_sw: 0 +fetch_stall_cycles: 0 +mem_stall_cycles: 0 +stall_warp: 0 +wspawn: 0 +stalled: 0 +********************************** scheduler ********************************* +valid: 1 +PC: 80000054 +wid: 0 +rd: 15 rs1: 15 rs2: -1 +is_lw: 0 +is_sw: 0 +fetch_stall_cycles: 0 +mem_stall_cycles: 0 +stall_warp: 0 +wspawn: 0 +stalled: 0 +********************************** Decode ********************************* +valid: 1 +PC: 80000058 +wid: 0 +rd: -1 rs1: 15 rs2: 0 +is_lw: 0 +is_sw: 0 +fetch_stall_cycles: 0 +mem_stall_cycles: 0 +stall_warp: 1 +wspawn: 0 +stalled: 0 +********************************** Fetch ********************************* +valid: 0 +PC: 0 +wid: 1 +rd: -1 rs1: -1 rs2: -1 +is_lw: 0 +is_sw: 0 +fetch_stall_cycles: 0 +mem_stall_cycles: 0 +stall_warp: 0 +wspawn: 0 +stalled: 0 + + + +------------------------------------------------------ +CYCLE: 349 +Stalled Warps: +1 0 0 0 0 0 0 0 + +********************************** Writeback ********************************* +valid: 1 +PC: 80000050 +wid: 0 +rd: 15 rs1: -1 rs2: -1 +is_lw: 0 +is_sw: 0 +fetch_stall_cycles: 0 +mem_stall_cycles: 0 +stall_warp: 0 +wspawn: 0 +stalled: 0 +********************************** LSU ********************************* +valid: 0 +PC: 0 +wid: 1 +rd: -1 rs1: -1 rs2: -1 +is_lw: 0 +is_sw: 0 +fetch_stall_cycles: 0 +mem_stall_cycles: 0 +stall_warp: 0 +wspawn: 0 +stalled: 0 +&&&&&&&&&&&&&&&&&&&&&&&& EXECUTE SRCS NOT READY +********************************** execute_unit ********************************* +valid: 0 +PC: 0 +wid: 2 +rd: -1 rs1: -1 rs2: -1 +is_lw: 0 +is_sw: 0 +fetch_stall_cycles: 0 +mem_stall_cycles: 0 +stall_warp: 0 +wspawn: 0 +stalled: 0 +********************************** scheduler ********************************* +valid: 1 +PC: 80000054 +wid: 0 +rd: 15 rs1: 15 rs2: -1 +is_lw: 0 +is_sw: 0 +fetch_stall_cycles: 0 +mem_stall_cycles: 0 +stall_warp: 0 +wspawn: 0 +stalled: 1 +********************************** Decode ********************************* +valid: 1 +PC: 80000058 +wid: 0 +rd: -1 rs1: 15 rs2: 0 +is_lw: 0 +is_sw: 0 +fetch_stall_cycles: 0 +mem_stall_cycles: 0 +stall_warp: 1 +wspawn: 0 +stalled: 0 +********************************** Fetch ********************************* +valid: 0 +PC: 0 +wid: 1 +rd: -1 rs1: -1 rs2: -1 +is_lw: 0 +is_sw: 0 +fetch_stall_cycles: 0 +mem_stall_cycles: 0 +stall_warp: 0 +wspawn: 0 +stalled: 0 + + + +------------------------------------------------------ +CYCLE: 350 +Stalled Warps: +1 0 0 0 0 0 0 0 + +********************************** Writeback ********************************* +valid: 0 +PC: 0 +wid: 2 +rd: -1 rs1: -1 rs2: -1 +is_lw: 0 +is_sw: 0 +fetch_stall_cycles: 0 +mem_stall_cycles: 0 +stall_warp: 0 +wspawn: 0 +stalled: 0 +********************************** LSU ********************************* +valid: 0 +PC: 0 +wid: 1 +rd: -1 rs1: -1 rs2: -1 +is_lw: 0 +is_sw: 0 +fetch_stall_cycles: 0 +mem_stall_cycles: 0 +stall_warp: 0 +wspawn: 0 +stalled: 0 +********************************** execute_unit ********************************* +valid: 1 +PC: 80000054 +wid: 0 +rd: 15 rs1: 15 rs2: -1 +is_lw: 0 +is_sw: 0 +fetch_stall_cycles: 0 +mem_stall_cycles: 0 +stall_warp: 0 +wspawn: 0 +stalled: 0 +********************************** scheduler ********************************* +valid: 1 +PC: 80000058 +wid: 0 +rd: -1 rs1: 15 rs2: 0 +is_lw: 0 +is_sw: 0 +fetch_stall_cycles: 0 +mem_stall_cycles: 0 +stall_warp: 1 +wspawn: 0 +stalled: 0 +********************************** Decode ********************************* +valid: 0 +PC: 0 +wid: 1 +rd: -1 rs1: -1 rs2: -1 +is_lw: 0 +is_sw: 0 +fetch_stall_cycles: 0 +mem_stall_cycles: 0 +stall_warp: 0 +wspawn: 0 +stalled: 0 +********************************** Fetch ********************************* +valid: 0 +PC: 0 +wid: 2 +rd: -1 rs1: -1 rs2: -1 +is_lw: 0 +is_sw: 0 +fetch_stall_cycles: 0 +mem_stall_cycles: 0 +stall_warp: 0 +wspawn: 0 +stalled: 0 + + + +------------------------------------------------------ +CYCLE: 351 +Stalled Warps: +1 0 0 0 0 0 0 0 + +********************************** Writeback ********************************* +valid: 1 +PC: 80000054 +wid: 0 +rd: 15 rs1: 15 rs2: -1 +is_lw: 0 +is_sw: 0 +fetch_stall_cycles: 0 +mem_stall_cycles: 0 +stall_warp: 0 +wspawn: 0 +stalled: 0 +********************************** LSU ********************************* +valid: 0 +PC: 0 +wid: 1 +rd: -1 rs1: -1 rs2: -1 +is_lw: 0 +is_sw: 0 +fetch_stall_cycles: 0 +mem_stall_cycles: 0 +stall_warp: 0 +wspawn: 0 +stalled: 0 +&&&&&&&&&&&&&&&&&&&&&&&& EXECUTE SRCS NOT READY +********************************** execute_unit ********************************* +valid: 0 +PC: 0 +wid: 3 +rd: -1 rs1: -1 rs2: -1 +is_lw: 0 +is_sw: 0 +fetch_stall_cycles: 0 +mem_stall_cycles: 0 +stall_warp: 0 +wspawn: 0 +stalled: 0 +********************************** scheduler ********************************* +valid: 1 +PC: 80000058 +wid: 0 +rd: -1 rs1: 15 rs2: 0 +is_lw: 0 +is_sw: 0 +fetch_stall_cycles: 0 +mem_stall_cycles: 0 +stall_warp: 1 +wspawn: 0 +stalled: 1 +********************************** Decode ********************************* +valid: 0 +PC: 0 +wid: 1 +rd: -1 rs1: -1 rs2: -1 +is_lw: 0 +is_sw: 0 +fetch_stall_cycles: 0 +mem_stall_cycles: 0 +stall_warp: 0 +wspawn: 0 +stalled: 0 +********************************** Fetch ********************************* +valid: 0 +PC: 0 +wid: 2 +rd: -1 rs1: -1 rs2: -1 +is_lw: 0 +is_sw: 0 +fetch_stall_cycles: 0 +mem_stall_cycles: 0 +stall_warp: 0 +wspawn: 0 +stalled: 0 + + + +------------------------------------------------------ +CYCLE: 352 +Stalled Warps: +1 0 0 0 0 0 0 0 + +********************************** Writeback ********************************* +valid: 0 +PC: 0 +wid: 3 +rd: -1 rs1: -1 rs2: -1 +is_lw: 0 +is_sw: 0 +fetch_stall_cycles: 0 +mem_stall_cycles: 0 +stall_warp: 0 +wspawn: 0 +stalled: 0 +********************************** LSU ********************************* +valid: 0 +PC: 0 +wid: 1 +rd: -1 rs1: -1 rs2: -1 +is_lw: 0 +is_sw: 0 +fetch_stall_cycles: 0 +mem_stall_cycles: 0 +stall_warp: 0 +wspawn: 0 +stalled: 0 +********************************** execute_unit ********************************* +valid: 1 +PC: 80000058 +wid: 0 +rd: -1 rs1: 15 rs2: 0 +is_lw: 0 +is_sw: 0 +fetch_stall_cycles: 0 +mem_stall_cycles: 0 +stall_warp: 1 +wspawn: 0 +stalled: 0 +********************************** scheduler ********************************* +valid: 0 +PC: 0 +wid: 1 +rd: -1 rs1: -1 rs2: -1 +is_lw: 0 +is_sw: 0 +fetch_stall_cycles: 0 +mem_stall_cycles: 0 +stall_warp: 0 +wspawn: 0 +stalled: 0 +********************************** Decode ********************************* +valid: 0 +PC: 0 +wid: 2 +rd: -1 rs1: -1 rs2: -1 +is_lw: 0 +is_sw: 0 +fetch_stall_cycles: 0 +mem_stall_cycles: 0 +stall_warp: 0 +wspawn: 0 +stalled: 0 +********************************** Fetch ********************************* +valid: 0 +PC: 0 +wid: 3 +rd: -1 rs1: -1 rs2: -1 +is_lw: 0 +is_sw: 0 +fetch_stall_cycles: 0 +mem_stall_cycles: 0 +stall_warp: 0 +wspawn: 0 +stalled: 0 + + + +------------------------------------------------------ +CYCLE: 353 +Stalled Warps: +1 0 0 0 0 0 0 0 + +********************************** Writeback ********************************* +valid: 1 +PC: 80000058 +wid: 0 +rd: -1 rs1: 15 rs2: 0 +is_lw: 0 +is_sw: 0 +fetch_stall_cycles: 0 +mem_stall_cycles: 0 +stall_warp: 1 +wspawn: 0 +stalled: 0 +********************************** LSU ********************************* +valid: 0 +PC: 0 +wid: 1 +rd: -1 rs1: -1 rs2: -1 +is_lw: 0 +is_sw: 0 +fetch_stall_cycles: 0 +mem_stall_cycles: 0 +stall_warp: 0 +wspawn: 0 +stalled: 0 +********************************** execute_unit ********************************* +valid: 0 +PC: 0 +wid: 1 +rd: -1 rs1: -1 rs2: -1 +is_lw: 0 +is_sw: 0 +fetch_stall_cycles: 0 +mem_stall_cycles: 0 +stall_warp: 0 +wspawn: 0 +stalled: 0 +********************************** scheduler ********************************* +valid: 0 +PC: 0 +wid: 2 +rd: -1 rs1: -1 rs2: -1 +is_lw: 0 +is_sw: 0 +fetch_stall_cycles: 0 +mem_stall_cycles: 0 +stall_warp: 0 +wspawn: 0 +stalled: 0 +********************************** Decode ********************************* +valid: 0 +PC: 0 +wid: 3 +rd: -1 rs1: -1 rs2: -1 +is_lw: 0 +is_sw: 0 +fetch_stall_cycles: 0 +mem_stall_cycles: 0 +stall_warp: 0 +wspawn: 0 +stalled: 0 +********************************** Fetch ********************************* +valid: 0 +PC: 0 +wid: 4 +rd: -1 rs1: -1 rs2: -1 +is_lw: 0 +is_sw: 0 +fetch_stall_cycles: 0 +mem_stall_cycles: 0 +stall_warp: 0 +wspawn: 0 +stalled: 0 + + + +------------------------------------------------------ +CYCLE: 354 +Stalled Warps: +1 0 0 0 0 0 0 0 + +********************************** Writeback ********************************* +valid: 0 +PC: 0 +wid: 5 +rd: -1 rs1: -1 rs2: -1 +is_lw: 0 +is_sw: 0 +fetch_stall_cycles: 0 +mem_stall_cycles: 0 +stall_warp: 0 +wspawn: 0 +stalled: 0 +********************************** LSU ********************************* +valid: 0 +PC: 0 +wid: 1 +rd: -1 rs1: -1 rs2: -1 +is_lw: 0 +is_sw: 0 +fetch_stall_cycles: 0 +mem_stall_cycles: 0 +stall_warp: 0 +wspawn: 0 +stalled: 0 +********************************** execute_unit ********************************* +valid: 0 +PC: 0 +wid: 2 +rd: -1 rs1: -1 rs2: -1 +is_lw: 0 +is_sw: 0 +fetch_stall_cycles: 0 +mem_stall_cycles: 0 +stall_warp: 0 +wspawn: 0 +stalled: 0 +********************************** scheduler ********************************* +valid: 0 +PC: 0 +wid: 3 +rd: -1 rs1: -1 rs2: -1 +is_lw: 0 +is_sw: 0 +fetch_stall_cycles: 0 +mem_stall_cycles: 0 +stall_warp: 0 +wspawn: 0 +stalled: 0 +********************************** Decode ********************************* +valid: 0 +PC: 0 +wid: 4 +rd: -1 rs1: -1 rs2: -1 +is_lw: 0 +is_sw: 0 +fetch_stall_cycles: 0 +mem_stall_cycles: 0 +stall_warp: 0 +wspawn: 0 +stalled: 0 +********************************** Fetch ********************************* +valid: 0 +PC: 0 +wid: 5 +rd: -1 rs1: -1 rs2: -1 +is_lw: 0 +is_sw: 0 +fetch_stall_cycles: 0 +mem_stall_cycles: 0 +stall_warp: 0 +wspawn: 0 +stalled: 0 +Warp ID 0 is running + + + +------------------------------------------------------ +CYCLE: 355 +Stalled Warps: +0 0 0 0 0 0 0 0 + +********************************** Writeback ********************************* +valid: 0 +PC: 0 +wid: 0 +rd: -1 rs1: -1 rs2: -1 +is_lw: 0 +is_sw: 0 +fetch_stall_cycles: 0 +mem_stall_cycles: 0 +stall_warp: 0 +wspawn: 0 +stalled: 0 +********************************** LSU ********************************* +valid: 0 +PC: 0 +wid: 1 +rd: -1 rs1: -1 rs2: -1 +is_lw: 0 +is_sw: 0 +fetch_stall_cycles: 0 +mem_stall_cycles: 0 +stall_warp: 0 +wspawn: 0 +stalled: 0 +********************************** execute_unit ********************************* +valid: 0 +PC: 0 +wid: 3 +rd: -1 rs1: -1 rs2: -1 +is_lw: 0 +is_sw: 0 +fetch_stall_cycles: 0 +mem_stall_cycles: 0 +stall_warp: 0 +wspawn: 0 +stalled: 0 +********************************** scheduler ********************************* +valid: 0 +PC: 0 +wid: 4 +rd: -1 rs1: -1 rs2: -1 +is_lw: 0 +is_sw: 0 +fetch_stall_cycles: 0 +mem_stall_cycles: 0 +stall_warp: 0 +wspawn: 0 +stalled: 0 +********************************** Decode ********************************* +valid: 0 +PC: 0 +wid: 5 +rd: -1 rs1: -1 rs2: -1 +is_lw: 0 +is_sw: 0 +fetch_stall_cycles: 0 +mem_stall_cycles: 0 +stall_warp: 0 +wspawn: 0 +stalled: 0 +DEBUG ../core.cpp:386: Core step stepping warp 0[1] +DEBUG ../core.cpp:683: in step pc=0x80000068 +help: in PC: 80000068 +CUrrent CODE: 8067 +DEBUG ../core.cpp:703: Fetched at 0x80000068 +DEBUG ../core.cpp:704: 0x80000068: jalr; +DEBUG ../instruction.cpp:350: Begin instruction execute. +JALR_INST +DEBUG ../instruction.cpp:2117: End instruction execute. +Next PC: 80000a04 +DEBUG ../core.cpp:717: Register state: + %r 0: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r 1: 80000a04 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r 2: 6fffeff0 6fffec04 6fffe808 6fffe40c 00000000 00000000 00000000 00000000 (0) + %r 3: 80001808 80001808 80001808 80001808 00000000 00000000 00000000 00000000 (0) + %r 4: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r 5: 80000a6c 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r 6: 0000000f 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r 7: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r 8: 80001004 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r 9: 00000001 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r10: 00000000 00000001 00000001 00000001 00000000 00000000 00000000 00000000 (0) + %r11: 80000924 00000400 00000800 00000c00 00000000 00000000 00000000 00000000 (0) + %r12: 00000000 00000004 00000008 0000000c 00000000 00000000 00000000 00000000 (0) + %r13: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r14: 00000001 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r15: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r16: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r17: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r18: 00000001 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r19: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r20: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r21: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r22: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r23: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r24: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r25: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r26: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r27: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r28: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r29: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r30: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r31: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) +DEBUG ../core.cpp:726: Thread mask: + 1 0 0 0 0 0 0 0 + + +DEBUG ../core.cpp:388: Now 1 active threads in 0 +********************************** Fetch ********************************* +valid: 1 +PC: 80000068 +wid: 0 +rd: 0 rs1: 1 rs2: -1 +is_lw: 0 +is_sw: 0 +fetch_stall_cycles: 0 +mem_stall_cycles: 0 +stall_warp: 1 +wspawn: 0 +stalled: 0 + + + +------------------------------------------------------ +CYCLE: 356 +Stalled Warps: +1 0 0 0 0 0 0 0 + +********************************** Writeback ********************************* +valid: 0 +PC: 0 +wid: 1 +rd: -1 rs1: -1 rs2: -1 +is_lw: 0 +is_sw: 0 +fetch_stall_cycles: 0 +mem_stall_cycles: 0 +stall_warp: 0 +wspawn: 0 +stalled: 0 +********************************** LSU ********************************* +valid: 0 +PC: 0 +wid: 1 +rd: -1 rs1: -1 rs2: -1 +is_lw: 0 +is_sw: 0 +fetch_stall_cycles: 0 +mem_stall_cycles: 0 +stall_warp: 0 +wspawn: 0 +stalled: 0 +********************************** execute_unit ********************************* +valid: 0 +PC: 0 +wid: 4 +rd: -1 rs1: -1 rs2: -1 +is_lw: 0 +is_sw: 0 +fetch_stall_cycles: 0 +mem_stall_cycles: 0 +stall_warp: 0 +wspawn: 0 +stalled: 0 +********************************** scheduler ********************************* +valid: 0 +PC: 0 +wid: 5 +rd: -1 rs1: -1 rs2: -1 +is_lw: 0 +is_sw: 0 +fetch_stall_cycles: 0 +mem_stall_cycles: 0 +stall_warp: 0 +wspawn: 0 +stalled: 0 +********************************** Decode ********************************* +valid: 1 +PC: 80000068 +wid: 0 +rd: 0 rs1: 1 rs2: -1 +is_lw: 0 +is_sw: 0 +fetch_stall_cycles: 0 +mem_stall_cycles: 0 +stall_warp: 1 +wspawn: 0 +stalled: 0 +********************************** Fetch ********************************* +valid: 0 +PC: 0 +wid: 1 +rd: -1 rs1: -1 rs2: -1 +is_lw: 0 +is_sw: 0 +fetch_stall_cycles: 0 +mem_stall_cycles: 0 +stall_warp: 0 +wspawn: 0 +stalled: 0 + + + +------------------------------------------------------ +CYCLE: 357 +Stalled Warps: +1 0 0 0 0 0 0 0 + +********************************** Writeback ********************************* +valid: 0 +PC: 0 +wid: 2 +rd: -1 rs1: -1 rs2: -1 +is_lw: 0 +is_sw: 0 +fetch_stall_cycles: 0 +mem_stall_cycles: 0 +stall_warp: 0 +wspawn: 0 +stalled: 0 +********************************** LSU ********************************* +valid: 0 +PC: 0 +wid: 1 +rd: -1 rs1: -1 rs2: -1 +is_lw: 0 +is_sw: 0 +fetch_stall_cycles: 0 +mem_stall_cycles: 0 +stall_warp: 0 +wspawn: 0 +stalled: 0 +********************************** execute_unit ********************************* +valid: 0 +PC: 0 +wid: 5 +rd: -1 rs1: -1 rs2: -1 +is_lw: 0 +is_sw: 0 +fetch_stall_cycles: 0 +mem_stall_cycles: 0 +stall_warp: 0 +wspawn: 0 +stalled: 0 +********************************** scheduler ********************************* +valid: 1 +PC: 80000068 +wid: 0 +rd: 0 rs1: 1 rs2: -1 +is_lw: 0 +is_sw: 0 +fetch_stall_cycles: 0 +mem_stall_cycles: 0 +stall_warp: 1 +wspawn: 0 +stalled: 0 +********************************** Decode ********************************* +valid: 0 +PC: 0 +wid: 1 +rd: -1 rs1: -1 rs2: -1 +is_lw: 0 +is_sw: 0 +fetch_stall_cycles: 0 +mem_stall_cycles: 0 +stall_warp: 0 +wspawn: 0 +stalled: 0 +********************************** Fetch ********************************* +valid: 0 +PC: 0 +wid: 2 +rd: -1 rs1: -1 rs2: -1 +is_lw: 0 +is_sw: 0 +fetch_stall_cycles: 0 +mem_stall_cycles: 0 +stall_warp: 0 +wspawn: 0 +stalled: 0 + + + +------------------------------------------------------ +CYCLE: 358 +Stalled Warps: +1 0 0 0 0 0 0 0 + +********************************** Writeback ********************************* +valid: 0 +PC: 0 +wid: 3 +rd: -1 rs1: -1 rs2: -1 +is_lw: 0 +is_sw: 0 +fetch_stall_cycles: 0 +mem_stall_cycles: 0 +stall_warp: 0 +wspawn: 0 +stalled: 0 +********************************** LSU ********************************* +valid: 0 +PC: 0 +wid: 1 +rd: -1 rs1: -1 rs2: -1 +is_lw: 0 +is_sw: 0 +fetch_stall_cycles: 0 +mem_stall_cycles: 0 +stall_warp: 0 +wspawn: 0 +stalled: 0 +********************************** execute_unit ********************************* +valid: 1 +PC: 80000068 +wid: 0 +rd: 0 rs1: 1 rs2: -1 +is_lw: 0 +is_sw: 0 +fetch_stall_cycles: 0 +mem_stall_cycles: 0 +stall_warp: 1 +wspawn: 0 +stalled: 0 +********************************** scheduler ********************************* +valid: 0 +PC: 0 +wid: 1 +rd: -1 rs1: -1 rs2: -1 +is_lw: 0 +is_sw: 0 +fetch_stall_cycles: 0 +mem_stall_cycles: 0 +stall_warp: 0 +wspawn: 0 +stalled: 0 +********************************** Decode ********************************* +valid: 0 +PC: 0 +wid: 2 +rd: -1 rs1: -1 rs2: -1 +is_lw: 0 +is_sw: 0 +fetch_stall_cycles: 0 +mem_stall_cycles: 0 +stall_warp: 0 +wspawn: 0 +stalled: 0 +********************************** Fetch ********************************* +valid: 0 +PC: 0 +wid: 3 +rd: -1 rs1: -1 rs2: -1 +is_lw: 0 +is_sw: 0 +fetch_stall_cycles: 0 +mem_stall_cycles: 0 +stall_warp: 0 +wspawn: 0 +stalled: 0 + + + +------------------------------------------------------ +CYCLE: 359 +Stalled Warps: +1 0 0 0 0 0 0 0 + +********************************** Writeback ********************************* +valid: 1 +PC: 80000068 +wid: 0 +rd: 0 rs1: 1 rs2: -1 +is_lw: 0 +is_sw: 0 +fetch_stall_cycles: 0 +mem_stall_cycles: 0 +stall_warp: 1 +wspawn: 0 +stalled: 0 +********************************** LSU ********************************* +valid: 0 +PC: 0 +wid: 1 +rd: -1 rs1: -1 rs2: -1 +is_lw: 0 +is_sw: 0 +fetch_stall_cycles: 0 +mem_stall_cycles: 0 +stall_warp: 0 +wspawn: 0 +stalled: 0 +********************************** execute_unit ********************************* +valid: 0 +PC: 0 +wid: 1 +rd: -1 rs1: -1 rs2: -1 +is_lw: 0 +is_sw: 0 +fetch_stall_cycles: 0 +mem_stall_cycles: 0 +stall_warp: 0 +wspawn: 0 +stalled: 0 +********************************** scheduler ********************************* +valid: 0 +PC: 0 +wid: 2 +rd: -1 rs1: -1 rs2: -1 +is_lw: 0 +is_sw: 0 +fetch_stall_cycles: 0 +mem_stall_cycles: 0 +stall_warp: 0 +wspawn: 0 +stalled: 0 +********************************** Decode ********************************* +valid: 0 +PC: 0 +wid: 3 +rd: -1 rs1: -1 rs2: -1 +is_lw: 0 +is_sw: 0 +fetch_stall_cycles: 0 +mem_stall_cycles: 0 +stall_warp: 0 +wspawn: 0 +stalled: 0 +********************************** Fetch ********************************* +valid: 0 +PC: 0 +wid: 4 +rd: -1 rs1: -1 rs2: -1 +is_lw: 0 +is_sw: 0 +fetch_stall_cycles: 0 +mem_stall_cycles: 0 +stall_warp: 0 +wspawn: 0 +stalled: 0 + + + +------------------------------------------------------ +CYCLE: 360 +Stalled Warps: +1 0 0 0 0 0 0 0 + +********************************** Writeback ********************************* +valid: 0 +PC: 0 +wid: 5 +rd: -1 rs1: -1 rs2: -1 +is_lw: 0 +is_sw: 0 +fetch_stall_cycles: 0 +mem_stall_cycles: 0 +stall_warp: 0 +wspawn: 0 +stalled: 0 +********************************** LSU ********************************* +valid: 0 +PC: 0 +wid: 1 +rd: -1 rs1: -1 rs2: -1 +is_lw: 0 +is_sw: 0 +fetch_stall_cycles: 0 +mem_stall_cycles: 0 +stall_warp: 0 +wspawn: 0 +stalled: 0 +********************************** execute_unit ********************************* +valid: 0 +PC: 0 +wid: 2 +rd: -1 rs1: -1 rs2: -1 +is_lw: 0 +is_sw: 0 +fetch_stall_cycles: 0 +mem_stall_cycles: 0 +stall_warp: 0 +wspawn: 0 +stalled: 0 +********************************** scheduler ********************************* +valid: 0 +PC: 0 +wid: 3 +rd: -1 rs1: -1 rs2: -1 +is_lw: 0 +is_sw: 0 +fetch_stall_cycles: 0 +mem_stall_cycles: 0 +stall_warp: 0 +wspawn: 0 +stalled: 0 +********************************** Decode ********************************* +valid: 0 +PC: 0 +wid: 4 +rd: -1 rs1: -1 rs2: -1 +is_lw: 0 +is_sw: 0 +fetch_stall_cycles: 0 +mem_stall_cycles: 0 +stall_warp: 0 +wspawn: 0 +stalled: 0 +********************************** Fetch ********************************* +valid: 0 +PC: 0 +wid: 5 +rd: -1 rs1: -1 rs2: -1 +is_lw: 0 +is_sw: 0 +fetch_stall_cycles: 0 +mem_stall_cycles: 0 +stall_warp: 0 +wspawn: 0 +stalled: 0 +Warp ID 0 is running + + + +------------------------------------------------------ +CYCLE: 361 +Stalled Warps: +0 0 0 0 0 0 0 0 + +********************************** Writeback ********************************* +valid: 0 +PC: 0 +wid: 0 +rd: -1 rs1: -1 rs2: -1 +is_lw: 0 +is_sw: 0 +fetch_stall_cycles: 0 +mem_stall_cycles: 0 +stall_warp: 0 +wspawn: 0 +stalled: 0 +********************************** LSU ********************************* +valid: 0 +PC: 0 +wid: 1 +rd: -1 rs1: -1 rs2: -1 +is_lw: 0 +is_sw: 0 +fetch_stall_cycles: 0 +mem_stall_cycles: 0 +stall_warp: 0 +wspawn: 0 +stalled: 0 +********************************** execute_unit ********************************* +valid: 0 +PC: 0 +wid: 3 +rd: -1 rs1: -1 rs2: -1 +is_lw: 0 +is_sw: 0 +fetch_stall_cycles: 0 +mem_stall_cycles: 0 +stall_warp: 0 +wspawn: 0 +stalled: 0 +********************************** scheduler ********************************* +valid: 0 +PC: 0 +wid: 4 +rd: -1 rs1: -1 rs2: -1 +is_lw: 0 +is_sw: 0 +fetch_stall_cycles: 0 +mem_stall_cycles: 0 +stall_warp: 0 +wspawn: 0 +stalled: 0 +********************************** Decode ********************************* +valid: 0 +PC: 0 +wid: 5 +rd: -1 rs1: -1 rs2: -1 +is_lw: 0 +is_sw: 0 +fetch_stall_cycles: 0 +mem_stall_cycles: 0 +stall_warp: 0 +wspawn: 0 +stalled: 0 +DEBUG ../core.cpp:386: Core step stepping warp 0[1] +DEBUG ../core.cpp:683: in step pc=0x80000a04 +help: in PC: 80000a04 +CUrrent CODE: fe9918e3 +DEBUG ../core.cpp:703: Fetched at 0x80000a04 +DEBUG ../core.cpp:704: 0x80000a04: branch; +DEBUG ../instruction.cpp:350: Begin instruction execute. +DEBUG ../instruction.cpp:2117: End instruction execute. +DEBUG ../core.cpp:717: Register state: + %r 0: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r 1: 80000a04 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r 2: 6fffeff0 6fffec04 6fffe808 6fffe40c 00000000 00000000 00000000 00000000 (0) + %r 3: 80001808 80001808 80001808 80001808 00000000 00000000 00000000 00000000 (0) + %r 4: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r 5: 80000a6c 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r 6: 0000000f 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r 7: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r 8: 80001004 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r 9: 00000001 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r10: 00000000 00000001 00000001 00000001 00000000 00000000 00000000 00000000 (0) + %r11: 80000924 00000400 00000800 00000c00 00000000 00000000 00000000 00000000 (0) + %r12: 00000000 00000004 00000008 0000000c 00000000 00000000 00000000 00000000 (0) + %r13: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r14: 00000001 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r15: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r16: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r17: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r18: 00000001 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r19: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r20: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r21: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r22: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r23: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r24: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r25: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r26: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r27: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r28: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r29: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r30: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r31: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) +DEBUG ../core.cpp:726: Thread mask: + 1 0 0 0 0 0 0 0 + + +DEBUG ../core.cpp:388: Now 1 active threads in 0 +********************************** Fetch ********************************* +valid: 1 +PC: 80000a04 +wid: 0 +rd: -1 rs1: 18 rs2: 9 +is_lw: 0 +is_sw: 0 +fetch_stall_cycles: 0 +mem_stall_cycles: 0 +stall_warp: 1 +wspawn: 0 +stalled: 0 + + + +------------------------------------------------------ +CYCLE: 362 +Stalled Warps: +1 0 0 0 0 0 0 0 + +********************************** Writeback ********************************* +valid: 0 +PC: 0 +wid: 1 +rd: -1 rs1: -1 rs2: -1 +is_lw: 0 +is_sw: 0 +fetch_stall_cycles: 0 +mem_stall_cycles: 0 +stall_warp: 0 +wspawn: 0 +stalled: 0 +********************************** LSU ********************************* +valid: 0 +PC: 0 +wid: 1 +rd: -1 rs1: -1 rs2: -1 +is_lw: 0 +is_sw: 0 +fetch_stall_cycles: 0 +mem_stall_cycles: 0 +stall_warp: 0 +wspawn: 0 +stalled: 0 +********************************** execute_unit ********************************* +valid: 0 +PC: 0 +wid: 4 +rd: -1 rs1: -1 rs2: -1 +is_lw: 0 +is_sw: 0 +fetch_stall_cycles: 0 +mem_stall_cycles: 0 +stall_warp: 0 +wspawn: 0 +stalled: 0 +********************************** scheduler ********************************* +valid: 0 +PC: 0 +wid: 5 +rd: -1 rs1: -1 rs2: -1 +is_lw: 0 +is_sw: 0 +fetch_stall_cycles: 0 +mem_stall_cycles: 0 +stall_warp: 0 +wspawn: 0 +stalled: 0 +********************************** Decode ********************************* +valid: 1 +PC: 80000a04 +wid: 0 +rd: -1 rs1: 18 rs2: 9 +is_lw: 0 +is_sw: 0 +fetch_stall_cycles: 0 +mem_stall_cycles: 0 +stall_warp: 1 +wspawn: 0 +stalled: 0 +********************************** Fetch ********************************* +valid: 0 +PC: 0 +wid: 1 +rd: -1 rs1: -1 rs2: -1 +is_lw: 0 +is_sw: 0 +fetch_stall_cycles: 0 +mem_stall_cycles: 0 +stall_warp: 0 +wspawn: 0 +stalled: 0 + + + +------------------------------------------------------ +CYCLE: 363 +Stalled Warps: +1 0 0 0 0 0 0 0 + +********************************** Writeback ********************************* +valid: 0 +PC: 0 +wid: 2 +rd: -1 rs1: -1 rs2: -1 +is_lw: 0 +is_sw: 0 +fetch_stall_cycles: 0 +mem_stall_cycles: 0 +stall_warp: 0 +wspawn: 0 +stalled: 0 +********************************** LSU ********************************* +valid: 0 +PC: 0 +wid: 1 +rd: -1 rs1: -1 rs2: -1 +is_lw: 0 +is_sw: 0 +fetch_stall_cycles: 0 +mem_stall_cycles: 0 +stall_warp: 0 +wspawn: 0 +stalled: 0 +********************************** execute_unit ********************************* +valid: 0 +PC: 0 +wid: 5 +rd: -1 rs1: -1 rs2: -1 +is_lw: 0 +is_sw: 0 +fetch_stall_cycles: 0 +mem_stall_cycles: 0 +stall_warp: 0 +wspawn: 0 +stalled: 0 +********************************** scheduler ********************************* +valid: 1 +PC: 80000a04 +wid: 0 +rd: -1 rs1: 18 rs2: 9 +is_lw: 0 +is_sw: 0 +fetch_stall_cycles: 0 +mem_stall_cycles: 0 +stall_warp: 1 +wspawn: 0 +stalled: 0 +********************************** Decode ********************************* +valid: 0 +PC: 0 +wid: 1 +rd: -1 rs1: -1 rs2: -1 +is_lw: 0 +is_sw: 0 +fetch_stall_cycles: 0 +mem_stall_cycles: 0 +stall_warp: 0 +wspawn: 0 +stalled: 0 +********************************** Fetch ********************************* +valid: 0 +PC: 0 +wid: 2 +rd: -1 rs1: -1 rs2: -1 +is_lw: 0 +is_sw: 0 +fetch_stall_cycles: 0 +mem_stall_cycles: 0 +stall_warp: 0 +wspawn: 0 +stalled: 0 + + + +------------------------------------------------------ +CYCLE: 364 +Stalled Warps: +1 0 0 0 0 0 0 0 + +********************************** Writeback ********************************* +valid: 0 +PC: 0 +wid: 3 +rd: -1 rs1: -1 rs2: -1 +is_lw: 0 +is_sw: 0 +fetch_stall_cycles: 0 +mem_stall_cycles: 0 +stall_warp: 0 +wspawn: 0 +stalled: 0 +********************************** LSU ********************************* +valid: 0 +PC: 0 +wid: 1 +rd: -1 rs1: -1 rs2: -1 +is_lw: 0 +is_sw: 0 +fetch_stall_cycles: 0 +mem_stall_cycles: 0 +stall_warp: 0 +wspawn: 0 +stalled: 0 +********************************** execute_unit ********************************* +valid: 1 +PC: 80000a04 +wid: 0 +rd: -1 rs1: 18 rs2: 9 +is_lw: 0 +is_sw: 0 +fetch_stall_cycles: 0 +mem_stall_cycles: 0 +stall_warp: 1 +wspawn: 0 +stalled: 0 +********************************** scheduler ********************************* +valid: 0 +PC: 0 +wid: 1 +rd: -1 rs1: -1 rs2: -1 +is_lw: 0 +is_sw: 0 +fetch_stall_cycles: 0 +mem_stall_cycles: 0 +stall_warp: 0 +wspawn: 0 +stalled: 0 +********************************** Decode ********************************* +valid: 0 +PC: 0 +wid: 2 +rd: -1 rs1: -1 rs2: -1 +is_lw: 0 +is_sw: 0 +fetch_stall_cycles: 0 +mem_stall_cycles: 0 +stall_warp: 0 +wspawn: 0 +stalled: 0 +********************************** Fetch ********************************* +valid: 0 +PC: 0 +wid: 3 +rd: -1 rs1: -1 rs2: -1 +is_lw: 0 +is_sw: 0 +fetch_stall_cycles: 0 +mem_stall_cycles: 0 +stall_warp: 0 +wspawn: 0 +stalled: 0 + + + +------------------------------------------------------ +CYCLE: 365 +Stalled Warps: +1 0 0 0 0 0 0 0 + +********************************** Writeback ********************************* +valid: 1 +PC: 80000a04 +wid: 0 +rd: -1 rs1: 18 rs2: 9 +is_lw: 0 +is_sw: 0 +fetch_stall_cycles: 0 +mem_stall_cycles: 0 +stall_warp: 1 +wspawn: 0 +stalled: 0 +********************************** LSU ********************************* +valid: 0 +PC: 0 +wid: 1 +rd: -1 rs1: -1 rs2: -1 +is_lw: 0 +is_sw: 0 +fetch_stall_cycles: 0 +mem_stall_cycles: 0 +stall_warp: 0 +wspawn: 0 +stalled: 0 +********************************** execute_unit ********************************* +valid: 0 +PC: 0 +wid: 1 +rd: -1 rs1: -1 rs2: -1 +is_lw: 0 +is_sw: 0 +fetch_stall_cycles: 0 +mem_stall_cycles: 0 +stall_warp: 0 +wspawn: 0 +stalled: 0 +********************************** scheduler ********************************* +valid: 0 +PC: 0 +wid: 2 +rd: -1 rs1: -1 rs2: -1 +is_lw: 0 +is_sw: 0 +fetch_stall_cycles: 0 +mem_stall_cycles: 0 +stall_warp: 0 +wspawn: 0 +stalled: 0 +********************************** Decode ********************************* +valid: 0 +PC: 0 +wid: 3 +rd: -1 rs1: -1 rs2: -1 +is_lw: 0 +is_sw: 0 +fetch_stall_cycles: 0 +mem_stall_cycles: 0 +stall_warp: 0 +wspawn: 0 +stalled: 0 +********************************** Fetch ********************************* +valid: 0 +PC: 0 +wid: 4 +rd: -1 rs1: -1 rs2: -1 +is_lw: 0 +is_sw: 0 +fetch_stall_cycles: 0 +mem_stall_cycles: 0 +stall_warp: 0 +wspawn: 0 +stalled: 0 + + + +------------------------------------------------------ +CYCLE: 366 +Stalled Warps: +1 0 0 0 0 0 0 0 + +********************************** Writeback ********************************* +valid: 0 +PC: 0 +wid: 5 +rd: -1 rs1: -1 rs2: -1 +is_lw: 0 +is_sw: 0 +fetch_stall_cycles: 0 +mem_stall_cycles: 0 +stall_warp: 0 +wspawn: 0 +stalled: 0 +********************************** LSU ********************************* +valid: 0 +PC: 0 +wid: 1 +rd: -1 rs1: -1 rs2: -1 +is_lw: 0 +is_sw: 0 +fetch_stall_cycles: 0 +mem_stall_cycles: 0 +stall_warp: 0 +wspawn: 0 +stalled: 0 +********************************** execute_unit ********************************* +valid: 0 +PC: 0 +wid: 2 +rd: -1 rs1: -1 rs2: -1 +is_lw: 0 +is_sw: 0 +fetch_stall_cycles: 0 +mem_stall_cycles: 0 +stall_warp: 0 +wspawn: 0 +stalled: 0 +********************************** scheduler ********************************* +valid: 0 +PC: 0 +wid: 3 +rd: -1 rs1: -1 rs2: -1 +is_lw: 0 +is_sw: 0 +fetch_stall_cycles: 0 +mem_stall_cycles: 0 +stall_warp: 0 +wspawn: 0 +stalled: 0 +********************************** Decode ********************************* +valid: 0 +PC: 0 +wid: 4 +rd: -1 rs1: -1 rs2: -1 +is_lw: 0 +is_sw: 0 +fetch_stall_cycles: 0 +mem_stall_cycles: 0 +stall_warp: 0 +wspawn: 0 +stalled: 0 +********************************** Fetch ********************************* +valid: 0 +PC: 0 +wid: 5 +rd: -1 rs1: -1 rs2: -1 +is_lw: 0 +is_sw: 0 +fetch_stall_cycles: 0 +mem_stall_cycles: 0 +stall_warp: 0 +wspawn: 0 +stalled: 0 +Warp ID 0 is running + + + +------------------------------------------------------ +CYCLE: 367 +Stalled Warps: +0 0 0 0 0 0 0 0 + +********************************** Writeback ********************************* +valid: 0 +PC: 0 +wid: 0 +rd: -1 rs1: -1 rs2: -1 +is_lw: 0 +is_sw: 0 +fetch_stall_cycles: 0 +mem_stall_cycles: 0 +stall_warp: 0 +wspawn: 0 +stalled: 0 +********************************** LSU ********************************* +valid: 0 +PC: 0 +wid: 1 +rd: -1 rs1: -1 rs2: -1 +is_lw: 0 +is_sw: 0 +fetch_stall_cycles: 0 +mem_stall_cycles: 0 +stall_warp: 0 +wspawn: 0 +stalled: 0 +********************************** execute_unit ********************************* +valid: 0 +PC: 0 +wid: 3 +rd: -1 rs1: -1 rs2: -1 +is_lw: 0 +is_sw: 0 +fetch_stall_cycles: 0 +mem_stall_cycles: 0 +stall_warp: 0 +wspawn: 0 +stalled: 0 +********************************** scheduler ********************************* +valid: 0 +PC: 0 +wid: 4 +rd: -1 rs1: -1 rs2: -1 +is_lw: 0 +is_sw: 0 +fetch_stall_cycles: 0 +mem_stall_cycles: 0 +stall_warp: 0 +wspawn: 0 +stalled: 0 +********************************** Decode ********************************* +valid: 0 +PC: 0 +wid: 5 +rd: -1 rs1: -1 rs2: -1 +is_lw: 0 +is_sw: 0 +fetch_stall_cycles: 0 +mem_stall_cycles: 0 +stall_warp: 0 +wspawn: 0 +stalled: 0 +DEBUG ../core.cpp:386: Core step stepping warp 0[1] +DEBUG ../core.cpp:683: in step pc=0x80000a08 +help: in PC: 80000a08 +CUrrent CODE: c12083 +DEBUG ../core.cpp:703: Fetched at 0x80000a08 +DEBUG ../core.cpp:704: 0x80000a08: load; +DEBUG ../instruction.cpp:350: Begin instruction execute. +DEBUG ../instruction.cpp:2117: End instruction execute. +DEBUG ../core.cpp:717: Register state: + %r 0: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r 1: 80000040 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r 2: 6fffeff0 6fffec04 6fffe808 6fffe40c 00000000 00000000 00000000 00000000 (0) + %r 3: 80001808 80001808 80001808 80001808 00000000 00000000 00000000 00000000 (0) + %r 4: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r 5: 80000a6c 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r 6: 0000000f 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r 7: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r 8: 80001004 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r 9: 00000001 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r10: 00000000 00000001 00000001 00000001 00000000 00000000 00000000 00000000 (0) + %r11: 80000924 00000400 00000800 00000c00 00000000 00000000 00000000 00000000 (0) + %r12: 00000000 00000004 00000008 0000000c 00000000 00000000 00000000 00000000 (0) + %r13: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r14: 00000001 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r15: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r16: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r17: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r18: 00000001 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r19: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r20: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r21: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r22: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r23: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r24: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r25: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r26: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r27: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r28: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r29: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r30: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r31: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) +DEBUG ../core.cpp:726: Thread mask: + 1 0 0 0 0 0 0 0 + + +DEBUG ../core.cpp:388: Now 1 active threads in 0 +********************************** Fetch ********************************* +valid: 1 +PC: 80000a08 +wid: 0 +rd: 1 rs1: 2 rs2: -1 +is_lw: 1 +is_sw: 0 +fetch_stall_cycles: 0 +mem_stall_cycles: 0 +stall_warp: 0 +wspawn: 0 +stalled: 0 + + + +------------------------------------------------------ +CYCLE: 368 +Stalled Warps: +0 0 0 0 0 0 0 0 + +********************************** Writeback ********************************* +valid: 0 +PC: 0 +wid: 0 +rd: -1 rs1: -1 rs2: -1 +is_lw: 0 +is_sw: 0 +fetch_stall_cycles: 0 +mem_stall_cycles: 0 +stall_warp: 0 +wspawn: 0 +stalled: 0 +********************************** LSU ********************************* +valid: 0 +PC: 0 +wid: 1 +rd: -1 rs1: -1 rs2: -1 +is_lw: 0 +is_sw: 0 +fetch_stall_cycles: 0 +mem_stall_cycles: 0 +stall_warp: 0 +wspawn: 0 +stalled: 0 +********************************** execute_unit ********************************* +valid: 0 +PC: 0 +wid: 4 +rd: -1 rs1: -1 rs2: -1 +is_lw: 0 +is_sw: 0 +fetch_stall_cycles: 0 +mem_stall_cycles: 0 +stall_warp: 0 +wspawn: 0 +stalled: 0 +********************************** scheduler ********************************* +valid: 0 +PC: 0 +wid: 5 +rd: -1 rs1: -1 rs2: -1 +is_lw: 0 +is_sw: 0 +fetch_stall_cycles: 0 +mem_stall_cycles: 0 +stall_warp: 0 +wspawn: 0 +stalled: 0 +********************************** Decode ********************************* +valid: 1 +PC: 80000a08 +wid: 0 +rd: 1 rs1: 2 rs2: -1 +is_lw: 1 +is_sw: 0 +fetch_stall_cycles: 0 +mem_stall_cycles: 0 +stall_warp: 0 +wspawn: 0 +stalled: 0 +DEBUG ../core.cpp:386: Core step stepping warp 0[1] +DEBUG ../core.cpp:683: in step pc=0x80000a0c +help: in PC: 80000a0c +CUrrent CODE: 812403 +DEBUG ../core.cpp:703: Fetched at 0x80000a0c +DEBUG ../core.cpp:704: 0x80000a0c: load; +DEBUG ../instruction.cpp:350: Begin instruction execute. +DEBUG ../instruction.cpp:2117: End instruction execute. +DEBUG ../core.cpp:717: Register state: + %r 0: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r 1: 80000040 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r 2: 6fffeff0 6fffec04 6fffe808 6fffe40c 00000000 00000000 00000000 00000000 (0) + %r 3: 80001808 80001808 80001808 80001808 00000000 00000000 00000000 00000000 (0) + %r 4: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r 5: 80000a6c 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r 6: 0000000f 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r 7: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r 8: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r 9: 00000001 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r10: 00000000 00000001 00000001 00000001 00000000 00000000 00000000 00000000 (0) + %r11: 80000924 00000400 00000800 00000c00 00000000 00000000 00000000 00000000 (0) + %r12: 00000000 00000004 00000008 0000000c 00000000 00000000 00000000 00000000 (0) + %r13: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r14: 00000001 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r15: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r16: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r17: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r18: 00000001 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r19: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r20: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r21: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r22: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r23: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r24: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r25: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r26: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r27: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r28: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r29: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r30: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r31: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) +DEBUG ../core.cpp:726: Thread mask: + 1 0 0 0 0 0 0 0 + + +DEBUG ../core.cpp:388: Now 1 active threads in 0 +********************************** Fetch ********************************* +valid: 1 +PC: 80000a0c +wid: 0 +rd: 8 rs1: 2 rs2: -1 +is_lw: 1 +is_sw: 0 +fetch_stall_cycles: 0 +mem_stall_cycles: 0 +stall_warp: 0 +wspawn: 0 +stalled: 0 + + + +------------------------------------------------------ +CYCLE: 369 +Stalled Warps: +0 0 0 0 0 0 0 0 + +********************************** Writeback ********************************* +valid: 0 +PC: 0 +wid: 0 +rd: -1 rs1: -1 rs2: -1 +is_lw: 0 +is_sw: 0 +fetch_stall_cycles: 0 +mem_stall_cycles: 0 +stall_warp: 0 +wspawn: 0 +stalled: 0 +********************************** LSU ********************************* +valid: 0 +PC: 0 +wid: 1 +rd: -1 rs1: -1 rs2: -1 +is_lw: 0 +is_sw: 0 +fetch_stall_cycles: 0 +mem_stall_cycles: 0 +stall_warp: 0 +wspawn: 0 +stalled: 0 +********************************** execute_unit ********************************* +valid: 0 +PC: 0 +wid: 5 +rd: -1 rs1: -1 rs2: -1 +is_lw: 0 +is_sw: 0 +fetch_stall_cycles: 0 +mem_stall_cycles: 0 +stall_warp: 0 +wspawn: 0 +stalled: 0 +********************************** scheduler ********************************* +valid: 1 +PC: 80000a08 +wid: 0 +rd: 1 rs1: 2 rs2: -1 +is_lw: 1 +is_sw: 0 +fetch_stall_cycles: 0 +mem_stall_cycles: 0 +stall_warp: 0 +wspawn: 0 +stalled: 0 +********************************** Decode ********************************* +valid: 1 +PC: 80000a0c +wid: 0 +rd: 8 rs1: 2 rs2: -1 +is_lw: 1 +is_sw: 0 +fetch_stall_cycles: 0 +mem_stall_cycles: 0 +stall_warp: 0 +wspawn: 0 +stalled: 0 +DEBUG ../core.cpp:386: Core step stepping warp 0[1] +DEBUG ../core.cpp:683: in step pc=0x80000a10 +help: in PC: 80000a10 +CUrrent CODE: 412483 +DEBUG ../core.cpp:703: Fetched at 0x80000a10 +DEBUG ../core.cpp:704: 0x80000a10: load; +DEBUG ../instruction.cpp:350: Begin instruction execute. +DEBUG ../instruction.cpp:2117: End instruction execute. +DEBUG ../core.cpp:717: Register state: + %r 0: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r 1: 80000040 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r 2: 6fffeff0 6fffec04 6fffe808 6fffe40c 00000000 00000000 00000000 00000000 (0) + %r 3: 80001808 80001808 80001808 80001808 00000000 00000000 00000000 00000000 (0) + %r 4: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r 5: 80000a6c 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r 6: 0000000f 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r 7: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r 8: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r 9: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r10: 00000000 00000001 00000001 00000001 00000000 00000000 00000000 00000000 (0) + %r11: 80000924 00000400 00000800 00000c00 00000000 00000000 00000000 00000000 (0) + %r12: 00000000 00000004 00000008 0000000c 00000000 00000000 00000000 00000000 (0) + %r13: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r14: 00000001 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r15: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r16: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r17: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r18: 00000001 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r19: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r20: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r21: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r22: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r23: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r24: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r25: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r26: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r27: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r28: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r29: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r30: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r31: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) +DEBUG ../core.cpp:726: Thread mask: + 1 0 0 0 0 0 0 0 + + +DEBUG ../core.cpp:388: Now 1 active threads in 0 +********************************** Fetch ********************************* +valid: 1 +PC: 80000a10 +wid: 0 +rd: 9 rs1: 2 rs2: -1 +is_lw: 1 +is_sw: 0 +fetch_stall_cycles: 3 +mem_stall_cycles: 0 +stall_warp: 0 +wspawn: 0 +stalled: 0 + + + +------------------------------------------------------ +CYCLE: 370 +Stalled Warps: +0 0 0 0 0 0 0 0 + +********************************** Writeback ********************************* +valid: 0 +PC: 0 +wid: 0 +rd: -1 rs1: -1 rs2: -1 +is_lw: 0 +is_sw: 0 +fetch_stall_cycles: 0 +mem_stall_cycles: 0 +stall_warp: 0 +wspawn: 0 +stalled: 0 +********************************** LSU ********************************* +valid: 1 +PC: 80000a08 +wid: 0 +rd: 1 rs1: 2 rs2: -1 +is_lw: 1 +is_sw: 0 +fetch_stall_cycles: 0 +mem_stall_cycles: 0 +stall_warp: 0 +wspawn: 0 +stalled: 0 +********************************** execute_unit ********************************* +valid: 0 +PC: 0 +wid: 0 +rd: -1 rs1: -1 rs2: -1 +is_lw: 0 +is_sw: 0 +fetch_stall_cycles: 0 +mem_stall_cycles: 0 +stall_warp: 0 +wspawn: 0 +stalled: 0 +********************************** scheduler ********************************* +valid: 1 +PC: 80000a0c +wid: 0 +rd: 8 rs1: 2 rs2: -1 +is_lw: 1 +is_sw: 0 +fetch_stall_cycles: 0 +mem_stall_cycles: 0 +stall_warp: 0 +wspawn: 0 +stalled: 0 +********************************** Decode ********************************* +valid: 0 +PC: 0 +wid: 0 +rd: -1 rs1: -1 rs2: -1 +is_lw: 0 +is_sw: 0 +fetch_stall_cycles: 0 +mem_stall_cycles: 0 +stall_warp: 0 +wspawn: 0 +stalled: 0 +********************************** Fetch ********************************* +valid: 1 +PC: 80000a10 +wid: 0 +rd: 9 rs1: 2 rs2: -1 +is_lw: 1 +is_sw: 0 +fetch_stall_cycles: 2 +mem_stall_cycles: 0 +stall_warp: 0 +wspawn: 0 +stalled: 0 + + + +------------------------------------------------------ +CYCLE: 371 +Stalled Warps: +0 0 0 0 0 0 0 0 + +********************************** Writeback ********************************* +valid: 1 +PC: 80000a08 +wid: 0 +rd: 1 rs1: 2 rs2: -1 +is_lw: 1 +is_sw: 0 +fetch_stall_cycles: 0 +mem_stall_cycles: 0 +stall_warp: 0 +wspawn: 0 +stalled: 0 +********************************** LSU ********************************* +valid: 1 +PC: 80000a0c +wid: 0 +rd: 8 rs1: 2 rs2: -1 +is_lw: 1 +is_sw: 0 +fetch_stall_cycles: 0 +mem_stall_cycles: 0 +stall_warp: 0 +wspawn: 0 +stalled: 0 +********************************** execute_unit ********************************* +valid: 0 +PC: 0 +wid: 0 +rd: -1 rs1: -1 rs2: -1 +is_lw: 0 +is_sw: 0 +fetch_stall_cycles: 0 +mem_stall_cycles: 0 +stall_warp: 0 +wspawn: 0 +stalled: 0 +********************************** scheduler ********************************* +valid: 0 +PC: 0 +wid: 0 +rd: -1 rs1: -1 rs2: -1 +is_lw: 0 +is_sw: 0 +fetch_stall_cycles: 0 +mem_stall_cycles: 0 +stall_warp: 0 +wspawn: 0 +stalled: 0 +********************************** Decode ********************************* +valid: 0 +PC: 0 +wid: 0 +rd: -1 rs1: -1 rs2: -1 +is_lw: 0 +is_sw: 0 +fetch_stall_cycles: 0 +mem_stall_cycles: 0 +stall_warp: 0 +wspawn: 0 +stalled: 0 +********************************** Fetch ********************************* +valid: 1 +PC: 80000a10 +wid: 0 +rd: 9 rs1: 2 rs2: -1 +is_lw: 1 +is_sw: 0 +fetch_stall_cycles: 1 +mem_stall_cycles: 0 +stall_warp: 0 +wspawn: 0 +stalled: 0 + + + +------------------------------------------------------ +CYCLE: 372 +Stalled Warps: +0 0 0 0 0 0 0 0 + +********************************** Writeback ********************************* +valid: 1 +PC: 80000a0c +wid: 0 +rd: 8 rs1: 2 rs2: -1 +is_lw: 1 +is_sw: 0 +fetch_stall_cycles: 0 +mem_stall_cycles: 0 +stall_warp: 0 +wspawn: 0 +stalled: 0 +********************************** LSU ********************************* +valid: 0 +PC: 0 +wid: 0 +rd: -1 rs1: -1 rs2: -1 +is_lw: 0 +is_sw: 0 +fetch_stall_cycles: 0 +mem_stall_cycles: 0 +stall_warp: 0 +wspawn: 0 +stalled: 0 +********************************** execute_unit ********************************* +valid: 0 +PC: 0 +wid: 0 +rd: -1 rs1: -1 rs2: -1 +is_lw: 0 +is_sw: 0 +fetch_stall_cycles: 0 +mem_stall_cycles: 0 +stall_warp: 0 +wspawn: 0 +stalled: 0 +********************************** scheduler ********************************* +valid: 0 +PC: 0 +wid: 0 +rd: -1 rs1: -1 rs2: -1 +is_lw: 0 +is_sw: 0 +fetch_stall_cycles: 0 +mem_stall_cycles: 0 +stall_warp: 0 +wspawn: 0 +stalled: 0 +********************************** Decode ********************************* +valid: 0 +PC: 0 +wid: 0 +rd: -1 rs1: -1 rs2: -1 +is_lw: 0 +is_sw: 0 +fetch_stall_cycles: 0 +mem_stall_cycles: 0 +stall_warp: 0 +wspawn: 0 +stalled: 0 +********************************** Fetch ********************************* +valid: 1 +PC: 80000a10 +wid: 0 +rd: 9 rs1: 2 rs2: -1 +is_lw: 1 +is_sw: 0 +fetch_stall_cycles: 0 +mem_stall_cycles: 0 +stall_warp: 0 +wspawn: 0 +stalled: 0 + + + +------------------------------------------------------ +CYCLE: 373 +Stalled Warps: +0 0 0 0 0 0 0 0 + +********************************** Writeback ********************************* +valid: 0 +PC: 0 +wid: 0 +rd: -1 rs1: -1 rs2: -1 +is_lw: 0 +is_sw: 0 +fetch_stall_cycles: 0 +mem_stall_cycles: 0 +stall_warp: 0 +wspawn: 0 +stalled: 0 +********************************** LSU ********************************* +valid: 0 +PC: 0 +wid: 0 +rd: -1 rs1: -1 rs2: -1 +is_lw: 0 +is_sw: 0 +fetch_stall_cycles: 0 +mem_stall_cycles: 0 +stall_warp: 0 +wspawn: 0 +stalled: 0 +********************************** execute_unit ********************************* +valid: 0 +PC: 0 +wid: 0 +rd: -1 rs1: -1 rs2: -1 +is_lw: 0 +is_sw: 0 +fetch_stall_cycles: 0 +mem_stall_cycles: 0 +stall_warp: 0 +wspawn: 0 +stalled: 0 +********************************** scheduler ********************************* +valid: 0 +PC: 0 +wid: 0 +rd: -1 rs1: -1 rs2: -1 +is_lw: 0 +is_sw: 0 +fetch_stall_cycles: 0 +mem_stall_cycles: 0 +stall_warp: 0 +wspawn: 0 +stalled: 0 +********************************** Decode ********************************* +valid: 1 +PC: 80000a10 +wid: 0 +rd: 9 rs1: 2 rs2: -1 +is_lw: 1 +is_sw: 0 +fetch_stall_cycles: 0 +mem_stall_cycles: 0 +stall_warp: 0 +wspawn: 0 +stalled: 0 +DEBUG ../core.cpp:386: Core step stepping warp 0[1] +DEBUG ../core.cpp:683: in step pc=0x80000a14 +help: in PC: 80000a14 +CUrrent CODE: 12903 +DEBUG ../core.cpp:703: Fetched at 0x80000a14 +DEBUG ../core.cpp:704: 0x80000a14: load; +DEBUG ../instruction.cpp:350: Begin instruction execute. +DEBUG ../instruction.cpp:2117: End instruction execute. +DEBUG ../core.cpp:717: Register state: + %r 0: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r 1: 80000040 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r 2: 6fffeff0 6fffec04 6fffe808 6fffe40c 00000000 00000000 00000000 00000000 (0) + %r 3: 80001808 80001808 80001808 80001808 00000000 00000000 00000000 00000000 (0) + %r 4: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r 5: 80000a6c 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r 6: 0000000f 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r 7: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r 8: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r 9: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r10: 00000000 00000001 00000001 00000001 00000000 00000000 00000000 00000000 (0) + %r11: 80000924 00000400 00000800 00000c00 00000000 00000000 00000000 00000000 (0) + %r12: 00000000 00000004 00000008 0000000c 00000000 00000000 00000000 00000000 (0) + %r13: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r14: 00000001 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r15: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r16: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r17: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r18: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r19: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r20: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r21: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r22: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r23: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r24: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r25: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r26: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r27: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r28: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r29: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r30: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r31: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) +DEBUG ../core.cpp:726: Thread mask: + 1 0 0 0 0 0 0 0 + + +DEBUG ../core.cpp:388: Now 1 active threads in 0 +********************************** Fetch ********************************* +valid: 1 +PC: 80000a14 +wid: 0 +rd: 18 rs1: 2 rs2: -1 +is_lw: 1 +is_sw: 0 +fetch_stall_cycles: 0 +mem_stall_cycles: 0 +stall_warp: 0 +wspawn: 0 +stalled: 0 + + + +------------------------------------------------------ +CYCLE: 374 +Stalled Warps: +0 0 0 0 0 0 0 0 + +********************************** Writeback ********************************* +valid: 0 +PC: 0 +wid: 0 +rd: -1 rs1: -1 rs2: -1 +is_lw: 0 +is_sw: 0 +fetch_stall_cycles: 0 +mem_stall_cycles: 0 +stall_warp: 0 +wspawn: 0 +stalled: 0 +********************************** LSU ********************************* +valid: 0 +PC: 0 +wid: 0 +rd: -1 rs1: -1 rs2: -1 +is_lw: 0 +is_sw: 0 +fetch_stall_cycles: 0 +mem_stall_cycles: 0 +stall_warp: 0 +wspawn: 0 +stalled: 0 +********************************** execute_unit ********************************* +valid: 0 +PC: 0 +wid: 0 +rd: -1 rs1: -1 rs2: -1 +is_lw: 0 +is_sw: 0 +fetch_stall_cycles: 0 +mem_stall_cycles: 0 +stall_warp: 0 +wspawn: 0 +stalled: 0 +********************************** scheduler ********************************* +valid: 1 +PC: 80000a10 +wid: 0 +rd: 9 rs1: 2 rs2: -1 +is_lw: 1 +is_sw: 0 +fetch_stall_cycles: 0 +mem_stall_cycles: 0 +stall_warp: 0 +wspawn: 0 +stalled: 0 +********************************** Decode ********************************* +valid: 1 +PC: 80000a14 +wid: 0 +rd: 18 rs1: 2 rs2: -1 +is_lw: 1 +is_sw: 0 +fetch_stall_cycles: 0 +mem_stall_cycles: 0 +stall_warp: 0 +wspawn: 0 +stalled: 0 +DEBUG ../core.cpp:386: Core step stepping warp 0[1] +DEBUG ../core.cpp:683: in step pc=0x80000a18 +help: in PC: 80000a18 +CUrrent CODE: 1010113 +DEBUG ../core.cpp:703: Fetched at 0x80000a18 +DEBUG ../core.cpp:704: 0x80000a18: i_type; +DEBUG ../instruction.cpp:350: Begin instruction execute. +DEBUG ../instruction.cpp:2117: End instruction execute. +DEBUG ../core.cpp:717: Register state: + %r 0: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r 1: 80000040 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r 2: 6ffff000 6fffec04 6fffe808 6fffe40c 00000000 00000000 00000000 00000000 (0) + %r 3: 80001808 80001808 80001808 80001808 00000000 00000000 00000000 00000000 (0) + %r 4: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r 5: 80000a6c 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r 6: 0000000f 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r 7: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r 8: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r 9: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r10: 00000000 00000001 00000001 00000001 00000000 00000000 00000000 00000000 (0) + %r11: 80000924 00000400 00000800 00000c00 00000000 00000000 00000000 00000000 (0) + %r12: 00000000 00000004 00000008 0000000c 00000000 00000000 00000000 00000000 (0) + %r13: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r14: 00000001 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r15: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r16: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r17: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r18: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r19: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r20: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r21: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r22: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r23: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r24: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r25: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r26: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r27: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r28: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r29: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r30: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r31: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) +DEBUG ../core.cpp:726: Thread mask: + 1 0 0 0 0 0 0 0 + + +DEBUG ../core.cpp:388: Now 1 active threads in 0 +********************************** Fetch ********************************* +valid: 1 +PC: 80000a18 +wid: 0 +rd: 2 rs1: 2 rs2: -1 +is_lw: 0 +is_sw: 0 +fetch_stall_cycles: 0 +mem_stall_cycles: 0 +stall_warp: 0 +wspawn: 0 +stalled: 0 + + + +------------------------------------------------------ +CYCLE: 375 +Stalled Warps: +0 0 0 0 0 0 0 0 + +********************************** Writeback ********************************* +valid: 0 +PC: 0 +wid: 0 +rd: -1 rs1: -1 rs2: -1 +is_lw: 0 +is_sw: 0 +fetch_stall_cycles: 0 +mem_stall_cycles: 0 +stall_warp: 0 +wspawn: 0 +stalled: 0 +********************************** LSU ********************************* +valid: 1 +PC: 80000a10 +wid: 0 +rd: 9 rs1: 2 rs2: -1 +is_lw: 1 +is_sw: 0 +fetch_stall_cycles: 0 +mem_stall_cycles: 0 +stall_warp: 0 +wspawn: 0 +stalled: 0 +********************************** execute_unit ********************************* +valid: 0 +PC: 0 +wid: 0 +rd: -1 rs1: -1 rs2: -1 +is_lw: 0 +is_sw: 0 +fetch_stall_cycles: 0 +mem_stall_cycles: 0 +stall_warp: 0 +wspawn: 0 +stalled: 0 +********************************** scheduler ********************************* +valid: 1 +PC: 80000a14 +wid: 0 +rd: 18 rs1: 2 rs2: -1 +is_lw: 1 +is_sw: 0 +fetch_stall_cycles: 0 +mem_stall_cycles: 0 +stall_warp: 0 +wspawn: 0 +stalled: 0 +********************************** Decode ********************************* +valid: 1 +PC: 80000a18 +wid: 0 +rd: 2 rs1: 2 rs2: -1 +is_lw: 0 +is_sw: 0 +fetch_stall_cycles: 0 +mem_stall_cycles: 0 +stall_warp: 0 +wspawn: 0 +stalled: 0 +DEBUG ../core.cpp:386: Core step stepping warp 0[1] +DEBUG ../core.cpp:683: in step pc=0x80000a1c +help: in PC: 80000a1c +CUrrent CODE: 8067 +DEBUG ../core.cpp:703: Fetched at 0x80000a1c +DEBUG ../core.cpp:704: 0x80000a1c: jalr; +DEBUG ../instruction.cpp:350: Begin instruction execute. +JALR_INST +DEBUG ../instruction.cpp:2117: End instruction execute. +Next PC: 80000040 +DEBUG ../core.cpp:717: Register state: + %r 0: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r 1: 80000040 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r 2: 6ffff000 6fffec04 6fffe808 6fffe40c 00000000 00000000 00000000 00000000 (0) + %r 3: 80001808 80001808 80001808 80001808 00000000 00000000 00000000 00000000 (0) + %r 4: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r 5: 80000a6c 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r 6: 0000000f 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r 7: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r 8: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r 9: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r10: 00000000 00000001 00000001 00000001 00000000 00000000 00000000 00000000 (0) + %r11: 80000924 00000400 00000800 00000c00 00000000 00000000 00000000 00000000 (0) + %r12: 00000000 00000004 00000008 0000000c 00000000 00000000 00000000 00000000 (0) + %r13: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r14: 00000001 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r15: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r16: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r17: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r18: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r19: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r20: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r21: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r22: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r23: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r24: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r25: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r26: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r27: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r28: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r29: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r30: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r31: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) +DEBUG ../core.cpp:726: Thread mask: + 1 0 0 0 0 0 0 0 + + +DEBUG ../core.cpp:388: Now 1 active threads in 0 +********************************** Fetch ********************************* +valid: 1 +PC: 80000a1c +wid: 0 +rd: 0 rs1: 1 rs2: -1 +is_lw: 0 +is_sw: 0 +fetch_stall_cycles: 0 +mem_stall_cycles: 0 +stall_warp: 1 +wspawn: 0 +stalled: 0 + + + +------------------------------------------------------ +CYCLE: 376 +Stalled Warps: +1 0 0 0 0 0 0 0 + +********************************** Writeback ********************************* +valid: 1 +PC: 80000a10 +wid: 0 +rd: 9 rs1: 2 rs2: -1 +is_lw: 1 +is_sw: 0 +fetch_stall_cycles: 0 +mem_stall_cycles: 0 +stall_warp: 0 +wspawn: 0 +stalled: 0 +********************************** LSU ********************************* +valid: 1 +PC: 80000a14 +wid: 0 +rd: 18 rs1: 2 rs2: -1 +is_lw: 1 +is_sw: 0 +fetch_stall_cycles: 0 +mem_stall_cycles: 0 +stall_warp: 0 +wspawn: 0 +stalled: 0 +********************************** execute_unit ********************************* +valid: 0 +PC: 0 +wid: 1 +rd: -1 rs1: -1 rs2: -1 +is_lw: 0 +is_sw: 0 +fetch_stall_cycles: 0 +mem_stall_cycles: 0 +stall_warp: 0 +wspawn: 0 +stalled: 0 +********************************** scheduler ********************************* +valid: 1 +PC: 80000a18 +wid: 0 +rd: 2 rs1: 2 rs2: -1 +is_lw: 0 +is_sw: 0 +fetch_stall_cycles: 0 +mem_stall_cycles: 0 +stall_warp: 0 +wspawn: 0 +stalled: 0 +********************************** Decode ********************************* +valid: 1 +PC: 80000a1c +wid: 0 +rd: 0 rs1: 1 rs2: -1 +is_lw: 0 +is_sw: 0 +fetch_stall_cycles: 0 +mem_stall_cycles: 0 +stall_warp: 1 +wspawn: 0 +stalled: 0 +********************************** Fetch ********************************* +valid: 0 +PC: 0 +wid: 1 +rd: -1 rs1: -1 rs2: -1 +is_lw: 0 +is_sw: 0 +fetch_stall_cycles: 0 +mem_stall_cycles: 0 +stall_warp: 0 +wspawn: 0 +stalled: 0 + + + +------------------------------------------------------ +CYCLE: 377 +Stalled Warps: +1 0 0 0 0 0 0 0 + +********************************** Writeback ********************************* +valid: 1 +PC: 80000a14 +wid: 0 +rd: 18 rs1: 2 rs2: -1 +is_lw: 1 +is_sw: 0 +fetch_stall_cycles: 0 +mem_stall_cycles: 0 +stall_warp: 0 +wspawn: 0 +stalled: 0 +********************************** LSU ********************************* +valid: 0 +PC: 0 +wid: 2 +rd: -1 rs1: -1 rs2: -1 +is_lw: 0 +is_sw: 0 +fetch_stall_cycles: 0 +mem_stall_cycles: 0 +stall_warp: 0 +wspawn: 0 +stalled: 0 +********************************** execute_unit ********************************* +valid: 1 +PC: 80000a18 +wid: 0 +rd: 2 rs1: 2 rs2: -1 +is_lw: 0 +is_sw: 0 +fetch_stall_cycles: 0 +mem_stall_cycles: 0 +stall_warp: 0 +wspawn: 0 +stalled: 0 +********************************** scheduler ********************************* +valid: 1 +PC: 80000a1c +wid: 0 +rd: 0 rs1: 1 rs2: -1 +is_lw: 0 +is_sw: 0 +fetch_stall_cycles: 0 +mem_stall_cycles: 0 +stall_warp: 1 +wspawn: 0 +stalled: 0 +********************************** Decode ********************************* +valid: 0 +PC: 0 +wid: 1 +rd: -1 rs1: -1 rs2: -1 +is_lw: 0 +is_sw: 0 +fetch_stall_cycles: 0 +mem_stall_cycles: 0 +stall_warp: 0 +wspawn: 0 +stalled: 0 +********************************** Fetch ********************************* +valid: 0 +PC: 0 +wid: 2 +rd: -1 rs1: -1 rs2: -1 +is_lw: 0 +is_sw: 0 +fetch_stall_cycles: 0 +mem_stall_cycles: 0 +stall_warp: 0 +wspawn: 0 +stalled: 0 + + + +------------------------------------------------------ +CYCLE: 378 +Stalled Warps: +1 0 0 0 0 0 0 0 + +********************************** Writeback ********************************* +valid: 1 +PC: 80000a18 +wid: 0 +rd: 2 rs1: 2 rs2: -1 +is_lw: 0 +is_sw: 0 +fetch_stall_cycles: 0 +mem_stall_cycles: 0 +stall_warp: 0 +wspawn: 0 +stalled: 0 +********************************** LSU ********************************* +valid: 0 +PC: 0 +wid: 2 +rd: -1 rs1: -1 rs2: -1 +is_lw: 0 +is_sw: 0 +fetch_stall_cycles: 0 +mem_stall_cycles: 0 +stall_warp: 0 +wspawn: 0 +stalled: 0 +********************************** execute_unit ********************************* +valid: 1 +PC: 80000a1c +wid: 0 +rd: 0 rs1: 1 rs2: -1 +is_lw: 0 +is_sw: 0 +fetch_stall_cycles: 0 +mem_stall_cycles: 0 +stall_warp: 1 +wspawn: 0 +stalled: 0 +********************************** scheduler ********************************* +valid: 0 +PC: 0 +wid: 1 +rd: -1 rs1: -1 rs2: -1 +is_lw: 0 +is_sw: 0 +fetch_stall_cycles: 0 +mem_stall_cycles: 0 +stall_warp: 0 +wspawn: 0 +stalled: 0 +********************************** Decode ********************************* +valid: 0 +PC: 0 +wid: 2 +rd: -1 rs1: -1 rs2: -1 +is_lw: 0 +is_sw: 0 +fetch_stall_cycles: 0 +mem_stall_cycles: 0 +stall_warp: 0 +wspawn: 0 +stalled: 0 +********************************** Fetch ********************************* +valid: 0 +PC: 0 +wid: 3 +rd: -1 rs1: -1 rs2: -1 +is_lw: 0 +is_sw: 0 +fetch_stall_cycles: 0 +mem_stall_cycles: 0 +stall_warp: 0 +wspawn: 0 +stalled: 0 + + + +------------------------------------------------------ +CYCLE: 379 +Stalled Warps: +1 0 0 0 0 0 0 0 + +********************************** Writeback ********************************* +valid: 1 +PC: 80000a1c +wid: 0 +rd: 0 rs1: 1 rs2: -1 +is_lw: 0 +is_sw: 0 +fetch_stall_cycles: 0 +mem_stall_cycles: 0 +stall_warp: 1 +wspawn: 0 +stalled: 0 +********************************** LSU ********************************* +valid: 0 +PC: 0 +wid: 2 +rd: -1 rs1: -1 rs2: -1 +is_lw: 0 +is_sw: 0 +fetch_stall_cycles: 0 +mem_stall_cycles: 0 +stall_warp: 0 +wspawn: 0 +stalled: 0 +********************************** execute_unit ********************************* +valid: 0 +PC: 0 +wid: 1 +rd: -1 rs1: -1 rs2: -1 +is_lw: 0 +is_sw: 0 +fetch_stall_cycles: 0 +mem_stall_cycles: 0 +stall_warp: 0 +wspawn: 0 +stalled: 0 +********************************** scheduler ********************************* +valid: 0 +PC: 0 +wid: 2 +rd: -1 rs1: -1 rs2: -1 +is_lw: 0 +is_sw: 0 +fetch_stall_cycles: 0 +mem_stall_cycles: 0 +stall_warp: 0 +wspawn: 0 +stalled: 0 +********************************** Decode ********************************* +valid: 0 +PC: 0 +wid: 3 +rd: -1 rs1: -1 rs2: -1 +is_lw: 0 +is_sw: 0 +fetch_stall_cycles: 0 +mem_stall_cycles: 0 +stall_warp: 0 +wspawn: 0 +stalled: 0 +********************************** Fetch ********************************* +valid: 0 +PC: 0 +wid: 4 +rd: -1 rs1: -1 rs2: -1 +is_lw: 0 +is_sw: 0 +fetch_stall_cycles: 0 +mem_stall_cycles: 0 +stall_warp: 0 +wspawn: 0 +stalled: 0 + + + +------------------------------------------------------ +CYCLE: 380 +Stalled Warps: +1 0 0 0 0 0 0 0 + +********************************** Writeback ********************************* +valid: 0 +PC: 0 +wid: 5 +rd: -1 rs1: -1 rs2: -1 +is_lw: 0 +is_sw: 0 +fetch_stall_cycles: 0 +mem_stall_cycles: 0 +stall_warp: 0 +wspawn: 0 +stalled: 0 +********************************** LSU ********************************* +valid: 0 +PC: 0 +wid: 2 +rd: -1 rs1: -1 rs2: -1 +is_lw: 0 +is_sw: 0 +fetch_stall_cycles: 0 +mem_stall_cycles: 0 +stall_warp: 0 +wspawn: 0 +stalled: 0 +********************************** execute_unit ********************************* +valid: 0 +PC: 0 +wid: 2 +rd: -1 rs1: -1 rs2: -1 +is_lw: 0 +is_sw: 0 +fetch_stall_cycles: 0 +mem_stall_cycles: 0 +stall_warp: 0 +wspawn: 0 +stalled: 0 +********************************** scheduler ********************************* +valid: 0 +PC: 0 +wid: 3 +rd: -1 rs1: -1 rs2: -1 +is_lw: 0 +is_sw: 0 +fetch_stall_cycles: 0 +mem_stall_cycles: 0 +stall_warp: 0 +wspawn: 0 +stalled: 0 +********************************** Decode ********************************* +valid: 0 +PC: 0 +wid: 4 +rd: -1 rs1: -1 rs2: -1 +is_lw: 0 +is_sw: 0 +fetch_stall_cycles: 0 +mem_stall_cycles: 0 +stall_warp: 0 +wspawn: 0 +stalled: 0 +********************************** Fetch ********************************* +valid: 0 +PC: 0 +wid: 5 +rd: -1 rs1: -1 rs2: -1 +is_lw: 0 +is_sw: 0 +fetch_stall_cycles: 0 +mem_stall_cycles: 0 +stall_warp: 0 +wspawn: 0 +stalled: 0 +Warp ID 0 is running + + + +------------------------------------------------------ +CYCLE: 381 +Stalled Warps: +0 0 0 0 0 0 0 0 + +********************************** Writeback ********************************* +valid: 0 +PC: 0 +wid: 0 +rd: -1 rs1: -1 rs2: -1 +is_lw: 0 +is_sw: 0 +fetch_stall_cycles: 0 +mem_stall_cycles: 0 +stall_warp: 0 +wspawn: 0 +stalled: 0 +********************************** LSU ********************************* +valid: 0 +PC: 0 +wid: 2 +rd: -1 rs1: -1 rs2: -1 +is_lw: 0 +is_sw: 0 +fetch_stall_cycles: 0 +mem_stall_cycles: 0 +stall_warp: 0 +wspawn: 0 +stalled: 0 +********************************** execute_unit ********************************* +valid: 0 +PC: 0 +wid: 3 +rd: -1 rs1: -1 rs2: -1 +is_lw: 0 +is_sw: 0 +fetch_stall_cycles: 0 +mem_stall_cycles: 0 +stall_warp: 0 +wspawn: 0 +stalled: 0 +********************************** scheduler ********************************* +valid: 0 +PC: 0 +wid: 4 +rd: -1 rs1: -1 rs2: -1 +is_lw: 0 +is_sw: 0 +fetch_stall_cycles: 0 +mem_stall_cycles: 0 +stall_warp: 0 +wspawn: 0 +stalled: 0 +********************************** Decode ********************************* +valid: 0 +PC: 0 +wid: 5 +rd: -1 rs1: -1 rs2: -1 +is_lw: 0 +is_sw: 0 +fetch_stall_cycles: 0 +mem_stall_cycles: 0 +stall_warp: 0 +wspawn: 0 +stalled: 0 +DEBUG ../core.cpp:386: Core step stepping warp 0[1] +DEBUG ../core.cpp:683: in step pc=0x80000040 +help: in PC: 80000040 +CUrrent CODE: 400513 +DEBUG ../core.cpp:703: Fetched at 0x80000040 +DEBUG ../core.cpp:704: 0x80000040: i_type; +DEBUG ../instruction.cpp:350: Begin instruction execute. +DEBUG ../instruction.cpp:2117: End instruction execute. +DEBUG ../core.cpp:717: Register state: + %r 0: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r 1: 80000040 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r 2: 6ffff000 6fffec04 6fffe808 6fffe40c 00000000 00000000 00000000 00000000 (0) + %r 3: 80001808 80001808 80001808 80001808 00000000 00000000 00000000 00000000 (0) + %r 4: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r 5: 80000a6c 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r 6: 0000000f 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r 7: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r 8: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r 9: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r10: 00000004 00000001 00000001 00000001 00000000 00000000 00000000 00000000 (0) + %r11: 80000924 00000400 00000800 00000c00 00000000 00000000 00000000 00000000 (0) + %r12: 00000000 00000004 00000008 0000000c 00000000 00000000 00000000 00000000 (0) + %r13: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r14: 00000001 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r15: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r16: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r17: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r18: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r19: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r20: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r21: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r22: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r23: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r24: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r25: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r26: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r27: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r28: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r29: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r30: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r31: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) +DEBUG ../core.cpp:726: Thread mask: + 1 0 0 0 0 0 0 0 + + +DEBUG ../core.cpp:388: Now 1 active threads in 0 +********************************** Fetch ********************************* +valid: 1 +PC: 80000040 +wid: 0 +rd: 10 rs1: 0 rs2: -1 +is_lw: 0 +is_sw: 0 +fetch_stall_cycles: 3 +mem_stall_cycles: 0 +stall_warp: 0 +wspawn: 0 +stalled: 0 + + + +------------------------------------------------------ +CYCLE: 382 +Stalled Warps: +0 0 0 0 0 0 0 0 + +********************************** Writeback ********************************* +valid: 0 +PC: 0 +wid: 0 +rd: -1 rs1: -1 rs2: -1 +is_lw: 0 +is_sw: 0 +fetch_stall_cycles: 0 +mem_stall_cycles: 0 +stall_warp: 0 +wspawn: 0 +stalled: 0 +********************************** LSU ********************************* +valid: 0 +PC: 0 +wid: 2 +rd: -1 rs1: -1 rs2: -1 +is_lw: 0 +is_sw: 0 +fetch_stall_cycles: 0 +mem_stall_cycles: 0 +stall_warp: 0 +wspawn: 0 +stalled: 0 +********************************** execute_unit ********************************* +valid: 0 +PC: 0 +wid: 4 +rd: -1 rs1: -1 rs2: -1 +is_lw: 0 +is_sw: 0 +fetch_stall_cycles: 0 +mem_stall_cycles: 0 +stall_warp: 0 +wspawn: 0 +stalled: 0 +********************************** scheduler ********************************* +valid: 0 +PC: 0 +wid: 5 +rd: -1 rs1: -1 rs2: -1 +is_lw: 0 +is_sw: 0 +fetch_stall_cycles: 0 +mem_stall_cycles: 0 +stall_warp: 0 +wspawn: 0 +stalled: 0 +********************************** Decode ********************************* +valid: 0 +PC: 0 +wid: 0 +rd: -1 rs1: -1 rs2: -1 +is_lw: 0 +is_sw: 0 +fetch_stall_cycles: 0 +mem_stall_cycles: 0 +stall_warp: 0 +wspawn: 0 +stalled: 0 +********************************** Fetch ********************************* +valid: 1 +PC: 80000040 +wid: 0 +rd: 10 rs1: 0 rs2: -1 +is_lw: 0 +is_sw: 0 +fetch_stall_cycles: 2 +mem_stall_cycles: 0 +stall_warp: 0 +wspawn: 0 +stalled: 0 + + + +------------------------------------------------------ +CYCLE: 383 +Stalled Warps: +0 0 0 0 0 0 0 0 + +********************************** Writeback ********************************* +valid: 0 +PC: 0 +wid: 0 +rd: -1 rs1: -1 rs2: -1 +is_lw: 0 +is_sw: 0 +fetch_stall_cycles: 0 +mem_stall_cycles: 0 +stall_warp: 0 +wspawn: 0 +stalled: 0 +********************************** LSU ********************************* +valid: 0 +PC: 0 +wid: 2 +rd: -1 rs1: -1 rs2: -1 +is_lw: 0 +is_sw: 0 +fetch_stall_cycles: 0 +mem_stall_cycles: 0 +stall_warp: 0 +wspawn: 0 +stalled: 0 +********************************** execute_unit ********************************* +valid: 0 +PC: 0 +wid: 5 +rd: -1 rs1: -1 rs2: -1 +is_lw: 0 +is_sw: 0 +fetch_stall_cycles: 0 +mem_stall_cycles: 0 +stall_warp: 0 +wspawn: 0 +stalled: 0 +********************************** scheduler ********************************* +valid: 0 +PC: 0 +wid: 0 +rd: -1 rs1: -1 rs2: -1 +is_lw: 0 +is_sw: 0 +fetch_stall_cycles: 0 +mem_stall_cycles: 0 +stall_warp: 0 +wspawn: 0 +stalled: 0 +********************************** Decode ********************************* +valid: 0 +PC: 0 +wid: 0 +rd: -1 rs1: -1 rs2: -1 +is_lw: 0 +is_sw: 0 +fetch_stall_cycles: 0 +mem_stall_cycles: 0 +stall_warp: 0 +wspawn: 0 +stalled: 0 +********************************** Fetch ********************************* +valid: 1 +PC: 80000040 +wid: 0 +rd: 10 rs1: 0 rs2: -1 +is_lw: 0 +is_sw: 0 +fetch_stall_cycles: 1 +mem_stall_cycles: 0 +stall_warp: 0 +wspawn: 0 +stalled: 0 + + + +------------------------------------------------------ +CYCLE: 384 +Stalled Warps: +0 0 0 0 0 0 0 0 + +********************************** Writeback ********************************* +valid: 0 +PC: 0 +wid: 0 +rd: -1 rs1: -1 rs2: -1 +is_lw: 0 +is_sw: 0 +fetch_stall_cycles: 0 +mem_stall_cycles: 0 +stall_warp: 0 +wspawn: 0 +stalled: 0 +********************************** LSU ********************************* +valid: 0 +PC: 0 +wid: 2 +rd: -1 rs1: -1 rs2: -1 +is_lw: 0 +is_sw: 0 +fetch_stall_cycles: 0 +mem_stall_cycles: 0 +stall_warp: 0 +wspawn: 0 +stalled: 0 +********************************** execute_unit ********************************* +valid: 0 +PC: 0 +wid: 0 +rd: -1 rs1: -1 rs2: -1 +is_lw: 0 +is_sw: 0 +fetch_stall_cycles: 0 +mem_stall_cycles: 0 +stall_warp: 0 +wspawn: 0 +stalled: 0 +********************************** scheduler ********************************* +valid: 0 +PC: 0 +wid: 0 +rd: -1 rs1: -1 rs2: -1 +is_lw: 0 +is_sw: 0 +fetch_stall_cycles: 0 +mem_stall_cycles: 0 +stall_warp: 0 +wspawn: 0 +stalled: 0 +********************************** Decode ********************************* +valid: 0 +PC: 0 +wid: 0 +rd: -1 rs1: -1 rs2: -1 +is_lw: 0 +is_sw: 0 +fetch_stall_cycles: 0 +mem_stall_cycles: 0 +stall_warp: 0 +wspawn: 0 +stalled: 0 +********************************** Fetch ********************************* +valid: 1 +PC: 80000040 +wid: 0 +rd: 10 rs1: 0 rs2: -1 +is_lw: 0 +is_sw: 0 +fetch_stall_cycles: 0 +mem_stall_cycles: 0 +stall_warp: 0 +wspawn: 0 +stalled: 0 + + + +------------------------------------------------------ +CYCLE: 385 +Stalled Warps: +0 0 0 0 0 0 0 0 + +********************************** Writeback ********************************* +valid: 0 +PC: 0 +wid: 0 +rd: -1 rs1: -1 rs2: -1 +is_lw: 0 +is_sw: 0 +fetch_stall_cycles: 0 +mem_stall_cycles: 0 +stall_warp: 0 +wspawn: 0 +stalled: 0 +********************************** LSU ********************************* +valid: 0 +PC: 0 +wid: 2 +rd: -1 rs1: -1 rs2: -1 +is_lw: 0 +is_sw: 0 +fetch_stall_cycles: 0 +mem_stall_cycles: 0 +stall_warp: 0 +wspawn: 0 +stalled: 0 +********************************** execute_unit ********************************* +valid: 0 +PC: 0 +wid: 0 +rd: -1 rs1: -1 rs2: -1 +is_lw: 0 +is_sw: 0 +fetch_stall_cycles: 0 +mem_stall_cycles: 0 +stall_warp: 0 +wspawn: 0 +stalled: 0 +********************************** scheduler ********************************* +valid: 0 +PC: 0 +wid: 0 +rd: -1 rs1: -1 rs2: -1 +is_lw: 0 +is_sw: 0 +fetch_stall_cycles: 0 +mem_stall_cycles: 0 +stall_warp: 0 +wspawn: 0 +stalled: 0 +********************************** Decode ********************************* +valid: 1 +PC: 80000040 +wid: 0 +rd: 10 rs1: 0 rs2: -1 +is_lw: 0 +is_sw: 0 +fetch_stall_cycles: 0 +mem_stall_cycles: 0 +stall_warp: 0 +wspawn: 0 +stalled: 0 +DEBUG ../core.cpp:386: Core step stepping warp 0[1] +DEBUG ../core.cpp:683: in step pc=0x80000044 +help: in PC: 80000044 +CUrrent CODE: 5006b +DEBUG ../core.cpp:703: Fetched at 0x80000044 +DEBUG ../core.cpp:704: 0x80000044: gpgpu; +DEBUG ../instruction.cpp:350: Begin instruction execute. +DEBUG ../instruction.cpp:2117: End instruction execute. +DEBUG ../core.cpp:717: Register state: + %r 0: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r 1: 80000040 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r 2: 6ffff000 6fffec04 6fffe808 6fffe40c 00000000 00000000 00000000 00000000 (0) + %r 3: 80001808 80001808 80001808 80001808 00000000 00000000 00000000 00000000 (0) + %r 4: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r 5: 80000a6c 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r 6: 0000000f 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r 7: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r 8: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r 9: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r10: 00000004 00000001 00000001 00000001 00000000 00000000 00000000 00000000 (0) + %r11: 80000924 00000400 00000800 00000c00 00000000 00000000 00000000 00000000 (0) + %r12: 00000000 00000004 00000008 0000000c 00000000 00000000 00000000 00000000 (0) + %r13: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r14: 00000001 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r15: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r16: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r17: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r18: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r19: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r20: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r21: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r22: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r23: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r24: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r25: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r26: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r27: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r28: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r29: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r30: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r31: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) +DEBUG ../core.cpp:726: Thread mask: + 1 1 1 1 0 0 0 0 + + +DEBUG ../core.cpp:388: Now 4 active threads in 0 +********************************** Fetch ********************************* +valid: 1 +PC: 80000044 +wid: 0 +rd: 0 rs1: 10 rs2: 0 +is_lw: 0 +is_sw: 0 +fetch_stall_cycles: 0 +mem_stall_cycles: 0 +stall_warp: 1 +wspawn: 0 +stalled: 0 + + + +------------------------------------------------------ +CYCLE: 386 +Stalled Warps: +1 0 0 0 0 0 0 0 + +********************************** Writeback ********************************* +valid: 0 +PC: 0 +wid: 1 +rd: -1 rs1: -1 rs2: -1 +is_lw: 0 +is_sw: 0 +fetch_stall_cycles: 0 +mem_stall_cycles: 0 +stall_warp: 0 +wspawn: 0 +stalled: 0 +********************************** LSU ********************************* +valid: 0 +PC: 0 +wid: 2 +rd: -1 rs1: -1 rs2: -1 +is_lw: 0 +is_sw: 0 +fetch_stall_cycles: 0 +mem_stall_cycles: 0 +stall_warp: 0 +wspawn: 0 +stalled: 0 +********************************** execute_unit ********************************* +valid: 0 +PC: 0 +wid: 0 +rd: -1 rs1: -1 rs2: -1 +is_lw: 0 +is_sw: 0 +fetch_stall_cycles: 0 +mem_stall_cycles: 0 +stall_warp: 0 +wspawn: 0 +stalled: 0 +********************************** scheduler ********************************* +valid: 1 +PC: 80000040 +wid: 0 +rd: 10 rs1: 0 rs2: -1 +is_lw: 0 +is_sw: 0 +fetch_stall_cycles: 0 +mem_stall_cycles: 0 +stall_warp: 0 +wspawn: 0 +stalled: 0 +********************************** Decode ********************************* +valid: 1 +PC: 80000044 +wid: 0 +rd: 0 rs1: 10 rs2: 0 +is_lw: 0 +is_sw: 0 +fetch_stall_cycles: 0 +mem_stall_cycles: 0 +stall_warp: 1 +wspawn: 0 +stalled: 0 +********************************** Fetch ********************************* +valid: 0 +PC: 0 +wid: 1 +rd: -1 rs1: -1 rs2: -1 +is_lw: 0 +is_sw: 0 +fetch_stall_cycles: 0 +mem_stall_cycles: 0 +stall_warp: 0 +wspawn: 0 +stalled: 0 + + + +------------------------------------------------------ +CYCLE: 387 +Stalled Warps: +1 0 0 0 0 0 0 0 + +********************************** Writeback ********************************* +valid: 0 +PC: 0 +wid: 2 +rd: -1 rs1: -1 rs2: -1 +is_lw: 0 +is_sw: 0 +fetch_stall_cycles: 0 +mem_stall_cycles: 0 +stall_warp: 0 +wspawn: 0 +stalled: 0 +********************************** LSU ********************************* +valid: 0 +PC: 0 +wid: 2 +rd: -1 rs1: -1 rs2: -1 +is_lw: 0 +is_sw: 0 +fetch_stall_cycles: 0 +mem_stall_cycles: 0 +stall_warp: 0 +wspawn: 0 +stalled: 0 +********************************** execute_unit ********************************* +valid: 1 +PC: 80000040 +wid: 0 +rd: 10 rs1: 0 rs2: -1 +is_lw: 0 +is_sw: 0 +fetch_stall_cycles: 0 +mem_stall_cycles: 0 +stall_warp: 0 +wspawn: 0 +stalled: 0 +********************************** scheduler ********************************* +valid: 1 +PC: 80000044 +wid: 0 +rd: 0 rs1: 10 rs2: 0 +is_lw: 0 +is_sw: 0 +fetch_stall_cycles: 0 +mem_stall_cycles: 0 +stall_warp: 1 +wspawn: 0 +stalled: 0 +********************************** Decode ********************************* +valid: 0 +PC: 0 +wid: 1 +rd: -1 rs1: -1 rs2: -1 +is_lw: 0 +is_sw: 0 +fetch_stall_cycles: 0 +mem_stall_cycles: 0 +stall_warp: 0 +wspawn: 0 +stalled: 0 +********************************** Fetch ********************************* +valid: 0 +PC: 0 +wid: 2 +rd: -1 rs1: -1 rs2: -1 +is_lw: 0 +is_sw: 0 +fetch_stall_cycles: 0 +mem_stall_cycles: 0 +stall_warp: 0 +wspawn: 0 +stalled: 0 + + + +------------------------------------------------------ +CYCLE: 388 +Stalled Warps: +1 0 0 0 0 0 0 0 + +********************************** Writeback ********************************* +valid: 1 +PC: 80000040 +wid: 0 +rd: 10 rs1: 0 rs2: -1 +is_lw: 0 +is_sw: 0 +fetch_stall_cycles: 0 +mem_stall_cycles: 0 +stall_warp: 0 +wspawn: 0 +stalled: 0 +********************************** LSU ********************************* +valid: 0 +PC: 0 +wid: 2 +rd: -1 rs1: -1 rs2: -1 +is_lw: 0 +is_sw: 0 +fetch_stall_cycles: 0 +mem_stall_cycles: 0 +stall_warp: 0 +wspawn: 0 +stalled: 0 +&&&&&&&&&&&&&&&&&&&&&&&& EXECUTE SRCS NOT READY +********************************** execute_unit ********************************* +valid: 0 +PC: 0 +wid: 3 +rd: -1 rs1: -1 rs2: -1 +is_lw: 0 +is_sw: 0 +fetch_stall_cycles: 0 +mem_stall_cycles: 0 +stall_warp: 0 +wspawn: 0 +stalled: 0 +********************************** scheduler ********************************* +valid: 1 +PC: 80000044 +wid: 0 +rd: 0 rs1: 10 rs2: 0 +is_lw: 0 +is_sw: 0 +fetch_stall_cycles: 0 +mem_stall_cycles: 0 +stall_warp: 1 +wspawn: 0 +stalled: 1 +********************************** Decode ********************************* +valid: 0 +PC: 0 +wid: 1 +rd: -1 rs1: -1 rs2: -1 +is_lw: 0 +is_sw: 0 +fetch_stall_cycles: 0 +mem_stall_cycles: 0 +stall_warp: 0 +wspawn: 0 +stalled: 0 +********************************** Fetch ********************************* +valid: 0 +PC: 0 +wid: 2 +rd: -1 rs1: -1 rs2: -1 +is_lw: 0 +is_sw: 0 +fetch_stall_cycles: 0 +mem_stall_cycles: 0 +stall_warp: 0 +wspawn: 0 +stalled: 0 + + + +------------------------------------------------------ +CYCLE: 389 +Stalled Warps: +1 0 0 0 0 0 0 0 + +********************************** Writeback ********************************* +valid: 0 +PC: 0 +wid: 3 +rd: -1 rs1: -1 rs2: -1 +is_lw: 0 +is_sw: 0 +fetch_stall_cycles: 0 +mem_stall_cycles: 0 +stall_warp: 0 +wspawn: 0 +stalled: 0 +********************************** LSU ********************************* +valid: 0 +PC: 0 +wid: 2 +rd: -1 rs1: -1 rs2: -1 +is_lw: 0 +is_sw: 0 +fetch_stall_cycles: 0 +mem_stall_cycles: 0 +stall_warp: 0 +wspawn: 0 +stalled: 0 +********************************** execute_unit ********************************* +valid: 1 +PC: 80000044 +wid: 0 +rd: 0 rs1: 10 rs2: 0 +is_lw: 0 +is_sw: 0 +fetch_stall_cycles: 0 +mem_stall_cycles: 0 +stall_warp: 1 +wspawn: 0 +stalled: 0 +********************************** scheduler ********************************* +valid: 0 +PC: 0 +wid: 1 +rd: -1 rs1: -1 rs2: -1 +is_lw: 0 +is_sw: 0 +fetch_stall_cycles: 0 +mem_stall_cycles: 0 +stall_warp: 0 +wspawn: 0 +stalled: 0 +********************************** Decode ********************************* +valid: 0 +PC: 0 +wid: 2 +rd: -1 rs1: -1 rs2: -1 +is_lw: 0 +is_sw: 0 +fetch_stall_cycles: 0 +mem_stall_cycles: 0 +stall_warp: 0 +wspawn: 0 +stalled: 0 +********************************** Fetch ********************************* +valid: 0 +PC: 0 +wid: 3 +rd: -1 rs1: -1 rs2: -1 +is_lw: 0 +is_sw: 0 +fetch_stall_cycles: 0 +mem_stall_cycles: 0 +stall_warp: 0 +wspawn: 0 +stalled: 0 + + + +------------------------------------------------------ +CYCLE: 390 +Stalled Warps: +1 0 0 0 0 0 0 0 + +********************************** Writeback ********************************* +valid: 1 +PC: 80000044 +wid: 0 +rd: 0 rs1: 10 rs2: 0 +is_lw: 0 +is_sw: 0 +fetch_stall_cycles: 0 +mem_stall_cycles: 0 +stall_warp: 1 +wspawn: 0 +stalled: 0 +********************************** LSU ********************************* +valid: 0 +PC: 0 +wid: 2 +rd: -1 rs1: -1 rs2: -1 +is_lw: 0 +is_sw: 0 +fetch_stall_cycles: 0 +mem_stall_cycles: 0 +stall_warp: 0 +wspawn: 0 +stalled: 0 +********************************** execute_unit ********************************* +valid: 0 +PC: 0 +wid: 1 +rd: -1 rs1: -1 rs2: -1 +is_lw: 0 +is_sw: 0 +fetch_stall_cycles: 0 +mem_stall_cycles: 0 +stall_warp: 0 +wspawn: 0 +stalled: 0 +********************************** scheduler ********************************* +valid: 0 +PC: 0 +wid: 2 +rd: -1 rs1: -1 rs2: -1 +is_lw: 0 +is_sw: 0 +fetch_stall_cycles: 0 +mem_stall_cycles: 0 +stall_warp: 0 +wspawn: 0 +stalled: 0 +********************************** Decode ********************************* +valid: 0 +PC: 0 +wid: 3 +rd: -1 rs1: -1 rs2: -1 +is_lw: 0 +is_sw: 0 +fetch_stall_cycles: 0 +mem_stall_cycles: 0 +stall_warp: 0 +wspawn: 0 +stalled: 0 +********************************** Fetch ********************************* +valid: 0 +PC: 0 +wid: 4 +rd: -1 rs1: -1 rs2: -1 +is_lw: 0 +is_sw: 0 +fetch_stall_cycles: 0 +mem_stall_cycles: 0 +stall_warp: 0 +wspawn: 0 +stalled: 0 + + + +------------------------------------------------------ +CYCLE: 391 +Stalled Warps: +1 0 0 0 0 0 0 0 + +********************************** Writeback ********************************* +valid: 0 +PC: 0 +wid: 5 +rd: -1 rs1: -1 rs2: -1 +is_lw: 0 +is_sw: 0 +fetch_stall_cycles: 0 +mem_stall_cycles: 0 +stall_warp: 0 +wspawn: 0 +stalled: 0 +********************************** LSU ********************************* +valid: 0 +PC: 0 +wid: 2 +rd: -1 rs1: -1 rs2: -1 +is_lw: 0 +is_sw: 0 +fetch_stall_cycles: 0 +mem_stall_cycles: 0 +stall_warp: 0 +wspawn: 0 +stalled: 0 +********************************** execute_unit ********************************* +valid: 0 +PC: 0 +wid: 2 +rd: -1 rs1: -1 rs2: -1 +is_lw: 0 +is_sw: 0 +fetch_stall_cycles: 0 +mem_stall_cycles: 0 +stall_warp: 0 +wspawn: 0 +stalled: 0 +********************************** scheduler ********************************* +valid: 0 +PC: 0 +wid: 3 +rd: -1 rs1: -1 rs2: -1 +is_lw: 0 +is_sw: 0 +fetch_stall_cycles: 0 +mem_stall_cycles: 0 +stall_warp: 0 +wspawn: 0 +stalled: 0 +********************************** Decode ********************************* +valid: 0 +PC: 0 +wid: 4 +rd: -1 rs1: -1 rs2: -1 +is_lw: 0 +is_sw: 0 +fetch_stall_cycles: 0 +mem_stall_cycles: 0 +stall_warp: 0 +wspawn: 0 +stalled: 0 +********************************** Fetch ********************************* +valid: 0 +PC: 0 +wid: 5 +rd: -1 rs1: -1 rs2: -1 +is_lw: 0 +is_sw: 0 +fetch_stall_cycles: 0 +mem_stall_cycles: 0 +stall_warp: 0 +wspawn: 0 +stalled: 0 +Warp ID 0 is running + + + +------------------------------------------------------ +CYCLE: 392 +Stalled Warps: +0 0 0 0 0 0 0 0 + +********************************** Writeback ********************************* +valid: 0 +PC: 0 +wid: 0 +rd: -1 rs1: -1 rs2: -1 +is_lw: 0 +is_sw: 0 +fetch_stall_cycles: 0 +mem_stall_cycles: 0 +stall_warp: 0 +wspawn: 0 +stalled: 0 +********************************** LSU ********************************* +valid: 0 +PC: 0 +wid: 2 +rd: -1 rs1: -1 rs2: -1 +is_lw: 0 +is_sw: 0 +fetch_stall_cycles: 0 +mem_stall_cycles: 0 +stall_warp: 0 +wspawn: 0 +stalled: 0 +********************************** execute_unit ********************************* +valid: 0 +PC: 0 +wid: 3 +rd: -1 rs1: -1 rs2: -1 +is_lw: 0 +is_sw: 0 +fetch_stall_cycles: 0 +mem_stall_cycles: 0 +stall_warp: 0 +wspawn: 0 +stalled: 0 +********************************** scheduler ********************************* +valid: 0 +PC: 0 +wid: 4 +rd: -1 rs1: -1 rs2: -1 +is_lw: 0 +is_sw: 0 +fetch_stall_cycles: 0 +mem_stall_cycles: 0 +stall_warp: 0 +wspawn: 0 +stalled: 0 +********************************** Decode ********************************* +valid: 0 +PC: 0 +wid: 5 +rd: -1 rs1: -1 rs2: -1 +is_lw: 0 +is_sw: 0 +fetch_stall_cycles: 0 +mem_stall_cycles: 0 +stall_warp: 0 +wspawn: 0 +stalled: 0 +DEBUG ../core.cpp:386: Core step stepping warp 0[4] +DEBUG ../core.cpp:683: in step pc=0x80000048 +help: in PC: 80000048 +CUrrent CODE: 5d000ef +DEBUG ../core.cpp:703: Fetched at 0x80000048 +DEBUG ../core.cpp:704: 0x80000048: jal; +DEBUG ../instruction.cpp:350: Begin instruction execute. +DEBUG ../instruction.cpp:2117: End instruction execute. +Next PC: 800008a4 +DEBUG ../core.cpp:717: Register state: + %r 0: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r 1: 8000004c 8000004c 8000004c 8000004c 00000000 00000000 00000000 00000000 (0) + %r 2: 6ffff000 6fffec04 6fffe808 6fffe40c 00000000 00000000 00000000 00000000 (0) + %r 3: 80001808 80001808 80001808 80001808 00000000 00000000 00000000 00000000 (0) + %r 4: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r 5: 80000a6c 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r 6: 0000000f 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r 7: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r 8: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r 9: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r10: 00000004 00000001 00000001 00000001 00000000 00000000 00000000 00000000 (0) + %r11: 80000924 00000400 00000800 00000c00 00000000 00000000 00000000 00000000 (0) + %r12: 00000000 00000004 00000008 0000000c 00000000 00000000 00000000 00000000 (0) + %r13: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r14: 00000001 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r15: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r16: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r17: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r18: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r19: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r20: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r21: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r22: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r23: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r24: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r25: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r26: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r27: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r28: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r29: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r30: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r31: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) +DEBUG ../core.cpp:726: Thread mask: + 1 1 1 1 0 0 0 0 + + +DEBUG ../core.cpp:388: Now 4 active threads in 0 +********************************** Fetch ********************************* +valid: 1 +PC: 80000048 +wid: 0 +rd: 1 rs1: -1 rs2: -1 +is_lw: 0 +is_sw: 0 +fetch_stall_cycles: 0 +mem_stall_cycles: 0 +stall_warp: 1 +wspawn: 0 +stalled: 0 + + + +------------------------------------------------------ +CYCLE: 393 +Stalled Warps: +1 0 0 0 0 0 0 0 + +********************************** Writeback ********************************* +valid: 0 +PC: 0 +wid: 1 +rd: -1 rs1: -1 rs2: -1 +is_lw: 0 +is_sw: 0 +fetch_stall_cycles: 0 +mem_stall_cycles: 0 +stall_warp: 0 +wspawn: 0 +stalled: 0 +********************************** LSU ********************************* +valid: 0 +PC: 0 +wid: 2 +rd: -1 rs1: -1 rs2: -1 +is_lw: 0 +is_sw: 0 +fetch_stall_cycles: 0 +mem_stall_cycles: 0 +stall_warp: 0 +wspawn: 0 +stalled: 0 +********************************** execute_unit ********************************* +valid: 0 +PC: 0 +wid: 4 +rd: -1 rs1: -1 rs2: -1 +is_lw: 0 +is_sw: 0 +fetch_stall_cycles: 0 +mem_stall_cycles: 0 +stall_warp: 0 +wspawn: 0 +stalled: 0 +********************************** scheduler ********************************* +valid: 0 +PC: 0 +wid: 5 +rd: -1 rs1: -1 rs2: -1 +is_lw: 0 +is_sw: 0 +fetch_stall_cycles: 0 +mem_stall_cycles: 0 +stall_warp: 0 +wspawn: 0 +stalled: 0 +********************************** Decode ********************************* +valid: 1 +PC: 80000048 +wid: 0 +rd: 1 rs1: -1 rs2: -1 +is_lw: 0 +is_sw: 0 +fetch_stall_cycles: 0 +mem_stall_cycles: 0 +stall_warp: 1 +wspawn: 0 +stalled: 0 +********************************** Fetch ********************************* +valid: 0 +PC: 0 +wid: 1 +rd: -1 rs1: -1 rs2: -1 +is_lw: 0 +is_sw: 0 +fetch_stall_cycles: 0 +mem_stall_cycles: 0 +stall_warp: 0 +wspawn: 0 +stalled: 0 + + + +------------------------------------------------------ +CYCLE: 394 +Stalled Warps: +1 0 0 0 0 0 0 0 + +********************************** Writeback ********************************* +valid: 0 +PC: 0 +wid: 2 +rd: -1 rs1: -1 rs2: -1 +is_lw: 0 +is_sw: 0 +fetch_stall_cycles: 0 +mem_stall_cycles: 0 +stall_warp: 0 +wspawn: 0 +stalled: 0 +********************************** LSU ********************************* +valid: 0 +PC: 0 +wid: 2 +rd: -1 rs1: -1 rs2: -1 +is_lw: 0 +is_sw: 0 +fetch_stall_cycles: 0 +mem_stall_cycles: 0 +stall_warp: 0 +wspawn: 0 +stalled: 0 +********************************** execute_unit ********************************* +valid: 0 +PC: 0 +wid: 5 +rd: -1 rs1: -1 rs2: -1 +is_lw: 0 +is_sw: 0 +fetch_stall_cycles: 0 +mem_stall_cycles: 0 +stall_warp: 0 +wspawn: 0 +stalled: 0 +********************************** scheduler ********************************* +valid: 1 +PC: 80000048 +wid: 0 +rd: 1 rs1: -1 rs2: -1 +is_lw: 0 +is_sw: 0 +fetch_stall_cycles: 0 +mem_stall_cycles: 0 +stall_warp: 1 +wspawn: 0 +stalled: 0 +********************************** Decode ********************************* +valid: 0 +PC: 0 +wid: 1 +rd: -1 rs1: -1 rs2: -1 +is_lw: 0 +is_sw: 0 +fetch_stall_cycles: 0 +mem_stall_cycles: 0 +stall_warp: 0 +wspawn: 0 +stalled: 0 +********************************** Fetch ********************************* +valid: 0 +PC: 0 +wid: 2 +rd: -1 rs1: -1 rs2: -1 +is_lw: 0 +is_sw: 0 +fetch_stall_cycles: 0 +mem_stall_cycles: 0 +stall_warp: 0 +wspawn: 0 +stalled: 0 + + + +------------------------------------------------------ +CYCLE: 395 +Stalled Warps: +1 0 0 0 0 0 0 0 + +********************************** Writeback ********************************* +valid: 0 +PC: 0 +wid: 3 +rd: -1 rs1: -1 rs2: -1 +is_lw: 0 +is_sw: 0 +fetch_stall_cycles: 0 +mem_stall_cycles: 0 +stall_warp: 0 +wspawn: 0 +stalled: 0 +********************************** LSU ********************************* +valid: 0 +PC: 0 +wid: 2 +rd: -1 rs1: -1 rs2: -1 +is_lw: 0 +is_sw: 0 +fetch_stall_cycles: 0 +mem_stall_cycles: 0 +stall_warp: 0 +wspawn: 0 +stalled: 0 +********************************** execute_unit ********************************* +valid: 1 +PC: 80000048 +wid: 0 +rd: 1 rs1: -1 rs2: -1 +is_lw: 0 +is_sw: 0 +fetch_stall_cycles: 0 +mem_stall_cycles: 0 +stall_warp: 1 +wspawn: 0 +stalled: 0 +********************************** scheduler ********************************* +valid: 0 +PC: 0 +wid: 1 +rd: -1 rs1: -1 rs2: -1 +is_lw: 0 +is_sw: 0 +fetch_stall_cycles: 0 +mem_stall_cycles: 0 +stall_warp: 0 +wspawn: 0 +stalled: 0 +********************************** Decode ********************************* +valid: 0 +PC: 0 +wid: 2 +rd: -1 rs1: -1 rs2: -1 +is_lw: 0 +is_sw: 0 +fetch_stall_cycles: 0 +mem_stall_cycles: 0 +stall_warp: 0 +wspawn: 0 +stalled: 0 +********************************** Fetch ********************************* +valid: 0 +PC: 0 +wid: 3 +rd: -1 rs1: -1 rs2: -1 +is_lw: 0 +is_sw: 0 +fetch_stall_cycles: 0 +mem_stall_cycles: 0 +stall_warp: 0 +wspawn: 0 +stalled: 0 + + + +------------------------------------------------------ +CYCLE: 396 +Stalled Warps: +1 0 0 0 0 0 0 0 + +********************************** Writeback ********************************* +valid: 1 +PC: 80000048 +wid: 0 +rd: 1 rs1: -1 rs2: -1 +is_lw: 0 +is_sw: 0 +fetch_stall_cycles: 0 +mem_stall_cycles: 0 +stall_warp: 1 +wspawn: 0 +stalled: 0 +********************************** LSU ********************************* +valid: 0 +PC: 0 +wid: 2 +rd: -1 rs1: -1 rs2: -1 +is_lw: 0 +is_sw: 0 +fetch_stall_cycles: 0 +mem_stall_cycles: 0 +stall_warp: 0 +wspawn: 0 +stalled: 0 +********************************** execute_unit ********************************* +valid: 0 +PC: 0 +wid: 1 +rd: -1 rs1: -1 rs2: -1 +is_lw: 0 +is_sw: 0 +fetch_stall_cycles: 0 +mem_stall_cycles: 0 +stall_warp: 0 +wspawn: 0 +stalled: 0 +********************************** scheduler ********************************* +valid: 0 +PC: 0 +wid: 2 +rd: -1 rs1: -1 rs2: -1 +is_lw: 0 +is_sw: 0 +fetch_stall_cycles: 0 +mem_stall_cycles: 0 +stall_warp: 0 +wspawn: 0 +stalled: 0 +********************************** Decode ********************************* +valid: 0 +PC: 0 +wid: 3 +rd: -1 rs1: -1 rs2: -1 +is_lw: 0 +is_sw: 0 +fetch_stall_cycles: 0 +mem_stall_cycles: 0 +stall_warp: 0 +wspawn: 0 +stalled: 0 +********************************** Fetch ********************************* +valid: 0 +PC: 0 +wid: 4 +rd: -1 rs1: -1 rs2: -1 +is_lw: 0 +is_sw: 0 +fetch_stall_cycles: 0 +mem_stall_cycles: 0 +stall_warp: 0 +wspawn: 0 +stalled: 0 + + + +------------------------------------------------------ +CYCLE: 397 +Stalled Warps: +1 0 0 0 0 0 0 0 + +********************************** Writeback ********************************* +valid: 0 +PC: 0 +wid: 5 +rd: -1 rs1: -1 rs2: -1 +is_lw: 0 +is_sw: 0 +fetch_stall_cycles: 0 +mem_stall_cycles: 0 +stall_warp: 0 +wspawn: 0 +stalled: 0 +********************************** LSU ********************************* +valid: 0 +PC: 0 +wid: 2 +rd: -1 rs1: -1 rs2: -1 +is_lw: 0 +is_sw: 0 +fetch_stall_cycles: 0 +mem_stall_cycles: 0 +stall_warp: 0 +wspawn: 0 +stalled: 0 +********************************** execute_unit ********************************* +valid: 0 +PC: 0 +wid: 2 +rd: -1 rs1: -1 rs2: -1 +is_lw: 0 +is_sw: 0 +fetch_stall_cycles: 0 +mem_stall_cycles: 0 +stall_warp: 0 +wspawn: 0 +stalled: 0 +********************************** scheduler ********************************* +valid: 0 +PC: 0 +wid: 3 +rd: -1 rs1: -1 rs2: -1 +is_lw: 0 +is_sw: 0 +fetch_stall_cycles: 0 +mem_stall_cycles: 0 +stall_warp: 0 +wspawn: 0 +stalled: 0 +********************************** Decode ********************************* +valid: 0 +PC: 0 +wid: 4 +rd: -1 rs1: -1 rs2: -1 +is_lw: 0 +is_sw: 0 +fetch_stall_cycles: 0 +mem_stall_cycles: 0 +stall_warp: 0 +wspawn: 0 +stalled: 0 +********************************** Fetch ********************************* +valid: 0 +PC: 0 +wid: 5 +rd: -1 rs1: -1 rs2: -1 +is_lw: 0 +is_sw: 0 +fetch_stall_cycles: 0 +mem_stall_cycles: 0 +stall_warp: 0 +wspawn: 0 +stalled: 0 +Warp ID 0 is running + + + +------------------------------------------------------ +CYCLE: 398 +Stalled Warps: +0 0 0 0 0 0 0 0 + +********************************** Writeback ********************************* +valid: 0 +PC: 0 +wid: 0 +rd: -1 rs1: -1 rs2: -1 +is_lw: 0 +is_sw: 0 +fetch_stall_cycles: 0 +mem_stall_cycles: 0 +stall_warp: 0 +wspawn: 0 +stalled: 0 +********************************** LSU ********************************* +valid: 0 +PC: 0 +wid: 2 +rd: -1 rs1: -1 rs2: -1 +is_lw: 0 +is_sw: 0 +fetch_stall_cycles: 0 +mem_stall_cycles: 0 +stall_warp: 0 +wspawn: 0 +stalled: 0 +********************************** execute_unit ********************************* +valid: 0 +PC: 0 +wid: 3 +rd: -1 rs1: -1 rs2: -1 +is_lw: 0 +is_sw: 0 +fetch_stall_cycles: 0 +mem_stall_cycles: 0 +stall_warp: 0 +wspawn: 0 +stalled: 0 +********************************** scheduler ********************************* +valid: 0 +PC: 0 +wid: 4 +rd: -1 rs1: -1 rs2: -1 +is_lw: 0 +is_sw: 0 +fetch_stall_cycles: 0 +mem_stall_cycles: 0 +stall_warp: 0 +wspawn: 0 +stalled: 0 +********************************** Decode ********************************* +valid: 0 +PC: 0 +wid: 5 +rd: -1 rs1: -1 rs2: -1 +is_lw: 0 +is_sw: 0 +fetch_stall_cycles: 0 +mem_stall_cycles: 0 +stall_warp: 0 +wspawn: 0 +stalled: 0 +DEBUG ../core.cpp:386: Core step stepping warp 0[4] +DEBUG ../core.cpp:683: in step pc=0x800008a4 +help: in PC: 800008a4 +CUrrent CODE: ff010113 +DEBUG ../core.cpp:703: Fetched at 0x800008a4 +DEBUG ../core.cpp:704: 0x800008a4: i_type; +DEBUG ../instruction.cpp:350: Begin instruction execute. +DEBUG ../instruction.cpp:2117: End instruction execute. +DEBUG ../core.cpp:717: Register state: + %r 0: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r 1: 8000004c 8000004c 8000004c 8000004c 00000000 00000000 00000000 00000000 (0) + %r 2: 6fffeff0 6fffebf4 6fffe7f8 6fffe3fc 00000000 00000000 00000000 00000000 (0) + %r 3: 80001808 80001808 80001808 80001808 00000000 00000000 00000000 00000000 (0) + %r 4: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r 5: 80000a6c 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r 6: 0000000f 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r 7: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r 8: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r 9: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r10: 00000004 00000001 00000001 00000001 00000000 00000000 00000000 00000000 (0) + %r11: 80000924 00000400 00000800 00000c00 00000000 00000000 00000000 00000000 (0) + %r12: 00000000 00000004 00000008 0000000c 00000000 00000000 00000000 00000000 (0) + %r13: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r14: 00000001 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r15: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r16: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r17: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r18: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r19: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r20: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r21: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r22: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r23: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r24: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r25: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r26: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r27: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r28: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r29: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r30: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r31: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) +DEBUG ../core.cpp:726: Thread mask: + 1 1 1 1 0 0 0 0 + + +DEBUG ../core.cpp:388: Now 4 active threads in 0 +********************************** Fetch ********************************* +valid: 1 +PC: 800008a4 +wid: 0 +rd: 2 rs1: 2 rs2: -1 +is_lw: 0 +is_sw: 0 +fetch_stall_cycles: 3 +mem_stall_cycles: 0 +stall_warp: 0 +wspawn: 0 +stalled: 0 + + + +------------------------------------------------------ +CYCLE: 399 +Stalled Warps: +0 0 0 0 0 0 0 0 + +********************************** Writeback ********************************* +valid: 0 +PC: 0 +wid: 0 +rd: -1 rs1: -1 rs2: -1 +is_lw: 0 +is_sw: 0 +fetch_stall_cycles: 0 +mem_stall_cycles: 0 +stall_warp: 0 +wspawn: 0 +stalled: 0 +********************************** LSU ********************************* +valid: 0 +PC: 0 +wid: 2 +rd: -1 rs1: -1 rs2: -1 +is_lw: 0 +is_sw: 0 +fetch_stall_cycles: 0 +mem_stall_cycles: 0 +stall_warp: 0 +wspawn: 0 +stalled: 0 +********************************** execute_unit ********************************* +valid: 0 +PC: 0 +wid: 4 +rd: -1 rs1: -1 rs2: -1 +is_lw: 0 +is_sw: 0 +fetch_stall_cycles: 0 +mem_stall_cycles: 0 +stall_warp: 0 +wspawn: 0 +stalled: 0 +********************************** scheduler ********************************* +valid: 0 +PC: 0 +wid: 5 +rd: -1 rs1: -1 rs2: -1 +is_lw: 0 +is_sw: 0 +fetch_stall_cycles: 0 +mem_stall_cycles: 0 +stall_warp: 0 +wspawn: 0 +stalled: 0 +********************************** Decode ********************************* +valid: 0 +PC: 0 +wid: 0 +rd: -1 rs1: -1 rs2: -1 +is_lw: 0 +is_sw: 0 +fetch_stall_cycles: 0 +mem_stall_cycles: 0 +stall_warp: 0 +wspawn: 0 +stalled: 0 +********************************** Fetch ********************************* +valid: 1 +PC: 800008a4 +wid: 0 +rd: 2 rs1: 2 rs2: -1 +is_lw: 0 +is_sw: 0 +fetch_stall_cycles: 2 +mem_stall_cycles: 0 +stall_warp: 0 +wspawn: 0 +stalled: 0 + + + +------------------------------------------------------ +CYCLE: 400 +Stalled Warps: +0 0 0 0 0 0 0 0 + +********************************** Writeback ********************************* +valid: 0 +PC: 0 +wid: 0 +rd: -1 rs1: -1 rs2: -1 +is_lw: 0 +is_sw: 0 +fetch_stall_cycles: 0 +mem_stall_cycles: 0 +stall_warp: 0 +wspawn: 0 +stalled: 0 +********************************** LSU ********************************* +valid: 0 +PC: 0 +wid: 2 +rd: -1 rs1: -1 rs2: -1 +is_lw: 0 +is_sw: 0 +fetch_stall_cycles: 0 +mem_stall_cycles: 0 +stall_warp: 0 +wspawn: 0 +stalled: 0 +********************************** execute_unit ********************************* +valid: 0 +PC: 0 +wid: 5 +rd: -1 rs1: -1 rs2: -1 +is_lw: 0 +is_sw: 0 +fetch_stall_cycles: 0 +mem_stall_cycles: 0 +stall_warp: 0 +wspawn: 0 +stalled: 0 +********************************** scheduler ********************************* +valid: 0 +PC: 0 +wid: 0 +rd: -1 rs1: -1 rs2: -1 +is_lw: 0 +is_sw: 0 +fetch_stall_cycles: 0 +mem_stall_cycles: 0 +stall_warp: 0 +wspawn: 0 +stalled: 0 +********************************** Decode ********************************* +valid: 0 +PC: 0 +wid: 0 +rd: -1 rs1: -1 rs2: -1 +is_lw: 0 +is_sw: 0 +fetch_stall_cycles: 0 +mem_stall_cycles: 0 +stall_warp: 0 +wspawn: 0 +stalled: 0 +********************************** Fetch ********************************* +valid: 1 +PC: 800008a4 +wid: 0 +rd: 2 rs1: 2 rs2: -1 +is_lw: 0 +is_sw: 0 +fetch_stall_cycles: 1 +mem_stall_cycles: 0 +stall_warp: 0 +wspawn: 0 +stalled: 0 + + + +------------------------------------------------------ +CYCLE: 401 +Stalled Warps: +0 0 0 0 0 0 0 0 + +********************************** Writeback ********************************* +valid: 0 +PC: 0 +wid: 0 +rd: -1 rs1: -1 rs2: -1 +is_lw: 0 +is_sw: 0 +fetch_stall_cycles: 0 +mem_stall_cycles: 0 +stall_warp: 0 +wspawn: 0 +stalled: 0 +********************************** LSU ********************************* +valid: 0 +PC: 0 +wid: 2 +rd: -1 rs1: -1 rs2: -1 +is_lw: 0 +is_sw: 0 +fetch_stall_cycles: 0 +mem_stall_cycles: 0 +stall_warp: 0 +wspawn: 0 +stalled: 0 +********************************** execute_unit ********************************* +valid: 0 +PC: 0 +wid: 0 +rd: -1 rs1: -1 rs2: -1 +is_lw: 0 +is_sw: 0 +fetch_stall_cycles: 0 +mem_stall_cycles: 0 +stall_warp: 0 +wspawn: 0 +stalled: 0 +********************************** scheduler ********************************* +valid: 0 +PC: 0 +wid: 0 +rd: -1 rs1: -1 rs2: -1 +is_lw: 0 +is_sw: 0 +fetch_stall_cycles: 0 +mem_stall_cycles: 0 +stall_warp: 0 +wspawn: 0 +stalled: 0 +********************************** Decode ********************************* +valid: 0 +PC: 0 +wid: 0 +rd: -1 rs1: -1 rs2: -1 +is_lw: 0 +is_sw: 0 +fetch_stall_cycles: 0 +mem_stall_cycles: 0 +stall_warp: 0 +wspawn: 0 +stalled: 0 +********************************** Fetch ********************************* +valid: 1 +PC: 800008a4 +wid: 0 +rd: 2 rs1: 2 rs2: -1 +is_lw: 0 +is_sw: 0 +fetch_stall_cycles: 0 +mem_stall_cycles: 0 +stall_warp: 0 +wspawn: 0 +stalled: 0 + + + +------------------------------------------------------ +CYCLE: 402 +Stalled Warps: +0 0 0 0 0 0 0 0 + +********************************** Writeback ********************************* +valid: 0 +PC: 0 +wid: 0 +rd: -1 rs1: -1 rs2: -1 +is_lw: 0 +is_sw: 0 +fetch_stall_cycles: 0 +mem_stall_cycles: 0 +stall_warp: 0 +wspawn: 0 +stalled: 0 +********************************** LSU ********************************* +valid: 0 +PC: 0 +wid: 2 +rd: -1 rs1: -1 rs2: -1 +is_lw: 0 +is_sw: 0 +fetch_stall_cycles: 0 +mem_stall_cycles: 0 +stall_warp: 0 +wspawn: 0 +stalled: 0 +********************************** execute_unit ********************************* +valid: 0 +PC: 0 +wid: 0 +rd: -1 rs1: -1 rs2: -1 +is_lw: 0 +is_sw: 0 +fetch_stall_cycles: 0 +mem_stall_cycles: 0 +stall_warp: 0 +wspawn: 0 +stalled: 0 +********************************** scheduler ********************************* +valid: 0 +PC: 0 +wid: 0 +rd: -1 rs1: -1 rs2: -1 +is_lw: 0 +is_sw: 0 +fetch_stall_cycles: 0 +mem_stall_cycles: 0 +stall_warp: 0 +wspawn: 0 +stalled: 0 +********************************** Decode ********************************* +valid: 1 +PC: 800008a4 +wid: 0 +rd: 2 rs1: 2 rs2: -1 +is_lw: 0 +is_sw: 0 +fetch_stall_cycles: 0 +mem_stall_cycles: 0 +stall_warp: 0 +wspawn: 0 +stalled: 0 +DEBUG ../core.cpp:386: Core step stepping warp 0[4] +DEBUG ../core.cpp:683: in step pc=0x800008a8 +help: in PC: 800008a8 +CUrrent CODE: 112623 +DEBUG ../core.cpp:703: Fetched at 0x800008a8 +DEBUG ../core.cpp:704: 0x800008a8: store; +DEBUG ../instruction.cpp:350: Begin instruction execute. +STORE MEM ADDRESS: 6fffeff0 + c +STORE MEM ADDRESS: 6fffebf4 + c +STORE MEM ADDRESS: 6fffe7f8 + c +STORE MEM ADDRESS: 6fffe3fc + c +DEBUG ../instruction.cpp:2117: End instruction execute. +DEBUG ../core.cpp:717: Register state: + %r 0: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r 1: 8000004c 8000004c 8000004c 8000004c 00000000 00000000 00000000 00000000 (0) + %r 2: 6fffeff0 6fffebf4 6fffe7f8 6fffe3fc 00000000 00000000 00000000 00000000 (0) + %r 3: 80001808 80001808 80001808 80001808 00000000 00000000 00000000 00000000 (0) + %r 4: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r 5: 80000a6c 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r 6: 0000000f 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r 7: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r 8: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r 9: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r10: 00000004 00000001 00000001 00000001 00000000 00000000 00000000 00000000 (0) + %r11: 80000924 00000400 00000800 00000c00 00000000 00000000 00000000 00000000 (0) + %r12: 00000000 00000004 00000008 0000000c 00000000 00000000 00000000 00000000 (0) + %r13: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r14: 00000001 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r15: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r16: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r17: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r18: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r19: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r20: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r21: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r22: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r23: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r24: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r25: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r26: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r27: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r28: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r29: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r30: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r31: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) +DEBUG ../core.cpp:726: Thread mask: + 1 1 1 1 0 0 0 0 + + +DEBUG ../core.cpp:388: Now 4 active threads in 0 +********************************** Fetch ********************************* +valid: 1 +PC: 800008a8 +wid: 0 +rd: -1 rs1: 2 rs2: 1 +is_lw: 0 +is_sw: 1 +fetch_stall_cycles: 0 +mem_stall_cycles: 9 +stall_warp: 0 +wspawn: 0 +stalled: 0 + + + +------------------------------------------------------ +CYCLE: 403 +Stalled Warps: +0 0 0 0 0 0 0 0 + +********************************** Writeback ********************************* +valid: 0 +PC: 0 +wid: 0 +rd: -1 rs1: -1 rs2: -1 +is_lw: 0 +is_sw: 0 +fetch_stall_cycles: 0 +mem_stall_cycles: 0 +stall_warp: 0 +wspawn: 0 +stalled: 0 +********************************** LSU ********************************* +valid: 0 +PC: 0 +wid: 2 +rd: -1 rs1: -1 rs2: -1 +is_lw: 0 +is_sw: 0 +fetch_stall_cycles: 0 +mem_stall_cycles: 0 +stall_warp: 0 +wspawn: 0 +stalled: 0 +********************************** execute_unit ********************************* +valid: 0 +PC: 0 +wid: 0 +rd: -1 rs1: -1 rs2: -1 +is_lw: 0 +is_sw: 0 +fetch_stall_cycles: 0 +mem_stall_cycles: 0 +stall_warp: 0 +wspawn: 0 +stalled: 0 +********************************** scheduler ********************************* +valid: 1 +PC: 800008a4 +wid: 0 +rd: 2 rs1: 2 rs2: -1 +is_lw: 0 +is_sw: 0 +fetch_stall_cycles: 0 +mem_stall_cycles: 0 +stall_warp: 0 +wspawn: 0 +stalled: 0 +********************************** Decode ********************************* +valid: 1 +PC: 800008a8 +wid: 0 +rd: -1 rs1: 2 rs2: 1 +is_lw: 0 +is_sw: 1 +fetch_stall_cycles: 0 +mem_stall_cycles: 9 +stall_warp: 0 +wspawn: 0 +stalled: 0 +DEBUG ../core.cpp:386: Core step stepping warp 0[4] +DEBUG ../core.cpp:683: in step pc=0x800008ac +help: in PC: 800008ac +CUrrent CODE: 812423 +DEBUG ../core.cpp:703: Fetched at 0x800008ac +DEBUG ../core.cpp:704: 0x800008ac: store; +DEBUG ../instruction.cpp:350: Begin instruction execute. +STORE MEM ADDRESS: 6fffeff0 + 8 +STORE MEM ADDRESS: 6fffebf4 + 8 +STORE MEM ADDRESS: 6fffe7f8 + 8 +STORE MEM ADDRESS: 6fffe3fc + 8 +DEBUG ../instruction.cpp:2117: End instruction execute. +DEBUG ../core.cpp:717: Register state: + %r 0: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r 1: 8000004c 8000004c 8000004c 8000004c 00000000 00000000 00000000 00000000 (0) + %r 2: 6fffeff0 6fffebf4 6fffe7f8 6fffe3fc 00000000 00000000 00000000 00000000 (0) + %r 3: 80001808 80001808 80001808 80001808 00000000 00000000 00000000 00000000 (0) + %r 4: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r 5: 80000a6c 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r 6: 0000000f 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r 7: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r 8: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r 9: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r10: 00000004 00000001 00000001 00000001 00000000 00000000 00000000 00000000 (0) + %r11: 80000924 00000400 00000800 00000c00 00000000 00000000 00000000 00000000 (0) + %r12: 00000000 00000004 00000008 0000000c 00000000 00000000 00000000 00000000 (0) + %r13: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r14: 00000001 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r15: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r16: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r17: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r18: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r19: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r20: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r21: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r22: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r23: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r24: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r25: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r26: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r27: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r28: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r29: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r30: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r31: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) +DEBUG ../core.cpp:726: Thread mask: + 1 1 1 1 0 0 0 0 + + +DEBUG ../core.cpp:388: Now 4 active threads in 0 +********************************** Fetch ********************************* +valid: 1 +PC: 800008ac +wid: 0 +rd: -1 rs1: 2 rs2: 8 +is_lw: 0 +is_sw: 1 +fetch_stall_cycles: 0 +mem_stall_cycles: 3 +stall_warp: 0 +wspawn: 0 +stalled: 0 + + + +------------------------------------------------------ +CYCLE: 404 +Stalled Warps: +0 0 0 0 0 0 0 0 + +********************************** Writeback ********************************* +valid: 0 +PC: 0 +wid: 0 +rd: -1 rs1: -1 rs2: -1 +is_lw: 0 +is_sw: 0 +fetch_stall_cycles: 0 +mem_stall_cycles: 0 +stall_warp: 0 +wspawn: 0 +stalled: 0 +********************************** LSU ********************************* +valid: 0 +PC: 0 +wid: 2 +rd: -1 rs1: -1 rs2: -1 +is_lw: 0 +is_sw: 0 +fetch_stall_cycles: 0 +mem_stall_cycles: 0 +stall_warp: 0 +wspawn: 0 +stalled: 0 +********************************** execute_unit ********************************* +valid: 1 +PC: 800008a4 +wid: 0 +rd: 2 rs1: 2 rs2: -1 +is_lw: 0 +is_sw: 0 +fetch_stall_cycles: 0 +mem_stall_cycles: 0 +stall_warp: 0 +wspawn: 0 +stalled: 0 +********************************** scheduler ********************************* +valid: 1 +PC: 800008a8 +wid: 0 +rd: -1 rs1: 2 rs2: 1 +is_lw: 0 +is_sw: 1 +fetch_stall_cycles: 0 +mem_stall_cycles: 9 +stall_warp: 0 +wspawn: 0 +stalled: 0 +********************************** Decode ********************************* +valid: 1 +PC: 800008ac +wid: 0 +rd: -1 rs1: 2 rs2: 8 +is_lw: 0 +is_sw: 1 +fetch_stall_cycles: 0 +mem_stall_cycles: 3 +stall_warp: 0 +wspawn: 0 +stalled: 0 +DEBUG ../core.cpp:386: Core step stepping warp 0[4] +DEBUG ../core.cpp:683: in step pc=0x800008b0 +help: in PC: 800008b0 +CUrrent CODE: 1010413 +DEBUG ../core.cpp:703: Fetched at 0x800008b0 +DEBUG ../core.cpp:704: 0x800008b0: i_type; +DEBUG ../instruction.cpp:350: Begin instruction execute. +DEBUG ../instruction.cpp:2117: End instruction execute. +DEBUG ../core.cpp:717: Register state: + %r 0: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r 1: 8000004c 8000004c 8000004c 8000004c 00000000 00000000 00000000 00000000 (0) + %r 2: 6fffeff0 6fffebf4 6fffe7f8 6fffe3fc 00000000 00000000 00000000 00000000 (0) + %r 3: 80001808 80001808 80001808 80001808 00000000 00000000 00000000 00000000 (0) + %r 4: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r 5: 80000a6c 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r 6: 0000000f 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r 7: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r 8: 6ffff000 6fffec04 6fffe808 6fffe40c 00000000 00000000 00000000 00000000 (0) + %r 9: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r10: 00000004 00000001 00000001 00000001 00000000 00000000 00000000 00000000 (0) + %r11: 80000924 00000400 00000800 00000c00 00000000 00000000 00000000 00000000 (0) + %r12: 00000000 00000004 00000008 0000000c 00000000 00000000 00000000 00000000 (0) + %r13: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r14: 00000001 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r15: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r16: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r17: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r18: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r19: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r20: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r21: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r22: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r23: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r24: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r25: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r26: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r27: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r28: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r29: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r30: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r31: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) +DEBUG ../core.cpp:726: Thread mask: + 1 1 1 1 0 0 0 0 + + +DEBUG ../core.cpp:388: Now 4 active threads in 0 +********************************** Fetch ********************************* +valid: 1 +PC: 800008b0 +wid: 0 +rd: 8 rs1: 2 rs2: -1 +is_lw: 0 +is_sw: 0 +fetch_stall_cycles: 3 +mem_stall_cycles: 0 +stall_warp: 0 +wspawn: 0 +stalled: 0 + + + +------------------------------------------------------ +CYCLE: 405 +Stalled Warps: +0 0 0 0 0 0 0 0 + +********************************** Writeback ********************************* +valid: 1 +PC: 800008a4 +wid: 0 +rd: 2 rs1: 2 rs2: -1 +is_lw: 0 +is_sw: 0 +fetch_stall_cycles: 0 +mem_stall_cycles: 0 +stall_warp: 0 +wspawn: 0 +stalled: 0 +********************************** LSU ********************************* +valid: 0 +PC: 0 +wid: 2 +rd: -1 rs1: -1 rs2: -1 +is_lw: 0 +is_sw: 0 +fetch_stall_cycles: 0 +mem_stall_cycles: 0 +stall_warp: 0 +wspawn: 0 +stalled: 0 +********************************** execute_unit ********************************* +valid: 0 +PC: 0 +wid: 0 +rd: -1 rs1: -1 rs2: -1 +is_lw: 0 +is_sw: 0 +fetch_stall_cycles: 0 +mem_stall_cycles: 0 +stall_warp: 0 +wspawn: 0 +stalled: 0 +********************************** scheduler ********************************* +valid: 1 +PC: 800008a8 +wid: 0 +rd: -1 rs1: 2 rs2: 1 +is_lw: 0 +is_sw: 1 +fetch_stall_cycles: 0 +mem_stall_cycles: 9 +stall_warp: 0 +wspawn: 0 +stalled: 1 +********************************** Decode ********************************* +valid: 1 +PC: 800008ac +wid: 0 +rd: -1 rs1: 2 rs2: 8 +is_lw: 0 +is_sw: 1 +fetch_stall_cycles: 0 +mem_stall_cycles: 3 +stall_warp: 0 +wspawn: 0 +stalled: 0 +********************************** Fetch ********************************* +valid: 1 +PC: 800008b0 +wid: 0 +rd: 8 rs1: 2 rs2: -1 +is_lw: 0 +is_sw: 0 +fetch_stall_cycles: 2 +mem_stall_cycles: 0 +stall_warp: 0 +wspawn: 0 +stalled: 0 + + + +------------------------------------------------------ +CYCLE: 406 +Stalled Warps: +0 0 0 0 0 0 0 0 + +********************************** Writeback ********************************* +valid: 0 +PC: 0 +wid: 0 +rd: -1 rs1: -1 rs2: -1 +is_lw: 0 +is_sw: 0 +fetch_stall_cycles: 0 +mem_stall_cycles: 0 +stall_warp: 0 +wspawn: 0 +stalled: 0 +********************************** LSU ********************************* +valid: 1 +PC: 800008a8 +wid: 0 +rd: -1 rs1: 2 rs2: 1 +is_lw: 0 +is_sw: 1 +fetch_stall_cycles: 0 +mem_stall_cycles: 8 +stall_warp: 0 +wspawn: 0 +stalled: 0 +********************************** execute_unit ********************************* +valid: 0 +PC: 0 +wid: 0 +rd: -1 rs1: -1 rs2: -1 +is_lw: 0 +is_sw: 0 +fetch_stall_cycles: 0 +mem_stall_cycles: 0 +stall_warp: 0 +wspawn: 0 +stalled: 0 +********************************** scheduler ********************************* +valid: 1 +PC: 800008ac +wid: 0 +rd: -1 rs1: 2 rs2: 8 +is_lw: 0 +is_sw: 1 +fetch_stall_cycles: 0 +mem_stall_cycles: 3 +stall_warp: 0 +wspawn: 0 +stalled: 0 +********************************** Decode ********************************* +valid: 0 +PC: 0 +wid: 0 +rd: -1 rs1: -1 rs2: -1 +is_lw: 0 +is_sw: 0 +fetch_stall_cycles: 0 +mem_stall_cycles: 0 +stall_warp: 0 +wspawn: 0 +stalled: 0 +********************************** Fetch ********************************* +valid: 1 +PC: 800008b0 +wid: 0 +rd: 8 rs1: 2 rs2: -1 +is_lw: 0 +is_sw: 0 +fetch_stall_cycles: 1 +mem_stall_cycles: 0 +stall_warp: 0 +wspawn: 0 +stalled: 0 + + + +------------------------------------------------------ +CYCLE: 407 +Stalled Warps: +0 0 0 0 0 0 0 0 + +********************************** Writeback ********************************* +valid: 0 +PC: 0 +wid: 0 +rd: -1 rs1: -1 rs2: -1 +is_lw: 0 +is_sw: 0 +fetch_stall_cycles: 0 +mem_stall_cycles: 0 +stall_warp: 0 +wspawn: 0 +stalled: 0 +********************************** LSU ********************************* +valid: 1 +PC: 800008ac +wid: 0 +rd: -1 rs1: 2 rs2: 8 +is_lw: 0 +is_sw: 1 +fetch_stall_cycles: 0 +mem_stall_cycles: 2 +stall_warp: 0 +wspawn: 0 +stalled: 0 +********************************** execute_unit ********************************* +valid: 0 +PC: 0 +wid: 0 +rd: -1 rs1: -1 rs2: -1 +is_lw: 0 +is_sw: 0 +fetch_stall_cycles: 0 +mem_stall_cycles: 0 +stall_warp: 0 +wspawn: 0 +stalled: 0 +********************************** scheduler ********************************* +valid: 0 +PC: 0 +wid: 0 +rd: -1 rs1: -1 rs2: -1 +is_lw: 0 +is_sw: 0 +fetch_stall_cycles: 0 +mem_stall_cycles: 0 +stall_warp: 0 +wspawn: 0 +stalled: 0 +********************************** Decode ********************************* +valid: 0 +PC: 0 +wid: 0 +rd: -1 rs1: -1 rs2: -1 +is_lw: 0 +is_sw: 0 +fetch_stall_cycles: 0 +mem_stall_cycles: 0 +stall_warp: 0 +wspawn: 0 +stalled: 0 +********************************** Fetch ********************************* +valid: 1 +PC: 800008b0 +wid: 0 +rd: 8 rs1: 2 rs2: -1 +is_lw: 0 +is_sw: 0 +fetch_stall_cycles: 0 +mem_stall_cycles: 0 +stall_warp: 0 +wspawn: 0 +stalled: 0 + + + +------------------------------------------------------ +CYCLE: 408 +Stalled Warps: +0 0 0 0 0 0 0 0 + +********************************** Writeback ********************************* +valid: 0 +PC: 0 +wid: 0 +rd: -1 rs1: -1 rs2: -1 +is_lw: 0 +is_sw: 0 +fetch_stall_cycles: 0 +mem_stall_cycles: 0 +stall_warp: 0 +wspawn: 0 +stalled: 0 +********************************** LSU ********************************* +valid: 0 +PC: 0 +wid: 0 +rd: -1 rs1: -1 rs2: -1 +is_lw: 0 +is_sw: 0 +fetch_stall_cycles: 0 +mem_stall_cycles: 0 +stall_warp: 0 +wspawn: 0 +stalled: 0 +********************************** execute_unit ********************************* +valid: 0 +PC: 0 +wid: 0 +rd: -1 rs1: -1 rs2: -1 +is_lw: 0 +is_sw: 0 +fetch_stall_cycles: 0 +mem_stall_cycles: 0 +stall_warp: 0 +wspawn: 0 +stalled: 0 +********************************** scheduler ********************************* +valid: 0 +PC: 0 +wid: 0 +rd: -1 rs1: -1 rs2: -1 +is_lw: 0 +is_sw: 0 +fetch_stall_cycles: 0 +mem_stall_cycles: 0 +stall_warp: 0 +wspawn: 0 +stalled: 0 +********************************** Decode ********************************* +valid: 1 +PC: 800008b0 +wid: 0 +rd: 8 rs1: 2 rs2: -1 +is_lw: 0 +is_sw: 0 +fetch_stall_cycles: 0 +mem_stall_cycles: 0 +stall_warp: 0 +wspawn: 0 +stalled: 0 +DEBUG ../core.cpp:386: Core step stepping warp 0[4] +DEBUG ../core.cpp:683: in step pc=0x800008b4 +help: in PC: 800008b4 +CUrrent CODE: 100513 +DEBUG ../core.cpp:703: Fetched at 0x800008b4 +DEBUG ../core.cpp:704: 0x800008b4: i_type; +DEBUG ../instruction.cpp:350: Begin instruction execute. +DEBUG ../instruction.cpp:2117: End instruction execute. +DEBUG ../core.cpp:717: Register state: + %r 0: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r 1: 8000004c 8000004c 8000004c 8000004c 00000000 00000000 00000000 00000000 (0) + %r 2: 6fffeff0 6fffebf4 6fffe7f8 6fffe3fc 00000000 00000000 00000000 00000000 (0) + %r 3: 80001808 80001808 80001808 80001808 00000000 00000000 00000000 00000000 (0) + %r 4: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r 5: 80000a6c 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r 6: 0000000f 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r 7: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r 8: 6ffff000 6fffec04 6fffe808 6fffe40c 00000000 00000000 00000000 00000000 (0) + %r 9: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r10: 00000001 00000001 00000001 00000001 00000000 00000000 00000000 00000000 (0) + %r11: 80000924 00000400 00000800 00000c00 00000000 00000000 00000000 00000000 (0) + %r12: 00000000 00000004 00000008 0000000c 00000000 00000000 00000000 00000000 (0) + %r13: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r14: 00000001 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r15: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r16: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r17: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r18: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r19: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r20: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r21: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r22: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r23: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r24: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r25: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r26: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r27: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r28: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r29: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r30: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r31: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) +DEBUG ../core.cpp:726: Thread mask: + 1 1 1 1 0 0 0 0 + + +DEBUG ../core.cpp:388: Now 4 active threads in 0 +********************************** Fetch ********************************* +valid: 1 +PC: 800008b4 +wid: 0 +rd: 10 rs1: 0 rs2: -1 +is_lw: 0 +is_sw: 0 +fetch_stall_cycles: 0 +mem_stall_cycles: 0 +stall_warp: 0 +wspawn: 0 +stalled: 0 + + + +------------------------------------------------------ +CYCLE: 409 +Stalled Warps: +0 0 0 0 0 0 0 0 + +********************************** Writeback ********************************* +valid: 0 +PC: 0 +wid: 0 +rd: -1 rs1: -1 rs2: -1 +is_lw: 0 +is_sw: 0 +fetch_stall_cycles: 0 +mem_stall_cycles: 0 +stall_warp: 0 +wspawn: 0 +stalled: 0 +********************************** LSU ********************************* +valid: 0 +PC: 0 +wid: 0 +rd: -1 rs1: -1 rs2: -1 +is_lw: 0 +is_sw: 0 +fetch_stall_cycles: 0 +mem_stall_cycles: 0 +stall_warp: 0 +wspawn: 0 +stalled: 0 +********************************** execute_unit ********************************* +valid: 0 +PC: 0 +wid: 0 +rd: -1 rs1: -1 rs2: -1 +is_lw: 0 +is_sw: 0 +fetch_stall_cycles: 0 +mem_stall_cycles: 0 +stall_warp: 0 +wspawn: 0 +stalled: 0 +********************************** scheduler ********************************* +valid: 1 +PC: 800008b0 +wid: 0 +rd: 8 rs1: 2 rs2: -1 +is_lw: 0 +is_sw: 0 +fetch_stall_cycles: 0 +mem_stall_cycles: 0 +stall_warp: 0 +wspawn: 0 +stalled: 0 +********************************** Decode ********************************* +valid: 1 +PC: 800008b4 +wid: 0 +rd: 10 rs1: 0 rs2: -1 +is_lw: 0 +is_sw: 0 +fetch_stall_cycles: 0 +mem_stall_cycles: 0 +stall_warp: 0 +wspawn: 0 +stalled: 0 +DEBUG ../core.cpp:386: Core step stepping warp 0[4] +DEBUG ../core.cpp:683: in step pc=0x800008b8 +help: in PC: 800008b8 +CUrrent CODE: f41ff0ef +DEBUG ../core.cpp:703: Fetched at 0x800008b8 +DEBUG ../core.cpp:704: 0x800008b8: jal; +DEBUG ../instruction.cpp:350: Begin instruction execute. +DEBUG ../instruction.cpp:2117: End instruction execute. +Next PC: 800007f8 +DEBUG ../core.cpp:717: Register state: + %r 0: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r 1: 800008bc 800008bc 800008bc 800008bc 00000000 00000000 00000000 00000000 (0) + %r 2: 6fffeff0 6fffebf4 6fffe7f8 6fffe3fc 00000000 00000000 00000000 00000000 (0) + %r 3: 80001808 80001808 80001808 80001808 00000000 00000000 00000000 00000000 (0) + %r 4: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r 5: 80000a6c 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r 6: 0000000f 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r 7: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r 8: 6ffff000 6fffec04 6fffe808 6fffe40c 00000000 00000000 00000000 00000000 (0) + %r 9: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r10: 00000001 00000001 00000001 00000001 00000000 00000000 00000000 00000000 (0) + %r11: 80000924 00000400 00000800 00000c00 00000000 00000000 00000000 00000000 (0) + %r12: 00000000 00000004 00000008 0000000c 00000000 00000000 00000000 00000000 (0) + %r13: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r14: 00000001 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r15: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r16: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r17: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r18: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r19: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r20: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r21: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r22: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r23: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r24: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r25: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r26: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r27: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r28: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r29: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r30: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r31: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) +DEBUG ../core.cpp:726: Thread mask: + 1 1 1 1 0 0 0 0 + + +DEBUG ../core.cpp:388: Now 4 active threads in 0 +********************************** Fetch ********************************* +valid: 1 +PC: 800008b8 +wid: 0 +rd: 1 rs1: -1 rs2: -1 +is_lw: 0 +is_sw: 0 +fetch_stall_cycles: 0 +mem_stall_cycles: 0 +stall_warp: 1 +wspawn: 0 +stalled: 0 + + + +------------------------------------------------------ +CYCLE: 410 +Stalled Warps: +1 0 0 0 0 0 0 0 + +********************************** Writeback ********************************* +valid: 0 +PC: 0 +wid: 1 +rd: -1 rs1: -1 rs2: -1 +is_lw: 0 +is_sw: 0 +fetch_stall_cycles: 0 +mem_stall_cycles: 0 +stall_warp: 0 +wspawn: 0 +stalled: 0 +********************************** LSU ********************************* +valid: 0 +PC: 0 +wid: 0 +rd: -1 rs1: -1 rs2: -1 +is_lw: 0 +is_sw: 0 +fetch_stall_cycles: 0 +mem_stall_cycles: 0 +stall_warp: 0 +wspawn: 0 +stalled: 0 +********************************** execute_unit ********************************* +valid: 1 +PC: 800008b0 +wid: 0 +rd: 8 rs1: 2 rs2: -1 +is_lw: 0 +is_sw: 0 +fetch_stall_cycles: 0 +mem_stall_cycles: 0 +stall_warp: 0 +wspawn: 0 +stalled: 0 +********************************** scheduler ********************************* +valid: 1 +PC: 800008b4 +wid: 0 +rd: 10 rs1: 0 rs2: -1 +is_lw: 0 +is_sw: 0 +fetch_stall_cycles: 0 +mem_stall_cycles: 0 +stall_warp: 0 +wspawn: 0 +stalled: 0 +********************************** Decode ********************************* +valid: 1 +PC: 800008b8 +wid: 0 +rd: 1 rs1: -1 rs2: -1 +is_lw: 0 +is_sw: 0 +fetch_stall_cycles: 0 +mem_stall_cycles: 0 +stall_warp: 1 +wspawn: 0 +stalled: 0 +********************************** Fetch ********************************* +valid: 0 +PC: 0 +wid: 1 +rd: -1 rs1: -1 rs2: -1 +is_lw: 0 +is_sw: 0 +fetch_stall_cycles: 0 +mem_stall_cycles: 0 +stall_warp: 0 +wspawn: 0 +stalled: 0 + + + +------------------------------------------------------ +CYCLE: 411 +Stalled Warps: +1 0 0 0 0 0 0 0 + +********************************** Writeback ********************************* +valid: 1 +PC: 800008b0 +wid: 0 +rd: 8 rs1: 2 rs2: -1 +is_lw: 0 +is_sw: 0 +fetch_stall_cycles: 0 +mem_stall_cycles: 0 +stall_warp: 0 +wspawn: 0 +stalled: 0 +********************************** LSU ********************************* +valid: 0 +PC: 0 +wid: 0 +rd: -1 rs1: -1 rs2: -1 +is_lw: 0 +is_sw: 0 +fetch_stall_cycles: 0 +mem_stall_cycles: 0 +stall_warp: 0 +wspawn: 0 +stalled: 0 +********************************** execute_unit ********************************* +valid: 1 +PC: 800008b4 +wid: 0 +rd: 10 rs1: 0 rs2: -1 +is_lw: 0 +is_sw: 0 +fetch_stall_cycles: 0 +mem_stall_cycles: 0 +stall_warp: 0 +wspawn: 0 +stalled: 0 +********************************** scheduler ********************************* +valid: 1 +PC: 800008b8 +wid: 0 +rd: 1 rs1: -1 rs2: -1 +is_lw: 0 +is_sw: 0 +fetch_stall_cycles: 0 +mem_stall_cycles: 0 +stall_warp: 1 +wspawn: 0 +stalled: 0 +********************************** Decode ********************************* +valid: 0 +PC: 0 +wid: 1 +rd: -1 rs1: -1 rs2: -1 +is_lw: 0 +is_sw: 0 +fetch_stall_cycles: 0 +mem_stall_cycles: 0 +stall_warp: 0 +wspawn: 0 +stalled: 0 +********************************** Fetch ********************************* +valid: 0 +PC: 0 +wid: 2 +rd: -1 rs1: -1 rs2: -1 +is_lw: 0 +is_sw: 0 +fetch_stall_cycles: 0 +mem_stall_cycles: 0 +stall_warp: 0 +wspawn: 0 +stalled: 0 + + + +------------------------------------------------------ +CYCLE: 412 +Stalled Warps: +1 0 0 0 0 0 0 0 + +********************************** Writeback ********************************* +valid: 1 +PC: 800008b4 +wid: 0 +rd: 10 rs1: 0 rs2: -1 +is_lw: 0 +is_sw: 0 +fetch_stall_cycles: 0 +mem_stall_cycles: 0 +stall_warp: 0 +wspawn: 0 +stalled: 0 +********************************** LSU ********************************* +valid: 0 +PC: 0 +wid: 0 +rd: -1 rs1: -1 rs2: -1 +is_lw: 0 +is_sw: 0 +fetch_stall_cycles: 0 +mem_stall_cycles: 0 +stall_warp: 0 +wspawn: 0 +stalled: 0 +********************************** execute_unit ********************************* +valid: 1 +PC: 800008b8 +wid: 0 +rd: 1 rs1: -1 rs2: -1 +is_lw: 0 +is_sw: 0 +fetch_stall_cycles: 0 +mem_stall_cycles: 0 +stall_warp: 1 +wspawn: 0 +stalled: 0 +********************************** scheduler ********************************* +valid: 0 +PC: 0 +wid: 1 +rd: -1 rs1: -1 rs2: -1 +is_lw: 0 +is_sw: 0 +fetch_stall_cycles: 0 +mem_stall_cycles: 0 +stall_warp: 0 +wspawn: 0 +stalled: 0 +********************************** Decode ********************************* +valid: 0 +PC: 0 +wid: 2 +rd: -1 rs1: -1 rs2: -1 +is_lw: 0 +is_sw: 0 +fetch_stall_cycles: 0 +mem_stall_cycles: 0 +stall_warp: 0 +wspawn: 0 +stalled: 0 +********************************** Fetch ********************************* +valid: 0 +PC: 0 +wid: 3 +rd: -1 rs1: -1 rs2: -1 +is_lw: 0 +is_sw: 0 +fetch_stall_cycles: 0 +mem_stall_cycles: 0 +stall_warp: 0 +wspawn: 0 +stalled: 0 + + + +------------------------------------------------------ +CYCLE: 413 +Stalled Warps: +1 0 0 0 0 0 0 0 + +********************************** Writeback ********************************* +valid: 1 +PC: 800008b8 +wid: 0 +rd: 1 rs1: -1 rs2: -1 +is_lw: 0 +is_sw: 0 +fetch_stall_cycles: 0 +mem_stall_cycles: 0 +stall_warp: 1 +wspawn: 0 +stalled: 0 +********************************** LSU ********************************* +valid: 0 +PC: 0 +wid: 0 +rd: -1 rs1: -1 rs2: -1 +is_lw: 0 +is_sw: 0 +fetch_stall_cycles: 0 +mem_stall_cycles: 0 +stall_warp: 0 +wspawn: 0 +stalled: 0 +********************************** execute_unit ********************************* +valid: 0 +PC: 0 +wid: 1 +rd: -1 rs1: -1 rs2: -1 +is_lw: 0 +is_sw: 0 +fetch_stall_cycles: 0 +mem_stall_cycles: 0 +stall_warp: 0 +wspawn: 0 +stalled: 0 +********************************** scheduler ********************************* +valid: 0 +PC: 0 +wid: 2 +rd: -1 rs1: -1 rs2: -1 +is_lw: 0 +is_sw: 0 +fetch_stall_cycles: 0 +mem_stall_cycles: 0 +stall_warp: 0 +wspawn: 0 +stalled: 0 +********************************** Decode ********************************* +valid: 0 +PC: 0 +wid: 3 +rd: -1 rs1: -1 rs2: -1 +is_lw: 0 +is_sw: 0 +fetch_stall_cycles: 0 +mem_stall_cycles: 0 +stall_warp: 0 +wspawn: 0 +stalled: 0 +********************************** Fetch ********************************* +valid: 0 +PC: 0 +wid: 4 +rd: -1 rs1: -1 rs2: -1 +is_lw: 0 +is_sw: 0 +fetch_stall_cycles: 0 +mem_stall_cycles: 0 +stall_warp: 0 +wspawn: 0 +stalled: 0 + + + +------------------------------------------------------ +CYCLE: 414 +Stalled Warps: +1 0 0 0 0 0 0 0 + +********************************** Writeback ********************************* +valid: 0 +PC: 0 +wid: 5 +rd: -1 rs1: -1 rs2: -1 +is_lw: 0 +is_sw: 0 +fetch_stall_cycles: 0 +mem_stall_cycles: 0 +stall_warp: 0 +wspawn: 0 +stalled: 0 +********************************** LSU ********************************* +valid: 0 +PC: 0 +wid: 0 +rd: -1 rs1: -1 rs2: -1 +is_lw: 0 +is_sw: 0 +fetch_stall_cycles: 0 +mem_stall_cycles: 0 +stall_warp: 0 +wspawn: 0 +stalled: 0 +********************************** execute_unit ********************************* +valid: 0 +PC: 0 +wid: 2 +rd: -1 rs1: -1 rs2: -1 +is_lw: 0 +is_sw: 0 +fetch_stall_cycles: 0 +mem_stall_cycles: 0 +stall_warp: 0 +wspawn: 0 +stalled: 0 +********************************** scheduler ********************************* +valid: 0 +PC: 0 +wid: 3 +rd: -1 rs1: -1 rs2: -1 +is_lw: 0 +is_sw: 0 +fetch_stall_cycles: 0 +mem_stall_cycles: 0 +stall_warp: 0 +wspawn: 0 +stalled: 0 +********************************** Decode ********************************* +valid: 0 +PC: 0 +wid: 4 +rd: -1 rs1: -1 rs2: -1 +is_lw: 0 +is_sw: 0 +fetch_stall_cycles: 0 +mem_stall_cycles: 0 +stall_warp: 0 +wspawn: 0 +stalled: 0 +********************************** Fetch ********************************* +valid: 0 +PC: 0 +wid: 5 +rd: -1 rs1: -1 rs2: -1 +is_lw: 0 +is_sw: 0 +fetch_stall_cycles: 0 +mem_stall_cycles: 0 +stall_warp: 0 +wspawn: 0 +stalled: 0 +Warp ID 0 is running + + + +------------------------------------------------------ +CYCLE: 415 +Stalled Warps: +0 0 0 0 0 0 0 0 + +********************************** Writeback ********************************* +valid: 0 +PC: 0 +wid: 0 +rd: -1 rs1: -1 rs2: -1 +is_lw: 0 +is_sw: 0 +fetch_stall_cycles: 0 +mem_stall_cycles: 0 +stall_warp: 0 +wspawn: 0 +stalled: 0 +********************************** LSU ********************************* +valid: 0 +PC: 0 +wid: 0 +rd: -1 rs1: -1 rs2: -1 +is_lw: 0 +is_sw: 0 +fetch_stall_cycles: 0 +mem_stall_cycles: 0 +stall_warp: 0 +wspawn: 0 +stalled: 0 +********************************** execute_unit ********************************* +valid: 0 +PC: 0 +wid: 3 +rd: -1 rs1: -1 rs2: -1 +is_lw: 0 +is_sw: 0 +fetch_stall_cycles: 0 +mem_stall_cycles: 0 +stall_warp: 0 +wspawn: 0 +stalled: 0 +********************************** scheduler ********************************* +valid: 0 +PC: 0 +wid: 4 +rd: -1 rs1: -1 rs2: -1 +is_lw: 0 +is_sw: 0 +fetch_stall_cycles: 0 +mem_stall_cycles: 0 +stall_warp: 0 +wspawn: 0 +stalled: 0 +********************************** Decode ********************************* +valid: 0 +PC: 0 +wid: 5 +rd: -1 rs1: -1 rs2: -1 +is_lw: 0 +is_sw: 0 +fetch_stall_cycles: 0 +mem_stall_cycles: 0 +stall_warp: 0 +wspawn: 0 +stalled: 0 +DEBUG ../core.cpp:386: Core step stepping warp 0[4] +DEBUG ../core.cpp:683: in step pc=0x800007f8 +help: in PC: 800007f8 +CUrrent CODE: 5006b +DEBUG ../core.cpp:703: Fetched at 0x800007f8 +DEBUG ../core.cpp:704: 0x800007f8: gpgpu; +DEBUG ../instruction.cpp:350: Begin instruction execute. +DEBUG ../instruction.cpp:2117: End instruction execute. +DEBUG ../core.cpp:717: Register state: + %r 0: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r 1: 800008bc 800008bc 800008bc 800008bc 00000000 00000000 00000000 00000000 (0) + %r 2: 6fffeff0 6fffebf4 6fffe7f8 6fffe3fc 00000000 00000000 00000000 00000000 (0) + %r 3: 80001808 80001808 80001808 80001808 00000000 00000000 00000000 00000000 (0) + %r 4: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r 5: 80000a6c 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r 6: 0000000f 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r 7: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r 8: 6ffff000 6fffec04 6fffe808 6fffe40c 00000000 00000000 00000000 00000000 (0) + %r 9: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r10: 00000001 00000001 00000001 00000001 00000000 00000000 00000000 00000000 (0) + %r11: 80000924 00000400 00000800 00000c00 00000000 00000000 00000000 00000000 (0) + %r12: 00000000 00000004 00000008 0000000c 00000000 00000000 00000000 00000000 (0) + %r13: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r14: 00000001 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r15: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r16: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r17: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r18: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r19: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r20: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r21: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r22: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r23: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r24: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r25: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r26: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r27: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r28: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r29: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r30: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r31: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) +DEBUG ../core.cpp:726: Thread mask: + 1 0 0 0 0 0 0 0 + + +DEBUG ../core.cpp:388: Now 1 active threads in 0 +********************************** Fetch ********************************* +valid: 1 +PC: 800007f8 +wid: 0 +rd: 0 rs1: 10 rs2: 0 +is_lw: 0 +is_sw: 0 +fetch_stall_cycles: 3 +mem_stall_cycles: 0 +stall_warp: 1 +wspawn: 0 +stalled: 0 + + + +------------------------------------------------------ +CYCLE: 416 +Stalled Warps: +1 0 0 0 0 0 0 0 + +********************************** Writeback ********************************* +valid: 0 +PC: 0 +wid: 1 +rd: -1 rs1: -1 rs2: -1 +is_lw: 0 +is_sw: 0 +fetch_stall_cycles: 0 +mem_stall_cycles: 0 +stall_warp: 0 +wspawn: 0 +stalled: 0 +********************************** LSU ********************************* +valid: 0 +PC: 0 +wid: 0 +rd: -1 rs1: -1 rs2: -1 +is_lw: 0 +is_sw: 0 +fetch_stall_cycles: 0 +mem_stall_cycles: 0 +stall_warp: 0 +wspawn: 0 +stalled: 0 +********************************** execute_unit ********************************* +valid: 0 +PC: 0 +wid: 4 +rd: -1 rs1: -1 rs2: -1 +is_lw: 0 +is_sw: 0 +fetch_stall_cycles: 0 +mem_stall_cycles: 0 +stall_warp: 0 +wspawn: 0 +stalled: 0 +********************************** scheduler ********************************* +valid: 0 +PC: 0 +wid: 5 +rd: -1 rs1: -1 rs2: -1 +is_lw: 0 +is_sw: 0 +fetch_stall_cycles: 0 +mem_stall_cycles: 0 +stall_warp: 0 +wspawn: 0 +stalled: 0 +********************************** Decode ********************************* +valid: 0 +PC: 0 +wid: 1 +rd: -1 rs1: -1 rs2: -1 +is_lw: 0 +is_sw: 0 +fetch_stall_cycles: 0 +mem_stall_cycles: 0 +stall_warp: 0 +wspawn: 0 +stalled: 0 +********************************** Fetch ********************************* +valid: 1 +PC: 800007f8 +wid: 0 +rd: 0 rs1: 10 rs2: 0 +is_lw: 0 +is_sw: 0 +fetch_stall_cycles: 2 +mem_stall_cycles: 0 +stall_warp: 1 +wspawn: 0 +stalled: 0 + + + +------------------------------------------------------ +CYCLE: 417 +Stalled Warps: +1 0 0 0 0 0 0 0 + +********************************** Writeback ********************************* +valid: 0 +PC: 0 +wid: 1 +rd: -1 rs1: -1 rs2: -1 +is_lw: 0 +is_sw: 0 +fetch_stall_cycles: 0 +mem_stall_cycles: 0 +stall_warp: 0 +wspawn: 0 +stalled: 0 +********************************** LSU ********************************* +valid: 0 +PC: 0 +wid: 0 +rd: -1 rs1: -1 rs2: -1 +is_lw: 0 +is_sw: 0 +fetch_stall_cycles: 0 +mem_stall_cycles: 0 +stall_warp: 0 +wspawn: 0 +stalled: 0 +********************************** execute_unit ********************************* +valid: 0 +PC: 0 +wid: 5 +rd: -1 rs1: -1 rs2: -1 +is_lw: 0 +is_sw: 0 +fetch_stall_cycles: 0 +mem_stall_cycles: 0 +stall_warp: 0 +wspawn: 0 +stalled: 0 +********************************** scheduler ********************************* +valid: 0 +PC: 0 +wid: 1 +rd: -1 rs1: -1 rs2: -1 +is_lw: 0 +is_sw: 0 +fetch_stall_cycles: 0 +mem_stall_cycles: 0 +stall_warp: 0 +wspawn: 0 +stalled: 0 +********************************** Decode ********************************* +valid: 0 +PC: 0 +wid: 1 +rd: -1 rs1: -1 rs2: -1 +is_lw: 0 +is_sw: 0 +fetch_stall_cycles: 0 +mem_stall_cycles: 0 +stall_warp: 0 +wspawn: 0 +stalled: 0 +********************************** Fetch ********************************* +valid: 1 +PC: 800007f8 +wid: 0 +rd: 0 rs1: 10 rs2: 0 +is_lw: 0 +is_sw: 0 +fetch_stall_cycles: 1 +mem_stall_cycles: 0 +stall_warp: 1 +wspawn: 0 +stalled: 0 + + + +------------------------------------------------------ +CYCLE: 418 +Stalled Warps: +1 0 0 0 0 0 0 0 + +********************************** Writeback ********************************* +valid: 0 +PC: 0 +wid: 1 +rd: -1 rs1: -1 rs2: -1 +is_lw: 0 +is_sw: 0 +fetch_stall_cycles: 0 +mem_stall_cycles: 0 +stall_warp: 0 +wspawn: 0 +stalled: 0 +********************************** LSU ********************************* +valid: 0 +PC: 0 +wid: 0 +rd: -1 rs1: -1 rs2: -1 +is_lw: 0 +is_sw: 0 +fetch_stall_cycles: 0 +mem_stall_cycles: 0 +stall_warp: 0 +wspawn: 0 +stalled: 0 +********************************** execute_unit ********************************* +valid: 0 +PC: 0 +wid: 1 +rd: -1 rs1: -1 rs2: -1 +is_lw: 0 +is_sw: 0 +fetch_stall_cycles: 0 +mem_stall_cycles: 0 +stall_warp: 0 +wspawn: 0 +stalled: 0 +********************************** scheduler ********************************* +valid: 0 +PC: 0 +wid: 1 +rd: -1 rs1: -1 rs2: -1 +is_lw: 0 +is_sw: 0 +fetch_stall_cycles: 0 +mem_stall_cycles: 0 +stall_warp: 0 +wspawn: 0 +stalled: 0 +********************************** Decode ********************************* +valid: 0 +PC: 0 +wid: 1 +rd: -1 rs1: -1 rs2: -1 +is_lw: 0 +is_sw: 0 +fetch_stall_cycles: 0 +mem_stall_cycles: 0 +stall_warp: 0 +wspawn: 0 +stalled: 0 +********************************** Fetch ********************************* +valid: 1 +PC: 800007f8 +wid: 0 +rd: 0 rs1: 10 rs2: 0 +is_lw: 0 +is_sw: 0 +fetch_stall_cycles: 0 +mem_stall_cycles: 0 +stall_warp: 1 +wspawn: 0 +stalled: 0 + + + +------------------------------------------------------ +CYCLE: 419 +Stalled Warps: +1 0 0 0 0 0 0 0 + +********************************** Writeback ********************************* +valid: 0 +PC: 0 +wid: 1 +rd: -1 rs1: -1 rs2: -1 +is_lw: 0 +is_sw: 0 +fetch_stall_cycles: 0 +mem_stall_cycles: 0 +stall_warp: 0 +wspawn: 0 +stalled: 0 +********************************** LSU ********************************* +valid: 0 +PC: 0 +wid: 0 +rd: -1 rs1: -1 rs2: -1 +is_lw: 0 +is_sw: 0 +fetch_stall_cycles: 0 +mem_stall_cycles: 0 +stall_warp: 0 +wspawn: 0 +stalled: 0 +********************************** execute_unit ********************************* +valid: 0 +PC: 0 +wid: 1 +rd: -1 rs1: -1 rs2: -1 +is_lw: 0 +is_sw: 0 +fetch_stall_cycles: 0 +mem_stall_cycles: 0 +stall_warp: 0 +wspawn: 0 +stalled: 0 +********************************** scheduler ********************************* +valid: 0 +PC: 0 +wid: 1 +rd: -1 rs1: -1 rs2: -1 +is_lw: 0 +is_sw: 0 +fetch_stall_cycles: 0 +mem_stall_cycles: 0 +stall_warp: 0 +wspawn: 0 +stalled: 0 +********************************** Decode ********************************* +valid: 1 +PC: 800007f8 +wid: 0 +rd: 0 rs1: 10 rs2: 0 +is_lw: 0 +is_sw: 0 +fetch_stall_cycles: 0 +mem_stall_cycles: 0 +stall_warp: 1 +wspawn: 0 +stalled: 0 +********************************** Fetch ********************************* +valid: 0 +PC: 0 +wid: 1 +rd: -1 rs1: -1 rs2: -1 +is_lw: 0 +is_sw: 0 +fetch_stall_cycles: 0 +mem_stall_cycles: 0 +stall_warp: 0 +wspawn: 0 +stalled: 0 + + + +------------------------------------------------------ +CYCLE: 420 +Stalled Warps: +1 0 0 0 0 0 0 0 + +********************************** Writeback ********************************* +valid: 0 +PC: 0 +wid: 2 +rd: -1 rs1: -1 rs2: -1 +is_lw: 0 +is_sw: 0 +fetch_stall_cycles: 0 +mem_stall_cycles: 0 +stall_warp: 0 +wspawn: 0 +stalled: 0 +********************************** LSU ********************************* +valid: 0 +PC: 0 +wid: 0 +rd: -1 rs1: -1 rs2: -1 +is_lw: 0 +is_sw: 0 +fetch_stall_cycles: 0 +mem_stall_cycles: 0 +stall_warp: 0 +wspawn: 0 +stalled: 0 +********************************** execute_unit ********************************* +valid: 0 +PC: 0 +wid: 1 +rd: -1 rs1: -1 rs2: -1 +is_lw: 0 +is_sw: 0 +fetch_stall_cycles: 0 +mem_stall_cycles: 0 +stall_warp: 0 +wspawn: 0 +stalled: 0 +********************************** scheduler ********************************* +valid: 1 +PC: 800007f8 +wid: 0 +rd: 0 rs1: 10 rs2: 0 +is_lw: 0 +is_sw: 0 +fetch_stall_cycles: 0 +mem_stall_cycles: 0 +stall_warp: 1 +wspawn: 0 +stalled: 0 +********************************** Decode ********************************* +valid: 0 +PC: 0 +wid: 1 +rd: -1 rs1: -1 rs2: -1 +is_lw: 0 +is_sw: 0 +fetch_stall_cycles: 0 +mem_stall_cycles: 0 +stall_warp: 0 +wspawn: 0 +stalled: 0 +********************************** Fetch ********************************* +valid: 0 +PC: 0 +wid: 2 +rd: -1 rs1: -1 rs2: -1 +is_lw: 0 +is_sw: 0 +fetch_stall_cycles: 0 +mem_stall_cycles: 0 +stall_warp: 0 +wspawn: 0 +stalled: 0 + + + +------------------------------------------------------ +CYCLE: 421 +Stalled Warps: +1 0 0 0 0 0 0 0 + +********************************** Writeback ********************************* +valid: 0 +PC: 0 +wid: 3 +rd: -1 rs1: -1 rs2: -1 +is_lw: 0 +is_sw: 0 +fetch_stall_cycles: 0 +mem_stall_cycles: 0 +stall_warp: 0 +wspawn: 0 +stalled: 0 +********************************** LSU ********************************* +valid: 0 +PC: 0 +wid: 0 +rd: -1 rs1: -1 rs2: -1 +is_lw: 0 +is_sw: 0 +fetch_stall_cycles: 0 +mem_stall_cycles: 0 +stall_warp: 0 +wspawn: 0 +stalled: 0 +********************************** execute_unit ********************************* +valid: 1 +PC: 800007f8 +wid: 0 +rd: 0 rs1: 10 rs2: 0 +is_lw: 0 +is_sw: 0 +fetch_stall_cycles: 0 +mem_stall_cycles: 0 +stall_warp: 1 +wspawn: 0 +stalled: 0 +********************************** scheduler ********************************* +valid: 0 +PC: 0 +wid: 1 +rd: -1 rs1: -1 rs2: -1 +is_lw: 0 +is_sw: 0 +fetch_stall_cycles: 0 +mem_stall_cycles: 0 +stall_warp: 0 +wspawn: 0 +stalled: 0 +********************************** Decode ********************************* +valid: 0 +PC: 0 +wid: 2 +rd: -1 rs1: -1 rs2: -1 +is_lw: 0 +is_sw: 0 +fetch_stall_cycles: 0 +mem_stall_cycles: 0 +stall_warp: 0 +wspawn: 0 +stalled: 0 +********************************** Fetch ********************************* +valid: 0 +PC: 0 +wid: 3 +rd: -1 rs1: -1 rs2: -1 +is_lw: 0 +is_sw: 0 +fetch_stall_cycles: 0 +mem_stall_cycles: 0 +stall_warp: 0 +wspawn: 0 +stalled: 0 + + + +------------------------------------------------------ +CYCLE: 422 +Stalled Warps: +1 0 0 0 0 0 0 0 + +********************************** Writeback ********************************* +valid: 1 +PC: 800007f8 +wid: 0 +rd: 0 rs1: 10 rs2: 0 +is_lw: 0 +is_sw: 0 +fetch_stall_cycles: 0 +mem_stall_cycles: 0 +stall_warp: 1 +wspawn: 0 +stalled: 0 +********************************** LSU ********************************* +valid: 0 +PC: 0 +wid: 0 +rd: -1 rs1: -1 rs2: -1 +is_lw: 0 +is_sw: 0 +fetch_stall_cycles: 0 +mem_stall_cycles: 0 +stall_warp: 0 +wspawn: 0 +stalled: 0 +********************************** execute_unit ********************************* +valid: 0 +PC: 0 +wid: 1 +rd: -1 rs1: -1 rs2: -1 +is_lw: 0 +is_sw: 0 +fetch_stall_cycles: 0 +mem_stall_cycles: 0 +stall_warp: 0 +wspawn: 0 +stalled: 0 +********************************** scheduler ********************************* +valid: 0 +PC: 0 +wid: 2 +rd: -1 rs1: -1 rs2: -1 +is_lw: 0 +is_sw: 0 +fetch_stall_cycles: 0 +mem_stall_cycles: 0 +stall_warp: 0 +wspawn: 0 +stalled: 0 +********************************** Decode ********************************* +valid: 0 +PC: 0 +wid: 3 +rd: -1 rs1: -1 rs2: -1 +is_lw: 0 +is_sw: 0 +fetch_stall_cycles: 0 +mem_stall_cycles: 0 +stall_warp: 0 +wspawn: 0 +stalled: 0 +********************************** Fetch ********************************* +valid: 0 +PC: 0 +wid: 4 +rd: -1 rs1: -1 rs2: -1 +is_lw: 0 +is_sw: 0 +fetch_stall_cycles: 0 +mem_stall_cycles: 0 +stall_warp: 0 +wspawn: 0 +stalled: 0 + + + +------------------------------------------------------ +CYCLE: 423 +Stalled Warps: +1 0 0 0 0 0 0 0 + +********************************** Writeback ********************************* +valid: 0 +PC: 0 +wid: 5 +rd: -1 rs1: -1 rs2: -1 +is_lw: 0 +is_sw: 0 +fetch_stall_cycles: 0 +mem_stall_cycles: 0 +stall_warp: 0 +wspawn: 0 +stalled: 0 +********************************** LSU ********************************* +valid: 0 +PC: 0 +wid: 0 +rd: -1 rs1: -1 rs2: -1 +is_lw: 0 +is_sw: 0 +fetch_stall_cycles: 0 +mem_stall_cycles: 0 +stall_warp: 0 +wspawn: 0 +stalled: 0 +********************************** execute_unit ********************************* +valid: 0 +PC: 0 +wid: 2 +rd: -1 rs1: -1 rs2: -1 +is_lw: 0 +is_sw: 0 +fetch_stall_cycles: 0 +mem_stall_cycles: 0 +stall_warp: 0 +wspawn: 0 +stalled: 0 +********************************** scheduler ********************************* +valid: 0 +PC: 0 +wid: 3 +rd: -1 rs1: -1 rs2: -1 +is_lw: 0 +is_sw: 0 +fetch_stall_cycles: 0 +mem_stall_cycles: 0 +stall_warp: 0 +wspawn: 0 +stalled: 0 +********************************** Decode ********************************* +valid: 0 +PC: 0 +wid: 4 +rd: -1 rs1: -1 rs2: -1 +is_lw: 0 +is_sw: 0 +fetch_stall_cycles: 0 +mem_stall_cycles: 0 +stall_warp: 0 +wspawn: 0 +stalled: 0 +********************************** Fetch ********************************* +valid: 0 +PC: 0 +wid: 5 +rd: -1 rs1: -1 rs2: -1 +is_lw: 0 +is_sw: 0 +fetch_stall_cycles: 0 +mem_stall_cycles: 0 +stall_warp: 0 +wspawn: 0 +stalled: 0 +Warp ID 0 is running + + + +------------------------------------------------------ +CYCLE: 424 +Stalled Warps: +0 0 0 0 0 0 0 0 + +********************************** Writeback ********************************* +valid: 0 +PC: 0 +wid: 0 +rd: -1 rs1: -1 rs2: -1 +is_lw: 0 +is_sw: 0 +fetch_stall_cycles: 0 +mem_stall_cycles: 0 +stall_warp: 0 +wspawn: 0 +stalled: 0 +********************************** LSU ********************************* +valid: 0 +PC: 0 +wid: 0 +rd: -1 rs1: -1 rs2: -1 +is_lw: 0 +is_sw: 0 +fetch_stall_cycles: 0 +mem_stall_cycles: 0 +stall_warp: 0 +wspawn: 0 +stalled: 0 +********************************** execute_unit ********************************* +valid: 0 +PC: 0 +wid: 3 +rd: -1 rs1: -1 rs2: -1 +is_lw: 0 +is_sw: 0 +fetch_stall_cycles: 0 +mem_stall_cycles: 0 +stall_warp: 0 +wspawn: 0 +stalled: 0 +********************************** scheduler ********************************* +valid: 0 +PC: 0 +wid: 4 +rd: -1 rs1: -1 rs2: -1 +is_lw: 0 +is_sw: 0 +fetch_stall_cycles: 0 +mem_stall_cycles: 0 +stall_warp: 0 +wspawn: 0 +stalled: 0 +********************************** Decode ********************************* +valid: 0 +PC: 0 +wid: 5 +rd: -1 rs1: -1 rs2: -1 +is_lw: 0 +is_sw: 0 +fetch_stall_cycles: 0 +mem_stall_cycles: 0 +stall_warp: 0 +wspawn: 0 +stalled: 0 +DEBUG ../core.cpp:386: Core step stepping warp 0[1] +DEBUG ../core.cpp:683: in step pc=0x800007fc +help: in PC: 800007fc +CUrrent CODE: 8067 +DEBUG ../core.cpp:703: Fetched at 0x800007fc +DEBUG ../core.cpp:704: 0x800007fc: jalr; +DEBUG ../instruction.cpp:350: Begin instruction execute. +JALR_INST +DEBUG ../instruction.cpp:2117: End instruction execute. +Next PC: 800008bc +DEBUG ../core.cpp:717: Register state: + %r 0: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r 1: 800008bc 800008bc 800008bc 800008bc 00000000 00000000 00000000 00000000 (0) + %r 2: 6fffeff0 6fffebf4 6fffe7f8 6fffe3fc 00000000 00000000 00000000 00000000 (0) + %r 3: 80001808 80001808 80001808 80001808 00000000 00000000 00000000 00000000 (0) + %r 4: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r 5: 80000a6c 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r 6: 0000000f 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r 7: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r 8: 6ffff000 6fffec04 6fffe808 6fffe40c 00000000 00000000 00000000 00000000 (0) + %r 9: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r10: 00000001 00000001 00000001 00000001 00000000 00000000 00000000 00000000 (0) + %r11: 80000924 00000400 00000800 00000c00 00000000 00000000 00000000 00000000 (0) + %r12: 00000000 00000004 00000008 0000000c 00000000 00000000 00000000 00000000 (0) + %r13: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r14: 00000001 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r15: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r16: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r17: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r18: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r19: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r20: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r21: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r22: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r23: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r24: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r25: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r26: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r27: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r28: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r29: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r30: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r31: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) +DEBUG ../core.cpp:726: Thread mask: + 1 0 0 0 0 0 0 0 + + +DEBUG ../core.cpp:388: Now 1 active threads in 0 +********************************** Fetch ********************************* +valid: 1 +PC: 800007fc +wid: 0 +rd: 0 rs1: 1 rs2: -1 +is_lw: 0 +is_sw: 0 +fetch_stall_cycles: 0 +mem_stall_cycles: 0 +stall_warp: 1 +wspawn: 0 +stalled: 0 + + + +------------------------------------------------------ +CYCLE: 425 +Stalled Warps: +1 0 0 0 0 0 0 0 + +********************************** Writeback ********************************* +valid: 0 +PC: 0 +wid: 1 +rd: -1 rs1: -1 rs2: -1 +is_lw: 0 +is_sw: 0 +fetch_stall_cycles: 0 +mem_stall_cycles: 0 +stall_warp: 0 +wspawn: 0 +stalled: 0 +********************************** LSU ********************************* +valid: 0 +PC: 0 +wid: 0 +rd: -1 rs1: -1 rs2: -1 +is_lw: 0 +is_sw: 0 +fetch_stall_cycles: 0 +mem_stall_cycles: 0 +stall_warp: 0 +wspawn: 0 +stalled: 0 +********************************** execute_unit ********************************* +valid: 0 +PC: 0 +wid: 4 +rd: -1 rs1: -1 rs2: -1 +is_lw: 0 +is_sw: 0 +fetch_stall_cycles: 0 +mem_stall_cycles: 0 +stall_warp: 0 +wspawn: 0 +stalled: 0 +********************************** scheduler ********************************* +valid: 0 +PC: 0 +wid: 5 +rd: -1 rs1: -1 rs2: -1 +is_lw: 0 +is_sw: 0 +fetch_stall_cycles: 0 +mem_stall_cycles: 0 +stall_warp: 0 +wspawn: 0 +stalled: 0 +********************************** Decode ********************************* +valid: 1 +PC: 800007fc +wid: 0 +rd: 0 rs1: 1 rs2: -1 +is_lw: 0 +is_sw: 0 +fetch_stall_cycles: 0 +mem_stall_cycles: 0 +stall_warp: 1 +wspawn: 0 +stalled: 0 +********************************** Fetch ********************************* +valid: 0 +PC: 0 +wid: 1 +rd: -1 rs1: -1 rs2: -1 +is_lw: 0 +is_sw: 0 +fetch_stall_cycles: 0 +mem_stall_cycles: 0 +stall_warp: 0 +wspawn: 0 +stalled: 0 + + + +------------------------------------------------------ +CYCLE: 426 +Stalled Warps: +1 0 0 0 0 0 0 0 + +********************************** Writeback ********************************* +valid: 0 +PC: 0 +wid: 2 +rd: -1 rs1: -1 rs2: -1 +is_lw: 0 +is_sw: 0 +fetch_stall_cycles: 0 +mem_stall_cycles: 0 +stall_warp: 0 +wspawn: 0 +stalled: 0 +********************************** LSU ********************************* +valid: 0 +PC: 0 +wid: 0 +rd: -1 rs1: -1 rs2: -1 +is_lw: 0 +is_sw: 0 +fetch_stall_cycles: 0 +mem_stall_cycles: 0 +stall_warp: 0 +wspawn: 0 +stalled: 0 +********************************** execute_unit ********************************* +valid: 0 +PC: 0 +wid: 5 +rd: -1 rs1: -1 rs2: -1 +is_lw: 0 +is_sw: 0 +fetch_stall_cycles: 0 +mem_stall_cycles: 0 +stall_warp: 0 +wspawn: 0 +stalled: 0 +********************************** scheduler ********************************* +valid: 1 +PC: 800007fc +wid: 0 +rd: 0 rs1: 1 rs2: -1 +is_lw: 0 +is_sw: 0 +fetch_stall_cycles: 0 +mem_stall_cycles: 0 +stall_warp: 1 +wspawn: 0 +stalled: 0 +********************************** Decode ********************************* +valid: 0 +PC: 0 +wid: 1 +rd: -1 rs1: -1 rs2: -1 +is_lw: 0 +is_sw: 0 +fetch_stall_cycles: 0 +mem_stall_cycles: 0 +stall_warp: 0 +wspawn: 0 +stalled: 0 +********************************** Fetch ********************************* +valid: 0 +PC: 0 +wid: 2 +rd: -1 rs1: -1 rs2: -1 +is_lw: 0 +is_sw: 0 +fetch_stall_cycles: 0 +mem_stall_cycles: 0 +stall_warp: 0 +wspawn: 0 +stalled: 0 + + + +------------------------------------------------------ +CYCLE: 427 +Stalled Warps: +1 0 0 0 0 0 0 0 + +********************************** Writeback ********************************* +valid: 0 +PC: 0 +wid: 3 +rd: -1 rs1: -1 rs2: -1 +is_lw: 0 +is_sw: 0 +fetch_stall_cycles: 0 +mem_stall_cycles: 0 +stall_warp: 0 +wspawn: 0 +stalled: 0 +********************************** LSU ********************************* +valid: 0 +PC: 0 +wid: 0 +rd: -1 rs1: -1 rs2: -1 +is_lw: 0 +is_sw: 0 +fetch_stall_cycles: 0 +mem_stall_cycles: 0 +stall_warp: 0 +wspawn: 0 +stalled: 0 +********************************** execute_unit ********************************* +valid: 1 +PC: 800007fc +wid: 0 +rd: 0 rs1: 1 rs2: -1 +is_lw: 0 +is_sw: 0 +fetch_stall_cycles: 0 +mem_stall_cycles: 0 +stall_warp: 1 +wspawn: 0 +stalled: 0 +********************************** scheduler ********************************* +valid: 0 +PC: 0 +wid: 1 +rd: -1 rs1: -1 rs2: -1 +is_lw: 0 +is_sw: 0 +fetch_stall_cycles: 0 +mem_stall_cycles: 0 +stall_warp: 0 +wspawn: 0 +stalled: 0 +********************************** Decode ********************************* +valid: 0 +PC: 0 +wid: 2 +rd: -1 rs1: -1 rs2: -1 +is_lw: 0 +is_sw: 0 +fetch_stall_cycles: 0 +mem_stall_cycles: 0 +stall_warp: 0 +wspawn: 0 +stalled: 0 +********************************** Fetch ********************************* +valid: 0 +PC: 0 +wid: 3 +rd: -1 rs1: -1 rs2: -1 +is_lw: 0 +is_sw: 0 +fetch_stall_cycles: 0 +mem_stall_cycles: 0 +stall_warp: 0 +wspawn: 0 +stalled: 0 + + + +------------------------------------------------------ +CYCLE: 428 +Stalled Warps: +1 0 0 0 0 0 0 0 + +********************************** Writeback ********************************* +valid: 1 +PC: 800007fc +wid: 0 +rd: 0 rs1: 1 rs2: -1 +is_lw: 0 +is_sw: 0 +fetch_stall_cycles: 0 +mem_stall_cycles: 0 +stall_warp: 1 +wspawn: 0 +stalled: 0 +********************************** LSU ********************************* +valid: 0 +PC: 0 +wid: 0 +rd: -1 rs1: -1 rs2: -1 +is_lw: 0 +is_sw: 0 +fetch_stall_cycles: 0 +mem_stall_cycles: 0 +stall_warp: 0 +wspawn: 0 +stalled: 0 +********************************** execute_unit ********************************* +valid: 0 +PC: 0 +wid: 1 +rd: -1 rs1: -1 rs2: -1 +is_lw: 0 +is_sw: 0 +fetch_stall_cycles: 0 +mem_stall_cycles: 0 +stall_warp: 0 +wspawn: 0 +stalled: 0 +********************************** scheduler ********************************* +valid: 0 +PC: 0 +wid: 2 +rd: -1 rs1: -1 rs2: -1 +is_lw: 0 +is_sw: 0 +fetch_stall_cycles: 0 +mem_stall_cycles: 0 +stall_warp: 0 +wspawn: 0 +stalled: 0 +********************************** Decode ********************************* +valid: 0 +PC: 0 +wid: 3 +rd: -1 rs1: -1 rs2: -1 +is_lw: 0 +is_sw: 0 +fetch_stall_cycles: 0 +mem_stall_cycles: 0 +stall_warp: 0 +wspawn: 0 +stalled: 0 +********************************** Fetch ********************************* +valid: 0 +PC: 0 +wid: 4 +rd: -1 rs1: -1 rs2: -1 +is_lw: 0 +is_sw: 0 +fetch_stall_cycles: 0 +mem_stall_cycles: 0 +stall_warp: 0 +wspawn: 0 +stalled: 0 + + + +------------------------------------------------------ +CYCLE: 429 +Stalled Warps: +1 0 0 0 0 0 0 0 + +********************************** Writeback ********************************* +valid: 0 +PC: 0 +wid: 5 +rd: -1 rs1: -1 rs2: -1 +is_lw: 0 +is_sw: 0 +fetch_stall_cycles: 0 +mem_stall_cycles: 0 +stall_warp: 0 +wspawn: 0 +stalled: 0 +********************************** LSU ********************************* +valid: 0 +PC: 0 +wid: 0 +rd: -1 rs1: -1 rs2: -1 +is_lw: 0 +is_sw: 0 +fetch_stall_cycles: 0 +mem_stall_cycles: 0 +stall_warp: 0 +wspawn: 0 +stalled: 0 +********************************** execute_unit ********************************* +valid: 0 +PC: 0 +wid: 2 +rd: -1 rs1: -1 rs2: -1 +is_lw: 0 +is_sw: 0 +fetch_stall_cycles: 0 +mem_stall_cycles: 0 +stall_warp: 0 +wspawn: 0 +stalled: 0 +********************************** scheduler ********************************* +valid: 0 +PC: 0 +wid: 3 +rd: -1 rs1: -1 rs2: -1 +is_lw: 0 +is_sw: 0 +fetch_stall_cycles: 0 +mem_stall_cycles: 0 +stall_warp: 0 +wspawn: 0 +stalled: 0 +********************************** Decode ********************************* +valid: 0 +PC: 0 +wid: 4 +rd: -1 rs1: -1 rs2: -1 +is_lw: 0 +is_sw: 0 +fetch_stall_cycles: 0 +mem_stall_cycles: 0 +stall_warp: 0 +wspawn: 0 +stalled: 0 +********************************** Fetch ********************************* +valid: 0 +PC: 0 +wid: 5 +rd: -1 rs1: -1 rs2: -1 +is_lw: 0 +is_sw: 0 +fetch_stall_cycles: 0 +mem_stall_cycles: 0 +stall_warp: 0 +wspawn: 0 +stalled: 0 +Warp ID 0 is running + + + +------------------------------------------------------ +CYCLE: 430 +Stalled Warps: +0 0 0 0 0 0 0 0 + +********************************** Writeback ********************************* +valid: 0 +PC: 0 +wid: 0 +rd: -1 rs1: -1 rs2: -1 +is_lw: 0 +is_sw: 0 +fetch_stall_cycles: 0 +mem_stall_cycles: 0 +stall_warp: 0 +wspawn: 0 +stalled: 0 +********************************** LSU ********************************* +valid: 0 +PC: 0 +wid: 0 +rd: -1 rs1: -1 rs2: -1 +is_lw: 0 +is_sw: 0 +fetch_stall_cycles: 0 +mem_stall_cycles: 0 +stall_warp: 0 +wspawn: 0 +stalled: 0 +********************************** execute_unit ********************************* +valid: 0 +PC: 0 +wid: 3 +rd: -1 rs1: -1 rs2: -1 +is_lw: 0 +is_sw: 0 +fetch_stall_cycles: 0 +mem_stall_cycles: 0 +stall_warp: 0 +wspawn: 0 +stalled: 0 +********************************** scheduler ********************************* +valid: 0 +PC: 0 +wid: 4 +rd: -1 rs1: -1 rs2: -1 +is_lw: 0 +is_sw: 0 +fetch_stall_cycles: 0 +mem_stall_cycles: 0 +stall_warp: 0 +wspawn: 0 +stalled: 0 +********************************** Decode ********************************* +valid: 0 +PC: 0 +wid: 5 +rd: -1 rs1: -1 rs2: -1 +is_lw: 0 +is_sw: 0 +fetch_stall_cycles: 0 +mem_stall_cycles: 0 +stall_warp: 0 +wspawn: 0 +stalled: 0 +DEBUG ../core.cpp:386: Core step stepping warp 0[1] +DEBUG ../core.cpp:683: in step pc=0x800008bc +help: in PC: 800008bc +CUrrent CODE: ff8ff0ef +DEBUG ../core.cpp:703: Fetched at 0x800008bc +DEBUG ../core.cpp:704: 0x800008bc: jal; +DEBUG ../instruction.cpp:350: Begin instruction execute. +DEBUG ../instruction.cpp:2117: End instruction execute. +Next PC: 800000b4 +DEBUG ../core.cpp:717: Register state: + %r 0: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r 1: 800008c0 800008bc 800008bc 800008bc 00000000 00000000 00000000 00000000 (0) + %r 2: 6fffeff0 6fffebf4 6fffe7f8 6fffe3fc 00000000 00000000 00000000 00000000 (0) + %r 3: 80001808 80001808 80001808 80001808 00000000 00000000 00000000 00000000 (0) + %r 4: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r 5: 80000a6c 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r 6: 0000000f 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r 7: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r 8: 6ffff000 6fffec04 6fffe808 6fffe40c 00000000 00000000 00000000 00000000 (0) + %r 9: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r10: 00000001 00000001 00000001 00000001 00000000 00000000 00000000 00000000 (0) + %r11: 80000924 00000400 00000800 00000c00 00000000 00000000 00000000 00000000 (0) + %r12: 00000000 00000004 00000008 0000000c 00000000 00000000 00000000 00000000 (0) + %r13: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r14: 00000001 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r15: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r16: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r17: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r18: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r19: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r20: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r21: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r22: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r23: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r24: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r25: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r26: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r27: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r28: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r29: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r30: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r31: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) +DEBUG ../core.cpp:726: Thread mask: + 1 0 0 0 0 0 0 0 + + +DEBUG ../core.cpp:388: Now 1 active threads in 0 +********************************** Fetch ********************************* +valid: 1 +PC: 800008bc +wid: 0 +rd: 1 rs1: -1 rs2: -1 +is_lw: 0 +is_sw: 0 +fetch_stall_cycles: 0 +mem_stall_cycles: 0 +stall_warp: 1 +wspawn: 0 +stalled: 0 + + + +------------------------------------------------------ +CYCLE: 431 +Stalled Warps: +1 0 0 0 0 0 0 0 + +********************************** Writeback ********************************* +valid: 0 +PC: 0 +wid: 1 +rd: -1 rs1: -1 rs2: -1 +is_lw: 0 +is_sw: 0 +fetch_stall_cycles: 0 +mem_stall_cycles: 0 +stall_warp: 0 +wspawn: 0 +stalled: 0 +********************************** LSU ********************************* +valid: 0 +PC: 0 +wid: 0 +rd: -1 rs1: -1 rs2: -1 +is_lw: 0 +is_sw: 0 +fetch_stall_cycles: 0 +mem_stall_cycles: 0 +stall_warp: 0 +wspawn: 0 +stalled: 0 +********************************** execute_unit ********************************* +valid: 0 +PC: 0 +wid: 4 +rd: -1 rs1: -1 rs2: -1 +is_lw: 0 +is_sw: 0 +fetch_stall_cycles: 0 +mem_stall_cycles: 0 +stall_warp: 0 +wspawn: 0 +stalled: 0 +********************************** scheduler ********************************* +valid: 0 +PC: 0 +wid: 5 +rd: -1 rs1: -1 rs2: -1 +is_lw: 0 +is_sw: 0 +fetch_stall_cycles: 0 +mem_stall_cycles: 0 +stall_warp: 0 +wspawn: 0 +stalled: 0 +********************************** Decode ********************************* +valid: 1 +PC: 800008bc +wid: 0 +rd: 1 rs1: -1 rs2: -1 +is_lw: 0 +is_sw: 0 +fetch_stall_cycles: 0 +mem_stall_cycles: 0 +stall_warp: 1 +wspawn: 0 +stalled: 0 +********************************** Fetch ********************************* +valid: 0 +PC: 0 +wid: 1 +rd: -1 rs1: -1 rs2: -1 +is_lw: 0 +is_sw: 0 +fetch_stall_cycles: 0 +mem_stall_cycles: 0 +stall_warp: 0 +wspawn: 0 +stalled: 0 + + + +------------------------------------------------------ +CYCLE: 432 +Stalled Warps: +1 0 0 0 0 0 0 0 + +********************************** Writeback ********************************* +valid: 0 +PC: 0 +wid: 2 +rd: -1 rs1: -1 rs2: -1 +is_lw: 0 +is_sw: 0 +fetch_stall_cycles: 0 +mem_stall_cycles: 0 +stall_warp: 0 +wspawn: 0 +stalled: 0 +********************************** LSU ********************************* +valid: 0 +PC: 0 +wid: 0 +rd: -1 rs1: -1 rs2: -1 +is_lw: 0 +is_sw: 0 +fetch_stall_cycles: 0 +mem_stall_cycles: 0 +stall_warp: 0 +wspawn: 0 +stalled: 0 +********************************** execute_unit ********************************* +valid: 0 +PC: 0 +wid: 5 +rd: -1 rs1: -1 rs2: -1 +is_lw: 0 +is_sw: 0 +fetch_stall_cycles: 0 +mem_stall_cycles: 0 +stall_warp: 0 +wspawn: 0 +stalled: 0 +********************************** scheduler ********************************* +valid: 1 +PC: 800008bc +wid: 0 +rd: 1 rs1: -1 rs2: -1 +is_lw: 0 +is_sw: 0 +fetch_stall_cycles: 0 +mem_stall_cycles: 0 +stall_warp: 1 +wspawn: 0 +stalled: 0 +********************************** Decode ********************************* +valid: 0 +PC: 0 +wid: 1 +rd: -1 rs1: -1 rs2: -1 +is_lw: 0 +is_sw: 0 +fetch_stall_cycles: 0 +mem_stall_cycles: 0 +stall_warp: 0 +wspawn: 0 +stalled: 0 +********************************** Fetch ********************************* +valid: 0 +PC: 0 +wid: 2 +rd: -1 rs1: -1 rs2: -1 +is_lw: 0 +is_sw: 0 +fetch_stall_cycles: 0 +mem_stall_cycles: 0 +stall_warp: 0 +wspawn: 0 +stalled: 0 + + + +------------------------------------------------------ +CYCLE: 433 +Stalled Warps: +1 0 0 0 0 0 0 0 + +********************************** Writeback ********************************* +valid: 0 +PC: 0 +wid: 3 +rd: -1 rs1: -1 rs2: -1 +is_lw: 0 +is_sw: 0 +fetch_stall_cycles: 0 +mem_stall_cycles: 0 +stall_warp: 0 +wspawn: 0 +stalled: 0 +********************************** LSU ********************************* +valid: 0 +PC: 0 +wid: 0 +rd: -1 rs1: -1 rs2: -1 +is_lw: 0 +is_sw: 0 +fetch_stall_cycles: 0 +mem_stall_cycles: 0 +stall_warp: 0 +wspawn: 0 +stalled: 0 +********************************** execute_unit ********************************* +valid: 1 +PC: 800008bc +wid: 0 +rd: 1 rs1: -1 rs2: -1 +is_lw: 0 +is_sw: 0 +fetch_stall_cycles: 0 +mem_stall_cycles: 0 +stall_warp: 1 +wspawn: 0 +stalled: 0 +********************************** scheduler ********************************* +valid: 0 +PC: 0 +wid: 1 +rd: -1 rs1: -1 rs2: -1 +is_lw: 0 +is_sw: 0 +fetch_stall_cycles: 0 +mem_stall_cycles: 0 +stall_warp: 0 +wspawn: 0 +stalled: 0 +********************************** Decode ********************************* +valid: 0 +PC: 0 +wid: 2 +rd: -1 rs1: -1 rs2: -1 +is_lw: 0 +is_sw: 0 +fetch_stall_cycles: 0 +mem_stall_cycles: 0 +stall_warp: 0 +wspawn: 0 +stalled: 0 +********************************** Fetch ********************************* +valid: 0 +PC: 0 +wid: 3 +rd: -1 rs1: -1 rs2: -1 +is_lw: 0 +is_sw: 0 +fetch_stall_cycles: 0 +mem_stall_cycles: 0 +stall_warp: 0 +wspawn: 0 +stalled: 0 + + + +------------------------------------------------------ +CYCLE: 434 +Stalled Warps: +1 0 0 0 0 0 0 0 + +********************************** Writeback ********************************* +valid: 1 +PC: 800008bc +wid: 0 +rd: 1 rs1: -1 rs2: -1 +is_lw: 0 +is_sw: 0 +fetch_stall_cycles: 0 +mem_stall_cycles: 0 +stall_warp: 1 +wspawn: 0 +stalled: 0 +********************************** LSU ********************************* +valid: 0 +PC: 0 +wid: 0 +rd: -1 rs1: -1 rs2: -1 +is_lw: 0 +is_sw: 0 +fetch_stall_cycles: 0 +mem_stall_cycles: 0 +stall_warp: 0 +wspawn: 0 +stalled: 0 +********************************** execute_unit ********************************* +valid: 0 +PC: 0 +wid: 1 +rd: -1 rs1: -1 rs2: -1 +is_lw: 0 +is_sw: 0 +fetch_stall_cycles: 0 +mem_stall_cycles: 0 +stall_warp: 0 +wspawn: 0 +stalled: 0 +********************************** scheduler ********************************* +valid: 0 +PC: 0 +wid: 2 +rd: -1 rs1: -1 rs2: -1 +is_lw: 0 +is_sw: 0 +fetch_stall_cycles: 0 +mem_stall_cycles: 0 +stall_warp: 0 +wspawn: 0 +stalled: 0 +********************************** Decode ********************************* +valid: 0 +PC: 0 +wid: 3 +rd: -1 rs1: -1 rs2: -1 +is_lw: 0 +is_sw: 0 +fetch_stall_cycles: 0 +mem_stall_cycles: 0 +stall_warp: 0 +wspawn: 0 +stalled: 0 +********************************** Fetch ********************************* +valid: 0 +PC: 0 +wid: 4 +rd: -1 rs1: -1 rs2: -1 +is_lw: 0 +is_sw: 0 +fetch_stall_cycles: 0 +mem_stall_cycles: 0 +stall_warp: 0 +wspawn: 0 +stalled: 0 + + + +------------------------------------------------------ +CYCLE: 435 +Stalled Warps: +1 0 0 0 0 0 0 0 + +********************************** Writeback ********************************* +valid: 0 +PC: 0 +wid: 5 +rd: -1 rs1: -1 rs2: -1 +is_lw: 0 +is_sw: 0 +fetch_stall_cycles: 0 +mem_stall_cycles: 0 +stall_warp: 0 +wspawn: 0 +stalled: 0 +********************************** LSU ********************************* +valid: 0 +PC: 0 +wid: 0 +rd: -1 rs1: -1 rs2: -1 +is_lw: 0 +is_sw: 0 +fetch_stall_cycles: 0 +mem_stall_cycles: 0 +stall_warp: 0 +wspawn: 0 +stalled: 0 +********************************** execute_unit ********************************* +valid: 0 +PC: 0 +wid: 2 +rd: -1 rs1: -1 rs2: -1 +is_lw: 0 +is_sw: 0 +fetch_stall_cycles: 0 +mem_stall_cycles: 0 +stall_warp: 0 +wspawn: 0 +stalled: 0 +********************************** scheduler ********************************* +valid: 0 +PC: 0 +wid: 3 +rd: -1 rs1: -1 rs2: -1 +is_lw: 0 +is_sw: 0 +fetch_stall_cycles: 0 +mem_stall_cycles: 0 +stall_warp: 0 +wspawn: 0 +stalled: 0 +********************************** Decode ********************************* +valid: 0 +PC: 0 +wid: 4 +rd: -1 rs1: -1 rs2: -1 +is_lw: 0 +is_sw: 0 +fetch_stall_cycles: 0 +mem_stall_cycles: 0 +stall_warp: 0 +wspawn: 0 +stalled: 0 +********************************** Fetch ********************************* +valid: 0 +PC: 0 +wid: 5 +rd: -1 rs1: -1 rs2: -1 +is_lw: 0 +is_sw: 0 +fetch_stall_cycles: 0 +mem_stall_cycles: 0 +stall_warp: 0 +wspawn: 0 +stalled: 0 +Warp ID 0 is running + + + +------------------------------------------------------ +CYCLE: 436 +Stalled Warps: +0 0 0 0 0 0 0 0 + +********************************** Writeback ********************************* +valid: 0 +PC: 0 +wid: 0 +rd: -1 rs1: -1 rs2: -1 +is_lw: 0 +is_sw: 0 +fetch_stall_cycles: 0 +mem_stall_cycles: 0 +stall_warp: 0 +wspawn: 0 +stalled: 0 +********************************** LSU ********************************* +valid: 0 +PC: 0 +wid: 0 +rd: -1 rs1: -1 rs2: -1 +is_lw: 0 +is_sw: 0 +fetch_stall_cycles: 0 +mem_stall_cycles: 0 +stall_warp: 0 +wspawn: 0 +stalled: 0 +********************************** execute_unit ********************************* +valid: 0 +PC: 0 +wid: 3 +rd: -1 rs1: -1 rs2: -1 +is_lw: 0 +is_sw: 0 +fetch_stall_cycles: 0 +mem_stall_cycles: 0 +stall_warp: 0 +wspawn: 0 +stalled: 0 +********************************** scheduler ********************************* +valid: 0 +PC: 0 +wid: 4 +rd: -1 rs1: -1 rs2: -1 +is_lw: 0 +is_sw: 0 +fetch_stall_cycles: 0 +mem_stall_cycles: 0 +stall_warp: 0 +wspawn: 0 +stalled: 0 +********************************** Decode ********************************* +valid: 0 +PC: 0 +wid: 5 +rd: -1 rs1: -1 rs2: -1 +is_lw: 0 +is_sw: 0 +fetch_stall_cycles: 0 +mem_stall_cycles: 0 +stall_warp: 0 +wspawn: 0 +stalled: 0 +DEBUG ../core.cpp:386: Core step stepping warp 0[1] +DEBUG ../core.cpp:683: in step pc=0x800000b4 +help: in PC: 800000b4 +CUrrent CODE: 200513 +DEBUG ../core.cpp:703: Fetched at 0x800000b4 +DEBUG ../core.cpp:704: 0x800000b4: i_type; +DEBUG ../instruction.cpp:350: Begin instruction execute. +DEBUG ../instruction.cpp:2117: End instruction execute. +DEBUG ../core.cpp:717: Register state: + %r 0: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r 1: 800008c0 800008bc 800008bc 800008bc 00000000 00000000 00000000 00000000 (0) + %r 2: 6fffeff0 6fffebf4 6fffe7f8 6fffe3fc 00000000 00000000 00000000 00000000 (0) + %r 3: 80001808 80001808 80001808 80001808 00000000 00000000 00000000 00000000 (0) + %r 4: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r 5: 80000a6c 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r 6: 0000000f 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r 7: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r 8: 6ffff000 6fffec04 6fffe808 6fffe40c 00000000 00000000 00000000 00000000 (0) + %r 9: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r10: 00000002 00000001 00000001 00000001 00000000 00000000 00000000 00000000 (0) + %r11: 80000924 00000400 00000800 00000c00 00000000 00000000 00000000 00000000 (0) + %r12: 00000000 00000004 00000008 0000000c 00000000 00000000 00000000 00000000 (0) + %r13: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r14: 00000001 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r15: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r16: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r17: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r18: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r19: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r20: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r21: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r22: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r23: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r24: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r25: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r26: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r27: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r28: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r29: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r30: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r31: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) +DEBUG ../core.cpp:726: Thread mask: + 1 0 0 0 0 0 0 0 + + +DEBUG ../core.cpp:388: Now 1 active threads in 0 +********************************** Fetch ********************************* +valid: 1 +PC: 800000b4 +wid: 0 +rd: 10 rs1: 0 rs2: -1 +is_lw: 0 +is_sw: 0 +fetch_stall_cycles: 3 +mem_stall_cycles: 0 +stall_warp: 0 +wspawn: 0 +stalled: 0 + + + +------------------------------------------------------ +CYCLE: 437 +Stalled Warps: +0 0 0 0 0 0 0 0 + +********************************** Writeback ********************************* +valid: 0 +PC: 0 +wid: 0 +rd: -1 rs1: -1 rs2: -1 +is_lw: 0 +is_sw: 0 +fetch_stall_cycles: 0 +mem_stall_cycles: 0 +stall_warp: 0 +wspawn: 0 +stalled: 0 +********************************** LSU ********************************* +valid: 0 +PC: 0 +wid: 0 +rd: -1 rs1: -1 rs2: -1 +is_lw: 0 +is_sw: 0 +fetch_stall_cycles: 0 +mem_stall_cycles: 0 +stall_warp: 0 +wspawn: 0 +stalled: 0 +********************************** execute_unit ********************************* +valid: 0 +PC: 0 +wid: 4 +rd: -1 rs1: -1 rs2: -1 +is_lw: 0 +is_sw: 0 +fetch_stall_cycles: 0 +mem_stall_cycles: 0 +stall_warp: 0 +wspawn: 0 +stalled: 0 +********************************** scheduler ********************************* +valid: 0 +PC: 0 +wid: 5 +rd: -1 rs1: -1 rs2: -1 +is_lw: 0 +is_sw: 0 +fetch_stall_cycles: 0 +mem_stall_cycles: 0 +stall_warp: 0 +wspawn: 0 +stalled: 0 +********************************** Decode ********************************* +valid: 0 +PC: 0 +wid: 0 +rd: -1 rs1: -1 rs2: -1 +is_lw: 0 +is_sw: 0 +fetch_stall_cycles: 0 +mem_stall_cycles: 0 +stall_warp: 0 +wspawn: 0 +stalled: 0 +********************************** Fetch ********************************* +valid: 1 +PC: 800000b4 +wid: 0 +rd: 10 rs1: 0 rs2: -1 +is_lw: 0 +is_sw: 0 +fetch_stall_cycles: 2 +mem_stall_cycles: 0 +stall_warp: 0 +wspawn: 0 +stalled: 0 + + + +------------------------------------------------------ +CYCLE: 438 +Stalled Warps: +0 0 0 0 0 0 0 0 + +********************************** Writeback ********************************* +valid: 0 +PC: 0 +wid: 0 +rd: -1 rs1: -1 rs2: -1 +is_lw: 0 +is_sw: 0 +fetch_stall_cycles: 0 +mem_stall_cycles: 0 +stall_warp: 0 +wspawn: 0 +stalled: 0 +********************************** LSU ********************************* +valid: 0 +PC: 0 +wid: 0 +rd: -1 rs1: -1 rs2: -1 +is_lw: 0 +is_sw: 0 +fetch_stall_cycles: 0 +mem_stall_cycles: 0 +stall_warp: 0 +wspawn: 0 +stalled: 0 +********************************** execute_unit ********************************* +valid: 0 +PC: 0 +wid: 5 +rd: -1 rs1: -1 rs2: -1 +is_lw: 0 +is_sw: 0 +fetch_stall_cycles: 0 +mem_stall_cycles: 0 +stall_warp: 0 +wspawn: 0 +stalled: 0 +********************************** scheduler ********************************* +valid: 0 +PC: 0 +wid: 0 +rd: -1 rs1: -1 rs2: -1 +is_lw: 0 +is_sw: 0 +fetch_stall_cycles: 0 +mem_stall_cycles: 0 +stall_warp: 0 +wspawn: 0 +stalled: 0 +********************************** Decode ********************************* +valid: 0 +PC: 0 +wid: 0 +rd: -1 rs1: -1 rs2: -1 +is_lw: 0 +is_sw: 0 +fetch_stall_cycles: 0 +mem_stall_cycles: 0 +stall_warp: 0 +wspawn: 0 +stalled: 0 +********************************** Fetch ********************************* +valid: 1 +PC: 800000b4 +wid: 0 +rd: 10 rs1: 0 rs2: -1 +is_lw: 0 +is_sw: 0 +fetch_stall_cycles: 1 +mem_stall_cycles: 0 +stall_warp: 0 +wspawn: 0 +stalled: 0 + + + +------------------------------------------------------ +CYCLE: 439 +Stalled Warps: +0 0 0 0 0 0 0 0 + +********************************** Writeback ********************************* +valid: 0 +PC: 0 +wid: 0 +rd: -1 rs1: -1 rs2: -1 +is_lw: 0 +is_sw: 0 +fetch_stall_cycles: 0 +mem_stall_cycles: 0 +stall_warp: 0 +wspawn: 0 +stalled: 0 +********************************** LSU ********************************* +valid: 0 +PC: 0 +wid: 0 +rd: -1 rs1: -1 rs2: -1 +is_lw: 0 +is_sw: 0 +fetch_stall_cycles: 0 +mem_stall_cycles: 0 +stall_warp: 0 +wspawn: 0 +stalled: 0 +********************************** execute_unit ********************************* +valid: 0 +PC: 0 +wid: 0 +rd: -1 rs1: -1 rs2: -1 +is_lw: 0 +is_sw: 0 +fetch_stall_cycles: 0 +mem_stall_cycles: 0 +stall_warp: 0 +wspawn: 0 +stalled: 0 +********************************** scheduler ********************************* +valid: 0 +PC: 0 +wid: 0 +rd: -1 rs1: -1 rs2: -1 +is_lw: 0 +is_sw: 0 +fetch_stall_cycles: 0 +mem_stall_cycles: 0 +stall_warp: 0 +wspawn: 0 +stalled: 0 +********************************** Decode ********************************* +valid: 0 +PC: 0 +wid: 0 +rd: -1 rs1: -1 rs2: -1 +is_lw: 0 +is_sw: 0 +fetch_stall_cycles: 0 +mem_stall_cycles: 0 +stall_warp: 0 +wspawn: 0 +stalled: 0 +********************************** Fetch ********************************* +valid: 1 +PC: 800000b4 +wid: 0 +rd: 10 rs1: 0 rs2: -1 +is_lw: 0 +is_sw: 0 +fetch_stall_cycles: 0 +mem_stall_cycles: 0 +stall_warp: 0 +wspawn: 0 +stalled: 0 + + + +------------------------------------------------------ +CYCLE: 440 +Stalled Warps: +0 0 0 0 0 0 0 0 + +********************************** Writeback ********************************* +valid: 0 +PC: 0 +wid: 0 +rd: -1 rs1: -1 rs2: -1 +is_lw: 0 +is_sw: 0 +fetch_stall_cycles: 0 +mem_stall_cycles: 0 +stall_warp: 0 +wspawn: 0 +stalled: 0 +********************************** LSU ********************************* +valid: 0 +PC: 0 +wid: 0 +rd: -1 rs1: -1 rs2: -1 +is_lw: 0 +is_sw: 0 +fetch_stall_cycles: 0 +mem_stall_cycles: 0 +stall_warp: 0 +wspawn: 0 +stalled: 0 +********************************** execute_unit ********************************* +valid: 0 +PC: 0 +wid: 0 +rd: -1 rs1: -1 rs2: -1 +is_lw: 0 +is_sw: 0 +fetch_stall_cycles: 0 +mem_stall_cycles: 0 +stall_warp: 0 +wspawn: 0 +stalled: 0 +********************************** scheduler ********************************* +valid: 0 +PC: 0 +wid: 0 +rd: -1 rs1: -1 rs2: -1 +is_lw: 0 +is_sw: 0 +fetch_stall_cycles: 0 +mem_stall_cycles: 0 +stall_warp: 0 +wspawn: 0 +stalled: 0 +********************************** Decode ********************************* +valid: 1 +PC: 800000b4 +wid: 0 +rd: 10 rs1: 0 rs2: -1 +is_lw: 0 +is_sw: 0 +fetch_stall_cycles: 0 +mem_stall_cycles: 0 +stall_warp: 0 +wspawn: 0 +stalled: 0 +DEBUG ../core.cpp:386: Core step stepping warp 0[1] +DEBUG ../core.cpp:683: in step pc=0x800000b8 +help: in PC: 800000b8 +CUrrent CODE: 8572d7 +Entered here: instr type = vector87 +Entered here: instr type = vector +Entered here: imm instrDEBUG ../enc.cpp:247: immed8 +DEBUG ../enc.cpp:250: lmul 0 +DEBUG ../enc.cpp:252: ediv 0 +DEBUG ../enc.cpp:254: sew 2 +DEBUG ../core.cpp:703: Fetched at 0x800000b8 +DEBUG ../core.cpp:704: 0x800000b8: vsetvl; +DEBUG ../instruction.cpp:350: Begin instruction execute. +DEBUG ../instruction.cpp:1091: VSET_ARITH +DEBUG ../instruction.cpp:2004: lmul:1 sew:32 ediv: 1 +DEBUG ../instruction.cpp:2014: VL:2 +DEBUG ../instruction.cpp:2117: End instruction execute. +DEBUG ../core.cpp:717: Register state: + %r 0: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r 1: 800008c0 800008bc 800008bc 800008bc 00000000 00000000 00000000 00000000 (0) + %r 2: 6fffeff0 6fffebf4 6fffe7f8 6fffe3fc 00000000 00000000 00000000 00000000 (0) + %r 3: 80001808 80001808 80001808 80001808 00000000 00000000 00000000 00000000 (0) + %r 4: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r 5: 00000002 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r 6: 0000000f 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r 7: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r 8: 6ffff000 6fffec04 6fffe808 6fffe40c 00000000 00000000 00000000 00000000 (0) + %r 9: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r10: 00000002 00000001 00000001 00000001 00000000 00000000 00000000 00000000 (0) + %r11: 80000924 00000400 00000800 00000c00 00000000 00000000 00000000 00000000 (0) + %r12: 00000000 00000004 00000008 0000000c 00000000 00000000 00000000 00000000 (0) + %r13: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r14: 00000001 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r15: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r16: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r17: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r18: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r19: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r20: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r21: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r22: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r23: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r24: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r25: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r26: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r27: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r28: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r29: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r30: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r31: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) +DEBUG ../core.cpp:726: Thread mask: + 1 0 0 0 0 0 0 0 + + +DEBUG ../core.cpp:388: Now 1 active threads in 0 +********************************** Fetch ********************************* +valid: 1 +PC: 800000b8 +wid: 0 +rd: 5 rs1: 10 rs2: -1 +is_lw: 0 +is_sw: 0 +fetch_stall_cycles: 0 +mem_stall_cycles: 0 +stall_warp: 0 +wspawn: 0 +stalled: 0 + + + +------------------------------------------------------ +CYCLE: 441 +Stalled Warps: +0 0 0 0 0 0 0 0 + +********************************** Writeback ********************************* +valid: 0 +PC: 0 +wid: 0 +rd: -1 rs1: -1 rs2: -1 +is_lw: 0 +is_sw: 0 +fetch_stall_cycles: 0 +mem_stall_cycles: 0 +stall_warp: 0 +wspawn: 0 +stalled: 0 +********************************** LSU ********************************* +valid: 0 +PC: 0 +wid: 0 +rd: -1 rs1: -1 rs2: -1 +is_lw: 0 +is_sw: 0 +fetch_stall_cycles: 0 +mem_stall_cycles: 0 +stall_warp: 0 +wspawn: 0 +stalled: 0 +********************************** execute_unit ********************************* +valid: 0 +PC: 0 +wid: 0 +rd: -1 rs1: -1 rs2: -1 +is_lw: 0 +is_sw: 0 +fetch_stall_cycles: 0 +mem_stall_cycles: 0 +stall_warp: 0 +wspawn: 0 +stalled: 0 +********************************** scheduler ********************************* +valid: 1 +PC: 800000b4 +wid: 0 +rd: 10 rs1: 0 rs2: -1 +is_lw: 0 +is_sw: 0 +fetch_stall_cycles: 0 +mem_stall_cycles: 0 +stall_warp: 0 +wspawn: 0 +stalled: 0 +********************************** Decode ********************************* +valid: 1 +PC: 800000b8 +wid: 0 +rd: 5 rs1: 10 rs2: -1 +is_lw: 0 +is_sw: 0 +fetch_stall_cycles: 0 +mem_stall_cycles: 0 +stall_warp: 0 +wspawn: 0 +stalled: 0 +DEBUG ../core.cpp:386: Core step stepping warp 0[1] +DEBUG ../core.cpp:683: in step pc=0x800000bc +help: in PC: 800000bc +CUrrent CODE: a00513 +DEBUG ../core.cpp:703: Fetched at 0x800000bc +DEBUG ../core.cpp:704: 0x800000bc: i_type; +DEBUG ../instruction.cpp:350: Begin instruction execute. +DEBUG ../instruction.cpp:2117: End instruction execute. +DEBUG ../core.cpp:717: Register state: + %r 0: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r 1: 800008c0 800008bc 800008bc 800008bc 00000000 00000000 00000000 00000000 (0) + %r 2: 6fffeff0 6fffebf4 6fffe7f8 6fffe3fc 00000000 00000000 00000000 00000000 (0) + %r 3: 80001808 80001808 80001808 80001808 00000000 00000000 00000000 00000000 (0) + %r 4: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r 5: 00000002 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r 6: 0000000f 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r 7: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r 8: 6ffff000 6fffec04 6fffe808 6fffe40c 00000000 00000000 00000000 00000000 (0) + %r 9: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r10: 0000000a 00000001 00000001 00000001 00000000 00000000 00000000 00000000 (0) + %r11: 80000924 00000400 00000800 00000c00 00000000 00000000 00000000 00000000 (0) + %r12: 00000000 00000004 00000008 0000000c 00000000 00000000 00000000 00000000 (0) + %r13: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r14: 00000001 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r15: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r16: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r17: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r18: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r19: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r20: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r21: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r22: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r23: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r24: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r25: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r26: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r27: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r28: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r29: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r30: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r31: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) +DEBUG ../core.cpp:726: Thread mask: + 1 0 0 0 0 0 0 0 + + +DEBUG ../core.cpp:388: Now 1 active threads in 0 +********************************** Fetch ********************************* +valid: 1 +PC: 800000bc +wid: 0 +rd: 10 rs1: 0 rs2: -1 +is_lw: 0 +is_sw: 0 +fetch_stall_cycles: 0 +mem_stall_cycles: 0 +stall_warp: 0 +wspawn: 0 +stalled: 0 + + + +------------------------------------------------------ +CYCLE: 442 +Stalled Warps: +0 0 0 0 0 0 0 0 + +********************************** Writeback ********************************* +valid: 0 +PC: 0 +wid: 0 +rd: -1 rs1: -1 rs2: -1 +is_lw: 0 +is_sw: 0 +fetch_stall_cycles: 0 +mem_stall_cycles: 0 +stall_warp: 0 +wspawn: 0 +stalled: 0 +********************************** LSU ********************************* +valid: 0 +PC: 0 +wid: 0 +rd: -1 rs1: -1 rs2: -1 +is_lw: 0 +is_sw: 0 +fetch_stall_cycles: 0 +mem_stall_cycles: 0 +stall_warp: 0 +wspawn: 0 +stalled: 0 +********************************** execute_unit ********************************* +valid: 1 +PC: 800000b4 +wid: 0 +rd: 10 rs1: 0 rs2: -1 +is_lw: 0 +is_sw: 0 +fetch_stall_cycles: 0 +mem_stall_cycles: 0 +stall_warp: 0 +wspawn: 0 +stalled: 0 +********************************** scheduler ********************************* +valid: 1 +PC: 800000b8 +wid: 0 +rd: 5 rs1: 10 rs2: -1 +is_lw: 0 +is_sw: 0 +fetch_stall_cycles: 0 +mem_stall_cycles: 0 +stall_warp: 0 +wspawn: 0 +stalled: 0 +********************************** Decode ********************************* +valid: 1 +PC: 800000bc +wid: 0 +rd: 10 rs1: 0 rs2: -1 +is_lw: 0 +is_sw: 0 +fetch_stall_cycles: 0 +mem_stall_cycles: 0 +stall_warp: 0 +wspawn: 0 +stalled: 0 +DEBUG ../core.cpp:386: Core step stepping warp 0[1] +DEBUG ../core.cpp:683: in step pc=0x800000c0 +help: in PC: 800000c0 +CUrrent CODE: a5a023 +DEBUG ../core.cpp:703: Fetched at 0x800000c0 +DEBUG ../core.cpp:704: 0x800000c0: store; +DEBUG ../instruction.cpp:350: Begin instruction execute. +STORE MEM ADDRESS: 80000924 + 0 +DEBUG ../instruction.cpp:2117: End instruction execute. +DEBUG ../core.cpp:717: Register state: + %r 0: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r 1: 800008c0 800008bc 800008bc 800008bc 00000000 00000000 00000000 00000000 (0) + %r 2: 6fffeff0 6fffebf4 6fffe7f8 6fffe3fc 00000000 00000000 00000000 00000000 (0) + %r 3: 80001808 80001808 80001808 80001808 00000000 00000000 00000000 00000000 (0) + %r 4: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r 5: 00000002 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r 6: 0000000f 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r 7: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r 8: 6ffff000 6fffec04 6fffe808 6fffe40c 00000000 00000000 00000000 00000000 (0) + %r 9: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r10: 0000000a 00000001 00000001 00000001 00000000 00000000 00000000 00000000 (0) + %r11: 80000924 00000400 00000800 00000c00 00000000 00000000 00000000 00000000 (0) + %r12: 00000000 00000004 00000008 0000000c 00000000 00000000 00000000 00000000 (0) + %r13: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r14: 00000001 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r15: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r16: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r17: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r18: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r19: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r20: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r21: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r22: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r23: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r24: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r25: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r26: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r27: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r28: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r29: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r30: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r31: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) +DEBUG ../core.cpp:726: Thread mask: + 1 0 0 0 0 0 0 0 + + +DEBUG ../core.cpp:388: Now 1 active threads in 0 +********************************** Fetch ********************************* +valid: 1 +PC: 800000c0 +wid: 0 +rd: -1 rs1: 11 rs2: 10 +is_lw: 0 +is_sw: 1 +fetch_stall_cycles: 3 +mem_stall_cycles: 3 +stall_warp: 0 +wspawn: 0 +stalled: 0 + + + +------------------------------------------------------ +CYCLE: 443 +Stalled Warps: +0 0 0 0 0 0 0 0 + +********************************** Writeback ********************************* +valid: 1 +PC: 800000b4 +wid: 0 +rd: 10 rs1: 0 rs2: -1 +is_lw: 0 +is_sw: 0 +fetch_stall_cycles: 0 +mem_stall_cycles: 0 +stall_warp: 0 +wspawn: 0 +stalled: 0 +********************************** LSU ********************************* +valid: 0 +PC: 0 +wid: 0 +rd: -1 rs1: -1 rs2: -1 +is_lw: 0 +is_sw: 0 +fetch_stall_cycles: 0 +mem_stall_cycles: 0 +stall_warp: 0 +wspawn: 0 +stalled: 0 +&&&&&&&&&&&&&&&&&&&&&&&& EXECUTE SRCS NOT READY +********************************** execute_unit ********************************* +valid: 0 +PC: 0 +wid: 0 +rd: -1 rs1: -1 rs2: -1 +is_lw: 0 +is_sw: 0 +fetch_stall_cycles: 0 +mem_stall_cycles: 0 +stall_warp: 0 +wspawn: 0 +stalled: 0 +********************************** scheduler ********************************* +valid: 1 +PC: 800000b8 +wid: 0 +rd: 5 rs1: 10 rs2: -1 +is_lw: 0 +is_sw: 0 +fetch_stall_cycles: 0 +mem_stall_cycles: 0 +stall_warp: 0 +wspawn: 0 +stalled: 1 +********************************** Decode ********************************* +valid: 1 +PC: 800000bc +wid: 0 +rd: 10 rs1: 0 rs2: -1 +is_lw: 0 +is_sw: 0 +fetch_stall_cycles: 0 +mem_stall_cycles: 0 +stall_warp: 0 +wspawn: 0 +stalled: 0 +********************************** Fetch ********************************* +valid: 1 +PC: 800000c0 +wid: 0 +rd: -1 rs1: 11 rs2: 10 +is_lw: 0 +is_sw: 1 +fetch_stall_cycles: 2 +mem_stall_cycles: 3 +stall_warp: 0 +wspawn: 0 +stalled: 0 + + + +------------------------------------------------------ +CYCLE: 444 +Stalled Warps: +0 0 0 0 0 0 0 0 + +********************************** Writeback ********************************* +valid: 0 +PC: 0 +wid: 0 +rd: -1 rs1: -1 rs2: -1 +is_lw: 0 +is_sw: 0 +fetch_stall_cycles: 0 +mem_stall_cycles: 0 +stall_warp: 0 +wspawn: 0 +stalled: 0 +********************************** LSU ********************************* +valid: 0 +PC: 0 +wid: 0 +rd: -1 rs1: -1 rs2: -1 +is_lw: 0 +is_sw: 0 +fetch_stall_cycles: 0 +mem_stall_cycles: 0 +stall_warp: 0 +wspawn: 0 +stalled: 0 +********************************** execute_unit ********************************* +valid: 1 +PC: 800000b8 +wid: 0 +rd: 5 rs1: 10 rs2: -1 +is_lw: 0 +is_sw: 0 +fetch_stall_cycles: 0 +mem_stall_cycles: 0 +stall_warp: 0 +wspawn: 0 +stalled: 0 +********************************** scheduler ********************************* +valid: 1 +PC: 800000bc +wid: 0 +rd: 10 rs1: 0 rs2: -1 +is_lw: 0 +is_sw: 0 +fetch_stall_cycles: 0 +mem_stall_cycles: 0 +stall_warp: 0 +wspawn: 0 +stalled: 0 +********************************** Decode ********************************* +valid: 0 +PC: 0 +wid: 0 +rd: -1 rs1: -1 rs2: -1 +is_lw: 0 +is_sw: 0 +fetch_stall_cycles: 0 +mem_stall_cycles: 0 +stall_warp: 0 +wspawn: 0 +stalled: 0 +********************************** Fetch ********************************* +valid: 1 +PC: 800000c0 +wid: 0 +rd: -1 rs1: 11 rs2: 10 +is_lw: 0 +is_sw: 1 +fetch_stall_cycles: 1 +mem_stall_cycles: 3 +stall_warp: 0 +wspawn: 0 +stalled: 0 + + + +------------------------------------------------------ +CYCLE: 445 +Stalled Warps: +0 0 0 0 0 0 0 0 + +********************************** Writeback ********************************* +valid: 1 +PC: 800000b8 +wid: 0 +rd: 5 rs1: 10 rs2: -1 +is_lw: 0 +is_sw: 0 +fetch_stall_cycles: 0 +mem_stall_cycles: 0 +stall_warp: 0 +wspawn: 0 +stalled: 0 +********************************** LSU ********************************* +valid: 0 +PC: 0 +wid: 0 +rd: -1 rs1: -1 rs2: -1 +is_lw: 0 +is_sw: 0 +fetch_stall_cycles: 0 +mem_stall_cycles: 0 +stall_warp: 0 +wspawn: 0 +stalled: 0 +********************************** execute_unit ********************************* +valid: 1 +PC: 800000bc +wid: 0 +rd: 10 rs1: 0 rs2: -1 +is_lw: 0 +is_sw: 0 +fetch_stall_cycles: 0 +mem_stall_cycles: 0 +stall_warp: 0 +wspawn: 0 +stalled: 0 +********************************** scheduler ********************************* +valid: 0 +PC: 0 +wid: 0 +rd: -1 rs1: -1 rs2: -1 +is_lw: 0 +is_sw: 0 +fetch_stall_cycles: 0 +mem_stall_cycles: 0 +stall_warp: 0 +wspawn: 0 +stalled: 0 +********************************** Decode ********************************* +valid: 0 +PC: 0 +wid: 0 +rd: -1 rs1: -1 rs2: -1 +is_lw: 0 +is_sw: 0 +fetch_stall_cycles: 0 +mem_stall_cycles: 0 +stall_warp: 0 +wspawn: 0 +stalled: 0 +********************************** Fetch ********************************* +valid: 1 +PC: 800000c0 +wid: 0 +rd: -1 rs1: 11 rs2: 10 +is_lw: 0 +is_sw: 1 +fetch_stall_cycles: 0 +mem_stall_cycles: 3 +stall_warp: 0 +wspawn: 0 +stalled: 0 + + + +------------------------------------------------------ +CYCLE: 446 +Stalled Warps: +0 0 0 0 0 0 0 0 + +********************************** Writeback ********************************* +valid: 1 +PC: 800000bc +wid: 0 +rd: 10 rs1: 0 rs2: -1 +is_lw: 0 +is_sw: 0 +fetch_stall_cycles: 0 +mem_stall_cycles: 0 +stall_warp: 0 +wspawn: 0 +stalled: 0 +********************************** LSU ********************************* +valid: 0 +PC: 0 +wid: 0 +rd: -1 rs1: -1 rs2: -1 +is_lw: 0 +is_sw: 0 +fetch_stall_cycles: 0 +mem_stall_cycles: 0 +stall_warp: 0 +wspawn: 0 +stalled: 0 +********************************** execute_unit ********************************* +valid: 0 +PC: 0 +wid: 0 +rd: -1 rs1: -1 rs2: -1 +is_lw: 0 +is_sw: 0 +fetch_stall_cycles: 0 +mem_stall_cycles: 0 +stall_warp: 0 +wspawn: 0 +stalled: 0 +********************************** scheduler ********************************* +valid: 0 +PC: 0 +wid: 0 +rd: -1 rs1: -1 rs2: -1 +is_lw: 0 +is_sw: 0 +fetch_stall_cycles: 0 +mem_stall_cycles: 0 +stall_warp: 0 +wspawn: 0 +stalled: 0 +********************************** Decode ********************************* +valid: 1 +PC: 800000c0 +wid: 0 +rd: -1 rs1: 11 rs2: 10 +is_lw: 0 +is_sw: 1 +fetch_stall_cycles: 0 +mem_stall_cycles: 3 +stall_warp: 0 +wspawn: 0 +stalled: 0 +DEBUG ../core.cpp:386: Core step stepping warp 0[1] +DEBUG ../core.cpp:683: in step pc=0x800000c4 +help: in PC: 800000c4 +CUrrent CODE: 2a5a023 +DEBUG ../core.cpp:703: Fetched at 0x800000c4 +DEBUG ../core.cpp:704: 0x800000c4: store; +DEBUG ../instruction.cpp:350: Begin instruction execute. +STORE MEM ADDRESS: 80000924 + 20 +DEBUG ../instruction.cpp:2117: End instruction execute. +DEBUG ../core.cpp:717: Register state: + %r 0: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r 1: 800008c0 800008bc 800008bc 800008bc 00000000 00000000 00000000 00000000 (0) + %r 2: 6fffeff0 6fffebf4 6fffe7f8 6fffe3fc 00000000 00000000 00000000 00000000 (0) + %r 3: 80001808 80001808 80001808 80001808 00000000 00000000 00000000 00000000 (0) + %r 4: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r 5: 00000002 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r 6: 0000000f 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r 7: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r 8: 6ffff000 6fffec04 6fffe808 6fffe40c 00000000 00000000 00000000 00000000 (0) + %r 9: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r10: 0000000a 00000001 00000001 00000001 00000000 00000000 00000000 00000000 (0) + %r11: 80000924 00000400 00000800 00000c00 00000000 00000000 00000000 00000000 (0) + %r12: 00000000 00000004 00000008 0000000c 00000000 00000000 00000000 00000000 (0) + %r13: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r14: 00000001 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r15: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r16: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r17: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r18: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r19: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r20: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r21: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r22: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r23: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r24: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r25: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r26: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r27: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r28: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r29: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r30: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r31: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) +DEBUG ../core.cpp:726: Thread mask: + 1 0 0 0 0 0 0 0 + + +DEBUG ../core.cpp:388: Now 1 active threads in 0 +********************************** Fetch ********************************* +valid: 1 +PC: 800000c4 +wid: 0 +rd: -1 rs1: 11 rs2: 10 +is_lw: 0 +is_sw: 1 +fetch_stall_cycles: 0 +mem_stall_cycles: 3 +stall_warp: 0 +wspawn: 0 +stalled: 0 + + + +------------------------------------------------------ +CYCLE: 447 +Stalled Warps: +0 0 0 0 0 0 0 0 + +********************************** Writeback ********************************* +valid: 0 +PC: 0 +wid: 0 +rd: -1 rs1: -1 rs2: -1 +is_lw: 0 +is_sw: 0 +fetch_stall_cycles: 0 +mem_stall_cycles: 0 +stall_warp: 0 +wspawn: 0 +stalled: 0 +********************************** LSU ********************************* +valid: 0 +PC: 0 +wid: 0 +rd: -1 rs1: -1 rs2: -1 +is_lw: 0 +is_sw: 0 +fetch_stall_cycles: 0 +mem_stall_cycles: 0 +stall_warp: 0 +wspawn: 0 +stalled: 0 +********************************** execute_unit ********************************* +valid: 0 +PC: 0 +wid: 0 +rd: -1 rs1: -1 rs2: -1 +is_lw: 0 +is_sw: 0 +fetch_stall_cycles: 0 +mem_stall_cycles: 0 +stall_warp: 0 +wspawn: 0 +stalled: 0 +********************************** scheduler ********************************* +valid: 1 +PC: 800000c0 +wid: 0 +rd: -1 rs1: 11 rs2: 10 +is_lw: 0 +is_sw: 1 +fetch_stall_cycles: 0 +mem_stall_cycles: 3 +stall_warp: 0 +wspawn: 0 +stalled: 0 +********************************** Decode ********************************* +valid: 1 +PC: 800000c4 +wid: 0 +rd: -1 rs1: 11 rs2: 10 +is_lw: 0 +is_sw: 1 +fetch_stall_cycles: 0 +mem_stall_cycles: 3 +stall_warp: 0 +wspawn: 0 +stalled: 0 +DEBUG ../core.cpp:386: Core step stepping warp 0[1] +DEBUG ../core.cpp:683: in step pc=0x800000c8 +help: in PC: 800000c8 +CUrrent CODE: 1205e087 +Entered here: instr type = vector7 +DEBUG ../enc.cpp:275: vector load instr +DEBUG ../core.cpp:703: Fetched at 0x800000c8 +DEBUG ../core.cpp:704: 0x800000c8: vl; +DEBUG ../instruction.cpp:350: Begin instruction execute. +DEBUG ../instruction.cpp:2035: Executing vector load +DEBUG ../instruction.cpp:2037: lmul: 1 VLEN:96sew: 32 +DEBUG ../instruction.cpp:2038: src: 11 2147485988 +DEBUG ../instruction.cpp:2039: dest1 +DEBUG ../instruction.cpp:2040: width6 +DEBUG ../instruction.cpp:2048: Data read 10 +DEBUG ../instruction.cpp:2048: Data read 10 +DEBUG ../instruction.cpp:2060: Vector Register state after addition: +reg[0][0] = 0 +reg[0][1] = 0 +reg[0][2] = 0 +reg[1][0] = 10 +reg[1][1] = 10 +reg[1][2] = 0 +reg[2][0] = 0 +reg[2][1] = 0 +reg[2][2] = 0 +reg[3][0] = 0 +reg[3][1] = 0 +reg[3][2] = 0 +reg[4][0] = 0 +reg[4][1] = 0 +reg[4][2] = 0 +reg[5][0] = 0 +reg[5][1] = 0 +reg[5][2] = 0 +reg[6][0] = 0 +reg[6][1] = 0 +reg[6][2] = 0 +reg[7][0] = 0 +reg[7][1] = 0 +reg[7][2] = 0 +reg[8][0] = 0 +reg[8][1] = 0 +reg[8][2] = 0 +reg[9][0] = 0 +reg[9][1] = 0 +reg[9][2] = 0 +reg[10][0] = 0 +reg[10][1] = 0 +reg[10][2] = 0 +reg[11][0] = 0 +reg[11][1] = 0 +reg[11][2] = 0 +reg[12][0] = 0 +reg[12][1] = 0 +reg[12][2] = 0 +reg[13][0] = 0 +reg[13][1] = 0 +reg[13][2] = 0 +reg[14][0] = 0 +reg[14][1] = 0 +reg[14][2] = 0 +reg[15][0] = 0 +reg[15][1] = 0 +reg[15][2] = 0 +reg[16][0] = 0 +reg[16][1] = 0 +reg[16][2] = 0 +reg[17][0] = 0 +reg[17][1] = 0 +reg[17][2] = 0 +reg[18][0] = 0 +reg[18][1] = 0 +reg[18][2] = 0 +reg[19][0] = 0 +reg[19][1] = 0 +reg[19][2] = 0 +reg[20][0] = 0 +reg[20][1] = 0 +reg[20][2] = 0 +reg[21][0] = 0 +reg[21][1] = 0 +reg[21][2] = 0 +reg[22][0] = 0 +reg[22][1] = 0 +reg[22][2] = 0 +reg[23][0] = 0 +reg[23][1] = 0 +reg[23][2] = 0 +reg[24][0] = 0 +reg[24][1] = 0 +reg[24][2] = 0 +reg[25][0] = 0 +reg[25][1] = 0 +reg[25][2] = 0 +reg[26][0] = 0 +reg[26][1] = 0 +reg[26][2] = 0 +reg[27][0] = 0 +reg[27][1] = 0 +reg[27][2] = 0 +reg[28][0] = 0 +reg[28][1] = 0 +reg[28][2] = 0 +reg[29][0] = 0 +reg[29][1] = 0 +reg[29][2] = 0 +reg[30][0] = 0 +reg[30][1] = 0 +reg[30][2] = 0 +reg[31][0] = 0 +reg[31][1] = 0 +reg[31][2] = 0 +DEBUG ../instruction.cpp:2117: End instruction execute. +DEBUG ../core.cpp:717: Register state: + %r 0: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r 1: 800008c0 800008bc 800008bc 800008bc 00000000 00000000 00000000 00000000 (0) + %r 2: 6fffeff0 6fffebf4 6fffe7f8 6fffe3fc 00000000 00000000 00000000 00000000 (0) + %r 3: 80001808 80001808 80001808 80001808 00000000 00000000 00000000 00000000 (0) + %r 4: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r 5: 00000002 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r 6: 0000000f 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r 7: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r 8: 6ffff000 6fffec04 6fffe808 6fffe40c 00000000 00000000 00000000 00000000 (0) + %r 9: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r10: 0000000a 00000001 00000001 00000001 00000000 00000000 00000000 00000000 (0) + %r11: 80000924 00000400 00000800 00000c00 00000000 00000000 00000000 00000000 (0) + %r12: 00000000 00000004 00000008 0000000c 00000000 00000000 00000000 00000000 (0) + %r13: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r14: 00000001 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r15: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r16: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r17: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r18: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r19: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r20: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r21: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r22: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r23: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r24: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r25: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r26: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r27: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r28: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r29: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r30: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r31: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) +DEBUG ../core.cpp:726: Thread mask: + 1 0 0 0 0 0 0 0 + + +DEBUG ../core.cpp:388: Now 1 active threads in 0 +********************************** Fetch ********************************* +valid: 1 +PC: 800000c8 +wid: 0 +rd: 1 rs1: 11 rs2: 0 +is_lw: 0 +is_sw: 0 +fetch_stall_cycles: 0 +mem_stall_cycles: 0 +stall_warp: 0 +wspawn: 0 +stalled: 0 + + + +------------------------------------------------------ +CYCLE: 448 +Stalled Warps: +0 0 0 0 0 0 0 0 + +********************************** Writeback ********************************* +valid: 0 +PC: 0 +wid: 0 +rd: -1 rs1: -1 rs2: -1 +is_lw: 0 +is_sw: 0 +fetch_stall_cycles: 0 +mem_stall_cycles: 0 +stall_warp: 0 +wspawn: 0 +stalled: 0 +********************************** LSU ********************************* +valid: 1 +PC: 800000c0 +wid: 0 +rd: -1 rs1: 11 rs2: 10 +is_lw: 0 +is_sw: 1 +fetch_stall_cycles: 0 +mem_stall_cycles: 2 +stall_warp: 0 +wspawn: 0 +stalled: 0 +********************************** execute_unit ********************************* +valid: 0 +PC: 0 +wid: 0 +rd: -1 rs1: -1 rs2: -1 +is_lw: 0 +is_sw: 0 +fetch_stall_cycles: 0 +mem_stall_cycles: 0 +stall_warp: 0 +wspawn: 0 +stalled: 0 +********************************** scheduler ********************************* +valid: 1 +PC: 800000c4 +wid: 0 +rd: -1 rs1: 11 rs2: 10 +is_lw: 0 +is_sw: 1 +fetch_stall_cycles: 0 +mem_stall_cycles: 3 +stall_warp: 0 +wspawn: 0 +stalled: 0 +********************************** Decode ********************************* +valid: 1 +PC: 800000c8 +wid: 0 +rd: 1 rs1: 11 rs2: 0 +is_lw: 0 +is_sw: 0 +fetch_stall_cycles: 0 +mem_stall_cycles: 0 +stall_warp: 0 +wspawn: 0 +stalled: 0 +DEBUG ../core.cpp:386: Core step stepping warp 0[1] +DEBUG ../core.cpp:683: in step pc=0x800000cc +help: in PC: 800000cc +CUrrent CODE: 100613 +DEBUG ../core.cpp:703: Fetched at 0x800000cc +DEBUG ../core.cpp:704: 0x800000cc: i_type; +DEBUG ../instruction.cpp:350: Begin instruction execute. +DEBUG ../instruction.cpp:2117: End instruction execute. +DEBUG ../core.cpp:717: Register state: + %r 0: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r 1: 800008c0 800008bc 800008bc 800008bc 00000000 00000000 00000000 00000000 (0) + %r 2: 6fffeff0 6fffebf4 6fffe7f8 6fffe3fc 00000000 00000000 00000000 00000000 (0) + %r 3: 80001808 80001808 80001808 80001808 00000000 00000000 00000000 00000000 (0) + %r 4: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r 5: 00000002 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r 6: 0000000f 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r 7: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r 8: 6ffff000 6fffec04 6fffe808 6fffe40c 00000000 00000000 00000000 00000000 (0) + %r 9: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r10: 0000000a 00000001 00000001 00000001 00000000 00000000 00000000 00000000 (0) + %r11: 80000924 00000400 00000800 00000c00 00000000 00000000 00000000 00000000 (0) + %r12: 00000001 00000004 00000008 0000000c 00000000 00000000 00000000 00000000 (0) + %r13: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r14: 00000001 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r15: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r16: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r17: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r18: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r19: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r20: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r21: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r22: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r23: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r24: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r25: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r26: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r27: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r28: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r29: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r30: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r31: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) +DEBUG ../core.cpp:726: Thread mask: + 1 0 0 0 0 0 0 0 + + +DEBUG ../core.cpp:388: Now 1 active threads in 0 +********************************** Fetch ********************************* +valid: 1 +PC: 800000cc +wid: 0 +rd: 12 rs1: 0 rs2: -1 +is_lw: 0 +is_sw: 0 +fetch_stall_cycles: 0 +mem_stall_cycles: 0 +stall_warp: 0 +wspawn: 0 +stalled: 0 + + + +------------------------------------------------------ +CYCLE: 449 +Stalled Warps: +0 0 0 0 0 0 0 0 + +********************************** Writeback ********************************* +valid: 0 +PC: 0 +wid: 0 +rd: -1 rs1: -1 rs2: -1 +is_lw: 0 +is_sw: 0 +fetch_stall_cycles: 0 +mem_stall_cycles: 0 +stall_warp: 0 +wspawn: 0 +stalled: 0 +********************************** LSU ********************************* +valid: 1 +PC: 800000c4 +wid: 0 +rd: -1 rs1: 11 rs2: 10 +is_lw: 0 +is_sw: 1 +fetch_stall_cycles: 0 +mem_stall_cycles: 2 +stall_warp: 0 +wspawn: 0 +stalled: 0 +********************************** execute_unit ********************************* +valid: 0 +PC: 0 +wid: 0 +rd: -1 rs1: -1 rs2: -1 +is_lw: 0 +is_sw: 0 +fetch_stall_cycles: 0 +mem_stall_cycles: 0 +stall_warp: 0 +wspawn: 0 +stalled: 0 +********************************** scheduler ********************************* +valid: 1 +PC: 800000c8 +wid: 0 +rd: 1 rs1: 11 rs2: 0 +is_lw: 0 +is_sw: 0 +fetch_stall_cycles: 0 +mem_stall_cycles: 0 +stall_warp: 0 +wspawn: 0 +stalled: 0 +********************************** Decode ********************************* +valid: 1 +PC: 800000cc +wid: 0 +rd: 12 rs1: 0 rs2: -1 +is_lw: 0 +is_sw: 0 +fetch_stall_cycles: 0 +mem_stall_cycles: 0 +stall_warp: 0 +wspawn: 0 +stalled: 0 +DEBUG ../core.cpp:386: Core step stepping warp 0[1] +DEBUG ../core.cpp:683: in step pc=0x800000d0 +help: in PC: 800000d0 +CUrrent CODE: c6a023 +DEBUG ../core.cpp:703: Fetched at 0x800000d0 +DEBUG ../core.cpp:704: 0x800000d0: store; +DEBUG ../instruction.cpp:350: Begin instruction execute. +STORE MEM ADDRESS: 0 + 0 +DEBUG ../instruction.cpp:2117: End instruction execute. +DEBUG ../core.cpp:717: Register state: + %r 0: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r 1: 800008c0 800008bc 800008bc 800008bc 00000000 00000000 00000000 00000000 (0) + %r 2: 6fffeff0 6fffebf4 6fffe7f8 6fffe3fc 00000000 00000000 00000000 00000000 (0) + %r 3: 80001808 80001808 80001808 80001808 00000000 00000000 00000000 00000000 (0) + %r 4: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r 5: 00000002 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r 6: 0000000f 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r 7: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r 8: 6ffff000 6fffec04 6fffe808 6fffe40c 00000000 00000000 00000000 00000000 (0) + %r 9: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r10: 0000000a 00000001 00000001 00000001 00000000 00000000 00000000 00000000 (0) + %r11: 80000924 00000400 00000800 00000c00 00000000 00000000 00000000 00000000 (0) + %r12: 00000001 00000004 00000008 0000000c 00000000 00000000 00000000 00000000 (0) + %r13: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r14: 00000001 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r15: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r16: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r17: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r18: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r19: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r20: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r21: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r22: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r23: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r24: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r25: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r26: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r27: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r28: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r29: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r30: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r31: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) +DEBUG ../core.cpp:726: Thread mask: + 1 0 0 0 0 0 0 0 + + +DEBUG ../core.cpp:388: Now 1 active threads in 0 +********************************** Fetch ********************************* +valid: 1 +PC: 800000d0 +wid: 0 +rd: -1 rs1: 13 rs2: 12 +is_lw: 0 +is_sw: 1 +fetch_stall_cycles: 3 +mem_stall_cycles: 3 +stall_warp: 0 +wspawn: 0 +stalled: 0 + + + +------------------------------------------------------ +CYCLE: 450 +Stalled Warps: +0 0 0 0 0 0 0 0 + +********************************** Writeback ********************************* +valid: 0 +PC: 0 +wid: 0 +rd: -1 rs1: -1 rs2: -1 +is_lw: 0 +is_sw: 0 +fetch_stall_cycles: 0 +mem_stall_cycles: 0 +stall_warp: 0 +wspawn: 0 +stalled: 0 +********************************** LSU ********************************* +valid: 0 +PC: 0 +wid: 0 +rd: -1 rs1: -1 rs2: -1 +is_lw: 0 +is_sw: 0 +fetch_stall_cycles: 0 +mem_stall_cycles: 0 +stall_warp: 0 +wspawn: 0 +stalled: 0 +********************************** execute_unit ********************************* +valid: 1 +PC: 800000c8 +wid: 0 +rd: 1 rs1: 11 rs2: 0 +is_lw: 0 +is_sw: 0 +fetch_stall_cycles: 0 +mem_stall_cycles: 0 +stall_warp: 0 +wspawn: 0 +stalled: 0 +********************************** scheduler ********************************* +valid: 1 +PC: 800000cc +wid: 0 +rd: 12 rs1: 0 rs2: -1 +is_lw: 0 +is_sw: 0 +fetch_stall_cycles: 0 +mem_stall_cycles: 0 +stall_warp: 0 +wspawn: 0 +stalled: 0 +********************************** Decode ********************************* +valid: 0 +PC: 0 +wid: 0 +rd: -1 rs1: -1 rs2: -1 +is_lw: 0 +is_sw: 0 +fetch_stall_cycles: 0 +mem_stall_cycles: 0 +stall_warp: 0 +wspawn: 0 +stalled: 0 +********************************** Fetch ********************************* +valid: 1 +PC: 800000d0 +wid: 0 +rd: -1 rs1: 13 rs2: 12 +is_lw: 0 +is_sw: 1 +fetch_stall_cycles: 2 +mem_stall_cycles: 3 +stall_warp: 0 +wspawn: 0 +stalled: 0 + + + +------------------------------------------------------ +CYCLE: 451 +Stalled Warps: +0 0 0 0 0 0 0 0 + +********************************** Writeback ********************************* +valid: 1 +PC: 800000c8 +wid: 0 +rd: 1 rs1: 11 rs2: 0 +is_lw: 0 +is_sw: 0 +fetch_stall_cycles: 0 +mem_stall_cycles: 0 +stall_warp: 0 +wspawn: 0 +stalled: 0 +********************************** LSU ********************************* +valid: 0 +PC: 0 +wid: 0 +rd: -1 rs1: -1 rs2: -1 +is_lw: 0 +is_sw: 0 +fetch_stall_cycles: 0 +mem_stall_cycles: 0 +stall_warp: 0 +wspawn: 0 +stalled: 0 +********************************** execute_unit ********************************* +valid: 1 +PC: 800000cc +wid: 0 +rd: 12 rs1: 0 rs2: -1 +is_lw: 0 +is_sw: 0 +fetch_stall_cycles: 0 +mem_stall_cycles: 0 +stall_warp: 0 +wspawn: 0 +stalled: 0 +********************************** scheduler ********************************* +valid: 0 +PC: 0 +wid: 0 +rd: -1 rs1: -1 rs2: -1 +is_lw: 0 +is_sw: 0 +fetch_stall_cycles: 0 +mem_stall_cycles: 0 +stall_warp: 0 +wspawn: 0 +stalled: 0 +********************************** Decode ********************************* +valid: 0 +PC: 0 +wid: 0 +rd: -1 rs1: -1 rs2: -1 +is_lw: 0 +is_sw: 0 +fetch_stall_cycles: 0 +mem_stall_cycles: 0 +stall_warp: 0 +wspawn: 0 +stalled: 0 +********************************** Fetch ********************************* +valid: 1 +PC: 800000d0 +wid: 0 +rd: -1 rs1: 13 rs2: 12 +is_lw: 0 +is_sw: 1 +fetch_stall_cycles: 1 +mem_stall_cycles: 3 +stall_warp: 0 +wspawn: 0 +stalled: 0 + + + +------------------------------------------------------ +CYCLE: 452 +Stalled Warps: +0 0 0 0 0 0 0 0 + +********************************** Writeback ********************************* +valid: 1 +PC: 800000cc +wid: 0 +rd: 12 rs1: 0 rs2: -1 +is_lw: 0 +is_sw: 0 +fetch_stall_cycles: 0 +mem_stall_cycles: 0 +stall_warp: 0 +wspawn: 0 +stalled: 0 +********************************** LSU ********************************* +valid: 0 +PC: 0 +wid: 0 +rd: -1 rs1: -1 rs2: -1 +is_lw: 0 +is_sw: 0 +fetch_stall_cycles: 0 +mem_stall_cycles: 0 +stall_warp: 0 +wspawn: 0 +stalled: 0 +********************************** execute_unit ********************************* +valid: 0 +PC: 0 +wid: 0 +rd: -1 rs1: -1 rs2: -1 +is_lw: 0 +is_sw: 0 +fetch_stall_cycles: 0 +mem_stall_cycles: 0 +stall_warp: 0 +wspawn: 0 +stalled: 0 +********************************** scheduler ********************************* +valid: 0 +PC: 0 +wid: 0 +rd: -1 rs1: -1 rs2: -1 +is_lw: 0 +is_sw: 0 +fetch_stall_cycles: 0 +mem_stall_cycles: 0 +stall_warp: 0 +wspawn: 0 +stalled: 0 +********************************** Decode ********************************* +valid: 0 +PC: 0 +wid: 0 +rd: -1 rs1: -1 rs2: -1 +is_lw: 0 +is_sw: 0 +fetch_stall_cycles: 0 +mem_stall_cycles: 0 +stall_warp: 0 +wspawn: 0 +stalled: 0 +********************************** Fetch ********************************* +valid: 1 +PC: 800000d0 +wid: 0 +rd: -1 rs1: 13 rs2: 12 +is_lw: 0 +is_sw: 1 +fetch_stall_cycles: 0 +mem_stall_cycles: 3 +stall_warp: 0 +wspawn: 0 +stalled: 0 + + + +------------------------------------------------------ +CYCLE: 453 +Stalled Warps: +0 0 0 0 0 0 0 0 + +********************************** Writeback ********************************* +valid: 0 +PC: 0 +wid: 0 +rd: -1 rs1: -1 rs2: -1 +is_lw: 0 +is_sw: 0 +fetch_stall_cycles: 0 +mem_stall_cycles: 0 +stall_warp: 0 +wspawn: 0 +stalled: 0 +********************************** LSU ********************************* +valid: 0 +PC: 0 +wid: 0 +rd: -1 rs1: -1 rs2: -1 +is_lw: 0 +is_sw: 0 +fetch_stall_cycles: 0 +mem_stall_cycles: 0 +stall_warp: 0 +wspawn: 0 +stalled: 0 +********************************** execute_unit ********************************* +valid: 0 +PC: 0 +wid: 0 +rd: -1 rs1: -1 rs2: -1 +is_lw: 0 +is_sw: 0 +fetch_stall_cycles: 0 +mem_stall_cycles: 0 +stall_warp: 0 +wspawn: 0 +stalled: 0 +********************************** scheduler ********************************* +valid: 0 +PC: 0 +wid: 0 +rd: -1 rs1: -1 rs2: -1 +is_lw: 0 +is_sw: 0 +fetch_stall_cycles: 0 +mem_stall_cycles: 0 +stall_warp: 0 +wspawn: 0 +stalled: 0 +********************************** Decode ********************************* +valid: 1 +PC: 800000d0 +wid: 0 +rd: -1 rs1: 13 rs2: 12 +is_lw: 0 +is_sw: 1 +fetch_stall_cycles: 0 +mem_stall_cycles: 3 +stall_warp: 0 +wspawn: 0 +stalled: 0 +DEBUG ../core.cpp:386: Core step stepping warp 0[1] +DEBUG ../core.cpp:683: in step pc=0x800000d4 +help: in PC: 800000d4 +CUrrent CODE: 613 +DEBUG ../core.cpp:703: Fetched at 0x800000d4 +DEBUG ../core.cpp:704: 0x800000d4: i_type; +DEBUG ../instruction.cpp:350: Begin instruction execute. +DEBUG ../instruction.cpp:2117: End instruction execute. +DEBUG ../core.cpp:717: Register state: + %r 0: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r 1: 800008c0 800008bc 800008bc 800008bc 00000000 00000000 00000000 00000000 (0) + %r 2: 6fffeff0 6fffebf4 6fffe7f8 6fffe3fc 00000000 00000000 00000000 00000000 (0) + %r 3: 80001808 80001808 80001808 80001808 00000000 00000000 00000000 00000000 (0) + %r 4: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r 5: 00000002 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r 6: 0000000f 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r 7: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r 8: 6ffff000 6fffec04 6fffe808 6fffe40c 00000000 00000000 00000000 00000000 (0) + %r 9: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r10: 0000000a 00000001 00000001 00000001 00000000 00000000 00000000 00000000 (0) + %r11: 80000924 00000400 00000800 00000c00 00000000 00000000 00000000 00000000 (0) + %r12: 00000000 00000004 00000008 0000000c 00000000 00000000 00000000 00000000 (0) + %r13: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r14: 00000001 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r15: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r16: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r17: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r18: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r19: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r20: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r21: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r22: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r23: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r24: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r25: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r26: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r27: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r28: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r29: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r30: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r31: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) +DEBUG ../core.cpp:726: Thread mask: + 1 0 0 0 0 0 0 0 + + +DEBUG ../core.cpp:388: Now 1 active threads in 0 +********************************** Fetch ********************************* +valid: 1 +PC: 800000d4 +wid: 0 +rd: 12 rs1: 0 rs2: -1 +is_lw: 0 +is_sw: 0 +fetch_stall_cycles: 0 +mem_stall_cycles: 0 +stall_warp: 0 +wspawn: 0 +stalled: 0 + + + +------------------------------------------------------ +CYCLE: 454 +Stalled Warps: +0 0 0 0 0 0 0 0 + +********************************** Writeback ********************************* +valid: 0 +PC: 0 +wid: 0 +rd: -1 rs1: -1 rs2: -1 +is_lw: 0 +is_sw: 0 +fetch_stall_cycles: 0 +mem_stall_cycles: 0 +stall_warp: 0 +wspawn: 0 +stalled: 0 +********************************** LSU ********************************* +valid: 0 +PC: 0 +wid: 0 +rd: -1 rs1: -1 rs2: -1 +is_lw: 0 +is_sw: 0 +fetch_stall_cycles: 0 +mem_stall_cycles: 0 +stall_warp: 0 +wspawn: 0 +stalled: 0 +********************************** execute_unit ********************************* +valid: 0 +PC: 0 +wid: 0 +rd: -1 rs1: -1 rs2: -1 +is_lw: 0 +is_sw: 0 +fetch_stall_cycles: 0 +mem_stall_cycles: 0 +stall_warp: 0 +wspawn: 0 +stalled: 0 +********************************** scheduler ********************************* +valid: 1 +PC: 800000d0 +wid: 0 +rd: -1 rs1: 13 rs2: 12 +is_lw: 0 +is_sw: 1 +fetch_stall_cycles: 0 +mem_stall_cycles: 3 +stall_warp: 0 +wspawn: 0 +stalled: 0 +********************************** Decode ********************************* +valid: 1 +PC: 800000d4 +wid: 0 +rd: 12 rs1: 0 rs2: -1 +is_lw: 0 +is_sw: 0 +fetch_stall_cycles: 0 +mem_stall_cycles: 0 +stall_warp: 0 +wspawn: 0 +stalled: 0 +DEBUG ../core.cpp:386: Core step stepping warp 0[1] +DEBUG ../core.cpp:683: in step pc=0x800000d8 +help: in PC: 800000d8 +CUrrent CODE: 2c6a023 +DEBUG ../core.cpp:703: Fetched at 0x800000d8 +DEBUG ../core.cpp:704: 0x800000d8: store; +DEBUG ../instruction.cpp:350: Begin instruction execute. +STORE MEM ADDRESS: 0 + 20 +DEBUG ../instruction.cpp:2117: End instruction execute. +DEBUG ../core.cpp:717: Register state: + %r 0: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r 1: 800008c0 800008bc 800008bc 800008bc 00000000 00000000 00000000 00000000 (0) + %r 2: 6fffeff0 6fffebf4 6fffe7f8 6fffe3fc 00000000 00000000 00000000 00000000 (0) + %r 3: 80001808 80001808 80001808 80001808 00000000 00000000 00000000 00000000 (0) + %r 4: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r 5: 00000002 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r 6: 0000000f 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r 7: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r 8: 6ffff000 6fffec04 6fffe808 6fffe40c 00000000 00000000 00000000 00000000 (0) + %r 9: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r10: 0000000a 00000001 00000001 00000001 00000000 00000000 00000000 00000000 (0) + %r11: 80000924 00000400 00000800 00000c00 00000000 00000000 00000000 00000000 (0) + %r12: 00000000 00000004 00000008 0000000c 00000000 00000000 00000000 00000000 (0) + %r13: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r14: 00000001 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r15: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r16: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r17: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r18: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r19: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r20: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r21: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r22: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r23: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r24: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r25: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r26: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r27: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r28: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r29: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r30: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r31: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) +DEBUG ../core.cpp:726: Thread mask: + 1 0 0 0 0 0 0 0 + + +DEBUG ../core.cpp:388: Now 1 active threads in 0 +********************************** Fetch ********************************* +valid: 1 +PC: 800000d8 +wid: 0 +rd: -1 rs1: 13 rs2: 12 +is_lw: 0 +is_sw: 1 +fetch_stall_cycles: 0 +mem_stall_cycles: 0 +stall_warp: 0 +wspawn: 0 +stalled: 0 + + + +------------------------------------------------------ +CYCLE: 455 +Stalled Warps: +0 0 0 0 0 0 0 0 + +********************************** Writeback ********************************* +valid: 0 +PC: 0 +wid: 0 +rd: -1 rs1: -1 rs2: -1 +is_lw: 0 +is_sw: 0 +fetch_stall_cycles: 0 +mem_stall_cycles: 0 +stall_warp: 0 +wspawn: 0 +stalled: 0 +********************************** LSU ********************************* +valid: 1 +PC: 800000d0 +wid: 0 +rd: -1 rs1: 13 rs2: 12 +is_lw: 0 +is_sw: 1 +fetch_stall_cycles: 0 +mem_stall_cycles: 2 +stall_warp: 0 +wspawn: 0 +stalled: 0 +********************************** execute_unit ********************************* +valid: 0 +PC: 0 +wid: 0 +rd: -1 rs1: -1 rs2: -1 +is_lw: 0 +is_sw: 0 +fetch_stall_cycles: 0 +mem_stall_cycles: 0 +stall_warp: 0 +wspawn: 0 +stalled: 0 +********************************** scheduler ********************************* +valid: 1 +PC: 800000d4 +wid: 0 +rd: 12 rs1: 0 rs2: -1 +is_lw: 0 +is_sw: 0 +fetch_stall_cycles: 0 +mem_stall_cycles: 0 +stall_warp: 0 +wspawn: 0 +stalled: 0 +********************************** Decode ********************************* +valid: 1 +PC: 800000d8 +wid: 0 +rd: -1 rs1: 13 rs2: 12 +is_lw: 0 +is_sw: 1 +fetch_stall_cycles: 0 +mem_stall_cycles: 0 +stall_warp: 0 +wspawn: 0 +stalled: 0 +DEBUG ../core.cpp:386: Core step stepping warp 0[1] +DEBUG ../core.cpp:683: in step pc=0x800000dc +help: in PC: 800000dc +CUrrent CODE: 1206e007 +Entered here: instr type = vector7 +DEBUG ../enc.cpp:275: vector load instr +DEBUG ../core.cpp:703: Fetched at 0x800000dc +DEBUG ../core.cpp:704: 0x800000dc: vl; +DEBUG ../instruction.cpp:350: Begin instruction execute. +DEBUG ../instruction.cpp:2035: Executing vector load +DEBUG ../instruction.cpp:2037: lmul: 1 VLEN:96sew: 32 +DEBUG ../instruction.cpp:2038: src: 13 0 +DEBUG ../instruction.cpp:2039: dest0 +DEBUG ../instruction.cpp:2040: width6 +DEBUG ../instruction.cpp:2048: Data read 1 +DEBUG ../instruction.cpp:2048: Data read 0 +DEBUG ../instruction.cpp:2060: Vector Register state after addition: +reg[0][0] = 1 +reg[0][1] = 0 +reg[0][2] = 0 +reg[1][0] = 10 +reg[1][1] = 10 +reg[1][2] = 0 +reg[2][0] = 0 +reg[2][1] = 0 +reg[2][2] = 0 +reg[3][0] = 0 +reg[3][1] = 0 +reg[3][2] = 0 +reg[4][0] = 0 +reg[4][1] = 0 +reg[4][2] = 0 +reg[5][0] = 0 +reg[5][1] = 0 +reg[5][2] = 0 +reg[6][0] = 0 +reg[6][1] = 0 +reg[6][2] = 0 +reg[7][0] = 0 +reg[7][1] = 0 +reg[7][2] = 0 +reg[8][0] = 0 +reg[8][1] = 0 +reg[8][2] = 0 +reg[9][0] = 0 +reg[9][1] = 0 +reg[9][2] = 0 +reg[10][0] = 0 +reg[10][1] = 0 +reg[10][2] = 0 +reg[11][0] = 0 +reg[11][1] = 0 +reg[11][2] = 0 +reg[12][0] = 0 +reg[12][1] = 0 +reg[12][2] = 0 +reg[13][0] = 0 +reg[13][1] = 0 +reg[13][2] = 0 +reg[14][0] = 0 +reg[14][1] = 0 +reg[14][2] = 0 +reg[15][0] = 0 +reg[15][1] = 0 +reg[15][2] = 0 +reg[16][0] = 0 +reg[16][1] = 0 +reg[16][2] = 0 +reg[17][0] = 0 +reg[17][1] = 0 +reg[17][2] = 0 +reg[18][0] = 0 +reg[18][1] = 0 +reg[18][2] = 0 +reg[19][0] = 0 +reg[19][1] = 0 +reg[19][2] = 0 +reg[20][0] = 0 +reg[20][1] = 0 +reg[20][2] = 0 +reg[21][0] = 0 +reg[21][1] = 0 +reg[21][2] = 0 +reg[22][0] = 0 +reg[22][1] = 0 +reg[22][2] = 0 +reg[23][0] = 0 +reg[23][1] = 0 +reg[23][2] = 0 +reg[24][0] = 0 +reg[24][1] = 0 +reg[24][2] = 0 +reg[25][0] = 0 +reg[25][1] = 0 +reg[25][2] = 0 +reg[26][0] = 0 +reg[26][1] = 0 +reg[26][2] = 0 +reg[27][0] = 0 +reg[27][1] = 0 +reg[27][2] = 0 +reg[28][0] = 0 +reg[28][1] = 0 +reg[28][2] = 0 +reg[29][0] = 0 +reg[29][1] = 0 +reg[29][2] = 0 +reg[30][0] = 0 +reg[30][1] = 0 +reg[30][2] = 0 +reg[31][0] = 0 +reg[31][1] = 0 +reg[31][2] = 0 +DEBUG ../instruction.cpp:2117: End instruction execute. +DEBUG ../core.cpp:717: Register state: + %r 0: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r 1: 800008c0 800008bc 800008bc 800008bc 00000000 00000000 00000000 00000000 (0) + %r 2: 6fffeff0 6fffebf4 6fffe7f8 6fffe3fc 00000000 00000000 00000000 00000000 (0) + %r 3: 80001808 80001808 80001808 80001808 00000000 00000000 00000000 00000000 (0) + %r 4: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r 5: 00000002 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r 6: 0000000f 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r 7: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r 8: 6ffff000 6fffec04 6fffe808 6fffe40c 00000000 00000000 00000000 00000000 (0) + %r 9: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r10: 0000000a 00000001 00000001 00000001 00000000 00000000 00000000 00000000 (0) + %r11: 80000924 00000400 00000800 00000c00 00000000 00000000 00000000 00000000 (0) + %r12: 00000000 00000004 00000008 0000000c 00000000 00000000 00000000 00000000 (0) + %r13: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r14: 00000001 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r15: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r16: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r17: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r18: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r19: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r20: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r21: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r22: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r23: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r24: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r25: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r26: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r27: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r28: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r29: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r30: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r31: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) +DEBUG ../core.cpp:726: Thread mask: + 1 0 0 0 0 0 0 0 + + +DEBUG ../core.cpp:388: Now 1 active threads in 0 +********************************** Fetch ********************************* +valid: 1 +PC: 800000dc +wid: 0 +rd: 0 rs1: 13 rs2: 0 +is_lw: 0 +is_sw: 0 +fetch_stall_cycles: 0 +mem_stall_cycles: 0 +stall_warp: 0 +wspawn: 0 +stalled: 0 + + + +------------------------------------------------------ +CYCLE: 456 +Stalled Warps: +0 0 0 0 0 0 0 0 + +********************************** Writeback ********************************* +valid: 0 +PC: 0 +wid: 0 +rd: -1 rs1: -1 rs2: -1 +is_lw: 0 +is_sw: 0 +fetch_stall_cycles: 0 +mem_stall_cycles: 0 +stall_warp: 0 +wspawn: 0 +stalled: 0 +********************************** LSU ********************************* +valid: 0 +PC: 0 +wid: 0 +rd: -1 rs1: -1 rs2: -1 +is_lw: 0 +is_sw: 0 +fetch_stall_cycles: 0 +mem_stall_cycles: 0 +stall_warp: 0 +wspawn: 0 +stalled: 0 +********************************** execute_unit ********************************* +valid: 1 +PC: 800000d4 +wid: 0 +rd: 12 rs1: 0 rs2: -1 +is_lw: 0 +is_sw: 0 +fetch_stall_cycles: 0 +mem_stall_cycles: 0 +stall_warp: 0 +wspawn: 0 +stalled: 0 +********************************** scheduler ********************************* +valid: 1 +PC: 800000d8 +wid: 0 +rd: -1 rs1: 13 rs2: 12 +is_lw: 0 +is_sw: 1 +fetch_stall_cycles: 0 +mem_stall_cycles: 0 +stall_warp: 0 +wspawn: 0 +stalled: 0 +********************************** Decode ********************************* +valid: 1 +PC: 800000dc +wid: 0 +rd: 0 rs1: 13 rs2: 0 +is_lw: 0 +is_sw: 0 +fetch_stall_cycles: 0 +mem_stall_cycles: 0 +stall_warp: 0 +wspawn: 0 +stalled: 0 +DEBUG ../core.cpp:386: Core step stepping warp 0[1] +DEBUG ../core.cpp:683: in step pc=0x800000e0 +help: in PC: 800000e0 +CUrrent CODE: 6a01a057 +Entered here: instr type = vector87 +Entered here: instr type = vector +DEBUG ../core.cpp:703: Fetched at 0x800000e0 +DEBUG ../core.cpp:704: 0x800000e0: vsetvl; +DEBUG ../instruction.cpp:350: Begin instruction execute. +DEBUG ../instruction.cpp:1091: VSET_ARITH +DEBUG ../instruction.cpp:1632: vmor +Comparing 0 + 1 = 1 +Comparing 0 + 0 = 0 +VLMAX: 3 +DEBUG ../instruction.cpp:2117: End instruction execute. +DEBUG ../core.cpp:717: Register state: + %r 0: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r 1: 800008c0 800008bc 800008bc 800008bc 00000000 00000000 00000000 00000000 (0) + %r 2: 6fffeff0 6fffebf4 6fffe7f8 6fffe3fc 00000000 00000000 00000000 00000000 (0) + %r 3: 80001808 80001808 80001808 80001808 00000000 00000000 00000000 00000000 (0) + %r 4: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r 5: 00000002 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r 6: 0000000f 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r 7: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r 8: 6ffff000 6fffec04 6fffe808 6fffe40c 00000000 00000000 00000000 00000000 (0) + %r 9: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r10: 0000000a 00000001 00000001 00000001 00000000 00000000 00000000 00000000 (0) + %r11: 80000924 00000400 00000800 00000c00 00000000 00000000 00000000 00000000 (0) + %r12: 00000000 00000004 00000008 0000000c 00000000 00000000 00000000 00000000 (0) + %r13: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r14: 00000001 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r15: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r16: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r17: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r18: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r19: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r20: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r21: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r22: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r23: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r24: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r25: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r26: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r27: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r28: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r29: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r30: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r31: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) +DEBUG ../core.cpp:726: Thread mask: + 1 0 0 0 0 0 0 0 + + +DEBUG ../core.cpp:388: Now 1 active threads in 0 +********************************** Fetch ********************************* +valid: 1 +PC: 800000e0 +wid: 0 +rd: 0 rs1: 3 rs2: 0 +is_lw: 0 +is_sw: 0 +fetch_stall_cycles: 3 +mem_stall_cycles: 0 +stall_warp: 0 +wspawn: 0 +stalled: 0 + + + +------------------------------------------------------ +CYCLE: 457 +Stalled Warps: +0 0 0 0 0 0 0 0 + +********************************** Writeback ********************************* +valid: 1 +PC: 800000d4 +wid: 0 +rd: 12 rs1: 0 rs2: -1 +is_lw: 0 +is_sw: 0 +fetch_stall_cycles: 0 +mem_stall_cycles: 0 +stall_warp: 0 +wspawn: 0 +stalled: 0 +********************************** LSU ********************************* +valid: 0 +PC: 0 +wid: 0 +rd: -1 rs1: -1 rs2: -1 +is_lw: 0 +is_sw: 0 +fetch_stall_cycles: 0 +mem_stall_cycles: 0 +stall_warp: 0 +wspawn: 0 +stalled: 0 +********************************** execute_unit ********************************* +valid: 0 +PC: 0 +wid: 0 +rd: -1 rs1: -1 rs2: -1 +is_lw: 0 +is_sw: 0 +fetch_stall_cycles: 0 +mem_stall_cycles: 0 +stall_warp: 0 +wspawn: 0 +stalled: 0 +********************************** scheduler ********************************* +valid: 1 +PC: 800000d8 +wid: 0 +rd: -1 rs1: 13 rs2: 12 +is_lw: 0 +is_sw: 1 +fetch_stall_cycles: 0 +mem_stall_cycles: 0 +stall_warp: 0 +wspawn: 0 +stalled: 1 +********************************** Decode ********************************* +valid: 1 +PC: 800000dc +wid: 0 +rd: 0 rs1: 13 rs2: 0 +is_lw: 0 +is_sw: 0 +fetch_stall_cycles: 0 +mem_stall_cycles: 0 +stall_warp: 0 +wspawn: 0 +stalled: 0 +********************************** Fetch ********************************* +valid: 1 +PC: 800000e0 +wid: 0 +rd: 0 rs1: 3 rs2: 0 +is_lw: 0 +is_sw: 0 +fetch_stall_cycles: 2 +mem_stall_cycles: 0 +stall_warp: 0 +wspawn: 0 +stalled: 0 + + + +------------------------------------------------------ +CYCLE: 458 +Stalled Warps: +0 0 0 0 0 0 0 0 + +********************************** Writeback ********************************* +valid: 0 +PC: 0 +wid: 0 +rd: -1 rs1: -1 rs2: -1 +is_lw: 0 +is_sw: 0 +fetch_stall_cycles: 0 +mem_stall_cycles: 0 +stall_warp: 0 +wspawn: 0 +stalled: 0 +********************************** LSU ********************************* +valid: 1 +PC: 800000d8 +wid: 0 +rd: -1 rs1: 13 rs2: 12 +is_lw: 0 +is_sw: 1 +fetch_stall_cycles: 0 +mem_stall_cycles: 0 +stall_warp: 0 +wspawn: 0 +stalled: 0 +********************************** execute_unit ********************************* +valid: 0 +PC: 0 +wid: 0 +rd: -1 rs1: -1 rs2: -1 +is_lw: 0 +is_sw: 0 +fetch_stall_cycles: 0 +mem_stall_cycles: 0 +stall_warp: 0 +wspawn: 0 +stalled: 0 +********************************** scheduler ********************************* +valid: 1 +PC: 800000dc +wid: 0 +rd: 0 rs1: 13 rs2: 0 +is_lw: 0 +is_sw: 0 +fetch_stall_cycles: 0 +mem_stall_cycles: 0 +stall_warp: 0 +wspawn: 0 +stalled: 0 +********************************** Decode ********************************* +valid: 0 +PC: 0 +wid: 0 +rd: -1 rs1: -1 rs2: -1 +is_lw: 0 +is_sw: 0 +fetch_stall_cycles: 0 +mem_stall_cycles: 0 +stall_warp: 0 +wspawn: 0 +stalled: 0 +********************************** Fetch ********************************* +valid: 1 +PC: 800000e0 +wid: 0 +rd: 0 rs1: 3 rs2: 0 +is_lw: 0 +is_sw: 0 +fetch_stall_cycles: 1 +mem_stall_cycles: 0 +stall_warp: 0 +wspawn: 0 +stalled: 0 + + + +------------------------------------------------------ +CYCLE: 459 +Stalled Warps: +0 0 0 0 0 0 0 0 + +********************************** Writeback ********************************* +valid: 0 +PC: 0 +wid: 0 +rd: -1 rs1: -1 rs2: -1 +is_lw: 0 +is_sw: 0 +fetch_stall_cycles: 0 +mem_stall_cycles: 0 +stall_warp: 0 +wspawn: 0 +stalled: 0 +********************************** LSU ********************************* +valid: 0 +PC: 0 +wid: 0 +rd: -1 rs1: -1 rs2: -1 +is_lw: 0 +is_sw: 0 +fetch_stall_cycles: 0 +mem_stall_cycles: 0 +stall_warp: 0 +wspawn: 0 +stalled: 0 +********************************** execute_unit ********************************* +valid: 1 +PC: 800000dc +wid: 0 +rd: 0 rs1: 13 rs2: 0 +is_lw: 0 +is_sw: 0 +fetch_stall_cycles: 0 +mem_stall_cycles: 0 +stall_warp: 0 +wspawn: 0 +stalled: 0 +********************************** scheduler ********************************* +valid: 0 +PC: 0 +wid: 0 +rd: -1 rs1: -1 rs2: -1 +is_lw: 0 +is_sw: 0 +fetch_stall_cycles: 0 +mem_stall_cycles: 0 +stall_warp: 0 +wspawn: 0 +stalled: 0 +********************************** Decode ********************************* +valid: 0 +PC: 0 +wid: 0 +rd: -1 rs1: -1 rs2: -1 +is_lw: 0 +is_sw: 0 +fetch_stall_cycles: 0 +mem_stall_cycles: 0 +stall_warp: 0 +wspawn: 0 +stalled: 0 +********************************** Fetch ********************************* +valid: 1 +PC: 800000e0 +wid: 0 +rd: 0 rs1: 3 rs2: 0 +is_lw: 0 +is_sw: 0 +fetch_stall_cycles: 0 +mem_stall_cycles: 0 +stall_warp: 0 +wspawn: 0 +stalled: 0 + + + +------------------------------------------------------ +CYCLE: 460 +Stalled Warps: +0 0 0 0 0 0 0 0 + +********************************** Writeback ********************************* +valid: 0 +PC: 0 +wid: 0 +rd: -1 rs1: -1 rs2: -1 +is_lw: 0 +is_sw: 0 +fetch_stall_cycles: 0 +mem_stall_cycles: 0 +stall_warp: 0 +wspawn: 0 +stalled: 0 +********************************** LSU ********************************* +valid: 0 +PC: 0 +wid: 0 +rd: -1 rs1: -1 rs2: -1 +is_lw: 0 +is_sw: 0 +fetch_stall_cycles: 0 +mem_stall_cycles: 0 +stall_warp: 0 +wspawn: 0 +stalled: 0 +********************************** execute_unit ********************************* +valid: 0 +PC: 0 +wid: 0 +rd: -1 rs1: -1 rs2: -1 +is_lw: 0 +is_sw: 0 +fetch_stall_cycles: 0 +mem_stall_cycles: 0 +stall_warp: 0 +wspawn: 0 +stalled: 0 +********************************** scheduler ********************************* +valid: 0 +PC: 0 +wid: 0 +rd: -1 rs1: -1 rs2: -1 +is_lw: 0 +is_sw: 0 +fetch_stall_cycles: 0 +mem_stall_cycles: 0 +stall_warp: 0 +wspawn: 0 +stalled: 0 +********************************** Decode ********************************* +valid: 1 +PC: 800000e0 +wid: 0 +rd: 0 rs1: 3 rs2: 0 +is_lw: 0 +is_sw: 0 +fetch_stall_cycles: 0 +mem_stall_cycles: 0 +stall_warp: 0 +wspawn: 0 +stalled: 0 +DEBUG ../core.cpp:386: Core step stepping warp 0[1] +DEBUG ../core.cpp:683: in step pc=0x800000e4 +help: in PC: 800000e4 +CUrrent CODE: 1080d7 +Entered here: instr type = vector87 +Entered here: instr type = vector +DEBUG ../core.cpp:703: Fetched at 0x800000e4 +DEBUG ../core.cpp:704: 0x800000e4: vsetvl; +DEBUG ../instruction.cpp:350: Begin instruction execute. +DEBUG ../instruction.cpp:1091: VSET_ARITH +DEBUG ../instruction.cpp:1101: Addition 1 1 Dest:1 +Doing 32 bit vector addition +Adding 10 + 10 = 20 +DEBUG ../instruction.cpp:1163: Vector Register state after addition: +reg[0][0] = 1 +reg[0][1] = 0 +reg[0][2] = 0 +reg[1][0] = 20 +reg[1][1] = 10 +reg[1][2] = 0 +reg[2][0] = 0 +reg[2][1] = 0 +reg[2][2] = 0 +reg[3][0] = 0 +reg[3][1] = 0 +reg[3][2] = 0 +reg[4][0] = 0 +reg[4][1] = 0 +reg[4][2] = 0 +reg[5][0] = 0 +reg[5][1] = 0 +reg[5][2] = 0 +reg[6][0] = 0 +reg[6][1] = 0 +reg[6][2] = 0 +reg[7][0] = 0 +reg[7][1] = 0 +reg[7][2] = 0 +reg[8][0] = 0 +reg[8][1] = 0 +reg[8][2] = 0 +reg[9][0] = 0 +reg[9][1] = 0 +reg[9][2] = 0 +reg[10][0] = 0 +reg[10][1] = 0 +reg[10][2] = 0 +reg[11][0] = 0 +reg[11][1] = 0 +reg[11][2] = 0 +reg[12][0] = 0 +reg[12][1] = 0 +reg[12][2] = 0 +reg[13][0] = 0 +reg[13][1] = 0 +reg[13][2] = 0 +reg[14][0] = 0 +reg[14][1] = 0 +reg[14][2] = 0 +reg[15][0] = 0 +reg[15][1] = 0 +reg[15][2] = 0 +reg[16][0] = 0 +reg[16][1] = 0 +reg[16][2] = 0 +reg[17][0] = 0 +reg[17][1] = 0 +reg[17][2] = 0 +reg[18][0] = 0 +reg[18][1] = 0 +reg[18][2] = 0 +reg[19][0] = 0 +reg[19][1] = 0 +reg[19][2] = 0 +reg[20][0] = 0 +reg[20][1] = 0 +reg[20][2] = 0 +reg[21][0] = 0 +reg[21][1] = 0 +reg[21][2] = 0 +reg[22][0] = 0 +reg[22][1] = 0 +reg[22][2] = 0 +reg[23][0] = 0 +reg[23][1] = 0 +reg[23][2] = 0 +reg[24][0] = 0 +reg[24][1] = 0 +reg[24][2] = 0 +reg[25][0] = 0 +reg[25][1] = 0 +reg[25][2] = 0 +reg[26][0] = 0 +reg[26][1] = 0 +reg[26][2] = 0 +reg[27][0] = 0 +reg[27][1] = 0 +reg[27][2] = 0 +reg[28][0] = 0 +reg[28][1] = 0 +reg[28][2] = 0 +reg[29][0] = 0 +reg[29][1] = 0 +reg[29][2] = 0 +reg[30][0] = 0 +reg[30][1] = 0 +reg[30][2] = 0 +reg[31][0] = 0 +reg[31][1] = 0 +reg[31][2] = 0 +DEBUG ../instruction.cpp:2117: End instruction execute. +DEBUG ../core.cpp:717: Register state: + %r 0: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r 1: 800008c0 800008bc 800008bc 800008bc 00000000 00000000 00000000 00000000 (0) + %r 2: 6fffeff0 6fffebf4 6fffe7f8 6fffe3fc 00000000 00000000 00000000 00000000 (0) + %r 3: 80001808 80001808 80001808 80001808 00000000 00000000 00000000 00000000 (0) + %r 4: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r 5: 00000002 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r 6: 0000000f 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r 7: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r 8: 6ffff000 6fffec04 6fffe808 6fffe40c 00000000 00000000 00000000 00000000 (0) + %r 9: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r10: 0000000a 00000001 00000001 00000001 00000000 00000000 00000000 00000000 (0) + %r11: 80000924 00000400 00000800 00000c00 00000000 00000000 00000000 00000000 (0) + %r12: 00000000 00000004 00000008 0000000c 00000000 00000000 00000000 00000000 (0) + %r13: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r14: 00000001 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r15: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r16: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r17: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r18: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r19: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r20: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r21: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r22: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r23: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r24: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r25: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r26: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r27: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r28: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r29: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r30: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r31: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) +DEBUG ../core.cpp:726: Thread mask: + 1 0 0 0 0 0 0 0 + + +DEBUG ../core.cpp:388: Now 1 active threads in 0 +********************************** Fetch ********************************* +valid: 1 +PC: 800000e4 +wid: 0 +rd: 1 rs1: 1 rs2: 1 +is_lw: 0 +is_sw: 0 +fetch_stall_cycles: 0 +mem_stall_cycles: 0 +stall_warp: 0 +wspawn: 0 +stalled: 0 + + + +------------------------------------------------------ +CYCLE: 461 +Stalled Warps: +0 0 0 0 0 0 0 0 + +********************************** Writeback ********************************* +valid: 0 +PC: 0 +wid: 0 +rd: -1 rs1: -1 rs2: -1 +is_lw: 0 +is_sw: 0 +fetch_stall_cycles: 0 +mem_stall_cycles: 0 +stall_warp: 0 +wspawn: 0 +stalled: 0 +********************************** LSU ********************************* +valid: 0 +PC: 0 +wid: 0 +rd: -1 rs1: -1 rs2: -1 +is_lw: 0 +is_sw: 0 +fetch_stall_cycles: 0 +mem_stall_cycles: 0 +stall_warp: 0 +wspawn: 0 +stalled: 0 +********************************** execute_unit ********************************* +valid: 0 +PC: 0 +wid: 0 +rd: -1 rs1: -1 rs2: -1 +is_lw: 0 +is_sw: 0 +fetch_stall_cycles: 0 +mem_stall_cycles: 0 +stall_warp: 0 +wspawn: 0 +stalled: 0 +********************************** scheduler ********************************* +valid: 1 +PC: 800000e0 +wid: 0 +rd: 0 rs1: 3 rs2: 0 +is_lw: 0 +is_sw: 0 +fetch_stall_cycles: 0 +mem_stall_cycles: 0 +stall_warp: 0 +wspawn: 0 +stalled: 0 +********************************** Decode ********************************* +valid: 1 +PC: 800000e4 +wid: 0 +rd: 1 rs1: 1 rs2: 1 +is_lw: 0 +is_sw: 0 +fetch_stall_cycles: 0 +mem_stall_cycles: 0 +stall_warp: 0 +wspawn: 0 +stalled: 0 +DEBUG ../core.cpp:386: Core step stepping warp 0[1] +DEBUG ../core.cpp:683: in step pc=0x800000e8 +help: in PC: 800000e8 +CUrrent CODE: 205e0a7 +Entered here: instr type = vector39 +DEBUG ../core.cpp:703: Fetched at 0x800000e8 +DEBUG ../core.cpp:704: 0x800000e8: vs; +DEBUG ../instruction.cpp:350: Begin instruction execute. +STORE MEM ADDRESS: 80000924 +DEBUG ../instruction.cpp:2100: store: 2147485988 value:20 +STORE MEM ADDRESS: 80000944 +DEBUG ../instruction.cpp:2100: store: 2147486020 value:10 +DEBUG ../instruction.cpp:2117: End instruction execute. +DEBUG ../core.cpp:717: Register state: + %r 0: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r 1: 800008c0 800008bc 800008bc 800008bc 00000000 00000000 00000000 00000000 (0) + %r 2: 6fffeff0 6fffebf4 6fffe7f8 6fffe3fc 00000000 00000000 00000000 00000000 (0) + %r 3: 80001808 80001808 80001808 80001808 00000000 00000000 00000000 00000000 (0) + %r 4: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r 5: 00000002 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r 6: 0000000f 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r 7: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r 8: 6ffff000 6fffec04 6fffe808 6fffe40c 00000000 00000000 00000000 00000000 (0) + %r 9: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r10: 0000000a 00000001 00000001 00000001 00000000 00000000 00000000 00000000 (0) + %r11: 80000924 00000400 00000800 00000c00 00000000 00000000 00000000 00000000 (0) + %r12: 00000000 00000004 00000008 0000000c 00000000 00000000 00000000 00000000 (0) + %r13: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r14: 00000001 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r15: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r16: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r17: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r18: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r19: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r20: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r21: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r22: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r23: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r24: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r25: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r26: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r27: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r28: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r29: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r30: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r31: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) +DEBUG ../core.cpp:726: Thread mask: + 1 0 0 0 0 0 0 0 + + +DEBUG ../core.cpp:388: Now 1 active threads in 0 +********************************** Fetch ********************************* +valid: 1 +PC: 800000e8 +wid: 0 +rd: 1 rs1: 11 rs2: 0 +is_lw: 0 +is_sw: 0 +fetch_stall_cycles: 0 +mem_stall_cycles: 0 +stall_warp: 0 +wspawn: 0 +stalled: 0 + + + +------------------------------------------------------ +CYCLE: 462 +Stalled Warps: +0 0 0 0 0 0 0 0 + +********************************** Writeback ********************************* +valid: 0 +PC: 0 +wid: 0 +rd: -1 rs1: -1 rs2: -1 +is_lw: 0 +is_sw: 0 +fetch_stall_cycles: 0 +mem_stall_cycles: 0 +stall_warp: 0 +wspawn: 0 +stalled: 0 +********************************** LSU ********************************* +valid: 0 +PC: 0 +wid: 0 +rd: -1 rs1: -1 rs2: -1 +is_lw: 0 +is_sw: 0 +fetch_stall_cycles: 0 +mem_stall_cycles: 0 +stall_warp: 0 +wspawn: 0 +stalled: 0 +********************************** execute_unit ********************************* +valid: 1 +PC: 800000e0 +wid: 0 +rd: 0 rs1: 3 rs2: 0 +is_lw: 0 +is_sw: 0 +fetch_stall_cycles: 0 +mem_stall_cycles: 0 +stall_warp: 0 +wspawn: 0 +stalled: 0 +********************************** scheduler ********************************* +valid: 1 +PC: 800000e4 +wid: 0 +rd: 1 rs1: 1 rs2: 1 +is_lw: 0 +is_sw: 0 +fetch_stall_cycles: 0 +mem_stall_cycles: 0 +stall_warp: 0 +wspawn: 0 +stalled: 0 +********************************** Decode ********************************* +valid: 1 +PC: 800000e8 +wid: 0 +rd: 1 rs1: 11 rs2: 0 +is_lw: 0 +is_sw: 0 +fetch_stall_cycles: 0 +mem_stall_cycles: 0 +stall_warp: 0 +wspawn: 0 +stalled: 0 +DEBUG ../core.cpp:386: Core step stepping warp 0[1] +DEBUG ../core.cpp:683: in step pc=0x800000ec +help: in PC: 800000ec +CUrrent CODE: 1205e287 +Entered here: instr type = vector7 +DEBUG ../enc.cpp:275: vector load instr +DEBUG ../core.cpp:703: Fetched at 0x800000ec +DEBUG ../core.cpp:704: 0x800000ec: vl; +DEBUG ../instruction.cpp:350: Begin instruction execute. +DEBUG ../instruction.cpp:2035: Executing vector load +DEBUG ../instruction.cpp:2037: lmul: 1 VLEN:96sew: 32 +DEBUG ../instruction.cpp:2038: src: 11 2147485988 +DEBUG ../instruction.cpp:2039: dest5 +DEBUG ../instruction.cpp:2040: width6 +DEBUG ../instruction.cpp:2048: Data read 20 +DEBUG ../instruction.cpp:2048: Data read 10 +DEBUG ../instruction.cpp:2060: Vector Register state after addition: +reg[0][0] = 1 +reg[0][1] = 0 +reg[0][2] = 0 +reg[1][0] = 20 +reg[1][1] = 10 +reg[1][2] = 0 +reg[2][0] = 0 +reg[2][1] = 0 +reg[2][2] = 0 +reg[3][0] = 0 +reg[3][1] = 0 +reg[3][2] = 0 +reg[4][0] = 0 +reg[4][1] = 0 +reg[4][2] = 0 +reg[5][0] = 20 +reg[5][1] = 10 +reg[5][2] = 0 +reg[6][0] = 0 +reg[6][1] = 0 +reg[6][2] = 0 +reg[7][0] = 0 +reg[7][1] = 0 +reg[7][2] = 0 +reg[8][0] = 0 +reg[8][1] = 0 +reg[8][2] = 0 +reg[9][0] = 0 +reg[9][1] = 0 +reg[9][2] = 0 +reg[10][0] = 0 +reg[10][1] = 0 +reg[10][2] = 0 +reg[11][0] = 0 +reg[11][1] = 0 +reg[11][2] = 0 +reg[12][0] = 0 +reg[12][1] = 0 +reg[12][2] = 0 +reg[13][0] = 0 +reg[13][1] = 0 +reg[13][2] = 0 +reg[14][0] = 0 +reg[14][1] = 0 +reg[14][2] = 0 +reg[15][0] = 0 +reg[15][1] = 0 +reg[15][2] = 0 +reg[16][0] = 0 +reg[16][1] = 0 +reg[16][2] = 0 +reg[17][0] = 0 +reg[17][1] = 0 +reg[17][2] = 0 +reg[18][0] = 0 +reg[18][1] = 0 +reg[18][2] = 0 +reg[19][0] = 0 +reg[19][1] = 0 +reg[19][2] = 0 +reg[20][0] = 0 +reg[20][1] = 0 +reg[20][2] = 0 +reg[21][0] = 0 +reg[21][1] = 0 +reg[21][2] = 0 +reg[22][0] = 0 +reg[22][1] = 0 +reg[22][2] = 0 +reg[23][0] = 0 +reg[23][1] = 0 +reg[23][2] = 0 +reg[24][0] = 0 +reg[24][1] = 0 +reg[24][2] = 0 +reg[25][0] = 0 +reg[25][1] = 0 +reg[25][2] = 0 +reg[26][0] = 0 +reg[26][1] = 0 +reg[26][2] = 0 +reg[27][0] = 0 +reg[27][1] = 0 +reg[27][2] = 0 +reg[28][0] = 0 +reg[28][1] = 0 +reg[28][2] = 0 +reg[29][0] = 0 +reg[29][1] = 0 +reg[29][2] = 0 +reg[30][0] = 0 +reg[30][1] = 0 +reg[30][2] = 0 +reg[31][0] = 0 +reg[31][1] = 0 +reg[31][2] = 0 +DEBUG ../instruction.cpp:2117: End instruction execute. +DEBUG ../core.cpp:717: Register state: + %r 0: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r 1: 800008c0 800008bc 800008bc 800008bc 00000000 00000000 00000000 00000000 (0) + %r 2: 6fffeff0 6fffebf4 6fffe7f8 6fffe3fc 00000000 00000000 00000000 00000000 (0) + %r 3: 80001808 80001808 80001808 80001808 00000000 00000000 00000000 00000000 (0) + %r 4: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r 5: 00000002 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r 6: 0000000f 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r 7: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r 8: 6ffff000 6fffec04 6fffe808 6fffe40c 00000000 00000000 00000000 00000000 (0) + %r 9: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r10: 0000000a 00000001 00000001 00000001 00000000 00000000 00000000 00000000 (0) + %r11: 80000924 00000400 00000800 00000c00 00000000 00000000 00000000 00000000 (0) + %r12: 00000000 00000004 00000008 0000000c 00000000 00000000 00000000 00000000 (0) + %r13: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r14: 00000001 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r15: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r16: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r17: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r18: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r19: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r20: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r21: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r22: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r23: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r24: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r25: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r26: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r27: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r28: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r29: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r30: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r31: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) +DEBUG ../core.cpp:726: Thread mask: + 1 0 0 0 0 0 0 0 + + +DEBUG ../core.cpp:388: Now 1 active threads in 0 +********************************** Fetch ********************************* +valid: 1 +PC: 800000ec +wid: 0 +rd: 5 rs1: 11 rs2: 0 +is_lw: 0 +is_sw: 0 +fetch_stall_cycles: 0 +mem_stall_cycles: 0 +stall_warp: 0 +wspawn: 0 +stalled: 0 + + + +------------------------------------------------------ +CYCLE: 463 +Stalled Warps: +0 0 0 0 0 0 0 0 + +********************************** Writeback ********************************* +valid: 0 +PC: 0 +wid: 0 +rd: -1 rs1: -1 rs2: -1 +is_lw: 0 +is_sw: 0 +fetch_stall_cycles: 0 +mem_stall_cycles: 0 +stall_warp: 0 +wspawn: 0 +stalled: 0 +********************************** LSU ********************************* +valid: 0 +PC: 0 +wid: 0 +rd: -1 rs1: -1 rs2: -1 +is_lw: 0 +is_sw: 0 +fetch_stall_cycles: 0 +mem_stall_cycles: 0 +stall_warp: 0 +wspawn: 0 +stalled: 0 +********************************** execute_unit ********************************* +valid: 1 +PC: 800000e4 +wid: 0 +rd: 1 rs1: 1 rs2: 1 +is_lw: 0 +is_sw: 0 +fetch_stall_cycles: 0 +mem_stall_cycles: 0 +stall_warp: 0 +wspawn: 0 +stalled: 0 +********************************** scheduler ********************************* +valid: 1 +PC: 800000e8 +wid: 0 +rd: 1 rs1: 11 rs2: 0 +is_lw: 0 +is_sw: 0 +fetch_stall_cycles: 0 +mem_stall_cycles: 0 +stall_warp: 0 +wspawn: 0 +stalled: 0 +********************************** Decode ********************************* +valid: 1 +PC: 800000ec +wid: 0 +rd: 5 rs1: 11 rs2: 0 +is_lw: 0 +is_sw: 0 +fetch_stall_cycles: 0 +mem_stall_cycles: 0 +stall_warp: 0 +wspawn: 0 +stalled: 0 +DEBUG ../core.cpp:386: Core step stepping warp 0[1] +DEBUG ../core.cpp:683: in step pc=0x800000f0 +help: in PC: 800000f0 +CUrrent CODE: 8067 +DEBUG ../core.cpp:703: Fetched at 0x800000f0 +DEBUG ../core.cpp:704: 0x800000f0: jalr; +DEBUG ../instruction.cpp:350: Begin instruction execute. +JALR_INST +DEBUG ../instruction.cpp:2117: End instruction execute. +Next PC: 800008c0 +DEBUG ../core.cpp:717: Register state: + %r 0: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r 1: 800008c0 800008bc 800008bc 800008bc 00000000 00000000 00000000 00000000 (0) + %r 2: 6fffeff0 6fffebf4 6fffe7f8 6fffe3fc 00000000 00000000 00000000 00000000 (0) + %r 3: 80001808 80001808 80001808 80001808 00000000 00000000 00000000 00000000 (0) + %r 4: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r 5: 00000002 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r 6: 0000000f 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r 7: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r 8: 6ffff000 6fffec04 6fffe808 6fffe40c 00000000 00000000 00000000 00000000 (0) + %r 9: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r10: 0000000a 00000001 00000001 00000001 00000000 00000000 00000000 00000000 (0) + %r11: 80000924 00000400 00000800 00000c00 00000000 00000000 00000000 00000000 (0) + %r12: 00000000 00000004 00000008 0000000c 00000000 00000000 00000000 00000000 (0) + %r13: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r14: 00000001 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r15: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r16: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r17: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r18: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r19: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r20: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r21: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r22: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r23: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r24: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r25: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r26: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r27: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r28: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r29: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r30: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r31: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) +DEBUG ../core.cpp:726: Thread mask: + 1 0 0 0 0 0 0 0 + + +DEBUG ../core.cpp:388: Now 1 active threads in 0 +********************************** Fetch ********************************* +valid: 1 +PC: 800000f0 +wid: 0 +rd: 0 rs1: 1 rs2: -1 +is_lw: 0 +is_sw: 0 +fetch_stall_cycles: 3 +mem_stall_cycles: 0 +stall_warp: 1 +wspawn: 0 +stalled: 0 + + + +------------------------------------------------------ +CYCLE: 464 +Stalled Warps: +1 0 0 0 0 0 0 0 + +********************************** Writeback ********************************* +valid: 1 +PC: 800000e4 +wid: 0 +rd: 1 rs1: 1 rs2: 1 +is_lw: 0 +is_sw: 0 +fetch_stall_cycles: 0 +mem_stall_cycles: 0 +stall_warp: 0 +wspawn: 0 +stalled: 0 +********************************** LSU ********************************* +valid: 0 +PC: 0 +wid: 0 +rd: -1 rs1: -1 rs2: -1 +is_lw: 0 +is_sw: 0 +fetch_stall_cycles: 0 +mem_stall_cycles: 0 +stall_warp: 0 +wspawn: 0 +stalled: 0 +********************************** execute_unit ********************************* +valid: 1 +PC: 800000e8 +wid: 0 +rd: 1 rs1: 11 rs2: 0 +is_lw: 0 +is_sw: 0 +fetch_stall_cycles: 0 +mem_stall_cycles: 0 +stall_warp: 0 +wspawn: 0 +stalled: 0 +********************************** scheduler ********************************* +valid: 1 +PC: 800000ec +wid: 0 +rd: 5 rs1: 11 rs2: 0 +is_lw: 0 +is_sw: 0 +fetch_stall_cycles: 0 +mem_stall_cycles: 0 +stall_warp: 0 +wspawn: 0 +stalled: 0 +********************************** Decode ********************************* +valid: 0 +PC: 0 +wid: 1 +rd: -1 rs1: -1 rs2: -1 +is_lw: 0 +is_sw: 0 +fetch_stall_cycles: 0 +mem_stall_cycles: 0 +stall_warp: 0 +wspawn: 0 +stalled: 0 +********************************** Fetch ********************************* +valid: 1 +PC: 800000f0 +wid: 0 +rd: 0 rs1: 1 rs2: -1 +is_lw: 0 +is_sw: 0 +fetch_stall_cycles: 2 +mem_stall_cycles: 0 +stall_warp: 1 +wspawn: 0 +stalled: 0 + + + +------------------------------------------------------ +CYCLE: 465 +Stalled Warps: +1 0 0 0 0 0 0 0 + +********************************** Writeback ********************************* +valid: 1 +PC: 800000e8 +wid: 0 +rd: 1 rs1: 11 rs2: 0 +is_lw: 0 +is_sw: 0 +fetch_stall_cycles: 0 +mem_stall_cycles: 0 +stall_warp: 0 +wspawn: 0 +stalled: 0 +********************************** LSU ********************************* +valid: 0 +PC: 0 +wid: 0 +rd: -1 rs1: -1 rs2: -1 +is_lw: 0 +is_sw: 0 +fetch_stall_cycles: 0 +mem_stall_cycles: 0 +stall_warp: 0 +wspawn: 0 +stalled: 0 +********************************** execute_unit ********************************* +valid: 1 +PC: 800000ec +wid: 0 +rd: 5 rs1: 11 rs2: 0 +is_lw: 0 +is_sw: 0 +fetch_stall_cycles: 0 +mem_stall_cycles: 0 +stall_warp: 0 +wspawn: 0 +stalled: 0 +********************************** scheduler ********************************* +valid: 0 +PC: 0 +wid: 1 +rd: -1 rs1: -1 rs2: -1 +is_lw: 0 +is_sw: 0 +fetch_stall_cycles: 0 +mem_stall_cycles: 0 +stall_warp: 0 +wspawn: 0 +stalled: 0 +********************************** Decode ********************************* +valid: 0 +PC: 0 +wid: 1 +rd: -1 rs1: -1 rs2: -1 +is_lw: 0 +is_sw: 0 +fetch_stall_cycles: 0 +mem_stall_cycles: 0 +stall_warp: 0 +wspawn: 0 +stalled: 0 +********************************** Fetch ********************************* +valid: 1 +PC: 800000f0 +wid: 0 +rd: 0 rs1: 1 rs2: -1 +is_lw: 0 +is_sw: 0 +fetch_stall_cycles: 1 +mem_stall_cycles: 0 +stall_warp: 1 +wspawn: 0 +stalled: 0 + + + +------------------------------------------------------ +CYCLE: 466 +Stalled Warps: +1 0 0 0 0 0 0 0 + +********************************** Writeback ********************************* +valid: 1 +PC: 800000ec +wid: 0 +rd: 5 rs1: 11 rs2: 0 +is_lw: 0 +is_sw: 0 +fetch_stall_cycles: 0 +mem_stall_cycles: 0 +stall_warp: 0 +wspawn: 0 +stalled: 0 +********************************** LSU ********************************* +valid: 0 +PC: 0 +wid: 0 +rd: -1 rs1: -1 rs2: -1 +is_lw: 0 +is_sw: 0 +fetch_stall_cycles: 0 +mem_stall_cycles: 0 +stall_warp: 0 +wspawn: 0 +stalled: 0 +********************************** execute_unit ********************************* +valid: 0 +PC: 0 +wid: 1 +rd: -1 rs1: -1 rs2: -1 +is_lw: 0 +is_sw: 0 +fetch_stall_cycles: 0 +mem_stall_cycles: 0 +stall_warp: 0 +wspawn: 0 +stalled: 0 +********************************** scheduler ********************************* +valid: 0 +PC: 0 +wid: 1 +rd: -1 rs1: -1 rs2: -1 +is_lw: 0 +is_sw: 0 +fetch_stall_cycles: 0 +mem_stall_cycles: 0 +stall_warp: 0 +wspawn: 0 +stalled: 0 +********************************** Decode ********************************* +valid: 0 +PC: 0 +wid: 1 +rd: -1 rs1: -1 rs2: -1 +is_lw: 0 +is_sw: 0 +fetch_stall_cycles: 0 +mem_stall_cycles: 0 +stall_warp: 0 +wspawn: 0 +stalled: 0 +********************************** Fetch ********************************* +valid: 1 +PC: 800000f0 +wid: 0 +rd: 0 rs1: 1 rs2: -1 +is_lw: 0 +is_sw: 0 +fetch_stall_cycles: 0 +mem_stall_cycles: 0 +stall_warp: 1 +wspawn: 0 +stalled: 0 + + + +------------------------------------------------------ +CYCLE: 467 +Stalled Warps: +1 0 0 0 0 0 0 0 + +********************************** Writeback ********************************* +valid: 0 +PC: 0 +wid: 1 +rd: -1 rs1: -1 rs2: -1 +is_lw: 0 +is_sw: 0 +fetch_stall_cycles: 0 +mem_stall_cycles: 0 +stall_warp: 0 +wspawn: 0 +stalled: 0 +********************************** LSU ********************************* +valid: 0 +PC: 0 +wid: 0 +rd: -1 rs1: -1 rs2: -1 +is_lw: 0 +is_sw: 0 +fetch_stall_cycles: 0 +mem_stall_cycles: 0 +stall_warp: 0 +wspawn: 0 +stalled: 0 +********************************** execute_unit ********************************* +valid: 0 +PC: 0 +wid: 1 +rd: -1 rs1: -1 rs2: -1 +is_lw: 0 +is_sw: 0 +fetch_stall_cycles: 0 +mem_stall_cycles: 0 +stall_warp: 0 +wspawn: 0 +stalled: 0 +********************************** scheduler ********************************* +valid: 0 +PC: 0 +wid: 1 +rd: -1 rs1: -1 rs2: -1 +is_lw: 0 +is_sw: 0 +fetch_stall_cycles: 0 +mem_stall_cycles: 0 +stall_warp: 0 +wspawn: 0 +stalled: 0 +********************************** Decode ********************************* +valid: 1 +PC: 800000f0 +wid: 0 +rd: 0 rs1: 1 rs2: -1 +is_lw: 0 +is_sw: 0 +fetch_stall_cycles: 0 +mem_stall_cycles: 0 +stall_warp: 1 +wspawn: 0 +stalled: 0 +********************************** Fetch ********************************* +valid: 0 +PC: 0 +wid: 1 +rd: -1 rs1: -1 rs2: -1 +is_lw: 0 +is_sw: 0 +fetch_stall_cycles: 0 +mem_stall_cycles: 0 +stall_warp: 0 +wspawn: 0 +stalled: 0 + + + +------------------------------------------------------ +CYCLE: 468 +Stalled Warps: +1 0 0 0 0 0 0 0 + +********************************** Writeback ********************************* +valid: 0 +PC: 0 +wid: 2 +rd: -1 rs1: -1 rs2: -1 +is_lw: 0 +is_sw: 0 +fetch_stall_cycles: 0 +mem_stall_cycles: 0 +stall_warp: 0 +wspawn: 0 +stalled: 0 +********************************** LSU ********************************* +valid: 0 +PC: 0 +wid: 0 +rd: -1 rs1: -1 rs2: -1 +is_lw: 0 +is_sw: 0 +fetch_stall_cycles: 0 +mem_stall_cycles: 0 +stall_warp: 0 +wspawn: 0 +stalled: 0 +********************************** execute_unit ********************************* +valid: 0 +PC: 0 +wid: 1 +rd: -1 rs1: -1 rs2: -1 +is_lw: 0 +is_sw: 0 +fetch_stall_cycles: 0 +mem_stall_cycles: 0 +stall_warp: 0 +wspawn: 0 +stalled: 0 +********************************** scheduler ********************************* +valid: 1 +PC: 800000f0 +wid: 0 +rd: 0 rs1: 1 rs2: -1 +is_lw: 0 +is_sw: 0 +fetch_stall_cycles: 0 +mem_stall_cycles: 0 +stall_warp: 1 +wspawn: 0 +stalled: 0 +********************************** Decode ********************************* +valid: 0 +PC: 0 +wid: 1 +rd: -1 rs1: -1 rs2: -1 +is_lw: 0 +is_sw: 0 +fetch_stall_cycles: 0 +mem_stall_cycles: 0 +stall_warp: 0 +wspawn: 0 +stalled: 0 +********************************** Fetch ********************************* +valid: 0 +PC: 0 +wid: 2 +rd: -1 rs1: -1 rs2: -1 +is_lw: 0 +is_sw: 0 +fetch_stall_cycles: 0 +mem_stall_cycles: 0 +stall_warp: 0 +wspawn: 0 +stalled: 0 + + + +------------------------------------------------------ +CYCLE: 469 +Stalled Warps: +1 0 0 0 0 0 0 0 + +********************************** Writeback ********************************* +valid: 0 +PC: 0 +wid: 3 +rd: -1 rs1: -1 rs2: -1 +is_lw: 0 +is_sw: 0 +fetch_stall_cycles: 0 +mem_stall_cycles: 0 +stall_warp: 0 +wspawn: 0 +stalled: 0 +********************************** LSU ********************************* +valid: 0 +PC: 0 +wid: 0 +rd: -1 rs1: -1 rs2: -1 +is_lw: 0 +is_sw: 0 +fetch_stall_cycles: 0 +mem_stall_cycles: 0 +stall_warp: 0 +wspawn: 0 +stalled: 0 +********************************** execute_unit ********************************* +valid: 1 +PC: 800000f0 +wid: 0 +rd: 0 rs1: 1 rs2: -1 +is_lw: 0 +is_sw: 0 +fetch_stall_cycles: 0 +mem_stall_cycles: 0 +stall_warp: 1 +wspawn: 0 +stalled: 0 +********************************** scheduler ********************************* +valid: 0 +PC: 0 +wid: 1 +rd: -1 rs1: -1 rs2: -1 +is_lw: 0 +is_sw: 0 +fetch_stall_cycles: 0 +mem_stall_cycles: 0 +stall_warp: 0 +wspawn: 0 +stalled: 0 +********************************** Decode ********************************* +valid: 0 +PC: 0 +wid: 2 +rd: -1 rs1: -1 rs2: -1 +is_lw: 0 +is_sw: 0 +fetch_stall_cycles: 0 +mem_stall_cycles: 0 +stall_warp: 0 +wspawn: 0 +stalled: 0 +********************************** Fetch ********************************* +valid: 0 +PC: 0 +wid: 3 +rd: -1 rs1: -1 rs2: -1 +is_lw: 0 +is_sw: 0 +fetch_stall_cycles: 0 +mem_stall_cycles: 0 +stall_warp: 0 +wspawn: 0 +stalled: 0 + + + +------------------------------------------------------ +CYCLE: 470 +Stalled Warps: +1 0 0 0 0 0 0 0 + +********************************** Writeback ********************************* +valid: 1 +PC: 800000f0 +wid: 0 +rd: 0 rs1: 1 rs2: -1 +is_lw: 0 +is_sw: 0 +fetch_stall_cycles: 0 +mem_stall_cycles: 0 +stall_warp: 1 +wspawn: 0 +stalled: 0 +********************************** LSU ********************************* +valid: 0 +PC: 0 +wid: 0 +rd: -1 rs1: -1 rs2: -1 +is_lw: 0 +is_sw: 0 +fetch_stall_cycles: 0 +mem_stall_cycles: 0 +stall_warp: 0 +wspawn: 0 +stalled: 0 +********************************** execute_unit ********************************* +valid: 0 +PC: 0 +wid: 1 +rd: -1 rs1: -1 rs2: -1 +is_lw: 0 +is_sw: 0 +fetch_stall_cycles: 0 +mem_stall_cycles: 0 +stall_warp: 0 +wspawn: 0 +stalled: 0 +********************************** scheduler ********************************* +valid: 0 +PC: 0 +wid: 2 +rd: -1 rs1: -1 rs2: -1 +is_lw: 0 +is_sw: 0 +fetch_stall_cycles: 0 +mem_stall_cycles: 0 +stall_warp: 0 +wspawn: 0 +stalled: 0 +********************************** Decode ********************************* +valid: 0 +PC: 0 +wid: 3 +rd: -1 rs1: -1 rs2: -1 +is_lw: 0 +is_sw: 0 +fetch_stall_cycles: 0 +mem_stall_cycles: 0 +stall_warp: 0 +wspawn: 0 +stalled: 0 +********************************** Fetch ********************************* +valid: 0 +PC: 0 +wid: 4 +rd: -1 rs1: -1 rs2: -1 +is_lw: 0 +is_sw: 0 +fetch_stall_cycles: 0 +mem_stall_cycles: 0 +stall_warp: 0 +wspawn: 0 +stalled: 0 + + + +------------------------------------------------------ +CYCLE: 471 +Stalled Warps: +1 0 0 0 0 0 0 0 + +********************************** Writeback ********************************* +valid: 0 +PC: 0 +wid: 5 +rd: -1 rs1: -1 rs2: -1 +is_lw: 0 +is_sw: 0 +fetch_stall_cycles: 0 +mem_stall_cycles: 0 +stall_warp: 0 +wspawn: 0 +stalled: 0 +********************************** LSU ********************************* +valid: 0 +PC: 0 +wid: 0 +rd: -1 rs1: -1 rs2: -1 +is_lw: 0 +is_sw: 0 +fetch_stall_cycles: 0 +mem_stall_cycles: 0 +stall_warp: 0 +wspawn: 0 +stalled: 0 +********************************** execute_unit ********************************* +valid: 0 +PC: 0 +wid: 2 +rd: -1 rs1: -1 rs2: -1 +is_lw: 0 +is_sw: 0 +fetch_stall_cycles: 0 +mem_stall_cycles: 0 +stall_warp: 0 +wspawn: 0 +stalled: 0 +********************************** scheduler ********************************* +valid: 0 +PC: 0 +wid: 3 +rd: -1 rs1: -1 rs2: -1 +is_lw: 0 +is_sw: 0 +fetch_stall_cycles: 0 +mem_stall_cycles: 0 +stall_warp: 0 +wspawn: 0 +stalled: 0 +********************************** Decode ********************************* +valid: 0 +PC: 0 +wid: 4 +rd: -1 rs1: -1 rs2: -1 +is_lw: 0 +is_sw: 0 +fetch_stall_cycles: 0 +mem_stall_cycles: 0 +stall_warp: 0 +wspawn: 0 +stalled: 0 +********************************** Fetch ********************************* +valid: 0 +PC: 0 +wid: 5 +rd: -1 rs1: -1 rs2: -1 +is_lw: 0 +is_sw: 0 +fetch_stall_cycles: 0 +mem_stall_cycles: 0 +stall_warp: 0 +wspawn: 0 +stalled: 0 +Warp ID 0 is running + + + +------------------------------------------------------ +CYCLE: 472 +Stalled Warps: +0 0 0 0 0 0 0 0 + +********************************** Writeback ********************************* +valid: 0 +PC: 0 +wid: 0 +rd: -1 rs1: -1 rs2: -1 +is_lw: 0 +is_sw: 0 +fetch_stall_cycles: 0 +mem_stall_cycles: 0 +stall_warp: 0 +wspawn: 0 +stalled: 0 +********************************** LSU ********************************* +valid: 0 +PC: 0 +wid: 0 +rd: -1 rs1: -1 rs2: -1 +is_lw: 0 +is_sw: 0 +fetch_stall_cycles: 0 +mem_stall_cycles: 0 +stall_warp: 0 +wspawn: 0 +stalled: 0 +********************************** execute_unit ********************************* +valid: 0 +PC: 0 +wid: 3 +rd: -1 rs1: -1 rs2: -1 +is_lw: 0 +is_sw: 0 +fetch_stall_cycles: 0 +mem_stall_cycles: 0 +stall_warp: 0 +wspawn: 0 +stalled: 0 +********************************** scheduler ********************************* +valid: 0 +PC: 0 +wid: 4 +rd: -1 rs1: -1 rs2: -1 +is_lw: 0 +is_sw: 0 +fetch_stall_cycles: 0 +mem_stall_cycles: 0 +stall_warp: 0 +wspawn: 0 +stalled: 0 +********************************** Decode ********************************* +valid: 0 +PC: 0 +wid: 5 +rd: -1 rs1: -1 rs2: -1 +is_lw: 0 +is_sw: 0 +fetch_stall_cycles: 0 +mem_stall_cycles: 0 +stall_warp: 0 +wspawn: 0 +stalled: 0 +DEBUG ../core.cpp:386: Core step stepping warp 0[1] +DEBUG ../core.cpp:683: in step pc=0x800008c0 +help: in PC: 800008c0 +CUrrent CODE: 513 +DEBUG ../core.cpp:703: Fetched at 0x800008c0 +DEBUG ../core.cpp:704: 0x800008c0: i_type; +DEBUG ../instruction.cpp:350: Begin instruction execute. +DEBUG ../instruction.cpp:2117: End instruction execute. +DEBUG ../core.cpp:717: Register state: + %r 0: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r 1: 800008c0 800008bc 800008bc 800008bc 00000000 00000000 00000000 00000000 (0) + %r 2: 6fffeff0 6fffebf4 6fffe7f8 6fffe3fc 00000000 00000000 00000000 00000000 (0) + %r 3: 80001808 80001808 80001808 80001808 00000000 00000000 00000000 00000000 (0) + %r 4: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r 5: 00000002 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r 6: 0000000f 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r 7: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r 8: 6ffff000 6fffec04 6fffe808 6fffe40c 00000000 00000000 00000000 00000000 (0) + %r 9: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r10: 00000000 00000001 00000001 00000001 00000000 00000000 00000000 00000000 (0) + %r11: 80000924 00000400 00000800 00000c00 00000000 00000000 00000000 00000000 (0) + %r12: 00000000 00000004 00000008 0000000c 00000000 00000000 00000000 00000000 (0) + %r13: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r14: 00000001 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r15: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r16: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r17: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r18: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r19: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r20: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r21: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r22: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r23: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r24: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r25: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r26: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r27: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r28: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r29: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r30: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r31: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) +DEBUG ../core.cpp:726: Thread mask: + 1 0 0 0 0 0 0 0 + + +DEBUG ../core.cpp:388: Now 1 active threads in 0 +********************************** Fetch ********************************* +valid: 1 +PC: 800008c0 +wid: 0 +rd: 10 rs1: 0 rs2: -1 +is_lw: 0 +is_sw: 0 +fetch_stall_cycles: 3 +mem_stall_cycles: 0 +stall_warp: 0 +wspawn: 0 +stalled: 0 + + + +------------------------------------------------------ +CYCLE: 473 +Stalled Warps: +0 0 0 0 0 0 0 0 + +********************************** Writeback ********************************* +valid: 0 +PC: 0 +wid: 0 +rd: -1 rs1: -1 rs2: -1 +is_lw: 0 +is_sw: 0 +fetch_stall_cycles: 0 +mem_stall_cycles: 0 +stall_warp: 0 +wspawn: 0 +stalled: 0 +********************************** LSU ********************************* +valid: 0 +PC: 0 +wid: 0 +rd: -1 rs1: -1 rs2: -1 +is_lw: 0 +is_sw: 0 +fetch_stall_cycles: 0 +mem_stall_cycles: 0 +stall_warp: 0 +wspawn: 0 +stalled: 0 +********************************** execute_unit ********************************* +valid: 0 +PC: 0 +wid: 4 +rd: -1 rs1: -1 rs2: -1 +is_lw: 0 +is_sw: 0 +fetch_stall_cycles: 0 +mem_stall_cycles: 0 +stall_warp: 0 +wspawn: 0 +stalled: 0 +********************************** scheduler ********************************* +valid: 0 +PC: 0 +wid: 5 +rd: -1 rs1: -1 rs2: -1 +is_lw: 0 +is_sw: 0 +fetch_stall_cycles: 0 +mem_stall_cycles: 0 +stall_warp: 0 +wspawn: 0 +stalled: 0 +********************************** Decode ********************************* +valid: 0 +PC: 0 +wid: 0 +rd: -1 rs1: -1 rs2: -1 +is_lw: 0 +is_sw: 0 +fetch_stall_cycles: 0 +mem_stall_cycles: 0 +stall_warp: 0 +wspawn: 0 +stalled: 0 +********************************** Fetch ********************************* +valid: 1 +PC: 800008c0 +wid: 0 +rd: 10 rs1: 0 rs2: -1 +is_lw: 0 +is_sw: 0 +fetch_stall_cycles: 2 +mem_stall_cycles: 0 +stall_warp: 0 +wspawn: 0 +stalled: 0 + + + +------------------------------------------------------ +CYCLE: 474 +Stalled Warps: +0 0 0 0 0 0 0 0 + +********************************** Writeback ********************************* +valid: 0 +PC: 0 +wid: 0 +rd: -1 rs1: -1 rs2: -1 +is_lw: 0 +is_sw: 0 +fetch_stall_cycles: 0 +mem_stall_cycles: 0 +stall_warp: 0 +wspawn: 0 +stalled: 0 +********************************** LSU ********************************* +valid: 0 +PC: 0 +wid: 0 +rd: -1 rs1: -1 rs2: -1 +is_lw: 0 +is_sw: 0 +fetch_stall_cycles: 0 +mem_stall_cycles: 0 +stall_warp: 0 +wspawn: 0 +stalled: 0 +********************************** execute_unit ********************************* +valid: 0 +PC: 0 +wid: 5 +rd: -1 rs1: -1 rs2: -1 +is_lw: 0 +is_sw: 0 +fetch_stall_cycles: 0 +mem_stall_cycles: 0 +stall_warp: 0 +wspawn: 0 +stalled: 0 +********************************** scheduler ********************************* +valid: 0 +PC: 0 +wid: 0 +rd: -1 rs1: -1 rs2: -1 +is_lw: 0 +is_sw: 0 +fetch_stall_cycles: 0 +mem_stall_cycles: 0 +stall_warp: 0 +wspawn: 0 +stalled: 0 +********************************** Decode ********************************* +valid: 0 +PC: 0 +wid: 0 +rd: -1 rs1: -1 rs2: -1 +is_lw: 0 +is_sw: 0 +fetch_stall_cycles: 0 +mem_stall_cycles: 0 +stall_warp: 0 +wspawn: 0 +stalled: 0 +********************************** Fetch ********************************* +valid: 1 +PC: 800008c0 +wid: 0 +rd: 10 rs1: 0 rs2: -1 +is_lw: 0 +is_sw: 0 +fetch_stall_cycles: 1 +mem_stall_cycles: 0 +stall_warp: 0 +wspawn: 0 +stalled: 0 + + + +------------------------------------------------------ +CYCLE: 475 +Stalled Warps: +0 0 0 0 0 0 0 0 + +********************************** Writeback ********************************* +valid: 0 +PC: 0 +wid: 0 +rd: -1 rs1: -1 rs2: -1 +is_lw: 0 +is_sw: 0 +fetch_stall_cycles: 0 +mem_stall_cycles: 0 +stall_warp: 0 +wspawn: 0 +stalled: 0 +********************************** LSU ********************************* +valid: 0 +PC: 0 +wid: 0 +rd: -1 rs1: -1 rs2: -1 +is_lw: 0 +is_sw: 0 +fetch_stall_cycles: 0 +mem_stall_cycles: 0 +stall_warp: 0 +wspawn: 0 +stalled: 0 +********************************** execute_unit ********************************* +valid: 0 +PC: 0 +wid: 0 +rd: -1 rs1: -1 rs2: -1 +is_lw: 0 +is_sw: 0 +fetch_stall_cycles: 0 +mem_stall_cycles: 0 +stall_warp: 0 +wspawn: 0 +stalled: 0 +********************************** scheduler ********************************* +valid: 0 +PC: 0 +wid: 0 +rd: -1 rs1: -1 rs2: -1 +is_lw: 0 +is_sw: 0 +fetch_stall_cycles: 0 +mem_stall_cycles: 0 +stall_warp: 0 +wspawn: 0 +stalled: 0 +********************************** Decode ********************************* +valid: 0 +PC: 0 +wid: 0 +rd: -1 rs1: -1 rs2: -1 +is_lw: 0 +is_sw: 0 +fetch_stall_cycles: 0 +mem_stall_cycles: 0 +stall_warp: 0 +wspawn: 0 +stalled: 0 +********************************** Fetch ********************************* +valid: 1 +PC: 800008c0 +wid: 0 +rd: 10 rs1: 0 rs2: -1 +is_lw: 0 +is_sw: 0 +fetch_stall_cycles: 0 +mem_stall_cycles: 0 +stall_warp: 0 +wspawn: 0 +stalled: 0 + + + +------------------------------------------------------ +CYCLE: 476 +Stalled Warps: +0 0 0 0 0 0 0 0 + +********************************** Writeback ********************************* +valid: 0 +PC: 0 +wid: 0 +rd: -1 rs1: -1 rs2: -1 +is_lw: 0 +is_sw: 0 +fetch_stall_cycles: 0 +mem_stall_cycles: 0 +stall_warp: 0 +wspawn: 0 +stalled: 0 +********************************** LSU ********************************* +valid: 0 +PC: 0 +wid: 0 +rd: -1 rs1: -1 rs2: -1 +is_lw: 0 +is_sw: 0 +fetch_stall_cycles: 0 +mem_stall_cycles: 0 +stall_warp: 0 +wspawn: 0 +stalled: 0 +********************************** execute_unit ********************************* +valid: 0 +PC: 0 +wid: 0 +rd: -1 rs1: -1 rs2: -1 +is_lw: 0 +is_sw: 0 +fetch_stall_cycles: 0 +mem_stall_cycles: 0 +stall_warp: 0 +wspawn: 0 +stalled: 0 +********************************** scheduler ********************************* +valid: 0 +PC: 0 +wid: 0 +rd: -1 rs1: -1 rs2: -1 +is_lw: 0 +is_sw: 0 +fetch_stall_cycles: 0 +mem_stall_cycles: 0 +stall_warp: 0 +wspawn: 0 +stalled: 0 +********************************** Decode ********************************* +valid: 1 +PC: 800008c0 +wid: 0 +rd: 10 rs1: 0 rs2: -1 +is_lw: 0 +is_sw: 0 +fetch_stall_cycles: 0 +mem_stall_cycles: 0 +stall_warp: 0 +wspawn: 0 +stalled: 0 +DEBUG ../core.cpp:386: Core step stepping warp 0[1] +DEBUG ../core.cpp:683: in step pc=0x800008c4 +help: in PC: 800008c4 +CUrrent CODE: f35ff0ef +DEBUG ../core.cpp:703: Fetched at 0x800008c4 +DEBUG ../core.cpp:704: 0x800008c4: jal; +DEBUG ../instruction.cpp:350: Begin instruction execute. +DEBUG ../instruction.cpp:2117: End instruction execute. +Next PC: 800007f8 +DEBUG ../core.cpp:717: Register state: + %r 0: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r 1: 800008c8 800008bc 800008bc 800008bc 00000000 00000000 00000000 00000000 (0) + %r 2: 6fffeff0 6fffebf4 6fffe7f8 6fffe3fc 00000000 00000000 00000000 00000000 (0) + %r 3: 80001808 80001808 80001808 80001808 00000000 00000000 00000000 00000000 (0) + %r 4: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r 5: 00000002 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r 6: 0000000f 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r 7: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r 8: 6ffff000 6fffec04 6fffe808 6fffe40c 00000000 00000000 00000000 00000000 (0) + %r 9: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r10: 00000000 00000001 00000001 00000001 00000000 00000000 00000000 00000000 (0) + %r11: 80000924 00000400 00000800 00000c00 00000000 00000000 00000000 00000000 (0) + %r12: 00000000 00000004 00000008 0000000c 00000000 00000000 00000000 00000000 (0) + %r13: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r14: 00000001 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r15: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r16: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r17: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r18: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r19: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r20: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r21: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r22: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r23: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r24: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r25: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r26: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r27: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r28: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r29: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r30: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r31: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) +DEBUG ../core.cpp:726: Thread mask: + 1 0 0 0 0 0 0 0 + + +DEBUG ../core.cpp:388: Now 1 active threads in 0 +********************************** Fetch ********************************* +valid: 1 +PC: 800008c4 +wid: 0 +rd: 1 rs1: -1 rs2: -1 +is_lw: 0 +is_sw: 0 +fetch_stall_cycles: 0 +mem_stall_cycles: 0 +stall_warp: 1 +wspawn: 0 +stalled: 0 + + + +------------------------------------------------------ +CYCLE: 477 +Stalled Warps: +1 0 0 0 0 0 0 0 + +********************************** Writeback ********************************* +valid: 0 +PC: 0 +wid: 1 +rd: -1 rs1: -1 rs2: -1 +is_lw: 0 +is_sw: 0 +fetch_stall_cycles: 0 +mem_stall_cycles: 0 +stall_warp: 0 +wspawn: 0 +stalled: 0 +********************************** LSU ********************************* +valid: 0 +PC: 0 +wid: 0 +rd: -1 rs1: -1 rs2: -1 +is_lw: 0 +is_sw: 0 +fetch_stall_cycles: 0 +mem_stall_cycles: 0 +stall_warp: 0 +wspawn: 0 +stalled: 0 +********************************** execute_unit ********************************* +valid: 0 +PC: 0 +wid: 0 +rd: -1 rs1: -1 rs2: -1 +is_lw: 0 +is_sw: 0 +fetch_stall_cycles: 0 +mem_stall_cycles: 0 +stall_warp: 0 +wspawn: 0 +stalled: 0 +********************************** scheduler ********************************* +valid: 1 +PC: 800008c0 +wid: 0 +rd: 10 rs1: 0 rs2: -1 +is_lw: 0 +is_sw: 0 +fetch_stall_cycles: 0 +mem_stall_cycles: 0 +stall_warp: 0 +wspawn: 0 +stalled: 0 +********************************** Decode ********************************* +valid: 1 +PC: 800008c4 +wid: 0 +rd: 1 rs1: -1 rs2: -1 +is_lw: 0 +is_sw: 0 +fetch_stall_cycles: 0 +mem_stall_cycles: 0 +stall_warp: 1 +wspawn: 0 +stalled: 0 +********************************** Fetch ********************************* +valid: 0 +PC: 0 +wid: 1 +rd: -1 rs1: -1 rs2: -1 +is_lw: 0 +is_sw: 0 +fetch_stall_cycles: 0 +mem_stall_cycles: 0 +stall_warp: 0 +wspawn: 0 +stalled: 0 + + + +------------------------------------------------------ +CYCLE: 478 +Stalled Warps: +1 0 0 0 0 0 0 0 + +********************************** Writeback ********************************* +valid: 0 +PC: 0 +wid: 2 +rd: -1 rs1: -1 rs2: -1 +is_lw: 0 +is_sw: 0 +fetch_stall_cycles: 0 +mem_stall_cycles: 0 +stall_warp: 0 +wspawn: 0 +stalled: 0 +********************************** LSU ********************************* +valid: 0 +PC: 0 +wid: 0 +rd: -1 rs1: -1 rs2: -1 +is_lw: 0 +is_sw: 0 +fetch_stall_cycles: 0 +mem_stall_cycles: 0 +stall_warp: 0 +wspawn: 0 +stalled: 0 +********************************** execute_unit ********************************* +valid: 1 +PC: 800008c0 +wid: 0 +rd: 10 rs1: 0 rs2: -1 +is_lw: 0 +is_sw: 0 +fetch_stall_cycles: 0 +mem_stall_cycles: 0 +stall_warp: 0 +wspawn: 0 +stalled: 0 +********************************** scheduler ********************************* +valid: 1 +PC: 800008c4 +wid: 0 +rd: 1 rs1: -1 rs2: -1 +is_lw: 0 +is_sw: 0 +fetch_stall_cycles: 0 +mem_stall_cycles: 0 +stall_warp: 1 +wspawn: 0 +stalled: 0 +********************************** Decode ********************************* +valid: 0 +PC: 0 +wid: 1 +rd: -1 rs1: -1 rs2: -1 +is_lw: 0 +is_sw: 0 +fetch_stall_cycles: 0 +mem_stall_cycles: 0 +stall_warp: 0 +wspawn: 0 +stalled: 0 +********************************** Fetch ********************************* +valid: 0 +PC: 0 +wid: 2 +rd: -1 rs1: -1 rs2: -1 +is_lw: 0 +is_sw: 0 +fetch_stall_cycles: 0 +mem_stall_cycles: 0 +stall_warp: 0 +wspawn: 0 +stalled: 0 + + + +------------------------------------------------------ +CYCLE: 479 +Stalled Warps: +1 0 0 0 0 0 0 0 + +********************************** Writeback ********************************* +valid: 1 +PC: 800008c0 +wid: 0 +rd: 10 rs1: 0 rs2: -1 +is_lw: 0 +is_sw: 0 +fetch_stall_cycles: 0 +mem_stall_cycles: 0 +stall_warp: 0 +wspawn: 0 +stalled: 0 +********************************** LSU ********************************* +valid: 0 +PC: 0 +wid: 0 +rd: -1 rs1: -1 rs2: -1 +is_lw: 0 +is_sw: 0 +fetch_stall_cycles: 0 +mem_stall_cycles: 0 +stall_warp: 0 +wspawn: 0 +stalled: 0 +********************************** execute_unit ********************************* +valid: 1 +PC: 800008c4 +wid: 0 +rd: 1 rs1: -1 rs2: -1 +is_lw: 0 +is_sw: 0 +fetch_stall_cycles: 0 +mem_stall_cycles: 0 +stall_warp: 1 +wspawn: 0 +stalled: 0 +********************************** scheduler ********************************* +valid: 0 +PC: 0 +wid: 1 +rd: -1 rs1: -1 rs2: -1 +is_lw: 0 +is_sw: 0 +fetch_stall_cycles: 0 +mem_stall_cycles: 0 +stall_warp: 0 +wspawn: 0 +stalled: 0 +********************************** Decode ********************************* +valid: 0 +PC: 0 +wid: 2 +rd: -1 rs1: -1 rs2: -1 +is_lw: 0 +is_sw: 0 +fetch_stall_cycles: 0 +mem_stall_cycles: 0 +stall_warp: 0 +wspawn: 0 +stalled: 0 +********************************** Fetch ********************************* +valid: 0 +PC: 0 +wid: 3 +rd: -1 rs1: -1 rs2: -1 +is_lw: 0 +is_sw: 0 +fetch_stall_cycles: 0 +mem_stall_cycles: 0 +stall_warp: 0 +wspawn: 0 +stalled: 0 + + + +------------------------------------------------------ +CYCLE: 480 +Stalled Warps: +1 0 0 0 0 0 0 0 + +********************************** Writeback ********************************* +valid: 1 +PC: 800008c4 +wid: 0 +rd: 1 rs1: -1 rs2: -1 +is_lw: 0 +is_sw: 0 +fetch_stall_cycles: 0 +mem_stall_cycles: 0 +stall_warp: 1 +wspawn: 0 +stalled: 0 +********************************** LSU ********************************* +valid: 0 +PC: 0 +wid: 0 +rd: -1 rs1: -1 rs2: -1 +is_lw: 0 +is_sw: 0 +fetch_stall_cycles: 0 +mem_stall_cycles: 0 +stall_warp: 0 +wspawn: 0 +stalled: 0 +********************************** execute_unit ********************************* +valid: 0 +PC: 0 +wid: 1 +rd: -1 rs1: -1 rs2: -1 +is_lw: 0 +is_sw: 0 +fetch_stall_cycles: 0 +mem_stall_cycles: 0 +stall_warp: 0 +wspawn: 0 +stalled: 0 +********************************** scheduler ********************************* +valid: 0 +PC: 0 +wid: 2 +rd: -1 rs1: -1 rs2: -1 +is_lw: 0 +is_sw: 0 +fetch_stall_cycles: 0 +mem_stall_cycles: 0 +stall_warp: 0 +wspawn: 0 +stalled: 0 +********************************** Decode ********************************* +valid: 0 +PC: 0 +wid: 3 +rd: -1 rs1: -1 rs2: -1 +is_lw: 0 +is_sw: 0 +fetch_stall_cycles: 0 +mem_stall_cycles: 0 +stall_warp: 0 +wspawn: 0 +stalled: 0 +********************************** Fetch ********************************* +valid: 0 +PC: 0 +wid: 4 +rd: -1 rs1: -1 rs2: -1 +is_lw: 0 +is_sw: 0 +fetch_stall_cycles: 0 +mem_stall_cycles: 0 +stall_warp: 0 +wspawn: 0 +stalled: 0 + + + +------------------------------------------------------ +CYCLE: 481 +Stalled Warps: +1 0 0 0 0 0 0 0 + +********************************** Writeback ********************************* +valid: 0 +PC: 0 +wid: 5 +rd: -1 rs1: -1 rs2: -1 +is_lw: 0 +is_sw: 0 +fetch_stall_cycles: 0 +mem_stall_cycles: 0 +stall_warp: 0 +wspawn: 0 +stalled: 0 +********************************** LSU ********************************* +valid: 0 +PC: 0 +wid: 0 +rd: -1 rs1: -1 rs2: -1 +is_lw: 0 +is_sw: 0 +fetch_stall_cycles: 0 +mem_stall_cycles: 0 +stall_warp: 0 +wspawn: 0 +stalled: 0 +********************************** execute_unit ********************************* +valid: 0 +PC: 0 +wid: 2 +rd: -1 rs1: -1 rs2: -1 +is_lw: 0 +is_sw: 0 +fetch_stall_cycles: 0 +mem_stall_cycles: 0 +stall_warp: 0 +wspawn: 0 +stalled: 0 +********************************** scheduler ********************************* +valid: 0 +PC: 0 +wid: 3 +rd: -1 rs1: -1 rs2: -1 +is_lw: 0 +is_sw: 0 +fetch_stall_cycles: 0 +mem_stall_cycles: 0 +stall_warp: 0 +wspawn: 0 +stalled: 0 +********************************** Decode ********************************* +valid: 0 +PC: 0 +wid: 4 +rd: -1 rs1: -1 rs2: -1 +is_lw: 0 +is_sw: 0 +fetch_stall_cycles: 0 +mem_stall_cycles: 0 +stall_warp: 0 +wspawn: 0 +stalled: 0 +********************************** Fetch ********************************* +valid: 0 +PC: 0 +wid: 5 +rd: -1 rs1: -1 rs2: -1 +is_lw: 0 +is_sw: 0 +fetch_stall_cycles: 0 +mem_stall_cycles: 0 +stall_warp: 0 +wspawn: 0 +stalled: 0 +Warp ID 0 is running + + + +------------------------------------------------------ +CYCLE: 482 +Stalled Warps: +0 0 0 0 0 0 0 0 + +********************************** Writeback ********************************* +valid: 0 +PC: 0 +wid: 0 +rd: -1 rs1: -1 rs2: -1 +is_lw: 0 +is_sw: 0 +fetch_stall_cycles: 0 +mem_stall_cycles: 0 +stall_warp: 0 +wspawn: 0 +stalled: 0 +********************************** LSU ********************************* +valid: 0 +PC: 0 +wid: 0 +rd: -1 rs1: -1 rs2: -1 +is_lw: 0 +is_sw: 0 +fetch_stall_cycles: 0 +mem_stall_cycles: 0 +stall_warp: 0 +wspawn: 0 +stalled: 0 +********************************** execute_unit ********************************* +valid: 0 +PC: 0 +wid: 3 +rd: -1 rs1: -1 rs2: -1 +is_lw: 0 +is_sw: 0 +fetch_stall_cycles: 0 +mem_stall_cycles: 0 +stall_warp: 0 +wspawn: 0 +stalled: 0 +********************************** scheduler ********************************* +valid: 0 +PC: 0 +wid: 4 +rd: -1 rs1: -1 rs2: -1 +is_lw: 0 +is_sw: 0 +fetch_stall_cycles: 0 +mem_stall_cycles: 0 +stall_warp: 0 +wspawn: 0 +stalled: 0 +********************************** Decode ********************************* +valid: 0 +PC: 0 +wid: 5 +rd: -1 rs1: -1 rs2: -1 +is_lw: 0 +is_sw: 0 +fetch_stall_cycles: 0 +mem_stall_cycles: 0 +stall_warp: 0 +wspawn: 0 +stalled: 0 +DEBUG ../core.cpp:386: Core step stepping warp 0[1] +DEBUG ../core.cpp:683: in step pc=0x800007f8 +help: in PC: 800007f8 +CUrrent CODE: 5006b +DEBUG ../core.cpp:703: Fetched at 0x800007f8 +DEBUG ../core.cpp:704: 0x800007f8: gpgpu; +DEBUG ../instruction.cpp:350: Begin instruction execute. +DEBUG ../instruction.cpp:2117: End instruction execute. +DEBUG ../core.cpp:717: Register state: + %r 0: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r 1: 800008c8 800008bc 800008bc 800008bc 00000000 00000000 00000000 00000000 (0) + %r 2: 6fffeff0 6fffebf4 6fffe7f8 6fffe3fc 00000000 00000000 00000000 00000000 (0) + %r 3: 80001808 80001808 80001808 80001808 00000000 00000000 00000000 00000000 (0) + %r 4: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r 5: 00000002 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r 6: 0000000f 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r 7: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r 8: 6ffff000 6fffec04 6fffe808 6fffe40c 00000000 00000000 00000000 00000000 (0) + %r 9: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r10: 00000000 00000001 00000001 00000001 00000000 00000000 00000000 00000000 (0) + %r11: 80000924 00000400 00000800 00000c00 00000000 00000000 00000000 00000000 (0) + %r12: 00000000 00000004 00000008 0000000c 00000000 00000000 00000000 00000000 (0) + %r13: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r14: 00000001 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r15: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r16: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r17: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r18: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r19: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r20: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r21: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r22: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r23: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r24: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r25: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r26: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r27: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r28: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r29: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r30: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) + %r31: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (0) +DEBUG ../core.cpp:726: Thread mask: + 0 0 0 0 0 0 0 0 + + +DEBUG ../core.cpp:388: Now 0 active threads in 0 +********************************** Fetch ********************************* +valid: 1 +PC: 800007f8 +wid: 0 +rd: 0 rs1: 10 rs2: 0 +is_lw: 0 +is_sw: 0 +fetch_stall_cycles: 0 +mem_stall_cycles: 0 +stall_warp: 1 +wspawn: 0 +stalled: 0 + + + +------------------------------------------------------ +CYCLE: 483 +Stalled Warps: +1 0 0 0 0 0 0 0 + +********************************** Writeback ********************************* +valid: 0 +PC: 0 +wid: 1 +rd: -1 rs1: -1 rs2: -1 +is_lw: 0 +is_sw: 0 +fetch_stall_cycles: 0 +mem_stall_cycles: 0 +stall_warp: 0 +wspawn: 0 +stalled: 0 +********************************** LSU ********************************* +valid: 0 +PC: 0 +wid: 0 +rd: -1 rs1: -1 rs2: -1 +is_lw: 0 +is_sw: 0 +fetch_stall_cycles: 0 +mem_stall_cycles: 0 +stall_warp: 0 +wspawn: 0 +stalled: 0 +********************************** execute_unit ********************************* +valid: 0 +PC: 0 +wid: 4 +rd: -1 rs1: -1 rs2: -1 +is_lw: 0 +is_sw: 0 +fetch_stall_cycles: 0 +mem_stall_cycles: 0 +stall_warp: 0 +wspawn: 0 +stalled: 0 +********************************** scheduler ********************************* +valid: 0 +PC: 0 +wid: 5 +rd: -1 rs1: -1 rs2: -1 +is_lw: 0 +is_sw: 0 +fetch_stall_cycles: 0 +mem_stall_cycles: 0 +stall_warp: 0 +wspawn: 0 +stalled: 0 +********************************** Decode ********************************* +valid: 1 +PC: 800007f8 +wid: 0 +rd: 0 rs1: 10 rs2: 0 +is_lw: 0 +is_sw: 0 +fetch_stall_cycles: 0 +mem_stall_cycles: 0 +stall_warp: 1 +wspawn: 0 +stalled: 0 +********************************** Fetch ********************************* +valid: 0 +PC: 0 +wid: 1 +rd: -1 rs1: -1 rs2: -1 +is_lw: 0 +is_sw: 0 +fetch_stall_cycles: 0 +mem_stall_cycles: 0 +stall_warp: 0 +wspawn: 0 +stalled: 0 + + + +------------------------------------------------------ +CYCLE: 484 +Stalled Warps: +1 0 0 0 0 0 0 0 + +********************************** Writeback ********************************* +valid: 0 +PC: 0 +wid: 2 +rd: -1 rs1: -1 rs2: -1 +is_lw: 0 +is_sw: 0 +fetch_stall_cycles: 0 +mem_stall_cycles: 0 +stall_warp: 0 +wspawn: 0 +stalled: 0 +********************************** LSU ********************************* +valid: 0 +PC: 0 +wid: 0 +rd: -1 rs1: -1 rs2: -1 +is_lw: 0 +is_sw: 0 +fetch_stall_cycles: 0 +mem_stall_cycles: 0 +stall_warp: 0 +wspawn: 0 +stalled: 0 +********************************** execute_unit ********************************* +valid: 0 +PC: 0 +wid: 5 +rd: -1 rs1: -1 rs2: -1 +is_lw: 0 +is_sw: 0 +fetch_stall_cycles: 0 +mem_stall_cycles: 0 +stall_warp: 0 +wspawn: 0 +stalled: 0 +********************************** scheduler ********************************* +valid: 1 +PC: 800007f8 +wid: 0 +rd: 0 rs1: 10 rs2: 0 +is_lw: 0 +is_sw: 0 +fetch_stall_cycles: 0 +mem_stall_cycles: 0 +stall_warp: 1 +wspawn: 0 +stalled: 0 +********************************** Decode ********************************* +valid: 0 +PC: 0 +wid: 1 +rd: -1 rs1: -1 rs2: -1 +is_lw: 0 +is_sw: 0 +fetch_stall_cycles: 0 +mem_stall_cycles: 0 +stall_warp: 0 +wspawn: 0 +stalled: 0 +********************************** Fetch ********************************* +valid: 0 +PC: 0 +wid: 2 +rd: -1 rs1: -1 rs2: -1 +is_lw: 0 +is_sw: 0 +fetch_stall_cycles: 0 +mem_stall_cycles: 0 +stall_warp: 0 +wspawn: 0 +stalled: 0 + + + +------------------------------------------------------ +CYCLE: 485 +Stalled Warps: +1 0 0 0 0 0 0 0 + +********************************** Writeback ********************************* +valid: 0 +PC: 0 +wid: 3 +rd: -1 rs1: -1 rs2: -1 +is_lw: 0 +is_sw: 0 +fetch_stall_cycles: 0 +mem_stall_cycles: 0 +stall_warp: 0 +wspawn: 0 +stalled: 0 +********************************** LSU ********************************* +valid: 0 +PC: 0 +wid: 0 +rd: -1 rs1: -1 rs2: -1 +is_lw: 0 +is_sw: 0 +fetch_stall_cycles: 0 +mem_stall_cycles: 0 +stall_warp: 0 +wspawn: 0 +stalled: 0 +********************************** execute_unit ********************************* +valid: 1 +PC: 800007f8 +wid: 0 +rd: 0 rs1: 10 rs2: 0 +is_lw: 0 +is_sw: 0 +fetch_stall_cycles: 0 +mem_stall_cycles: 0 +stall_warp: 1 +wspawn: 0 +stalled: 0 +********************************** scheduler ********************************* +valid: 0 +PC: 0 +wid: 1 +rd: -1 rs1: -1 rs2: -1 +is_lw: 0 +is_sw: 0 +fetch_stall_cycles: 0 +mem_stall_cycles: 0 +stall_warp: 0 +wspawn: 0 +stalled: 0 +********************************** Decode ********************************* +valid: 0 +PC: 0 +wid: 2 +rd: -1 rs1: -1 rs2: -1 +is_lw: 0 +is_sw: 0 +fetch_stall_cycles: 0 +mem_stall_cycles: 0 +stall_warp: 0 +wspawn: 0 +stalled: 0 +********************************** Fetch ********************************* +valid: 0 +PC: 0 +wid: 3 +rd: -1 rs1: -1 rs2: -1 +is_lw: 0 +is_sw: 0 +fetch_stall_cycles: 0 +mem_stall_cycles: 0 +stall_warp: 0 +wspawn: 0 +stalled: 0 + + + +------------------------------------------------------ +CYCLE: 486 +Stalled Warps: +1 0 0 0 0 0 0 0 + +********************************** Writeback ********************************* +valid: 1 +PC: 800007f8 +wid: 0 +rd: 0 rs1: 10 rs2: 0 +is_lw: 0 +is_sw: 0 +fetch_stall_cycles: 0 +mem_stall_cycles: 0 +stall_warp: 1 +wspawn: 0 +stalled: 0 +********************************** LSU ********************************* +valid: 0 +PC: 0 +wid: 0 +rd: -1 rs1: -1 rs2: -1 +is_lw: 0 +is_sw: 0 +fetch_stall_cycles: 0 +mem_stall_cycles: 0 +stall_warp: 0 +wspawn: 0 +stalled: 0 +********************************** execute_unit ********************************* +valid: 0 +PC: 0 +wid: 1 +rd: -1 rs1: -1 rs2: -1 +is_lw: 0 +is_sw: 0 +fetch_stall_cycles: 0 +mem_stall_cycles: 0 +stall_warp: 0 +wspawn: 0 +stalled: 0 +********************************** scheduler ********************************* +valid: 0 +PC: 0 +wid: 2 +rd: -1 rs1: -1 rs2: -1 +is_lw: 0 +is_sw: 0 +fetch_stall_cycles: 0 +mem_stall_cycles: 0 +stall_warp: 0 +wspawn: 0 +stalled: 0 +********************************** Decode ********************************* +valid: 0 +PC: 0 +wid: 3 +rd: -1 rs1: -1 rs2: -1 +is_lw: 0 +is_sw: 0 +fetch_stall_cycles: 0 +mem_stall_cycles: 0 +stall_warp: 0 +wspawn: 0 +stalled: 0 +********************************** Fetch ********************************* +valid: 0 +PC: 0 +wid: 4 +rd: -1 rs1: -1 rs2: -1 +is_lw: 0 +is_sw: 0 +fetch_stall_cycles: 0 +mem_stall_cycles: 0 +stall_warp: 0 +wspawn: 0 +stalled: 0 + + + +------------------------------------------------------ +CYCLE: 487 +Stalled Warps: +1 0 0 0 0 0 0 0 + +********************************** Writeback ********************************* +valid: 0 +PC: 0 +wid: 5 +rd: -1 rs1: -1 rs2: -1 +is_lw: 0 +is_sw: 0 +fetch_stall_cycles: 0 +mem_stall_cycles: 0 +stall_warp: 0 +wspawn: 0 +stalled: 0 +********************************** LSU ********************************* +valid: 0 +PC: 0 +wid: 0 +rd: -1 rs1: -1 rs2: -1 +is_lw: 0 +is_sw: 0 +fetch_stall_cycles: 0 +mem_stall_cycles: 0 +stall_warp: 0 +wspawn: 0 +stalled: 0 +********************************** execute_unit ********************************* +valid: 0 +PC: 0 +wid: 2 +rd: -1 rs1: -1 rs2: -1 +is_lw: 0 +is_sw: 0 +fetch_stall_cycles: 0 +mem_stall_cycles: 0 +stall_warp: 0 +wspawn: 0 +stalled: 0 +********************************** scheduler ********************************* +valid: 0 +PC: 0 +wid: 3 +rd: -1 rs1: -1 rs2: -1 +is_lw: 0 +is_sw: 0 +fetch_stall_cycles: 0 +mem_stall_cycles: 0 +stall_warp: 0 +wspawn: 0 +stalled: 0 +********************************** Decode ********************************* +valid: 0 +PC: 0 +wid: 4 +rd: -1 rs1: -1 rs2: -1 +is_lw: 0 +is_sw: 0 +fetch_stall_cycles: 0 +mem_stall_cycles: 0 +stall_warp: 0 +wspawn: 0 +stalled: 0 +********************************** Fetch ********************************* +valid: 0 +PC: 0 +wid: 5 +rd: -1 rs1: -1 rs2: -1 +is_lw: 0 +is_sw: 0 +fetch_stall_cycles: 0 +mem_stall_cycles: 0 +stall_warp: 0 +wspawn: 0 +stalled: 0 +=== Warp 0 === +Steps : 0 +Insts : 200 +Loads : 0 +Stores: 25 +GRADE: FAILED 0 +=== Warp 1 === +Steps : 0 +Insts : 59 +Loads : 0 +Stores: 0 +GRADE: FAILED 0 +=== Warp 2 === +Steps : 0 +Insts : 59 +Loads : 0 +Stores: 0 +GRADE: FAILED 0 +=== Warp 3 === +Steps : 0 +Insts : 59 +Loads : 0 +Stores: 0 +GRADE: FAILED 0 +=== Warp 4 === +Steps : 0 +Insts : 0 +Loads : 0 +Stores: 0 +GRADE: FAILED 0 +=== Warp 5 === +Steps : 0 +Insts : 0 +Loads : 0 +Stores: 0 +GRADE: FAILED 0 +=== Warp 6 === +Steps : 0 +Insts : 0 +Loads : 0 +Stores: 0 +GRADE: FAILED 0 +=== Warp 7 === +Steps : 0 +Insts : 0 +Loads : 0 +Stores: 0 +GRADE: FAILED 0 + diff --git a/simX/obj_dir/enc.d b/simX/obj_dir/enc.d new file mode 100644 index 00000000..c9cdd837 --- /dev/null +++ b/simX/obj_dir/enc.d @@ -0,0 +1,5 @@ +enc.o: ../enc.cpp ../include/debug.h ../include/types.h ../include/util.h \ + ../include/types.h ../include/enc.h ../include/instruction.h \ + ../include/trace.h ../include/obj.h ../include/archdef.h \ + ../include/enc.h ../include/asm-tokens.h ../include/archdef.h \ + ../include/instruction.h diff --git a/simX/obj_dir/enc.o b/simX/obj_dir/enc.o new file mode 100644 index 00000000..a6aaa41a Binary files /dev/null and b/simX/obj_dir/enc.o differ diff --git a/simX/obj_dir/instruction.d b/simX/obj_dir/instruction.d new file mode 100644 index 00000000..b985df34 --- /dev/null +++ b/simX/obj_dir/instruction.d @@ -0,0 +1,10 @@ +instruction.o: ../instruction.cpp ../include/instruction.h \ + ../include/types.h ../include/trace.h ../include/obj.h \ + ../include/archdef.h ../include/instruction.h ../include/enc.h \ + ../include/obj.h ../include/asm-tokens.h ../include/core.h \ + ../include/mem.h ../include/debug.h Vcache_simX.h \ + /usr/local/share/verilator/include/verilated.h \ + /usr/local/share/verilator/include/verilatedos.h \ + /usr/local/share/verilator/include/verilated_vcd_c.h \ + /usr/local/share/verilator/include/verilated.h ../include/harpfloat.h \ + ../include/debug.h diff --git a/simX/obj_dir/instruction.o b/simX/obj_dir/instruction.o new file mode 100644 index 00000000..b40ddaf2 Binary files /dev/null and b/simX/obj_dir/instruction.o differ diff --git a/simX/obj_dir/mem.d b/simX/obj_dir/mem.d new file mode 100644 index 00000000..f2d8844d --- /dev/null +++ b/simX/obj_dir/mem.d @@ -0,0 +1,9 @@ +mem.o: ../mem.cpp ../include/debug.h ../include/types.h ../include/util.h \ + ../include/types.h ../include/mem.h ../include/core.h \ + ../include/archdef.h ../include/enc.h ../include/instruction.h \ + ../include/trace.h ../include/obj.h ../include/asm-tokens.h \ + ../include/mem.h ../include/debug.h Vcache_simX.h \ + /usr/local/share/verilator/include/verilated.h \ + /usr/local/share/verilator/include/verilatedos.h \ + /usr/local/share/verilator/include/verilated_vcd_c.h \ + /usr/local/share/verilator/include/verilated.h diff --git a/simX/obj_dir/mem.o b/simX/obj_dir/mem.o new file mode 100644 index 00000000..69a48843 Binary files /dev/null and b/simX/obj_dir/mem.o differ diff --git a/simX/obj_dir/simX.d b/simX/obj_dir/simX.d new file mode 100644 index 00000000..2310ae70 --- /dev/null +++ b/simX/obj_dir/simX.d @@ -0,0 +1,11 @@ +simX.o: ../simX.cpp ../include/debug.h ../include/types.h \ + ../include/core.h ../include/types.h ../include/archdef.h \ + ../include/enc.h ../include/instruction.h ../include/trace.h \ + ../include/obj.h ../include/asm-tokens.h ../include/mem.h \ + ../include/debug.h Vcache_simX.h \ + /usr/local/share/verilator/include/verilated.h \ + /usr/local/share/verilator/include/verilatedos.h \ + /usr/local/share/verilator/include/verilated_vcd_c.h \ + /usr/local/share/verilator/include/verilated.h ../include/enc.h \ + ../include/instruction.h ../include/mem.h ../include/obj.h \ + ../include/archdef.h ../include/args.h ../include/help.h diff --git a/simX/obj_dir/simX.o b/simX/obj_dir/simX.o new file mode 100644 index 00000000..b40a3fa1 Binary files /dev/null and b/simX/obj_dir/simX.o differ diff --git a/simX/obj_dir/util.d b/simX/obj_dir/util.d new file mode 100644 index 00000000..d7d5aee0 --- /dev/null +++ b/simX/obj_dir/util.d @@ -0,0 +1,2 @@ +util.o: ../util.cpp ../include/types.h ../include/util.h \ + ../include/types.h diff --git a/simX/obj_dir/util.o b/simX/obj_dir/util.o new file mode 100644 index 00000000..f8b206bc Binary files /dev/null and b/simX/obj_dir/util.o differ diff --git a/simX/obj_dir/verilated.d b/simX/obj_dir/verilated.d new file mode 100644 index 00000000..4f8241f8 --- /dev/null +++ b/simX/obj_dir/verilated.d @@ -0,0 +1,8 @@ +verilated.o: /usr/local/share/verilator/include/verilated.cpp \ + /usr/local/share/verilator/include/verilatedos.h \ + /usr/local/share/verilator/include/verilated_imp.h \ + /usr/local/share/verilator/include/verilated.h \ + /usr/local/share/verilator/include/verilated_heavy.h \ + /usr/local/share/verilator/include/verilated_syms.h \ + /usr/local/share/verilator/include/verilated_sym_props.h \ + /usr/local/share/verilator/include/verilated_config.h diff --git a/simX/obj_dir/verilated.o b/simX/obj_dir/verilated.o new file mode 100644 index 00000000..93498745 Binary files /dev/null and b/simX/obj_dir/verilated.o differ diff --git a/simX/obj_dir/verilated_vcd_c.d b/simX/obj_dir/verilated_vcd_c.d new file mode 100644 index 00000000..1240003b --- /dev/null +++ b/simX/obj_dir/verilated_vcd_c.d @@ -0,0 +1,4 @@ +verilated_vcd_c.o: /usr/local/share/verilator/include/verilated_vcd_c.cpp \ + /usr/local/share/verilator/include/verilatedos.h \ + /usr/local/share/verilator/include/verilated.h \ + /usr/local/share/verilator/include/verilated_vcd_c.h diff --git a/simX/obj_dir/verilated_vcd_c.o b/simX/obj_dir/verilated_vcd_c.o new file mode 100644 index 00000000..712c9739 Binary files /dev/null and b/simX/obj_dir/verilated_vcd_c.o differ