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refactor VX_define.v

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Blaise Tine
2020-03-27 13:56:16 -04:00
parent 3df21b6e71
commit 6dc3d0d371
1 changed files with 529 additions and 523 deletions
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36
rtl/VX_define.v
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@@ -159,6 +159,7 @@
// ========================================= Dcache Configurable Knobs ========================================= // ========================================= Dcache Configurable Knobs =========================================
// General Cache Knobs // General Cache Knobs
// Size of cache in bytes // Size of cache in bytes
`ifndef DCACHE_SIZE_BYTES `ifndef DCACHE_SIZE_BYTES
`define DCACHE_SIZE_BYTES 4096 `define DCACHE_SIZE_BYTES 4096
@@ -198,45 +199,56 @@
`ifndef DBANK_LINE_SIZE_WORDS `ifndef DBANK_LINE_SIZE_WORDS
`define DBANK_LINE_SIZE_WORDS (`DBANK_LINE_SIZE_BYTES / `DWORD_SIZE_BYTES) `define DBANK_LINE_SIZE_WORDS (`DBANK_LINE_SIZE_BYTES / `DWORD_SIZE_BYTES)
`endif `endif
// Bank Number of words range
`ifndef DBANK_LINE_SIZE_RNG `ifndef DBANK_LINE_SIZE_RNG
`define DBANK_LINE_SIZE_RNG `DBANK_LINE_SIZE_WORDS-1:0 `define DBANK_LINE_SIZE_RNG `DBANK_LINE_SIZE_WORDS-1:0
`endif `endif
// Queues feeding into banks Knobs {1, 2, 4, 8, ...} // Queues feeding into banks Knobs {1, 2, 4, 8, ...}
// Core Request Queue Size // Core Request Queue Size
`ifndef DREQQ_SIZE `ifndef DREQQ_SIZE
`define DREQQ_SIZE `NW `define DREQQ_SIZE `NW
`endif `endif
// Miss Reserv Queue Knob // Miss Reserv Queue Knob
`ifndef DMRVQ_SIZE `ifndef DMRVQ_SIZE
`define DMRVQ_SIZE (`NW*`NT) `define DMRVQ_SIZE (`NW*`NT)
`endif `endif
// Dram Fill Rsp Queue Size // Dram Fill Rsp Queue Size
`ifndef DDFPQ_SIZE `ifndef DDFPQ_SIZE
`define DDFPQ_SIZE 2 `define DDFPQ_SIZE 2
`endif `endif
// Snoop Req Queue // Snoop Req Queue
`ifndef DSNRQ_SIZE `ifndef DSNRQ_SIZE
`define DSNRQ_SIZE 8 `define DSNRQ_SIZE 8
`endif `endif
// Queues for writebacks Knobs {1, 2, 4, 8, ...} // Queues for writebacks Knobs {1, 2, 4, 8, ...}
// Core Writeback Queue Size // Core Writeback Queue Size
`ifndef DCWBQ_SIZE `ifndef DCWBQ_SIZE
`define DCWBQ_SIZE `DREQQ_SIZE `define DCWBQ_SIZE `DREQQ_SIZE
`endif `endif
// Dram Writeback Queue Size // Dram Writeback Queue Size
`ifndef DDWBQ_SIZE `ifndef DDWBQ_SIZE
`define DDWBQ_SIZE 4 `define DDWBQ_SIZE 4
`endif `endif
// Dram Fill Req Queue Size // Dram Fill Req Queue Size
`ifndef DDFQQ_SIZE `ifndef DDFQQ_SIZE
`define DDFQQ_SIZE `DREQQ_SIZE `define DDFQQ_SIZE `DREQQ_SIZE
`endif `endif
// Lower Level Cache Hit Queue Size // Lower Level Cache Hit Queue Size
`ifndef DLLVQ_SIZE `ifndef DLLVQ_SIZE
`define DLLVQ_SIZE 0 `define DLLVQ_SIZE 0
`endif `endif
// Fill Forward SNP Queue // Fill Forward SNP Queue
`ifndef DFFSQ_SIZE `ifndef DFFSQ_SIZE
`define DFFSQ_SIZE 8 `define DFFSQ_SIZE 8
@@ -252,12 +264,10 @@
`define DSIMULATED_DRAM_LATENCY_CYCLES 10 `define DSIMULATED_DRAM_LATENCY_CYCLES 10
`endif `endif
// ========================================= Dcache Configurable Knobs =========================================
// ========================================= Icache Configurable Knobs ========================================= // ========================================= Icache Configurable Knobs =========================================
// General Cache Knobs // General Cache Knobs
// Size of cache in bytes // Size of cache in bytes
`ifndef ICACHE_SIZE_BYTES `ifndef ICACHE_SIZE_BYTES
`define ICACHE_SIZE_BYTES 1024 `define ICACHE_SIZE_BYTES 1024
@@ -298,6 +308,7 @@
`define IBANK_LINE_SIZE_WORDS (`IBANK_LINE_SIZE_BYTES / `IWORD_SIZE_BYTES) `define IBANK_LINE_SIZE_WORDS (`IBANK_LINE_SIZE_BYTES / `IWORD_SIZE_BYTES)
`endif `endif
// Bank Number of words range
`ifndef IBANK_LINE_SIZE_RNG `ifndef IBANK_LINE_SIZE_RNG
`define IBANK_LINE_SIZE_RNG `IBANK_LINE_SIZE_WORDS-1:0 `define IBANK_LINE_SIZE_RNG `IBANK_LINE_SIZE_WORDS-1:0
`endif `endif
@@ -361,8 +372,6 @@
`define ISIMULATED_DRAM_LATENCY_CYCLES 10 `define ISIMULATED_DRAM_LATENCY_CYCLES 10
`endif `endif
// ========================================= Icache Configurable Knobs =========================================
// ========================================= SM Configurable Knobs ========================================= // ========================================= SM Configurable Knobs =========================================
// General Cache Knobs // General Cache Knobs
@@ -469,13 +478,10 @@
`define SSIMULATED_DRAM_LATENCY_CYCLES 10 `define SSIMULATED_DRAM_LATENCY_CYCLES 10
`endif `endif
// ========================================= SM Configurable Knobs =========================================
// ========================================= L2cache Configurable Knobs ========================================= // ========================================= L2cache Configurable Knobs =========================================
// General Cache Knobs // General Cache Knobs
// Size of cache in bytes // Size of cache in bytes
`ifndef LLCACHE_SIZE_BYTES `ifndef LLCACHE_SIZE_BYTES
`define LLCACHE_SIZE_BYTES 1024 `define LLCACHE_SIZE_BYTES 1024
@@ -517,6 +523,7 @@
`ifndef LLBANK_LINE_SIZE_RNG `ifndef LLBANK_LINE_SIZE_RNG
`define LLBANK_LINE_SIZE_RNG `LLBANK_LINE_SIZE_WORDS-1:0 `define LLBANK_LINE_SIZE_RNG `LLBANK_LINE_SIZE_WORDS-1:0
`endif `endif
// Queues feeding into banks Knobs {1, 2, 4, 8, ...} // Queues feeding into banks Knobs {1, 2, 4, 8, ...}
// Core Request Queue Size // Core Request Queue Size
@@ -540,6 +547,7 @@
`endif `endif
// Queues for writebacks Knobs {1, 2, 4, 8, ...} // Queues for writebacks Knobs {1, 2, 4, 8, ...}
// Core Writeback Queue Size // Core Writeback Queue Size
`ifndef LLCWBQ_SIZE `ifndef LLCWBQ_SIZE
`define LLCWBQ_SIZE `LLREQQ_SIZE `define LLCWBQ_SIZE `LLREQQ_SIZE
@@ -575,11 +583,10 @@
`define LLSIMULATED_DRAM_LATENCY_CYCLES 10 `define LLSIMULATED_DRAM_LATENCY_CYCLES 10
`endif `endif
// ========================================= L2cache Configurable Knobs =========================================
// ========================================= L3cache Configurable Knobs ========================================= // ========================================= L3cache Configurable Knobs =========================================
// General Cache Knobs // General Cache Knobs
// Size of cache in bytes // Size of cache in bytes
`ifndef L3CACHE_SIZE_BYTES `ifndef L3CACHE_SIZE_BYTES
`define L3CACHE_SIZE_BYTES 1024 `define L3CACHE_SIZE_BYTES 1024
@@ -645,6 +652,7 @@
`endif `endif
// Queues for writebacks Knobs {1, 2, 4, 8, ...} // Queues for writebacks Knobs {1, 2, 4, 8, ...}
// Core Writeback Queue Size // Core Writeback Queue Size
`ifndef L3CWBQ_SIZE `ifndef L3CWBQ_SIZE
`define L3CWBQ_SIZE `L3REQQ_SIZE `define L3CWBQ_SIZE `L3REQQ_SIZE
@@ -680,7 +688,5 @@
`define L3SIMULATED_DRAM_LATENCY_CYCLES 10 `define L3SIMULATED_DRAM_LATENCY_CYCLES 10
`endif `endif
// ========================================= L3cache Configurable Knobs ========================================= // VX_DEFINE
`endif `endif