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minor fix.

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This commit is contained in:
Blaise Tine
2021-02-21 03:37:36 -08:00
parent 258eb633a6
commit 6d7692da37
1 changed files with 5 additions and 5 deletions
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10
hw/rtl/VX_decode.v
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@@ -208,12 +208,12 @@ module VX_decode #(
wire is_fpu = (is_fl || is_fs || is_fci || is_fr4); wire is_fpu = (is_fl || is_fs || is_fci || is_fr4);
reg [2:0] frm; reg [2:0] frm;
reg if_fsqrt; reg is_fsqrt;
always @(*) begin always @(*) begin
fpu_op = `FPU_MISC; fpu_op = `FPU_MISC;
frm = func3; frm = func3;
if_fsqrt = 0; is_fsqrt = 0;
if (is_fr4) begin if (is_fr4) begin
case ({is_fmadd, is_fmsub, is_fnmsub, is_fnmadd}) case ({is_fmadd, is_fmsub, is_fnmsub, is_fnmadd})
4'b1000: fpu_op = `FPU_MADD; 4'b1000: fpu_op = `FPU_MADD;
@@ -238,7 +238,7 @@ module VX_decode #(
end end
7'h2C: begin 7'h2C: begin
fpu_op = `FPU_SQRT; fpu_op = `FPU_SQRT;
if_fsqrt = 1; is_fsqrt = 1;
end end
7'h50: fpu_op = `FPU_CMP; // wb to intReg 7'h50: fpu_op = `FPU_CMP; // wb to intReg
7'h60: fpu_op = (instr[20]) ? `FPU_CVTWUS : `FPU_CVTWS; // doesn't need rs2, and read rs1 from fpReg, WB to intReg 7'h60: fpu_op = (instr[20]) ? `FPU_CVTWUS : `FPU_CVTWS; // doesn't need rs2, and read rs1 from fpReg, WB to intReg
@@ -309,8 +309,8 @@ module VX_decode #(
|| is_gpu || is_gpu
|| (is_jalr || is_btype || is_ltype || is_stype || is_itype || is_rtype || !is_csr_imm || is_gpu); || (is_jalr || is_btype || is_ltype || is_stype || is_itype || is_rtype || !is_csr_imm || is_gpu);
wire use_rs2 = (is_fpu && ~(is_fl || if_fsqrt || is_fcvti || is_fcvtf || is_fmvw_clss || is_fmvx)) wire use_rs2 = (is_fpu && ~(is_fl || is_fsqrt || is_fcvti || is_fcvtf || is_fmvw_clss || is_fmvx))
|| (is_gpu_bar || is_qpu_spawn) || (is_gpu && (is_gpu_bar || is_qpu_spawn))
|| (is_btype || is_stype || is_rtype); || (is_btype || is_stype || is_rtype);
wire use_rs3 = is_fr4; wire use_rs3 = is_fr4;