Restructure
This commit is contained in:
felsabbagh3
804
emulator/instruction.cpp
Normal file
804
emulator/instruction.cpp
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@@ -0,0 +1,804 @@
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/*******************************************************************************
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HARPtools by Chad D. Kersey, Summer 2011
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*******************************************************************************/
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#include <iostream>
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#include <stdlib.h>
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#include "include/instruction.h"
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#include "include/obj.h"
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#include "include/core.h"
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#include "include/harpfloat.h"
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#include "include/debug.h"
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#ifdef EMU_INSTRUMENTATION
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#include "include/qsim-harp.h"
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#endif
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using namespace Harp;
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using namespace std;
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/* It is important that this stays consistent with the Harp::Instruction::Opcode
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enum. */
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ostream &Harp::operator<<(ostream& os, Instruction &inst) {
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os << dec;
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// if (inst.predicated) {
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// os << "@p" << dec << inst.pred << " ? ";
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// }
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// os << inst.instTable[inst.op].opString << ' ';
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// if (inst.rdestPresent) os << "%r" << dec << inst.rdest << ' ';
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// if (inst.pdestPresent) os << "@p" << inst.pdest << ' ';
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// for (int i = 0; i < inst.nRsrc; i++) {
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// os << "%r" << dec << inst.rsrc[i] << ' ';
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// }
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// for (int i = 0; i < inst.nPsrc; i++) {
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// os << "@p" << dec << inst.psrc[i] << ' ';
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// }
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// if (inst.immsrcPresent) {
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// if (inst.refLiteral) os << inst.refLiteral->name;
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// else os << "#0x" << hex << inst.immsrc;
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// }
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os << instTable[inst.op].opString;
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os << ';';
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return os;
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}
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bool checkUnanimous(unsigned p, const std::vector<std::vector<Reg<Word> > >& m,
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const std::vector<bool> &tm) {
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bool same;
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unsigned i;
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for (i = 0; i < m.size(); ++i) {
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if (tm[i]) {
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same = m[i][p];
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break;
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}
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}
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if (i == m.size()) throw DivergentBranchException();
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//std::cout << "same: " << same << " with -> ";
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for (; i < m.size(); ++i) {
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if (tm[i]) {
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//std::cout << " " << (bool(m[i][p]));
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if (same != (bool(m[i][p]))) {
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//std::cout << " FALSE\n";
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return false;
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}
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}
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}
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//std::cout << " TRUE\n";
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return true;
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}
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Word signExt(Word w, Size bit, Word mask) {
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if (w>>(bit-1)) w |= ~mask;
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return w;
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}
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void Instruction::executeOn(Warp &c) {
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D(3, "Begin instruction execute.");
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/* If I try to execute a privileged instruction in user mode, throw an
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exception 3. */
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if (instTable[op].privileged && !c.supervisorMode) {
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std::cout << "INTERRUPT SUPERVISOR\n";
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c.interrupt(3);
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return;
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}
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// /* Also throw exceptions on non-masked divergent branches. */
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// if (instTable[op].controlFlow) {
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// Size t, count, active;
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// for (t = 0, count = 0, active = 0; t < c.activeThreads; ++t) {
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// if ((!predicated || c.pred[t][pred]) && c.tmask[t]) ++count;
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// if (c.tmask[t]) ++active;
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// }
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// if (count != 0 && count != active)
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// throw DivergentBranchException();
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// }
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Size nextActiveThreads = c.activeThreads;
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Size wordSz = c.core->a.getWordSize();
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Word nextPc = c.pc;
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c.memAccesses.clear();
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// If we have a load, overwriting a register's contents, we have to make sure
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// ahead of time it will not fault. Otherwise we may perform an indirect load
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// by mistake.
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// if (op == L_INST && rdest == rsrc[0]) {
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// for (Size t = 0; t < c.activeThreads; t++) {
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// if ((!predicated || c.pred[t][pred]) && c.tmask[t]) {
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// Word memAddr = c.reg[t][rsrc[0]] + immsrc;
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// c.core->mem.read(memAddr, c.supervisorMode);
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// }
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// }
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// }
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bool sjOnce(true), // Has not yet split or joined once.
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pcSet(false); // PC has already been set
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for (Size t = 0; t < c.activeThreads; t++) {
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vector<Reg<Word> > ®(c.reg[t]);
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vector<Reg<bool> > &pReg(c.pred[t]);
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stack<DomStackEntry> &domStack(c.domStack);
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//std::cout << std::hex << "opcode: " << op << " func3: " << func3 << "\n";
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//if (op == GPGPU) //std::cout << "OPCODE MATCHED GPGPU\n";
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// If this thread is masked out, don't execute the instruction, unless it's
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// a split or join.
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// if (((predicated && !pReg[pred]) || !c.tmask[t]) &&
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// op != SPLIT && op != JOIN) continue;
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bool split = (op == GPGPU) && (func3 == 2);
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bool join = (op == GPGPU) && (func3 == 3);
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predicated = (op == GPGPU) && ((func3 == 7) || (func3 == 2));
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// printf("Predicated: %d, split: %d, join: %d\n",predicated, split, join );
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// printf("%d && ((%d) || (%d))\n",(op == GPGPU), (func3 == 7), (func3 == 2) );
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// cout << "before " << op << " = " << GPGPU << "\n";
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if (((predicated && !reg[pred]) || !c.tmask[t]) && !split && !join)
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{
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// cout << "about to continue\n";
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continue;
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}
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// cout << "after\n";
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++c.insts;
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Word memAddr;
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Word shift_by;
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Word shamt;
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Word temp;
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Word data_read;
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int op1, op2;
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bool m_exten;
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// std::cout << "op = " << op << "\n";
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// std::cout << "R_INST: " << R_INST << "\n";
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switch (op) {
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case NOP:
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//std::cout << "NOP_INST\n";
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break;
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case R_INST:
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// std::cout << "R_INST\n";
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m_exten = func7 & 0x1;
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if (m_exten)
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{
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// std::cout << "FOUND A MUL/DIV\n";
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switch (func3)
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{
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case 0:
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// MUL
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// cout << "MUL\n";
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reg[rdest] = ((int) reg[rsrc[0]]) * ((int) reg[rsrc[1]]);
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break;
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case 1:
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// MULH
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{
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int64_t first = (int64_t) reg[rsrc[0]];
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if (reg[rsrc[0]] & 0x80000000)
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{
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first = first | 0xFFFFFFFF00000000;
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}
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int64_t second = (int64_t) reg[rsrc[1]];
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if (reg[rsrc[1]] & 0x80000000)
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{
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second = second | 0xFFFFFFFF00000000;
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}
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// cout << "mulh: " << std::dec << first << " * " << second;
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uint64_t result = first * second;
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reg[rdest] = ( result >> 32) & 0xFFFFFFFF;
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// cout << " = " << result << " or " << reg[rdest] << "\n";
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}
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break;
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case 2:
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// MULHSU
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{
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int64_t first = (int64_t) reg[rsrc[0]];
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if (reg[rsrc[0]] & 0x80000000)
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{
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first = first | 0xFFFFFFFF00000000;
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}
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int64_t second = (int64_t) reg[rsrc[1]];
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reg[rdest] = (( first * second ) >> 32) & 0xFFFFFFFF;
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}
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break;
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case 3:
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// MULHU
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{
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uint64_t first = (uint64_t) reg[rsrc[0]];
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uint64_t second = (uint64_t) reg[rsrc[1]];
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// cout << "MULHU\n";
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reg[rdest] = (( first * second) >> 32) & 0xFFFFFFFF;
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}
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break;
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case 4:
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// DIV
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if (reg[rsrc[1]] == 0)
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{
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reg[rdest] = -1;
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break;
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}
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// cout << "dividing: " << dec << ((int) reg[rsrc[0]]) << " / " << ((int) reg[rsrc[1]]);
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reg[rdest] = ( (int) reg[rsrc[0]]) / ( (int) reg[rsrc[1]]);
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// cout << " = " << ((int) reg[rdest]) << "\n";
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break;
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case 5:
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// DIVU
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if (reg[rsrc[1]] == 0)
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{
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reg[rdest] = -1;
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break;
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}
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reg[rdest] = ((uint32_t) reg[rsrc[0]]) / ((uint32_t) reg[rsrc[1]]);
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break;
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case 6:
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// REM
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if (reg[rsrc[1]] == 0)
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{
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reg[rdest] = reg[rsrc[0]];
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break;
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}
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reg[rdest] = ((int) reg[rsrc[0]]) % ((int) reg[rsrc[1]]);
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break;
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case 7:
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// REMU
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if (reg[rsrc[1]] == 0)
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{
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reg[rdest] = reg[rsrc[0]];
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break;
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}
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reg[rdest] = ((uint32_t) reg[rsrc[0]]) % ((uint32_t) reg[rsrc[1]]);
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break;
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default:
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cout << "unsupported MUL/DIV instr\n";
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exit(1);
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}
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}
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else
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{
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// std::cout << "NORMAL R-TYPE\n";
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switch (func3)
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{
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case 0:
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if (func7)
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{
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reg[rdest] = reg[rsrc[0]] - reg[rsrc[1]];
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reg[rdest].trunc(wordSz);
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}
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else
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{
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reg[rdest] = reg[rsrc[0]] + reg[rsrc[1]];
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reg[rdest].trunc(wordSz);
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}
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break;
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case 1:
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reg[rdest] = reg[rsrc[0]] << reg[rsrc[1]];
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reg[rdest].trunc(wordSz);
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break;
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case 2:
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if ( int(reg[rsrc[0]]) < int(reg[rsrc[1]]))
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{
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reg[rdest] = 1;
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}
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else
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{
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reg[rdest] = 0;
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}
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break;
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case 3:
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if ( Word_u(reg[rsrc[0]]) < Word_u(reg[rsrc[1]]))
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{
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reg[rdest] = 1;
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}
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else
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{
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reg[rdest] = 0;
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}
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break;
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case 4:
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reg[rdest] = reg[rsrc[0]] ^ reg[rsrc[1]];
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break;
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case 5:
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if (func7)
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{
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reg[rdest] = int(reg[rsrc[0]]) >> int(reg[rsrc[1]]);
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reg[rdest].trunc(wordSz);
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}
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else
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{
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reg[rdest] = Word_u(reg[rsrc[0]]) >> Word_u(reg[rsrc[1]]);
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reg[rdest].trunc(wordSz);
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}
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break;
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case 6:
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reg[rdest] = reg[rsrc[0]] | reg[rsrc[1]];
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break;
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case 7:
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reg[rdest] = reg[rsrc[0]] & reg[rsrc[1]];
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break;
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default:
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cout << "ERROR: UNSUPPORTED R INST\n";
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exit(1);
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}
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}
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break;
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case L_INST:
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//std::cout << "L_INST\n";
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memAddr = ((reg[rsrc[0]] + immsrc) & 0xFFFFFFFC);
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shift_by = ((reg[rsrc[0]] + immsrc) & 0x00000003) * 8;
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data_read = c.core->mem.read(memAddr, c.supervisorMode);
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// //std::cout <<std::hex<< "EXECUTE: " << reg[rsrc[0]] << " + " << immsrc << " = " << memAddr << " -> data_read: " << data_read << "\n";
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#ifdef EMU_INSTRUMENTATION
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Harp::OSDomain::osDomain->
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do_mem(0, memAddr, c.core->mem.virtToPhys(memAddr), 8, true);
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#endif
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switch (func3)
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{
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case 0:
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// LB
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reg[rdest] = signExt((data_read >> shift_by) & 0xFF, 8, 0xFF);
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break;
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case 1:
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// LH
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// //std::cout << "shifting by: " << shift_by << " final data: " << ((data_read >> shift_by) & 0xFFFF, 16, 0xFFFF) << "\n";
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reg[rdest] = signExt((data_read >> shift_by) & 0xFFFF, 16, 0xFFFF);
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break;
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case 2:
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reg[rdest] = int(data_read & 0xFFFFFFFF);
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break;
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case 4:
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// LBU
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reg[rdest] = unsigned((data_read >> shift_by) & 0xFF);
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break;
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case 5:
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reg[rdest] = unsigned((data_read >> shift_by) & 0xFFFF);
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break;
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default:
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cout << "ERROR: UNSUPPORTED L INST\n";
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exit(1);
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c.memAccesses.push_back(Warp::MemAccess(false, memAddr));
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}
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break;
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case I_INST:
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//std::cout << "I_INST\n";
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switch (func3)
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{
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case 0:
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// ADDI
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reg[rdest] = reg[rsrc[0]] + immsrc;
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reg[rdest].trunc(wordSz);
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break;
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case 2:
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// SLTI
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if ( int(reg[rsrc[0]]) < int(immsrc))
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{
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reg[rdest] = 1;
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}
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else
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{
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reg[rdest] = 0;
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}
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break;
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case 3:
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// SLTIU
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op1 = (unsigned) reg[rsrc[0]];
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if ( unsigned(reg[rsrc[0]]) < unsigned(immsrc))
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{
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reg[rdest] = 1;
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}
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else
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{
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reg[rdest] = 0;
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}
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break;
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case 4:
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// XORI
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reg[rdest] = reg[rsrc[0]] ^ immsrc;
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break;
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case 6:
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// ORI;
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reg[rdest] = reg[rsrc[0]] | immsrc;
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break;
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case 7:
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// ANDI
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reg[rdest] = reg[rsrc[0]] & immsrc;
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break;
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case 1:
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// SLLI
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reg[rdest] = reg[rsrc[0]] << immsrc;
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reg[rdest].trunc(wordSz);
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break;
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case 5:
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if ((func7 == 0))
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{
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// SRLI
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// //std::cout << "WTF\n";
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bool isNeg = ((0x80000000 & reg[rsrc[0]])) > 0;
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Word result = Word_u(reg[rsrc[0]]) >> Word_u(immsrc);
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// if (isNeg)
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// {
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// Word mask = 0x80000000;
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// for (int i = 32; i < Word_u(immsrc); i++)
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// {
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// result |= mask;
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// mask = mask >> 1;
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// }
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// }
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reg[rdest] = result;
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reg[rdest].trunc(wordSz);
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}
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else
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{
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// SRAI
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// //std::cout << "WOHOOOOO\n";
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op1 = reg[rsrc[0]];
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op2 = immsrc;
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reg[rdest] = op1 >> op2;
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reg[rdest].trunc(wordSz);
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}
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break;
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default:
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cout << "ERROR: UNSUPPORTED L INST\n";
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exit(1);
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}
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break;
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case S_INST:
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//std::cout << "S_INST\n";
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++c.stores;
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memAddr = reg[rsrc[0]] + immsrc;
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// //std::cout << "STORE MEM ADDRESS: " << std::hex << reg[rsrc[0]] << " + " << immsrc << "\n";
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// //std::cout << "FUNC3: " << func3 << "\n";
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if (memAddr == 0x00010000)
|
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{
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std::cout << (char) reg[rsrc[1]];
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||||
break;
|
||||
}
|
||||
switch (func3)
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||||
{
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||||
case 0:
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// //std::cout << "SB\n";
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c.core->mem.write(memAddr, reg[rsrc[1]] & 0x000000FF, c.supervisorMode, 1);
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||||
break;
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||||
case 1:
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// //std::cout << "SH\n";
|
||||
c.core->mem.write(memAddr, reg[rsrc[1]], c.supervisorMode, 2);
|
||||
break;
|
||||
case 2:
|
||||
// //std::cout << std::hex << "SW: about to write: " << reg[rsrc[1]] << " to " << memAddr << "\n";
|
||||
c.core->mem.write(memAddr, reg[rsrc[1]], c.supervisorMode, 4);
|
||||
break;
|
||||
default:
|
||||
cout << "ERROR: UNSUPPORTED S INST\n";
|
||||
exit(1);
|
||||
}
|
||||
c.memAccesses.push_back(Warp::MemAccess(true, memAddr));
|
||||
#ifdef EMU_INSTRUMENTATION
|
||||
Harp::OSDomain::osDomain->
|
||||
do_mem(0, memAddr, c.core->mem.virtToPhys(memAddr), 8, true);
|
||||
#endif
|
||||
break;
|
||||
case B_INST:
|
||||
//std::cout << "B_INST\n";
|
||||
switch (func3)
|
||||
{
|
||||
case 0:
|
||||
// BEQ
|
||||
if (int(reg[rsrc[0]]) == int(reg[rsrc[1]]))
|
||||
{
|
||||
if (!pcSet) nextPc = (c.pc - 4) + immsrc;
|
||||
pcSet = true;
|
||||
}
|
||||
break;
|
||||
case 1:
|
||||
// BNE
|
||||
if (int(reg[rsrc[0]]) != int(reg[rsrc[1]]))
|
||||
{
|
||||
if (!pcSet) nextPc = (c.pc - 4) + immsrc;
|
||||
pcSet = true;
|
||||
}
|
||||
break;
|
||||
case 4:
|
||||
// BLT
|
||||
if (int(reg[rsrc[0]]) < int(reg[rsrc[1]]))
|
||||
{
|
||||
if (!pcSet) nextPc = (c.pc - 4) + immsrc;
|
||||
pcSet = true;
|
||||
}
|
||||
break;
|
||||
case 5:
|
||||
// BGE
|
||||
if (int(reg[rsrc[0]]) >= int(reg[rsrc[1]]))
|
||||
{
|
||||
if (!pcSet) nextPc = (c.pc - 4) + immsrc;
|
||||
pcSet = true;
|
||||
}
|
||||
break;
|
||||
case 6:
|
||||
// BLTU
|
||||
if (Word_u(reg[rsrc[0]]) < Word_u(reg[rsrc[1]]))
|
||||
{
|
||||
if (!pcSet) nextPc = (c.pc - 4) + immsrc;
|
||||
pcSet = true;
|
||||
}
|
||||
break;
|
||||
case 7:
|
||||
// BGEU
|
||||
if (Word_u(reg[rsrc[0]]) >= Word_u(reg[rsrc[1]]))
|
||||
{
|
||||
if (!pcSet) nextPc = (c.pc - 4) + immsrc;
|
||||
pcSet = true;
|
||||
}
|
||||
break;
|
||||
}
|
||||
break;
|
||||
case LUI_INST:
|
||||
//std::cout << "LUI_INST\n";
|
||||
reg[rdest] = (immsrc << 12) & 0xfffff000;
|
||||
break;
|
||||
case AUIPC_INST:
|
||||
//std::cout << "AUIPC_INST\n";
|
||||
reg[rdest] = ((immsrc << 12) & 0xfffff000) + (c.pc - 4);
|
||||
break;
|
||||
case JAL_INST:
|
||||
//std::cout << "JAL_INST\n";
|
||||
if (!pcSet) nextPc = (c.pc - 4) + immsrc;
|
||||
if (!pcSet) //std::cout << "JAL... SETTING PC: " << nextPc << "\n";
|
||||
if (rdest != 0)
|
||||
{
|
||||
reg[rdest] = c.pc;
|
||||
}
|
||||
pcSet = true;
|
||||
break;
|
||||
case JALR_INST:
|
||||
//std::cout << "JALR_INST\n";
|
||||
if (!pcSet) nextPc = reg[rsrc[0]] + immsrc;
|
||||
if (!pcSet) //std::cout << "JALR... SETTING PC: " << nextPc << "\n";
|
||||
if (rdest != 0)
|
||||
{
|
||||
reg[rdest] = c.pc;
|
||||
}
|
||||
pcSet = true;
|
||||
break;
|
||||
case SYS_INST:
|
||||
//std::cout << "SYS_INST\n";
|
||||
temp = reg[rsrc[0]];
|
||||
switch (func3)
|
||||
{
|
||||
case 1:
|
||||
// printf("Case 1\n");
|
||||
if (rdest != 0)
|
||||
{
|
||||
reg[rdest] = c.csr[immsrc & 0x00000FFF];
|
||||
}
|
||||
c.csr[immsrc & 0x00000FFF] = temp;
|
||||
|
||||
break;
|
||||
case 2:
|
||||
// printf("Case 2\n");
|
||||
if (rdest != 0)
|
||||
{
|
||||
// printf("Reading from CSR: %d = %d\n", (immsrc & 0x00000FFF), c.csr[immsrc & 0x00000FFF]);
|
||||
reg[rdest] = c.csr[immsrc & 0x00000FFF];
|
||||
}
|
||||
// printf("Writing to CSR --> %d = %d\n", immsrc, (temp | c.csr[immsrc & 0x00000FFF]));
|
||||
c.csr[immsrc & 0x00000FFF] = temp | c.csr[immsrc & 0x00000FFF];
|
||||
|
||||
break;
|
||||
case 3:
|
||||
// printf("Case 3\n");
|
||||
if (rdest != 0)
|
||||
{
|
||||
reg[rdest] = c.csr[immsrc & 0x00000FFF];
|
||||
}
|
||||
c.csr[immsrc & 0x00000FFF] = temp & (~c.csr[immsrc & 0x00000FFF]);
|
||||
|
||||
break;
|
||||
case 5:
|
||||
// printf("Case 5\n");
|
||||
if (rdest != 0)
|
||||
{
|
||||
reg[rdest] = c.csr[immsrc & 0x00000FFF];
|
||||
}
|
||||
c.csr[immsrc & 0x00000FFF] = rsrc[0];
|
||||
|
||||
break;
|
||||
case 6:
|
||||
// printf("Case 6\n");
|
||||
if (rdest != 0)
|
||||
{
|
||||
reg[rdest] = c.csr[immsrc & 0x00000FFF];
|
||||
}
|
||||
c.csr[immsrc & 0x00000FFF] = rsrc[0] | c.csr[immsrc & 0x00000FFF];
|
||||
|
||||
break;
|
||||
case 7:
|
||||
// printf("Case 7\n");
|
||||
if (rdest != 0)
|
||||
{
|
||||
reg[rdest] = c.csr[immsrc & 0x00000FFF];
|
||||
}
|
||||
c.csr[immsrc & 0x00000FFF] = rsrc[0] & (~c.csr[immsrc & 0x00000FFF]);
|
||||
|
||||
break;
|
||||
case 0:
|
||||
if (immsrc < 2)
|
||||
{
|
||||
//std::cout << "INTERRUPT ECALL/EBREAK\n";
|
||||
nextActiveThreads = 0;
|
||||
c.spawned = false;
|
||||
// c.interrupt(0);
|
||||
}
|
||||
break;
|
||||
default:
|
||||
break;
|
||||
}
|
||||
break;
|
||||
case TRAP:
|
||||
//std::cout << "INTERRUPT TRAP\n";
|
||||
nextActiveThreads = 0;
|
||||
c.interrupt(0);
|
||||
break;
|
||||
case FENCE:
|
||||
//std::cout << "FENCE_INST\n";
|
||||
break;
|
||||
case PJ_INST:
|
||||
// pred jump reg
|
||||
//std::cout << "pred jump... src: " << rsrc[0] << std::hex << " val: " << reg[rsrc[0]] << " dest: " << reg[rsrc[1]] << "\n";
|
||||
if (reg[rsrc[0]])
|
||||
{
|
||||
if (!pcSet) nextPc = reg[rsrc[1]];
|
||||
pcSet = true;
|
||||
}
|
||||
break;
|
||||
case GPGPU:
|
||||
//std::cout << "GPGPU\n";
|
||||
switch(func3)
|
||||
{
|
||||
case 0:
|
||||
// WSPAWN
|
||||
//std::cout << "WSPAWN\n";
|
||||
if (sjOnce)
|
||||
{
|
||||
sjOnce = false;
|
||||
D(0, "Spawning a new warp.");
|
||||
// //std::cout << "SIZE: " << c.core->w.size() << "\n";
|
||||
for (unsigned i = 0; i < c.core->w.size(); ++i)
|
||||
{
|
||||
// std::cout << "SPAWNING WARP\n";
|
||||
Warp &newWarp(c.core->w[i]);
|
||||
// //std::cout << "STARTING\n";
|
||||
if (newWarp.spawned == false) {
|
||||
// //std::cout << "ABOUT TO START\n";
|
||||
newWarp.pc = reg[rsrc[0]];
|
||||
newWarp.reg[0] = reg;
|
||||
newWarp.csr = c.csr;
|
||||
newWarp.activeThreads = 1;
|
||||
newWarp.supervisorMode = false;
|
||||
newWarp.spawned = true;
|
||||
break;
|
||||
}
|
||||
}
|
||||
}
|
||||
break;
|
||||
case 2:
|
||||
{
|
||||
// SPLIT
|
||||
//std::cout << "SPLIT\n";
|
||||
if (sjOnce)
|
||||
{
|
||||
sjOnce = false;
|
||||
if (checkUnanimous(pred, c.reg, c.tmask)) {
|
||||
//std::cout << "Unanimous pred: " << pred << " val: " << reg[pred] << "\n";
|
||||
DomStackEntry e(c.tmask);
|
||||
e.uni = true;
|
||||
c.domStack.push(e);
|
||||
break;
|
||||
}
|
||||
DomStackEntry e(pred, c.reg, c.tmask, c.pc);
|
||||
c.domStack.push(c.tmask);
|
||||
c.domStack.push(e);
|
||||
for (unsigned i = 0; i < e.tmask.size(); ++i)
|
||||
{
|
||||
c.tmask[i] = !e.tmask[i] && c.tmask[i];
|
||||
}
|
||||
}
|
||||
}
|
||||
break;
|
||||
case 3:
|
||||
// JOIN
|
||||
//std::cout << "JOIN\n";
|
||||
if (sjOnce)
|
||||
{
|
||||
sjOnce = false;
|
||||
if (!c.domStack.empty() && c.domStack.top().uni) {
|
||||
D(2, "Uni branch at join");
|
||||
c.tmask = c.domStack.top().tmask;
|
||||
c.domStack.pop();
|
||||
break;
|
||||
}
|
||||
if (!c.domStack.top().fallThrough) {
|
||||
if (!pcSet) nextPc = c.domStack.top().pc;
|
||||
pcSet = true;
|
||||
}
|
||||
c.tmask = c.domStack.top().tmask;
|
||||
c.domStack.pop();
|
||||
}
|
||||
break;
|
||||
case 4:
|
||||
// JMPRT
|
||||
//std::cout << "JMPRT\n";
|
||||
nextActiveThreads = 1;
|
||||
if (!pcSet) nextPc = reg[rsrc[0]];
|
||||
pcSet = true;
|
||||
break;
|
||||
case 5:
|
||||
// CLONE
|
||||
//std::cout << "CLONE\n";
|
||||
// //std::cout << "CLONING REG: " << rsrc[0] << " lane: " << reg[rsrc[0]] << "\n";
|
||||
c.reg[reg[rsrc[0]]] = reg;
|
||||
break;
|
||||
case 6:
|
||||
// JALRS
|
||||
//std::cout << "JALRS\n";
|
||||
nextActiveThreads = reg[rsrc[1]];
|
||||
reg[rdest] = c.pc;
|
||||
if (!pcSet) nextPc = reg[rsrc[0]];
|
||||
pcSet = true;
|
||||
// //std::cout << "ACTIVE_THREDS: " << rsrc[1] << " val: " << reg[rsrc[1]] << "\n";
|
||||
// //std::cout << "nextPC: " << rsrc[0] << " val: " << std::hex << reg[rsrc[0]] << "\n";
|
||||
break;
|
||||
default:
|
||||
cout << "ERROR: UNSUPPORTED GPGPU INSTRUCTION " << *this << "\n";
|
||||
}
|
||||
break;
|
||||
default:
|
||||
cout << "pc: " << hex << (c.pc) << "\n";
|
||||
cout << "aERROR: Unsupported instruction: " << *this << "\n" << flush;
|
||||
exit(1);
|
||||
}
|
||||
}
|
||||
|
||||
D(3, "End instruction execute.");
|
||||
|
||||
c.activeThreads = nextActiveThreads;
|
||||
|
||||
// if (nextActiveThreads != 0)
|
||||
// {
|
||||
// for (int i = 7; i >= c.activeThreads; i--)
|
||||
// {
|
||||
// c.tmask[i] = c.tmask[i] && false;
|
||||
// }
|
||||
// }
|
||||
|
||||
|
||||
|
||||
// //std::cout << "new thread mask: ";
|
||||
// for (int i = 0; i < c.tmask.size(); ++i) //std::cout << " " << c.tmask[i];
|
||||
// //std::cout << "\n";
|
||||
|
||||
// This way, if pc was set by a side effect (such as interrupt), it will
|
||||
// retain its new value.
|
||||
if (pcSet) c.pc = nextPc;
|
||||
|
||||
if (nextActiveThreads > c.reg.size()) {
|
||||
cerr << "Error: attempt to spawn " << nextActiveThreads << " threads. "
|
||||
<< c.reg.size() << " available.\n";
|
||||
abort();
|
||||
}
|
||||
}
|
||||
Reference in New Issue
Block a user