Restructure

emulator/LICENSE

@@ -0,0 +1,12 @@
+Copyright (c) 2011, Georgia Institute of Technology
+All rights reserved.
+
+Redistribution and use in source and binary forms, with or without modification, are permitted provided that the following conditions are met:
+
+1. Redistributions of source code must retain the above copyright notice, this list of conditions and the following disclaimer.
+
+2. Redistributions in binary form must reproduce the above copyright notice, this list of conditions and the following disclaimer in the documentation and/or other materials provided with the distribution.
+
+3. Neither the name of the copyright holder nor the names of its contributors may be used to endorse or promote products derived from this software without specific prior written permission.
+
+THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.

emulator/Makefile

@@ -0,0 +1,54 @@
+################################################################################
+# HARPtools by Chad D. Kersey, Summer 2011                                     #
+################################################################################
+CXXFLAGS ?= -std=c++11 -fPIC -O3 # -g -DUSE_DEBUG=3 -DPRINT_ACTIVE_THREADS
+LDLIBS ?= -pthread
+PREFIX ?= /usr/local
+
+LIB_OBJS=args.o mem.o core.o instruction.o enc.o util.o
+
+all: harptool libharplib.so libharplib.a #libqsim-harp.so
+
+# Use -static so we don't have to install the library in order to just run
+# Harptool.
+harptool: harptool.o libharplib.a
+	$(CXX) $(LDFLAGS) -o $@ harptool.o libharplib.a $(LDLIBS)
+
+libharplib.so: $(LIB_OBJS)
+	$(CXX) -shared -o $@ $(LIB_OBJS) $(LDLIBS)
+
+libharplib.a: $(LIB_OBJS)
+	ar rcs $@ $(LIB_OBJS)
+
+args.o : args.cpp include/args.h
+enc.o : enc.cpp include/types.h include/util.h include/enc.h include/archdef.h\
+                include/instruction.h
+harptool.o : harptool.cpp include/types.h include/core.h include/enc.h \
+             include/instruction.h include/mem.h include/obj.h \
+             include/archdef.h include/args.h include/help.h include/debug.h
+instruction.o : instruction.cpp include/instruction.h include/obj.h \
+                include/core.h include/debug.h include/asm-tokens.h
+util.o : util.cpp include/types.h include/util.h
+mem.o : mem.cpp include/types.h include/util.h include/mem.h include/debug.h \
+        include/core.h
+core.o : core.cpp include/types.h include/util.h include/mem.h \
+         include/debug.h include/archdef.h include/core.h
+
+#QSIM_CXXFLAGS=-DEMU_INSTRUMENTATION
+#
+#libqsim-harp.so: args.cpp enc.cpp instruction.cpp obj.cpp util.cpp mem.cpp \
+#                 core.cpp qsim-harp.cpp lex.yy.o include/qsim-harp.h \
+#                 include/types.h include/core.h include/util.h include/enc.h \
+#                 include/archdef.h include/instruction.h include/asm-tokens.h \
+#                 include/mem.h
+#	$(CXX) $(CXXFLAGS) $(QSIM_CXXFLAGS) -shared -o $@ $^
+
+
+install:
+	cp libharplib.so $(PREFIX)/lib
+	cp harptool $(PREFIX)/bin
+	mkdir -p $(PREFIX)/include/harp
+	cp include/* $(PREFIX)/include/harp
+
+clean:
+	rm -f *~ \#* *.o *.a *.so include/*~ include/\#* harptool

emulator/WISHLIST

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+- Anonymous chunks whose names are not saved by the object writer.
+- 32-bit instruction encoding for larger-pointered architecture versions.
+- HOFDump mode for HARPTool/HOFTool
+- Make operation information tables into member functions of Instruction, if
+  possible.
+- Anonymous assigned values in the assembler.
+- References (pointers) as .word directive contents in the assembler.
+- Instruction validation before encoding.
+- Make readError in obj.cpp throw something instead of printing a message and
+  exiting.
+- Limit checking for byte/word encoders (e.g. 255 pRegs, 256 regs for byte)
+- Eliminate the tmp_buf nonsense from the chunk encoder.
+- Loosen arch restrictions imposed for interoperability (the number of lanes is
+  typically unimportant)

emulator/args.cpp

@@ -0,0 +1,52 @@
+/*******************************************************************************
+ HARPtools by Chad D. Kersey, Summer 2011
+*******************************************************************************/
+#include "include/args.h"
+
+#include <iostream>
+#include <string>
+
+using namespace HarpTools;
+using std::string;
+
+std::string CommandLineArg::helpString;
+std::map<string, CommandLineArg *> CommandLineArg::longArgs;
+std::map<string, CommandLineArg *> CommandLineArg::shortArgs;
+
+CommandLineArg::CommandLineArg(string s, string l, const char *helpText)
+{
+  helpString += helpText;
+  longArgs[l] = this;
+  shortArgs[s] = this;
+}
+
+CommandLineArg::CommandLineArg(string l, const char *helpText) {
+  helpString += helpText;
+  longArgs[l] = this;
+}
+
+void CommandLineArg::readArgs(int argc, char **argv) {
+  for (int i = 0; i < argc; i++) {
+    std::map<string, CommandLineArg *>::iterator 
+      s = shortArgs.find(std::string(argv[i])), 
+      l = longArgs.find(std::string(argv[i]));
+
+    if (s != shortArgs.end()) {
+      i += s->second->read(argc - i, &argv[i]);
+    } else if (l != longArgs.end()) {
+      i += l->second->read(argc - i, &argv[i]);
+    } else {
+      throw BadArg(string(argv[i]));
+    }
+  }
+}
+
+void CommandLineArg::clearArgs() {
+  shortArgs.clear();
+  longArgs.clear();
+  helpString = "";
+}
+
+void CommandLineArg::showHelp(std::ostream &os) {
+  os << helpString;
+}

emulator/core.cpp

@@ -0,0 +1,264 @@
+/*******************************************************************************
+ HARPtools by Chad D. Kersey, Summer 2011
+*******************************************************************************/
+
+#include <iostream>
+
+// #define USE_DEBUG 7
+// #define PRINT_ACTIVE_THREADS
+
+#include "include/types.h"
+#include "include/util.h"
+#include "include/archdef.h"
+#include "include/mem.h"
+#include "include/enc.h"
+#include "include/core.h"
+#include "include/debug.h"
+
+#ifdef EMU_INSTRUMENTATION
+#include "include/qsim-harp.h"
+#endif
+
+using namespace Harp;
+using namespace std;
+
+#ifdef EMU_INSTRUMENTATION
+void Harp::reg_doRead(Word cpuId, Word regNum) {
+  Harp::OSDomain::osDomain->do_reg(cpuId, regNum, 8, true);
+}
+
+void Harp::reg_doWrite(Word cpuId, Word regNum) {
+  Harp::OSDomain::osDomain->do_reg(cpuId, regNum, 8, false);
+}
+#endif
+
+Core::Core(const ArchDef &a, Decoder &d, MemoryUnit &mem, Word id):
+  a(a), iDec(d), mem(mem), steps(0)
+{
+  for (unsigned i = 0; i < a.getNWarps(); ++i)
+    w.push_back(Warp(this));
+
+  w[0].activeThreads = 1;
+  w[0].spawned = true;
+}
+
+bool Core::interrupt(Word r0) {
+  w[0].interrupt(r0);
+}
+
+void Core::step() {
+  ++steps;
+
+  #ifdef PRINT_ACTIVE_THREADS
+  cout << endl << "Threads:";
+  #endif
+
+  for (unsigned i = 0; i < w.size(); ++i) {
+    if (w[i].activeThreads) {
+      D(3, "Core step stepping warp " << i << '[' << w[i].activeThreads << ']');
+      w[i].step();
+      D(3, "Now " << w[i].activeThreads << " active threads in " << i);
+    }
+   
+    #ifdef PRINT_ACTIVE_THREADS
+    for (unsigned j = 0; j < w[i].tmask.size(); ++j) {
+      if (w[i].activeThreads > j && w[i].tmask[j]) cout << " 1";
+      else cout << " 0";
+      if (j != w[i].tmask.size()-1 || i != w.size()-1) cout << ',';
+    }
+    #endif
+  }
+  #ifdef PRINT_ACTIVE_THREADS
+  cout << endl;
+  #endif
+}
+
+bool Core::running() const {
+  for (unsigned i = 0; i < w.size(); ++i)
+    if (w[i].running()) return true;
+  return false;
+}
+
+void Core::printStats() const {
+  unsigned long insts = 0;
+  for (unsigned i = 0; i < w.size(); ++i)
+    insts += w[i].insts;
+
+  cout << "Total steps: " << steps << endl;
+  cout << "Total insts: " << insts << endl;
+  for (unsigned i = 0; i < w.size(); ++i) {
+    cout << "=== Warp " << i << " ===" << endl;
+    w[i].printStats();
+  }
+}
+
+Warp::Warp(Core *c, Word id) : 
+  core(c), pc(0), interruptEnable(true),
+  supervisorMode(true), activeThreads(0), reg(0), pred(0),
+  shadowReg(core->a.getNRegs()), shadowPReg(core->a.getNPRegs()), id(id),
+  spawned(false), steps(0), insts(0), loads(0), stores(0)
+{
+  /* Build the register file. */
+  Word regNum(0);
+  for (Word j = 0; j < core->a.getNThds(); ++j) {
+    reg.push_back(vector<Reg<Word> >(0));
+    for (Word i = 0; i < core->a.getNRegs(); ++i) {
+      reg[j].push_back(Reg<Word>(id, regNum++));
+    }
+
+    pred.push_back(vector<Reg<bool> >(0));
+    for (Word i = 0; i < core->a.getNPRegs(); ++i) {
+      pred[j].push_back(Reg<bool>(id, regNum++));
+    }
+
+    tmask.push_back(true);
+    shadowTmask.push_back(true);
+  }
+
+  Word csrNum(0);
+  for (Word i = 0; i < (1<<12); i++)
+  {
+    csr.push_back(Reg<uint16_t>(id, regNum++));
+  }
+
+  /* Set initial register contents. */
+  reg[0][0] = (core->a.getNThds()<<(core->a.getWordSize()*8 / 2)) | id;
+}
+
+void Warp::step() {
+  Size fetchPos(0), decPos, wordSize(core->a.getWordSize());
+  vector<Byte> fetchBuffer(wordSize);
+
+  if (activeThreads == 0) return;
+
+  ++steps;
+  
+  D(3, "in step pc=0x" << hex << pc);
+
+  // std::cout << "pc: " << hex << pc << "\n";
+
+  /* Fetch and decode. */
+  if (wordSize < sizeof(pc)) pc &= ((1ll<<(wordSize*8))-1);
+  Instruction *inst;
+  bool fetchMore;
+  do {
+    /* Todo: speed this up for the byte encoder? */
+    try {
+      fetchMore = false;
+      unsigned fetchSize(wordSize - (pc+fetchPos)%wordSize);
+      fetchBuffer.resize(fetchPos + fetchSize);
+      Word fetched = core->mem.fetch(pc + fetchPos, supervisorMode);
+      writeWord(fetchBuffer, fetchPos, fetchSize, fetched);
+      decPos = 0;
+      inst = core->iDec.decode(fetchBuffer, decPos);
+    } catch (OutOfBytes o) {
+      D(3, "Caught OutOfBytes. Fetching more.");
+      fetchMore = true;
+    } catch (MemoryUnit::PageFault pf) {
+      fetchPos = 0;
+      fetchMore = true;
+      interrupt(pf.notFound?1:2);
+      reg[0][1] = pf.faultAddr;
+    }
+  } while (fetchMore);
+  D(3, "Fetched at 0x" << hex << pc);
+  D(3, "0x" << hex << pc << ": " << *inst);
+
+#ifdef EMU_INSTRUMENTATION
+  { Addr pcPhys(core->mem.virtToPhys(pc));
+    Harp::OSDomain::osDomain->
+      do_inst(0, pc, pcPhys, decPos, core->mem.getPtr(pcPhys, decPos), 
+              (enum inst_type)inst->instTable[inst->getOpcode()].iType);
+  }
+#endif
+
+  // Update pc
+  pc += decPos;
+
+  // Execute
+  try {
+    inst->executeOn(*this);
+  } catch (MemoryUnit::PageFault pf) {
+    D(2, "Interrupt: Page fault");
+    pc -= decPos; /* Reset to beginning of faulting address. */
+    interrupt(pf.notFound?1:2);
+    reg[0][1] = pf.faultAddr;
+  } catch (DivergentBranchException e) {
+    D(2, "Interrupt 4: Divergent branch");
+    pc -= decPos;
+    interrupt(4);
+  } catch (DomainException e) {
+    D(2, "Interrupt: DomainException");
+    interrupt(5);
+  }
+ 
+  // At Debug Level 3, print debug info after each instruction.
+  #ifdef USE_DEBUG
+  if (USE_DEBUG >= 3) {
+    D(3, "Register state:");
+    for (unsigned i = 0; i < reg[0].size(); ++i) {
+      D_RAW("  %r" << dec << i << ':');
+      for (unsigned j = 0; j < reg.size(); ++j) 
+        D_RAW(' ' << hex << reg[j][i] << ' ');
+      D_RAW('(' << shadowReg[i] << ')' << endl);
+    }
+    // D(3, "Predicate state:");
+    // D_RAW("  ");
+    // for (unsigned j = 0; j < pred.size(); ++j) {
+    //   for (unsigned i = 0; i < pred[j].size(); ++i) D_RAW(pred[j][i]);
+    //   D_RAW(endl);
+    // }
+    // D_RAW(" (");
+    // for (unsigned i = 0; i < shadowPReg.size(); ++i) D_RAW(shadowPReg[i]);
+    // D_RAW(')' << endl);
+
+    D(3, "Thread mask:");
+    D_RAW("  ");
+    for (unsigned i = 0; i < tmask.size(); ++i) D_RAW(tmask[i] << ' ');
+    D_RAW(endl);
+    D_RAW(endl);
+    D_RAW(endl);
+  }
+  #endif
+
+  // Clean up.
+  delete inst;
+}
+
+bool Warp::interrupt(Word r0) {
+  if (!interruptEnable) return false;
+
+#ifdef EMU_INSTRUMENTATION
+  Harp::OSDomain::osDomain->do_int(0, r0);
+#endif
+
+  shadowActiveThreads = activeThreads;
+  shadowTmask = tmask;
+  shadowInterruptEnable = interruptEnable; /* For traps. */
+  shadowSupervisorMode = supervisorMode;
+  
+  for (Word i = 0; i < reg[0].size(); ++i) shadowReg[i] = reg[0][i];
+  for (Word i = 0; i < pred[0].size(); ++i) shadowPReg[i] = pred[0][i];
+  for (Word i = 0; i < reg.size(); ++i) tmask[i] = 1;
+
+  shadowPc = pc;
+  activeThreads = 1;
+  interruptEnable = false;
+  supervisorMode = true;
+  reg[0][0] = r0;
+  pc = core->interruptEntry;
+
+  return true;
+}
+
+void Warp::printStats() const {
+  cout << "Steps : " << steps << endl
+       << "Insts : " << insts << endl
+       << "Loads : " << loads << endl
+       << "Stores: " << stores << endl;
+
+  unsigned const grade = reg[0][28];
+
+  if (grade == 1) cout << "GRADE: PASSED\n";
+  else              cout << "GRADE: FAILED "  << (grade >> 1) << "\n";
+}

emulator/enc.cpp

@@ -0,0 +1,405 @@
+/*******************************************************************************
+ HARPtools by Chad D. Kersey, Summer 2011
+*******************************************************************************/
+#include <iostream>
+#include <string>
+#include <stdlib.h>
+#include <string.h>
+#include <iomanip>
+#include <vector>
+
+#include "include/debug.h"
+#include "include/types.h"
+#include "include/util.h"
+#include "include/enc.h"
+#include "include/archdef.h"
+#include "include/instruction.h"
+
+using namespace std;
+using namespace Harp;
+
+ByteDecoder::ByteDecoder(const ArchDef &ad) {
+  wordSize = ad.getWordSize();
+}
+
+static void decodeError(string msg) {
+  cout << "Instruction decoder error: " << msg << '\n';
+  exit(1);
+}
+
+void Encoder::encodeChunk(DataChunk &dest, const TextChunk &src) {
+  // typedef vector<Instruction*>::const_iterator vec_it;
+  // const vector<Instruction*> &s(src.instructions);
+  // vector<Byte> &d(dest.contents);
+
+  // /* Keep encoding the instructions. */
+  // Size n = 0;
+
+  // /* For each instruction. */
+  // for (vec_it i = s.begin(); i != s.end(); i++) {
+  //   Ref *ref;
+
+  //   /* Perform the encoding. */
+  //   n += encode(ref, d, n, **i);
+    
+  //   /* Add reference if necessary. */
+  //   if (ref != NULL) {
+  //     ref->ibase = n;
+  //     dest.refs.push_back(ref);
+  //   }
+  // }
+
+  // dest.alignment = src.alignment;
+  // dest.flags = src.flags;
+  // dest.address = src.address;
+  // dest.bound = src.bound;
+  // if (src.isGlobal()) dest.setGlobal();
+
+  // d.resize(n);
+  // dest.size = n;
+}
+
+void Decoder::decodeChunk(TextChunk &dest, const DataChunk &src) {
+//   typedef vector<Instruction*>::const_iterator vec_it;
+//   const vector<Byte> &v(src.contents);
+//   Size n = 0;
+
+//   setRefs(src.refs);
+
+//   while (n < src.contents.size()) {
+//     Instruction *inst = decode(v, n);
+//     if (inst->hasRefLiteral()) {
+//       dest.refs.push_back(inst->getRefLiteral());
+//     }
+
+//     dest.instructions.push_back(inst);
+//   }
+
+//   dest.alignment = src.alignment;
+//   dest.flags = src.flags;
+//   dest.address = src.address;
+//   dest.bound = src.bound;
+//   if (src.isGlobal()) dest.setGlobal();
+
+//   clearRefs();
+// }
+
+// void Decoder::setRefs(const std::vector<Ref*> &refVec) {
+//   haveRefs = true;
+
+//   typedef std::vector<Ref*>::const_iterator vec_ci;
+
+//   for (vec_ci i = refVec.begin(); i != refVec.end(); i++) {
+//     OffsetRef *oref = dynamic_cast<OffsetRef*>(*i);
+//     if (oref) {
+//       refMap[oref->getOffset()] = *i;
+//     } else {
+//       decodeError("Unknown Ref type in Decoder::setRefs");
+//     }
+//   }
+}
+
+Instruction *ByteDecoder::decode(const vector<Byte> &v, Size &n) {
+  Instruction &inst = *(new Instruction());
+
+  // uint8_t pred = readByte(v, n);
+  // if (pred != 0xff) inst.setPred(pred);
+
+  // unsigned op = readByte(v, n);
+  // inst.setOpcode(Instruction::Opcode(op));
+
+  // bool usedImm = false;
+
+  // switch ((Instruction::instTable[op]).argClass) {
+  //   case Instruction::AC_NONE:
+  //     break;
+  //   case Instruction::AC_2REG:
+  //     inst.setDestReg(readByte(v, n));
+  //     inst.setSrcReg(readByte(v, n));
+  //     break;
+  //   case Instruction::AC_2IMM:
+  //     inst.setDestReg(readByte(v, n));
+  //     inst.setSrcImm(readWord(v, n, wordSize));
+  //     usedImm = true;
+  //     break;
+  //   case Instruction::AC_3REG:
+  //     inst.setDestReg(readByte(v, n));
+  //     inst.setSrcReg(readByte(v, n));
+  //     inst.setSrcReg(readByte(v, n));
+  //     break;
+  //   case Instruction::AC_3PREG:
+  //     inst.setDestPReg(readByte(v, n));
+  //     inst.setSrcPReg(readByte(v, n));
+  //     inst.setSrcPReg(readByte(v, n));
+  //     break;
+  //   case Instruction::AC_3IMM:
+  //     inst.setDestReg(readByte(v, n));
+  //     inst.setSrcReg(readByte(v, n));
+  //     inst.setSrcImm(readWord(v, n, wordSize));
+  //     usedImm = true;
+  //     break;
+  //   case Instruction::AC_3REGSRC:
+  //     inst.setSrcReg(readByte(v, n));
+  //     inst.setSrcReg(readByte(v, n));
+  //     inst.setSrcReg(readByte(v, n));
+  //     break;
+  //   case Instruction::AC_1IMM:
+  //     inst.setSrcImm(readWord(v, n, wordSize));
+  //     usedImm = true;
+  //     break;
+  //   case Instruction::AC_1REG:
+  //     inst.setSrcReg(readByte(v, n));
+  //     break;
+  //   case Instruction::AC_3IMMSRC:
+  //     inst.setSrcReg(readByte(v, n));
+  //     inst.setSrcReg(readByte(v, n));
+  //     inst.setSrcImm(readWord(v, n, wordSize));
+  //     usedImm = true;
+  //     break;
+  //   case Instruction::AC_PREG_REG:
+  //     inst.setDestPReg(readByte(v, n));
+  //     inst.setSrcReg(readByte(v, n));
+  //     break;
+  //   case Instruction::AC_2PREG:
+  //     inst.setDestPReg(readByte(v, n));
+  //     inst.setSrcPReg(readByte(v, n));
+  //     break;
+  //   case Instruction::AC_2REGSRC:
+  //     inst.setSrcReg(readByte(v, n));
+  //     inst.setSrcReg(readByte(v, n));
+  //     break;
+  //  default:
+  //     decodeError("Unknown argument class.");
+  // }
+
+  // if (haveRefs && usedImm && 
+  //     refMap.find(n - wordSize) != refMap.end()) {
+  //   OffsetRef *oref = dynamic_cast<OffsetRef*>(refMap[n - wordSize]);
+  //   if (!oref) {
+  //     decodeError("Expected OffsetRef when decoding instruction stream.");
+  //   }
+  //   Ref *r = new SimpleRef(oref->name, *(Addr*)(inst.setSrcImm()), 
+  //                          inst.hasRelImm());
+  //   inst.setImmRef(*r);
+  // } 
+
+  return &inst;
+}
+
+ByteEncoder::ByteEncoder(const ArchDef &ad) {
+  wordSize = ad.getWordSize();
+}
+
+Size ByteEncoder::encode(Ref *&ref, vector<Byte> &v, Size n0, Instruction &i) {
+  // Size n(n0);
+
+  // if (i.hasPred()) writeByte(v, n, i.getPred());
+  // else writeByte(v, n, 0xff);
+
+  // writeByte(v, n, Byte(i.getOpcode()));
+
+  // if (i.hasRDest()) {
+  //   writeByte(v, n, Byte(i.getRDest()));
+  // } else if (i.hasPDest()) {
+  //   writeByte(v, n, Byte(i.getPDest()));
+  // }
+
+  // for (RegNum j = 0; j < i.getNRSrc(); j++) {
+  //   writeByte(v, n, Byte(i.getRSrc(j)));
+  // }
+
+  // for (RegNum j = 0; j < i.getNPSrc(); j++) {
+  //   writeByte(v, n, Byte(i.getPSrc(j)));
+  // }
+
+  // ref = NULL;
+  // if (i.hasImm()) {
+  //   if (i.hasRefLiteral()) {
+  //     Ref *r = i.getRefLiteral();
+  //     ref = new OffsetRef(r->name, v, n, wordSize*8, wordSize, i.hasRelImm());
+  //   }
+
+  //   writeWord(v, n, wordSize, i.getImm());
+  // }
+
+  // return n - n0;
+  return 0;
+}
+
+static unsigned ceilLog2(RegNum x) {
+  unsigned z = 0;
+  bool nonZeroInnerValues(false);
+
+  if (x == 0) return 0;
+
+  while (x != 1) {
+    z++;
+    if (x&1) nonZeroInnerValues = true;
+    x >>= 1;
+  }
+
+  if (nonZeroInnerValues) z++;
+
+  return z;
+}
+
+
+WordDecoder::WordDecoder(const ArchDef &arch) {
+
+    inst_s   = arch.getWordSize() * 8;
+    opcode_s = 7;
+    reg_s    = 5;
+    func3_s  = 3;
+
+    shift_opcode    = 0;
+    shift_rd        = opcode_s;
+    shift_func3     = opcode_s + reg_s;
+    shift_rs1       = opcode_s + reg_s + func3_s;
+    shift_rs2       = opcode_s + reg_s + func3_s + reg_s;
+    shift_func7     = opcode_s + reg_s + func3_s + reg_s + reg_s;
+    shift_j_u_immed = opcode_s + reg_s;
+    shift_s_b_immed = opcode_s + reg_s + func3_s + reg_s + reg_s;
+    shift_i_immed   = opcode_s + reg_s + func3_s + reg_s;
+
+    reg_mask     = 0x1f;
+    func3_mask   = 0x7;
+    func7_mask   = 0x7f;
+    opcode_mask  = 0x7f;
+    i_immed_mask = 0xfff;
+    s_immed_mask = 0xfff;
+    b_immed_mask = 0x1fff;
+    u_immed_mask = 0xfffff;
+    j_immed_mask = 0xfffff;
+
+}
+
+static Word signExt(Word w, Size bit, Word mask) {
+  if (w>>(bit-1)) w |= ~mask;
+  return w;
+}
+
+Instruction *WordDecoder::decode(const std::vector<Byte> &v, Size &idx) {
+  Word code(readWord(v, idx, inst_s/8));
+
+  // std::cout << "code: " << (int) code << "  v: " << v << " indx: " << idx << "\n";
+  
+
+  Instruction &inst = * new Instruction();  
+
+  // bool predicated = (code>>(n-1));
+  bool predicated = false;
+  if (predicated) { inst.setPred((code>>(inst_s-p-1))&pMask); }
+
+  Opcode op = (Opcode)((code>>shift_opcode)&opcode_mask);
+  // std::cout << "opcode: " << op << "\n";
+  inst.setOpcode(op);
+
+  bool usedImm(false);
+  Word imeed, dest_bits, imm_bits, bit_11, bits_4_1, bit_10_5,
+          bit_12, bits_19_12, bits_10_1, bit_20, unordered, func3;
+
+  // std::cout << "op: " << std::hex << op << " what " << instTable[op].iType << "\n";
+  switch(instTable[op].iType)
+  {
+    case InstType::N_TYPE:
+      break;
+    case InstType::R_TYPE:
+      inst.setPred((code>>shift_rs1)   & reg_mask);
+      inst.setDestReg((code>>shift_rd)   & reg_mask);
+      inst.setSrcReg((code>>shift_rs1)   & reg_mask);
+      inst.setSrcReg((code>>shift_rs2)   & reg_mask);
+      inst.setFunc3 ((code>>shift_func3) & func3_mask);
+      inst.setFunc7 ((code>>shift_func7) & func7_mask);
+      break;
+    case InstType::I_TYPE:
+      inst.setDestReg((code>>shift_rd)   & reg_mask);
+      inst.setSrcReg((code>>shift_rs1)   & reg_mask);
+      inst.setFunc7 ((code>>shift_func7) & func7_mask);
+      func3 = (code>>shift_func3) & func3_mask;
+      inst.setFunc3 (func3);
+
+      if ((func3 == 5) && (op != L_INST))
+      {
+        // std::cout << "func7: " << func7 << "\n";
+        inst.setSrcImm(signExt(((code>>shift_rs2)&reg_mask), 5, reg_mask));
+      }
+      else
+      {
+        inst.setSrcImm(signExt(code>>shift_i_immed, 12, i_immed_mask));
+      }
+
+      usedImm = true;
+      break;
+    case InstType::S_TYPE:
+      // std::cout << "************STORE\n";
+      inst.setSrcReg((code>>shift_rs1)   & reg_mask);
+      inst.setSrcReg((code>>shift_rs2)   & reg_mask);
+      inst.setFunc3 ((code>>shift_func3) & func3_mask);
+
+      dest_bits = (code>>shift_rd)  & reg_mask;
+      imm_bits  = (code>>shift_s_b_immed & func7_mask);
+      imeed     = (imm_bits << reg_s) | dest_bits;
+      // std::cout << "ENC: store imeed: " << imeed << "\n";
+      inst.setSrcImm(signExt(imeed, 12, s_immed_mask));
+      usedImm = true;
+      break;
+    case InstType::B_TYPE:
+
+      inst.setSrcReg((code>>shift_rs1)   & reg_mask);
+      inst.setSrcReg((code>>shift_rs2)   & reg_mask);
+      inst.setFunc3 ((code>>shift_func3) & func3_mask);
+
+      dest_bits = (code>>shift_rd)  & reg_mask;
+      imm_bits  = (code>>shift_s_b_immed & func7_mask);
+
+      bit_11   = dest_bits & 0x1;
+      bits_4_1 = dest_bits >> 1;
+      bit_10_5 = imm_bits & 0x3f;
+      bit_12   = imm_bits >> 6;
+
+      imeed    = 0 | (bits_4_1 << 1) | (bit_10_5 << 5) | (bit_11 << 11) | (bit_12 << 12);
+
+      inst.setSrcImm(signExt(imeed, 13, b_immed_mask));
+      usedImm = true;
+      break;
+    case InstType::U_TYPE:
+      inst.setDestReg((code>>shift_rd)   & reg_mask);
+      inst.setSrcImm(signExt(code>>shift_j_u_immed, 20, u_immed_mask));
+      usedImm = true;
+      break;
+    case InstType::J_TYPE:
+      inst.setDestReg((code>>shift_rd)   & reg_mask);
+
+      // [20 | 10:1 | 11 | 19:12]
+
+      unordered = code>>shift_j_u_immed;
+
+      bits_19_12 = unordered & 0xff;
+      bit_11     = (unordered>>8) & 0x1;
+      bits_10_1  = (unordered >> 9) & 0x3ff;
+      bit_20     = (unordered>>19) & 0x1;
+
+      imeed  = 0 | (bits_10_1 << 1) | (bit_11 << 11) | (bits_19_12 << 12) | (bit_20 << 20);
+
+      inst.setSrcImm(signExt(imeed, 20, j_immed_mask));
+      usedImm = true;
+      break;
+   defualt:
+      cout << "Unrecognized argument class in word decoder.\n";
+      exit(1);
+  }
+
+  if (haveRefs && usedImm && refMap.find(idx-n/8) != refMap.end()) {
+    Ref *srcRef = refMap[idx-n/8];
+
+    /* Create a new ref tied to this instruction. */
+    Ref *r = new SimpleRef(srcRef->name, *(Addr*)inst.setSrcImm(),
+                           inst.hasRelImm());
+    inst.setImmRef(*r);
+  }
+
+  D(2, "Decoded 0x" << hex << code << " into: " << inst << '\n');
+
+  return &inst;
+}
+

emulator/harptool.cpp

@@ -0,0 +1,132 @@
+/*******************************************************************************
+ HARPtools by Chad D. Kersey, Summer 2011
+*******************************************************************************/
+#include <iostream>
+#include <iomanip>
+#include <string>
+#include <sstream>
+#include <fstream>
+#include <stdlib.h>
+
+
+#include "include/debug.h"
+#include "include/types.h"
+#include "include/core.h"
+#include "include/enc.h"
+#include "include/instruction.h"
+#include "include/mem.h"
+#include "include/obj.h"
+#include "include/archdef.h"
+
+#include "include/args.h"
+#include "include/help.h"
+
+
+using namespace Harp;
+using namespace HarpTools;
+using namespace std; 
+
+enum HarpToolMode { HARPTOOL_MODE_ASM, HARPTOOL_MODE_DISASM, HARPTOOL_MODE_EMU, 
+                    HARPTOOL_MODE_LD,  HARPTOOL_MODE_HELP };
+
+HarpToolMode findMode(int argc, char** argv) {
+  bool mode_asm, mode_disasm, mode_emu, mode_ld, mode_help;
+
+  if (argc == 0) return HARPTOOL_MODE_HELP;
+
+  CommandLineArgFlag fh("--help", "-h", "", mode_help);
+  CommandLineArgFlag fa("-A", "--asm", "", mode_asm);
+  CommandLineArgFlag fd("-D", "--disasm", "", mode_disasm);
+  CommandLineArgFlag fe("-E", "--emu", "", mode_emu);
+  CommandLineArgFlag fl("-L", "--ld", "", mode_ld);
+
+  CommandLineArg::readArgs((argc == 0?0:1), argv);
+  CommandLineArg::clearArgs();
+
+  if (mode_asm)    return HARPTOOL_MODE_ASM;
+  if (mode_disasm) return HARPTOOL_MODE_DISASM;
+  if (mode_emu)    return HARPTOOL_MODE_EMU;
+  if (mode_ld)     return HARPTOOL_MODE_LD;
+  return HARPTOOL_MODE_HELP;
+}
+
+int emu_main(int argc, char **argv) {
+  string archString("rv32i"), imgFileName("a.dsfsdout.bin");
+  bool showHelp, showStats, basicMachine, batch;
+
+  /* Read the command line arguments. */
+  CommandLineArgFlag          fh("-h", "--help", "", showHelp);
+  CommandLineArgSetter<string>fc("-c", "--core", "", imgFileName);
+  CommandLineArgSetter<string>fa("-a", "--arch", "", archString);
+  CommandLineArgFlag          fs("-s", "--stats", "", showStats);
+  CommandLineArgFlag          fb("-b", "--basic", "", basicMachine);
+  CommandLineArgFlag          fi("-i", "--batch", "", batch);
+  
+  CommandLineArg::readArgs(argc, argv);
+  if (showHelp) {
+    cout << Help::emuHelp;
+    return 0;
+  }
+
+  /* Instantiate a Core, RAM, and console output. */
+  ArchDef arch(archString);
+
+  Decoder *dec;
+
+  switch (arch.getEncChar()) {
+    case 'b': dec = new ByteDecoder(arch); break;
+    case 'w': dec = new WordDecoder(arch); break;
+    case 'r': dec = new WordDecoder(arch); break;
+    default:
+      cout << "Unrecognized decoder type: '" << arch.getEncChar() << "'.\n";
+      return 1;
+  }
+
+    // std::cout << "TESTING:  " << tests[t] << "\n"; 
+
+
+    MemoryUnit mu(4096, arch.getWordSize(), basicMachine);
+    Core core(arch, *dec, mu/*, ID in multicore implementations*/);
+
+    // RamMemDevice mem(imgFileName.c_str(), arch.getWordSize());
+    RAM old_ram;
+    old_ram.loadHexImpl(imgFileName.c_str());
+    // old_ram.loadHexImpl(tests[t]);
+    // MemDevice * memory = &old_ram;
+
+    ConsoleMemDevice console(arch.getWordSize(), cout, core, batch);
+    mu.attach(old_ram,     0);
+    mu.attach(console, 1ll<<(arch.getWordSize()*8 - 1));
+    // mu.attach(console, 0xf0000000);
+
+    // core.w[0].pc = 0x8000007c; // If I want to start at a specific location
+    std::cout << "ABOUT TO START\n";
+    while (core.running()) { console.poll(); core.step(); }
+
+    if (showStats) core.printStats();
+
+
+    std::cout << "\n";
+  return 0;
+}
+
+
+int main(int argc, char** argv) {
+  try {
+    switch (findMode(argc - 1, argv + 1)) {
+      case HARPTOOL_MODE_ASM:    cout << "ASM not supported\n";
+      case HARPTOOL_MODE_DISASM: cout << "DISASM not supported\n";
+      case HARPTOOL_MODE_EMU:    return emu_main   (argc - 2, argv + 2);
+      case HARPTOOL_MODE_LD:     cout << "LD not supported\n";
+      case HARPTOOL_MODE_HELP:
+      default:
+        cout << "Usage:\n" << Help::mainHelp;
+        return 0;
+    }
+  } catch (BadArg ba) {
+    cout << "Unrecognized argument \"" << ba.arg << "\".\n";
+    return 1;
+  }
+
+  return 0;
+}

emulator/include/archdef.h

@@ -0,0 +1,116 @@
+/*******************************************************************************
+ HARPtools by Chad D. Kersey, Summer 2011
+*******************************************************************************/
+#ifndef __ARCHDEF_H
+#define __ARCHDEF_H
+
+#include <string>
+#include <sstream>
+
+#include <cstdlib>
+#include <stdio.h>
+#include "types.h"
+
+namespace Harp {
+  class ArchDef {
+  public:
+    struct Undefined {};
+
+    ArchDef(const std::string &s) {
+      std::istringstream iss(s.c_str());
+            
+      wordSize = 4;
+      encChar = 'w';
+      nRegs = 32;
+      nPRegs = 0;
+      nThds = 8;
+      nWarps = 8;
+
+      extent = EXT_WARPS;
+
+      // if (!iss) { extent = EXT_NULL; return; }
+      // iss >> encChar;
+      // if (!iss) { extent = EXT_WORDSIZE; return; }
+      // iss >> nRegs;
+      // if (!iss) { extent = EXT_ENC; return; }
+      // char sep;
+      // iss >> sep >> nPRegs;
+      // if (!iss || sep != '/') { extent = EXT_REGS; return; }
+      // iss >> sep >> nThds;
+      // if (!iss || sep != '/') { extent = EXT_PREGS; return; }
+      // iss >> sep >> nWarps;
+      // if (!iss || sep != '/') { extent = EXT_THDS; return; }
+      // extent = EXT_WARPS;
+    }
+
+    operator std::string () const {
+      if (extent == EXT_NULL) return "";
+
+      std::ostringstream oss;
+      if (extent >= EXT_WORDSIZE) oss << wordSize;
+      if (extent >= EXT_ENC     ) oss << encChar;
+      if (extent >= EXT_REGS    ) oss << nRegs;
+      if (extent >= EXT_PREGS   ) oss << '/' << nPRegs;
+      if (extent >= EXT_THDS    ) oss << '/' << nThds;
+      if (extent >= EXT_WARPS    ) oss << '/' << nWarps;
+
+      return oss.str();
+    }
+
+    bool operator==(const ArchDef &r) const {
+      Extent minExtent(r.extent > extent ? extent : r.extent);
+
+      // Can't be equal if we can't specify a binary encoding at all.
+      if (minExtent < EXT_PREGS) return false;
+      
+      if (minExtent >= EXT_WORDSIZE) { if (wordSize!=r.wordSize) return false; }
+      if (minExtent >= EXT_ENC     ) { if (encChar != r.encChar) return false; }
+      if (minExtent >= EXT_REGS    ) { if (nRegs   !=   r.nRegs) return false; }
+      if (minExtent >= EXT_PREGS   ) { if (nPRegs  !=  r.nPRegs) return false; }
+      if (minExtent >= EXT_THDS    ) { if (nThds   !=   r.nThds) return false; }
+      if (minExtent >= EXT_WARPS   ) { if (nWarps  !=  r.nWarps) return false; }
+
+      return true;
+    }
+
+    bool operator!=(const ArchDef &r) const { return !(*this == r); }
+
+    Size getWordSize() const { 
+      if (extent <  EXT_WORDSIZE) throw Undefined(); else return wordSize; 
+    }
+
+    char getEncChar() const {
+      if (extent<EXT_ENC||encChar=='x') throw Undefined(); else return encChar;
+    }
+
+    RegNum getNRegs() const {
+      if (extent < EXT_REGS) throw Undefined(); else return nRegs;
+    }
+
+    RegNum getNPRegs() const {
+      if (extent < EXT_PREGS) throw Undefined(); else return nPRegs;
+    }
+  
+    ThdNum getNThds() const {
+      if (extent < EXT_THDS) throw Undefined(); else return nThds;
+    }
+
+    ThdNum getNWarps() const {
+      if (extent < EXT_WARPS) throw Undefined(); else return nWarps;
+    }
+    
+  private:
+    enum Extent { 
+      EXT_NULL, EXT_WORDSIZE, EXT_ENC, EXT_REGS, EXT_PREGS, EXT_THDS, EXT_WARPS
+    };
+
+    Extent extent;
+
+    Size wordSize;
+    ThdNum nThds, nWarps;
+    RegNum nRegs, nPRegs;
+    char encChar;
+  };
+};
+
+#endif

emulator/include/args.h

@@ -0,0 +1,61 @@
+/*******************************************************************************
+ HARPtools by Chad D. Kersey, Summer 2011
+*******************************************************************************/
+#ifndef __ARGS_H
+#define __ARGS_H
+
+#include <iostream>
+#include <string>
+#include <sstream>
+#include <map>
+
+namespace HarpTools {
+  struct BadArg { BadArg(std::string s) : arg(s) {} std::string arg; };
+
+  class CommandLineArg {
+  public:
+    CommandLineArg(std::string s, std::string l, const char *helpText);
+    CommandLineArg(std::string l, const char *helpText);
+    virtual int read(int argc, char** argv) = 0;
+
+    static void readArgs(int argc, char **argv);
+    static void clearArgs();
+    static void showHelp(std::ostream &os);
+
+  private:
+    static std::string helpString;
+    static std::map<std::string, CommandLineArg *> longArgs;
+    static std::map<std::string, CommandLineArg *> shortArgs;
+  };
+
+  template <typename T> class CommandLineArgSetter : public CommandLineArg {
+  public:
+    CommandLineArgSetter(std::string s, std::string l, const char *ht, T &x) :
+      CommandLineArg(s, l, ht), x(x) {}
+    CommandLineArgSetter(std::string l, const char *ht, T &x) :
+      CommandLineArg(l, ht), x(x) {}
+
+    int read(int argc, char **argv) {
+      std::istringstream iss(argv[1]);
+      iss >> x;
+      return 1;
+    }
+  private:
+    T &x;
+  };
+
+  class CommandLineArgFlag : public CommandLineArg {
+  public:
+    CommandLineArgFlag(std::string s, std::string l, const char *ht, bool &x) :
+      CommandLineArg(s, l, ht), x(x) { x = false; }
+    CommandLineArgFlag(std::string l, const char *ht, bool &x) :
+      CommandLineArg(l, ht), x(x) { x = false; }
+
+    int read(int argc, char **argv) { x = true; return 0; }
+  private:
+    bool &x;
+  };
+  
+};
+
+#endif

emulator/include/asm-tokens.h

@@ -0,0 +1,16 @@
+#ifndef HARPTOOL_ASM_TOKENS
+#define HARPTOOL_ASM_TOKENS
+
+namespace HarpTools {
+  enum AsmTokens {
+    ASM_T_DIR_DEF = 1, ASM_T_DIR_PERM,    ASM_T_DIR_BYTE,  ASM_T_DIR_WORD,
+    ASM_T_DIR_SPACE,   ASM_T_DIR_STRING,  ASM_T_DIR_ALIGN, ASM_T_DIR_ENTRY,
+    ASM_T_DIR_GLOBAL,  ASM_T_DIR_ARG_NUM, ASM_T_DIR_ARG_STRING,
+    ASM_T_DIR_ARG_SYM, ASM_T_DIR_ARG_R,   ASM_T_DIR_ARG_W, ASM_T_DIR_ARG_X,
+    ASM_T_DIR_END,     ASM_T_LABEL,       ASM_T_PRED,      ASM_T_INST,
+    ASM_T_PREG,        ASM_T_REG,         ASM_T_REG_RA,    ASM_T_REG_SP,
+    ASM_T_REG_FP,      ASM_T_LIT,         ASM_T_SYM,       ASM_T_PEXP
+  };
+};
+
+#endif

emulator/include/core.h

@@ -0,0 +1,145 @@
+/*******************************************************************************
+ HARPtools by Chad D. Kersey, Summer 2011
+*******************************************************************************/
+#ifndef __CORE_H
+#define __CORE_H
+
+#include <string>
+#include <vector>
+#include <stack>
+#include <map>
+#include <set>
+
+#include "types.h"
+#include "archdef.h"
+#include "enc.h"
+#include "mem.h"
+#include "debug.h"
+
+namespace Harp {
+#ifdef EMU_INSTRUMENTATION
+  void reg_doWrite(Word cpuId, Word regNum);
+  void reg_doRead(Word cpuId, Word regNum);
+#endif
+
+  template <typename T> class Reg {
+  public:
+    Reg(): cpuId(0), regNum(0), val(0) {}
+    Reg(Word c, Word n): cpuId(c), regNum(n), val(0) {}
+
+    Reg &operator=(T r) { if (regNum) {val = r; doWrite();} return *this; }
+
+    operator T() const { doRead(); return val; }
+
+    void trunc(Size s) {
+      Word mask((~0ull >> (sizeof(Word)-s)*8));
+      val &= mask;
+    }
+
+  private:
+    Word cpuId, regNum;
+    T val;
+
+#ifdef EMU_INSTRUMENTATION
+    /* Access size here is 8, representing the register size of 64-bit cores. */
+    void doWrite() const { reg_doWrite(cpuId, regNum); }
+    void doRead() const { reg_doRead(cpuId, regNum); }
+#else
+    void doWrite() const {}
+    void doRead() const {}
+#endif
+  };
+
+  // Entry in the IPDOM Stack
+  struct DomStackEntry {
+    DomStackEntry(
+      unsigned p, const std::vector<std::vector<Reg<Word> > >& m,
+      std::vector<bool> &tm, Word pc
+    ): pc(pc), fallThrough(false), uni(false)
+    {
+      std::cout << "DomStackEntry TMASK: ";
+      for (unsigned i = 0; i < m.size(); ++i)
+      {
+        std::cout << " " << (!bool(m[i][p]) && tm[i]);
+        tmask.push_back(!bool(m[i][p]) && tm[i]);
+      }
+      std::cout << "\n";
+    }
+
+    DomStackEntry(const std::vector<bool> &tmask):
+      tmask(tmask), fallThrough(true), uni(false) {}
+
+    bool fallThrough;
+    bool uni;
+    std::vector<bool> tmask;
+    Word pc;
+  };
+
+  class Warp;
+
+  class Core {
+  public:
+    Core(const ArchDef &a, Decoder &d, MemoryUnit &mem, Word id=0);
+
+    bool interrupt(Word r0);
+    bool running() const;
+    void step();
+
+    void printStats() const;
+    
+    const ArchDef &a;
+    Decoder &iDec;
+    MemoryUnit &mem;
+
+    Word interruptEntry;
+
+    unsigned long steps;
+    std::vector<Warp> w;
+    std::map<Word, std::set<Warp *> > b; // Barriers
+  };
+
+  class Warp {
+  public:
+    Warp(Core *c, Word id=0);
+
+    void step();
+    bool interrupt(Word r0);
+    bool running() const { return activeThreads; }
+#ifdef EMU_INSTRUMENTATION
+    bool getSupervisorMode() const { return supervisorMode; }
+#endif
+
+    void printStats() const;
+
+    struct MemAccess {
+      MemAccess(bool w, Word a): wr(w), addr(a) {}
+      bool wr;
+      Word addr;
+    };
+    std::vector<MemAccess> memAccesses;
+    
+//  private:
+    Core *core;
+
+    Word pc, shadowPc, id;
+    Size activeThreads, shadowActiveThreads;
+    std::vector<std::vector<Reg<Word> > > reg;
+    std::vector<std::vector<Reg<bool> > > pred;
+    std::vector<Reg<uint16_t> > csr;
+
+    std::vector<bool> tmask, shadowTmask;
+    std::stack<DomStackEntry> domStack;
+
+    std::vector<Word> shadowReg;
+    std::vector<bool> shadowPReg;
+
+    bool interruptEnable, shadowInterruptEnable, supervisorMode, 
+         shadowSupervisorMode, spawned;
+
+    unsigned long steps, insts, loads, stores;
+    
+    friend class Instruction;
+  };
+};
+
+#endif

emulator/include/debug.h

@@ -0,0 +1,29 @@
+/*******************************************************************************
+ HARPtools by Chad D. Kersey, Spring 2013
+*******************************************************************************/
+#ifndef __DEBUG_H
+#define __DEBUG_H
+
+// #define USE_DEBUG 9
+
+#ifdef USE_DEBUG
+#include <iostream>
+
+#define D(lvl, x) do { \
+  using namespace std; \
+  if ((lvl) <= USE_DEBUG) { \
+    cout << "DEBUG " << __FILE__ << ':' << dec << __LINE__ << ": " \
+         << x << endl; \
+  } \
+} while(0)
+
+#define D_RAW(x) do { \
+  std::cout << x; \
+} while (0)
+#else
+
+#define D(lvl, x) do {} while(0)
+
+#endif
+
+#endif

emulator/include/enc.h

@@ -0,0 +1,95 @@
+/*******************************************************************************
+ HARPtools by Chad D. Kersey, Summer 2011
+*******************************************************************************/
+#ifndef __ENC_H
+#define __ENC_H
+
+#include <map>
+
+#include "types.h"
+#include "instruction.h"
+#include "obj.h"
+
+namespace Harp {
+  class DataChunk;
+  class TextChunk;
+  class Ref;
+
+  class Encoder {
+  public:
+    Encoder() {}
+    virtual ~Encoder() {}
+
+    virtual Size encode(Ref *&ref, std::vector<Byte> &v, Size n, 
+                        Instruction &i) = 0;
+    void encodeChunk(DataChunk &dest, const TextChunk &src);
+  };
+
+  class Decoder {
+  public:
+    Decoder() : haveRefs(false) {}
+    Decoder(const std::vector<Ref*> &refVec) : haveRefs(true) {
+      setRefs(refVec);
+    }
+
+    virtual ~Decoder() {}
+
+    void setRefs(const std::vector<Ref*> &);
+    void clearRefs() { refMap.clear(); }
+    virtual Instruction *decode(const std::vector<Byte> &v, Size &n) = 0;
+    void decodeChunk(TextChunk &dest, const DataChunk &src);
+  protected:
+    bool haveRefs;
+    std::map <Size, Ref*> refMap;
+  };
+
+  class WordDecoder : public Decoder {
+  public:
+    WordDecoder(const ArchDef &);    
+    virtual Instruction *decode(const std::vector<Byte> &v, Size &n);
+
+  private:
+    Size n, o, r, p, i1, i2, i3;
+    Word oMask, rMask, pMask, i1Mask, i2Mask, i3Mask;
+
+    // FARES
+    Size inst_s, opcode_s, reg_s, func3_s;
+    Size shift_opcode, shift_rd, shift_rs1, shift_rs2, shift_func3, shift_func7;
+    Size shift_j_u_immed, shift_s_b_immed, shift_i_immed;
+
+
+
+    Word reg_mask, func3_mask, func7_mask, opcode_mask, i_immed_mask, 
+          s_immed_mask, b_immed_mask, u_immed_mask, j_immed_mask;
+
+  };
+
+  class ByteDecoder : public Decoder {
+  public:
+    ByteDecoder(const ArchDef &);
+    virtual Instruction *decode(const std::vector<Byte> &v, Size &n);
+  private:
+    Size wordSize;
+  };
+
+  class WordEncoder : public Encoder {
+  public:
+    WordEncoder(const ArchDef &);
+    virtual Size encode(Ref *&ref, std::vector<Byte> &v,
+                        Size n, Instruction &i);
+  private:
+    Size n, o, r, p, i1, i2, i3;
+    Word oMask, rMask, pMask, i1Mask, i2Mask, i3Mask;
+  };
+
+  class ByteEncoder : public Encoder {
+  public:
+    ByteEncoder(const ArchDef &);
+    virtual Size encode(Ref *&ref, std::vector<Byte> &v,
+                        Size n, Instruction &i);
+  private:
+    Size wordSize;
+  };
+};
+
+#endif

emulator/include/harpfloat.h

@@ -0,0 +1,123 @@
+/*******************************************************************************
+ HARPtools by Chad D. Kersey, Summer 2011
+*******************************************************************************/
+#include <math.h>
+#include <stdlib.h>
+
+#include "types.h"
+
+#ifdef DEBUG
+#include <iostream>
+
+#define DEBUGMSG(x) do { \
+  std::cout << __FILE__ << ':' <<__LINE__ << ": " << x << '\n'; \
+} while(0)
+#else
+#define DEBUGMSG(x) do { } while(0)
+#endif
+
+namespace Harp {
+  // This class serves to handle the strange-precision floating point that can 
+  // crop up in HARP. 
+  class Float {
+  public:
+    Float(Word_u bin, Size n): sz(n) {
+      DEBUGMSG("Float(0x" << std::hex << bin << ", " << std::dec << n << ')');
+      
+      bool sign(bin >> (n*8 - 1));
+      
+      Size expSz;
+      if (n < 4) {
+        expSz = 5;
+      } else if (n < 8) {
+        expSz = 8;
+      } else {
+        expSz = 11;
+      }
+
+      Size sigSz = n*8 - expSz - 1;
+
+      DEBUGMSG("  exp: " << std::dec << expSz <<
+               " bits, sig: " << std::dec << sigSz << " bits.");
+
+      int exp = (bin >> sigSz) & ((1<<expSz) - 1);
+      Word_u sig = bin & ((1llu<<sigSz) - 1);
+      DEBUGMSG("  sig=" << std::dec << sig << " exp=" << exp);
+
+      if (exp == 0) {
+        // Subnormal 
+        d = sig / pow(2, ((1<<(expSz-1))-2)) / pow(2, sigSz);
+        DEBUGMSG("  Denorm.");
+      } else if (exp == ((1<<expSz) - 1)) {
+        // Infinity
+        d = HUGE_VAL;
+        DEBUGMSG("  Inf.");
+      } else {
+        // Normalized, implied 1.
+        exp -= (1<<(expSz - 1)) - 1;
+        d = pow(2.0, exp - int(sigSz)) * double((1ll << sigSz) + sig);
+        DEBUGMSG("  Norm, exp=" << exp);
+      }
+
+      if (sign) d = -d;
+
+      DEBUGMSG("Set to " << d);
+    }
+
+    Float(double d, Size n): sz(n), d(d) { DEBUGMSG("Float(double, size)"); }
+
+    operator Word_u() {
+      DEBUGMSG("Float -> Word_u: " << d);
+      Size expSz;
+      if (sz < 4) {
+        expSz = 5;
+      } else if (sz < 8) {
+        expSz = 8;
+      } else {
+        expSz = 11;
+      }
+
+      Size sigSz = 8*sz - expSz - 1;
+
+      bool sign(d < 0);
+
+      bool inf(isinf(d)), zero(d == 0.0);
+      int exp;
+
+      if (!inf && !zero) exp = floor(log2(fabs(d)));
+
+      Word_u rval;
+      if (inf) {
+        // Infinity
+        DEBUGMSG("  Inf.");
+        rval = ((1llu<<expSz)-1llu)<<sigSz;
+      } else if (!zero && abs(exp) < (1<<(expSz-1)) - 1) {
+        // Normalized with implied 1.
+        Word_u sig = (fabs(d) * pow(2.0, -exp) - 1.0) * pow(2.0, sigSz);
+        DEBUGMSG("  Norm, exp=" << exp << ", sig=" << sig);
+        rval = ((((exp + ((1llu<<(expSz-1)) - 1llu))
+                                          &((1llu<<expSz)-1llu)))<<sigSz) | sig;
+      } else if (!zero && exp > -(1<<(expSz-1)) - sigSz) {
+        // Subnormal number.
+        Word_u sig = round(fabs(d)*pow(2.0,((1<<(expSz-1))-2))*pow(2.0, sigSz));
+        DEBUGMSG("  Denorm, exp=" << exp << ", sig=" << sig);
+        rval = sig;
+      } else {
+        // Zero.
+        rval = 0;
+      }
+      
+      if (sign) rval |= 1llu<<(sz*8 - 1);
+
+      DEBUGMSG("  Returning 0x" << std::hex << rval);
+
+      return rval;
+    }
+
+    operator double() { DEBUGMSG("Float->double " << d); return d; }
+
+  private:
+    double d;
+    Size sz;
+  };
+};

emulator/include/help.h

@@ -0,0 +1,37 @@
+/*******************************************************************************
+ HARPtools by Chad D. Kersey, Summer 2011
+*******************************************************************************/
+#ifndef __HELP_H
+#define __HELP_H
+
+/* Help messages. */
+namespace HarpTools {
+  namespace Help {
+    const char *mainHelp = 
+      "--help, -h, no arguments\n"
+      "  Print this message.\n"
+      "-E, --emu; -A, --asm; -L, --ld; -D, --disasm\n"
+      "  Invoke the emulator, assembler, linker, and disassembler, "
+        "respectively.\n"
+      "<mode> --help\n"
+      "  Display contextual help.\n",
+      *emuHelp = "HARP Emulator command line arguments:\n"
+                  "  -c, --core <filename>    RAM image\n"
+                  "  -a, --arch <arch string> Architecture string\n"
+                  "  -s, --stats              Print stats on exit.\n"
+                  "  -b, --basic              Disable virtual memory.\n"
+                  "  -i, --batch              Disable console input.\n",
+      *asmHelp = "HARP Assembler command line arguments:\n"
+                  "  -a, --arch <arch string>\n"
+                  "  -o, --output <filename>\n",
+      *ldHelp = "HARP Linker command line arguments:\n"
+                "  -o, --output <filename>\n"
+                "  -a, --arch <filename>\n"
+                "  -f, --format <foramt string>\n"
+                "  --offset <bytes>\n",
+      *disasmHelp = "HARP Disassembler command line arguments:\n"
+                     "  -a, --arch <arch string> Architecture string.\n"
+                     "  -o, --output <filename>  Output filename.\n";
+  };
+};
+#endif

emulator/include/instruction.h

@@ -0,0 +1,144 @@
+/*******************************************************************************
+ HARPtools by Chad D. Kersey, Summer 2011
+*******************************************************************************/
+#ifndef __INSTRUCTION_H
+#define __INSTRUCTION_H
+
+#include <map>
+#include <iostream>
+
+#include "types.h"
+
+namespace Harp {
+  class Warp;
+  class Ref;
+
+  enum Opcode
+  {   
+      NOP = 0,    
+      R_INST = 51,
+      L_INST = 3,
+      I_INST = 19,
+      S_INST = 35,
+      B_INST = 99,
+      LUI_INST = 55,
+      AUIPC_INST = 23,
+      JAL_INST = 111,
+      JALR_INST = 103,
+      SYS_INST = 115,
+      TRAP     = 0x7f,
+      FENCE    = 0x0f,
+      PJ_INST  = 0x7b,
+      GPGPU    = 0x6b
+   };
+
+  enum InstType { N_TYPE, R_TYPE, I_TYPE, S_TYPE, B_TYPE, U_TYPE, J_TYPE};
+
+  // We build a table of instruction information out of this.
+  struct InstTableEntry_t {
+    const char *opString;
+    bool controlFlow, relAddress, allSrcArgs, privileged;
+    InstType iType;
+
+  };
+
+  static std::map<int, struct InstTableEntry_t> instTable = 
+  {
+    {Opcode::NOP,        {"nop"   , false, false, false, false, InstType::N_TYPE }},
+    {Opcode::R_INST,     {"r_type", false, false, false, false, InstType::R_TYPE }},
+    {Opcode::L_INST,     {"load"  , false, false, false, false, InstType::I_TYPE }},
+    {Opcode::I_INST,     {"i_type", false, false, false, false, InstType::I_TYPE }},
+    {Opcode::S_INST,     {"store" , false, false, false, false, InstType::S_TYPE }},
+    {Opcode::B_INST,     {"branch", true , false, false, false, InstType::B_TYPE }},
+    {Opcode::LUI_INST,   {"lui"   , false, false, false, false, InstType::U_TYPE }},
+    {Opcode::AUIPC_INST, {"auipc" , false, false, false, false, InstType::U_TYPE }},
+    {Opcode::JAL_INST,   {"jal"   , true , false, false, false, InstType::J_TYPE }},
+    {Opcode::JALR_INST,  {"jalr"  , true , false, false, false, InstType::I_TYPE }},
+    {Opcode::SYS_INST,   {"SYS"   , true , false, false, false, InstType::I_TYPE }},
+    {Opcode::TRAP,       {"TRAP"  , true , false, false, false, InstType::I_TYPE }},
+    {Opcode::FENCE,      {"fence" , true , false, false, false, InstType::I_TYPE }},
+    {Opcode::PJ_INST,    {"pred j", true , false, false, false, InstType::R_TYPE }},
+    {Opcode::GPGPU,      {"gpgpu" , false, false, false, false, InstType::R_TYPE }}
+  };
+
+  static const Size MAX_REG_SOURCES(3);
+  static const Size MAX_PRED_SOURCES(2);
+
+  class Instruction;
+
+  struct DivergentBranchException {};
+  struct DomainException {};
+
+  std::ostream &operator<<(std::ostream &, Instruction &);
+
+  class Instruction {
+  public:
+    Instruction() : 
+      predicated(false), nRsrc(0), nPsrc(0), immsrcPresent(false), 
+      rdestPresent(false), pdestPresent(false), refLiteral(NULL)
+      {
+      }
+
+    void executeOn(Warp &warp);
+    friend std::ostream &operator<<(std::ostream &, Instruction &);
+
+    /* Setters used to "craft" the instruction. */
+    void  setOpcode  (Opcode opc)  { op = opc; }
+    void  setPred    (RegNum pReg) { predicated = true; pred = pReg; }
+    void  setDestReg (RegNum destReg) { rdestPresent = true; rdest = destReg; }
+    void  setSrcReg  (RegNum srcReg) { rsrc[nRsrc++] = srcReg; }
+    void  setFunc3  (Word func3) { this->func3 = func3; }
+    void  setFunc7  (Word func7) { this->func7 = func7; }
+    void  setDestPReg(RegNum dPReg) { pdestPresent = true; pdest = dPReg; }
+    void  setSrcPReg (RegNum srcPReg) { psrc[nPsrc++] = srcPReg; }
+    Word *setSrcImm  () { immsrcPresent = true; immsrc = 0xa5; return &immsrc;}
+    void  setSrcImm  (Word srcImm) { immsrcPresent = true; immsrc = srcImm; }
+    void  setImmRef  (Ref &r) { refLiteral = &r; }
+
+    /* Getters used by encoders. */
+    Opcode getOpcode() const { return op; }
+    bool hasPred() const { return predicated; }
+    RegNum getPred() const { return pred; }
+    RegNum getNRSrc() const { return nRsrc; }
+    RegNum getRSrc(RegNum i) const { return rsrc[i]; }
+    RegNum getNPSrc() const { return nPsrc; }
+    RegNum getPSrc(RegNum i) const { return psrc[i]; }
+    bool hasRDest() const { return rdestPresent; }
+    RegNum getRDest() const { return rdest; }
+    bool hasPDest() const { return pdestPresent; }
+    RegNum getPDest() const { return pdest; }
+    bool hasImm() const { return immsrcPresent; }
+    Word getImm() const { return immsrc; }
+    bool hasRefLiteral() const { return refLiteral != NULL; }
+    Ref *getRefLiteral() const { return refLiteral; }
+
+    /* Getters used as table lookup. */
+    bool hasRelImm() const { return (*(instTable.find(op))).second.relAddress; }
+
+  private:
+    bool predicated;
+    RegNum pred;
+    Opcode op;
+    int nRsrc, nPsrc;
+    RegNum rsrc[MAX_REG_SOURCES], psrc[MAX_PRED_SOURCES];
+    bool immsrcPresent;
+    Word immsrc;
+    Word func3;
+    Word func7;
+    bool rdestPresent, pdestPresent;
+    RegNum rdest, pdest;
+    Ref *refLiteral;
+
+  public:
+    
+
+  };
+};
+
+#endif
+
+    // static struct InstTableEntry {
+    //   const char *opString;
+    //   bool controlFlow, relAddress, allSrcArgs, privileged;
+    //   InstType iType;
+    // };

emulator/include/mem.h

@@ -0,0 +1,432 @@
+/*******************************************************************************
+ HARPtools by Chad D. Kersey, Summer 2011
+*******************************************************************************/
+#ifndef __MEM_H
+#define __MEM_H
+
+#include <ostream>
+#include <vector>
+#include <queue>
+#include <map>
+#include <pthread.h>
+
+#include "types.h"
+
+namespace Harp {
+  void *consoleInputThread(void *);
+  struct BadAddress {};
+
+  class MemDevice {
+  public:
+    virtual ~MemDevice() {}
+    virtual Size size() const = 0;
+    virtual Word read(Addr) = 0;
+    virtual void write(Addr, Word) = 0;
+    virtual Byte *base() { return NULL; } /* Null if unavailable. */
+  };
+
+  class RamMemDevice : public MemDevice {
+  public:
+    RamMemDevice(Size size, Size wordSize);
+    RamMemDevice(const char* filename, Size wordSize);
+    ~RamMemDevice() {}
+
+    virtual Size size() const { return contents.size(); };
+    virtual Word read(Addr);
+    virtual void write(Addr, Word);
+    virtual Byte *base() { return &contents[0]; }
+
+  protected:
+    Size wordSize;
+    std::vector<Byte> contents;
+  };
+
+  class RomMemDevice : public RamMemDevice {
+  public:
+    RomMemDevice(const char* filename, Size wordSize) :
+      RamMemDevice(filename, wordSize) {}
+    RomMemDevice(Size size, Size wordSize) :
+      RamMemDevice(size, wordSize) {}
+    ~RomMemDevice();
+
+    virtual void write(Addr, Word);
+  };
+
+  class Core;
+  class ConsoleMemDevice : public MemDevice {
+  public:
+    ConsoleMemDevice(Size wS, std::ostream &o, Core &core, bool batch = false);
+    ~ConsoleMemDevice() {} 
+
+    //virtual Size wordSize() const { return wordSize; }
+    virtual Size size() const { return wordSize; }
+    virtual Word read(Addr) { pthread_mutex_lock(&cBufLock);
+                              char c = cBuf.front();
+                              cBuf.pop();
+                              pthread_mutex_unlock(&cBufLock);
+                              return Word(c); }
+    virtual void write(Addr a, Word w) { output << char(w); }
+
+    void poll();
+
+    friend void *Harp::consoleInputThread(void *);
+
+  private:
+    std::ostream &output;
+    Size wordSize;
+    Core &core;
+
+    std::queue<char> cBuf;
+    pthread_mutex_t cBufLock;
+  };
+
+  class DiskControllerMemDevice : public MemDevice {
+  public:
+    DiskControllerMemDevice(Size wordSize, Size blockSize, Core &c) : 
+      wordSize(wordSize), blockSize(blockSize), core(c), disks() {}
+    
+    void addDisk(Byte *file, Size n) { disks.push_back(Disk(file, n)); }
+
+    virtual Size size() const { return wordSize * 6; }
+    virtual Word read(Addr);
+    virtual void write(Addr, Word);
+
+  private:
+    Word curDisk, curBlock, nBlocks, physAddr, command, status;
+    enum Status { OK = 0, INVALID_DISK, INVALID_BLOCK };
+    struct Disk {
+      Disk(Byte *f, Size n): file(f), blocks(n) {}
+      Byte *file;
+      Size blocks;
+    };
+    std::vector <Disk> disks;
+    Core &core;
+    Size wordSize, blockSize;;
+  };
+
+  class MemoryUnit {
+  public:
+    MemoryUnit(Size pageSize, Size addrBytes, bool disableVm = false) : 
+      pageSize(pageSize), addrBytes(addrBytes), ad(), disableVm(disableVm)
+    {
+      if (!disableVm)
+        tlb[0] = TLBEntry(0, 077);
+    }
+    void attach(MemDevice &m, Addr base);
+
+    //Size wordSize();
+    struct PageFault { 
+      PageFault(Addr a, bool nf) : faultAddr(a), notFound(nf) {}
+      Addr faultAddr;
+      bool notFound;
+    }; /* Thrown on page fault. */
+
+    Word read(Addr, bool sup);  /* For data accesses. */
+    Word fetch(Addr, bool sup); /* For instruction accesses. */
+    Byte *getPtr(Addr, Size);
+    void write(Addr, Word, bool sup, Size);
+    void tlbAdd(Addr virt, Addr phys, Word flags);
+    void tlbRm(Addr va);
+    void tlbFlush() { tlb.clear(); }
+
+#ifdef EMU_INSTRUMENTATION
+    Addr virtToPhys(Addr va);
+#endif
+
+  private:
+    class ADecoder {
+    public:
+      ADecoder() : zeroChild(NULL), oneChild(NULL), range(0) {}
+      ADecoder(MemDevice &md, Size range) : 
+        zeroChild(NULL), oneChild(NULL), range(range), md(&md) {}
+      Byte *getPtr(Addr a, Size sz, Size wordSize);
+      Word read(Addr a, bool sup, Size wordSize);
+      void write(Addr a, Word w, bool sup, Size wordSize);
+      void map(Addr a, MemDevice &md, Size range, Size bit);
+    private:
+      MemDevice &doLookup(Addr a, Size &bit);
+      ADecoder *zeroChild, *oneChild;
+      MemDevice *md;
+      Size range;
+    };
+
+    ADecoder ad;
+
+    struct TLBEntry {
+      TLBEntry() {}
+      TLBEntry(Word pfn, Word flags): pfn(pfn), flags(flags) {}
+      Word flags;
+      Word pfn;
+    };
+
+    std::map<Addr, TLBEntry> tlb;
+    TLBEntry tlbLookup(Addr vAddr, Word flagMask);
+
+    Size pageSize, addrBytes;
+
+    bool disableVm;
+  };
+
+
+  class RAM : public MemDevice {
+  public:
+      uint8_t* mem[1 << 12];
+
+      RAM(){
+          for(uint32_t i = 0;i < (1 << 12);i++) mem[i] = NULL;
+      }
+      ~RAM(){
+          for(uint32_t i = 0;i < (1 << 12);i++) if(mem[i]) delete [] mem[i];
+      }
+
+      void clear(){
+          for(uint32_t i = 0;i < (1 << 12);i++)
+          {
+              if(mem[i])
+              { 
+                  delete mem[i];
+                  mem[i] = NULL;
+              }
+          }
+      }
+
+      uint8_t* get(uint32_t address){
+
+          if(mem[address >> 20] == NULL) {
+              uint8_t* ptr = new uint8_t[1024*1024];
+              for(uint32_t i = 0;i < 1024*1024;i+=4) {
+                  ptr[i + 0] = 0xaa;
+                  ptr[i + 1] = 0xbb;
+                  ptr[i + 2] = 0xcc;
+                  ptr[i + 3] = 0xdd;
+              }
+              mem[address >> 20] = ptr;
+          }
+          return &mem[address >> 20][address & 0xFFFFF];
+      }
+
+      void read(uint32_t address,uint32_t length, uint8_t *data){
+          for(unsigned i = 0;i < length;i++){
+              data[i] = (*this)[address + i];
+          }
+      }
+
+      void write(uint32_t address,uint32_t length, uint8_t *data){
+          for(unsigned i = 0;i < length;i++){
+              (*this)[address + i] = data[i];
+          }
+      }
+
+      virtual Size size() const { return (1<<31); };
+
+      void getBlock(uint32_t address, uint8_t *data)
+      {
+          uint32_t block_number = address & 0xffffff00; // To zero out block offset
+          uint32_t bytes_num    = 256;
+
+          this->read(block_number, bytes_num, data);
+      }
+
+      void getWord(uint32_t address, uint32_t * data)
+      {
+          data[0] = 0;
+
+          uint8_t first  = *get(address + 0);
+          uint8_t second = *get(address + 1);
+          uint8_t third  = *get(address + 2);
+          uint8_t fourth = *get(address + 3);
+
+
+          // std::cout << std::hex;
+          // std::cout << "RAM: READING ADDRESS " << address + 0 << " DATA: " << (uint32_t) first << "\n";
+          // std::cout << "RAM: READING ADDRESS " << address + 1 << " DATA: " << (uint32_t) second << "\n";
+          // std::cout << "RAM: READING ADDRESS " << address + 2 << " DATA: " << (uint32_t) third << "\n";
+          // std::cout << "RAM: READING ADDRESS " << address + 3 << " DATA: " << (uint32_t) fourth << "\n";
+
+          data[0] = (data[0] << 0) | fourth;
+          data[0] = (data[0] << 8) | third;
+          data[0] = (data[0] << 8) | second;
+          data[0] = (data[0] << 8) | first;
+          // data[0] = (data[0] << 0) | first;
+          // data[0] = (data[0] << 8) | second;
+          // data[0] = (data[0] << 8) | third;
+          // data[0] = (data[0] << 8) | fourth;
+
+          // std::cout << "FINAL DATA: " << data[0] << "\n";
+
+      }
+
+      void writeWord(uint32_t address, uint32_t * data)
+      {
+          uint32_t data_to_write = *data;
+
+          uint32_t byte_mask = 0xFF;
+
+          for (int i = 0; i < 4; i++)
+          {
+              // std::cout << "RAM: DATA TO WRITE " << data_to_write << "\n";
+              // std::cout << "RAM: DATA TO MASK  " << byte_mask << "\n";
+              // std::cout << "RAM: WRITING ADDRESS " << address + i << " DATA: " << (data_to_write & byte_mask) << "\n";
+              (*this)[address + i] = data_to_write & byte_mask;
+              data_to_write        = data_to_write >> 8;
+          }
+      }
+
+      void writeHalf(uint32_t address, uint32_t * data)
+      {
+          uint32_t data_to_write = *data;
+
+          uint32_t byte_mask = 0xFF;
+
+          for (int i = 0; i < 2; i++)
+          {
+              // std::cout << "RAM: DATA TO WRITE " << data_to_write << "\n";
+              // std::cout << "RAM: DATA TO MASK  " << byte_mask << "\n";
+              // std::cout << "RAM: WRITING ADDRESS " << address + i << " DATA: " << (data_to_write & byte_mask) << "\n";
+              (*this)[address + i] = data_to_write & byte_mask;
+              data_to_write        = data_to_write >> 8;
+          }
+      }
+
+      void writeByte(uint32_t address, uint32_t * data)
+      {
+          uint32_t data_to_write = *data;
+
+          uint32_t byte_mask = 0xFF;
+
+          (*this)[address] = data_to_write & byte_mask;
+          data_to_write    = data_to_write >> 8;
+
+      }
+
+      uint8_t& operator [](uint32_t address) {
+          return *get(address);
+      }
+
+      virtual void write(Addr addr, Word w)
+      {
+          uint32_t word = (uint32_t) w;
+          writeWord(addr, &word);
+      }
+
+      virtual Word read(Addr addr)
+      {
+          uint32_t w;
+          getWord(addr, &w);
+          // std::cout << "RAM: read -> " << w << " at addr: " << addr << "\n";
+          return (Word) w;
+      }
+
+      virtual Byte *base()
+      {
+          return (Byte *) this->get(0);
+      }
+
+  // MEMORY UTILS
+
+  uint32_t hti_old(char c) {
+      if (c >= 'A' && c <= 'F')
+          return c - 'A' + 10;
+      if (c >= 'a' && c <= 'f')
+          return c - 'a' + 10;
+      return c - '0';
+  }
+
+  uint32_t hToI_old(char *c, uint32_t size) {
+      uint32_t value = 0;
+      for (uint32_t i = 0; i < size; i++) {
+          value += hti_old(c[i]) << ((size - i - 1) * 4);
+      }
+      return value;
+  }
+
+
+
+  void loadHexImpl(std::string path) {
+      this->clear();
+      FILE *fp = fopen(&path[0], "r");
+      if(fp == 0){
+          std::cout << path << " not found" << std::endl;
+      }
+      //Preload 0x0 <-> 0x80000000 jumps
+      ((uint32_t*)this->get(0))[0] = 0xf1401073;
+      ((uint32_t*)this->get(0))[1] = 0xf1401073;
+
+      // ((uint32_t*)this->get(0))[1] = 0xf1401073;
+      ((uint32_t*)this->get(0))[2] = 0x30101073;
+
+      ((uint32_t*)this->get(0))[3] = 0x800000b7;
+      ((uint32_t*)this->get(0))[4] = 0x000080e7;
+      
+      ((uint32_t*)this->get(0x80000000))[0] = 0x00000097;
+
+      ((uint32_t*)this->get(0xb0000000))[0] = 0x01C02023;
+      // F00FFF10
+      ((uint32_t*)this->get(0xf00fff10))[0] = 0x12345678;
+
+
+      
+
+      fseek(fp, 0, SEEK_END);
+      uint32_t size = ftell(fp);
+      fseek(fp, 0, SEEK_SET);
+      char* content = new char[size];
+      int x = fread(content, 1, size, fp);
+
+      if (!x) { std::cout << "COULD NOT READ FILE\n"; exit(1);}
+
+      int offset = 0;
+      char* line = content;
+      // std::cout << "WHTA\n";
+      while (1) {
+          if (line[0] == ':') {
+              uint32_t byteCount = hToI_old(line + 1, 2);
+              uint32_t nextAddr = hToI_old(line + 3, 4) + offset;
+              uint32_t key = hToI_old(line + 7, 2);
+              switch (key) {
+              case 0:
+                  for (uint32_t i = 0; i < byteCount; i++) {
+
+                      unsigned add = nextAddr + i;
+
+                      *(this->get(add)) = hToI_old(line + 9 + i * 2, 2);
+                      // std::cout << "lhi: Address: " << std::hex <<(add) << "\tValue: " << std::hex << hToI_old(line + 9 + i * 2, 2) << std::endl;
+                  }
+                  break;
+              case 2:
+  //              cout << offset << endl;
+                  offset = hToI_old(line + 9, 4) << 4;
+                  break;
+              case 4:
+  //              cout << offset << endl;
+                  offset = hToI_old(line + 9, 4) << 16;
+                  break;
+              default:
+  //              cout << "??? " << key << endl;
+                  break;
+              }
+          }
+
+          while (*line != '\n' && size != 0) {
+              line++;
+              size--;
+          }
+          if (size <= 1)
+              break;
+          line++;
+          size--;
+      }
+      
+
+      if (content) delete[] content;
+  }
+
+  };
+
+
+
+
+};
+
+
+#endif

emulator/include/obj.h

@@ -0,0 +1,210 @@
+/*******************************************************************************
+ HARPtools by Chad D. Kersey, Summer 2011
+*******************************************************************************/
+#ifndef __OBJ_H
+#define __OBJ_H
+
+#include <iostream>
+#include <string>
+#include <vector>
+#include <list>
+#include <stdlib.h>
+
+#include "types.h"
+#include "archdef.h"
+#include "instruction.h"
+#include "enc.h"
+#include "asm-tokens.h"
+
+namespace Harp {
+  class Decoder;
+  class Encoder;
+
+  class Ref {
+  public:
+    std::string name;
+    Ref(const std::string &n, bool r, Size ib = 0): 
+      name(n), bound(false), relative(r), ibase(ib) { }
+    virtual ~Ref() { }
+    virtual void bind(Addr addr, Addr base = 0) = 0;
+    virtual Addr getAddr() const = 0;
+
+    bool bound, relative;
+    Size ibase;
+  };
+
+  /* Used in not-yet-encoded code objects, plain old data. */
+  class SimpleRef : public Ref {
+  public:
+    SimpleRef(const std::string &name, Addr &addr, bool rel = false) : 
+      Ref(name, rel), addr(addr) { }
+    virtual void bind(Addr addr, Addr base = 0) {
+      std::cout << "Attempted to bind a SimpleRef.\n";
+      exit(1);
+    } 
+    virtual Addr getAddr() const { return this->addr; }
+    Byte *getAddrPtr() { return (Byte*)&addr; }
+
+  private:
+    Addr &addr;
+  };
+
+//   /* Used in already-encoded code objects. */
+//   class OffsetRef : public Ref {
+//   public:
+//     OffsetRef(
+//       const std::string &name, std::vector<Byte> &v, Size offset, Size bits,
+//       Size ws, bool rel = false, Size ibase = 0
+//     ) : Ref(name, rel, ibase), data(v), offset(offset), bits(bits), wordSize(ws)
+//     {}
+
+//     virtual void bind(Addr addr, Addr base = 0) {
+//       Size bytes(bits/8), remainder(bits%8);
+
+//       if (relative) {
+//         addr = addr - base;
+//         Word_s addr_s(addr);
+//         if ((addr_s >> bits) != ~0ull && (addr_s >> bits) != 0) goto noFit;
+//       } else {
+//         Addr mask = (1ull<<bits)-1;
+//         if (addr > mask) goto noFit;
+//       }
+
+//       { Byte mask((1ull<<remainder) - 1);
+//         Size i;
+//         for (i = 0; i < bytes; i++) {
+//           data[offset+i] = addr & 0xff;
+//           addr >>= 8;
+//         }
+//         data[offset+i] &= ~mask;
+//         data[offset+i] |= (addr&mask);
+//         bound = true; 
+//       }
+
+//       return;
+//     noFit:
+//       std::cout << "Attempt to bind a " << bits << "-bit "
+//                 << (relative?"":"non-") << "relative symbol to an address"
+//                                            " it cannot reach.\n";
+//       exit(1);
+//     }
+
+//     virtual Addr getAddr() const {
+//       Size bytes = bits/8, remainder = bits%8;
+//       Byte mask((1<<remainder)-1);
+//       Addr a(data[offset]&mask);
+
+//       for (Size i = 0; i < bytes-1; i++) {
+//         a |= data[offset + bytes - i - 1];
+//         a <<= 8;
+//       }
+//       return a;
+//     }
+
+//     Size getOffset() const { return offset; }
+//     Size getBits() const { return bits; }
+
+//   private:
+//     std::vector<Byte> &data;
+//     Size offset, bits, wordSize;
+//   };
+
+//   class Chunk { 
+//   public:
+//     Chunk(std::string n, Size a = 0, Word f = 0) : 
+//       name(n), alignment(a), bound(false), flags(f), global(false) {}
+//     virtual ~Chunk() { for (Size i = 0; i < refs.size(); i++) delete refs[i]; }
+//     void bind(Addr a) { address = a; bound = true; }
+//     void setGlobal() { global = true; }
+//     bool isGlobal() const { return global; }
+//     std::string name;
+//     Size alignment;
+//     bool bound, global;
+//     Addr address;
+//     Word flags;
+//     std::vector<Ref*> refs;    
+//   };
+
+//   class TextChunk : public Chunk {
+//   public:
+//     TextChunk(std::string n, Size a = 0, Word f = 0) 
+//       : Chunk(n, a, f), instructions() {}
+
+//     ~TextChunk() { 
+//       for (Size i = 0; i < instructions.size(); i++) delete instructions[i]; 
+//     }
+
+//     std::vector<Instruction*> instructions;
+//   };
+
+//   class DataChunk : public Chunk {
+//   public:
+//     DataChunk(std::string n, Size a = 0, Word f = 0) 
+//       : Chunk(n, a, f), size(0), contents() {}
+//     Size size;
+//     std::vector<Byte> contents; /* 0 to size bytes in length. */
+//   };
+
+//   class Obj {
+//   public:
+//     ~Obj() { for (Size i = 0; i < chunks.size(); i++) delete chunks[i]; }
+//     std::vector<Chunk*> chunks;
+//     Size entry;
+//   };
+
+//   class DynObj : public Obj {
+//   public:
+//     std::vector<std::string> deps;
+//   };
+
+//   class ObjReader {
+//   public:
+//     virtual Obj *read(std::istream &input) = 0;
+//   private:
+//   };
+
+//   class ObjWriter {
+//   public:
+//     virtual void write(std::ostream &output, const Obj &o) = 0;
+//   private:
+//   };
+
+//   class AsmReader : public ObjReader {
+//   public:
+//     AsmReader(ArchDef arch) :
+//       wordSize(arch.getWordSize()), nRegs(arch.getNRegs()) {}
+//     virtual Obj *read(std::istream &input);
+//   private:
+//     Size wordSize, nRegs;
+
+//     // Operand type sequences indexed by argument class
+//     enum ArgType {AT_END, AT_REG, AT_PREG, AT_LIT};
+//     static ArgType operandtype_table[][4]; // ArgClass -> ArgType[arg_idx]
+//   };
+   
+//   class HOFReader : public ObjReader {
+//   public:
+//     HOFReader(ArchDef &arch) : arch(arch) {}
+//     Obj *read(std::istream &input);
+//   private:
+//     const ArchDef &arch;
+//   };
+
+//   class AsmWriter : public ObjWriter {
+//   public:
+//     AsmWriter(ArchDef arch): wordSize(arch.getWordSize()) {}
+//     virtual void write(std::ostream &output, const Obj &obj);
+//   private:
+//     Size wordSize;
+//   };
+ 
+//   class HOFWriter : public ObjWriter {
+//   public:
+//     HOFWriter(ArchDef &arch) : arch(arch) {}
+//     virtual void write(std::ostream &output, const Obj &obj);
+//   private:
+//     const ArchDef &arch;
+//   };
+};
+
+#endif

emulator/include/qsim-harp.h

@@ -0,0 +1,169 @@
+/*******************************************************************************
+ HARPtools by Chad D. Kersey, Summer 2011
+*******************************************************************************/
+#ifndef EMU_INSTRUMENTATION
+#define EMU_INSTRUMENTATION
+#endif
+
+#ifndef __QSIM_HARP_H
+#define __QSIM_HARP_H
+
+#include "types.h"
+#include "core.h"
+#include "enc.h"
+#include "instruction.h"
+#include "mem.h"
+#include "obj.h"
+#include "archdef.h"
+
+#include <stdint.h>
+#include <iostream>
+#include <vector>
+#include <string>
+
+#include <qsim.h>
+
+namespace Harp {
+  class OSDomain {
+  public:
+    OSDomain(Harp::ArchDef &arch, std::string imgFile);
+
+    bool idle(unsigned i) const { return cpus[i].idle(); }
+    int get_tid(unsigned i) const { return cpus[i].get_tid(); }
+    bool get_prot(unsigned i) const { return cpus[i].get_prot(); }
+
+    int get_n() const { return cpus.size(); }
+
+    uint64_t run(unsigned i, uint64_t n) { return cpus[i].run(n); }
+    void connect_console(std::ostream &s);
+    void timer_interrupt() { /* TODO: timer convention */ }
+    void interrupt(unsigned i, int vec) { cpus[i].interrupt(vec); }
+    bool booted(unsigned i) const { return cpus[i].booted(); }
+    void save_state(const char* state_file);
+
+    template <typename T>
+      void set_atomic_cb
+        (T *p, typename Qsim::OSDomain::atomic_cb_obj<T>::atomic_cb_t f)
+    {
+      atomic_cbs.push_back(new Qsim::OSDomain::atomic_cb_obj<T>(p, f));
+    }
+
+    template <typename T>
+      void set_inst_cb
+        (T* p, typename Qsim::OSDomain::inst_cb_obj<T>::inst_cb_t f)
+    { 
+      inst_cbs.push_back(new Qsim::OSDomain::inst_cb_obj<T>(p, f));
+    }
+
+    template <typename T>
+      void set_int_cb
+        (T *p, typename Qsim::OSDomain::int_cb_obj<T>::int_cb_t f)
+    {
+      int_cbs.push_back(new Qsim::OSDomain::int_cb_obj<T>(p, f));
+    }
+
+    template <typename T>
+      void set_mem_cb
+        (T *p, typename Qsim::OSDomain::mem_cb_obj<T>::mem_cb_t f)
+    {
+      mem_cbs.push_back(new Qsim::OSDomain::mem_cb_obj<T>(p, f));
+    }
+
+    template <typename T>
+      void set_magic_cb
+        (T *p, typename Qsim::OSDomain::magic_cb_obj<T>::magic_cb_t f)
+    {
+      magic_cbs.push_back(new Qsim::OSDomain::magic_cb_obj<T>(p, f));
+    }
+
+    template <typename T>
+      void set_io_cb
+        (T *p, typename Qsim::OSDomain::io_cb_obj<T>::io_cb_t f)
+      { /* Do nothing. We have no separate IO address space. */ }
+
+    template <typename T>
+      void set_reg_cb
+        (T *p, typename Qsim::OSDomain::reg_cb_obj<T>::reg_cb_t f)
+    {
+      reg_cbs.push_back(new Qsim::OSDomain::reg_cb_obj<T>(p, f));
+    }
+
+    template <typename T> void mem_rd(T& d, uint64_t paddr);
+    template <typename T> void mem_rd_virt(unsigned i, T& d, uint64_t vaddr);
+    template <typename T> void mem_wr(T& d, uint64_t paddr);
+    template <typename T> void mem_wr_virt(unsigned i, T& d, uint64_t vaddr);
+
+    static OSDomain *osDomain;
+
+    bool do_atomic(unsigned c) {
+      bool rval(false);
+      for (unsigned i = 0; i < atomic_cbs.size(); ++i)
+        if ((*atomic_cbs[i])(c)) rval = true;
+      return rval;
+    }
+
+    void do_inst(unsigned c, uint64_t va, uint64_t pa, uint8_t l, 
+                 const uint8_t *b, enum inst_type t)
+    {
+      for (unsigned i = 0; i < inst_cbs.size(); ++i)
+        (*inst_cbs[i])(c, va, pa, l, b, t);
+    }
+
+    void do_int(unsigned c, int v) {
+      for (unsigned i = 0; i < int_cbs.size(); ++i)
+        (*int_cbs[i])(c, v);
+    }
+
+    void do_mem(unsigned c, uint64_t va, uint64_t pa, uint8_t s, bool w) {
+      for (unsigned i = 0; i < mem_cbs.size(); ++i)
+        (*mem_cbs[i])(c, va, pa, s, w);
+    }
+
+    bool do_magic(unsigned c, uint64_t r0) {
+      bool rval(false);
+      for (unsigned i = 0; i < magic_cbs.size(); ++i)
+        if ((*magic_cbs[i])(c, r0)) rval = true;
+      return rval;
+    }
+
+    void do_reg(unsigned c, int r, uint8_t s, bool w) {
+      for (unsigned i = 0; i < reg_cbs.size(); ++i)
+        (*reg_cbs[i])(c, r, s, w);
+    }
+
+  private:
+    class Cpu {
+    public:
+      Cpu(Harp::OSDomain &osd);
+      Cpu(): dec(NULL), core(NULL) {}
+      ~Cpu() { if (dec) delete dec; if (core) delete core; }
+
+      bool idle() const { return false; }
+      int get_tid() const { return 0; }
+      bool get_prot() const { return core->getSupervisorMode(); }
+      uint64_t run(uint64_t n);
+      void interrupt(int vec) { core->interrupt(vec); }
+      bool booted() const { return core->running(); }
+
+      Harp::OSDomain *osd;
+      Harp::Decoder *dec;
+      Harp::Core *core;
+    };
+
+    Harp::ArchDef arch;
+
+    Harp::MemoryUnit mu;
+    Harp::RamMemDevice ram;
+    Harp::ConsoleMemDevice *console;
+
+    std::vector <Harp::OSDomain::Cpu> cpus;
+
+    std::vector <Qsim::OSDomain::atomic_cb_obj_base*> atomic_cbs;
+    std::vector <Qsim::OSDomain::inst_cb_obj_base*>   inst_cbs;
+    std::vector <Qsim::OSDomain::int_cb_obj_base*>    int_cbs;
+    std::vector <Qsim::OSDomain::mem_cb_obj_base*>    mem_cbs;
+    std::vector <Qsim::OSDomain::magic_cb_obj_base*>  magic_cbs;
+    std::vector <Qsim::OSDomain::reg_cb_obj_base*>    reg_cbs;
+  };
+};
+#endif

emulator/include/types.h

@@ -0,0 +1,25 @@
+/*******************************************************************************
+ HARPtools by Chad D. Kersey, Summer 2011
+*******************************************************************************/
+#ifndef __TYPES_H
+#define __TYPES_H
+
+#include <stdint.h>
+
+namespace Harp {
+  typedef uint8_t  Byte;
+  typedef uint32_t Word;
+  typedef uint32_t Word_u;
+  typedef int32_t  Word_s;
+
+  typedef Word_u   Addr;
+  typedef Word_u   Size;
+
+  typedef unsigned RegNum;
+  typedef unsigned ThdNum;
+
+  enum MemFlags {RD_USR = 1, WR_USR = 2,  EX_USR = 4, 
+                 RD_SUP = 8, WR_SUP = 16, EX_SUP = 32};
+};
+
+#endif

emulator/include/util.h

@@ -0,0 +1,24 @@
+/*******************************************************************************
+ HARPtools by Chad D. Kersey, Summer 2011
+*******************************************************************************/
+#ifndef __UTIL_H
+#define __UTIL_H
+
+#include <vector>
+#include "types.h"
+
+namespace Harp {
+  Word_u bytesToWord(const Byte *b, Size wordSize);
+  void wordToBytes(Byte *b, Word_u w, Size wordSize);
+  Word_u flagsToWord(bool r, bool w, bool x);
+  void wordToFlags(bool &r, bool &w, bool &x, Word_u f);
+
+  class OutOfBytes {};
+
+  Byte readByte(const std::vector<Byte> &b, Size &n);
+  Word_u readWord(const std::vector<Byte> &b, Size &n, Size wordSize);
+  void writeByte(std::vector<Byte> &p, Size &n, Byte b);
+  void writeWord(std::vector<Byte> &p, Size &n, Size wordSize, Word w);
+};
+
+#endif

emulator/instruction.cpp

@@ -0,0 +1,804 @@
+/*******************************************************************************
+ HARPtools by Chad D. Kersey, Summer 2011
+*******************************************************************************/
+#include <iostream>
+#include <stdlib.h>
+
+#include "include/instruction.h"
+#include "include/obj.h"
+#include "include/core.h"
+#include "include/harpfloat.h"
+#include "include/debug.h"
+
+#ifdef EMU_INSTRUMENTATION
+#include "include/qsim-harp.h"
+#endif
+
+using namespace Harp;
+using namespace std;
+
+/* It is important that this stays consistent with the Harp::Instruction::Opcode
+   enum. */
+
+ostream &Harp::operator<<(ostream& os, Instruction &inst) {
+  os << dec;
+
+  // if (inst.predicated) {
+  //   os << "@p" << dec << inst.pred << " ? ";
+  // }
+
+  // os << inst.instTable[inst.op].opString << ' ';
+  // if (inst.rdestPresent) os << "%r" << dec << inst.rdest << ' ';
+  // if (inst.pdestPresent) os << "@p" << inst.pdest << ' ';
+  // for (int i = 0; i < inst.nRsrc; i++) {
+  //   os << "%r" << dec << inst.rsrc[i] << ' ';
+  // }
+  // for (int i = 0; i < inst.nPsrc; i++) {
+  //   os << "@p" << dec << inst.psrc[i] << ' ';
+  // }
+  // if (inst.immsrcPresent) {
+  //   if (inst.refLiteral) os << inst.refLiteral->name;
+  //   else os << "#0x" << hex << inst.immsrc;
+  // }
+
+  os << instTable[inst.op].opString;
+
+  os << ';';
+  return os;
+}
+
+bool checkUnanimous(unsigned p, const std::vector<std::vector<Reg<Word> > >& m,
+  const std::vector<bool> &tm) {
+  bool same;
+  unsigned i;
+  for (i = 0; i < m.size(); ++i) {
+    if (tm[i]) {
+      same = m[i][p];
+      break;
+    }
+  }
+  if (i == m.size()) throw DivergentBranchException();
+
+  //std::cout << "same: " << same << "  with -> ";
+  for (; i < m.size(); ++i) {
+    if (tm[i]) {
+      //std::cout << " " << (bool(m[i][p]));
+      if (same != (bool(m[i][p]))) {
+        //std::cout << " FALSE\n";
+        return false;
+      }
+    } 
+  }
+  //std::cout << " TRUE\n";
+  return true;
+}
+
+Word signExt(Word w, Size bit, Word mask) {
+  if (w>>(bit-1)) w |= ~mask;
+  return w;
+}
+
+void Instruction::executeOn(Warp &c) {
+  D(3, "Begin instruction execute.");
+
+  /* If I try to execute a privileged instruction in user mode, throw an
+     exception 3. */
+  if (instTable[op].privileged && !c.supervisorMode) {
+    std::cout << "INTERRUPT SUPERVISOR\n";
+    c.interrupt(3);
+    return;
+  }
+
+  // /* Also throw exceptions on non-masked divergent branches. */
+  // if (instTable[op].controlFlow) {
+  //   Size t, count, active;
+  //   for (t = 0, count = 0, active = 0; t < c.activeThreads; ++t) {
+  //     if ((!predicated || c.pred[t][pred]) && c.tmask[t]) ++count;
+  //     if (c.tmask[t]) ++active;
+  //   }
+
+  //   if (count != 0 && count != active)
+  //     throw DivergentBranchException();
+  // }
+
+  Size nextActiveThreads = c.activeThreads;
+  Size wordSz = c.core->a.getWordSize();
+  Word nextPc = c.pc;
+
+  c.memAccesses.clear();
+  
+  // If we have a load, overwriting a register's contents, we have to make sure
+  // ahead of time it will not fault. Otherwise we may perform an indirect load
+  // by mistake.
+  // if (op == L_INST && rdest == rsrc[0]) {
+  //   for (Size t = 0; t < c.activeThreads; t++) {
+  //     if ((!predicated || c.pred[t][pred]) && c.tmask[t]) {
+  //       Word memAddr = c.reg[t][rsrc[0]] + immsrc;
+  //       c.core->mem.read(memAddr, c.supervisorMode);
+  //     }
+  //   }
+  // }
+
+  bool sjOnce(true), // Has not yet split or joined once.
+       pcSet(false); // PC has already been set
+  for (Size t = 0; t < c.activeThreads; t++) {
+    vector<Reg<Word> > &reg(c.reg[t]);
+    vector<Reg<bool> > &pReg(c.pred[t]);
+    stack<DomStackEntry> &domStack(c.domStack);
+
+    //std::cout << std::hex << "opcode: " << op << "  func3: " << func3 << "\n";
+    //if (op == GPGPU) //std::cout << "OPCODE MATCHED GPGPU\n";
+
+    // If this thread is masked out, don't execute the instruction, unless it's
+    // a split or join.
+    // if (((predicated && !pReg[pred]) || !c.tmask[t]) &&
+    //       op != SPLIT && op != JOIN) continue;
+
+    bool split = (op == GPGPU) && (func3 == 2);
+    bool join  = (op == GPGPU) && (func3 == 3);
+
+
+    predicated = (op == GPGPU) && ((func3 == 7) || (func3 == 2));
+
+
+    // printf("Predicated: %d, split: %d, join: %d\n",predicated, split, join );
+    // printf("%d && ((%d) || (%d))\n",(op == GPGPU), (func3 == 7), (func3 == 2) );
+
+    // cout << "before " << op << " = " << GPGPU << "\n";
+    if (((predicated && !reg[pred]) || !c.tmask[t]) && !split && !join)
+    {
+      // cout << "about to continue\n";
+      continue;
+    }
+    // cout << "after\n";
+
+    ++c.insts;
+
+    Word memAddr;
+    Word shift_by;
+    Word shamt;
+    Word temp;
+    Word data_read;
+    int op1, op2;
+    bool m_exten;
+    // std::cout << "op = " << op << "\n";
+    // std::cout << "R_INST: " << R_INST << "\n";
+    switch (op) {
+
+      case NOP:
+        //std::cout << "NOP_INST\n";
+        break;
+      case R_INST:
+        // std::cout << "R_INST\n";
+        m_exten = func7 & 0x1;
+
+        if (m_exten)
+        {
+          // std::cout << "FOUND A MUL/DIV\n";
+
+          switch (func3)
+          {
+            case 0:
+              // MUL
+              // cout << "MUL\n";
+              reg[rdest] = ((int) reg[rsrc[0]]) * ((int) reg[rsrc[1]]);
+              break;
+            case 1:
+              // MULH
+              {
+                int64_t first  = (int64_t) reg[rsrc[0]];
+                if (reg[rsrc[0]] & 0x80000000)
+                {
+                  first = first | 0xFFFFFFFF00000000;
+                }
+                int64_t second = (int64_t) reg[rsrc[1]];
+                if (reg[rsrc[1]] & 0x80000000)
+                {
+                  second = second | 0xFFFFFFFF00000000;
+                }
+                // cout << "mulh: " << std::dec << first << " * " << second;
+                uint64_t result = first * second;
+                reg[rdest] = ( result >> 32) & 0xFFFFFFFF;
+                // cout << " = " << result << "   or  " <<  reg[rdest] << "\n";
+              }
+              break;
+            case 2:
+              // MULHSU
+              {
+                int64_t first  = (int64_t) reg[rsrc[0]];
+                if (reg[rsrc[0]] & 0x80000000)
+                {
+                  first = first | 0xFFFFFFFF00000000;
+                }
+                int64_t second = (int64_t) reg[rsrc[1]];
+                reg[rdest] = (( first * second ) >> 32) & 0xFFFFFFFF;
+              }
+              break;
+            case 3:
+              // MULHU
+              {
+                uint64_t first  = (uint64_t) reg[rsrc[0]];
+                uint64_t second = (uint64_t) reg[rsrc[1]];
+                // cout << "MULHU\n";
+                reg[rdest] = (( first * second) >> 32) & 0xFFFFFFFF;
+              }
+                break;
+            case 4:
+              // DIV
+              if (reg[rsrc[1]] == 0) 
+              {
+                reg[rdest] = -1;
+                break;
+              }
+              // cout << "dividing: " << dec << ((int) reg[rsrc[0]]) << " / " << ((int) reg[rsrc[1]]);
+              reg[rdest] = ( (int) reg[rsrc[0]]) / ( (int) reg[rsrc[1]]);
+              // cout << " = " << ((int) reg[rdest]) << "\n";
+              break;
+            case 5:
+              // DIVU
+              if (reg[rsrc[1]] == 0) 
+              {
+                reg[rdest] = -1;
+                break;
+              }
+              reg[rdest] = ((uint32_t) reg[rsrc[0]]) / ((uint32_t) reg[rsrc[1]]);
+              break;
+            case 6:
+              // REM
+              if (reg[rsrc[1]] == 0) 
+              {
+                reg[rdest] = reg[rsrc[0]];
+                break;
+              }
+              reg[rdest] = ((int) reg[rsrc[0]]) % ((int) reg[rsrc[1]]);
+              break;
+            case 7:
+              // REMU
+              if (reg[rsrc[1]] == 0) 
+              {
+                reg[rdest] = reg[rsrc[0]];
+                break;
+              }
+              reg[rdest] = ((uint32_t) reg[rsrc[0]]) % ((uint32_t) reg[rsrc[1]]);
+              break;
+            default:
+              cout << "unsupported MUL/DIV instr\n";
+              exit(1);
+          }
+        }
+        else
+        {
+          // std::cout << "NORMAL R-TYPE\n";
+          switch (func3)
+          {
+            case 0:
+              if (func7)
+              {
+                  reg[rdest] = reg[rsrc[0]] - reg[rsrc[1]];
+                  reg[rdest].trunc(wordSz);
+              }
+              else
+              {
+                  reg[rdest] = reg[rsrc[0]] + reg[rsrc[1]];
+                  reg[rdest].trunc(wordSz);
+              }
+              break;
+            case 1:
+                  reg[rdest] = reg[rsrc[0]] << reg[rsrc[1]];
+                  reg[rdest].trunc(wordSz);
+              break;
+            case 2:
+              if ( int(reg[rsrc[0]]) <  int(reg[rsrc[1]]))
+              {
+                reg[rdest] = 1;
+              }
+              else
+              {
+                reg[rdest] = 0;
+              }
+              break;
+            case 3:
+              if ( Word_u(reg[rsrc[0]]) <  Word_u(reg[rsrc[1]]))
+              {
+                reg[rdest] = 1;
+              }
+              else
+              {
+                reg[rdest] = 0;
+              }
+              break;
+            case 4:
+              reg[rdest] = reg[rsrc[0]] ^ reg[rsrc[1]];
+              break;
+            case 5:
+              if (func7)
+              {
+                  reg[rdest] = int(reg[rsrc[0]]) >> int(reg[rsrc[1]]);
+                  reg[rdest].trunc(wordSz);
+              }
+              else
+              {
+                  reg[rdest] = Word_u(reg[rsrc[0]]) >> Word_u(reg[rsrc[1]]);
+                  reg[rdest].trunc(wordSz);
+              }
+              break;
+            case 6:
+              reg[rdest] = reg[rsrc[0]] | reg[rsrc[1]];
+              break;
+            case 7:
+              reg[rdest] = reg[rsrc[0]] & reg[rsrc[1]];
+              break;
+            default:
+              cout << "ERROR: UNSUPPORTED R INST\n";
+              exit(1);
+          }
+        }
+        break;
+      case L_INST:
+           //std::cout << "L_INST\n";
+           memAddr   = ((reg[rsrc[0]] + immsrc) & 0xFFFFFFFC);
+           shift_by  = ((reg[rsrc[0]] + immsrc) & 0x00000003) * 8;
+           data_read = c.core->mem.read(memAddr, c.supervisorMode);
+           // //std::cout <<std::hex<< "EXECUTE: " << reg[rsrc[0]] << " + " << immsrc << " = " << memAddr <<  " -> data_read: " << data_read << "\n";
+#ifdef EMU_INSTRUMENTATION
+           Harp::OSDomain::osDomain->
+             do_mem(0, memAddr, c.core->mem.virtToPhys(memAddr), 8, true);
+#endif
+        switch (func3)
+        {
+
+          case 0:
+            // LB
+            reg[rdest] = signExt((data_read >> shift_by) & 0xFF, 8, 0xFF);
+            break;
+          case 1:
+            // LH
+            // //std::cout << "shifting by: " << shift_by << "  final data: " << ((data_read >> shift_by) & 0xFFFF, 16, 0xFFFF) << "\n";
+            reg[rdest] = signExt((data_read >> shift_by) & 0xFFFF, 16, 0xFFFF);
+            break;
+          case 2:
+            reg[rdest] = int(data_read & 0xFFFFFFFF);
+            break;
+          case 4:
+            // LBU
+            reg[rdest] = unsigned((data_read >> shift_by) & 0xFF);
+            break;
+          case 5:
+            reg[rdest] = unsigned((data_read >> shift_by) & 0xFFFF);
+            break;
+          default:
+            cout << "ERROR: UNSUPPORTED L INST\n";
+            exit(1);
+          c.memAccesses.push_back(Warp::MemAccess(false, memAddr));
+        }
+        break;
+      case I_INST:
+        //std::cout << "I_INST\n";
+        switch (func3)
+        {
+
+          case 0:
+            // ADDI
+            reg[rdest] = reg[rsrc[0]] + immsrc;
+            reg[rdest].trunc(wordSz);
+            break;
+          case 2:
+            // SLTI
+            if ( int(reg[rsrc[0]]) <  int(immsrc))
+            {
+              reg[rdest] = 1;
+            }
+            else
+            {
+              reg[rdest] = 0;
+            }
+            break;
+          case 3:
+            // SLTIU
+            op1 = (unsigned) reg[rsrc[0]];
+            if ( unsigned(reg[rsrc[0]]) <  unsigned(immsrc))
+            {
+              reg[rdest] = 1;
+            }
+            else
+            {
+              reg[rdest] = 0;
+            }
+            break;
+          case 4:
+            // XORI
+            reg[rdest] = reg[rsrc[0]] ^ immsrc;
+            break;
+          case 6:
+            // ORI;
+            reg[rdest] = reg[rsrc[0]] | immsrc;
+            break;
+          case 7:
+            // ANDI
+            reg[rdest] = reg[rsrc[0]] & immsrc;
+            break;
+          case 1:
+            // SLLI
+            reg[rdest] = reg[rsrc[0]] << immsrc;
+            reg[rdest].trunc(wordSz);
+            break;
+          case 5:
+            if ((func7 == 0))
+            {
+              // SRLI
+                // //std::cout << "WTF\n";
+                bool isNeg  = ((0x80000000 & reg[rsrc[0]])) > 0;
+                Word result = Word_u(reg[rsrc[0]]) >> Word_u(immsrc);
+                // if (isNeg)
+                // {
+                //   Word mask = 0x80000000;
+                //   for (int i = 32; i < Word_u(immsrc); i++)
+                //   {
+                //     result |= mask;
+                //     mask = mask >> 1;
+                //   }
+                // }
+
+                reg[rdest] = result;
+      
+                reg[rdest].trunc(wordSz);
+            }
+            else
+            {
+                // SRAI
+                // //std::cout << "WOHOOOOO\n";
+                op1 = reg[rsrc[0]];
+                op2 = immsrc;
+                reg[rdest] = op1 >> op2;
+                reg[rdest].trunc(wordSz);
+            }
+            break;
+          default:
+            cout << "ERROR: UNSUPPORTED L INST\n";
+            exit(1);
+        }
+        break;
+      case S_INST:
+        //std::cout << "S_INST\n";
+        ++c.stores;
+        memAddr = reg[rsrc[0]] + immsrc;
+        // //std::cout << "STORE MEM ADDRESS: " << std::hex << reg[rsrc[0]] << " + " << immsrc << "\n";
+        // //std::cout << "FUNC3: " << func3 << "\n";
+        if (memAddr == 0x00010000)
+        {
+          std::cout << (char) reg[rsrc[1]];
+          break;
+        }
+        switch (func3)
+        {
+          case 0:
+            // //std::cout << "SB\n";
+            c.core->mem.write(memAddr, reg[rsrc[1]] & 0x000000FF, c.supervisorMode, 1);
+            break;
+          case 1:
+            // //std::cout << "SH\n";
+            c.core->mem.write(memAddr, reg[rsrc[1]], c.supervisorMode, 2);
+            break;
+          case 2:
+            // //std::cout << std::hex << "SW: about to write: " << reg[rsrc[1]] << " to " << memAddr << "\n"; 
+            c.core->mem.write(memAddr, reg[rsrc[1]], c.supervisorMode, 4);
+            break;
+          default:
+            cout << "ERROR: UNSUPPORTED S INST\n";
+            exit(1);
+        }
+        c.memAccesses.push_back(Warp::MemAccess(true, memAddr));
+#ifdef EMU_INSTRUMENTATION
+       Harp::OSDomain::osDomain->
+       do_mem(0, memAddr, c.core->mem.virtToPhys(memAddr), 8, true);
+#endif
+        break;
+      case B_INST:
+        //std::cout << "B_INST\n";
+        switch (func3)
+        {
+          case 0:
+            // BEQ
+            if (int(reg[rsrc[0]]) == int(reg[rsrc[1]]))
+            {
+              if (!pcSet) nextPc = (c.pc - 4) + immsrc;
+              pcSet = true;
+            }
+            break;
+          case 1:
+            // BNE
+            if (int(reg[rsrc[0]]) != int(reg[rsrc[1]]))
+            {
+              if (!pcSet) nextPc = (c.pc - 4) + immsrc;
+              pcSet = true;
+            }
+            break;
+          case 4:
+            // BLT
+            if (int(reg[rsrc[0]]) < int(reg[rsrc[1]]))
+            {
+              if (!pcSet) nextPc = (c.pc - 4) + immsrc;
+              pcSet = true;
+            }
+            break;
+          case 5:
+            // BGE
+            if (int(reg[rsrc[0]]) >= int(reg[rsrc[1]]))
+            {
+              if (!pcSet) nextPc = (c.pc - 4) + immsrc;
+              pcSet = true;
+            }
+            break;
+          case 6:
+            // BLTU
+            if (Word_u(reg[rsrc[0]]) < Word_u(reg[rsrc[1]]))
+            {
+              if (!pcSet) nextPc = (c.pc - 4) + immsrc;
+              pcSet = true;
+            }
+            break;
+          case 7:
+            // BGEU
+            if (Word_u(reg[rsrc[0]]) >= Word_u(reg[rsrc[1]]))
+            {
+              if (!pcSet) nextPc = (c.pc - 4) + immsrc;
+              pcSet = true;
+            }
+            break;
+        }
+        break;
+      case LUI_INST:
+        //std::cout << "LUI_INST\n";
+        reg[rdest] = (immsrc << 12) & 0xfffff000;
+        break;
+      case AUIPC_INST:
+        //std::cout << "AUIPC_INST\n";
+        reg[rdest] = ((immsrc << 12) & 0xfffff000) + (c.pc - 4);
+        break;
+      case JAL_INST:
+        //std::cout << "JAL_INST\n";
+        if (!pcSet) nextPc = (c.pc - 4) + immsrc;
+        if (!pcSet) //std::cout << "JAL... SETTING PC: " << nextPc << "\n"; 
+        if (rdest != 0)
+        {
+          reg[rdest] = c.pc;
+        }
+        pcSet = true;
+        break;
+      case JALR_INST:
+        //std::cout << "JALR_INST\n";
+        if (!pcSet) nextPc = reg[rsrc[0]] + immsrc;
+        if (!pcSet) //std::cout << "JALR... SETTING PC: " << nextPc << "\n"; 
+        if (rdest != 0)
+        {
+          reg[rdest] = c.pc;
+        }
+        pcSet = true;
+        break;
+      case SYS_INST:
+        //std::cout << "SYS_INST\n";
+        temp = reg[rsrc[0]];
+        switch (func3)
+        {
+          case 1:
+            // printf("Case 1\n");
+            if (rdest != 0)
+            {
+              reg[rdest] = c.csr[immsrc & 0x00000FFF];
+            }
+            c.csr[immsrc & 0x00000FFF] = temp;
+            
+            break;
+          case 2:
+            // printf("Case 2\n");
+            if (rdest != 0)
+            {
+              // printf("Reading from CSR: %d = %d\n", (immsrc & 0x00000FFF),  c.csr[immsrc & 0x00000FFF]);
+              reg[rdest] = c.csr[immsrc & 0x00000FFF];
+            }
+            // printf("Writing to CSR --> %d = %d\n", immsrc,  (temp |  c.csr[immsrc & 0x00000FFF]));
+            c.csr[immsrc & 0x00000FFF] = temp |  c.csr[immsrc & 0x00000FFF];
+            
+            break;
+          case 3:
+            // printf("Case 3\n");
+            if (rdest != 0)
+            {              
+              reg[rdest]                 = c.csr[immsrc & 0x00000FFF];
+            }
+              c.csr[immsrc & 0x00000FFF] = temp &  (~c.csr[immsrc & 0x00000FFF]);
+            
+            break;
+          case 5:
+            // printf("Case 5\n");
+            if (rdest != 0)
+            {
+              reg[rdest] = c.csr[immsrc & 0x00000FFF];
+            }
+              c.csr[immsrc & 0x00000FFF] = rsrc[0];
+            
+            break;
+          case 6:
+            // printf("Case 6\n");
+            if (rdest != 0)
+            {              
+              reg[rdest]                 = c.csr[immsrc & 0x00000FFF];
+            }
+              c.csr[immsrc & 0x00000FFF] = rsrc[0] |  c.csr[immsrc & 0x00000FFF];
+            
+            break;
+          case 7:
+            // printf("Case 7\n");
+            if (rdest != 0)
+            {              
+              reg[rdest] = c.csr[immsrc & 0x00000FFF];
+            }
+              c.csr[immsrc & 0x00000FFF] = rsrc[0] &  (~c.csr[immsrc & 0x00000FFF]);
+            
+            break;
+          case 0:
+          if (immsrc < 2)
+          {
+            //std::cout << "INTERRUPT ECALL/EBREAK\n";
+            nextActiveThreads = 0;
+            c.spawned = false;
+            // c.interrupt(0);
+          }
+            break;
+          default:
+            break;
+        }
+        break;
+      case TRAP:
+        //std::cout << "INTERRUPT TRAP\n";
+        nextActiveThreads = 0;
+        c.interrupt(0);
+        break;
+      case FENCE:
+        //std::cout << "FENCE_INST\n";
+        break;
+      case PJ_INST:
+        // pred jump reg
+        //std::cout << "pred jump... src: " << rsrc[0] << std::hex << " val: " << reg[rsrc[0]] << " dest: " <<  reg[rsrc[1]] << "\n";
+        if (reg[rsrc[0]])
+        {
+          if (!pcSet) nextPc = reg[rsrc[1]];
+          pcSet = true;
+        }
+        break;
+      case GPGPU:
+        //std::cout << "GPGPU\n";
+        switch(func3)
+        {
+          case 0:
+            // WSPAWN
+            //std::cout << "WSPAWN\n";
+            if (sjOnce)
+            {
+              sjOnce = false;
+              D(0, "Spawning a new warp.");
+              // //std::cout << "SIZE: " << c.core->w.size() << "\n";
+              for (unsigned i = 0; i < c.core->w.size(); ++i)
+              {
+                // std::cout << "SPAWNING WARP\n";
+                Warp &newWarp(c.core->w[i]);
+                // //std::cout << "STARTING\n";
+                if (newWarp.spawned == false) {
+                  // //std::cout << "ABOUT TO START\n";
+                  newWarp.pc     = reg[rsrc[0]];
+                  newWarp.reg[0] = reg;
+                  newWarp.csr = c.csr;
+                  newWarp.activeThreads = 1;
+                  newWarp.supervisorMode = false;
+                  newWarp.spawned = true;
+                  break;
+                }
+              }
+            }
+            break;
+          case 2:
+          {
+            // SPLIT
+            //std::cout << "SPLIT\n";
+            if (sjOnce)
+            {
+              sjOnce = false;
+              if (checkUnanimous(pred, c.reg, c.tmask)) {
+                //std::cout << "Unanimous pred: " << pred << "  val: " << reg[pred] << "\n";
+                DomStackEntry e(c.tmask);
+                e.uni = true;
+                c.domStack.push(e);
+                break;
+              }
+              DomStackEntry e(pred, c.reg, c.tmask, c.pc);
+              c.domStack.push(c.tmask);
+              c.domStack.push(e);
+              for (unsigned i = 0; i < e.tmask.size(); ++i)
+              {
+                c.tmask[i] = !e.tmask[i] && c.tmask[i];
+              }
+            }
+          }
+            break;
+          case 3:
+            // JOIN
+            //std::cout << "JOIN\n";
+            if (sjOnce)
+            {
+              sjOnce = false;
+              if (!c.domStack.empty() && c.domStack.top().uni) {
+                D(2, "Uni branch at join");
+                c.tmask = c.domStack.top().tmask;
+                c.domStack.pop();
+                break;
+              }
+              if (!c.domStack.top().fallThrough) {
+                if (!pcSet) nextPc = c.domStack.top().pc;
+                  pcSet = true;
+              }
+              c.tmask = c.domStack.top().tmask;
+              c.domStack.pop();
+            }
+            break;
+          case 4:
+            // JMPRT
+            //std::cout << "JMPRT\n";
+            nextActiveThreads = 1;
+            if (!pcSet) nextPc = reg[rsrc[0]];
+            pcSet = true;
+            break;
+          case 5:
+            // CLONE
+            //std::cout << "CLONE\n";
+            // //std::cout << "CLONING REG: " << rsrc[0] << " lane: " << reg[rsrc[0]] << "\n";
+            c.reg[reg[rsrc[0]]] = reg;
+            break;
+          case 6:
+            // JALRS
+            //std::cout << "JALRS\n";
+            nextActiveThreads = reg[rsrc[1]];
+            reg[rdest] = c.pc;
+            if (!pcSet) nextPc = reg[rsrc[0]];
+            pcSet = true;
+            // //std::cout << "ACTIVE_THREDS: " << rsrc[1] << " val: " << reg[rsrc[1]] << "\n";
+            // //std::cout << "nextPC: " << rsrc[0] << " val: " << std::hex << reg[rsrc[0]] << "\n";
+            break;
+          default:
+            cout << "ERROR: UNSUPPORTED GPGPU INSTRUCTION " << *this << "\n";
+        }
+        break;
+      default:
+        cout << "pc: " << hex << (c.pc) << "\n";
+        cout << "aERROR: Unsupported instruction: " << *this << "\n" << flush;
+        exit(1);
+    }
+  }
+
+  D(3, "End instruction execute.");
+
+  c.activeThreads = nextActiveThreads;
+
+  // if (nextActiveThreads != 0)
+  // {
+  //   for (int i = 7; i >= c.activeThreads; i--)
+  //   {
+  //     c.tmask[i] = c.tmask[i] && false;
+  //   }
+  // }
+
+
+
+  // //std::cout << "new thread mask: ";
+  // for (int i = 0; i < c.tmask.size(); ++i) //std::cout << " " << c.tmask[i];
+  // //std::cout << "\n";
+
+  // This way, if pc was set by a side effect (such as interrupt), it will
+  // retain its new value.
+  if (pcSet) c.pc = nextPc;
+  
+  if (nextActiveThreads > c.reg.size()) {
+    cerr << "Error: attempt to spawn " << nextActiveThreads << " threads. "
+         << c.reg.size() << " available.\n";
+    abort();
+  }
+}

emulator/mem.cpp

@@ -0,0 +1,284 @@
+/*******************************************************************************
+ HARPtools by Chad D. Kersey, Summer 2011
+*******************************************************************************/
+#include <fstream>
+#include <iostream>
+#include <iomanip>
+#include <string>
+#include <vector>
+#include <stdlib.h>
+#include <pthread.h>
+
+#include "include/debug.h"
+#include "include/types.h"
+#include "include/util.h"
+#include "include/mem.h"
+#include "include/core.h"
+
+using namespace std;
+using namespace Harp;
+
+RamMemDevice::RamMemDevice(const char *filename, Size wordSize) :
+  wordSize(wordSize), contents()
+{
+  ifstream input(filename);
+
+  if (!input) {
+    cout << "Error reading file \"" << filename << "\" into RamMemDevice.\n";
+    exit(1);
+  }
+
+  do { contents.push_back(input.get()); } while (input);
+
+  while (contents.size() % wordSize) contents.push_back(0x00);
+}
+
+RamMemDevice::RamMemDevice(Size size, Size wordSize) : 
+  contents(size), wordSize(wordSize) {}
+
+void RomMemDevice::write(Addr, Word) {
+  cout << "Attempt to write to ROM.\n";
+  exit(1);
+}
+
+Word RamMemDevice::read(Addr addr) {
+  D(2, "RAM read, addr=0x" << hex << addr);
+  Word w = readWord(contents, addr, wordSize - addr%wordSize);
+  return w;
+}
+
+void RamMemDevice::write(Addr addr, Word w) {
+  D(2, "RAM write, addr=0x" << hex << addr);
+  writeWord(contents, addr, wordSize - addr%wordSize, w);
+}
+
+MemDevice &MemoryUnit::ADecoder::doLookup(Addr a, Size &bit) {
+  if (range == 0 || (a&((1ll<<bit)-1)) >= range) {
+    ADecoder *p(((a>>bit)&1)?oneChild:zeroChild);
+    if (p) { bit--; return p->doLookup(a, bit); }
+    else {cout << "lookup of 0x" << hex << a << " failed.\n";
+          throw BadAddress();}
+  } else {
+    return *md;
+  }
+}
+
+void MemoryUnit::ADecoder::map(Addr a, MemDevice &m, Size r, Size bit)
+{
+  if ((1llu << bit) <= r) {
+    md = &m;
+    range = m.size();
+  } else {
+    ADecoder *&child(((a>>bit)&1)?oneChild:zeroChild);
+    if (!child) child = new ADecoder();
+    child->map(a, m, r, bit-1);
+  }
+}
+
+Byte *MemoryUnit::ADecoder::getPtr(Addr a, Size sz, Size wordSize) {
+  Size bit = wordSize - 1;
+  MemDevice &m(doLookup(a, bit));
+  a &= (2<<bit)-1;
+  if (a + sz <= m.size()) return m.base() + a;
+  return NULL;
+}
+
+Word MemoryUnit::ADecoder::read(Addr a, bool sup, Size wordSize) {
+  Size bit = wordSize - 1;
+  MemDevice &m(doLookup(a, bit));
+  a &= (2<<bit)-1;
+  // std::cout << std::hex << "ADecoder::read(Addr " << a << ", sup " << sup << ", wordSize " << wordSize << " -> ";
+  // std::cout << "Data: " << m.read(a) << "\n";
+  return m.read(a);
+}
+
+void MemoryUnit::ADecoder::write(Addr a, Word w, bool sup, Size wordSize) {
+  Size bit = wordSize - 1;
+  MemDevice &m(doLookup(a, bit));
+
+  RAM & r = (RAM &) m;
+  // a &= (2<<bit)-1;
+  // std::cout << std::hex << "ADecoder::write(Addr " << a << ", w " << w << ", sup " << sup << ", wordSize " << wordSize << "\n";
+  Word before = m.read(a);
+  Word new_word = w;
+
+  if (a == 0x8000012c)
+  {
+    printf("WRITING TO 0x8000012c -> %d\n", w);
+  }
+
+  if (wordSize == 8)
+  {
+    r.writeByte(a, &w);
+  }
+  else if (wordSize == 16)
+  {
+    r.writeHalf(a, &w);
+  }
+  else
+  {
+    r.writeWord(a, &w);
+  }
+  // m.write(a, new_word);
+}
+
+Byte *MemoryUnit::getPtr(Addr a, Size s) {
+  return ad.getPtr(a, s, addrBytes*8);
+}
+
+void MemoryUnit::attach(MemDevice &m, Addr base) {
+  ad.map(base, m, m.size(), addrBytes*8 - 1);
+}
+
+MemoryUnit::TLBEntry MemoryUnit::tlbLookup(Addr vAddr, Word flagMask) {
+  map<Addr, MemoryUnit::TLBEntry>::iterator i;
+  if ((i = tlb.find(vAddr/pageSize)) != tlb.end()) {
+    TLBEntry &t = i->second;
+    if (t.flags & flagMask) return t;
+    else {
+      D(2, "Page fault on addr 0x" << hex << vAddr << "(bad flags)");
+      throw PageFault(vAddr, false);
+    }
+  } else {
+    D(2, "Page fault on addr 0x" << hex << vAddr << "(not in TLB)");
+    throw PageFault(vAddr, true);
+  }
+}
+
+#ifdef EMU_INSTRUMENTATION
+Addr MemoryUnit::virtToPhys(Addr vAddr) {
+  TLBEntry t = tlbLookup(vAddr, 077);
+  return t.pfn*pageSize + vAddr%pageSize;
+}
+#endif
+
+Word MemoryUnit::read(Addr vAddr, bool sup) {
+  Addr pAddr;
+  if (disableVm) {
+    pAddr = vAddr;
+  } else {
+    Word flagMask = sup?8:1;
+    TLBEntry t = tlbLookup(vAddr, flagMask);
+    pAddr = t.pfn*pageSize + vAddr%pageSize;
+  }
+  // std::cout << "MU::write: About to read: " << std::hex << pAddr << " = " << (ad.read(pAddr, sup, 8*addrBytes)) << " with " << std::dec << (8*addrBytes) << "\n";
+  return ad.read(pAddr, sup, 8*addrBytes);
+}
+
+Word MemoryUnit::fetch(Addr vAddr, bool sup) {
+  Addr pAddr;
+
+  if (disableVm) {
+    pAddr = vAddr;
+  } else {
+    Word flagMask = sup?32:4;
+    TLBEntry t = tlbLookup(vAddr, flagMask);
+    pAddr = t.pfn*pageSize + vAddr%pageSize;
+  }
+
+  Word instruction = ad.read(pAddr, sup, 8*addrBytes);
+
+  return instruction;
+}
+
+void MemoryUnit::write(Addr vAddr, Word w, bool sup, Size bytes) {
+  Addr pAddr;
+
+  if (disableVm) {
+    pAddr = vAddr;
+  } else {
+    Word flagMask = sup?16:2;
+    TLBEntry t = tlbLookup(vAddr, flagMask);
+    pAddr = t.pfn*pageSize + vAddr%pageSize;
+  }
+  // std::cout << "MU::write: About to write: " << std::hex << pAddr << " = " << w << " with " << std::dec << 8*bytes << "\n";
+  ad.write(pAddr, w, sup, 8*bytes);
+  // std::cout << std::hex << "reading same address: " << (this->read(vAddr, sup)) << "\n";
+}
+
+void MemoryUnit::tlbAdd(Addr virt, Addr phys, Word flags) {
+  D(1, "tlbAdd(0x" << hex << virt << ", 0x" << phys << ", 0x" << flags << ')');
+  tlb[virt/pageSize] = TLBEntry(phys/pageSize, flags);
+}
+
+void MemoryUnit::tlbRm(Addr va) {
+  if (tlb.find(va/pageSize) != tlb.end()) tlb.erase(tlb.find(va/pageSize));
+}
+
+void *Harp::consoleInputThread(void* arg_vp) {
+  ConsoleMemDevice *arg = (ConsoleMemDevice *)arg_vp;
+  char c;
+  while (cin) {
+    c = cin.get();
+    pthread_mutex_lock(&arg->cBufLock);
+    arg->cBuf.push(c);
+    pthread_mutex_unlock(&arg->cBufLock);
+  }
+  cout << "Console input ended. Exiting.\n";
+  exit(4);
+}
+
+ConsoleMemDevice::ConsoleMemDevice(Size wS, std::ostream &o, Core &core,
+                                   bool batch) : 
+  wordSize(wS), output(o), core(core), cBuf()
+{
+  // Create a console input thread if we are running in interactive mode.
+  if (!batch) {
+    pthread_t *thread = new pthread_t;
+    pthread_create(thread, NULL, consoleInputThread, (void*)this);
+  }
+  pthread_mutex_init(&cBufLock, NULL);
+}
+
+void ConsoleMemDevice::poll() {
+  pthread_mutex_lock(&cBufLock);
+  if (!cBuf.empty()) core.interrupt(8);
+  pthread_mutex_unlock(&cBufLock);
+}
+
+Word DiskControllerMemDevice::read(Addr a) {
+  switch (a/8) {
+    case 0: return curDisk;
+    case 1: return curBlock;
+    case 2: return disks[curDisk].blocks * blockSize;
+    case 3: return physAddr;
+    case 4: return command;
+    case 5: return status;
+    default:
+      cout << "Attempt to read invalid disk controller register.\n";
+      exit(1);
+  }
+}
+
+void DiskControllerMemDevice::write(Addr a, Word w) {
+  switch (a/8) {
+    case 0: if (w <= disks.size()) {
+              curDisk = w;
+              status = OK;
+            } else {
+              status = INVALID_DISK;
+            }
+            break;
+    case 1: if (w < disks[curDisk].blocks) {
+              curBlock = w;
+            } else {
+              status = INVALID_BLOCK;
+            }
+            break;
+    case 2: nBlocks = w >= disks[curDisk].blocks?disks[curDisk].blocks - 1 : w;
+            status = OK;
+            break;
+    case 3: physAddr = w;
+            status = OK;
+            break;
+    case 4: if (w == 0) {
+            } else {
+            }
+            cout << "TODO: Implement disk read and write!\n";
+            break;
+  }
+}
+
+
+
+

emulator/qsim-harp.cpp

@@ -0,0 +1,57 @@
+/*******************************************************************************
+ HARPtools by Chad D. Kersey, Summer 2011 
+*******************************************************************************/
+#include "include/qsim-harp.h"
+
+#include <iostream>
+#include <string>
+
+using namespace Harp;
+using namespace Qsim;
+using namespace std;
+
+Harp::OSDomain* Harp::OSDomain::osDomain(NULL);
+
+Harp::OSDomain::OSDomain(ArchDef &archref, string imgFile) :
+  /* TODO: Move the mu to the Cpu. They're sharing a TLB now! */
+  arch(archref), mu(4096, arch.getWordSize()), 
+  ram(imgFile.c_str(), arch.getWordSize()),
+  cpus(0)
+{
+  if (osDomain != NULL) {
+    cout << "Error: OSDomain is a singleton.";
+    exit(1);
+  }
+  osDomain = this;
+
+  std::cout << "Constructing an OSDomain with archref, " << archref.getNPRegs() << '\n';
+
+  std::cout << "Pushing back a Cpu in OSDomain constructor.\n";
+  cpus.push_back(Cpu(*this));
+
+  console = new ConsoleMemDevice(arch.getWordSize(), cout, *cpus[0].core);
+
+  mu.attach(ram, 0);
+  mu.attach(*console, 1ll<<(arch.getWordSize()*8 - 1));
+}
+
+void Harp::OSDomain::connect_console(std::ostream &s) {
+  /* For now this does nothing. ConsoleMemDevice is not redirectable. */
+  std::cout << "in connect_console\n";
+}
+
+Harp::OSDomain::Cpu::Cpu(Harp::OSDomain &o) :
+  /* TODO: This should support non-word decoders! */
+  osd(&o), dec(new WordDecoder(osd->arch)),
+  core(new Core(osd->arch, *dec, osd->mu))
+{
+  std::cout << "Constructing a new Cpu.\n";
+}
+
+uint64_t Harp::OSDomain::Cpu::run(uint64_t n) {
+  uint64_t i;
+  std::cout << "pc=0x" << std::hex << core->pc << ", " << std::dec << sizeof(*core) << '\n';
+  //osd->console->poll();
+  for (i = 0; i < n; ++i) core->step();
+  return i;
+}

emulator/results.txt

@@ -0,0 +1 @@
+start

emulator/riscv_tests/C.ADD.elf.hex

@@ -0,0 +1,50 @@
+:0200000480007A
+:1000000001000100010001000100010001000100E8
+:1000100001000100010001000100010001000100D8
+:1000200001000100010001000100010001000100C8
+:1000300001000100010001000100010001000100B8
+:1000400001000100010001000100010001000100A8
+:100050000100010001000100010001000100010098
+:100060000100010001000100010001000100010088
+:100070000100010001000100010001000100010078
+:100080000100010001000100010001000100010068
+:100090000100010001000100010001000100010058
+:1000A0000100010001000100010001000100010048
+:1000B0000100010001000100010001000100010038
+:1000C0000100010001000100010001000100010028
+:1000D0000100010001000100010001000100010018
+:1000E00001000100010001000100010001001711E1
+:1000F0000000130121F10142814192910EC081441F
+:100100000544269422C201469305F0FFB2952EC401
+:100110000147B78600009386F6FFBA9636C60148B7
+:10012000A167C2973EC8171100001301E1EE05490F
+:100130008148CA9846C0054A8549D2994EC2054BA6
+:10014000930AF0FFDA9A56C4054CB78B0000938BE4
+:10015000FBFFE29B5EC6054DA16CEA9C66C81711C9
+:1001600000001301A1EC130EF0FF814DF29D6EC053
+:10017000130FF0FF854EFA9E76C29301F0FF930FA6
+:10018000F0FF8E9F7EC41304F0FF3782000013023D
+:10019000F2FF229212C69305F0FFA164AE9426C826
+:1001A000171100001301C1E9B78600009386F6FF1E
+:1001B0000146369632C0B78700009387F7FF0547A0
+:1001C0003E973AC2B78800009388F8FF1308F0FF03
+:1001D000469842C4B78900009389F9FF3789000027
+:1001E0001309F9FF4E994AC6B78A0000938AFAFFAD
+:1001F000216A569A52C8171100001301A1E5A16B9C
+:10020000014B5E9B5AC0A16C054C669C62C2A16DFD
+:10021000130DF0FF6E9D6AC4A16E378E0000130EA1
+:10022000FEFF769E72C6A16F216F7E9F7AC817155A
+:100230000000130525DD971500009385A5E337061B
+:1002400010F01306C6F2630CB500544514C21445F1
+:1002500014C2544114C2144114C24105EDB737050C
+:1002600010F0130505F22320050000000000000037
+:0202700000008C
+:10100000FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF0
+:10101000FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFE0
+:10102000FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFD0
+:10103000FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFC0
+:10104000FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFB0
+:10105000FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFA0
+:10106000FFFFFFFF00000000000000000000000084
+:040000058000000077
+:00000001FF

emulator/riscv_tests/C.ADDI.elf.hex

@@ -0,0 +1,45 @@
+:0200000480007A
+:1000000001000100010001000100010001000100E8
+:1000100001000100010001000100010001000100D8
+:1000200001000100010001000100010001000100C8
+:1000300001000100010001000100010001000100B8
+:1000400001000100010001000100010001000100A8
+:100050000100010001000100010001000100010098
+:100060000100010001000100010001000100010088
+:100070000100010001000100010001000100010078
+:100080000100010001000100010001000100010068
+:100090000100010001000100010001000100010058
+:1000A0000100010001000100010001000100010048
+:1000B0000100010001000100010001000100010038
+:1000C0000100010001000100010001000100010028
+:1000D0000100010001000100010001000100010018
+:1000E00001000100010001000100010001001711E1
+:1000F0000000130121F1814185010EC00142090276
+:1001000012C201443D0422C48144C10426C6814573
+:10011000FD052EC817110000130101F00546050664
+:1001200032C08546890636C205473D073AC4854731
+:10013000C1073EC605487D0842C8171100001301DB
+:10014000E1EE9308F0FF850846C01309F0FF0909A6
+:100150004AC29309F0FFBD094EC4130AF0FF410AD9
+:1001600052C6930AF0FFFD0A56C81711000013018A
+:1001700021ED370B0800130BFBFF050B5AC0B70B23
+:100180000800938BFBFF890B5EC2370C0800130C31
+:10019000FCFF3D0C62C4B70C0800938CFCFFC10C43
+:1001A00066C6370D0800130DFDFF7D0D6AC81711D7
+:1001B0000000130121EAB70D0800850D6EC0370E4F
+:1001C0000800090E72C2B70E0800BD0E76C4370FC4
+:1001D0000800410F7AC6B70F0800FD0F7EC817153B
+:1001E0000000130525E2971500009385A5E8370662
+:1001F00010F01306C6F2630CB500544514C2144542
+:1002000014C2544114C2144114C24105EDB737055C
+:1002100010F0130505F22320050000000000000087
+:020220000000DC
+:10100000FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF0
+:10101000FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFE0
+:10102000FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFD0
+:10103000FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFC0
+:10104000FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFB0
+:10105000FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFA0
+:10106000FFFFFFFF00000000000000000000000084
+:040000058000000077
+:00000001FF

emulator/riscv_tests/C.ADDI16SP.elf.hex

@@ -0,0 +1,29 @@
+:0200000480007A
+:1000000001000100010001000100010001000100E8
+:1000100001000100010001000100010001000100D8
+:1000200001000100010001000100010001000100C8
+:1000300001000100010001000100010001000100B8
+:1000400001000100010001000100010001000100A8
+:100050000100010001000100010001000100010098
+:100060000100010001000100010001000100010088
+:100070000100010001000100010001000100010078
+:100080000100010001000100010001000100010068
+:100090000100010001000100010001000100010058
+:1000A0000100010001000100010001000100010048
+:1000B0000100010001000100010001000100010038
+:1000C0000100010001000100010001000100010028
+:1000D0000100010001000100010001000100010018
+:1000E0000100010001000100010001000100971062
+:1000F0000000938020F1410123A020009710000010
+:10010000938080F0056123A0200097100000938069
+:10011000E0EF216123A0200097100000938040EFC2
+:100120007D6123A02000971000009380A0EE017154
+:1001300023A02000171500001305C5EC971500003B
+:10014000938545EE370610F01306C6F2630CB50032
+:10015000544514C2144514C2544114C2144114C26B
+:100160004105EDB7370510F0130505F22320050012
+:0201700000008D
+:10100000FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF0
+:10101000FFFFFFFF000000000000000000000000D4
+:040000058000000077
+:00000001FF

emulator/riscv_tests/C.ADDI4SPN.elf.hex

@@ -0,0 +1,29 @@
+:0200000480007A
+:1000000001000100010001000100010001000100E8
+:1000100001000100010001000100010001000100D8
+:1000200001000100010001000100010001000100C8
+:1000300001000100010001000100010001000100B8
+:1000400001000100010001000100010001000100A8
+:100050000100010001000100010001000100010098
+:100060000100010001000100010001000100010088
+:100070000100010001000100010001000100010078
+:100080000100010001000100010001000100010068
+:100090000100010001000100010001000100010058
+:1000A0000100010001000100010001000100010048
+:1000B0000100010001000100010001000100010038
+:1000C0000100010001000100010001000100010028
+:1000D0000100010001000100010001000100010018
+:1000E0000100010001000100010001000100971062
+:1000F0000000938020F1500023A0C0009710000062
+:10010000938080F0340023A0D000971000009380EB
+:10011000E0EF780023A0E00097100000938040EF0C
+:100120001C0823A0F000971000009380A0EEE01FB1
+:1001300023A08000171500001305C5EC97150000DB
+:10014000938545EE370610F01306C6F2630CB50032
+:10015000544514C2144514C2544114C2144114C26B
+:100160004105EDB7370510F0130505F22320050012
+:0201700000008D
+:10100000FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF0
+:10101000FFFFFFFF000000000000000000000000D4
+:040000058000000077
+:00000001FF

emulator/riscv_tests/C.AND.elf.hex

@@ -0,0 +1,50 @@
+:0200000480007A
+:1000000001000100010001000100010001000100E8
+:1000100001000100010001000100010001000100D8
+:1000200001000100010001000100010001000100C8
+:1000300001000100010001000100010001000100B8
+:1000400001000100010001000100010001000100A8
+:100050000100010001000100010001000100010098
+:100060000100010001000100010001000100010088
+:100070000100010001000100010001000100010078
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emulator/riscv_tests/C.ANDI.elf.hex

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emulator/riscv_tests/C.BEQZ.elf.hex

@@ -0,0 +1,33 @@
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emulator/riscv_tests/C.BNEZ.elf.hex

@@ -0,0 +1,30 @@
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emulator/riscv_tests/C.J.elf.hex

@@ -0,0 +1,32 @@
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emulator/riscv_tests/C.JAL.elf.hex

@@ -0,0 +1,32 @@
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emulator/riscv_tests/C.JALR.elf.hex

@@ -0,0 +1,35 @@
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emulator/riscv_tests/C.JR.elf.hex

@@ -0,0 +1,35 @@
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emulator/riscv_tests/C.LI.elf.hex

@@ -0,0 +1,45 @@
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emulator/riscv_tests/C.LUI.elf.hex

@@ -0,0 +1,45 @@
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emulator/riscv_tests/C.LW.elf.hex

@@ -0,0 +1,39 @@
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emulator/riscv_tests/C.LWSP.elf.hex

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emulator/riscv_tests/C.MV.elf.hex

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emulator/riscv_tests/C.OR.elf.hex

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emulator/riscv_tests/C.SLLI.elf.hex

@@ -0,0 +1,45 @@
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emulator/riscv_tests/C.SRAI.elf.hex

@@ -0,0 +1,45 @@
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emulator/riscv_tests/C.SRLI.elf.hex

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emulator/riscv_tests/C.SUB.elf.hex

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emulator/riscv_tests/C.SW.elf.hex

@@ -0,0 +1,41 @@
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emulator/riscv_tests/C.SWSP.elf.hex

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emulator/riscv_tests/C.XOR.elf.hex

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emulator/riscv_tests/DIV.elf.hex

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emulator/riscv_tests/DIVU.elf.hex

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emulator/riscv_tests/I-ADD-01.elf.hex

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emulator/riscv_tests/I-ADDI-01.elf.hex

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emulator/riscv_tests/I-AND-01.elf.hex

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emulator/riscv_tests/I-ANDI-01.elf.hex

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emulator/riscv_tests/I-AUIPC-01.elf.hex

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emulator/riscv_tests/I-BEQ-01.elf.hex

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emulator/riscv_tests/I-BGE-01.elf.hex

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emulator/riscv_tests/I-BGEU-01.elf.hex

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emulator/riscv_tests/I-BLT-01.elf.hex

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emulator/riscv_tests/I-BLTU-01.elf.hex

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emulator/riscv_tests/I-BNE-01.elf.hex

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emulator/riscv_tests/I-CSRRC-01.elf.hex

@@ -0,0 +1,39 @@
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emulator/riscv_tests/I-CSRRCI-01.elf.hex

@@ -0,0 +1,25 @@
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emulator/riscv_tests/I-CSRRS-01.elf.hex

@@ -0,0 +1,38 @@
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emulator/riscv_tests/I-CSRRSI-01.elf.hex

@@ -0,0 +1,24 @@
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emulator/riscv_tests/I-CSRRW-01.elf.hex

@@ -0,0 +1,30 @@
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emulator/riscv_tests/I-CSRRWI-01.elf.hex

@@ -0,0 +1,16 @@
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emulator/riscv_tests/I-DELAY_SLOTS-01.elf.hex

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emulator/riscv_tests/I-EBREAK-01.elf.hex

@@ -0,0 +1,15 @@
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emulator/riscv_tests/I-ECALL-01.elf.hex

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emulator/riscv_tests/I-ENDIANESS-01.elf.hex

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emulator/riscv_tests/I-FENCE.I-01.elf.hex

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emulator/riscv_tests/I-IO.elf.hex

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emulator/riscv_tests/I-JAL-01.elf.hex

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emulator/riscv_tests/I-JALR-01.elf.hex

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emulator/riscv_tests/I-LB-01.elf.hex

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emulator/riscv_tests/I-LBU-01.elf.hex

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emulator/riscv_tests/I-LH-01.elf.hex

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emulator/riscv_tests/I-LHU-01.elf.hex

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emulator/riscv_tests/I-LUI-01.elf.hex

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emulator/riscv_tests/I-LW-01.elf.hex

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emulator/riscv_tests/I-MISALIGN_JMP-01.elf.hex

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emulator/riscv_tests/I-MISALIGN_LDST-01.elf.hex

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emulator/riscv_tests/I-NOP-01.elf.hex

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emulator/riscv_tests/I-OR-01.elf.hex

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emulator/riscv_tests/I-ORI-01.elf.hex

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emulator/riscv_tests/I-RF_size-01.elf.hex

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emulator/riscv_tests/I-RF_width-01.elf.hex

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emulator/riscv_tests/I-RF_x0-01.elf.hex

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emulator/riscv_tests/I-SB-01.elf.hex

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emulator/riscv_tests/I-SH-01.elf.hex

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emulator/riscv_tests/I-SLL-01.elf.hex

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emulator/riscv_tests/I-SLLI-01.elf.hex

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