diff --git a/rtl/VX_cache/VX_bank.v b/rtl/VX_cache/VX_bank.v index d2b24462..281f0ee8 100644 --- a/rtl/VX_cache/VX_bank.v +++ b/rtl/VX_cache/VX_bank.v @@ -14,6 +14,8 @@ module VX_bank parameter NUMBER_REQUESTS = 2, // Number of cycles to complete stage 1 (read from memory) parameter STAGE_1_CYCLES = 2, + // Function ID, {Dcache=0, Icache=1, Sharedmemory=2} + parameter FUNC_ID = 0, // Queues feeding into banks Knobs {1, 2, 4, 8, ...} @@ -438,6 +440,7 @@ module VX_bank .WORD_SIZE_BYTES (WORD_SIZE_BYTES), .NUMBER_REQUESTS (NUMBER_REQUESTS), .STAGE_1_CYCLES (STAGE_1_CYCLES), + .FUNC_ID (FUNC_ID), .REQQ_SIZE (REQQ_SIZE), .MRVQ_SIZE (MRVQ_SIZE), .DFPQ_SIZE (DFPQ_SIZE), diff --git a/rtl/VX_cache/VX_cache.v b/rtl/VX_cache/VX_cache.v index 855b0905..b9ef9373 100644 --- a/rtl/VX_cache/VX_cache.v +++ b/rtl/VX_cache/VX_cache.v @@ -14,6 +14,8 @@ module VX_cache parameter NUMBER_REQUESTS = 2, // Number of cycles to complete stage 1 (read from memory) parameter STAGE_1_CYCLES = 2, + // Function ID, {Dcache=0, Icache=1, Sharedmemory=2} + parameter FUNC_ID = 0, // Queues feeding into banks Knobs {1, 2, 4, 8, ...} @@ -384,6 +386,7 @@ module VX_cache .WORD_SIZE_BYTES (WORD_SIZE_BYTES), .NUMBER_REQUESTS (NUMBER_REQUESTS), .STAGE_1_CYCLES (STAGE_1_CYCLES), + .FUNC_ID (FUNC_ID), .REQQ_SIZE (REQQ_SIZE), .MRVQ_SIZE (MRVQ_SIZE), .DFPQ_SIZE (DFPQ_SIZE), diff --git a/rtl/VX_cache/VX_tag_data_access.v b/rtl/VX_cache/VX_tag_data_access.v index 71710636..d717e02c 100644 --- a/rtl/VX_cache/VX_tag_data_access.v +++ b/rtl/VX_cache/VX_tag_data_access.v @@ -14,6 +14,8 @@ module VX_tag_data_access parameter NUMBER_REQUESTS = 2, // Number of cycles to complete stage 1 (read from memory) parameter STAGE_1_CYCLES = 2, + // Function ID, {Dcache=0, Icache=1, Sharedmemory=2} + parameter FUNC_ID = 0, // Queues feeding into banks Knobs {1, 2, 4, 8, ...} @@ -101,6 +103,7 @@ module VX_tag_data_access .WORD_SIZE_BYTES (WORD_SIZE_BYTES), .NUMBER_REQUESTS (NUMBER_REQUESTS), .STAGE_1_CYCLES (STAGE_1_CYCLES), + .FUNC_ID (FUNC_ID), .REQQ_SIZE (REQQ_SIZE), .MRVQ_SIZE (MRVQ_SIZE), .DFPQ_SIZE (DFPQ_SIZE), @@ -155,9 +158,9 @@ module VX_tag_data_access endgenerate - assign use_read_valid_st1e = read_valid_st1c[STAGE_1_CYCLES-2]; - assign use_read_dirty_st1e = read_dirty_st1c[STAGE_1_CYCLES-2]; - assign use_read_tag_st1e = read_tag_st1c [STAGE_1_CYCLES-2]; + assign use_read_valid_st1e = read_valid_st1c[STAGE_1_CYCLES-2] || (FUNC_ID == `SFUNC_ID); // If shared memory, always valid + assign use_read_dirty_st1e = read_dirty_st1c[STAGE_1_CYCLES-2] && (FUNC_ID == `DFUNC_ID); // Dirty only applies in Dcache + assign use_read_tag_st1e = (FUNC_ID == `SFUNC_ID) ? writeaddr_st1e[`TAG_SELECT_ADDR_RNG] : read_tag_st1c [STAGE_1_CYCLES-2]; // Tag is always the same in SM genvar curr_w; for (curr_w = 0; curr_w < `BANK_LINE_SIZE_WORDS; curr_w = curr_w+1) assign use_read_data_st1e[curr_w][31:0] = read_data_st1c[STAGE_1_CYCLES-2][curr_w][31:0]; diff --git a/rtl/VX_cache/VX_tag_data_structure.v b/rtl/VX_cache/VX_tag_data_structure.v index d869f35e..de8544c5 100644 --- a/rtl/VX_cache/VX_tag_data_structure.v +++ b/rtl/VX_cache/VX_tag_data_structure.v @@ -14,7 +14,9 @@ module VX_tag_data_structure parameter NUMBER_REQUESTS = 2, // Number of cycles to complete stage 1 (read from memory) parameter STAGE_1_CYCLES = 2, - + // Function ID, {Dcache=0, Icache=1, Sharedmemory=2} + parameter FUNC_ID = 0, + // Queues feeding into banks Knobs {1, 2, 4, 8, ...} // Core Request Queue Size diff --git a/rtl/VX_define.v b/rtl/VX_define.v index f9b9d9f5..ad2c1a96 100644 --- a/rtl/VX_define.v +++ b/rtl/VX_define.v @@ -228,6 +228,8 @@ `define DNUMBER_REQUESTS `NT // Number of cycles to complete stage 1 (read from memory) `define DSTAGE_1_CYCLES 2 + // Function ID + `define DFUNC_ID 0 // Bank Number of words in a line `define DBANK_LINE_SIZE_WORDS (`DBANK_LINE_SIZE_BYTES / `DWORD_SIZE_BYTES) @@ -277,6 +279,8 @@ `define INUMBER_REQUESTS 1 // Number of cycles to complete stage 1 (read from memory) `define ISTAGE_1_CYCLES 2 + // Function ID + `define IFUNC_ID 1 // Bank Number of words in a line `define IBANK_LINE_SIZE_WORDS (`IBANK_LINE_SIZE_BYTES / `IWORD_SIZE_BYTES) @@ -286,7 +290,7 @@ // Core Request Queue Size `define IREQQ_SIZE `NW // Miss Reserv Queue Knob - `define IMRVQ_SIZE `DREQQ_SIZE + `define IMRVQ_SIZE `IREQQ_SIZE // Dram Fill Rsp Queue Size `define IDFPQ_SIZE 2 // Snoop Req Queue @@ -294,11 +298,11 @@ // Queues for writebacks Knobs {1, 2, 4, 8, ...} // Core Writeback Queue Size - `define ICWBQ_SIZE `DREQQ_SIZE + `define ICWBQ_SIZE `IREQQ_SIZE // Dram Writeback Queue Size - `define IDWBQ_SIZE 4 + `define IDWBQ_SIZE 0 // Dram Fill Req Queue Size - `define IDFQQ_SIZE `DREQQ_SIZE + `define IDFQQ_SIZE `IREQQ_SIZE // Lower Level Cache Hit Queue Size `define ILLVQ_SIZE 0 @@ -310,7 +314,55 @@ // ========================================= Icache Configurable Knobs ========================================= +// ========================================= Icache Configurable Knobs ========================================= +// General Cache Knobs + // Size of cache in bytes + `define SCACHE_SIZE_BYTES 1024 + // Size of line inside a bank in bytes + `define SBANK_LINE_SIZE_BYTES 16 + // Number of banks {1, 2, 4, 8,...} + `define SNUMBER_BANKS 8 + // Size of a word in bytes + `define SWORD_SIZE_BYTES 4 + // Number of Word requests per cycle {1, 2, 4, 8, ...} + `define SNUMBER_REQUESTS 1 + // Number of cycles to complete stage 1 (read from memory) + `define SSTAGE_1_CYCLES 2 + // Function ID + `define SFUNC_ID 2 + + // Bank Number of words in a line + `define SBANK_LINE_SIZE_WORDS (`SBANK_LINE_SIZE_BYTES / `SWORD_SIZE_BYTES) + `define SBANK_LINE_SIZE_RNG `SBANK_LINE_SIZE_WORDS-1:0 +// Queues feeding into banks Knobs {1, 2, 4, 8, ...} + + // Core Request Queue Size + `define SREQQ_SIZE `NW + // Miss Reserv Queue Knob + `define SMRVQ_SIZE `SREQQ_SIZE + // Dram Fill Rsp Queue Size + `define SDFPQ_SIZE 0 + // Snoop Req Queue + `define SSNRQ_SIZE 0 + +// Queues for writebacks Knobs {1, 2, 4, 8, ...} + // Core Writeback Queue Size + `define SCWBQ_SIZE `SREQQ_SIZE + // Dram Writeback Queue Size + `define SDWBQ_SIZE 0 + // Dram Fill Req Queue Size + `define SDFQQ_SIZE 0 + // Lower Level Cache Hit Queue Size + `define SLLVQ_SIZE 0 + + // Fill Invalidator Size {Fill invalidator must be active} + `define SFILL_INVALIDAOR_SIZE 16 + +// Dram knobs + `define SSIMULATED_DRAM_LATENCY_CYCLES 10 + +// ========================================= Icache Configurable Knobs ========================================= `endif diff --git a/rtl/VX_dmem_controller.v b/rtl/VX_dmem_controller.v index 00a6aa37..29ba47dd 100644 --- a/rtl/VX_dmem_controller.v +++ b/rtl/VX_dmem_controller.v @@ -21,49 +21,148 @@ module VX_dmem_controller ( VX_gpu_dcache_req_inter VX_icache_req ); - wire to_shm = VX_dcache_req.core_req_addr[0][31:24] == 8'hFF; - wire[`NT_M1:0] cache_driver_in_valid = VX_dcache_req.core_req_valid & {`NT{~to_shm}}; - - // wire[`NT_M1:0] sm_driver_in_valid = VX_dcache_req.core_req_valid & {`NT{to_shm}}; - // wire[2:0] sm_driver_in_mem_read = !(|sm_driver_in_valid) ? `NO_MEM_READ : VX_dcache_req.core_req_mem_read; - // wire[2:0] sm_driver_in_mem_write = !(|sm_driver_in_valid) ? `NO_MEM_WRITE : VX_dcache_req.core_req_mem_write; - - // wire[`NT_M1:0][31:0] cache_driver_out_data; - // wire[`NT_M1:0][31:0] sm_driver_out_data; - // wire[`NT_M1:0] cache_driver_out_valid; // Not used for now - // wire sm_delay; + VX_gpu_dcache_res_inter VX_dcache_rsp_smem(); + VX_gpu_dcache_req_inter VX_dcache_req_smem(); - // VX_shared_memory #( - // .SM_SIZE (`SHARED_MEMORY_SIZE), - // .SM_BANKS (`SHARED_MEMORY_BANKS), - // .SM_BYTES_PER_READ (`SHARED_MEMORY_BYTES_PER_READ), - // .SM_WORDS_PER_READ (`SHARED_MEMORY_WORDS_PER_READ), - // .SM_LOG_WORDS_PER_READ (`SHARED_MEMORY_LOG_WORDS_PER_READ), - // .SM_BANK_OFFSET_START (`SHARED_MEMORY_BANK_OFFSET_ST), - // .SM_BANK_OFFSET_END (`SHARED_MEMORY_BANK_OFFSET_ED), - // .SM_BLOCK_OFFSET_START (`SHARED_MEMORY_BLOCK_OFFSET_ST), - // .SM_BLOCK_OFFSET_END (`SHARED_MEMORY_BLOCK_OFFSET_ED), - // .SM_INDEX_START (`SHARED_MEMORY_INDEX_OFFSET_ST), - // .SM_INDEX_END (`SHARED_MEMORY_INDEX_OFFSET_ED), - // .SM_HEIGHT (`SHARED_MEMORY_HEIGHT), - // .NUM_REQ (`SHARED_MEMORY_NUM_REQ), - // .BITS_PER_BANK (`SHARED_MEMORY_BITS_PER_BANK) - // ) - // shared_memory - // ( - // .clk (clk), - // .reset (reset), - // .in_valid (sm_driver_in_valid), - // .in_address(VX_dcache_req.core_req_addr), - // .in_data (VX_dcache_req.core_req_writedata), - // .mem_read (sm_driver_in_mem_read), - // .mem_write (sm_driver_in_mem_write), - // .out_valid (cache_driver_out_valid), - // .out_data (sm_driver_out_data), - // .stall (sm_delay) - // ); + VX_gpu_dcache_res_inter VX_dcache_rsp_dcache(); + VX_gpu_dcache_req_inter VX_dcache_req_dcache(); + + + wire to_shm = VX_dcache_req.core_req_addr[0][31:24] == 8'hFF; + wire dcache_wants_wb = (|VX_dcache_rsp_dcache.core_wb_valid); + + // Dcache Request + assign VX_dcache_req_dcache.core_req_valid = VX_dcache_req.core_req_valid & {`NT{~to_shm}}; + assign VX_dcache_req_dcache.core_req_addr = VX_dcache_req.core_req_addr; + assign VX_dcache_req_dcache.core_req_writedata = VX_dcache_req.core_req_writedata; + assign VX_dcache_req_dcache.core_req_mem_read = VX_dcache_req.core_req_mem_read; + assign VX_dcache_req_dcache.core_req_mem_write = VX_dcache_req.core_req_mem_write; + assign VX_dcache_req_dcache.core_req_rd = VX_dcache_req.core_req_rd; + assign VX_dcache_req_dcache.core_req_wb = VX_dcache_req.core_req_wb; + assign VX_dcache_req_dcache.core_req_warp_num = VX_dcache_req.core_req_warp_num; + assign VX_dcache_req_dcache.core_req_pc = VX_dcache_req.core_req_pc; + assign VX_dcache_req_dcache.core_no_wb_slot = VX_dcache_req.core_no_wb_slot; + + + // Shred Memory Request + assign VX_dcache_req_smem.core_req_valid = VX_dcache_req.core_req_valid & {`NT{to_shm}}; + assign VX_dcache_req_smem.core_req_addr = VX_dcache_req.core_req_addr; + assign VX_dcache_req_smem.core_req_writedata = VX_dcache_req.core_req_writedata; + assign VX_dcache_req_smem.core_req_mem_read = VX_dcache_req.core_req_mem_read; + assign VX_dcache_req_smem.core_req_mem_write = VX_dcache_req.core_req_mem_write; + assign VX_dcache_req_smem.core_req_rd = VX_dcache_req.core_req_rd; + assign VX_dcache_req_smem.core_req_wb = VX_dcache_req.core_req_wb; + assign VX_dcache_req_smem.core_req_warp_num = VX_dcache_req.core_req_warp_num; + assign VX_dcache_req_smem.core_req_pc = VX_dcache_req.core_req_pc; + assign VX_dcache_req_smem.core_no_wb_slot = VX_dcache_req.core_no_wb_slot || dcache_wants_wb; + + + // Dcache Response + assign VX_dcache_rsp.core_wb_valid = dcache_wants_wb ? VX_dcache_rsp_dcache.core_wb_valid : VX_dcache_rsp_smem.core_wb_valid; + assign VX_dcache_rsp.core_wb_req_rd = dcache_wants_wb ? VX_dcache_rsp_dcache.core_wb_req_rd : VX_dcache_rsp_smem.core_wb_req_rd; + assign VX_dcache_rsp.core_wb_req_wb = dcache_wants_wb ? VX_dcache_rsp_dcache.core_wb_req_wb : VX_dcache_rsp_smem.core_wb_req_wb; + assign VX_dcache_rsp.core_wb_warp_num = dcache_wants_wb ? VX_dcache_rsp_dcache.core_wb_warp_num : VX_dcache_rsp_smem.core_wb_warp_num; + assign VX_dcache_rsp.core_wb_readdata = dcache_wants_wb ? VX_dcache_rsp_dcache.core_wb_readdata : VX_dcache_rsp_smem.core_wb_readdata; + assign VX_dcache_rsp.core_wb_pc = dcache_wants_wb ? VX_dcache_rsp_dcache.core_wb_pc : VX_dcache_rsp_smem.core_wb_pc; + + assign VX_dcache_rsp.delay_req = to_shm ? VX_dcache_rsp_smem.delay_req : VX_dcache_rsp_dcache.delay_req; + + + + + + wire Sllvq_pop; + wire[`DNUMBER_REQUESTS-1:0] Sllvq_valid; + wire[`DNUMBER_REQUESTS-1:0][31:0] Sllvq_res_addr; + wire[`DNUMBER_REQUESTS-1:0][`DBANK_LINE_SIZE_RNG][31:0] Sllvq_res_data; + + VX_gpu_dcache_dram_req_inter VX_gpu_smem_dram_req(); + VX_gpu_dcache_dram_res_inter VX_gpu_smem_dram_res(); + + + + assign Sllvq_pop = 0; + VX_cache #( + .CACHE_SIZE_BYTES (`SCACHE_SIZE_BYTES), + .BANK_LINE_SIZE_BYTES (`SBANK_LINE_SIZE_BYTES), + .NUMBER_BANKS (`SNUMBER_BANKS), + .WORD_SIZE_BYTES (`SWORD_SIZE_BYTES), + .NUMBER_REQUESTS (`SNUMBER_REQUESTS), + .STAGE_1_CYCLES (`SSTAGE_1_CYCLES), + .FUNC_ID (`SFUNC_ID), + .REQQ_SIZE (`SREQQ_SIZE), + .MRVQ_SIZE (`SMRVQ_SIZE), + .DFPQ_SIZE (`SDFPQ_SIZE), + .SNRQ_SIZE (`SSNRQ_SIZE), + .CWBQ_SIZE (`SCWBQ_SIZE), + .DWBQ_SIZE (`SDWBQ_SIZE), + .DFQQ_SIZE (`SDFQQ_SIZE), + .LLVQ_SIZE (`SLLVQ_SIZE), + .FILL_INVALIDAOR_SIZE (`SFILL_INVALIDAOR_SIZE), + .SIMULATED_DRAM_LATENCY_CYCLES(`SSIMULATED_DRAM_LATENCY_CYCLES) + ) + gpu_smem + ( + .clk (clk), + .reset (reset), + + // Core req + .core_req_valid (VX_dcache_req_smem.core_req_valid), + .core_req_addr (VX_dcache_req_smem.core_req_addr), + .core_req_writedata(VX_dcache_req_smem.core_req_writedata), + .core_req_mem_read (VX_dcache_req_smem.core_req_mem_read), + .core_req_mem_write(VX_dcache_req_smem.core_req_mem_write), + .core_req_rd (VX_dcache_req_smem.core_req_rd), + .core_req_wb (VX_dcache_req_smem.core_req_wb), + .core_req_warp_num (VX_dcache_req_smem.core_req_warp_num), + .core_req_pc (VX_dcache_req_smem.core_req_pc), + + // Delay Core Req + .delay_req (VX_dcache_rsp_smem.delay_req), + + // Core Cache Can't WB + .core_no_wb_slot (VX_dcache_req_smem.core_no_wb_slot), + + // Cache CWB + .core_wb_valid (VX_dcache_rsp_smem.core_wb_valid), + .core_wb_req_rd (VX_dcache_rsp_smem.core_wb_req_rd), + .core_wb_req_wb (VX_dcache_rsp_smem.core_wb_req_wb), + .core_wb_warp_num (VX_dcache_rsp_smem.core_wb_warp_num), + .core_wb_readdata (VX_dcache_rsp_smem.core_wb_readdata), + .core_wb_pc (VX_dcache_rsp_smem.core_wb_pc), + + // DRAM response + .dram_fill_rsp (VX_gpu_smem_dram_res.dram_fill_rsp), + .dram_fill_rsp_addr(VX_gpu_smem_dram_res.dram_fill_rsp_addr), + .dram_fill_rsp_data(VX_gpu_smem_dram_res.dram_fill_rsp_data), + + // DRAM accept response + .dram_fill_accept (VX_gpu_smem_dram_req.dram_fill_accept), + + // DRAM Req + .dram_req (VX_gpu_smem_dram_req.dram_req), + .dram_req_write (VX_gpu_smem_dram_req.dram_req_write), + .dram_req_read (VX_gpu_smem_dram_req.dram_req_read), + .dram_req_addr (VX_gpu_smem_dram_req.dram_req_addr), + .dram_req_size (VX_gpu_smem_dram_req.dram_req_size), + .dram_req_data (VX_gpu_smem_dram_req.dram_req_data), + + // Snoop Response + .dram_req_because_of_wb(VX_gpu_smem_dram_req.dram_because_of_snp), + .dram_snp_full (VX_gpu_smem_dram_req.dram_snp_full), + + // Snoop Request + .snp_req (0), + .snp_req_addr (0), + + // LLVQ stuff + .llvq_pop (Sllvq_pop), + .llvq_valid (Sllvq_valid), + .llvq_res_addr (Sllvq_res_addr), + .llvq_res_data (Sllvq_res_data) + ); wire Dllvq_pop; @@ -71,6 +170,7 @@ module VX_dmem_controller ( wire[`DNUMBER_REQUESTS-1:0][31:0] Dllvq_res_addr; wire[`DNUMBER_REQUESTS-1:0][`DBANK_LINE_SIZE_RNG][31:0] Dllvq_res_data; + assign Dllvq_pop = 0; VX_cache #( .CACHE_SIZE_BYTES (`DCACHE_SIZE_BYTES), @@ -79,6 +179,7 @@ module VX_dmem_controller ( .WORD_SIZE_BYTES (`DWORD_SIZE_BYTES), .NUMBER_REQUESTS (`DNUMBER_REQUESTS), .STAGE_1_CYCLES (`DSTAGE_1_CYCLES), + .FUNC_ID (`DFUNC_ID), .REQQ_SIZE (`DREQQ_SIZE), .MRVQ_SIZE (`DMRVQ_SIZE), .DFPQ_SIZE (`DDFPQ_SIZE), @@ -96,29 +197,29 @@ module VX_dmem_controller ( .reset (reset), // Core req - .core_req_valid (cache_driver_in_valid), - .core_req_addr (VX_dcache_req.core_req_addr), - .core_req_writedata(VX_dcache_req.core_req_writedata), - .core_req_mem_read (VX_dcache_req.core_req_mem_read), - .core_req_mem_write(VX_dcache_req.core_req_mem_write), - .core_req_rd (VX_dcache_req.core_req_rd), - .core_req_wb (VX_dcache_req.core_req_wb), - .core_req_warp_num (VX_dcache_req.core_req_warp_num), - .core_req_pc (VX_dcache_req.core_req_pc), + .core_req_valid (VX_dcache_req_dcache.core_req_valid), + .core_req_addr (VX_dcache_req_dcache.core_req_addr), + .core_req_writedata(VX_dcache_req_dcache.core_req_writedata), + .core_req_mem_read (VX_dcache_req_dcache.core_req_mem_read), + .core_req_mem_write(VX_dcache_req_dcache.core_req_mem_write), + .core_req_rd (VX_dcache_req_dcache.core_req_rd), + .core_req_wb (VX_dcache_req_dcache.core_req_wb), + .core_req_warp_num (VX_dcache_req_dcache.core_req_warp_num), + .core_req_pc (VX_dcache_req_dcache.core_req_pc), // Delay Core Req - .delay_req (VX_dcache_rsp.delay_req), + .delay_req (VX_dcache_rsp_dcache.delay_req), // Core Cache Can't WB - .core_no_wb_slot (VX_dcache_req.core_no_wb_slot), + .core_no_wb_slot (VX_dcache_req_dcache.core_no_wb_slot), // Cache CWB - .core_wb_valid (VX_dcache_rsp.core_wb_valid), - .core_wb_req_rd (VX_dcache_rsp.core_wb_req_rd), - .core_wb_req_wb (VX_dcache_rsp.core_wb_req_wb), - .core_wb_warp_num (VX_dcache_rsp.core_wb_warp_num), - .core_wb_readdata (VX_dcache_rsp.core_wb_readdata), - .core_wb_pc (VX_dcache_rsp.core_wb_pc), + .core_wb_valid (VX_dcache_rsp_dcache.core_wb_valid), + .core_wb_req_rd (VX_dcache_rsp_dcache.core_wb_req_rd), + .core_wb_req_wb (VX_dcache_rsp_dcache.core_wb_req_wb), + .core_wb_warp_num (VX_dcache_rsp_dcache.core_wb_warp_num), + .core_wb_readdata (VX_dcache_rsp_dcache.core_wb_readdata), + .core_wb_pc (VX_dcache_rsp_dcache.core_wb_pc), // DRAM response .dram_fill_rsp (VX_gpu_dcache_dram_res.dram_fill_rsp), @@ -153,6 +254,11 @@ module VX_dmem_controller ( + wire Illvq_pop; + wire[`DNUMBER_REQUESTS-1:0] Illvq_valid; + wire[`DNUMBER_REQUESTS-1:0][31:0] Illvq_res_addr; + wire[`DNUMBER_REQUESTS-1:0][`DBANK_LINE_SIZE_RNG][31:0] Illvq_res_data; + assign Illvq_pop = 0; VX_cache #( .CACHE_SIZE_BYTES (`ICACHE_SIZE_BYTES), .BANK_LINE_SIZE_BYTES (`IBANK_LINE_SIZE_BYTES), @@ -160,6 +266,7 @@ module VX_dmem_controller ( .WORD_SIZE_BYTES (`IWORD_SIZE_BYTES), .NUMBER_REQUESTS (`INUMBER_REQUESTS), .STAGE_1_CYCLES (`ISTAGE_1_CYCLES), + .FUNC_ID (`IFUNC_ID), .REQQ_SIZE (`IREQQ_SIZE), .MRVQ_SIZE (`IMRVQ_SIZE), .DFPQ_SIZE (`IDFPQ_SIZE), @@ -226,10 +333,10 @@ module VX_dmem_controller ( .snp_req_addr (0), // LLVQ stuff - .llvq_pop (Dllvq_pop), - .llvq_valid (Dllvq_valid), - .llvq_res_addr (Dllvq_res_addr), - .llvq_res_data (Dllvq_res_data) + .llvq_pop (Illvq_pop), + .llvq_valid (Illvq_valid), + .llvq_res_addr (Illvq_res_addr), + .llvq_res_data (Illvq_res_data) );