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pipeline refactoring - fmax >= 222 mhz

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This commit is contained in:
Blaise Tine
2020-08-14 21:50:14 -07:00
parent 71a46d04b9
commit 6c12391338
107 changed files with 1392 additions and 1239 deletions
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37
hw/unit_tests/VX_divide_tb.v
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@@ -17,26 +17,23 @@ module VX_tb_divide();
wire [31:0] o_div[0:7], o_rem[0:7];
genvar i;
generate
for (i = 0; i < 8; i++) begin
VX_divide#(
.WIDTHN(32),
.WIDTHD(32),
.WIDTHQ(32),
.WIDTHR(32),
.PIPELINE(i)
) div(
.clock(clk),
.aclr(rst),
.clken(1'b1),
.numer(numer),
.denom(denom),
.quotient(o_div[i]),
.remainder(o_rem[i])
);
end
endgenerate
for (genvar i = 0; i < 8; i++) begin
VX_divide#(
.WIDTHN(32),
.WIDTHD(32),
.WIDTHQ(32),
.WIDTHR(32),
.PIPELINE(i)
) div(
.clock(clk),
.aclr(rst),
.clken(1'b1),
.numer(numer),
.denom(denom),
.quotient(o_div[i]),
.remainder(o_rem[i])
);
end
initial begin
clk = 0; rst = 0;