pipeline refactoring - fmax >= 222 mhz

2020-08-14 21:50:14 -07:00
parent 71a46d04b9
commit 6c12391338
107 changed files with 1392 additions and 1239 deletions
--- a/hw/rtl/libs/VX_shift_register.v
+++ b/hw/rtl/libs/VX_shift_register.v
@@ -16,7 +16,7 @@ module VX_shift_register #(

        always @(posedge clk) begin
            if (reset) begin
-                entries <= '0;
+                entries <= (DEPTH * DATAW)'(0);
            end else begin
                if (enable) begin                    
                    entries <= in;
@@ -28,7 +28,7 @@ module VX_shift_register #(
        
        always @(posedge clk) begin
            if (reset) begin
-                entries <= '0;
+                entries <= (DEPTH * DATAW)'(0);
            end else begin
                if (enable) begin                    
                    entries <= {entries[DEPTH-2:0], in};