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pipeline refactoring - fmax >= 222 mhz

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This commit is contained in:
Blaise Tine
2020-08-14 21:50:14 -07:00
parent 71a46d04b9
commit 6c12391338
107 changed files with 1392 additions and 1239 deletions
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4
hw/rtl/fp_cores/altera/VX_fp_add.v
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@@ -22,9 +22,7 @@ module VX_fp_add (
wire enable = ~stall;
assign ready_in = enable;
genvar i;
for (i = 0; i < `NUM_THREADS; i++) begin
for (genvar i = 0; i < `NUM_THREADS; i++) begin
twentynm_fp_mac mac_fp_wys (
// inputs
.accumulate(),

4
hw/rtl/fp_cores/altera/VX_fp_div.v
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@@ -22,9 +22,7 @@ module VX_fp_div (
wire enable = ~stall;
assign ready_in = enable;
genvar i;
for (i = 0; i < `NUM_THREADS; i++) begin
for (genvar i = 0; i < `NUM_THREADS; i++) begin
acl_fp_div fdiv (
.clk (clk),
.areset (1'b0),

4
hw/rtl/fp_cores/altera/VX_fp_ftoi.v
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@@ -21,9 +21,7 @@ module VX_fp_ftoi (
wire enable = ~stall;
assign ready_in = enable;
genvar i;
for (i = 0; i < `NUM_THREADS; i++) begin
for (genvar i = 0; i < `NUM_THREADS; i++) begin
acl_fp_ftoi ftoi (
.clk (clk),
.areset (1'b0),

4
hw/rtl/fp_cores/altera/VX_fp_ftou.v
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@@ -21,9 +21,7 @@ module VX_fp_ftou (
wire enable = ~stall;
assign ready_in = enable;
genvar i;
for (i = 0; i < `NUM_THREADS; i++) begin
for (genvar i = 0; i < `NUM_THREADS; i++) begin
acl_fp_ftou ftou (
.clk (clk),
.areset (1'b0),

4
hw/rtl/fp_cores/altera/VX_fp_itof.v
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@@ -21,9 +21,7 @@ module VX_fp_itof (
wire enable = ~stall;
assign ready_in = enable;
genvar i;
for (i = 0; i < `NUM_THREADS; i++) begin
for (genvar i = 0; i < `NUM_THREADS; i++) begin
acl_fp_itof itof (
.clk (clk),
.areset (1'b0),

4
hw/rtl/fp_cores/altera/VX_fp_madd.v
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@@ -28,9 +28,7 @@ module VX_fp_madd (
wire [`ISTAG_BITS-1:0] out_tag_st0, out_tag_st1;
wire in_valid_st0, out_valid_st0, out_valid_st1;
genvar i;
for (i = 0; i < `NUM_THREADS; i++) begin
for (genvar i = 0; i < `NUM_THREADS; i++) begin
twentynm_fp_mac mac_fp_wys0 (
// inputs
.accumulate(),

4
hw/rtl/fp_cores/altera/VX_fp_msub.v
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@@ -28,9 +28,7 @@ module VX_fp_msub (
wire [`ISTAG_BITS-1:0] out_tag_st0, out_tag_st1;
wire in_valid_st0, out_valid_st0, out_valid_st1;
genvar i;
for (i = 0; i < `NUM_THREADS; i++) begin
for (genvar i = 0; i < `NUM_THREADS; i++) begin
twentynm_fp_mac mac_fp_wys0 (
// inputs
.accumulate(),

4
hw/rtl/fp_cores/altera/VX_fp_mul.v
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@@ -22,9 +22,7 @@ module VX_fp_mul (
wire enable = ~stall;
assign ready_in = enable;
genvar i;
for (i = 0; i < `NUM_THREADS; i++) begin
for (genvar i = 0; i < `NUM_THREADS; i++) begin
twentynm_fp_mac mac_fp_wys (
// inputs
.accumulate(),

4
hw/rtl/fp_cores/altera/VX_fp_sqrt.v
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@@ -21,9 +21,7 @@ module VX_fp_sqrt (
wire enable = ~stall;
assign ready_in = enable;
genvar i;
for (i = 0; i < `NUM_THREADS; i++) begin
for (genvar i = 0; i < `NUM_THREADS; i++) begin
acl_fp_sqrt fsqrt (
.clk (clk),
.areset (1'b0),

4
hw/rtl/fp_cores/altera/VX_fp_sub.v
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@@ -22,9 +22,7 @@ module VX_fp_sub (
wire enable = ~stall;
assign ready_in = enable;
genvar i;
for (i = 0; i < `NUM_THREADS; i++) begin
for (genvar i = 0; i < `NUM_THREADS; i++) begin
twentynm_fp_mac mac_fp_wys (
// inputs
.accumulate(),

4
hw/rtl/fp_cores/altera/VX_fp_utof.v
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@@ -21,9 +21,7 @@ module VX_fp_utof (
wire enable = ~stall;
assign ready_in = enable;
genvar i;
for (i = 0; i < `NUM_THREADS; i++) begin
for (genvar i = 0; i < `NUM_THREADS; i++) begin
acl_fp_utof utof (
.clk (clk),
.areset (1'b0),