pipeline refactoring - fmax >= 222 mhz
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9
hw/rtl/cache/VX_cache_miss_resrv.v
vendored
9
hw/rtl/cache/VX_cache_miss_resrv.v
vendored
@@ -77,9 +77,8 @@ module VX_cache_miss_resrv #(
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reg [MRVQ_SIZE-1:0] make_ready;
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reg [MRVQ_SIZE-1:0] make_ready_push;
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reg [MRVQ_SIZE-1:0] valid_address_match;
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genvar i;
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for (i = 0; i < MRVQ_SIZE; i++) begin
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for (genvar i = 0; i < MRVQ_SIZE; i++) begin
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assign valid_address_match[i] = valid_table[i] ? (addr_table[i] == fill_addr_st1) : 0;
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assign make_ready[i] = is_fill_st1 && valid_address_match[i];
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end
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@@ -121,7 +120,6 @@ module VX_cache_miss_resrv #(
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head_ptr <= 0;
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tail_ptr <= 0;
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end else begin
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if (mrvq_push) begin
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valid_table[enqueue_index] <= 1;
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ready_table[enqueue_index] <= mrvq_init_ready_state;
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@@ -157,11 +155,10 @@ module VX_cache_miss_resrv #(
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end
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`ifdef DBG_PRINT_CACHE_MSRQ
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integer j;
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always @(posedge clk) begin
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if (mrvq_push || mrvq_pop || increment_head || recover_state) begin
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$write("%t: bank%0d:%0d msrq: push=%b pop=%b incr=%d recv=%d", $time, CACHE_ID, BANK_ID, mrvq_push, mrvq_pop, increment_head, recover_state);
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for (j = 0; j < MRVQ_SIZE; j++) begin
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for (integer j = 0; j < MRVQ_SIZE; j++) begin
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if (valid_table[j]) begin
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$write(" ");
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if (schedule_ptr == $bits(schedule_ptr)'(j)) $write("*");
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