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pipeline refactoring - fmax >= 222 mhz

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This commit is contained in:
Blaise Tine
2020-08-14 21:50:14 -07:00
parent 71a46d04b9
commit 6c12391338
107 changed files with 1392 additions and 1239 deletions
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33
hw/rtl/VX_gpr_fp_ctrl.v
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@@ -10,40 +10,43 @@ module VX_gpr_fp_ctrl (
input wire [`NUM_THREADS-1:0][31:0] rs2_data,
// outputs
output wire [`NW_BITS+`NR_BITS-1:0] raddr1,
output wire [`NW_BITS+`NR_BITS-1:0] raddr1,
VX_gpr_read_if gpr_read_if
);
reg [`NUM_THREADS-1:0][31:0] tmp_rs1_data;
reg [`NUM_THREADS-1:0][31:0] rs1_tmp_data, rs2_tmp_data, rs3_tmp_data;
reg read_rs3;
wire rs3_delay = gpr_read_if.valid && gpr_read_if.use_rs3 && ~read_rs3;
wire read_fire = gpr_read_if.valid && read_rs3;
always @(posedge clk) begin
if (reset) begin
read_rs3 <= 0;
end else if (rs3_delay) begin
read_rs3 <= 1;
end else if (read_fire) begin
read_rs3 <= 0;
end
end else begin
if (rs3_delay) begin
read_rs3 <= 1;
end else if (read_fire) begin
read_rs3 <= 0;
end
end
end
// backup original rs1 data
always @(posedge clk) begin
if (rs3_delay) begin
tmp_rs1_data <= rs1_data;
if (~gpr_read_if.use_rs3 || rs3_delay) begin
rs1_tmp_data <= rs1_data;
end
rs2_tmp_data <= rs2_data;
rs3_tmp_data <= rs1_data;
end
// outputs
assign raddr1 = {gpr_read_if.warp_num, (read_rs3 ? gpr_read_if.rs3 : gpr_read_if.rs1)};
wire [`NR_BITS-1:0] rs1 = read_rs3 ? gpr_read_if.rs3 : gpr_read_if.rs1;
assign raddr1 = {gpr_read_if.wid, rs1};
assign gpr_read_if.ready = ~rs3_delay;
assign gpr_read_if.rs1_data = gpr_read_if.use_rs3 ? tmp_rs1_data : rs1_data;
assign gpr_read_if.rs2_data = rs2_data;
assign gpr_read_if.rs3_data = rs1_data;
assign gpr_read_if.rs1_data = rs1_tmp_data;
assign gpr_read_if.rs2_data = rs2_tmp_data;
assign gpr_read_if.rs3_data = rs3_tmp_data;
endmodule