pipeline refactoring - fmax >= 222 mhz
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@@ -19,7 +19,7 @@ module VX_decode #(
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wire [31:0] instr = ifetch_rsp_if.instr;
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reg [`ALU_BITS-1:0] alu_op;
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reg [`BR_BITS-1:0] br_op;
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reg [`BRU_BITS-1:0] br_op;
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reg [`LSU_BITS-1:0] lsu_op;
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reg [`CSR_BITS-1:0] csr_op;
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reg [`MUL_BITS-1:0] mul_op;
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@@ -100,27 +100,27 @@ module VX_decode #(
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wire is_br = (is_btype || is_jal || is_jalr || is_jals);
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always @(*) begin
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br_op = `BR_EQ;
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br_op = `BRU_OTHER;
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case (opcode)
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`INST_B: begin
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case (func3)
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3'h0: br_op = `BR_EQ;
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3'h1: br_op = `BR_NE;
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3'h4: br_op = `BR_LT;
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3'h5: br_op = `BR_GE;
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3'h6: br_op = `BR_LTU;
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3'h7: br_op = `BR_GEU;
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3'h0: br_op = `BRU_EQ;
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3'h1: br_op = `BRU_NE;
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3'h4: br_op = `BRU_LT;
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3'h5: br_op = `BRU_GE;
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3'h6: br_op = `BRU_LTU;
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3'h7: br_op = `BRU_GEU;
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default:;
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endcase
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end
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`INST_JAL: br_op = `BR_JAL;
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`INST_JALR: br_op = `BR_JALR;
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`INST_JAL: br_op = `BRU_JAL;
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`INST_JALR: br_op = `BRU_JALR;
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`INST_SYS: begin
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if (is_jals && u_12 == 12'h000) br_op = `BR_ECALL;
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if (is_jals && u_12 == 12'h001) br_op = `BR_EBREAK;
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if (is_jals && u_12 == 12'h302) br_op = `BR_MRET;
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if (is_jals && u_12 == 12'h102) br_op = `BR_SRET;
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if (is_jals && u_12 == 12'h7B2) br_op = `BR_DRET;
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if (is_jals && u_12 == 12'h000) br_op = `BRU_ECALL;
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if (is_jals && u_12 == 12'h001) br_op = `BRU_EBREAK;
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if (is_jals && u_12 == 12'h302) br_op = `BRU_MRET;
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if (is_jals && u_12 == 12'h102) br_op = `BRU_SRET;
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if (is_jals && u_12 == 12'h7B2) br_op = `BRU_DRET;
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end
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default:;
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endcase
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@@ -292,18 +292,17 @@ module VX_decode #(
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VX_decode_if decode_tmp_if();
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assign decode_tmp_if.valid = ifetch_rsp_if.valid;
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assign decode_tmp_if.warp_num = ifetch_rsp_if.warp_num;
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assign decode_tmp_if.thread_mask= ifetch_rsp_if.thread_mask;
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assign decode_tmp_if.curr_PC = ifetch_rsp_if.curr_PC;
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assign decode_tmp_if.next_PC = ifetch_rsp_if.curr_PC + 32'h4;
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assign decode_tmp_if.valid = ifetch_rsp_if.valid;
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assign decode_tmp_if.wid = ifetch_rsp_if.wid;
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assign decode_tmp_if.thread_mask = ifetch_rsp_if.thread_mask;
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assign decode_tmp_if.curr_PC = ifetch_rsp_if.curr_PC;
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assign decode_tmp_if.ex_type = is_lsu ? `EX_LSU :
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is_csr ? `EX_CSR :
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is_mul ? `EX_MUL :
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is_fpu ? `EX_FPU :
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is_gpu ? `EX_GPU :
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is_br ? `EX_ALU :
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is_br ? `EX_BRU :
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(is_rtype || is_itype || is_lui || is_auipc) ? `EX_ALU :
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`EX_NOP;
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@@ -312,7 +311,7 @@ module VX_decode #(
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is_mul ? `OP_BITS'(mul_op) :
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is_fpu ? `OP_BITS'(fpu_op) :
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is_gpu ? `OP_BITS'(gpu_op) :
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is_br ? `OP_BITS'({1'b1, br_op}) :
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is_br ? `OP_BITS'(br_op) :
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(is_rtype || is_itype || is_lui || is_auipc) ? `OP_BITS'(alu_op) :
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0;
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@@ -347,28 +346,28 @@ module VX_decode #(
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is_csr ? 32'(u_12) :
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src2_imm;
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assign decode_tmp_if.rs1_is_PC = is_auipc;
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assign decode_tmp_if.rs1_is_PC = is_auipc || is_btype || is_jal || is_jals;
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assign decode_tmp_if.rs2_is_imm = is_itype || is_lui || is_auipc || is_csr_imm;
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assign decode_tmp_if.frm = func3;
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assign join_if.is_join = valid_in && is_gpu && (gpu_op == `GPU_JOIN);
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assign join_if.warp_num = ifetch_rsp_if.warp_num;
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assign join_if.wid = ifetch_rsp_if.wid;
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assign wstall_if.wstall = valid_in && (is_btype || is_jal || is_jalr || (is_gpu && (gpu_op == `GPU_TMC || gpu_op == `GPU_SPLIT || gpu_op == `GPU_BAR)));
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assign wstall_if.warp_num = ifetch_rsp_if.warp_num;
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assign wstall_if.wid = ifetch_rsp_if.wid;
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wire stall = ~decode_if.ready && decode_if.valid;
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VX_generic_register #(
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.N(1 + `NW_BITS + `NUM_THREADS + 32 + 32 + `NR_BITS + `NR_BITS + `NR_BITS + 32 + 1 + `EX_BITS + `OP_BITS + 1 + `NR_BITS + 1 + 1 + `FRM_BITS + `NUM_REGS)
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.N(1 + `NW_BITS + `NUM_THREADS + 32 + `NR_BITS + `NR_BITS + `NR_BITS + 32 + 1 + `EX_BITS + `OP_BITS + 1 + `NR_BITS + 1 + 1 + `FRM_BITS + `NUM_REGS)
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) decode_reg (
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.clk (clk),
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.reset (reset),
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.stall (stall),
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.flush (0),
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.in ({decode_tmp_if.valid, decode_tmp_if.warp_num, decode_tmp_if.thread_mask, decode_tmp_if.curr_PC, decode_tmp_if.next_PC, decode_tmp_if.rd, decode_tmp_if.rs1, decode_tmp_if.rs2, decode_tmp_if.imm, decode_tmp_if.rs1_is_PC, decode_tmp_if.rs2_is_imm, decode_tmp_if.ex_type, decode_tmp_if.ex_op, decode_tmp_if.wb, decode_tmp_if.rs3, decode_tmp_if.use_rs3, decode_tmp_if.frm, decode_tmp_if.reg_use_mask}),
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.out ({decode_if.valid, decode_if.warp_num, decode_if.thread_mask, decode_if.curr_PC, decode_if.next_PC, decode_if.rd, decode_if.rs1, decode_if.rs2, decode_if.imm, decode_if.rs1_is_PC, decode_if.rs2_is_imm, decode_if.ex_type, decode_if.ex_op, decode_if.wb, decode_if.rs3, decode_if.use_rs3, decode_if.frm, decode_if.reg_use_mask})
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.in ({decode_tmp_if.valid, decode_tmp_if.wid, decode_tmp_if.thread_mask, decode_tmp_if.curr_PC, decode_tmp_if.rd, decode_tmp_if.rs1, decode_tmp_if.rs2, decode_tmp_if.imm, decode_tmp_if.rs1_is_PC, decode_tmp_if.rs2_is_imm, decode_tmp_if.ex_type, decode_tmp_if.ex_op, decode_tmp_if.wb, decode_tmp_if.rs3, decode_tmp_if.use_rs3, decode_tmp_if.frm, decode_tmp_if.reg_use_mask}),
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.out ({decode_if.valid, decode_if.wid, decode_if.thread_mask, decode_if.curr_PC, decode_if.rd, decode_if.rs1, decode_if.rs2, decode_if.imm, decode_if.rs1_is_PC, decode_if.rs2_is_imm, decode_if.ex_type, decode_if.ex_op, decode_if.wb, decode_if.rs3, decode_if.use_rs3, decode_if.frm, decode_if.reg_use_mask})
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);
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assign ifetch_rsp_if.ready = ~stall;
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@@ -376,7 +375,7 @@ module VX_decode #(
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`ifdef DBG_PRINT_PIPELINE
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always @(posedge clk) begin
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if (decode_tmp_if.valid && ~stall) begin
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$write("%t: Core%0d-Decode: warp=%0d, PC=%0h, ex=", $time, CORE_ID, decode_tmp_if.warp_num, decode_tmp_if.curr_PC);
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$write("%t: Core%0d-Decode: wid=%0d, PC=%0h, ex=", $time, CORE_ID, decode_tmp_if.wid, decode_tmp_if.curr_PC);
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print_ex_type(decode_tmp_if.ex_type);
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$write(", op=");
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print_ex_op(decode_tmp_if.ex_type, decode_tmp_if.ex_op);
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@@ -386,6 +385,7 @@ module VX_decode #(
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// trap unsupported instructions
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assert(~(~stall && (decode_tmp_if.ex_type == `EX_ALU) && `ALU_OP(decode_tmp_if.ex_op) == `ALU_OTHER));
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assert(~(~stall && (decode_tmp_if.ex_type == `EX_BRU) && `BRU_OP(decode_tmp_if.ex_op) == `BRU_OTHER));
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assert(~(~stall && (decode_tmp_if.ex_type == `EX_CSR) && `CSR_OP(decode_tmp_if.ex_op) == `CSR_OTHER));
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assert(~(~stall && (decode_tmp_if.ex_type == `EX_GPU) && `GPU_OP(decode_tmp_if.ex_op) == `GPU_OTHER));
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end
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