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pipeline refactoring - fmax >= 222 mhz

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This commit is contained in:
Blaise Tine
2020-08-14 21:50:14 -07:00
parent 71a46d04b9
commit 6c12391338
107 changed files with 1392 additions and 1239 deletions
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31
hw/rtl/VX_csr_unit.v
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@@ -15,11 +15,11 @@ module VX_csr_unit #(
VX_csr_req_if csr_req_if,
VX_exu_to_cmt_if csr_commit_if
);
VX_csr_req_if csr_pipe_req_if();
VX_exu_to_cmt_if csr_pipe_commit_if();
VX_csr_req_if csr_pipe_req_if();
VX_csr_rsp_if csr_pipe_rsp_if();
wire select_io_req = csr_io_req_if.valid;
wire select_io_rsp;
wire select_io_req = csr_io_req_if.valid;
wire select_io_rsp;
VX_csr_arb csr_arb (
.clk (clk),
@@ -29,7 +29,7 @@ module VX_csr_unit #(
.csr_io_req_if (csr_io_req_if),
.csr_req_if (csr_pipe_req_if),
.csr_rsp_if (csr_pipe_commit_if),
.csr_rsp_if (csr_pipe_rsp_if),
.csr_io_rsp_if (csr_io_rsp_if),
.csr_commit_if (csr_commit_if),
@@ -41,7 +41,7 @@ module VX_csr_unit #(
wire [`CSR_ADDR_BITS-1:0] csr_addr_s1;
wire [31:0] csr_read_data, csr_read_data_s1;
wire [31:0] csr_updated_data_s1;
wire [`NW_BITS-1:0] warp_num_s1;
wire [`NW_BITS-1:0] wid_s1;
VX_csr_data #(
.CORE_ID(CORE_ID)
@@ -56,12 +56,12 @@ module VX_csr_unit #(
.write_enable (csr_we_s1),
.write_data (csr_updated_data_s1[`CSR_WIDTH-1:0]),
.write_addr (csr_addr_s1),
.warp_num (csr_pipe_req_if.warp_num)
.wid (csr_pipe_req_if.wid)
);
wire csr_hazard = (csr_addr_s1 == csr_pipe_req_if.csr_addr)
&& (warp_num_s1 == csr_pipe_req_if.warp_num)
&& csr_pipe_commit_if.valid;
&& (wid_s1 == csr_pipe_req_if.wid)
&& csr_pipe_rsp_if.valid;
wire [31:0] csr_read_data_qual = csr_hazard ? csr_updated_data_s1 : csr_read_data;
@@ -71,7 +71,7 @@ module VX_csr_unit #(
always @(*) begin
csr_we_s0_unqual = 0;
case (csr_pipe_req_if.csr_op)
case (csr_pipe_req_if.op)
`CSR_RW: begin
csr_updated_data = csr_pipe_req_if.csr_mask;
csr_we_s0_unqual = 1;
@@ -90,7 +90,7 @@ module VX_csr_unit #(
wire csr_we_s0 = csr_we_s0_unqual && csr_pipe_req_if.valid;
wire stall = ~csr_pipe_commit_if.ready && csr_pipe_commit_if.valid;
wire stall = ~csr_pipe_rsp_if.ready && csr_pipe_rsp_if.valid;
VX_generic_register #(
.N(1 + `ISTAG_BITS + `NW_BITS + 1 + `CSR_ADDR_BITS + 1 + 32 + 32)
@@ -99,13 +99,12 @@ module VX_csr_unit #(
.reset (reset),
.stall (stall),
.flush (0),
.in ({csr_pipe_req_if.valid, csr_pipe_req_if.issue_tag, csr_pipe_req_if.warp_num, csr_we_s0, csr_pipe_req_if.csr_addr, csr_pipe_req_if.is_io, csr_read_data_qual, csr_updated_data}),
.out ({csr_pipe_commit_if.valid, csr_pipe_commit_if.issue_tag, warp_num_s1, csr_we_s1, csr_addr_s1, select_io_rsp, csr_read_data_s1, csr_updated_data_s1})
.in ({csr_pipe_req_if.valid, csr_pipe_req_if.issue_tag, csr_pipe_req_if.wid, csr_we_s0, csr_pipe_req_if.csr_addr, csr_pipe_req_if.is_io, csr_read_data_qual, csr_updated_data}),
.out ({csr_pipe_rsp_if.valid, csr_pipe_rsp_if.issue_tag, wid_s1, csr_we_s1, csr_addr_s1, select_io_rsp, csr_read_data_s1, csr_updated_data_s1})
);
genvar i;
for (i = 0; i < `NUM_THREADS; i++) begin
assign csr_pipe_commit_if.data[i] = (csr_addr_s1 == `CSR_LTID) ? i :
for (genvar i = 0; i < `NUM_THREADS; i++) begin
assign csr_pipe_rsp_if.data[i] = (csr_addr_s1 == `CSR_LTID) ? i :
(csr_addr_s1 == `CSR_GTID) ? (csr_read_data_s1 * `NUM_THREADS + i) :
csr_read_data_s1;
end