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pipeline refactoring - fmax >= 222 mhz

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This commit is contained in:
Blaise Tine
2020-08-14 21:50:14 -07:00
parent 71a46d04b9
commit 6c12391338
107 changed files with 1392 additions and 1239 deletions
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8
hw/rtl/VX_csr_arb.v
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@@ -12,7 +12,7 @@ module VX_csr_arb (
VX_csr_req_if csr_req_if,
// input
VX_exu_to_cmt_if csr_rsp_if,
VX_csr_rsp_if csr_rsp_if,
// outputs
VX_exu_to_cmt_if csr_commit_if,
@@ -28,9 +28,9 @@ module VX_csr_arb (
// requests
assign csr_req_if.valid = (~select_io_req) ? csr_core_req_if.valid : csr_io_req_if.valid;
assign csr_req_if.issue_tag = (~select_io_req) ? csr_core_req_if.issue_tag : 0;
assign csr_req_if.warp_num = (~select_io_req) ? csr_core_req_if.warp_num : 0;
assign csr_req_if.wid = (~select_io_req) ? csr_core_req_if.wid : 0;
assign csr_req_if.curr_PC = (~select_io_req) ? csr_core_req_if.curr_PC : 0;
assign csr_req_if.csr_op = (~select_io_req) ? csr_core_req_if.csr_op : (csr_io_req_if.rw ? `CSR_RW : `CSR_RS);
assign csr_req_if.op = (~select_io_req) ? csr_core_req_if.op : (csr_io_req_if.rw ? `CSR_RW : `CSR_RS);
assign csr_req_if.csr_addr = (~select_io_req) ? csr_core_req_if.csr_addr : csr_io_req_if.addr;
assign csr_req_if.csr_mask = (~select_io_req) ? csr_core_req_if.csr_mask : (csr_io_req_if.rw ? csr_io_req_if.data : 32'b0);
assign csr_req_if.rd = (~select_io_req) ? csr_core_req_if.rd : 0;
@@ -48,6 +48,6 @@ module VX_csr_arb (
assign csr_commit_if.issue_tag= csr_rsp_if.issue_tag;
assign csr_commit_if.data = csr_rsp_if.data;
assign csr_rsp_if.ready = select_io_rsp ? csr_io_rsp_if.ready : csr_commit_if.ready;
assign csr_rsp_if.ready = select_io_rsp ? csr_io_rsp_if.ready : 1'b1;
endmodule