minor update

hw/rtl/VX_alu_unit.v

@@ -78,6 +78,8 @@ module VX_alu_unit #(
             endcase
         end       
     end
+
+    // branch
     
     wire is_jal = is_br_op && (br_op == `BR_JAL || br_op == `BR_JALR);
     wire [`NUM_THREADS-1:0][31:0] alu_jal_result = is_jal ? {`NUM_THREADS{alu_req_if.next_PC}} : alu_result; 

hw/rtl/afu/vortex_afu.sv

@@ -739,8 +739,9 @@ always @(posedge clk) begin
 end
 
 VX_fifo_queue #(
-  .DATAW   (CCI_RD_QUEUE_DATAW),
-  .SIZE    (CCI_RD_QUEUE_SIZE)
+  .DATAW    (CCI_RD_QUEUE_DATAW),
+  .SIZE     (CCI_RD_QUEUE_SIZE),
+  .BUFFERED (1)
 ) cci_rd_req_queue (
   .clk      (clk),
   .reset    (reset),