diff --git a/benchmarks/opencl/guassian/.depend b/benchmarks/opencl/guassian/.depend deleted file mode 100644 index 7006e94e..00000000 --- a/benchmarks/opencl/guassian/.depend +++ /dev/null @@ -1,12 +0,0 @@ -main.o: main.cc gaussianElim.h clutils.h \ - /opt/pocl/runtime/include/CL/cl.h \ - /opt/pocl/runtime/include/CL/cl_version.h \ - /opt/pocl/runtime/include/CL/cl_platform.h \ - /opt/pocl/runtime/include/CL/opencl.h \ - /opt/pocl/runtime/include/CL/cl_gl.h \ - /opt/pocl/runtime/include/CL/cl_gl_ext.h \ - /opt/pocl/runtime/include/CL/cl_ext.h -clutils.o: clutils.cpp /opt/pocl/runtime/include/CL/cl.h \ - /opt/pocl/runtime/include/CL/cl_version.h \ - /opt/pocl/runtime/include/CL/cl_platform.h clutils.h utils.h -utils.o: utils.cpp utils.h diff --git a/benchmarks/opencl/guassian/guassian b/benchmarks/opencl/guassian/guassian deleted file mode 100755 index be28fb83..00000000 Binary files a/benchmarks/opencl/guassian/guassian and /dev/null differ diff --git a/benchmarks/opencl/nearn/.depend b/benchmarks/opencl/nearn/.depend deleted file mode 100644 index 083b7b77..00000000 --- a/benchmarks/opencl/nearn/.depend +++ /dev/null @@ -1,11 +0,0 @@ -main.o: main.cc nearestNeighbor.h /opt/pocl/runtime/include/CL/opencl.h \ - /opt/pocl/runtime/include/CL/cl.h \ - /opt/pocl/runtime/include/CL/cl_version.h \ - /opt/pocl/runtime/include/CL/cl_platform.h \ - /opt/pocl/runtime/include/CL/cl_gl.h \ - /opt/pocl/runtime/include/CL/cl_gl_ext.h \ - /opt/pocl/runtime/include/CL/cl_ext.h clutils.h -clutils.o: clutils.cpp /opt/pocl/runtime/include/CL/cl.h \ - /opt/pocl/runtime/include/CL/cl_version.h \ - /opt/pocl/runtime/include/CL/cl_platform.h clutils.h utils.h -utils.o: utils.cpp utils.h diff --git a/benchmarks/opencl/saxpy/.depend b/benchmarks/opencl/saxpy/.depend deleted file mode 100644 index 1960f024..00000000 --- a/benchmarks/opencl/saxpy/.depend +++ /dev/null @@ -1,3 +0,0 @@ -main.o: main.cc /opt/pocl/runtime/include/CL/cl.h \ - /opt/pocl/runtime/include/CL/cl_version.h \ - /opt/pocl/runtime/include/CL/cl_platform.h diff --git a/benchmarks/opencl/saxpy/saxpy b/benchmarks/opencl/saxpy/saxpy deleted file mode 100755 index 7e11e504..00000000 Binary files a/benchmarks/opencl/saxpy/saxpy and /dev/null differ diff --git a/benchmarks/opencl/sfilter/.depend b/benchmarks/opencl/sfilter/.depend deleted file mode 100644 index 1960f024..00000000 --- a/benchmarks/opencl/sfilter/.depend +++ /dev/null @@ -1,3 +0,0 @@ -main.o: main.cc /opt/pocl/runtime/include/CL/cl.h \ - /opt/pocl/runtime/include/CL/cl_version.h \ - /opt/pocl/runtime/include/CL/cl_platform.h diff --git a/benchmarks/opencl/sfilter/sfilter b/benchmarks/opencl/sfilter/sfilter deleted file mode 100755 index dfafd2bf..00000000 Binary files a/benchmarks/opencl/sfilter/sfilter and /dev/null differ diff --git a/benchmarks/opencl/sgemm/.depend b/benchmarks/opencl/sgemm/.depend deleted file mode 100644 index 632ededc..00000000 --- a/benchmarks/opencl/sgemm/.depend +++ /dev/null @@ -1,7 +0,0 @@ -main.o: main.cc /opt/pocl/runtime/include/CL/opencl.h \ - /opt/pocl/runtime/include/CL/cl.h \ - /opt/pocl/runtime/include/CL/cl_version.h \ - /opt/pocl/runtime/include/CL/cl_platform.h \ - /opt/pocl/runtime/include/CL/cl_gl.h \ - /opt/pocl/runtime/include/CL/cl_gl_ext.h \ - /opt/pocl/runtime/include/CL/cl_ext.h diff --git a/benchmarks/opencl/sgemm/sgemm b/benchmarks/opencl/sgemm/sgemm deleted file mode 100755 index 6a5dc24b..00000000 Binary files a/benchmarks/opencl/sgemm/sgemm and /dev/null differ diff --git a/benchmarks/opencl/vecadd/.depend b/benchmarks/opencl/vecadd/.depend deleted file mode 100644 index 632ededc..00000000 --- a/benchmarks/opencl/vecadd/.depend +++ /dev/null @@ -1,7 +0,0 @@ -main.o: main.cc /opt/pocl/runtime/include/CL/opencl.h \ - /opt/pocl/runtime/include/CL/cl.h \ - /opt/pocl/runtime/include/CL/cl_version.h \ - /opt/pocl/runtime/include/CL/cl_platform.h \ - /opt/pocl/runtime/include/CL/cl_gl.h \ - /opt/pocl/runtime/include/CL/cl_gl_ext.h \ - /opt/pocl/runtime/include/CL/cl_ext.h diff --git a/driver/opae/.depend b/driver/opae/.depend deleted file mode 100644 index 33a007b5..00000000 --- a/driver/opae/.depend +++ /dev/null @@ -1,4 +0,0 @@ -vortex.o: vortex.cpp ../include/vortex.h ../../hw/VX_config.h \ - vortex_afu.h -vx_utils.o: ../common/vx_utils.cpp ../include/vortex.h \ - ../../hw/VX_config.h diff --git a/driver/opae/vlsim/Makefile b/driver/opae/vlsim/Makefile index 69dabc36..47611fe5 100644 --- a/driver/opae/vlsim/Makefile +++ b/driver/opae/vlsim/Makefile @@ -44,7 +44,8 @@ SRCS = fpga.cpp opae_sim.cpp SRCS += $(DPI_DIR)/util_dpi.cpp $(DPI_DIR)/float_dpi.cpp FPU_INCLUDE = -I$(RTL_DIR)/fp_cores -I$(DPI_DIR) -I$(RTL_DIR)/fp_cores/fpnew/src/common_cells/include -I$(RTL_DIR)/fp_cores/fpnew/src/common_cells/src -I$(RTL_DIR)/fp_cores/fpnew/src/fpu_div_sqrt_mvp/hdl -I$(RTL_DIR)/fp_cores/fpnew/src -RTL_INCLUDE = -I$(RTL_DIR) -I$(RTL_DIR)/libs -I$(RTL_DIR)/interfaces -I$(RTL_DIR)/cache $(FPU_INCLUDE) +TEX_INCLUDE = -I$(RTL_DIR)/tex_unit +RTL_INCLUDE = -I$(RTL_DIR) -I$(RTL_DIR)/libs -I$(RTL_DIR)/interfaces -I$(RTL_DIR)/cache $(FPU_INCLUDE) $(TEX_INCLUDE) RTL_INCLUDE += -I$(RTL_DIR)/afu -I$(RTL_DIR)/afu/ccip VL_FLAGS += -O2 --language 1800-2009 --assert -Wall -Wpedantic $(CONFIGS) diff --git a/driver/opae/vlsim/libopae-c-vlsim.so b/driver/opae/vlsim/libopae-c-vlsim.so deleted file mode 100755 index 39527d15..00000000 Binary files a/driver/opae/vlsim/libopae-c-vlsim.so and /dev/null differ diff --git a/driver/opae/vlsim/libvortex.so b/driver/opae/vlsim/libvortex.so deleted file mode 100755 index a7fea0da..00000000 Binary files a/driver/opae/vlsim/libvortex.so and /dev/null differ diff --git a/driver/rtlsim/Makefile b/driver/rtlsim/Makefile index 2dc8e72e..c665ffcb 100644 --- a/driver/rtlsim/Makefile +++ b/driver/rtlsim/Makefile @@ -41,7 +41,8 @@ SRCS = vortex.cpp ../common/vx_utils.cpp ../../hw/simulate/simulator.cpp SRCS += $(DPI_DIR)/util_dpi.cpp $(DPI_DIR)/float_dpi.cpp FPU_INCLUDE = -I$(RTL_DIR)/fp_cores -I$(DPI_DIR) -I$(RTL_DIR)/fp_cores/fpnew/src/common_cells/include -I$(RTL_DIR)/fp_cores/fpnew/src/common_cells/src -I$(RTL_DIR)/fp_cores/fpnew/src/fpu_div_sqrt_mvp/hdl -I$(RTL_DIR)/fp_cores/fpnew/src -RTL_INCLUDE = -I$(RTL_DIR) -I$(RTL_DIR)/libs -I$(RTL_DIR)/interfaces -I$(RTL_DIR)/cache $(FPU_INCLUDE) +TEX_INCLUDE = -I$(RTL_DIR)/tex_unit +RTL_INCLUDE = -I$(RTL_DIR) -I$(RTL_DIR)/libs -I$(RTL_DIR)/interfaces -I$(RTL_DIR)/cache $(FPU_INCLUDE) $(TEX_INCLUDE) VL_FLAGS += -O2 --language 1800-2009 --assert -Wall -Wpedantic $(CONFIGS) VL_FLAGS += -Wno-DECLFILENAME diff --git a/driver/stub/libvortex.so b/driver/stub/libvortex.so deleted file mode 100755 index 0c50c54c..00000000 Binary files a/driver/stub/libvortex.so and /dev/null differ diff --git a/driver/tests/tex_demo/.depend b/driver/tests/tex_demo/.depend deleted file mode 100644 index 1647eae7..00000000 --- a/driver/tests/tex_demo/.depend +++ /dev/null @@ -1 +0,0 @@ -demo.o: demo.cpp ../../include/vortex.h common.h diff --git a/hw/VX_config.h b/hw/VX_config.h deleted file mode 100644 index 05339ece..00000000 --- a/hw/VX_config.h +++ /dev/null @@ -1,437 +0,0 @@ -// auto-generated by gen_config.py. DO NOT EDIT -// Generated at 2021-03-13 13:57:30.622905 - -#ifndef VX_USER_CONFIG -#define VX_USER_CONFIG - - -#endif -// auto-generated by gen_config.py. DO NOT EDIT -// Generated at 2021-03-13 13:57:30.624676 - -// Translated from VX_config.vh: - -#ifndef VX_CONFIG -#define VX_CONFIG - - - -#ifndef NUM_CLUSTERS -#define NUM_CLUSTERS 1 -#endif - -#ifndef NUM_CORES -#define NUM_CORES 1 -#endif - -#ifndef NUM_WARPS -#define NUM_WARPS 4 -#endif - -#ifndef NUM_THREADS -#define NUM_THREADS 4 -#endif - -#ifndef NUM_BARRIERS -#define NUM_BARRIERS 4 -#endif - -#ifndef L2_ENABLE -#define L2_ENABLE 0 -#endif - -#ifndef L3_ENABLE -#define L3_ENABLE 0 -#endif - -#ifndef SM_ENABLE -#define SM_ENABLE 1 -#endif - -#ifndef GLOBAL_BLOCK_SIZE -#define GLOBAL_BLOCK_SIZE 64 -#endif - -#ifndef L1_BLOCK_SIZE -#define L1_BLOCK_SIZE (NUM_THREADS * 4) -#endif - -#ifndef STARTUP_ADDR -#define STARTUP_ADDR 0x80000000 -#endif - -#ifndef IO_BUS_BASE_ADDR -#define IO_BUS_BASE_ADDR 0xFF000000 -#endif - -#ifndef SHARED_MEM_BASE_ADDR -#define SHARED_MEM_BASE_ADDR IO_BUS_BASE_ADDR -#endif - -#ifndef SHARED_MEM_BASE_ADDR_ALIGN -#define SHARED_MEM_BASE_ADDR_ALIGN 64 -#endif - -#ifndef IO_BUS_ADDR_COUT -#define IO_BUS_ADDR_COUT 0xFFFFFFFC -#endif - -#ifndef FRAME_BUFFER_BASE_ADDR -#define FRAME_BUFFER_BASE_ADDR 0xFF000000 -#endif - -#ifndef FRAME_BUFFER_WIDTH -#define FRAME_BUFFER_WIDTH 1920 -#endif - -#ifndef FRAME_BUFFER_HEIGHT -#define FRAME_BUFFER_HEIGHT 1080 -#endif - -#define FRAME_BUFFER_SIZE (FRAME_BUFFER_WIDTH * FRAME_BUFFER_HEIGHT) - -#ifndef EXT_M_DISABLE -#define EXT_M_ENABLE -#endif - -#ifndef EXT_F_DISABLE -#define EXT_F_ENABLE -#endif - -// Device identification -#define VENDOR_ID 0 -#define ARCHITECTURE_ID 0 -#define IMPLEMENTATION_ID 0 - -/////////////////////////////////////////////////////////////////////////////// - -#ifndef LATENCY_IMUL -#define LATENCY_IMUL 3 -#endif - -#ifndef LATENCY_FNCP -#define LATENCY_FNCP 2 -#endif - -#ifndef LATENCY_FMA -#define LATENCY_FMA 4 -#endif - -#ifndef LATENCY_FDIV -#ifdef ALTERA_S10 -#define LATENCY_FDIV 34 -#else -#define LATENCY_FDIV 15 -#endif -#endif - -#ifndef LATENCY_FSQRT -#ifdef ALTERA_S10 -#define LATENCY_FSQRT 25 -#else -#define LATENCY_FSQRT 10 -#endif -#endif - -#ifndef LATENCY_FDIVSQRT -#define LATENCY_FDIVSQRT 32 -#endif - -#ifndef LATENCY_FCVT -#define LATENCY_FCVT 4 -#endif - -// CSR Addresses ////////////////////////////////////////////////////////////// - -// User Floating-Point CSRs -#define CSR_FFLAGS 0x001 -#define CSR_FRM 0x002 -#define CSR_FCSR 0x003 - -#define CSR_SATP 0x180 - -#define CSR_PMPCFG0 0x3A0 -#define CSR_PMPADDR0 0x3B0 - -#define CSR_MSTATUS 0x300 -#define CSR_MISA 0x301 -#define CSR_MEDELEG 0x302 -#define CSR_MIDELEG 0x303 -#define CSR_MIE 0x304 -#define CSR_MTVEC 0x305 - -#define CSR_MEPC 0x341 - -// Machine Counter/Timers -#define CSR_CYCLE 0xC00 -#define CSR_CYCLE_H 0xC80 -#define CSR_INSTRET 0xC02 -#define CSR_INSTRET_H 0xC82 - -// Machine Performance-monitoring counters -// PERF: pipeline -#define CSR_MPM_IBUF_ST 0xB03 -#define CSR_MPM_IBUF_ST_H 0xB83 -#define CSR_MPM_SCRB_ST 0xB04 -#define CSR_MPM_SCRB_ST_H 0xB84 -#define CSR_MPM_ALU_ST 0xB05 -#define CSR_MPM_ALU_ST_H 0xB85 -#define CSR_MPM_LSU_ST 0xB06 -#define CSR_MPM_LSU_ST_H 0xB86 -#define CSR_MPM_CSR_ST 0xB07 -#define CSR_MPM_CSR_ST_H 0xB87 -#define CSR_MPM_FPU_ST 0xB08 -#define CSR_MPM_FPU_ST_H 0xB88 -#define CSR_MPM_GPU_ST 0xB09 -#define CSR_MPM_GPU_ST_H 0xB89 -// PERF: icache -#define CSR_MPM_ICACHE_READS 0xB0A // total reads -#define CSR_MPM_ICACHE_READS_H 0xB8A -#define CSR_MPM_ICACHE_MISS_R 0xB0B // total misses -#define CSR_MPM_ICACHE_MISS_R_H 0xB8B -#define CSR_MPM_ICACHE_PIPE_ST 0xB0C // pipeline stalls -#define CSR_MPM_ICACHE_PIPE_ST_H 0xB8C -#define CSR_MPM_ICACHE_CRSP_ST 0xB0D // core response stalls -#define CSR_MPM_ICACHE_CRSP_ST_H 0xB8D -// PERF: dcache -#define CSR_MPM_DCACHE_READS 0xB0E // total reads -#define CSR_MPM_DCACHE_READS_H 0xB8E -#define CSR_MPM_DCACHE_WRITES 0xB0F // total writes -#define CSR_MPM_DCACHE_WRITES_H 0xB8F -#define CSR_MPM_DCACHE_MISS_R 0xB10 // read misses -#define CSR_MPM_DCACHE_MISS_R_H 0xB90 -#define CSR_MPM_DCACHE_MISS_W 0xB11 // write misses -#define CSR_MPM_DCACHE_MISS_W_H 0xB91 -#define CSR_MPM_DCACHE_BANK_ST 0xB12 // bank conflicts stalls -#define CSR_MPM_DCACHE_BANK_ST_H 0xB92 -#define CSR_MPM_DCACHE_MSHR_ST 0xB13 // MSHR stalls -#define CSR_MPM_DCACHE_MSHR_ST_H 0xB93 -#define CSR_MPM_DCACHE_PIPE_ST 0xB14 // pipeline stalls -#define CSR_MPM_DCACHE_PIPE_ST_H 0xB94 -#define CSR_MPM_DCACHE_CRSP_ST 0xB15 // core response stalls -#define CSR_MPM_DCACHE_CRSP_ST_H 0xB95 -// PERF: smem -#define CSR_MPM_SMEM_READS 0xB16 // total reads -#define CSR_MPM_SMEM_READS_H 0xB96 -#define CSR_MPM_SMEM_WRITES 0xB17 // total writes -#define CSR_MPM_SMEM_WRITES_H 0xB97 -#define CSR_MPM_SMEM_BANK_ST 0xB18 // bank conflicts stalls -#define CSR_MPM_SMEM_BANK_ST_H 0xB98 -// PERF: memory -#define CSR_MPM_DRAM_READS 0xB19 // dram reads -#define CSR_MPM_DRAM_READS_H 0xB99 -#define CSR_MPM_DRAM_WRITES 0xB1A // dram writes -#define CSR_MPM_DRAM_WRITES_H 0xB9A -#define CSR_MPM_DRAM_ST 0xB1B // dram request stalls -#define CSR_MPM_DRAM_ST_H 0xB9B -#define CSR_MPM_DRAM_LAT 0xB1C // dram latency (total) -#define CSR_MPM_DRAM_LAT_H 0xB9C - -// Machine Information Registers -#define CSR_MVENDORID 0xF11 -#define CSR_MARCHID 0xF12 -#define CSR_MIMPID 0xF13 -#define CSR_MHARTID 0xF14 - -// User SIMT CSRs -#define CSR_WTID 0xCC0 -#define CSR_LTID 0xCC1 -#define CSR_GTID 0xCC2 -#define CSR_LWID 0xCC3 -#define CSR_GWID CSR_MHARTID -#define CSR_GCID 0xCC5 - -// Machine SIMT CSRs -#define CSR_NT 0xFC0 -#define CSR_NW 0xFC1 -#define CSR_NC 0xFC2 - -////////// Texture Unit CSRs ///////////// -#define CSR_TEX_BEGIN 0xFD0 -// Unit 1 -#define CSR_TEX0_ADDR CSR_TEX_BEGIN -#define CSR_TEX0_FORMAT CSR_TEX_BEGIN + 0x1 -#define CSR_TEX0_WIDTH CSR_TEX_BEGIN + 0x2 -#define CSR_TEX0_HEIGHT CSR_TEX_BEGIN + 0x3 -#define CSR_TEX0_STRIDE CSR_TEX_BEGIN + 0x4 -#define CSR_TEX0_WRAP_U CSR_TEX_BEGIN + 0x5 -#define CSR_TEX0_WRAP_V CSR_TEX_BEGIN + 0x6 -#define CSR_TEX0_MIN_FILTER CSR_TEX_BEGIN + 0x7 -#define CSR_TEX0_MAX_FILTER CSR_TEX_BEGIN + 0x8 - -// Unit 2 -#define CSR_TEX1_ADDR CSR_TEX_BEGIN + 0x9 -#define CSR_TEX1_FORMAT CSR_TEX_BEGIN + 0xA -#define CSR_TEX1_WIDTH CSR_TEX_BEGIN + 0xB -#define CSR_TEX1_HEIGHT CSR_TEX_BEGIN + 0xC -#define CSR_TEX1_STRIDE CSR_TEX_BEGIN + 0xD -#define CSR_TEX1_WRAP_U CSR_TEX_BEGIN + 0xE -#define CSR_TEX1_WRAP_V CSR_TEX_BEGIN + 0xF -#define CSR_TEX1_MIN_FILTER CSR_TEX_BEGIN + 0x10 -#define CSR_TEX1_MAX_FILTER CSR_TEX_BEGIN + 0x11 - -#define CSR_TEX_END CSR_TEX1_MAX_FILTER -// Pipeline Queues //////////////////////////////////////////////////////////// - -// Size of LSU Request Queue -#ifndef LSUQ_SIZE -#define LSUQ_SIZE 8 -#endif - -// Size of FPU Request Queue -#ifndef FPUQ_SIZE -#define FPUQ_SIZE 8 -#endif - -// Icache Configurable Knobs ////////////////////////////////////////////////// - -// Size of cache in bytes -#ifndef ICACHE_SIZE -#define ICACHE_SIZE 16384 -#endif - -// Core Request Queue Size -#ifndef ICREQ_SIZE -#define ICREQ_SIZE 4 -#endif - -// Miss Handling Register Size -#ifndef IMSHR_SIZE -#define IMSHR_SIZE NUM_WARPS -#endif - -// DRAM Request Queue Size -#ifndef IDREQ_SIZE -#define IDREQ_SIZE 4 -#endif - -// DRAM Response Queue Size -#ifndef IDRSQ_SIZE -#define IDRSQ_SIZE 4 -#endif - -// Dcache Configurable Knobs ////////////////////////////////////////////////// - -// Size of cache in bytes -#ifndef DCACHE_SIZE -#define DCACHE_SIZE 16384 -#endif - -// Number of banks -#ifndef DNUM_BANKS -#define DNUM_BANKS NUM_THREADS -#endif - -// Number of bank ports -#ifndef DNUM_PORTS -#define DNUM_PORTS 1 -#endif - -// Core Request Queue Size -#ifndef DCREQ_SIZE -#define DCREQ_SIZE 4 -#endif - -// Miss Handling Register Size -#ifndef DMSHR_SIZE -#define DMSHR_SIZE LSUQ_SIZE -#endif - -// DRAM Request Queue Size -#ifndef DDREQ_SIZE -#define DDREQ_SIZE 4 -#endif - -// DRAM Response Queue Size -#ifndef DDRSQ_SIZE -#define DDRSQ_SIZE MAX(4, (DNUM_BANKS * 2)) -#endif - -// SM Configurable Knobs ////////////////////////////////////////////////////// - -// per thread stack size -#ifndef STACK_SIZE -#define STACK_SIZE 1024 -#endif - -// Size of cache in bytes -#ifndef SMEM_SIZE -#define SMEM_SIZE (STACK_SIZE * NUM_WARPS * NUM_THREADS) -#endif - -// Number of banks -#ifndef SNUM_BANKS -#define SNUM_BANKS NUM_THREADS -#endif - -// Core Request Queue Size -#ifndef SCREQ_SIZE -#define SCREQ_SIZE 4 -#endif - -// L2cache Configurable Knobs ///////////////////////////////////////////////// - -// Size of cache in bytes -#ifndef L2CACHE_SIZE -#define L2CACHE_SIZE 65536 -#endif - -// Number of banks -#ifndef L2NUM_BANKS -#define L2NUM_BANKS MIN(NUM_CORES, 4) -#endif - -// Core Request Queue Size -#ifndef L2CREQ_SIZE -#define L2CREQ_SIZE 4 -#endif - -// Miss Handling Register Size -#ifndef L2MSHR_SIZE -#define L2MSHR_SIZE 16 -#endif - -// DRAM Request Queue Size -#ifndef L2DREQ_SIZE -#define L2DREQ_SIZE 4 -#endif - -// DRAM Response Queue Size -#ifndef L2DRSQ_SIZE -#define L2DRSQ_SIZE MAX(4, (L2NUM_BANKS * 2)) -#endif - -// L3cache Configurable Knobs ///////////////////////////////////////////////// - -// Size of cache in bytes -#ifndef L3CACHE_SIZE -#define L3CACHE_SIZE 131072 -#endif - -// Number of banks -#ifndef L3NUM_BANKS -#define L3NUM_BANKS MIN(NUM_CLUSTERS, 4) -#endif - -// Core Request Queue Size -#ifndef L3CREQ_SIZE -#define L3CREQ_SIZE 4 -#endif - -// Miss Handling Register Size -#ifndef L3MSHR_SIZE -#define L3MSHR_SIZE 16 -#endif - -// DRAM Request Queue Size -#ifndef L3DREQ_SIZE -#define L3DREQ_SIZE 4 -#endif - -// DRAM Response Queue Size -#ifndef L3DRSQ_SIZE -#define L3DRSQ_SIZE MAX(4, (L3NUM_BANKS * 2)) -#endif - -#endif - diff --git a/hw/rtl/tex_unit/VX_tex_unit.v b/hw/rtl/tex_unit/VX_tex_unit.v index 6961cb3c..dd6ba8a3 100644 --- a/hw/rtl/tex_unit/VX_tex_unit.v +++ b/hw/rtl/tex_unit/VX_tex_unit.v @@ -44,8 +44,7 @@ module VX_tex_unit #( // output wire cache_rsp_ready ); - // `UNUSED_VAR (clk) - `UNUSED_VAR (reset) + `UNUSED_PARAM (CORE_ID) `UNUSED_VAR (reset) `UNUSED_VAR(tex_addr) diff --git a/runtime/libvortexrt.a b/runtime/libvortexrt.a deleted file mode 100644 index e762c866..00000000 Binary files a/runtime/libvortexrt.a and /dev/null differ diff --git a/runtime/libvortexrt.dump b/runtime/libvortexrt.dump deleted file mode 100644 index 7f1de08a..00000000 --- a/runtime/libvortexrt.dump +++ /dev/null @@ -1,1073 +0,0 @@ -In archive libvortexrt.a: - -vx_start.S.o: file format elf32-littleriscv - - -Disassembly of section .text: - -00000000 <_exit>: - 0: 00000513 li a0,0 - 4: 0005006b 0x5006b - -00000008 : - 8: fc002573 csrr a0,0xfc0 - c: 0005006b 0x5006b - 10: 00000197 auipc gp,0x0 - 14: 00018193 mv gp,gp - 18: 00000117 auipc sp,0x0 - 1c: 00010113 mv sp,sp - 20: 00000597 auipc a1,0x0 - 24: 00058593 mv a1,a1 - 28: cc102673 csrr a2,0xcc1 - 2c: 02c585b3 mul a1,a1,a2 - 30: 40b10133 sub sp,sp,a1 - 34: cc3026f3 csrr a3,0xcc3 - 38: 00068663 beqz a3,44 - 3c: 00000513 li a0,0 - 40: 0005006b 0x5006b - -00000044 : - 44: 00008067 ret - -Disassembly of section .data: - -00000000 <__dso_handle>: - 0: 0000 unimp - ... - -Disassembly of section .init: - -00000000 <_start>: - 0: 00000597 auipc a1,0x0 - 4: 00058593 mv a1,a1 - 8: fc102573 csrr a0,0xfc1 - c: 00b5106b 0xb5106b - 10: ff9ff0ef jal ra,8 <_start+0x8> - 14: 00100513 li a0,1 - 18: 0005006b 0x5006b - 1c: 00000517 auipc a0,0x0 - 20: 00050513 mv a0,a0 - 24: 00000617 auipc a2,0x0 - 28: 00060613 mv a2,a2 - 2c: 40a60633 sub a2,a2,a0 - 30: 00000593 li a1,0 - 34: 00000097 auipc ra,0x0 - 38: 000080e7 jalr ra # 34 <_start+0x34> - 3c: 00000517 auipc a0,0x0 - 40: 00050513 mv a0,a0 - 44: 00000097 auipc ra,0x0 - 48: 000080e7 jalr ra # 44 <_start+0x44> - 4c: 00000097 auipc ra,0x0 - 50: 000080e7 jalr ra # 4c <_start+0x4c> - 54: 00000097 auipc ra,0x0 - 58: 000080e7 jalr ra # 54 <_start+0x54> - 5c: 00000317 auipc t1,0x0 - 60: 00030067 jr t1 # 5c <_start+0x5c> - -Disassembly of section .riscv.attributes: - -00000000 <.riscv.attributes>: - 0: 2341 jal 580 - 2: 0000 unimp - 4: 7200 flw fs0,32(a2) - 6: 7369 lui t1,0xffffa - 8: 01007663 bgeu zero,a6,14 <.riscv.attributes+0x14> - c: 0019 c.nop 6 - e: 0000 unimp - 10: 7205 lui tp,0xfffe1 - 12: 3376 fld ft6,376(sp) - 14: 6932 flw fs2,12(sp) - 16: 7032 flw ft0,44(sp) - 18: 5f30 lw a2,120(a4) - 1a: 326d jal fffff9c4 - 1c: 3070 fld fa2,224(s0) - 1e: 665f 7032 0030 0x307032665f - -vx_print.S.o: file format elf32-littleriscv - - -Disassembly of section .text: - -00000000 : - 0: 00000297 auipc t0,0x0 - 4: 00028293 mv t0,t0 - 8: 0002a283 lw t0,0(t0) # 0 - c: cc202373 csrr t1,0xcc2 - 10: 01031313 slli t1,t1,0x10 - 14: 00a36333 or t1,t1,a0 - 18: 0062a023 sw t1,0(t0) - 1c: 00008067 ret - -Disassembly of section .data: - -00000000 : - 0: fffc fsw fa5,124(a5) - 2: ffff 0xffff - -Disassembly of section .riscv.attributes: - -00000000 <.riscv.attributes>: - 0: 2341 jal 580 - 2: 0000 unimp - 4: 7200 flw fs0,32(a2) - 6: 7369 lui t1,0xffffa - 8: 01007663 bgeu zero,a6,14 <.riscv.attributes+0x14> - c: 0019 c.nop 6 - e: 0000 unimp - 10: 7205 lui tp,0xfffe1 - 12: 3376 fld ft6,376(sp) - 14: 6932 flw fs2,12(sp) - 16: 7032 flw ft0,44(sp) - 18: 5f30 lw a2,120(a4) - 1a: 326d jal fffff9c4 - 1c: 3070 fld fa2,224(s0) - 1e: 665f 7032 0030 0x307032665f - -vx_print.c.o: file format elf32-littleriscv - - -Disassembly of section .text.vx_vprintf: - -00000000 : - 0: 22050063 beqz a0,220 <.L24> - 4: f5010113 addi sp,sp,-176 - 8: 0a812423 sw s0,168(sp) - c: 09312e23 sw s3,156(sp) - 10: 0a112623 sw ra,172(sp) - 14: 0a912223 sw s1,164(sp) - 18: 0b212023 sw s2,160(sp) - 1c: 09412c23 sw s4,152(sp) - 20: 09512a23 sw s5,148(sp) - 24: 09612823 sw s6,144(sp) - 28: 09712623 sw s7,140(sp) - 2c: 00050993 mv s3,a0 - 30: 00054503 lbu a0,0(a0) - 34: 00198413 addi s0,s3,1 - 38: 1e050063 beqz a0,218 <.L25> - 3c: 000034b7 lui s1,0x3 - 40: 00000ab7 lui s5,0x0 - 44: 00058a13 mv s4,a1 - 48: 02500913 li s2,37 - 4c: 80948493 addi s1,s1,-2039 # 2809 <.L24+0x25e9> - 50: 000a8a93 mv s5,s5 - -00000054 <.L23>: - 54: 05250663 beq a0,s2,a0 <.L38> - 58: 00000097 auipc ra,0x0 - 5c: 000080e7 jalr ra # 58 <.L23+0x4> - 60: 00044503 lbu a0,0(s0) - 64: 00140b13 addi s6,s0,1 - 68: 000b0413 mv s0,s6 - 6c: fe0514e3 bnez a0,54 <.L23> - -00000070 <.L40>: - 70: 41340533 sub a0,s0,s3 - -00000074 <.L1>: - 74: 0ac12083 lw ra,172(sp) - 78: 0a812403 lw s0,168(sp) - 7c: 0a412483 lw s1,164(sp) - 80: 0a012903 lw s2,160(sp) - 84: 09c12983 lw s3,156(sp) - 88: 09812a03 lw s4,152(sp) - 8c: 09412a83 lw s5,148(sp) - 90: 09012b03 lw s6,144(sp) - 94: 08c12b83 lw s7,140(sp) - 98: 0b010113 addi sp,sp,176 - 9c: 00008067 ret - -000000a0 <.L38>: - a0: 00040b13 mv s6,s0 - a4: 00d00613 li a2,13 - a8: 00100693 li a3,1 - -000000ac <.L6>: - ac: 000b4703 lbu a4,0(s6) - b0: 000b0513 mv a0,s6 - b4: 001b0b13 addi s6,s6,1 - b8: fe070793 addi a5,a4,-32 - bc: 0ff7f793 andi a5,a5,255 - c0: 00f66863 bltu a2,a5,d0 <.L5> - c4: 00f697b3 sll a5,a3,a5 - c8: 0097f7b3 and a5,a5,s1 - cc: fe0790e3 bnez a5,ac <.L6> - -000000d0 <.L5>: - d0: 02a00793 li a5,42 - d4: 00f70c63 beq a4,a5,ec <.L7> - d8: 00a00613 li a2,10 - dc: 04010593 addi a1,sp,64 - e0: 00000097 auipc ra,0x0 - e4: 000080e7 jalr ra # e0 <.L5+0x10> - e8: 04012b03 lw s6,64(sp) - -000000ec <.L7>: - ec: 000b4783 lbu a5,0(s6) - f0: 02e00713 li a4,46 - f4: 001b0513 addi a0,s6,1 - f8: 0ee78263 beq a5,a4,1dc <.L39> - -000000fc <.L8>: - fc: fb478793 addi a5,a5,-76 - 100: 0ff7f793 andi a5,a5,255 - 104: 02e00713 li a4,46 - 108: 02f76463 bltu a4,a5,130 <.L10> - 10c: 00279793 slli a5,a5,0x2 - 110: 015787b3 add a5,a5,s5 - 114: 0007a783 lw a5,0(a5) - 118: 00078067 jr a5 - -0000011c <.L14>: - 11c: 001b4703 lbu a4,1(s6) - 120: 06800793 li a5,104 - 124: 08f70e63 beq a4,a5,1c0 <.L16> - -00000128 <.L11>: - 128: 00050b13 mv s6,a0 - 12c: 00150513 addi a0,a0,1 - -00000130 <.L10>: - 130: 05210023 sb s2,64(sp) - 134: 40850533 sub a0,a0,s0 - 138: 08a05e63 blez a0,1d4 <.L26> - -0000013c <.L41>: - 13c: 00040793 mv a5,s0 - 140: 04110713 addi a4,sp,65 - 144: 00a40633 add a2,s0,a0 - -00000148 <.L18>: - 148: 0007c683 lbu a3,0(a5) - 14c: 00178793 addi a5,a5,1 - 150: 00170713 addi a4,a4,1 - 154: fed70fa3 sb a3,-1(a4) - 158: fec798e3 bne a5,a2,148 <.L18> - 15c: 00150513 addi a0,a0,1 - -00000160 <.L17>: - 160: 08010793 addi a5,sp,128 - 164: 00a787b3 add a5,a5,a0 - 168: 000a0693 mv a3,s4 - 16c: 04010613 addi a2,sp,64 - 170: 10000593 li a1,256 - 174: 00010513 mv a0,sp - 178: fc078023 sb zero,-64(a5) - 17c: 00000097 auipc ra,0x0 - 180: 000080e7 jalr ra # 17c <.L17+0x1c> - 184: 00010413 mv s0,sp - 188: 00a10bb3 add s7,sp,a0 - 18c: 00a05c63 blez a0,1a4 <.L22> - -00000190 <.L21>: - 190: 00044503 lbu a0,0(s0) - 194: 00140413 addi s0,s0,1 - 198: 00000097 auipc ra,0x0 - 19c: 000080e7 jalr ra # 198 <.L21+0x8> - 1a0: fe8b98e3 bne s7,s0,190 <.L21> - -000001a4 <.L22>: - 1a4: 001b4503 lbu a0,1(s6) - 1a8: 002b0413 addi s0,s6,2 - 1ac: ea0514e3 bnez a0,54 <.L23> - 1b0: ec1ff06f j 70 <.L40> - -000001b4 <.L13>: - 1b4: 001b4703 lbu a4,1(s6) - 1b8: 06c00793 li a5,108 - 1bc: f6f716e3 bne a4,a5,128 <.L11> - -000001c0 <.L16>: - 1c0: 003b0513 addi a0,s6,3 - 1c4: 05210023 sb s2,64(sp) - 1c8: 40850533 sub a0,a0,s0 - 1cc: 002b0b13 addi s6,s6,2 - 1d0: f6a046e3 bgtz a0,13c <.L41> - -000001d4 <.L26>: - 1d4: 00100513 li a0,1 - 1d8: f89ff06f j 160 <.L17> - -000001dc <.L39>: - 1dc: 001b4703 lbu a4,1(s6) - 1e0: 02a00793 li a5,42 - 1e4: 00f71a63 bne a4,a5,1f8 <.L9> - 1e8: 002b4783 lbu a5,2(s6) - 1ec: 003b0513 addi a0,s6,3 - 1f0: 002b0b13 addi s6,s6,2 - 1f4: f09ff06f j fc <.L8> - -000001f8 <.L9>: - 1f8: 00a00613 li a2,10 - 1fc: 04010593 addi a1,sp,64 - 200: 00000097 auipc ra,0x0 - 204: 000080e7 jalr ra # 200 <.L9+0x8> - 208: 04012b03 lw s6,64(sp) - 20c: 000b4783 lbu a5,0(s6) - 210: 001b0513 addi a0,s6,1 - 214: ee9ff06f j fc <.L8> - -00000218 <.L25>: - 218: 00100513 li a0,1 - 21c: e59ff06f j 74 <.L1> - -00000220 <.L24>: - 220: fff00513 li a0,-1 - 224: 00008067 ret - -Disassembly of section .rodata.vx_vprintf: - -00000000 <.L12>: - ... - -Disassembly of section .text.vx_printf: - -00000000 : - 0: fc010113 addi sp,sp,-64 - 4: 02410313 addi t1,sp,36 - 8: 02b12223 sw a1,36(sp) - c: 00030593 mv a1,t1 - 10: 00112e23 sw ra,28(sp) - 14: 02c12423 sw a2,40(sp) - 18: 02d12623 sw a3,44(sp) - 1c: 02e12823 sw a4,48(sp) - 20: 02f12a23 sw a5,52(sp) - 24: 03012c23 sw a6,56(sp) - 28: 03112e23 sw a7,60(sp) - 2c: 00612623 sw t1,12(sp) - 30: 00000097 auipc ra,0x0 - 34: 000080e7 jalr ra # 30 - 38: 01c12083 lw ra,28(sp) - 3c: 04010113 addi sp,sp,64 - 40: 00008067 ret - -Disassembly of section .text.vx_prints: - -00000000 : - 0: ff010113 addi sp,sp,-16 - 4: 00812423 sw s0,8(sp) - 8: 00112623 sw ra,12(sp) - c: 00050413 mv s0,a0 - 10: 00054503 lbu a0,0(a0) - 14: 00050e63 beqz a0,30 <.L44> - 18: 00140413 addi s0,s0,1 - -0000001c <.L46>: - 1c: 00140413 addi s0,s0,1 - 20: 00000097 auipc ra,0x0 - 24: 000080e7 jalr ra # 20 <.L46+0x4> - 28: fff44503 lbu a0,-1(s0) - 2c: fe0518e3 bnez a0,1c <.L46> - -00000030 <.L44>: - 30: 00c12083 lw ra,12(sp) - 34: 00812403 lw s0,8(sp) - 38: 01010113 addi sp,sp,16 - 3c: 00008067 ret - -Disassembly of section .text.vx_printx: - -00000000 : - 0: ff010113 addi sp,sp,-16 - 4: 00912223 sw s1,4(sp) - 8: 00112623 sw ra,12(sp) - c: 00812423 sw s0,8(sp) - 10: 01212023 sw s2,0(sp) - 14: 00f00793 li a5,15 - 18: 00050493 mv s1,a0 - 1c: 06a7f063 bgeu a5,a0,7c <.L63> - 20: 00000937 lui s2,0x0 - 24: 00000693 li a3,0 - 28: 02000413 li s0,32 - 2c: 00090913 mv s2,s2 - -00000030 <.L53>: - 30: ffc40413 addi s0,s0,-4 - 34: 0084d7b3 srl a5,s1,s0 - 38: 00f7f793 andi a5,a5,15 - 3c: 00f90733 add a4,s2,a5 - 40: 00079463 bnez a5,48 <.L55> - 44: 00068a63 beqz a3,58 <.L56> - -00000048 <.L55>: - 48: 00074503 lbu a0,0(a4) - 4c: 00000097 auipc ra,0x0 - 50: 000080e7 jalr ra # 4c <.L55+0x4> - 54: 00100693 li a3,1 - -00000058 <.L56>: - 58: fc041ce3 bnez s0,30 <.L53> - 5c: 00812403 lw s0,8(sp) - 60: 00c12083 lw ra,12(sp) - 64: 00412483 lw s1,4(sp) - 68: 00012903 lw s2,0(sp) - 6c: 00a00513 li a0,10 - 70: 01010113 addi sp,sp,16 - 74: 00000317 auipc t1,0x0 - 78: 00030067 jr t1 # 74 <.L56+0x1c> - -0000007c <.L63>: - 7c: 000007b7 lui a5,0x0 - 80: 00078793 mv a5,a5 - 84: 00a784b3 add s1,a5,a0 - 88: 0004c503 lbu a0,0(s1) - 8c: 00000097 auipc ra,0x0 - 90: 000080e7 jalr ra # 8c <.L63+0x10> - 94: 00812403 lw s0,8(sp) - 98: 00c12083 lw ra,12(sp) - 9c: 00412483 lw s1,4(sp) - a0: 00012903 lw s2,0(sp) - a4: 00a00513 li a0,10 - a8: 01010113 addi sp,sp,16 - ac: 00000317 auipc t1,0x0 - b0: 00030067 jr t1 # ac <.L63+0x30> - -Disassembly of section .text.vx_printv: - -00000000 : - 0: ff010113 addi sp,sp,-16 - 4: 00812423 sw s0,8(sp) - 8: 00912223 sw s1,4(sp) - c: 00112623 sw ra,12(sp) - 10: 01212023 sw s2,0(sp) - 14: 00050413 mv s0,a0 - 18: 00054503 lbu a0,0(a0) - 1c: 00058493 mv s1,a1 - 20: 00050e63 beqz a0,3c <.L66> - 24: 00140413 addi s0,s0,1 - -00000028 <.L67>: - 28: 00140413 addi s0,s0,1 - 2c: 00000097 auipc ra,0x0 - 30: 000080e7 jalr ra # 2c <.L67+0x4> - 34: fff44503 lbu a0,-1(s0) - 38: fe0518e3 bnez a0,28 <.L67> - -0000003c <.L66>: - 3c: 00f00793 li a5,15 - 40: 00000693 li a3,0 - 44: 02000413 li s0,32 - 48: 0497fc63 bgeu a5,s1,a0 <.L82> - 4c: 00000937 lui s2,0x0 - 50: 00090913 mv s2,s2 - -00000054 <.L68>: - 54: ffc40413 addi s0,s0,-4 - 58: 0084d7b3 srl a5,s1,s0 - 5c: 00f7f793 andi a5,a5,15 - 60: 00f90733 add a4,s2,a5 - 64: 00079463 bnez a5,6c <.L70> - 68: 00068a63 beqz a3,7c <.L71> - -0000006c <.L70>: - 6c: 00074503 lbu a0,0(a4) - 70: 00000097 auipc ra,0x0 - 74: 000080e7 jalr ra # 70 <.L70+0x4> - 78: 00100693 li a3,1 - -0000007c <.L71>: - 7c: fc041ce3 bnez s0,54 <.L68> - 80: 00812403 lw s0,8(sp) - 84: 00c12083 lw ra,12(sp) - 88: 00412483 lw s1,4(sp) - 8c: 00012903 lw s2,0(sp) - 90: 00a00513 li a0,10 - 94: 01010113 addi sp,sp,16 - 98: 00000317 auipc t1,0x0 - 9c: 00030067 jr t1 # 98 <.L71+0x1c> - -000000a0 <.L82>: - a0: 000007b7 lui a5,0x0 - a4: 00078793 mv a5,a5 - a8: 009784b3 add s1,a5,s1 - ac: 0004c503 lbu a0,0(s1) - b0: 00000097 auipc ra,0x0 - b4: 000080e7 jalr ra # b0 <.L82+0x10> - b8: 00812403 lw s0,8(sp) - bc: 00c12083 lw ra,12(sp) - c0: 00412483 lw s1,4(sp) - c4: 00012903 lw s2,0(sp) - c8: 00a00513 li a0,10 - cc: 01010113 addi sp,sp,16 - d0: 00000317 auipc t1,0x0 - d4: 00030067 jr t1 # d0 <.L82+0x30> - -Disassembly of section .rodata.hextoa: - -00000000 : - 0: 3130 fld fa2,96(a0) - 2: 3332 fld ft6,296(sp) - 4: 3534 fld fa3,104(a0) - 6: 3736 fld fa4,360(sp) - 8: 3938 fld fa4,112(a0) - a: 6261 lui tp,0x18 - c: 66656463 bltu a0,t1,674 <.L24+0x454> - ... - -Disassembly of section .comment: - -00000000 <.comment>: - 0: 4700 lw s0,8(a4) - 2: 203a4343 fmadd.s ft6,fs4,ft3,ft4,rmm - 6: 4728 lw a0,72(a4) - 8: 554e lw a0,240(sp) - a: 2029 jal 14 - c: 2e39 jal 32a <.L24+0x10a> - e: 2e32 fld ft8,264(sp) - 10: 0030 addi a2,sp,8 - -Disassembly of section .riscv.attributes: - -00000000 <.riscv.attributes>: - 0: 2541 jal 680 <.L24+0x460> - 2: 0000 unimp - 4: 7200 flw fs0,32(a2) - 6: 7369 lui t1,0xffffa - 8: 01007663 bgeu zero,a6,14 <.riscv.attributes+0x14> - c: 0000001b 0x1b - 10: 1004 addi s1,sp,32 - 12: 7205 lui tp,0xfffe1 - 14: 3376 fld ft6,376(sp) - 16: 6932 flw fs2,12(sp) - 18: 7032 flw ft0,44(sp) - 1a: 5f30 lw a2,120(a4) - 1c: 326d jal fffff9c6 <.L24+0xfffff7a6> - 1e: 3070 fld fa2,224(s0) - 20: 665f 7032 0030 0x307032665f - -vx_spawn.c.o: file format elf32-littleriscv - - -Disassembly of section .text.spawn_tasks_callback: - -00000000 : - 0: fe010113 addi sp,sp,-32 - 4: 00112e23 sw ra,28(sp) - 8: 00812c23 sw s0,24(sp) - c: 00912a23 sw s1,20(sp) - 10: 01212823 sw s2,16(sp) - 14: 01312623 sw s3,12(sp) - 18: fc0027f3 csrr a5,0xfc0 - 1c: 0007806b 0x7806b - 20: cc5026f3 csrr a3,0xcc5 - 24: cc3029f3 csrr s3,0xcc3 - 28: cc002773 csrr a4,0xcc0 - 2c: fc002673 csrr a2,0xfc0 - 30: 000007b7 lui a5,0x0 - 34: 00269693 slli a3,a3,0x2 - 38: 00078793 mv a5,a5 - 3c: 00d787b3 add a5,a5,a3 - 40: 0007a483 lw s1,0(a5) # 0 - 44: 0104a403 lw s0,16(s1) - 48: 00c4a683 lw a3,12(s1) - 4c: 0089a933 slt s2,s3,s0 - 50: 00040793 mv a5,s0 - 54: 00d90933 add s2,s2,a3 - 58: 03368433 mul s0,a3,s3 - 5c: 00f9d463 bge s3,a5,64 <.L2> - 60: 00098793 mv a5,s3 - -00000064 <.L2>: - 64: 00f40433 add s0,s0,a5 - 68: 0084a683 lw a3,8(s1) - 6c: 02c40433 mul s0,s0,a2 - 70: 02e907b3 mul a5,s2,a4 - 74: 00d40433 add s0,s0,a3 - 78: 00f40433 add s0,s0,a5 - 7c: 00890933 add s2,s2,s0 - 80: 01245e63 bge s0,s2,9c <.L3> - -00000084 <.L4>: - 84: 0004a783 lw a5,0(s1) - 88: 0044a583 lw a1,4(s1) - 8c: 00040513 mv a0,s0 - 90: 00140413 addi s0,s0,1 - 94: 000780e7 jalr a5 - 98: fe8916e3 bne s2,s0,84 <.L4> - -0000009c <.L3>: - 9c: 0019b993 seqz s3,s3 - a0: 0009806b 0x9806b - a4: 01c12083 lw ra,28(sp) - a8: 01812403 lw s0,24(sp) - ac: 01412483 lw s1,20(sp) - b0: 01012903 lw s2,16(sp) - b4: 00c12983 lw s3,12(sp) - b8: 02010113 addi sp,sp,32 - bc: 00008067 ret - -Disassembly of section .text.spawn_kernel_callback: - -00000000 : - 0: fe010113 addi sp,sp,-32 - 4: 00112e23 sw ra,28(sp) - 8: 00812c23 sw s0,24(sp) - c: 00912a23 sw s1,20(sp) - 10: 01212823 sw s2,16(sp) - 14: 01312623 sw s3,12(sp) - 18: 01412423 sw s4,8(sp) - 1c: 01512223 sw s5,4(sp) - 20: fc0027f3 csrr a5,0xfc0 - 24: 0007806b 0x7806b - 28: cc5026f3 csrr a3,0xcc5 - 2c: cc302973 csrr s2,0xcc3 - 30: cc002773 csrr a4,0xcc0 - 34: fc002673 csrr a2,0xfc0 - 38: 000007b7 lui a5,0x0 - 3c: 00269693 slli a3,a3,0x2 - 40: 00078793 mv a5,a5 - 44: 00d787b3 add a5,a5,a3 - 48: 0007a403 lw s0,0(a5) # 0 - 4c: 01442483 lw s1,20(s0) - 50: 01042683 lw a3,16(s0) - 54: 00992ab3 slt s5,s2,s1 - 58: 00048793 mv a5,s1 - 5c: 00da8ab3 add s5,s5,a3 - 60: 032684b3 mul s1,a3,s2 - 64: 00f95463 bge s2,a5,6c <.L9> - 68: 00090793 mv a5,s2 - -0000006c <.L9>: - 6c: 00f484b3 add s1,s1,a5 - 70: 00042583 lw a1,0(s0) - 74: 00c42683 lw a3,12(s0) - 78: 0005a983 lw s3,0(a1) - 7c: 0045aa03 lw s4,4(a1) - 80: 02c484b3 mul s1,s1,a2 - 84: 02ea87b3 mul a5,s5,a4 - 88: 00d484b3 add s1,s1,a3 - 8c: 00f484b3 add s1,s1,a5 - 90: 009a8ab3 add s5,s5,s1 - 94: 03498a33 mul s4,s3,s4 - 98: 0754c063 blt s1,s5,f8 <.L15> - 9c: 0800006f j 11c <.L10> - -000000a0 <.L17>: - a0: 01a44703 lbu a4,26(s0) - a4: 01944683 lbu a3,25(s0) - a8: 40e4d733 sra a4,s1,a4 - ac: 034707b3 mul a5,a4,s4 - b0: 40f487b3 sub a5,s1,a5 - b4: 06068063 beqz a3,114 <.L13> - -000000b8 <.L18>: - b8: 01b44683 lbu a3,27(s0) - bc: 40d7d6b3 sra a3,a5,a3 - -000000c0 <.L14>: - c0: 033688b3 mul a7,a3,s3 - c4: 0145ae03 lw t3,20(a1) - c8: 0105a303 lw t1,16(a1) - cc: 00c5a603 lw a2,12(a1) - d0: 00442803 lw a6,4(s0) - d4: 00842503 lw a0,8(s0) - d8: 00148493 addi s1,s1,1 - dc: 01c70733 add a4,a4,t3 - e0: 006686b3 add a3,a3,t1 - e4: 411787b3 sub a5,a5,a7 - e8: 00c78633 add a2,a5,a2 - ec: 000800e7 jalr a6 - f0: 029a8663 beq s5,s1,11c <.L10> - f4: 00042583 lw a1,0(s0) - -000000f8 <.L15>: - f8: 01844783 lbu a5,24(s0) - fc: fa0792e3 bnez a5,a0 <.L17> - 100: 0344c733 div a4,s1,s4 - 104: 01944683 lbu a3,25(s0) - 108: 034707b3 mul a5,a4,s4 - 10c: 40f487b3 sub a5,s1,a5 - 110: fa0694e3 bnez a3,b8 <.L18> - -00000114 <.L13>: - 114: 0337c6b3 div a3,a5,s3 - 118: fa9ff06f j c0 <.L14> - -0000011c <.L10>: - 11c: 00193913 seqz s2,s2 - 120: 0009006b 0x9006b - 124: 01c12083 lw ra,28(sp) - 128: 01812403 lw s0,24(sp) - 12c: 01412483 lw s1,20(sp) - 130: 01012903 lw s2,16(sp) - 134: 00c12983 lw s3,12(sp) - 138: 00812a03 lw s4,8(sp) - 13c: 00412a83 lw s5,4(sp) - 140: 02010113 addi sp,sp,32 - 144: 00008067 ret - -Disassembly of section .text.spawn_remaining_tasks_callback: - -00000000 : - 0: ff010113 addi sp,sp,-16 - 4: 00112623 sw ra,12(sp) - 8: 0005006b 0x5006b - c: cc502773 csrr a4,0xcc5 - 10: cc202573 csrr a0,0xcc2 - 14: 000007b7 lui a5,0x0 - 18: 00271713 slli a4,a4,0x2 - 1c: 00078793 mv a5,a5 - 20: 00e787b3 add a5,a5,a4 - 24: 0007a783 lw a5,0(a5) # 0 - 28: 0087a683 lw a3,8(a5) - 2c: 0007a703 lw a4,0(a5) - 30: 0047a583 lw a1,4(a5) - 34: 00d50533 add a0,a0,a3 - 38: 000700e7 jalr a4 - 3c: 00100793 li a5,1 - 40: 0007806b 0x7806b - 44: 00c12083 lw ra,12(sp) - 48: 01010113 addi sp,sp,16 - 4c: 00008067 ret - -Disassembly of section .text.vx_spawn_tasks: - -00000000 : - 0: fc010113 addi sp,sp,-64 - 4: 02112e23 sw ra,60(sp) - 8: 02812c23 sw s0,56(sp) - c: 02912a23 sw s1,52(sp) - 10: 03212823 sw s2,48(sp) - 14: 03312623 sw s3,44(sp) - 18: fc2026f3 csrr a3,0xfc2 - 1c: fc102873 csrr a6,0xfc1 - 20: fc002473 csrr s0,0xfc0 - 24: cc5027f3 csrr a5,0xcc5 - 28: 01f00713 li a4,31 - 2c: 0cf74463 blt a4,a5,f4 <.L21> - 30: 030408b3 mul a7,s0,a6 - 34: 00100713 li a4,1 - 38: 00a8d463 bge a7,a0,40 <.L23> - 3c: 03154733 div a4,a0,a7 - -00000040 <.L23>: - 40: 0ce6c863 blt a3,a4,110 <.L39> - 44: 0ae7d863 bge a5,a4,f4 <.L21> - -00000048 <.L41>: - 48: fff68693 addi a3,a3,-1 - 4c: 02e54333 div t1,a0,a4 - 50: 00030893 mv a7,t1 - 54: 00f69663 bne a3,a5,60 <.L25> - 58: 02e56533 rem a0,a0,a4 - 5c: 006508b3 add a7,a0,t1 - -00000060 <.L25>: - 60: 0288c4b3 div s1,a7,s0 - 64: 0288e933 rem s2,a7,s0 - 68: 0b04ca63 blt s1,a6,11c <.L32> - 6c: 00100693 li a3,1 - 70: 0304c733 div a4,s1,a6 - 74: 00070663 beqz a4,80 <.L26> - 78: 00070693 mv a3,a4 - 7c: 0304e733 rem a4,s1,a6 - -00000080 <.L26>: - 80: 000009b7 lui s3,0x0 - 84: 00098993 mv s3,s3 - 88: 00e12e23 sw a4,28(sp) - 8c: 00c10713 addi a4,sp,12 - 90: 00b12623 sw a1,12(sp) - 94: 00c12823 sw a2,16(sp) - 98: 00d12c23 sw a3,24(sp) - 9c: 02f30333 mul t1,t1,a5 - a0: 00279793 slli a5,a5,0x2 - a4: 00f987b3 add a5,s3,a5 - a8: 00e7a023 sw a4,0(a5) - ac: 00612a23 sw t1,20(sp) - b0: 06904c63 bgtz s1,128 <.L40> - -000000b4 <.L27>: - b4: 04090063 beqz s2,f4 <.L21> - b8: 02848433 mul s0,s1,s0 - bc: 00812a23 sw s0,20(sp) - c0: 0009006b 0x9006b - c4: cc5027f3 csrr a5,0xcc5 - c8: cc202573 csrr a0,0xcc2 - cc: 00279793 slli a5,a5,0x2 - d0: 00f989b3 add s3,s3,a5 - d4: 0009a783 lw a5,0(s3) # 0 - d8: 0087a683 lw a3,8(a5) - dc: 0007a703 lw a4,0(a5) - e0: 0047a583 lw a1,4(a5) - e4: 00d50533 add a0,a0,a3 - e8: 000700e7 jalr a4 - ec: 00100793 li a5,1 - f0: 0007806b 0x7806b - -000000f4 <.L21>: - f4: 03c12083 lw ra,60(sp) - f8: 03812403 lw s0,56(sp) - fc: 03412483 lw s1,52(sp) - 100: 03012903 lw s2,48(sp) - 104: 02c12983 lw s3,44(sp) - 108: 04010113 addi sp,sp,64 - 10c: 00008067 ret - -00000110 <.L39>: - 110: 00068713 mv a4,a3 - 114: f2e7cae3 blt a5,a4,48 <.L41> - 118: fddff06f j f4 <.L21> - -0000011c <.L32>: - 11c: 00000713 li a4,0 - 120: 00100693 li a3,1 - 124: f5dff06f j 80 <.L26> - -00000128 <.L40>: - 128: 00048713 mv a4,s1 - 12c: 00985463 bge a6,s1,134 <.L28> - 130: 00080713 mv a4,a6 - -00000134 <.L28>: - 134: 000007b7 lui a5,0x0 - 138: 00078793 mv a5,a5 - 13c: 00f7106b 0xf7106b - 140: 00000097 auipc ra,0x0 - 144: 000080e7 jalr ra # 140 <.L28+0xc> - 148: f6dff06f j b4 <.L27> - -Disassembly of section .text.vx_spawn_kernel: - -00000000 : - 0: fc010113 addi sp,sp,-64 - 4: 02112e23 sw ra,60(sp) - 8: 02812c23 sw s0,56(sp) - c: 02912a23 sw s1,52(sp) - 10: 03212823 sw s2,48(sp) - 14: 03312623 sw s3,44(sp) - 18: fc2028f3 csrr a7,0xfc2 - 1c: fc102373 csrr t1,0xfc1 - 20: fc002473 csrr s0,0xfc0 - 24: cc5027f3 csrr a5,0xcc5 - 28: 01f00713 li a4,31 - 2c: 0ef74663 blt a4,a5,118 <.L42> - 30: 00052e03 lw t3,0(a0) - 34: 00452683 lw a3,4(a0) - 38: 00852803 lw a6,8(a0) - 3c: 02830eb3 mul t4,t1,s0 - 40: 00100713 li a4,1 - 44: 02de06b3 mul a3,t3,a3 - 48: 03068833 mul a6,a3,a6 - 4c: 010ed463 bge t4,a6,54 <.L44> - 50: 03d84733 div a4,a6,t4 - -00000054 <.L44>: - 54: 0ee8c063 blt a7,a4,134 <.L64> - 58: 0ce7d063 bge a5,a4,118 <.L42> - -0000005c <.L67>: - 5c: fff88893 addi a7,a7,-1 - 60: 02e84eb3 div t4,a6,a4 - 64: 000e8493 mv s1,t4 - 68: 00f89663 bne a7,a5,74 <.L46> - 6c: 02e86733 rem a4,a6,a4 - 70: 01d704b3 add s1,a4,t4 - -00000074 <.L46>: - 74: 0284c933 div s2,s1,s0 - 78: 0284e4b3 rem s1,s1,s0 - 7c: 0c694263 blt s2,t1,140 <.L57> - 80: 00100293 li t0,1 - 84: 02694833 div a6,s2,t1 - 88: 00080663 beqz a6,94 <.L47> - 8c: 00080293 mv t0,a6 - 90: 02696833 rem a6,s2,t1 - -00000094 <.L47>: - 94: d006f7d3 fcvt.s.w fa5,a3 - 98: fff68f93 addi t6,a3,-1 - 9c: fffe0f13 addi t5,t3,-1 - a0: 000009b7 lui s3,0x0 - a4: 00dff6b3 and a3,t6,a3 - a8: 00098993 mv s3,s3 - ac: 0016b693 seqz a3,a3 - b0: 00a12223 sw a0,4(sp) - b4: 00b12423 sw a1,8(sp) - b8: 00c12623 sw a2,12(sp) - bc: 00512a23 sw t0,20(sp) - c0: 01012c23 sw a6,24(sp) - c4: 00d10e23 sb a3,28(sp) - c8: 02fe8733 mul a4,t4,a5 - cc: e0078ed3 fmv.x.w t4,fa5 - d0: d00e77d3 fcvt.s.w fa5,t3 - d4: 00279793 slli a5,a5,0x2 - d8: 01cf7e33 and t3,t5,t3 - dc: e00788d3 fmv.x.w a7,fa5 - e0: 417ede93 srai t4,t4,0x17 - e4: 001e3e13 seqz t3,t3 - e8: 4178d893 srai a7,a7,0x17 - ec: f81e8e93 addi t4,t4,-127 - f0: f8188893 addi a7,a7,-127 - f4: 00f987b3 add a5,s3,a5 - f8: 00e12823 sw a4,16(sp) - fc: 00410713 addi a4,sp,4 - 100: 01c10ea3 sb t3,29(sp) - 104: 01d10f23 sb t4,30(sp) - 108: 01110fa3 sb a7,31(sp) - 10c: 00e7a023 sw a4,0(a5) # 0 - 110: 03204e63 bgtz s2,14c <.L65> - 114: 04049e63 bnez s1,170 <.L66> - -00000118 <.L42>: - 118: 03c12083 lw ra,60(sp) - 11c: 03812403 lw s0,56(sp) - 120: 03412483 lw s1,52(sp) - 124: 03012903 lw s2,48(sp) - 128: 02c12983 lw s3,44(sp) - 12c: 04010113 addi sp,sp,64 - 130: 00008067 ret - -00000134 <.L64>: - 134: 00088713 mv a4,a7 - 138: f2e7c2e3 blt a5,a4,5c <.L67> - 13c: fddff06f j 118 <.L42> - -00000140 <.L57>: - 140: 00000813 li a6,0 - 144: 00100293 li t0,1 - 148: f4dff06f j 94 <.L47> - -0000014c <.L65>: - 14c: 00090713 mv a4,s2 - 150: 01235463 bge t1,s2,158 <.L49> - 154: 00030713 mv a4,t1 - -00000158 <.L49>: - 158: 000007b7 lui a5,0x0 - 15c: 00078793 mv a5,a5 - 160: 00f7106b 0xf7106b - 164: 00000097 auipc ra,0x0 - 168: 000080e7 jalr ra # 164 <.L49+0xc> - 16c: fa0486e3 beqz s1,118 <.L42> - -00000170 <.L66>: - 170: 02890433 mul s0,s2,s0 - 174: 00812823 sw s0,16(sp) - 178: 0004806b 0x4806b - 17c: cc502773 csrr a4,0xcc5 - 180: cc2027f3 csrr a5,0xcc2 - 184: 00271713 slli a4,a4,0x2 - 188: 00e989b3 add s3,s3,a4 - 18c: 0009a503 lw a0,0(s3) # 0 - 190: 00052583 lw a1,0(a0) - 194: 00c52683 lw a3,12(a0) - 198: 01854703 lbu a4,24(a0) - 19c: 0005a803 lw a6,0(a1) - 1a0: 0045a603 lw a2,4(a1) - 1a4: 00d787b3 add a5,a5,a3 - 1a8: 02c80633 mul a2,a6,a2 - 1ac: 06070e63 beqz a4,228 <.L50> - 1b0: 01a54703 lbu a4,26(a0) - 1b4: 40e7d733 sra a4,a5,a4 - -000001b8 <.L51>: - 1b8: 01954683 lbu a3,25(a0) - 1bc: 02e60633 mul a2,a2,a4 - 1c0: 40c787b3 sub a5,a5,a2 - 1c4: 04068e63 beqz a3,220 <.L52> - 1c8: 01b54883 lbu a7,27(a0) - 1cc: 4117d8b3 sra a7,a5,a7 - -000001d0 <.L53>: - 1d0: 03180833 mul a6,a6,a7 - 1d4: 0145ae03 lw t3,20(a1) - 1d8: 0105a683 lw a3,16(a1) - 1dc: 00c5a603 lw a2,12(a1) - 1e0: 00452303 lw t1,4(a0) - 1e4: 00852503 lw a0,8(a0) - 1e8: 01c70733 add a4,a4,t3 - 1ec: 00d886b3 add a3,a7,a3 - 1f0: 410787b3 sub a5,a5,a6 - 1f4: 00c78633 add a2,a5,a2 - 1f8: 000300e7 jalr t1 - 1fc: 00100793 li a5,1 - 200: 0007806b 0x7806b - 204: 03c12083 lw ra,60(sp) - 208: 03812403 lw s0,56(sp) - 20c: 03412483 lw s1,52(sp) - 210: 03012903 lw s2,48(sp) - 214: 02c12983 lw s3,44(sp) - 218: 04010113 addi sp,sp,64 - 21c: 00008067 ret - -00000220 <.L52>: - 220: 0307c8b3 div a7,a5,a6 - 224: fadff06f j 1d0 <.L53> - -00000228 <.L50>: - 228: 02c7c733 div a4,a5,a2 - 22c: f8dff06f j 1b8 <.L51> - -Disassembly of section .comment: - -00000000 <.comment>: - 0: 4700 lw s0,8(a4) - 2: 203a4343 fmadd.s ft6,fs4,ft3,ft4,rmm - 6: 4728 lw a0,72(a4) - 8: 554e lw a0,240(sp) - a: 2029 jal 14 - c: 2e39 jal 32a <.L50+0x102> - e: 2e32 fld ft8,264(sp) - 10: 0030 addi a2,sp,8 - -Disassembly of section .riscv.attributes: - -00000000 <.riscv.attributes>: - 0: 2541 jal 680 <.L50+0x458> - 2: 0000 unimp - 4: 7200 flw fs0,32(a2) - 6: 7369 lui t1,0xffffa - 8: 01007663 bgeu zero,a6,14 <.riscv.attributes+0x14> - c: 0000001b 0x1b - 10: 1004 addi s1,sp,32 - 12: 7205 lui tp,0xfffe1 - 14: 3376 fld ft6,376(sp) - 16: 6932 flw fs2,12(sp) - 18: 7032 flw ft0,44(sp) - 1a: 5f30 lw a2,120(a4) - 1c: 326d jal fffff9c6 <.L50+0xfffff79e> - 1e: 3070 fld fa2,224(s0) - 20: 665f 7032 0030 0x307032665f - -vx_tex.c.o: file format elf32-littleriscv - - -Disassembly of section .text.vx_tex: - -00000000 : - 0: 00869693 slli a3,a3,0x8 - 4: 00a6e6b3 or a3,a3,a0 - 8: 00000513 li a0,0 - c: 6ac5d56b 0x6ac5d56b - 10: 00008067 ret - -Disassembly of section .comment: - -00000000 <.comment>: - 0: 4700 lw s0,8(a4) - 2: 203a4343 fmadd.s ft6,fs4,ft3,ft4,rmm - 6: 4728 lw a0,72(a4) - 8: 554e lw a0,240(sp) - a: 2029 jal 14 - c: 2e39 jal 32a - e: 2e32 fld ft8,264(sp) - 10: 0030 addi a2,sp,8 - -Disassembly of section .riscv.attributes: - -00000000 <.riscv.attributes>: - 0: 2541 jal 680 - 2: 0000 unimp - 4: 7200 flw fs0,32(a2) - 6: 7369 lui t1,0xffffa - 8: 01007663 bgeu zero,a6,14 - c: 0000001b 0x1b - 10: 1004 addi s1,sp,32 - 12: 7205 lui tp,0xfffe1 - 14: 3376 fld ft6,376(sp) - 16: 6932 flw fs2,12(sp) - 18: 7032 flw ft0,44(sp) - 1a: 5f30 lw a2,120(a4) - 1c: 326d jal fffff9c6 - 1e: 3070 fld fa2,224(s0) - 20: 665f 7032 0030 0x307032665f diff --git a/runtime/vx_print.S.o b/runtime/vx_print.S.o deleted file mode 100644 index fb1c1352..00000000 Binary files a/runtime/vx_print.S.o and /dev/null differ diff --git a/runtime/vx_print.c.o b/runtime/vx_print.c.o deleted file mode 100644 index 809e45b1..00000000 Binary files a/runtime/vx_print.c.o and /dev/null differ diff --git a/runtime/vx_spawn.c.o b/runtime/vx_spawn.c.o deleted file mode 100644 index 57381a4a..00000000 Binary files a/runtime/vx_spawn.c.o and /dev/null differ diff --git a/runtime/vx_start.S.o b/runtime/vx_start.S.o deleted file mode 100644 index f96091b9..00000000 Binary files a/runtime/vx_start.S.o and /dev/null differ diff --git a/runtime/vx_tex.c.o b/runtime/vx_tex.c.o deleted file mode 100644 index 69ffadd0..00000000 Binary files a/runtime/vx_tex.c.o and /dev/null differ diff --git a/simX/simX b/simX/simX deleted file mode 100755 index cd3eb523..00000000 Binary files a/simX/simX and /dev/null differ