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rtl refactoring

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This commit is contained in:
Blaise Tine
2020-05-03 17:10:02 -04:00
parent a1dc90b951
commit 69f607b73e
83 changed files with 30487 additions and 30536 deletions
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6
driver/tests/basic/Makefile
View File

@@ -8,10 +8,10 @@ VX_CPY = $(RISCV_TOOL_PATH)/bin/riscv32-unknown-elf-objcopy
VX_NEWLIB = $(VX_RT_PATH)/newlib/newlib.c
VX_STR = $(VX_RT_PATH)/startup/vx_start.S
VX_INT = $(VX_RT_PATH)/intrinsics/vx_intrinsics.s
VX_IO = $(VX_RT_PATH)/io/vx_io.s $(VX_RT_PATH)/io/vx_io.c
VX_INT = $(VX_RT_PATH)/intrinsics/vx_intrinsics.S
VX_IO = $(VX_RT_PATH)/io/vx_io.S $(VX_RT_PATH)/io/vx_io.c
VX_API = $(VX_RT_PATH)/vx_api/vx_api.c
VX_FIO = $(VX_RT_PATH)/fileio/fileio.s
VX_FIO = $(VX_RT_PATH)/fileio/fileio.S
VX_CFLAGS = -march=rv32im -mabi=ilp32 -O3 -Wl,-Bstatic,-T,$(VX_RT_PATH)/startup/vx_link.ld -ffreestanding -nostartfiles -Wl,--gc-sections

6
driver/tests/demo/Makefile
View File

@@ -8,10 +8,10 @@ VX_CPY = $(RISCV_TOOL_PATH)/bin/riscv32-unknown-elf-objcopy
VX_NEWLIB = $(VX_RT_PATH)/newlib/newlib.c
VX_STR = $(VX_RT_PATH)/startup/vx_start.S
VX_INT = $(VX_RT_PATH)/intrinsics/vx_intrinsics.s
VX_IO = $(VX_RT_PATH)/io/vx_io.s $(VX_RT_PATH)/io/vx_io.c
VX_INT = $(VX_RT_PATH)/intrinsics/vx_intrinsics.S
VX_IO = $(VX_RT_PATH)/io/vx_io.S $(VX_RT_PATH)/io/vx_io.c
VX_API = $(VX_RT_PATH)/vx_api/vx_api.c
VX_FIO = $(VX_RT_PATH)/fileio/fileio.s
VX_FIO = $(VX_RT_PATH)/fileio/fileio.S
VX_CFLAGS = -march=rv32im -mabi=ilp32 -O3 -Wl,-Bstatic,-T,$(VX_RT_PATH)/startup/vx_link.ld -ffreestanding -nostartfiles -Wl,--gc-sections

8
driver/tests/demo/kernel.c
View File

@@ -10,10 +10,10 @@ void kernel_body(void* arg) {
int* y = (int*)_arg->src1_ptr;
int* z = (int*)_arg->dst_ptr;
unsigned wNo = vx_warpNum();
unsigned tid = vx_threadID();
unsigned wid = vx_warp_gid();
unsigned tid = vx_thread_id();
unsigned i = ((wNo * _arg->num_threads) + tid) * _arg->stride;
unsigned i = ((wid * _arg->num_threads) + tid) * _arg->stride;
for (unsigned j = 0; j < _arg->stride; ++j) {
z[i+j] = x[i+j] + y[i+j];
@@ -28,5 +28,5 @@ void main() {
printf("src0_ptr=0x%x\n", arg->src0_ptr);
printf("src1_ptr=0x%x\n", arg->src1_ptr);
printf("dst_ptr=0x%x\n", arg->dst_ptr);*/
vx_spawnWarps(arg->num_warps, arg->num_threads, kernel_body, arg);
vx_spawn_warps(arg->num_warps, arg->num_threads, kernel_body, arg);
}

128
driver/tests/demo/run.log
View File

@@ -1730,13 +1730,13 @@ DEBUG ../../../../simX/core.cpp:176: stalled warps: 0 0 0 0
DEBUG ../../../../simX/core.cpp:750: current PC=0x80000094
DEBUG ../../../../simX/enc.cpp:324: Decoded instr 0x2002673 into: SYS
DEBUG ../../../../simX/instruction.cpp:781: SYS_INST: r12 <- r0, imm=32
DEBUG ../../../../simX/instruction.cpp:788: vx_threadID: r12=0
DEBUG ../../../../simX/instruction.cpp:788: vx_thread_id: r12=0
DEBUG ../../../../simX/instruction.cpp:781: SYS_INST: r12 <- r0, imm=32
DEBUG ../../../../simX/instruction.cpp:788: vx_threadID: r12=1
DEBUG ../../../../simX/instruction.cpp:788: vx_thread_id: r12=1
DEBUG ../../../../simX/instruction.cpp:781: SYS_INST: r12 <- r0, imm=32
DEBUG ../../../../simX/instruction.cpp:788: vx_threadID: r12=2
DEBUG ../../../../simX/instruction.cpp:788: vx_thread_id: r12=2
DEBUG ../../../../simX/instruction.cpp:781: SYS_INST: r12 <- r0, imm=32
DEBUG ../../../../simX/instruction.cpp:788: vx_threadID: r12=3
DEBUG ../../../../simX/instruction.cpp:788: vx_thread_id: r12=3
DEBUG ../../../../simX/core.cpp:781: Register state:
%r 0: 00000000 00000000 00000000 00000000 (0)
%r 1: 00000000 00000000 00000000 00000000 (0)
@@ -1789,13 +1789,13 @@ DEBUG ../../../../simX/core.cpp:176: stalled warps: 0 0 0 0
DEBUG ../../../../simX/core.cpp:750: current PC=0x80000094
DEBUG ../../../../simX/enc.cpp:324: Decoded instr 0x2002673 into: SYS
DEBUG ../../../../simX/instruction.cpp:781: SYS_INST: r12 <- r0, imm=32
DEBUG ../../../../simX/instruction.cpp:788: vx_threadID: r12=0
DEBUG ../../../../simX/instruction.cpp:788: vx_thread_id: r12=0
DEBUG ../../../../simX/instruction.cpp:781: SYS_INST: r12 <- r0, imm=32
DEBUG ../../../../simX/instruction.cpp:788: vx_threadID: r12=1
DEBUG ../../../../simX/instruction.cpp:788: vx_thread_id: r12=1
DEBUG ../../../../simX/instruction.cpp:781: SYS_INST: r12 <- r0, imm=32
DEBUG ../../../../simX/instruction.cpp:788: vx_threadID: r12=2
DEBUG ../../../../simX/instruction.cpp:788: vx_thread_id: r12=2
DEBUG ../../../../simX/instruction.cpp:781: SYS_INST: r12 <- r0, imm=32
DEBUG ../../../../simX/instruction.cpp:788: vx_threadID: r12=3
DEBUG ../../../../simX/instruction.cpp:788: vx_thread_id: r12=3
DEBUG ../../../../simX/core.cpp:781: Register state:
%r 0: 00000000 00000000 00000000 00000000 (0)
%r 1: 00000000 00000000 00000000 00000000 (0)
@@ -1848,13 +1848,13 @@ DEBUG ../../../../simX/core.cpp:176: stalled warps: 0 0 0 0
DEBUG ../../../../simX/core.cpp:750: current PC=0x80000094
DEBUG ../../../../simX/enc.cpp:324: Decoded instr 0x2002673 into: SYS
DEBUG ../../../../simX/instruction.cpp:781: SYS_INST: r12 <- r0, imm=32
DEBUG ../../../../simX/instruction.cpp:788: vx_threadID: r12=0
DEBUG ../../../../simX/instruction.cpp:788: vx_thread_id: r12=0
DEBUG ../../../../simX/instruction.cpp:781: SYS_INST: r12 <- r0, imm=32
DEBUG ../../../../simX/instruction.cpp:788: vx_threadID: r12=1
DEBUG ../../../../simX/instruction.cpp:788: vx_thread_id: r12=1
DEBUG ../../../../simX/instruction.cpp:781: SYS_INST: r12 <- r0, imm=32
DEBUG ../../../../simX/instruction.cpp:788: vx_threadID: r12=2
DEBUG ../../../../simX/instruction.cpp:788: vx_thread_id: r12=2
DEBUG ../../../../simX/instruction.cpp:781: SYS_INST: r12 <- r0, imm=32
DEBUG ../../../../simX/instruction.cpp:788: vx_threadID: r12=3
DEBUG ../../../../simX/instruction.cpp:788: vx_thread_id: r12=3
DEBUG ../../../../simX/core.cpp:781: Register state:
%r 0: 00000000 00000000 00000000 00000000 (0)
%r 1: 00000000 00000000 00000000 00000000 (0)
@@ -2127,13 +2127,13 @@ DEBUG ../../../../simX/core.cpp:176: stalled warps: 0 0 0 0
DEBUG ../../../../simX/core.cpp:750: current PC=0x80000094
DEBUG ../../../../simX/enc.cpp:324: Decoded instr 0x2002673 into: SYS
DEBUG ../../../../simX/instruction.cpp:781: SYS_INST: r12 <- r0, imm=32
DEBUG ../../../../simX/instruction.cpp:788: vx_threadID: r12=0
DEBUG ../../../../simX/instruction.cpp:788: vx_thread_id: r12=0
DEBUG ../../../../simX/instruction.cpp:781: SYS_INST: r12 <- r0, imm=32
DEBUG ../../../../simX/instruction.cpp:788: vx_threadID: r12=1
DEBUG ../../../../simX/instruction.cpp:788: vx_thread_id: r12=1
DEBUG ../../../../simX/instruction.cpp:781: SYS_INST: r12 <- r0, imm=32
DEBUG ../../../../simX/instruction.cpp:788: vx_threadID: r12=2
DEBUG ../../../../simX/instruction.cpp:788: vx_thread_id: r12=2
DEBUG ../../../../simX/instruction.cpp:781: SYS_INST: r12 <- r0, imm=32
DEBUG ../../../../simX/instruction.cpp:788: vx_threadID: r12=3
DEBUG ../../../../simX/instruction.cpp:788: vx_thread_id: r12=3
DEBUG ../../../../simX/core.cpp:781: Register state:
%r 0: 00000000 00000000 00000000 00000000 (0)
%r 1: 80000014 00000000 00000000 00000000 (0)
@@ -3286,13 +3286,13 @@ DEBUG ../../../../simX/core.cpp:176: stalled warps: 0 0 0 0
DEBUG ../../../../simX/core.cpp:750: current PC=0x800000b0
DEBUG ../../../../simX/enc.cpp:324: Decoded instr 0x21026f3 into: SYS
DEBUG ../../../../simX/instruction.cpp:781: SYS_INST: r13 <- r0, imm=33
DEBUG ../../../../simX/instruction.cpp:792: vx_warpID: r13=1
DEBUG ../../../../simX/instruction.cpp:792: vx_warp_id: r13=1
DEBUG ../../../../simX/instruction.cpp:781: SYS_INST: r13 <- r0, imm=33
DEBUG ../../../../simX/instruction.cpp:792: vx_warpID: r13=1
DEBUG ../../../../simX/instruction.cpp:792: vx_warp_id: r13=1
DEBUG ../../../../simX/instruction.cpp:781: SYS_INST: r13 <- r0, imm=33
DEBUG ../../../../simX/instruction.cpp:792: vx_warpID: r13=1
DEBUG ../../../../simX/instruction.cpp:792: vx_warp_id: r13=1
DEBUG ../../../../simX/instruction.cpp:781: SYS_INST: r13 <- r0, imm=33
DEBUG ../../../../simX/instruction.cpp:792: vx_warpID: r13=1
DEBUG ../../../../simX/instruction.cpp:792: vx_warp_id: r13=1
DEBUG ../../../../simX/core.cpp:781: Register state:
%r 0: 00000000 00000000 00000000 00000000 (0)
%r 1: 00000000 00000000 00000000 00000000 (0)
@@ -3345,13 +3345,13 @@ DEBUG ../../../../simX/core.cpp:176: stalled warps: 0 0 0 0
DEBUG ../../../../simX/core.cpp:750: current PC=0x800000b0
DEBUG ../../../../simX/enc.cpp:324: Decoded instr 0x21026f3 into: SYS
DEBUG ../../../../simX/instruction.cpp:781: SYS_INST: r13 <- r0, imm=33
DEBUG ../../../../simX/instruction.cpp:792: vx_warpID: r13=2
DEBUG ../../../../simX/instruction.cpp:792: vx_warp_id: r13=2
DEBUG ../../../../simX/instruction.cpp:781: SYS_INST: r13 <- r0, imm=33
DEBUG ../../../../simX/instruction.cpp:792: vx_warpID: r13=2
DEBUG ../../../../simX/instruction.cpp:792: vx_warp_id: r13=2
DEBUG ../../../../simX/instruction.cpp:781: SYS_INST: r13 <- r0, imm=33
DEBUG ../../../../simX/instruction.cpp:792: vx_warpID: r13=2
DEBUG ../../../../simX/instruction.cpp:792: vx_warp_id: r13=2
DEBUG ../../../../simX/instruction.cpp:781: SYS_INST: r13 <- r0, imm=33
DEBUG ../../../../simX/instruction.cpp:792: vx_warpID: r13=2
DEBUG ../../../../simX/instruction.cpp:792: vx_warp_id: r13=2
DEBUG ../../../../simX/core.cpp:781: Register state:
%r 0: 00000000 00000000 00000000 00000000 (0)
%r 1: 00000000 00000000 00000000 00000000 (0)
@@ -3404,13 +3404,13 @@ DEBUG ../../../../simX/core.cpp:176: stalled warps: 0 0 0 0
DEBUG ../../../../simX/core.cpp:750: current PC=0x800000b0
DEBUG ../../../../simX/enc.cpp:324: Decoded instr 0x21026f3 into: SYS
DEBUG ../../../../simX/instruction.cpp:781: SYS_INST: r13 <- r0, imm=33
DEBUG ../../../../simX/instruction.cpp:792: vx_warpID: r13=3
DEBUG ../../../../simX/instruction.cpp:792: vx_warp_id: r13=3
DEBUG ../../../../simX/instruction.cpp:781: SYS_INST: r13 <- r0, imm=33
DEBUG ../../../../simX/instruction.cpp:792: vx_warpID: r13=3
DEBUG ../../../../simX/instruction.cpp:792: vx_warp_id: r13=3
DEBUG ../../../../simX/instruction.cpp:781: SYS_INST: r13 <- r0, imm=33
DEBUG ../../../../simX/instruction.cpp:792: vx_warpID: r13=3
DEBUG ../../../../simX/instruction.cpp:792: vx_warp_id: r13=3
DEBUG ../../../../simX/instruction.cpp:781: SYS_INST: r13 <- r0, imm=33
DEBUG ../../../../simX/instruction.cpp:792: vx_warpID: r13=3
DEBUG ../../../../simX/instruction.cpp:792: vx_warp_id: r13=3
DEBUG ../../../../simX/core.cpp:781: Register state:
%r 0: 00000000 00000000 00000000 00000000 (0)
%r 1: 00000000 00000000 00000000 00000000 (0)
@@ -3683,13 +3683,13 @@ DEBUG ../../../../simX/core.cpp:176: stalled warps: 0 1 1 1
DEBUG ../../../../simX/core.cpp:750: current PC=0x800000b0
DEBUG ../../../../simX/enc.cpp:324: Decoded instr 0x21026f3 into: SYS
DEBUG ../../../../simX/instruction.cpp:781: SYS_INST: r13 <- r0, imm=33
DEBUG ../../../../simX/instruction.cpp:792: vx_warpID: r13=0
DEBUG ../../../../simX/instruction.cpp:792: vx_warp_id: r13=0
DEBUG ../../../../simX/instruction.cpp:781: SYS_INST: r13 <- r0, imm=33
DEBUG ../../../../simX/instruction.cpp:792: vx_warpID: r13=0
DEBUG ../../../../simX/instruction.cpp:792: vx_warp_id: r13=0
DEBUG ../../../../simX/instruction.cpp:781: SYS_INST: r13 <- r0, imm=33
DEBUG ../../../../simX/instruction.cpp:792: vx_warpID: r13=0
DEBUG ../../../../simX/instruction.cpp:792: vx_warp_id: r13=0
DEBUG ../../../../simX/instruction.cpp:781: SYS_INST: r13 <- r0, imm=33
DEBUG ../../../../simX/instruction.cpp:792: vx_warpID: r13=0
DEBUG ../../../../simX/instruction.cpp:792: vx_warp_id: r13=0
DEBUG ../../../../simX/core.cpp:781: Register state:
%r 0: 00000000 00000000 00000000 00000000 (0)
%r 1: 80000014 00000000 00000000 00000000 (0)
@@ -22160,13 +22160,13 @@ DEBUG ../../../../simX/core.cpp:176: stalled warps: 1 0 1 1
DEBUG ../../../../simX/core.cpp:750: current PC=0x80000758
DEBUG ../../../../simX/enc.cpp:324: Decoded instr 0x2002573 into: SYS
DEBUG ../../../../simX/instruction.cpp:781: SYS_INST: r10 <- r0, imm=32
DEBUG ../../../../simX/instruction.cpp:788: vx_threadID: r10=0
DEBUG ../../../../simX/instruction.cpp:788: vx_thread_id: r10=0
DEBUG ../../../../simX/instruction.cpp:781: SYS_INST: r10 <- r0, imm=32
DEBUG ../../../../simX/instruction.cpp:788: vx_threadID: r10=1
DEBUG ../../../../simX/instruction.cpp:788: vx_thread_id: r10=1
DEBUG ../../../../simX/instruction.cpp:781: SYS_INST: r10 <- r0, imm=32
DEBUG ../../../../simX/instruction.cpp:788: vx_threadID: r10=2
DEBUG ../../../../simX/instruction.cpp:788: vx_thread_id: r10=2
DEBUG ../../../../simX/instruction.cpp:781: SYS_INST: r10 <- r0, imm=32
DEBUG ../../../../simX/instruction.cpp:788: vx_threadID: r10=3
DEBUG ../../../../simX/instruction.cpp:788: vx_thread_id: r10=3
DEBUG ../../../../simX/core.cpp:781: Register state:
%r 0: 00000000 00000000 00000000 00000000 (0)
%r 1: 800009d0 800009d0 800009d0 800009d0 (0)
@@ -22219,13 +22219,13 @@ DEBUG ../../../../simX/core.cpp:176: stalled warps: 1 0 0 1
DEBUG ../../../../simX/core.cpp:750: current PC=0x80000758
DEBUG ../../../../simX/enc.cpp:324: Decoded instr 0x2002573 into: SYS
DEBUG ../../../../simX/instruction.cpp:781: SYS_INST: r10 <- r0, imm=32
DEBUG ../../../../simX/instruction.cpp:788: vx_threadID: r10=0
DEBUG ../../../../simX/instruction.cpp:788: vx_thread_id: r10=0
DEBUG ../../../../simX/instruction.cpp:781: SYS_INST: r10 <- r0, imm=32
DEBUG ../../../../simX/instruction.cpp:788: vx_threadID: r10=1
DEBUG ../../../../simX/instruction.cpp:788: vx_thread_id: r10=1
DEBUG ../../../../simX/instruction.cpp:781: SYS_INST: r10 <- r0, imm=32
DEBUG ../../../../simX/instruction.cpp:788: vx_threadID: r10=2
DEBUG ../../../../simX/instruction.cpp:788: vx_thread_id: r10=2
DEBUG ../../../../simX/instruction.cpp:781: SYS_INST: r10 <- r0, imm=32
DEBUG ../../../../simX/instruction.cpp:788: vx_threadID: r10=3
DEBUG ../../../../simX/instruction.cpp:788: vx_thread_id: r10=3
DEBUG ../../../../simX/core.cpp:781: Register state:
%r 0: 00000000 00000000 00000000 00000000 (0)
%r 1: 800009d0 800009d0 800009d0 800009d0 (0)
@@ -22278,13 +22278,13 @@ DEBUG ../../../../simX/core.cpp:176: stalled warps: 1 0 0 0
DEBUG ../../../../simX/core.cpp:750: current PC=0x80000758
DEBUG ../../../../simX/enc.cpp:324: Decoded instr 0x2002573 into: SYS
DEBUG ../../../../simX/instruction.cpp:781: SYS_INST: r10 <- r0, imm=32
DEBUG ../../../../simX/instruction.cpp:788: vx_threadID: r10=0
DEBUG ../../../../simX/instruction.cpp:788: vx_thread_id: r10=0
DEBUG ../../../../simX/instruction.cpp:781: SYS_INST: r10 <- r0, imm=32
DEBUG ../../../../simX/instruction.cpp:788: vx_threadID: r10=1
DEBUG ../../../../simX/instruction.cpp:788: vx_thread_id: r10=1
DEBUG ../../../../simX/instruction.cpp:781: SYS_INST: r10 <- r0, imm=32
DEBUG ../../../../simX/instruction.cpp:788: vx_threadID: r10=2
DEBUG ../../../../simX/instruction.cpp:788: vx_thread_id: r10=2
DEBUG ../../../../simX/instruction.cpp:781: SYS_INST: r10 <- r0, imm=32
DEBUG ../../../../simX/instruction.cpp:788: vx_threadID: r10=3
DEBUG ../../../../simX/instruction.cpp:788: vx_thread_id: r10=3
DEBUG ../../../../simX/core.cpp:781: Register state:
%r 0: 00000000 00000000 00000000 00000000 (0)
%r 1: 800009d0 800009d0 800009d0 800009d0 (0)
@@ -22337,13 +22337,13 @@ DEBUG ../../../../simX/core.cpp:176: stalled warps: 0 0 0 0
DEBUG ../../../../simX/core.cpp:750: current PC=0x80000758
DEBUG ../../../../simX/enc.cpp:324: Decoded instr 0x2002573 into: SYS
DEBUG ../../../../simX/instruction.cpp:781: SYS_INST: r10 <- r0, imm=32
DEBUG ../../../../simX/instruction.cpp:788: vx_threadID: r10=0
DEBUG ../../../../simX/instruction.cpp:788: vx_thread_id: r10=0
DEBUG ../../../../simX/instruction.cpp:781: SYS_INST: r10 <- r0, imm=32
DEBUG ../../../../simX/instruction.cpp:788: vx_threadID: r10=1
DEBUG ../../../../simX/instruction.cpp:788: vx_thread_id: r10=1
DEBUG ../../../../simX/instruction.cpp:781: SYS_INST: r10 <- r0, imm=32
DEBUG ../../../../simX/instruction.cpp:788: vx_threadID: r10=2
DEBUG ../../../../simX/instruction.cpp:788: vx_thread_id: r10=2
DEBUG ../../../../simX/instruction.cpp:781: SYS_INST: r10 <- r0, imm=32
DEBUG ../../../../simX/instruction.cpp:788: vx_threadID: r10=3
DEBUG ../../../../simX/instruction.cpp:788: vx_thread_id: r10=3
DEBUG ../../../../simX/core.cpp:781: Register state:
%r 0: 00000000 00000000 00000000 00000000 (0)
%r 1: 800009d0 800009d0 800009d0 800009d0 (0)
@@ -39870,13 +39870,13 @@ DEBUG ../../../../simX/core.cpp:176: stalled warps: 1 0 0 0
DEBUG ../../../../simX/core.cpp:750: current PC=0x80000748
DEBUG ../../../../simX/enc.cpp:324: Decoded instr 0x2102573 into: SYS
DEBUG ../../../../simX/instruction.cpp:781: SYS_INST: r10 <- r0, imm=33
DEBUG ../../../../simX/instruction.cpp:792: vx_warpID: r10=2
DEBUG ../../../../simX/instruction.cpp:792: vx_warp_id: r10=2
DEBUG ../../../../simX/instruction.cpp:781: SYS_INST: r10 <- r0, imm=33
DEBUG ../../../../simX/instruction.cpp:792: vx_warpID: r10=2
DEBUG ../../../../simX/instruction.cpp:792: vx_warp_id: r10=2
DEBUG ../../../../simX/instruction.cpp:781: SYS_INST: r10 <- r0, imm=33
DEBUG ../../../../simX/instruction.cpp:792: vx_warpID: r10=2
DEBUG ../../../../simX/instruction.cpp:792: vx_warp_id: r10=2
DEBUG ../../../../simX/instruction.cpp:781: SYS_INST: r10 <- r0, imm=33
DEBUG ../../../../simX/instruction.cpp:792: vx_warpID: r10=2
DEBUG ../../../../simX/instruction.cpp:792: vx_warp_id: r10=2
DEBUG ../../../../simX/core.cpp:781: Register state:
%r 0: 00000000 00000000 00000000 00000000 (0)
%r 1: 80000810 80000810 80000810 80000810 (0)
@@ -39929,13 +39929,13 @@ DEBUG ../../../../simX/core.cpp:176: stalled warps: 1 0 0 0
DEBUG ../../../../simX/core.cpp:750: current PC=0x80000748
DEBUG ../../../../simX/enc.cpp:324: Decoded instr 0x2102573 into: SYS
DEBUG ../../../../simX/instruction.cpp:781: SYS_INST: r10 <- r0, imm=33
DEBUG ../../../../simX/instruction.cpp:792: vx_warpID: r10=3
DEBUG ../../../../simX/instruction.cpp:792: vx_warp_id: r10=3
DEBUG ../../../../simX/instruction.cpp:781: SYS_INST: r10 <- r0, imm=33
DEBUG ../../../../simX/instruction.cpp:792: vx_warpID: r10=3
DEBUG ../../../../simX/instruction.cpp:792: vx_warp_id: r10=3
DEBUG ../../../../simX/instruction.cpp:781: SYS_INST: r10 <- r0, imm=33
DEBUG ../../../../simX/instruction.cpp:792: vx_warpID: r10=3
DEBUG ../../../../simX/instruction.cpp:792: vx_warp_id: r10=3
DEBUG ../../../../simX/instruction.cpp:781: SYS_INST: r10 <- r0, imm=33
DEBUG ../../../../simX/instruction.cpp:792: vx_warpID: r10=3
DEBUG ../../../../simX/instruction.cpp:792: vx_warp_id: r10=3
DEBUG ../../../../simX/core.cpp:781: Register state:
%r 0: 00000000 00000000 00000000 00000000 (0)
%r 1: 80000810 80000810 80000810 80000810 (0)
@@ -39988,13 +39988,13 @@ DEBUG ../../../../simX/core.cpp:176: stalled warps: 1 0 0 0
DEBUG ../../../../simX/core.cpp:750: current PC=0x80000748
DEBUG ../../../../simX/enc.cpp:324: Decoded instr 0x2102573 into: SYS
DEBUG ../../../../simX/instruction.cpp:781: SYS_INST: r10 <- r0, imm=33
DEBUG ../../../../simX/instruction.cpp:792: vx_warpID: r10=1
DEBUG ../../../../simX/instruction.cpp:792: vx_warp_id: r10=1
DEBUG ../../../../simX/instruction.cpp:781: SYS_INST: r10 <- r0, imm=33
DEBUG ../../../../simX/instruction.cpp:792: vx_warpID: r10=1
DEBUG ../../../../simX/instruction.cpp:792: vx_warp_id: r10=1
DEBUG ../../../../simX/instruction.cpp:781: SYS_INST: r10 <- r0, imm=33
DEBUG ../../../../simX/instruction.cpp:792: vx_warpID: r10=1
DEBUG ../../../../simX/instruction.cpp:792: vx_warp_id: r10=1
DEBUG ../../../../simX/instruction.cpp:781: SYS_INST: r10 <- r0, imm=33
DEBUG ../../../../simX/instruction.cpp:792: vx_warpID: r10=1
DEBUG ../../../../simX/instruction.cpp:792: vx_warp_id: r10=1
DEBUG ../../../../simX/core.cpp:781: Register state:
%r 0: 00000000 00000000 00000000 00000000 (0)
%r 1: 80000810 80000810 80000810 80000810 (0)
@@ -40159,13 +40159,13 @@ DEBUG ../../../../simX/core.cpp:176: stalled warps: 0 0 1 1
DEBUG ../../../../simX/core.cpp:750: current PC=0x80000748
DEBUG ../../../../simX/enc.cpp:324: Decoded instr 0x2102573 into: SYS
DEBUG ../../../../simX/instruction.cpp:781: SYS_INST: r10 <- r0, imm=33
DEBUG ../../../../simX/instruction.cpp:792: vx_warpID: r10=0
DEBUG ../../../../simX/instruction.cpp:792: vx_warp_id: r10=0
DEBUG ../../../../simX/instruction.cpp:781: SYS_INST: r10 <- r0, imm=33
DEBUG ../../../../simX/instruction.cpp:792: vx_warpID: r10=0
DEBUG ../../../../simX/instruction.cpp:792: vx_warp_id: r10=0
DEBUG ../../../../simX/instruction.cpp:781: SYS_INST: r10 <- r0, imm=33
DEBUG ../../../../simX/instruction.cpp:792: vx_warpID: r10=0
DEBUG ../../../../simX/instruction.cpp:792: vx_warp_id: r10=0
DEBUG ../../../../simX/instruction.cpp:781: SYS_INST: r10 <- r0, imm=33
DEBUG ../../../../simX/instruction.cpp:792: vx_warpID: r10=0
DEBUG ../../../../simX/instruction.cpp:792: vx_warp_id: r10=0
DEBUG ../../../../simX/core.cpp:781: Register state:
%r 0: 00000000 00000000 00000000 00000000 (0)
%r 1: 800008c4 800008c4 800008c4 800008c4 (0)