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driver basic test and demo test refactoring

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This commit is contained in:
Blaise Tine
2020-06-19 09:12:07 -07:00
parent e2e1b63e14
commit 68d9fc9a75
55 changed files with 1006 additions and 1205 deletions
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2
hw/syn/quartus/cache/Makefile vendored
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@@ -49,7 +49,7 @@ smart.log: $(PROJECT_FILES)
# Project initialization
$(PROJECT_FILES):
quartus_sh -t project.tcl -project $(PROJECT) -family $(FAMILY) -device $(DEVICE) -top $(TOP_LEVEL_ENTITY) -src $(SRC_FILE) -sdc project.sdc -inc "../../../rtl;../../../rtl/libs;../../../rtl/interfaces;../../../rtl/cache"
quartus_sh -t ../project.tcl -project $(PROJECT) -family $(FAMILY) -device $(DEVICE) -top $(TOP_LEVEL_ENTITY) -src $(SRC_FILE) -sdc ../project.sdc -inc "../../../rtl;../../../rtl/libs;../../../rtl/cache"
syn.chg:
$(STAMP) syn.chg

1
hw/syn/quartus/cache/project.sdc vendored
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@@ -1 +0,0 @@
create_clock -name {clk} -period "250 MHz" -waveform { 0.0 1.0 } [get_ports {clk}]

67
hw/syn/quartus/cache/project.tcl vendored
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@@ -1,67 +0,0 @@
load_package flow
package require cmdline
set options {
{ "project.arg" "" "Project name" }
{ "family.arg" "" "Device family name" }
{ "device.arg" "" "Device name" }
{ "top.arg" "" "Top level module" }
{ "src.arg" "" "Verilog source file" }
{ "inc.arg" "" "Include path (optional)" }
{ "sdc.arg" "" "Timing Design Constraints file (optional)" }
{ "set.arg" "" "Macro value (optional)" }
}
set q_args_orig $quartus(args)
array set opts [::cmdline::getoptions quartus(args) $options]
# Verify required parameters
set requiredParameters {project family device top src}
foreach p $requiredParameters {
if {$opts($p) == ""} {
puts stderr "Missing required parameter: -$p"
exit 1
}
}
project_new $opts(project) -overwrite
set_global_assignment -name FAMILY $opts(family)
set_global_assignment -name DEVICE $opts(device)
set_global_assignment -name TOP_LEVEL_ENTITY $opts(top)
set_global_assignment -name PROJECT_OUTPUT_DIRECTORY bin
set_global_assignment -name NUM_PARALLEL_PROCESSORS ALL
set_global_assignment -name VERILOG_INPUT_VERSION SYSTEMVERILOG_2009
set idx 0
foreach arg $q_args_orig {
incr idx
if [string match "-src" $arg] {
set_global_assignment -name VERILOG_FILE [lindex $q_args_orig $idx]
}
if [string match "-inc" $arg] {
set_global_assignment -name SEARCH_PATH [lindex $q_args_orig $idx]
}
if [string match "-sdc" $arg] {
set_global_assignment -name SDC_FILE [lindex $q_args_orig $idx]
}
if [string match "-set" $arg] {
set_global_assignment -name VERILOG_MACRO [lindex $q_args_orig $idx]
}
}
proc make_all_pins_virtual {} {
execute_module -tool map
set name_ids [get_names -filter * -node_type pin]
foreach_in_collection name_id $name_ids {
set pin_name [get_name_info -info full_path $name_id]
post_message "Making VIRTUAL_PIN assignment to $pin_name"
set_instance_assignment -to $pin_name -name VIRTUAL_PIN ON
}
export_assignments
}
make_all_pins_virtual
project_close