driver basic test and demo test refactoring
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17
hw/rtl/cache/VX_cache.v
vendored
17
hw/rtl/cache/VX_cache.v
vendored
@@ -65,6 +65,8 @@ module VX_cache #(
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// Snooping forward tag width
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parameter SNP_FWD_TAG_WIDTH = 1
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) (
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`SCOPE_SIGNALS_ICACHE_IO
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input wire clk,
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input wire reset,
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@@ -125,7 +127,7 @@ module VX_cache #(
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output wire [NUM_SNP_REQUESTS-1:0] snp_fwdin_ready
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);
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`DEBUG_BLOCK(
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`ifdef DBG_CORE_REQ_INFO
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wire[31:0] debug_core_req_use_pc;
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wire[1:0] debug_core_req_wb;
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wire[4:0] debug_core_req_rd;
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@@ -135,7 +137,8 @@ module VX_cache #(
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if (WORD_SIZE != `GLOBAL_BLOCK_SIZE) begin
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assign {debug_core_req_use_pc, debug_core_req_wb, debug_core_req_rd, debug_core_req_warp_num, debug_core_req_idx} = core_req_tag[0];
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end
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)
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`endif
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wire [NUM_BANKS-1:0][NUM_REQUESTS-1:0] per_bank_valid;
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wire [NUM_BANKS-1:0] per_bank_core_req_ready;
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@@ -476,7 +479,13 @@ module VX_cache #(
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.per_bank_snp_rsp_ready (per_bank_snp_rsp_ready),
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.snp_rsp_valid (snp_rsp_valid),
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.snp_rsp_tag (snp_rsp_tag),
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.snp_rsp_ready (snp_rsp_ready)
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);
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.snp_rsp_ready (snp_rsp_ready)
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);
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`SCOPE_ASSIGN(scope_idram_req_valid, per_bank_dram_fill_req_valid[0]);
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`SCOPE_ASSIGN(scope_idram_req_ready, dram_fill_req_ready);
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`SCOPE_ASSIGN(scope_idram_rsp_valid, per_bank_core_rsp_valid[0]);
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`SCOPE_ASSIGN(scope_idram_rsp_ready, per_bank_core_rsp_ready[0]);
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endmodule
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