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driver basic test and demo test refactoring

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This commit is contained in:
Blaise Tine
2020-06-19 09:12:07 -07:00
parent e2e1b63e14
commit 68d9fc9a75
55 changed files with 1006 additions and 1205 deletions
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4
hw/rtl/VX_back_end.v
View File

@@ -3,7 +3,7 @@
module VX_back_end #(
parameter CORE_ID = 0
) (
`SCOPE_SIGNALS_DCACHE_IO
`SCOPE_SIGNALS_LSU_IO
`SCOPE_SIGNALS_BE_IO
input wire clk,
@@ -71,7 +71,7 @@ module VX_back_end #(
VX_lsu_unit #(
.CORE_ID(CORE_ID)
) lsu_unit (
`SCOPE_SIGNALS_DCACHE_ATTACH
`SCOPE_SIGNALS_LSU_BIND
.clk (clk),
.reset (reset),

314
hw/rtl/VX_define.vh
View File

@@ -2,6 +2,7 @@
`define VX_DEFINE
`include "VX_config.vh"
`include "VX_scope.vh"
// `define QUEUE_FORCE_MLAB 1
// `define SYN 1
@@ -139,7 +140,7 @@
///////////////////////////////////////////////////////////////////////////////
`ifndef NDEBUG // pc, wb, rd, warp_num
`ifdef DBG_CORE_REQ_INFO // pc, wb, rd, warp_num
`define DEBUG_CORE_REQ_MDATA_WIDTH (32 + 2 + 5 + `NW_BITS)
`else
`define DEBUG_CORE_REQ_MDATA_WIDTH 0
@@ -286,316 +287,5 @@
`define DRAM_TO_BYTE_ADDR(x) {x, (32-$bits(x))'(0)}
///////////////////////////////////////////////////////////////////////////////
`ifdef SCOPE
`define SCOPE_SIGNALS_DATA_LIST \
scope_icache_req_warp_num, \
scope_icache_req_addr, \
scope_icache_req_tag, \
scope_icache_rsp_data, \
scope_icache_rsp_tag, \
scope_dcache_req_warp_num, \
scope_dcache_req_curr_PC, \
scope_dcache_req_addr, \
scope_dcache_req_rw, \
scope_dcache_req_byteen, \
scope_dcache_req_data, \
scope_dcache_req_tag, \
scope_dcache_rsp_data, \
scope_dcache_rsp_tag, \
scope_dram_req_addr, \
scope_dram_req_rw, \
scope_dram_req_byteen, \
scope_dram_req_data, \
scope_dram_req_tag, \
scope_dram_rsp_data, \
scope_dram_rsp_tag, \
scope_snp_req_addr, \
scope_snp_req_invalidate, \
scope_snp_req_tag, \
scope_snp_rsp_tag, \
scope_decode_warp_num, \
scope_decode_curr_PC, \
scope_decode_is_jal, \
scope_decode_rs1, \
scope_decode_rs2, \
scope_execute_warp_num, \
scope_execute_rd, \
scope_execute_a, \
scope_execute_b, \
scope_writeback_warp_num, \
scope_writeback_wb, \
scope_writeback_rd, \
scope_writeback_data,
`define SCOPE_SIGNALS_UPD_LIST \
scope_icache_req_valid, \
scope_icache_req_ready, \
scope_icache_rsp_valid, \
scope_icache_rsp_ready, \
scope_dcache_req_valid, \
scope_dcache_req_ready, \
scope_dcache_rsp_valid, \
scope_dcache_rsp_ready, \
scope_dram_req_valid, \
scope_dram_req_ready, \
scope_dram_rsp_valid, \
scope_dram_rsp_ready, \
scope_snp_req_valid, \
scope_snp_req_ready, \
scope_snp_rsp_valid, \
scope_snp_rsp_ready, \
scope_decode_valid, \
scope_execute_valid, \
scope_writeback_valid, \
scope_schedule_delay, \
scope_memory_delay, \
scope_exec_delay, \
scope_gpr_stage_delay, \
scope_busy
`define SCOPE_SIGNALS_DECL \
wire scope_icache_req_valid; \
wire [1:0] scope_icache_req_warp_num; \
wire [31:0] scope_icache_req_addr; \
wire [`ICORE_TAG_WIDTH-1:0] scope_icache_req_tag; \
wire scope_icache_req_ready; \
wire scope_icache_rsp_valid; \
wire [31:0] scope_icache_rsp_data; \
wire [`ICORE_TAG_WIDTH-1:0] scope_icache_rsp_tag; \
wire scope_icache_rsp_ready; \
wire [`DNUM_REQUESTS-1:0] scope_dcache_req_valid; \
wire [1:0] scope_dcache_req_warp_num; \
wire [31:0] scope_dcache_req_curr_PC; \
wire [31:0] scope_dcache_req_addr; \
wire scope_dcache_req_rw; \
wire [3:0] scope_dcache_req_byteen; \
wire [31:0] scope_dcache_req_data; \
wire [`DCORE_TAG_WIDTH-1:0] scope_dcache_req_tag; \
wire scope_dcache_req_ready; \
wire [`DNUM_REQUESTS-1:0] scope_dcache_rsp_valid; \
wire [31:0] scope_dcache_rsp_data; \
wire [`DCORE_TAG_WIDTH-1:0] scope_dcache_rsp_tag; \
wire scope_dcache_rsp_ready; \
wire scope_dram_req_valid; \
wire [31:0] scope_dram_req_addr; \
wire scope_dram_req_rw; \
wire [15:0] scope_dram_req_byteen; \
wire [31:0] scope_dram_req_data; \
wire [`VX_DRAM_TAG_WIDTH-1:0] scope_dram_req_tag; \
wire scope_dram_req_ready; \
wire scope_dram_rsp_valid; \
wire [31:0] scope_dram_rsp_data; \
wire [`VX_DRAM_TAG_WIDTH-1:0] scope_dram_rsp_tag; \
wire scope_dram_rsp_ready; \
wire scope_snp_req_valid; \
wire [31:0] scope_snp_req_addr; \
wire scope_snp_req_invalidate; \
wire [`VX_SNP_TAG_WIDTH-1:0] scope_snp_req_tag; \
wire scope_snp_req_ready; \
wire scope_snp_rsp_valid; \
wire [`VX_SNP_TAG_WIDTH-1:0] scope_snp_rsp_tag; \
wire scope_busy; \
wire scope_snp_rsp_ready; \
wire scope_schedule_delay; \
wire scope_memory_delay; \
wire scope_exec_delay; \
wire scope_gpr_stage_delay; \
wire [3:0] scope_decode_valid; \
wire [1:0] scope_decode_warp_num; \
wire [31:0] scope_decode_curr_PC; \
wire scope_decode_is_jal; \
wire [4:0] scope_decode_rs1; \
wire [4:0] scope_decode_rs2; \
wire [3:0] scope_execute_valid; \
wire [1:0] scope_execute_warp_num; \
wire [4:0] scope_execute_rd; \
wire [31:0] scope_execute_a; \
wire [31:0] scope_execute_b; \
wire [3:0] scope_writeback_valid; \
wire [1:0] scope_writeback_warp_num; \
wire [1:0] scope_writeback_wb; \
wire [4:0] scope_writeback_rd; \
wire [31:0] scope_writeback_data;
`define SCOPE_SIGNALS_ICACHE_IO \
/* verilator lint_off UNDRIVEN */ \
output wire scope_icache_req_valid, \
output wire [1:0] scope_icache_req_warp_num, \
output wire [31:0] scope_icache_req_addr, \
output wire [`ICORE_TAG_WIDTH-1:0] scope_icache_req_tag, \
output wire scope_icache_req_ready, \
output wire scope_icache_rsp_valid, \
output wire [31:0] scope_icache_rsp_data, \
output wire [`ICORE_TAG_WIDTH-1:0] scope_icache_rsp_tag, \
output wire scope_icache_rsp_ready, \
/* verilator lint_on UNDRIVEN */
`define SCOPE_SIGNALS_DCACHE_IO \
/* verilator lint_off UNDRIVEN */ \
output wire [`DNUM_REQUESTS-1:0] scope_dcache_req_valid, \
output wire [1:0] scope_dcache_req_warp_num, \
output wire [31:0] scope_dcache_req_curr_PC, \
output wire [31:0] scope_dcache_req_addr, \
output wire scope_dcache_req_rw, \
output wire [3:0] scope_dcache_req_byteen, \
output wire [31:0] scope_dcache_req_data, \
output wire [`DCORE_TAG_WIDTH-1:0] scope_dcache_req_tag, \
output wire scope_dcache_req_ready, \
output wire [`DNUM_REQUESTS-1:0] scope_dcache_rsp_valid, \
output wire [31:0] scope_dcache_rsp_data, \
output wire [`DCORE_TAG_WIDTH-1:0] scope_dcache_rsp_tag, \
output wire scope_dcache_rsp_ready, \
/* verilator lint_on UNDRIVEN */
`define SCOPE_SIGNALS_DRAM_IO \
/* verilator lint_off UNDRIVEN */ \
output wire scope_dram_req_valid, \
output wire [31:0] scope_dram_req_addr, \
output wire scope_dram_req_rw, \
output wire [15:0] scope_dram_req_byteen, \
output wire [31:0] scope_dram_req_data, \
output wire [`VX_DRAM_TAG_WIDTH-1:0] scope_dram_req_tag, \
output wire scope_dram_req_ready, \
output wire scope_dram_rsp_valid, \
output wire [31:0] scope_dram_rsp_data, \
output wire [`VX_DRAM_TAG_WIDTH-1:0] scope_dram_rsp_tag, \
output wire scope_dram_rsp_ready, \
/* verilator lint_on UNDRIVEN */
`define SCOPE_SIGNALS_SNP_IO \
/* verilator lint_off UNDRIVEN */ \
output wire scope_snp_req_valid, \
output wire [31:0] scope_snp_req_addr, \
output wire scope_snp_req_invalidate, \
output wire [`VX_SNP_TAG_WIDTH-1:0] scope_snp_req_tag, \
output wire scope_snp_req_ready, \
output wire scope_snp_rsp_valid, \
output wire [`VX_SNP_TAG_WIDTH-1:0] scope_snp_rsp_tag, \
output wire scope_snp_rsp_ready, \
/* verilator lint_on UNDRIVEN */
`define SCOPE_SIGNALS_CORE_IO \
/* verilator lint_off UNDRIVEN */ \
output wire scope_busy, \
output wire scope_schedule_delay, \
output wire scope_memory_delay, \
output wire scope_exec_delay, \
output wire scope_gpr_stage_delay, \
/* verilator lint_on UNDRIVEN */
`define SCOPE_SIGNALS_BE_IO \
/* verilator lint_off UNDRIVEN */ \
output wire [3:0] scope_decode_valid, \
output wire [1:0] scope_decode_warp_num, \
output wire [31:0] scope_decode_curr_PC, \
output wire scope_decode_is_jal, \
output wire [4:0] scope_decode_rs1, \
output wire [4:0] scope_decode_rs2, \
output wire [3:0] scope_execute_valid, \
output wire [1:0] scope_execute_warp_num, \
output wire [4:0] scope_execute_rd, \
output wire [31:0] scope_execute_a, \
output wire [31:0] scope_execute_b, \
output wire [3:0] scope_writeback_valid, \
output wire [1:0] scope_writeback_warp_num, \
output wire [1:0] scope_writeback_wb, \
output wire [4:0] scope_writeback_rd, \
output wire [31:0] scope_writeback_data,
/* verilator lint_on UNDRIVEN */
`define SCOPE_SIGNALS_ICACHE_ATTACH \
.scope_icache_req_valid (scope_icache_req_valid), \
.scope_icache_req_warp_num (scope_icache_req_warp_num), \
.scope_icache_req_addr (scope_icache_req_addr), \
.scope_icache_req_tag (scope_icache_req_tag), \
.scope_icache_req_ready (scope_icache_req_ready), \
.scope_icache_rsp_valid (scope_icache_rsp_valid), \
.scope_icache_rsp_data (scope_icache_rsp_data), \
.scope_icache_rsp_tag (scope_icache_rsp_tag), \
.scope_icache_rsp_ready (scope_icache_rsp_ready),
`define SCOPE_SIGNALS_DCACHE_ATTACH \
.scope_dcache_req_valid (scope_dcache_req_valid), \
.scope_dcache_req_warp_num (scope_dcache_req_warp_num), \
.scope_dcache_req_curr_PC (scope_dcache_req_curr_PC), \
.scope_dcache_req_addr (scope_dcache_req_addr), \
.scope_dcache_req_rw (scope_dcache_req_rw), \
.scope_dcache_req_byteen(scope_dcache_req_byteen), \
.scope_dcache_req_data (scope_dcache_req_data), \
.scope_dcache_req_tag (scope_dcache_req_tag), \
.scope_dcache_req_ready (scope_dcache_req_ready), \
.scope_dcache_rsp_valid (scope_dcache_rsp_valid), \
.scope_dcache_rsp_data (scope_dcache_rsp_data), \
.scope_dcache_rsp_tag (scope_dcache_rsp_tag), \
.scope_dcache_rsp_ready (scope_dcache_rsp_ready),
`define SCOPE_SIGNALS_DRAM_ATTACH \
.scope_dram_req_valid (scope_dram_req_valid), \
.scope_dram_req_addr (scope_dram_req_addr), \
.scope_dram_req_rw (scope_dram_req_rw), \
.scope_dram_req_byteen (scope_dram_req_byteen), \
.scope_dram_req_data (scope_dram_req_data), \
.scope_dram_req_tag (scope_dram_req_tag), \
.scope_dram_req_ready (scope_dram_req_ready), \
.scope_dram_rsp_valid (scope_dram_rsp_valid), \
.scope_dram_rsp_data (scope_dram_rsp_data), \
.scope_dram_rsp_tag (scope_dram_rsp_tag), \
.scope_dram_rsp_ready (scope_dram_rsp_ready),
`define SCOPE_SIGNALS_SNP_ATTACH \
.scope_snp_req_valid (scope_snp_req_valid), \
.scope_snp_req_addr (scope_snp_req_addr), \
.scope_snp_req_invalidate(scope_snp_req_invalidate), \
.scope_snp_req_tag (scope_snp_req_tag), \
.scope_snp_req_ready (scope_snp_req_ready), \
.scope_snp_rsp_valid (scope_snp_rsp_valid), \
.scope_snp_rsp_tag (scope_snp_rsp_tag), \
.scope_snp_rsp_ready (scope_snp_rsp_ready),
`define SCOPE_SIGNALS_CORE_ATTACH \
.scope_busy (scope_busy), \
.scope_schedule_delay (scope_schedule_delay), \
.scope_memory_delay (scope_memory_delay), \
.scope_exec_delay (scope_exec_delay), \
.scope_gpr_stage_delay (scope_gpr_stage_delay),
`define SCOPE_SIGNALS_BE_ATTACH \
.scope_decode_valid (scope_decode_valid), \
.scope_decode_warp_num (scope_decode_warp_num), \
.scope_decode_curr_PC (scope_decode_curr_PC), \
.scope_decode_is_jal (scope_decode_is_jal), \
.scope_decode_rs1 (scope_decode_rs1), \
.scope_decode_rs2 (scope_decode_rs2), \
.scope_execute_valid (scope_execute_valid), \
.scope_execute_warp_num (scope_execute_warp_num), \
.scope_execute_rd (scope_execute_rd), \
.scope_execute_a (scope_execute_a), \
.scope_execute_b (scope_execute_b), \
.scope_writeback_valid (scope_writeback_valid), \
.scope_writeback_warp_num (scope_writeback_warp_num), \
.scope_writeback_wb (scope_writeback_wb), \
.scope_writeback_rd (scope_writeback_rd), \
.scope_writeback_data (scope_writeback_data),
`define SCOPE_ASSIGN(d,s) assign d = s
`else
`define SCOPE_SIGNALS_ICACHE_IO
`define SCOPE_SIGNALS_DCACHE_IO
`define SCOPE_SIGNALS_DRAM_IO
`define SCOPE_SIGNALS_CORE_IO
`define SCOPE_SIGNALS_BE_IO
`define SCOPE_SIGNALS_ICACHE_ATTACH
`define SCOPE_SIGNALS_DCACHE_ATTACH
`define SCOPE_SIGNALS_DRAM_ATTACH
`define SCOPE_SIGNALS_CORE_ATTACH
`define SCOPE_SIGNALS_BE_ATTACH
`define SCOPE_ASSIGN(d,s)
`endif
// VX_DEFINE
`endif

4
hw/rtl/VX_front_end.v
View File

@@ -3,7 +3,7 @@
module VX_front_end #(
parameter CORE_ID = 0
) (
`SCOPE_SIGNALS_ICACHE_IO
`SCOPE_SIGNALS_ISTAGE_IO
input wire clk,
input wire reset,
@@ -65,7 +65,7 @@ module VX_front_end #(
VX_icache_stage #(
.CORE_ID(CORE_ID)
) icache_stage (
`SCOPE_SIGNALS_ICACHE_ATTACH
`SCOPE_SIGNALS_ISTAGE_BIND
.clk (clk),
.reset (reset),

6
hw/rtl/VX_icache_stage.v
View File

@@ -3,7 +3,7 @@
module VX_icache_stage #(
parameter CORE_ID = 0
) (
`SCOPE_SIGNALS_ICACHE_IO
`SCOPE_SIGNALS_ISTAGE_IO
input wire clk,
input wire reset,
@@ -68,7 +68,7 @@ module VX_icache_stage #(
// Can't accept new request
assign icache_stage_delay = mrq_full || ~icache_req_if.core_req_ready;
`ifndef NDEBUG
`ifdef DBG_CORE_REQ_INFO
assign icache_req_if.core_req_tag = {fe_inst_meta_fi.inst_pc, 2'b1, 5'b0, fe_inst_meta_fi.warp_num, mrq_write_addr};
`else
assign icache_req_if.core_req_tag = mrq_write_addr;
@@ -95,7 +95,7 @@ module VX_icache_stage #(
`SCOPE_ASSIGN(scope_icache_rsp_ready, icache_rsp_if.core_rsp_ready);
`ifdef DBG_PRINT_CORE_ICACHE
always_ff @(posedge clk) begin
always @(posedge clk) begin
if (icache_req_if.core_req_valid && icache_req_if.core_req_ready) begin
$display("%t: I%01d$ req: tag=%0h, pc=%0h, warp=%0d", $time, CORE_ID, mrq_write_addr, fe_inst_meta_fi.inst_pc, fe_inst_meta_fi.warp_num);
end

10
hw/rtl/VX_lsu_unit.v
View File

@@ -3,7 +3,7 @@
module VX_lsu_unit #(
parameter CORE_ID = 0
) (
`SCOPE_SIGNALS_DCACHE_IO
`SCOPE_SIGNALS_LSU_IO
input wire clk,
input wire reset,
@@ -130,10 +130,10 @@ module VX_lsu_unit #(
assign dcache_req_if.core_req_addr = mem_req_addr;
assign dcache_req_if.core_req_data = mem_req_data;
`ifndef NDEBUG
assign dcache_req_if.core_req_tag = {use_pc, use_wb, use_rd, use_warp_num, mrq_write_addr};
`ifdef DBG_CORE_REQ_INFO
assign dcache_req_if.core_req_tag = {use_pc, use_wb, use_rd, use_warp_num, mrq_write_addr};
`else
assign dcache_req_if.core_req_tag = mrq_write_addr;
assign dcache_req_if.core_req_tag = mrq_write_addr;
`endif
// Can't accept new request
@@ -179,7 +179,7 @@ module VX_lsu_unit #(
`SCOPE_ASSIGN(scope_dcache_rsp_ready, dcache_rsp_if.core_rsp_ready);
`ifdef DBG_PRINT_CORE_DCACHE
always_ff @(posedge clk) begin
always @(posedge clk) begin
if ((| dcache_req_if.core_req_valid) && dcache_req_if.core_req_ready) begin
$display("%t: D%01d$ req: valid=%b, addr=%0h, tag=%0h, r=%0d, w=%0d, pc=%0h, rd=%0d, warp=%0d, byteen=%0h, data=%0h",
$time, CORE_ID, use_valid, use_address, mrq_write_addr, use_mem_read, use_mem_write, use_pc, use_rd, use_warp_num, mem_req_byteen, mem_req_data);

12
hw/rtl/VX_mem_ctrl.v → hw/rtl/VX_mem_unit.v
View File

@@ -1,8 +1,10 @@
`include "VX_define.vh"
module VX_mem_ctrl # (
module VX_mem_unit # (
parameter CORE_ID = 0
) (
`SCOPE_SIGNALS_ICACHE_IO
input wire clk,
input wire reset,
@@ -74,7 +76,7 @@ module VX_mem_ctrl # (
.CORE_TAG_WIDTH (`DCORE_TAG_WIDTH),
.CORE_TAG_ID_BITS (`DCORE_TAG_ID_BITS),
.DRAM_TAG_WIDTH (`SDRAM_TAG_WIDTH)
) gpu_smem (
) smem (
.clk (clk),
.reset (reset),
@@ -157,7 +159,7 @@ module VX_mem_ctrl # (
.CORE_TAG_ID_BITS (`DCORE_TAG_ID_BITS),
.DRAM_TAG_WIDTH (`DDRAM_TAG_WIDTH),
.SNP_REQ_TAG_WIDTH (`DSNP_TAG_WIDTH)
) gpu_dcache (
) dcache (
.clk (clk),
.reset (reset),
@@ -239,7 +241,9 @@ module VX_mem_ctrl # (
.CORE_TAG_WIDTH (`DCORE_TAG_WIDTH),
.CORE_TAG_ID_BITS (`DCORE_TAG_ID_BITS),
.DRAM_TAG_WIDTH (`IDRAM_TAG_WIDTH)
) gpu_icache (
) icache (
`SCOPE_SIGNALS_ICACHE_BIND
.clk (clk),
.reset (reset),

14
hw/rtl/VX_pipeline.v
View File

@@ -3,9 +3,9 @@
module VX_pipeline #(
parameter CORE_ID = 0
) (
`SCOPE_SIGNALS_ICACHE_IO
`SCOPE_SIGNALS_DCACHE_IO
`SCOPE_SIGNALS_CORE_IO
`SCOPE_SIGNALS_ISTAGE_IO
`SCOPE_SIGNALS_LSU_IO
`SCOPE_SIGNALS_PIPELINE_IO
`SCOPE_SIGNALS_BE_IO
// Clock
@@ -100,7 +100,7 @@ module VX_pipeline #(
VX_front_end #(
.CORE_ID(CORE_ID)
) front_end (
`SCOPE_SIGNALS_ICACHE_ATTACH
`SCOPE_SIGNALS_ISTAGE_BIND
.clk (clk),
.reset (reset),
@@ -129,8 +129,8 @@ module VX_pipeline #(
VX_back_end #(
.CORE_ID(CORE_ID)
) back_end (
`SCOPE_SIGNALS_DCACHE_ATTACH
`SCOPE_SIGNALS_BE_ATTACH
`SCOPE_SIGNALS_LSU_BIND
`SCOPE_SIGNALS_BE_BIND
.clk (clk),
.reset (reset),
@@ -181,7 +181,7 @@ module VX_pipeline #(
`SCOPE_ASSIGN(scope_gpr_stage_delay, gpr_stage_delay);
`ifdef DBG_PRINT_WB
always_ff @(posedge clk) begin
always @(posedge clk) begin
if ((| writeback_if.valid) && (writeback_if.wb != 0)) begin
$display("%t: Writeback: wid=%0d, rd=%0d, data=%0h", $time, writeback_if.warp_num, writeback_if.rd, writeback_if.data);
end

27
hw/rtl/VX_scheduler.v
View File

@@ -13,11 +13,10 @@ module VX_scheduler (
output wire schedule_delay,
output wire is_empty
);
reg [31:0][`NUM_THREADS-1:0] rename_table[`NUM_WARPS-1:0];
reg [31:0] count_valid;
localparam CTVW = `CLOG2(`NUM_WARPS * 32 + 1);
wire acquire_rd = (| bckE_req_if.valid) && (bckE_req_if.wb != 0) && (bckE_req_if.rd != 0);
wire release_rd = (| writeback_if.valid) && (writeback_if.wb != 0) && (writeback_if.rd != 0);
reg [31:0][`NUM_THREADS-1:0] rename_table[`NUM_WARPS-1:0];
reg [CTVW-1:0] count_valid;
wire is_store = (bckE_req_if.mem_write != `BYTE_EN_NO);
wire is_load = (bckE_req_if.mem_read != `BYTE_EN_NO);
@@ -51,7 +50,14 @@ module VX_scheduler (
integer i, w;
wire acquire_rd = (| bckE_req_if.valid) && (bckE_req_if.wb != 0) && (bckE_req_if.rd != 0) && !schedule_delay;
wire release_rd = (| writeback_if.valid) && (writeback_if.wb != 0) && (writeback_if.rd != 0);
wire [`NUM_THREADS-1:0] valid_wb_new_mask = rename_table[writeback_if.warp_num][writeback_if.rd] & ~writeback_if.valid;
reg [CTVW-1:0] count_valid_next = (acquire_rd && ~(release_rd && (0 == valid_wb_new_mask))) ? (count_valid + 1) :
(~acquire_rd && (release_rd && (0 == valid_wb_new_mask))) ? (count_valid - 1) :
count_valid;
always @(posedge clk) begin
if (reset) begin
@@ -62,19 +68,14 @@ module VX_scheduler (
end
count_valid <= 0;
end else begin
if (acquire_rd && !schedule_delay) begin
if (acquire_rd) begin
rename_table[bckE_req_if.warp_num][bckE_req_if.rd] <= bckE_req_if.valid;
count_valid <= count_valid + 1;
end
if (release_rd) begin
assert(rename_table[writeback_if.warp_num][writeback_if.rd] != 0);
rename_table[writeback_if.warp_num][writeback_if.rd] <= valid_wb_new_mask;
if (0 == valid_wb_new_mask) begin
assert(count_valid != 0);
count_valid <= count_valid - 1;
end
end
rename_table[writeback_if.warp_num][writeback_if.rd] <= valid_wb_new_mask;
end
count_valid <= count_valid_next;
end
end

283
hw/rtl/VX_scope.vh Normal file
View File

@@ -0,0 +1,283 @@
`ifndef VX_SCOPE
`define VX_SCOPE
`ifdef SCOPE
`define SCOPE_SIGNALS_DATA_LIST \
scope_icache_req_warp_num, \
scope_icache_req_addr, \
scope_icache_req_tag, \
scope_icache_rsp_data, \
scope_icache_rsp_tag, \
scope_dcache_req_warp_num, \
scope_dcache_req_curr_PC, \
scope_dcache_req_addr, \
scope_dcache_req_rw, \
scope_dcache_req_byteen, \
scope_dcache_req_data, \
scope_dcache_req_tag, \
scope_dcache_rsp_data, \
scope_dcache_rsp_tag, \
scope_dram_req_addr, \
scope_dram_req_rw, \
scope_dram_req_byteen, \
scope_dram_req_data, \
scope_dram_req_tag, \
scope_dram_rsp_data, \
scope_dram_rsp_tag, \
scope_snp_req_addr, \
scope_snp_req_invalidate, \
scope_snp_req_tag, \
scope_snp_rsp_tag, \
scope_decode_warp_num, \
scope_decode_curr_PC, \
scope_decode_is_jal, \
scope_decode_rs1, \
scope_decode_rs2, \
scope_execute_warp_num, \
scope_execute_rd, \
scope_execute_a, \
scope_execute_b, \
scope_writeback_warp_num, \
scope_writeback_wb, \
scope_writeback_rd, \
scope_writeback_data,
`define SCOPE_SIGNALS_UPD_LIST \
scope_icache_req_valid, \
scope_icache_req_ready, \
scope_icache_rsp_valid, \
scope_icache_rsp_ready, \
scope_dcache_req_valid, \
scope_dcache_req_ready, \
scope_dcache_rsp_valid, \
scope_dcache_rsp_ready, \
scope_dram_req_valid, \
scope_dram_req_ready, \
scope_dram_rsp_valid, \
scope_dram_rsp_ready, \
scope_snp_req_valid, \
scope_snp_req_ready, \
scope_snp_rsp_valid, \
scope_snp_rsp_ready, \
scope_decode_valid, \
scope_execute_valid, \
scope_writeback_valid, \
scope_schedule_delay, \
scope_memory_delay, \
scope_exec_delay, \
scope_gpr_stage_delay, \
scope_busy, \
scope_idram_req_valid, \
scope_idram_req_ready, \
scope_idram_rsp_valid, \
scope_idram_rsp_ready
`define SCOPE_SIGNALS_DECL \
wire scope_icache_req_valid; \
wire [`NW_BITS-1:0] scope_icache_req_warp_num; \
wire [31:0] scope_icache_req_addr; \
wire [`ICORE_TAG_WIDTH-1:0] scope_icache_req_tag; \
wire scope_icache_req_ready; \
wire scope_icache_rsp_valid; \
wire [31:0] scope_icache_rsp_data; \
wire [`ICORE_TAG_WIDTH-1:0] scope_icache_rsp_tag; \
wire scope_icache_rsp_ready; \
wire [`NUM_THREADS-1:0] scope_dcache_req_valid; \
wire [`NW_BITS-1:0] scope_dcache_req_warp_num; \
wire [31:0] scope_dcache_req_curr_PC; \
wire [31:0] scope_dcache_req_addr; \
wire scope_dcache_req_rw; \
wire [3:0] scope_dcache_req_byteen; \
wire [31:0] scope_dcache_req_data; \
wire [`DCORE_TAG_WIDTH-1:0] scope_dcache_req_tag; \
wire scope_dcache_req_ready; \
wire [`NUM_THREADS-1:0] scope_dcache_rsp_valid; \
wire [31:0] scope_dcache_rsp_data; \
wire [`DCORE_TAG_WIDTH-1:0] scope_dcache_rsp_tag; \
wire scope_dcache_rsp_ready; \
wire scope_dram_req_valid; \
wire [31:0] scope_dram_req_addr; \
wire scope_dram_req_rw; \
wire [15:0] scope_dram_req_byteen; \
wire [31:0] scope_dram_req_data; \
wire [`VX_DRAM_TAG_WIDTH-1:0] scope_dram_req_tag; \
wire scope_dram_req_ready; \
wire scope_dram_rsp_valid; \
wire [31:0] scope_dram_rsp_data; \
wire [`VX_DRAM_TAG_WIDTH-1:0] scope_dram_rsp_tag; \
wire scope_dram_rsp_ready; \
wire scope_snp_req_valid; \
wire [31:0] scope_snp_req_addr; \
wire scope_snp_req_invalidate; \
wire [`VX_SNP_TAG_WIDTH-1:0] scope_snp_req_tag; \
wire scope_snp_req_ready; \
wire scope_snp_rsp_valid; \
wire [`VX_SNP_TAG_WIDTH-1:0] scope_snp_rsp_tag; \
wire scope_busy; \
wire scope_snp_rsp_ready; \
wire scope_schedule_delay; \
wire scope_memory_delay; \
wire scope_exec_delay; \
wire scope_gpr_stage_delay; \
wire [`NUM_THREADS-1:0] scope_decode_valid; \
wire [`NW_BITS-1:0] scope_decode_warp_num; \
wire [31:0] scope_decode_curr_PC; \
wire scope_decode_is_jal; \
wire [4:0] scope_decode_rs1; \
wire [4:0] scope_decode_rs2; \
wire [`NUM_THREADS-1:0] scope_execute_valid; \
wire [`NW_BITS-1:0] scope_execute_warp_num; \
wire [4:0] scope_execute_rd; \
wire [31:0] scope_execute_a; \
wire [31:0] scope_execute_b; \
wire [`NUM_THREADS-1:0] scope_writeback_valid; \
wire [`NW_BITS-1:0] scope_writeback_warp_num; \
wire [1:0] scope_writeback_wb; \
wire [4:0] scope_writeback_rd; \
wire [31:0] scope_writeback_data; \
wire scope_idram_req_valid; \
wire scope_idram_req_ready; \
wire scope_idram_rsp_valid; \
wire scope_idram_rsp_ready;
`define SCOPE_SIGNALS_ISTAGE_IO \
output wire scope_icache_req_valid, \
output wire [`NW_BITS-1:0] scope_icache_req_warp_num, \
output wire [31:0] scope_icache_req_addr, \
output wire [`ICORE_TAG_WIDTH-1:0] scope_icache_req_tag, \
output wire scope_icache_req_ready, \
output wire scope_icache_rsp_valid, \
output wire [31:0] scope_icache_rsp_data, \
output wire [`ICORE_TAG_WIDTH-1:0] scope_icache_rsp_tag, \
output wire scope_icache_rsp_ready,
`define SCOPE_SIGNALS_LSU_IO \
output wire [`NUM_THREADS-1:0] scope_dcache_req_valid, \
output wire [`NW_BITS-1:0] scope_dcache_req_warp_num, \
output wire [31:0] scope_dcache_req_curr_PC, \
output wire [31:0] scope_dcache_req_addr, \
output wire scope_dcache_req_rw, \
output wire [3:0] scope_dcache_req_byteen, \
output wire [31:0] scope_dcache_req_data, \
output wire [`DCORE_TAG_WIDTH-1:0] scope_dcache_req_tag, \
output wire scope_dcache_req_ready, \
output wire [`NUM_THREADS-1:0] scope_dcache_rsp_valid, \
output wire [31:0] scope_dcache_rsp_data, \
output wire [`DCORE_TAG_WIDTH-1:0] scope_dcache_rsp_tag, \
output wire scope_dcache_rsp_ready,
`define SCOPE_SIGNALS_CORE_IO \
`define SCOPE_SIGNALS_ICACHE_IO \
output wire scope_idram_req_valid, \
output wire scope_idram_req_ready, \
output wire scope_idram_rsp_valid, \
output wire scope_idram_rsp_ready,
`define SCOPE_SIGNALS_PIPELINE_IO \
output wire scope_busy, \
output wire scope_schedule_delay, \
output wire scope_memory_delay, \
output wire scope_exec_delay, \
output wire scope_gpr_stage_delay,
`define SCOPE_SIGNALS_BE_IO \
output wire [`NUM_THREADS-1:0] scope_decode_valid, \
output wire [`NW_BITS-1:0] scope_decode_warp_num, \
output wire [31:0] scope_decode_curr_PC, \
output wire scope_decode_is_jal, \
output wire [4:0] scope_decode_rs1, \
output wire [4:0] scope_decode_rs2, \
output wire [`NUM_THREADS-1:0] scope_execute_valid, \
output wire [`NW_BITS-1:0] scope_execute_warp_num, \
output wire [4:0] scope_execute_rd, \
output wire [31:0] scope_execute_a, \
output wire [31:0] scope_execute_b, \
output wire [`NUM_THREADS-1:0] scope_writeback_valid, \
output wire [`NW_BITS-1:0] scope_writeback_warp_num, \
output wire [1:0] scope_writeback_wb, \
output wire [4:0] scope_writeback_rd, \
output wire [31:0] scope_writeback_data,
`define SCOPE_SIGNALS_ISTAGE_BIND \
.scope_icache_req_valid (scope_icache_req_valid), \
.scope_icache_req_warp_num (scope_icache_req_warp_num), \
.scope_icache_req_addr (scope_icache_req_addr), \
.scope_icache_req_tag (scope_icache_req_tag), \
.scope_icache_req_ready (scope_icache_req_ready), \
.scope_icache_rsp_valid (scope_icache_rsp_valid), \
.scope_icache_rsp_data (scope_icache_rsp_data), \
.scope_icache_rsp_tag (scope_icache_rsp_tag), \
.scope_icache_rsp_ready (scope_icache_rsp_ready),
`define SCOPE_SIGNALS_LSU_BIND \
.scope_dcache_req_valid (scope_dcache_req_valid), \
.scope_dcache_req_warp_num (scope_dcache_req_warp_num), \
.scope_dcache_req_curr_PC (scope_dcache_req_curr_PC), \
.scope_dcache_req_addr (scope_dcache_req_addr), \
.scope_dcache_req_rw (scope_dcache_req_rw), \
.scope_dcache_req_byteen(scope_dcache_req_byteen), \
.scope_dcache_req_data (scope_dcache_req_data), \
.scope_dcache_req_tag (scope_dcache_req_tag), \
.scope_dcache_req_ready (scope_dcache_req_ready), \
.scope_dcache_rsp_valid (scope_dcache_rsp_valid), \
.scope_dcache_rsp_data (scope_dcache_rsp_data), \
.scope_dcache_rsp_tag (scope_dcache_rsp_tag), \
.scope_dcache_rsp_ready (scope_dcache_rsp_ready),
`define SCOPE_SIGNALS_CORE_BIND \
`define SCOPE_SIGNALS_ICACHE_BIND \
.scope_idram_req_valid (scope_idram_req_valid), \
.scope_idram_req_ready (scope_idram_req_ready), \
.scope_idram_rsp_valid (scope_idram_rsp_valid), \
.scope_idram_rsp_ready (scope_idram_rsp_ready),
`define SCOPE_SIGNALS_PIPELINE_BIND \
.scope_busy (scope_busy), \
.scope_schedule_delay (scope_schedule_delay), \
.scope_memory_delay (scope_memory_delay), \
.scope_exec_delay (scope_exec_delay), \
.scope_gpr_stage_delay (scope_gpr_stage_delay),
`define SCOPE_SIGNALS_BE_BIND \
.scope_decode_valid (scope_decode_valid), \
.scope_decode_warp_num (scope_decode_warp_num), \
.scope_decode_curr_PC (scope_decode_curr_PC), \
.scope_decode_is_jal (scope_decode_is_jal), \
.scope_decode_rs1 (scope_decode_rs1), \
.scope_decode_rs2 (scope_decode_rs2), \
.scope_execute_valid (scope_execute_valid), \
.scope_execute_warp_num (scope_execute_warp_num), \
.scope_execute_rd (scope_execute_rd), \
.scope_execute_a (scope_execute_a), \
.scope_execute_b (scope_execute_b), \
.scope_writeback_valid (scope_writeback_valid), \
.scope_writeback_warp_num (scope_writeback_warp_num), \
.scope_writeback_wb (scope_writeback_wb), \
.scope_writeback_rd (scope_writeback_rd), \
.scope_writeback_data (scope_writeback_data),
`define SCOPE_ASSIGN(d,s) assign d = s
`else
`define SCOPE_SIGNALS_ISTAGE_IO
`define SCOPE_SIGNALS_LSU_IO
`define SCOPE_SIGNALS_CORE_IO
`define SCOPE_SIGNALS_ICACHE_IO
`define SCOPE_SIGNALS_PIPELINE_IO
`define SCOPE_SIGNALS_BE_IO
`define SCOPE_SIGNALS_ISTAGE_BIND
`define SCOPE_SIGNALS_LSU_BIND
`define SCOPE_SIGNALS_CORE_BIND
`define SCOPE_SIGNALS_ICACHE_BIND
`define SCOPE_SIGNALS_PIPELINE_BIND
`define SCOPE_SIGNALS_BE_BIND
`define SCOPE_ASSIGN(d,s)
`endif
// VX_SCOPE
`endif

22
hw/rtl/Vortex.v
View File

@@ -3,9 +3,11 @@
module Vortex #(
parameter CORE_ID = 0
) (
`SCOPE_SIGNALS_ICACHE_IO
`SCOPE_SIGNALS_DCACHE_IO
`SCOPE_SIGNALS_ISTAGE_IO
`SCOPE_SIGNALS_LSU_IO
`SCOPE_SIGNALS_CORE_IO
`SCOPE_SIGNALS_ICACHE_IO
`SCOPE_SIGNALS_PIPELINE_IO
`SCOPE_SIGNALS_BE_IO
// Clock
@@ -169,10 +171,10 @@ module Vortex #(
VX_pipeline #(
.CORE_ID(CORE_ID)
) pipeline (
`SCOPE_SIGNALS_ICACHE_ATTACH
`SCOPE_SIGNALS_DCACHE_ATTACH
`SCOPE_SIGNALS_CORE_ATTACH
`SCOPE_SIGNALS_BE_ATTACH
`SCOPE_SIGNALS_ISTAGE_BIND
`SCOPE_SIGNALS_LSU_BIND
`SCOPE_SIGNALS_PIPELINE_BIND
`SCOPE_SIGNALS_BE_BIND
.clk(clk),
.reset(reset),
@@ -232,9 +234,11 @@ module Vortex #(
assign snp_rsp_tag = dcache_snp_rsp_if.snp_rsp_tag;
assign dcache_snp_rsp_if.snp_rsp_ready = snp_rsp_ready;
VX_mem_ctrl #(
VX_mem_unit #(
.CORE_ID(CORE_ID)
) mem_ctrl (
) mem_unit (
`SCOPE_SIGNALS_ICACHE_BIND
.clk (clk),
.reset (reset),
@@ -269,7 +273,7 @@ module Vortex #(
.core_io_rsp_if (arb_io_rsp_if),
.core_rsp_if (core_dcache_rsp_if)
);
endmodule // Vortex

16
hw/rtl/Vortex_Cluster.v
View File

@@ -3,9 +3,11 @@
module Vortex_Cluster #(
parameter CLUSTER_ID = 0
) (
`SCOPE_SIGNALS_ICACHE_IO
`SCOPE_SIGNALS_DCACHE_IO
`SCOPE_SIGNALS_ISTAGE_IO
`SCOPE_SIGNALS_LSU_IO
`SCOPE_SIGNALS_CORE_IO
`SCOPE_SIGNALS_ICACHE_IO
`SCOPE_SIGNALS_PIPELINE_IO
`SCOPE_SIGNALS_BE_IO
// Clock
@@ -115,10 +117,12 @@ module Vortex_Cluster #(
Vortex #(
.CORE_ID(i + (CLUSTER_ID * `NUM_CORES))
) vortex_core (
`SCOPE_SIGNALS_ICACHE_ATTACH
`SCOPE_SIGNALS_DCACHE_ATTACH
`SCOPE_SIGNALS_CORE_ATTACH
`SCOPE_SIGNALS_BE_ATTACH
`SCOPE_SIGNALS_ISTAGE_BIND
`SCOPE_SIGNALS_LSU_BIND
`SCOPE_SIGNALS_CORE_BIND
`SCOPE_SIGNALS_ICACHE_BIND
`SCOPE_SIGNALS_PIPELINE_BIND
`SCOPE_SIGNALS_BE_BIND
.clk (clk),
.reset (reset),

28
hw/rtl/Vortex_Socket.v
View File

@@ -1,9 +1,11 @@
`include "VX_define.vh"
module Vortex_Socket (
`SCOPE_SIGNALS_ICACHE_IO
`SCOPE_SIGNALS_DCACHE_IO
`SCOPE_SIGNALS_ISTAGE_IO
`SCOPE_SIGNALS_LSU_IO
`SCOPE_SIGNALS_CORE_IO
`SCOPE_SIGNALS_ICACHE_IO
`SCOPE_SIGNALS_PIPELINE_IO
`SCOPE_SIGNALS_BE_IO
// Clock
@@ -61,10 +63,12 @@ module Vortex_Socket (
Vortex_Cluster #(
.CLUSTER_ID(`L3CACHE_ID)
) Vortex_Cluster (
`SCOPE_SIGNALS_ICACHE_ATTACH
`SCOPE_SIGNALS_DCACHE_ATTACH
`SCOPE_SIGNALS_CORE_ATTACH
`SCOPE_SIGNALS_BE_ATTACH
`SCOPE_SIGNALS_ISTAGE_BIND
`SCOPE_SIGNALS_LSU_BIND
`SCOPE_SIGNALS_CORE_BIND
`SCOPE_SIGNALS_ICACHE_BIND
`SCOPE_SIGNALS_PIPELINE_BIND
`SCOPE_SIGNALS_BE_BIND
.clk (clk),
.reset (reset),
@@ -155,10 +159,12 @@ module Vortex_Socket (
Vortex_Cluster #(
.CLUSTER_ID(i)
) Vortex_Cluster (
`SCOPE_SIGNALS_ICACHE_ATTACH
`SCOPE_SIGNALS_DCACHE_ATTACH
`SCOPE_SIGNALS_CORE_ATTACH
`SCOPE_SIGNALS_BE_ATTACH
`SCOPE_SIGNALS_ISTAGE_BIND
`SCOPE_SIGNALS_LSU_BIND
`SCOPE_SIGNALS_CORE_BIND
`SCOPE_SIGNALS_ICACHE_BIND
`SCOPE_SIGNALS_PIPELINE_BIND
`SCOPE_SIGNALS_BE_BIND
.clk (clk),
.reset (reset),
@@ -387,7 +393,7 @@ module Vortex_Socket (
end
`ifdef DBG_PRINT_DRAM
always_ff @(posedge clk) begin
always @(posedge clk) begin
if (dram_req_valid && dram_req_ready) begin
$display("%t: DRAM req: rw=%b addr=%0h, tag=%0h, byteen=%0h data=%0h", $time, dram_req_rw, `DRAM_TO_BYTE_ADDR(dram_req_addr), dram_req_tag, dram_req_byteen, dram_req_data);
end

169
hw/rtl/cache/VX_bank.v vendored
View File

@@ -101,7 +101,7 @@ module VX_bank #(
input wire snp_rsp_ready
);
`DEBUG_BLOCK(
`ifdef DBG_CORE_REQ_INFO
wire[31:0] debug_use_pc_st0;
wire[1:0] debug_wb_st0;
wire[4:0] debug_rd_st0;
@@ -128,7 +128,7 @@ module VX_bank #(
wire[WORD_SIZE-1:0] debug_byteen_st2;
wire[`REQS_BITS-1:0] debug_tid_st2;
wire[`UP(CORE_TAG_ID_BITS)-1:0] debug_tagid_st2;
)
`endif
wire snrq_pop;
wire snrq_empty;
@@ -300,7 +300,6 @@ module VX_bank #(
wire qual_is_snp_st0;
wire qual_snp_invalidate_st0;
wire valid_st1 [STAGE_1_CYCLES-1:0];
wire [`LINE_ADDR_WIDTH-1:0] addr_st1 [STAGE_1_CYCLES-1:0];
wire [`UP(`WORD_SELECT_WIDTH)-1:0] wsel_st1 [STAGE_1_CYCLES-1:0];
@@ -313,17 +312,17 @@ module VX_bank #(
assign qual_is_fill_st0 = dfpq_pop_unqual;
assign qual_valid_st0 = dfpq_pop || mrvq_pop || reqq_pop || snrq_pop;
assign qual_valid_st0 = dfpq_pop || mrvq_pop || reqq_pop || snrq_pop;
assign qual_addr_st0 = dfpq_pop_unqual ? dfpq_addr_st0 :
mrvq_pop_unqual ? mrvq_addr_st0 :
reqq_pop_unqual ? reqq_req_addr_st0[`LINE_SELECT_ADDR_RNG] :
snrq_pop_unqual ? snrq_addr_st0 :
0;
assign qual_addr_st0 = dfpq_pop_unqual ? dfpq_addr_st0 :
mrvq_pop_unqual ? mrvq_addr_st0 :
reqq_pop_unqual ? reqq_req_addr_st0[`LINE_SELECT_ADDR_RNG] :
snrq_pop_unqual ? snrq_addr_st0 :
0;
if (`WORD_SELECT_WIDTH != 0) begin
assign qual_wsel_st0 = reqq_pop_unqual ? reqq_req_addr_st0[`WORD_SELECT_WIDTH-1:0] :
mrvq_pop_unqual ? mrvq_wsel_st0 :
0;
assign qual_wsel_st0 = reqq_pop_unqual ? reqq_req_addr_st0[`WORD_SELECT_WIDTH-1:0] :
mrvq_pop_unqual ? mrvq_wsel_st0 :
0;
end else begin
`UNUSED_VAR(mrvq_wsel_st0)
assign qual_wsel_st0 = 0;
@@ -355,11 +354,11 @@ module VX_bank #(
assign qual_from_mrvq_st0 = mrvq_pop_unqual;
`DEBUG_BLOCK(
`ifdef DBG_CORE_REQ_INFO
if (WORD_SIZE != `GLOBAL_BLOCK_SIZE) begin
assign {debug_use_pc_st0, debug_wb_st0, debug_rd_st0, debug_warp_num_st0, debug_tagid_st0, debug_rw_st0, debug_byteen_st0, debug_tid_st0} = qual_inst_meta_st0;
end
)
`endif
VX_generic_register #(
.N(1 + 1 + 1 + 1 + 1 + `LINE_ADDR_WIDTH + `UP(`WORD_SELECT_WIDTH) + `WORD_WIDTH + `REQ_INST_META_WIDTH + 1 + `BANK_LINE_WIDTH)
@@ -408,18 +407,23 @@ module VX_bank #(
wire from_mrvq_st1e;
wire mrvq_recover_ready_state_st1e;
assign from_mrvq_st1e = from_mrvq_st1[STAGE_1_CYCLES-1];
assign from_mrvq_st1e = from_mrvq_st1[STAGE_1_CYCLES-1];
assign valid_st1e = valid_st1 [STAGE_1_CYCLES-1];
assign is_snp_st1e = is_snp_st1 [STAGE_1_CYCLES-1];
assign snp_invalidate_st1e = snp_invalidate_st1 [STAGE_1_CYCLES-1];
assign {tag_st1e, mem_rw_st1e, mem_byteen_st1e, tid_st1e} = inst_meta_st1[STAGE_1_CYCLES-1];
assign st2_pending_hazard_st1e = (miss_add_because_miss) && ((addr_st2 == addr_st1[STAGE_1_CYCLES-1]) && !is_fill_st2);
assign st2_pending_hazard_st1e = (miss_add_because_miss)
&& ((addr_st2 == addr_st1[STAGE_1_CYCLES-1]) && !is_fill_st2);
assign force_request_miss_st1e = (valid_st1e && !from_mrvq_st1e && (mrvq_pending_hazard_st1e || st2_pending_hazard_st1e)) || (valid_st1e && from_mrvq_st1e && recover_mrvq_state_st2);
assign force_request_miss_st1e = (valid_st1e && !from_mrvq_st1e && (mrvq_pending_hazard_st1e || st2_pending_hazard_st1e))
|| (valid_st1e && from_mrvq_st1e && recover_mrvq_state_st2);
assign mrvq_recover_ready_state_st1e = valid_st1e && from_mrvq_st1e && recover_mrvq_state_st2 && (addr_st2 == addr_st1[STAGE_1_CYCLES-1]);
assign mrvq_recover_ready_state_st1e = valid_st1e
&& from_mrvq_st1e
&& recover_mrvq_state_st2
&& (addr_st2 == addr_st1[STAGE_1_CYCLES-1]);
VX_tag_data_access #(
.CACHE_SIZE (CACHE_SIZE),
@@ -466,11 +470,12 @@ module VX_bank #(
.mrvq_init_ready_state_st1e(mrvq_init_ready_state_st1e)
);
`DEBUG_BLOCK(
`ifdef DBG_CORE_REQ_INFO
if (WORD_SIZE != `GLOBAL_BLOCK_SIZE) begin
assign {debug_use_pc_st1e, debug_wb_st1e, debug_rd_st1e, debug_warp_num_st1e, debug_tagid_st1e, debug_rw_st1e, debug_byteen_st1e, debug_tid_st1e} = inst_meta_st1[STAGE_1_CYCLES-1];
end
)
`endif
wire qual_valid_st1e_2 = valid_st1e && !is_fill_st1[STAGE_1_CYCLES-1];
wire from_mrvq_st1e_st2 = from_mrvq_st1e;
@@ -506,11 +511,11 @@ module VX_bank #(
.out ({mrvq_recover_ready_state_st2 , from_mrvq_st2 , mrvq_init_ready_state_unqual_st2, snp_to_mrvq_st2 , is_snp_st2 , snp_invalidate_st2, fill_saw_dirty_st2 , is_fill_st2 , valid_st2 , addr_st2 , wsel_st2, writeword_st2 , readword_st2 , readdata_st2 , readtag_st2 , miss_st2 , dirty_st2 , dirtyb_st2, inst_meta_st2 })
);
`DEBUG_BLOCK(
`ifdef DBG_CORE_REQ_INFO
if (WORD_SIZE != `GLOBAL_BLOCK_SIZE) begin
assign {debug_use_pc_st2, debug_wb_st2, debug_rd_st2, debug_warp_num_st2, debug_tagid_st2, debug_rw_st2, debug_byteen_st2, debug_tid_st2} = inst_meta_st2;
end
)
`endif
// Enqueue to miss reserv if it's a valid miss
assign miss_add_because_miss = valid_st2 && !is_snp_st2 && miss_st2;
@@ -539,7 +544,9 @@ module VX_bank #(
assign mrvq_init_ready_state_hazard_st0_st1 = miss_add_unqual && qual_is_fill_st0 && (miss_add_addr == qual_addr_st0 );
assign mrvq_init_ready_state_hazard_st1e_st1 = miss_add_unqual && is_fill_st1[STAGE_1_CYCLES-1] && (miss_add_addr == addr_st1[STAGE_1_CYCLES-1]);
assign mrvq_init_ready_state_st2 = mrvq_init_ready_state_unqual_st2 || mrvq_init_ready_state_hazard_st0_st1 || mrvq_init_ready_state_hazard_st1e_st1;
assign mrvq_init_ready_state_st2 = mrvq_init_ready_state_unqual_st2
|| mrvq_init_ready_state_hazard_st0_st1
|| mrvq_init_ready_state_hazard_st1e_st1;
VX_cache_miss_resrv #(
.BANK_ID (BANK_ID),
@@ -592,10 +599,8 @@ module VX_bank #(
// Enqueue core response
wire cwbq_push;
wire cwbq_pop;
wire cwbq_empty;
wire cwbq_full;
wire cwbq_push, cwbq_pop;
wire cwbq_empty, cwbq_full;
wire cwbq_push_unqual = valid_st2 && !miss_st2 && !is_fill_st2 && !is_snp_st2;
assign cwbq_push_stall = cwbq_push_unqual && cwbq_full;
@@ -634,42 +639,22 @@ module VX_bank #(
// Enqueue DRAM fill request
// `IGNORE_WARNINGS_BEGIN
// wire invalidate_fill;
// `IGNORE_WARNINGS_END
// wire possible_fill = valid_st2 && miss_st2 && dram_fill_req_ready && ~is_snp_st2;
// wire [`LINE_ADDR_WIDTH-1:0] fill_invalidator_addr = addr_st2;
wire dram_fill_req_unqual = miss_add_unqual
&& (!mrvq_init_ready_state_st2
|| (from_mrvq_st2 && !mrvq_recover_ready_state_st2));
// VX_fill_invalidator #(
// .BANK_LINE_SIZE (BANK_LINE_SIZE),
// .NUM_BANKS (NUM_BANKS),
// .FILL_INVALIDAOR_SIZE (FILL_INVALIDAOR_SIZE)
// ) fill_invalidator (
// .clk (clk),
// .reset (reset),
// .possible_fill (possible_fill),
// .success_fill (is_fill_st2),
// .fill_addr (fill_invalidator_addr),
// .invalidate_fill (invalidate_fill)
// );
wire dram_fill_req_unqual = miss_add_unqual && (!mrvq_init_ready_state_st2 || (from_mrvq_st2 && !mrvq_recover_ready_state_st2));
assign dram_fill_req_valid = dram_fill_req_unqual
&& dram_fill_req_ready
&& !( dwbq_push_stall
|| mrvq_push_stall
|| cwbq_push_stall);
assign dram_fill_req_valid = dram_fill_req_unqual
&& !(dwbq_push_stall
|| mrvq_push_stall
|| cwbq_push_stall);
assign dram_fill_req_addr = addr_st2;
assign dram_fill_req_stall = dram_fill_req_unqual && ~dram_fill_req_ready;
// Enqueue DRAM writeback request
wire dwbq_push;
wire dwbq_pop;
wire dwbq_empty;
wire dwbq_full;
wire dwbq_push, dwbq_pop;
wire dwbq_empty, dwbq_full;
wire dwbq_is_dwb_in, dwbq_is_snp_in;
wire dwbq_is_dwb_out, dwbq_is_snp_out;
@@ -724,9 +709,9 @@ module VX_bank #(
assign dram_wb_req_valid = ~dwbq_empty && dwbq_is_dwb_out && (~dwbq_is_snp_out || dwbq_dual_valid_sel == 0);
assign snp_rsp_valid = ~dwbq_empty && dwbq_is_snp_out && (~dwbq_is_dwb_out || dwbq_dual_valid_sel == 1);
assign dwbq_pop = (dwbq_is_dwb_out && ~dwbq_is_snp_out && dram_wb_req_fire)
|| (dwbq_is_snp_out && ~dwbq_is_dwb_out && snp_rsp_fire)
|| (dwbq_is_dwb_out && dwbq_is_snp_out && snp_rsp_fire);
assign dwbq_pop = (dwbq_is_dwb_out && ~dwbq_is_snp_out && dram_wb_req_fire)
|| (dwbq_is_snp_out && ~dwbq_is_dwb_out && snp_rsp_fire)
|| (dwbq_is_dwb_out && dwbq_is_snp_out && snp_rsp_fire);
// bank pipeline stall
assign stall_bank_pipe = cwbq_push_stall
@@ -735,53 +720,27 @@ module VX_bank #(
|| dram_fill_req_stall;
`ifdef DBG_PRINT_CACHE_BANK
if (NUM_BANKS == 1) begin
always_ff @(posedge clk) begin
if (core_req_valid && core_req_ready) begin
$display("%t: bank%0d-%0d core req: addr=%0h, tag=%0h", $time, CACHE_ID, BANK_ID, `LINE_TO_BYTE_ADDR0(core_req_addr), core_req_tag);
end
if (core_rsp_valid && core_rsp_ready) begin
$display("%t: bank%0d-%0d core rsp: tag=%0h, data=%0h", $time, CACHE_ID, BANK_ID, core_rsp_tag, core_rsp_data);
end
if (dram_fill_req_valid && dram_fill_req_ready) begin
$display("%t: bank%0d-%0d dram_fill req: addr=%0h", $time, CACHE_ID, BANK_ID, `LINE_TO_BYTE_ADDR0(dram_fill_req_addr));
end
if (dram_wb_req_valid && dram_wb_req_ready) begin
$display("%t: bank%0d-%0d dram_wb req: addr=%0h, data=%0h", $time, CACHE_ID, BANK_ID, `LINE_TO_BYTE_ADDR0(dram_wb_req_addr), dram_wb_req_data);
end
if (dram_fill_rsp_valid && dram_fill_rsp_ready) begin
$display("%t: bank%0d-%0d dram_fill rsp: addr=%0h, data=%0h", $time, CACHE_ID, BANK_ID, `LINE_TO_BYTE_ADDR0(dram_fill_rsp_addr), dram_fill_rsp_data);
end
if (snp_req_valid && snp_req_ready) begin
$display("%t: bank%0d-%0d snp req: addr=%0h, tag=%0h", $time, CACHE_ID, BANK_ID, `LINE_TO_BYTE_ADDR0(snp_req_addr), snp_req_tag);
end
if (snp_rsp_valid && snp_rsp_ready) begin
$display("%t: bank%0d-%0d snp rsp: tag=%0h", $time, CACHE_ID, BANK_ID, snp_rsp_tag);
end
always @(posedge clk) begin
if ((|core_req_valid) && core_req_ready) begin
$display("%t: bank%0d-%0d core req: addr=%0h, tag=%0h", $time, CACHE_ID, BANK_ID, `LINE_TO_BYTE_ADDR(core_req_addr, BANK_ID), core_req_tag);
end
end else begin
always_ff @(posedge clk) begin
if ((|core_req_valid) && core_req_ready) begin
$display("%t: bank%0d-%0d core req: addr=%0h, tag=%0h", $time, CACHE_ID, BANK_ID, `LINE_TO_BYTE_ADDR(core_req_addr, BANK_ID), core_req_tag);
end
if (core_rsp_valid && core_rsp_ready) begin
$display("%t: bank%0d-%0d core rsp: tag=%0h, data=%0h", $time, CACHE_ID, BANK_ID, core_rsp_tag, core_rsp_data);
end
if (dram_fill_req_valid && dram_fill_req_ready) begin
$display("%t: bank%0d-%0d dram_fill req: addr=%0h", $time, CACHE_ID, BANK_ID, `LINE_TO_BYTE_ADDR(dram_fill_req_addr, BANK_ID));
end
if (dram_wb_req_valid && dram_wb_req_ready) begin
$display("%t: bank%0d-%0d dram_wb req: addr=%0h, data=%0h", $time, CACHE_ID, BANK_ID, `LINE_TO_BYTE_ADDR(dram_wb_req_addr, BANK_ID), dram_wb_req_data);
end
if (dram_fill_rsp_valid && dram_fill_rsp_ready) begin
$display("%t: bank%0d-%0d dram_fill rsp: addr=%0h, data=%0h", $time, CACHE_ID, BANK_ID, `LINE_TO_BYTE_ADDR(dram_fill_rsp_addr, BANK_ID), dram_fill_rsp_data);
end
if (snp_req_valid && snp_req_ready) begin
$display("%t: bank%0d-%0d snp req: addr=%0h, invalidate=%0d, tag=%0h", $time, CACHE_ID, BANK_ID, `LINE_TO_BYTE_ADDR(snp_req_addr, BANK_ID), snp_req_invalidate, snp_req_tag);
end
if (snp_rsp_valid && snp_rsp_ready) begin
$display("%t: bank%0d-%0d snp rsp: tag=%0h", $time, CACHE_ID, BANK_ID, snp_rsp_tag);
end
if (core_rsp_valid && core_rsp_ready) begin
$display("%t: bank%0d-%0d core rsp: tag=%0h, data=%0h", $time, CACHE_ID, BANK_ID, core_rsp_tag, core_rsp_data);
end
if (dram_fill_req_valid && dram_fill_req_ready) begin
$display("%t: bank%0d-%0d dram_fill req: addr=%0h", $time, CACHE_ID, BANK_ID, `LINE_TO_BYTE_ADDR(dram_fill_req_addr, BANK_ID));
end
if (dram_wb_req_firevalid && dram_wb_req_ready) begin
$display("%t: bank%0d-%0d dram_wb req: addr=%0h, data=%0h", $time, CACHE_ID, BANK_ID, `LINE_TO_BYTE_ADDR(dram_wb_req_addr, BANK_ID), dram_wb_req_data);
end
if (dram_fill_rsp_valid && dram_fill_rsp_ready) begin
$display("%t: bank%0d-%0d dram_fill rsp: addr=%0h, data=%0h", $time, CACHE_ID, BANK_ID, `LINE_TO_BYTE_ADDR(dram_fill_rsp_addr, BANK_ID), dram_fill_rsp_data);
end
if (snp_req_valid && snp_req_ready) begin
$display("%t: bank%0d-%0d snp req: addr=%0h, invalidate=%0d, tag=%0h", $time, CACHE_ID, BANK_ID, `LINE_TO_BYTE_ADDR(snp_req_addr, BANK_ID), snp_req_invalidate, snp_req_tag);
end
if (snp_rsp_valid && snp_rsp_ready) begin
$display("%t: bank%0d-%0d snp rsp: tag=%0h", $time, CACHE_ID, BANK_ID, snp_rsp_tag);
end
end
`endif

17
hw/rtl/cache/VX_cache.v vendored
View File

@@ -65,6 +65,8 @@ module VX_cache #(
// Snooping forward tag width
parameter SNP_FWD_TAG_WIDTH = 1
) (
`SCOPE_SIGNALS_ICACHE_IO
input wire clk,
input wire reset,
@@ -125,7 +127,7 @@ module VX_cache #(
output wire [NUM_SNP_REQUESTS-1:0] snp_fwdin_ready
);
`DEBUG_BLOCK(
`ifdef DBG_CORE_REQ_INFO
wire[31:0] debug_core_req_use_pc;
wire[1:0] debug_core_req_wb;
wire[4:0] debug_core_req_rd;
@@ -135,7 +137,8 @@ module VX_cache #(
if (WORD_SIZE != `GLOBAL_BLOCK_SIZE) begin
assign {debug_core_req_use_pc, debug_core_req_wb, debug_core_req_rd, debug_core_req_warp_num, debug_core_req_idx} = core_req_tag[0];
end
)
`endif
wire [NUM_BANKS-1:0][NUM_REQUESTS-1:0] per_bank_valid;
wire [NUM_BANKS-1:0] per_bank_core_req_ready;
@@ -476,7 +479,13 @@ module VX_cache #(
.per_bank_snp_rsp_ready (per_bank_snp_rsp_ready),
.snp_rsp_valid (snp_rsp_valid),
.snp_rsp_tag (snp_rsp_tag),
.snp_rsp_ready (snp_rsp_ready)
);
.snp_rsp_ready (snp_rsp_ready)
);
`SCOPE_ASSIGN(scope_idram_req_valid, per_bank_dram_fill_req_valid[0]);
`SCOPE_ASSIGN(scope_idram_req_ready, dram_fill_req_ready);
`SCOPE_ASSIGN(scope_idram_rsp_valid, per_bank_core_rsp_valid[0]);
`SCOPE_ASSIGN(scope_idram_rsp_ready, per_bank_core_rsp_ready[0]);
endmodule

4
hw/rtl/cache/VX_cache_config.vh vendored
View File

@@ -72,8 +72,6 @@
`define LINE_TO_DRAM_ADDR(x, i) {x, `BANK_SELECT_BITS'(i)}
`define LINE_TO_BYTE_ADDR(x, i) {x, `BANK_SELECT_BITS'(i), `BASE_ADDR_BITS'(0)}
`define LINE_TO_BYTE_ADDR0(x) {x, `BASE_ADDR_BITS'(0)}
`define LINE_TO_BYTE_ADDR(x, i) {x, (((`BANK_SELECT_BITS + `BASE_ADDR_BITS)'(i)) << `BASE_ADDR_BITS)}
`endif

45
hw/rtl/cache/VX_cache_miss_resrv.v vendored
View File

@@ -151,38 +151,21 @@ module VX_cache_miss_resrv #(
end
end
`ifdef DBG_PRINT_CACHE_MSRQ
`ifdef DBG_PRINT_CACHE_MSRQ
integer j;
if (NUM_BANKS == 1) begin
always_ff @(posedge clk) begin
if (mrvq_push || mrvq_pop || increment_head || recover_state) begin
$write("%t: bank%0d-%0d msrq: push=%b pop=%b incr=%d recv=%d", $time, CACHE_ID, BANK_ID, mrvq_push, mrvq_pop, increment_head, recover_state);
for (j = 0; j < MRVQ_SIZE; j++) begin
if (valid_table[j]) begin
$write(" ");
if (schedule_ptr == $bits(schedule_ptr)'(j)) $write("*");
if (~ready_table[j]) $write("!");
$write("addr%0d=%0h", j, {addr_table[j], `BASE_ADDR_BITS'(0)});
end
end
$write("\n");
end
end
end else begin
always_ff @(posedge clk) begin
if (mrvq_push || mrvq_pop || increment_head || recover_state) begin
$write("%t: bank%0d-%0d msrq: push=%b pop=%b incr=%d recv=%d", $time, CACHE_ID, BANK_ID, mrvq_push, mrvq_pop, increment_head, recover_state);
for (j = 0; j < MRVQ_SIZE; j++) begin
if (valid_table[j]) begin
$write(" ");
if (schedule_ptr == $bits(schedule_ptr)'(j)) $write("*");
if (~ready_table[j]) $write("!");
$write("addr%0d=%0h", j, `LINE_TO_BYTE_ADDR(addr_table[j], BANK_ID));
end
end
$write("\n");
end
end
always @(posedge clk) begin
if (mrvq_push || mrvq_pop || increment_head || recover_state) begin
$write("%t: bank%0d-%0d msrq: push=%b pop=%b incr=%d recv=%d", $time, CACHE_ID, BANK_ID, mrvq_push, mrvq_pop, increment_head, recover_state);
for (j = 0; j < MRVQ_SIZE; j++) begin
if (valid_table[j]) begin
$write(" ");
if (schedule_ptr == $bits(schedule_ptr)'(j)) $write("*");
if (~ready_table[j]) $write("!");
$write("addr%0d=%0h", j, `LINE_TO_BYTE_ADDR(addr_table[j], BANK_ID));
end
end
$write("\n");
end
end
`endif

2
hw/rtl/cache/VX_snp_forwarder.v vendored
View File

@@ -116,7 +116,7 @@ module VX_snp_forwarder #(
end
`ifdef DBG_PRINT_CACHE_SNP
always_ff @(posedge clk) begin
always @(posedge clk) begin
if (snp_req_valid && snp_req_ready) begin
$display("%t: cache%0d snp req: addr=%0h, invalidate=%0d, tag=%0h", $time, CACHE_ID, `DRAM_TO_BYTE_ADDR(snp_req_addr), snp_req_invalidate, snp_req_tag);
end

159
hw/rtl/libs/VX_divide.v
View File

@@ -17,112 +17,105 @@ module VX_divide #(
output reg [WIDTHD-1:0] remainder
);
// synthesis read_comments_as_HDL on
// localparam IMPL = "quartus";
// synthesis read_comments_as_HDL off
// altera translate_off
localparam IMPL="fallback";
// altera translate_on
generate
if (NREP != DREP) begin
different_nrep_drep_not_yet_supported non_existing_module();
end
if (IMPL == "quartus") begin
`ifdef QUARTUS
localparam lpm_speed=SPEED == "HIGHEST" ? 9:5;
localparam lpm_speed=SPEED == "HIGHEST" ? 9 : 5;
lpm_divide #(
.LPM_WIDTHN(WIDTHN),
.LPM_WIDTHD(WIDTHD),
.LPM_NREPRESENTATION(NREP),
.LPM_DREPRESENTATION(DREP),
.LPM_PIPELINE(PIPELINE),
.LPM_REMAINDERPOSITIVE("FALSE"), // emulate verilog % operator
.MAXIMIZE_SPEED(lpm_speed)
) quartus_divider (
.clock(clock),
.aclr(aclr),
.clken(clken),
.numer(numer),
.denom(denom),
.quotient(quotient),
.remain(remainder)
);
end
else begin
lpm_divide #(
.LPM_WIDTHN(WIDTHN),
.LPM_WIDTHD(WIDTHD),
.LPM_NREPRESENTATION(NREP),
.LPM_DREPRESENTATION(DREP),
.LPM_PIPELINE(PIPELINE),
.LPM_REMAINDERPOSITIVE("FALSE"), // emulate verilog % operator
.MAXIMIZE_SPEED(lpm_speed)
) quartus_divider (
.clock(clock),
.aclr(aclr),
.clken(clken),
.numer(numer),
.denom(denom),
.quotient(quotient),
.remain(remainder)
);
wire [WIDTHN-1:0] numer_pipe_end;
wire [WIDTHD-1:0] denom_pipe_end;
`else
if (PIPELINE == 0) begin
assign numer_pipe_end = numer;
assign denom_pipe_end = denom;
end else begin
reg [WIDTHN-1:0] numer_pipe [0:PIPELINE-1];
reg [WIDTHD-1:0] denom_pipe [0:PIPELINE-1];
wire [WIDTHN-1:0] numer_pipe_end;
wire [WIDTHD-1:0] denom_pipe_end;
genvar i;
for (i = 0; i < PIPELINE-1; i++) begin : pipe_stages
always @(posedge clock or posedge aclr) begin
if (aclr) begin
numer_pipe[i+1] <= 0;
denom_pipe[i+1] <= 0;
end
else if (clken) begin
numer_pipe[i+1] <= numer_pipe[i];
denom_pipe[i+1] <= denom_pipe[i];
end
end
end
if (PIPELINE == 0) begin
assign numer_pipe_end = numer;
assign denom_pipe_end = denom;
end else begin
reg [WIDTHN-1:0] numer_pipe [0:PIPELINE-1];
reg [WIDTHD-1:0] denom_pipe [0:PIPELINE-1];
genvar i;
for (i = 0; i < PIPELINE-1; i++) begin : pipe_stages
always @(posedge clock or posedge aclr) begin
if (aclr) begin
numer_pipe[0] <= 0;
denom_pipe[0] <= 0;
numer_pipe[i+1] <= 0;
denom_pipe[i+1] <= 0;
end
else if (clken) begin
numer_pipe[0] <= numer;
denom_pipe[0] <= denom;
numer_pipe[i+1] <= numer_pipe[i];
denom_pipe[i+1] <= denom_pipe[i];
end
end
assign numer_pipe_end = numer_pipe[PIPELINE-1];
assign denom_pipe_end = denom_pipe[PIPELINE-1];
end
/* * * * * * * * * * * * * * * * * * * * * * */
/* Do the actual fallback computation here */
/* * * * * * * * * * * * * * * * * * * * * * */
if (NREP == "SIGNED") begin
always @(*) begin
if (denom_pipe_end == 0) begin
quotient = 32'hffffffff;
remainder = numer_pipe_end;
end
else if (denom_pipe_end == 32'hffffffff && numer_pipe_end == 32'h80000000) begin
// this edge case kills verilator in some cases by causing a division
// overflow exception. INT_MIN / -1 (on x86)
quotient = 0;
remainder = 0;
end
else begin
quotient = $signed($signed(numer_pipe_end) / $signed(denom_pipe_end));
remainder = $signed($signed(numer_pipe_end) % $signed(denom_pipe_end));
end
always @(posedge clock or posedge aclr) begin
if (aclr) begin
numer_pipe[0] <= 0;
denom_pipe[0] <= 0;
end
else if (clken) begin
numer_pipe[0] <= numer;
denom_pipe[0] <= denom;
end
end
else begin
assign quotient = (denom_pipe_end == 0) ? 32'hffffffff : numer_pipe_end/denom_pipe_end;
assign remainder = (denom_pipe_end == 0) ? numer_pipe_end : numer_pipe_end%denom_pipe_end;
end
assign numer_pipe_end = numer_pipe[PIPELINE-1];
assign denom_pipe_end = denom_pipe[PIPELINE-1];
end
/* * * * * * * * * * * * * * * * * * * * * * */
/* Do the actual fallback computation here */
/* * * * * * * * * * * * * * * * * * * * * * */
if (NREP == "SIGNED") begin
always @(*) begin
if (denom_pipe_end == 0) begin
quotient = 32'hffffffff;
remainder = numer_pipe_end;
end
else if (denom_pipe_end == 32'hffffffff
&& numer_pipe_end == 32'h80000000) begin
// this edge case kills verilator in some cases by causing a division
// overflow exception. INT_MIN / -1 (on x86)
quotient = 0;
remainder = 0;
end
else begin
quotient = $signed($signed(numer_pipe_end) / $signed(denom_pipe_end));
remainder = $signed($signed(numer_pipe_end) % $signed(denom_pipe_end));
end
end
end
else begin
assign quotient = (denom_pipe_end == 0) ? 32'hffffffff : numer_pipe_end/denom_pipe_end;
assign remainder = (denom_pipe_end == 0) ? numer_pipe_end : numer_pipe_end%denom_pipe_end;
end
`endif
endgenerate
endmodule : VX_divide

14
hw/rtl/libs/VX_generic_priority_encoder.v
View File

@@ -2,21 +2,17 @@
module VX_generic_priority_encoder #(
parameter N = 1
) (
input wire[N-1:0] valids,
//output reg[$clog2(N)-1:0] index,
output reg[(`LOG2UP(N))-1:0] index,
//output reg[`LOG2UP(N):0] index, // eh
output reg found
);
) (
input wire[N-1:0] valids,
output reg[(`LOG2UP(N))-1:0] index,
output reg found
);
integer i;
always @(*) begin
index = 0;
found = 0;
for (i = N-1; i >= 0; i = i - 1) begin
if (valids[i]) begin
//index = i[$clog2(N)-1:0];
index = i[(`LOG2UP(N))-1:0];
found = 1;
end

2
hw/rtl/libs/VX_generic_queue.v
View File

@@ -132,7 +132,7 @@ module VX_generic_queue #(
rd_ptr_r <= rd_ptr_next_r;
if (SIZE > 2) begin
rd_ptr_next_r <= rd_ptr_r + 2;
rd_ptr_next_r <= rd_ptr_r + $bits(rd_ptr_r)'(2);
end else begin // (SIZE == 2);
rd_ptr_next_r <= ~rd_ptr_next_r;
end

160
hw/rtl/libs/VX_mult.v
View File

@@ -19,110 +19,102 @@ module VX_mult #(
output reg [WIDTHP-1:0] result
);
// synthesis read_comments_as_HDL on
// localparam IMPL = "quartus";
// synthesis read_comments_as_HDL off
// altera translate_off
localparam IMPL="fallback";
// altera translate_on
generate
if (IMPL == "quartus") begin
`ifdef QUARTUS
localparam lpm_speed = (SPEED == "HIGHEST") ? 10 : 5;
if (FORCE_LE == "YES") begin
lpm_mult #(
.LPM_WIDTHA(WIDTHA),
.LPM_WIDTHB(WIDTHB),
.LPM_WIDTHP(WIDTHP),
.LPM_REPRESENTATION(REP),
.LPM_PIPELINE(PIPELINE),
.DSP_BLOCK_BALANCING("LOGIC ELEMENTS"),
.MAXIMIZE_SPEED(lpm_speed)
) quartus_mult (
.clock(clock),
.aclr(aclr),
.clken(clken),
.dataa(dataa),
.datab(datab),
.result(result)
);
end
else begin
lpm_mult#(
.LPM_WIDTHA(WIDTHA),
.LPM_WIDTHB(WIDTHB),
.LPM_WIDTHP(WIDTHP),
.LPM_REPRESENTATION(REP),
.LPM_PIPELINE(PIPELINE),
.MAXIMIZE_SPEED(lpm_speed)
) quartus_mult(
.clock(clock),
.aclr(aclr),
.clken(clken),
.dataa(dataa),
.datab(datab),
.result(result)
);
end
localparam lpm_speed = (SPEED == "HIGHEST") ? 10 : 5;
if (FORCE_LE == "YES") begin
lpm_mult #(
.LPM_WIDTHA(WIDTHA),
.LPM_WIDTHB(WIDTHB),
.LPM_WIDTHP(WIDTHP),
.LPM_REPRESENTATION(REP),
.LPM_PIPELINE(PIPELINE),
.DSP_BLOCK_BALANCING("LOGIC ELEMENTS"),
.MAXIMIZE_SPEED(lpm_speed)
) quartus_mult (
.clock(clock),
.aclr(aclr),
.clken(clken),
.dataa(dataa),
.datab(datab),
.result(result)
);
end
else begin
lpm_mult#(
.LPM_WIDTHA(WIDTHA),
.LPM_WIDTHB(WIDTHB),
.LPM_WIDTHP(WIDTHP),
.LPM_REPRESENTATION(REP),
.LPM_PIPELINE(PIPELINE),
.MAXIMIZE_SPEED(lpm_speed)
) quartus_mult(
.clock(clock),
.aclr(aclr),
.clken(clken),
.dataa(dataa),
.datab(datab),
.result(result)
);
end
wire [WIDTHA-1:0] dataa_pipe_end;
wire [WIDTHB-1:0] datab_pipe_end;
`else
wire [WIDTHA-1:0] dataa_pipe_end;
wire [WIDTHB-1:0] datab_pipe_end;
if (PIPELINE == 0) begin
assign dataa_pipe_end = dataa;
assign datab_pipe_end = datab;
end else begin
reg [WIDTHA-1:0] dataa_pipe [0:PIPELINE-1];
reg [WIDTHB-1:0] datab_pipe [0:PIPELINE-1];
genvar i;
for (i = 0; i < PIPELINE-1; i++) begin : pipe_stages
always @(posedge clock or posedge aclr) begin
if (aclr) begin
dataa_pipe[i+1] <= 0;
datab_pipe[i+1] <= 0;
end
else if (clken) begin
dataa_pipe[i+1] <= dataa_pipe[i];
datab_pipe[i+1] <= datab_pipe[i];
end
end
end
if (PIPELINE == 0) begin
assign dataa_pipe_end = dataa;
assign datab_pipe_end = datab;
end else begin
reg [WIDTHA-1:0] dataa_pipe [0:PIPELINE-1];
reg [WIDTHB-1:0] datab_pipe [0:PIPELINE-1];
genvar i;
for (i = 0; i < PIPELINE-1; i++) begin : pipe_stages
always @(posedge clock or posedge aclr) begin
if (aclr) begin
dataa_pipe[0] <= 0;
datab_pipe[0] <= 0;
dataa_pipe[i+1] <= 0;
datab_pipe[i+1] <= 0;
end
else if (clken) begin
dataa_pipe[0] <= dataa;
datab_pipe[0] <= datab;
dataa_pipe[i+1] <= dataa_pipe[i];
datab_pipe[i+1] <= datab_pipe[i];
end
end
assign dataa_pipe_end = dataa_pipe[PIPELINE-1];
assign datab_pipe_end = datab_pipe[PIPELINE-1];
end
/* * * * * * * * * * * * * * * * * * * * * * */
/* Do the actual fallback computation here */
/* * * * * * * * * * * * * * * * * * * * * * */
if (REP == "SIGNED") begin
assign result = $signed($signed(dataa_pipe_end)*$signed(datab_pipe_end));
end
else begin
assign result = dataa_pipe_end*datab_pipe_end;
always @(posedge clock or posedge aclr) begin
if (aclr) begin
dataa_pipe[0] <= 0;
datab_pipe[0] <= 0;
end
else if (clken) begin
dataa_pipe[0] <= dataa;
datab_pipe[0] <= datab;
end
end
assign dataa_pipe_end = dataa_pipe[PIPELINE-1];
assign datab_pipe_end = datab_pipe[PIPELINE-1];
end
/* * * * * * * * * * * * * * * * * * * * * * */
/* Do the actual fallback computation here */
/* * * * * * * * * * * * * * * * * * * * * * */
if (REP == "SIGNED") begin
assign result = $signed($signed(dataa_pipe_end)*$signed(datab_pipe_end));
end
else begin
assign result = dataa_pipe_end * datab_pipe_end;
end
`endif
endgenerate
endmodule: VX_mult

42
hw/rtl/libs/VX_scope.v
View File

@@ -18,26 +18,22 @@ module VX_scope #(
input wire bus_write,
input wire bus_read
);
localparam DELTA_ENABLE = (UPDW != 0);
localparam MAX_DELTA = (2 ** DELTAW) - 1;
localparam DELTA_ENABLE = (UPDW != 0);
localparam MAX_DELTA = (2 ** DELTAW) - 1;
typedef enum logic[2:0] {
CMD_GET_VALID,
CMD_GET_DATA,
CMD_GET_WIDTH,
CMD_GET_COUNT,
CMD_SET_DELAY,
CMD_SET_STOP,
CMD_RESERVED1,
CMD_RESERVED2
} cmd_t;
localparam CMD_GET_VALID = 3'd0;
localparam CMD_GET_DATA = 3'd1;
localparam CMD_GET_WIDTH = 3'd2;
localparam CMD_GET_COUNT = 3'd3;
localparam CMD_SET_DELAY = 3'd4;
localparam CMD_SET_STOP = 3'd5;
localparam CMD_RESERVED1 = 3'd6;
localparam CMD_RESERVED2 = 3'd7;
typedef enum logic[1:0] {
GET_VALID,
GET_DATA,
GET_WIDTH,
GET_COUNT
} cmd_get_t;
localparam GET_VALID = 2'd0;
localparam GET_DATA = 2'd1;
localparam GET_WIDTH = 2'd2;
localparam GET_COUNT = 2'd3;
reg [DATAW-1:0] data_store [SIZE-1:0];
reg [DELTAW-1:0] delta_store [SIZE-1:0];
@@ -84,10 +80,10 @@ module VX_scope #(
CMD_GET_VALID,
CMD_GET_DATA,
CMD_GET_WIDTH,
CMD_GET_COUNT: out_cmd <= $bits(out_cmd)'(cmd_type);
CMD_SET_DELAY: delay_val <= $bits(delay_val)'(cmd_data);
CMD_SET_STOP: waddr_end <= $bits(waddr)'(cmd_data);
default:;
CMD_GET_COUNT: out_cmd <= $bits(out_cmd)'(cmd_type);
CMD_SET_DELAY: delay_val <= $bits(delay_val)'(cmd_data);
CMD_SET_STOP: waddr_end <= $bits(waddr)'(cmd_data);
default:;
endcase
end
@@ -183,7 +179,7 @@ module VX_scope #(
end
`ifdef DBG_PRINT_SCOPE
always_ff @(posedge clk) begin
always @(posedge clk) begin
if (bus_read) begin
$display("%t: scope-read: cmd=%0d, out=0x%0h, addr=%0d", $time, out_cmd, bus_out, raddr);
end