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tex refactoring and bug fixes

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This commit is contained in:
Blaise Tine
2021-03-16 09:25:57 -04:00
parent 17424ad554
commit 676a13f30d
21 changed files with 227 additions and 154 deletions
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124
hw/rtl/VX_gpu_unit.v
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@@ -10,7 +10,10 @@ module VX_gpu_unit #(
// Inputs
VX_gpu_req_if gpu_req_if,
`ifdef EXT_TEX_ENABLE
VX_tex_csr_if tex_csr_if,
`endif
// Outputs
VX_warp_ctl_if warp_ctl_if,
@@ -18,23 +21,30 @@ module VX_gpu_unit #(
);
`UNUSED_PARAM (CORE_ID)
`UNUSED_VAR (clk)
`UNUSED_VAR (reset)
wire rsp_valid;
wire [`NW_BITS-1:0] rsp_wid;
wire [`NUM_THREADS-1:0] rsp_tmask;
wire [31:0] rsp_PC;
wire [`NR_BITS-1:0] rsp_rd;
wire rsp_wb;
wire [`NUM_THREADS-1:0][31:0] rsp_data;
gpu_tmc_t tmc;
gpu_wspawn_t wspawn;
gpu_barrier_t barrier;
gpu_split_t split;
VX_tex_req_if tex_req_if;
VX_tex_rsp_if tex_rsp_if;
wire [(`NUM_THREADS * 32)-1:0] warp_ctl_data;
wire is_warp_ctl;
wire stall_in, stall_out;
wire is_wspawn = (gpu_req_if.op_type == `GPU_WSPAWN);
wire is_tmc = (gpu_req_if.op_type == `GPU_TMC);
wire is_split = (gpu_req_if.op_type == `GPU_SPLIT);
wire is_bar = (gpu_req_if.op_type == `GPU_BAR);
wire is_tex = (gpu_req_if.op_type == `GPU_TEX);
// tmc
wire [`NUM_THREADS-1:0] tmc_new_mask;
@@ -76,10 +86,28 @@ module VX_gpu_unit #(
assign barrier.valid = is_bar;
assign barrier.id = gpu_req_if.rs1_data[0][`NB_BITS-1:0];
assign barrier.size_m1 = (`NW_BITS)'(gpu_req_if.rs2_data[0] - 1);
assign barrier.size_m1 = (`NW_BITS)'(gpu_req_if.rs2_data[0] - 1);
// pack warp ctl result
`IGNORE_WARNINGS_BEGIN
assign warp_ctl_data = {tmc, wspawn, barrier, split};
`IGNORE_WARNINGS_END
// texture
assign tex_req_if.valid = is_tex;
`ifdef EXT_TEX_ENABLE
VX_tex_req_if tex_req_if;
VX_tex_rsp_if tex_rsp_if;
wire is_tex = (gpu_req_if.op_type == `GPU_TEX);
assign tex_req_if.valid = gpu_req_if.valid && is_tex;
assign tex_req_if.wid = gpu_req_if.wid;
assign tex_req_if.tmask = gpu_req_if.tmask;
assign tex_req_if.PC = gpu_req_if.PC;
assign tex_req_if.rd = gpu_req_if.rd;
assign tex_req_if.wb = gpu_req_if.wb;
for (genvar i = 0; i < `NUM_THREADS; i++) begin
assign tex_req_if.u[i] = gpu_req_if.rs1_data[i];
@@ -87,54 +115,78 @@ module VX_gpu_unit #(
assign tex_req_if.lod_t[i] = gpu_req_if.rs3_data[i];
end
`UNUSED_VAR (tex_req_if.u)
`UNUSED_VAR (tex_req_if.v)
`UNUSED_VAR (tex_req_if.valid)
`UNUSED_VAR (tex_req_if.lod_t)
VX_tex_unit #(
.CORE_ID(CORE_ID)
) texture_unit (
.clk (clk),
.reset (reset),
.tex_req_if (tex_req_if),
.tex_csr_if (tex_csr_if),
.tex_rsp_if (tex_rsp_if)
.clk (clk),
.reset (reset),
.tex_req_if (tex_req_if),
.tex_csr_if (tex_csr_if),
.tex_rsp_if (tex_rsp_if)
);
assign gpu_req_if.valid = is_tex;
assign gpu_req_if.wb = tex_rsp_if.ready;
assign tex_rsp_if.ready = !stall_out;
assign stall_in = (is_tex && ~tex_req_if.ready)
|| (~is_tex && (tex_rsp_if.valid || stall_out));
assign is_warp_ctl = !(is_tex || tex_rsp_if.valid);
assign rsp_valid = tex_rsp_if.valid || (gpu_req_if.valid && ~is_tex);
assign rsp_wid = tex_rsp_if.valid ? tex_rsp_if.wid : gpu_req_if.wid;
assign rsp_tmask = tex_rsp_if.valid ? tex_rsp_if.tmask : gpu_req_if.tmask;
assign rsp_PC = tex_rsp_if.valid ? tex_rsp_if.PC : gpu_req_if.PC;
assign rsp_rd = tex_rsp_if.rd;
assign rsp_wb = tex_rsp_if.valid && tex_rsp_if.wb;
assign rsp_data = tex_rsp_if.valid ? tex_rsp_if.data : warp_ctl_data;
`else
assign stall_in = stall_out;
assign is_warp_ctl = 1;
assign rsp_valid = gpu_req_if.valid;
assign rsp_wid = gpu_req_if.wid;
assign rsp_tmask = gpu_req_if.tmask;
assign rsp_PC = gpu_req_if.PC;
assign rsp_rd = 0;
assign rsp_wb = 0;
assign rsp_data = warp_ctl_data;
`UNUSED_VAR (gpu_req_if.rd)
`UNUSED_VAR (gpu_req_if.wb)
`endif
wire is_warp_ctl_r;
// output
wire stall = ~gpu_commit_if.ready && gpu_commit_if.valid;
assign stall_out = ~gpu_commit_if.ready && gpu_commit_if.valid;
VX_pipe_register #(
.DATAW (1 + `NW_BITS + `NUM_THREADS + 32 + `NR_BITS + 1 + `GPU_TMC_SIZE + `GPU_WSPAWN_SIZE + `GPU_SPLIT_SIZE + `GPU_BARRIER_SIZE + (`NUM_THREADS * 32)),
.DATAW (1 + `NW_BITS + `NUM_THREADS + 32 + `NR_BITS + 1 + (`NUM_THREADS * 32) + 1),
.RESETW (1)
) pipe_reg (
.clk (clk),
.reset (reset),
.enable (!stall),
.data_in ({gpu_req_if.valid, gpu_req_if.wid, gpu_req_if.tmask, gpu_req_if.PC, tex_rsp_if.data, gpu_req_if.rd, gpu_req_if.wb, tmc, wspawn, split, barrier}),
.data_out ({gpu_commit_if.valid, gpu_commit_if.wid, gpu_commit_if.tmask, gpu_commit_if.PC, gpu_commit_if.data, gpu_commit_if.rd, gpu_commit_if.wb, warp_ctl_if.tmc, warp_ctl_if.wspawn, warp_ctl_if.split, warp_ctl_if.barrier})
.enable (!stall_out),
.data_in ({rsp_valid, rsp_wid, rsp_tmask, rsp_PC, rsp_rd, rsp_wb, rsp_data, is_warp_ctl}),
.data_out ({gpu_commit_if.valid, gpu_commit_if.wid, gpu_commit_if.tmask, gpu_commit_if.PC, gpu_commit_if.rd, gpu_commit_if.wb, gpu_commit_if.data, is_warp_ctl_r})
);
assign gpu_commit_if.eop = 1'b1;
assign warp_ctl_if.valid = gpu_commit_if.valid && gpu_commit_if.ready;
assign warp_ctl_if.wid = gpu_commit_if.wid;
// warp control reponse
`IGNORE_WARNINGS_BEGIN
assign {warp_ctl_if.tmc, warp_ctl_if.wspawn, warp_ctl_if.barrier, warp_ctl_if.split} = gpu_commit_if.data;
`IGNORE_WARNINGS_END
assign warp_ctl_if.valid = gpu_commit_if.valid && gpu_commit_if.ready && is_warp_ctl_r;
assign warp_ctl_if.wid = gpu_commit_if.wid;
// can accept new request?
assign gpu_req_if.ready = ~stall;
assign gpu_req_if.ready = ~stall_in;
`SCOPE_ASSIGN (gpu_req_fire, gpu_req_if.valid && gpu_req_if.ready);
`SCOPE_ASSIGN (gpu_req_wid, gpu_req_if.wid);
`SCOPE_ASSIGN (gpu_req_tmask, gpu_req_if.tmask);
`SCOPE_ASSIGN (gpu_req_op_type, gpu_req_if.op_type);
`SCOPE_ASSIGN (gpu_req_rs1, gpu_req_if.rs1_data[0]);
`SCOPE_ASSIGN (gpu_req_rs2, gpu_req_if.rs2_data[0]);
`SCOPE_ASSIGN (gpu_rsp_valid, warp_ctl_if.valid);
`SCOPE_ASSIGN (gpu_rsp_wid, warp_ctl_if.wid);
`SCOPE_ASSIGN (gpu_rsp_tmc, warp_ctl_if.tmc);