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tex refactoring and bug fixes

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This commit is contained in:
Blaise Tine
2021-03-16 09:25:57 -04:00
parent 17424ad554
commit 676a13f30d
21 changed files with 227 additions and 154 deletions
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11
hw/rtl/VX_csr_data.v
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@@ -13,7 +13,10 @@ module VX_csr_data #(
VX_cmt_to_csr_if cmt_to_csr_if,
VX_fpu_to_csr_if fpu_to_csr_if,
`ifdef EXT_TEX_ENABLE
VX_tex_csr_if tex_csr_if,
`endif
input wire read_enable,
input wire[`CSR_ADDR_BITS-1:0] read_addr,
@@ -80,10 +83,12 @@ module VX_csr_data #(
end
end
//write tex csrs
assign tex_csr_if.write_addr = write_addr;
assign tex_csr_if.write_data = write_data;
// TEX CSRs
`ifdef EXT_TEX_ENABLE
assign tex_csr_if.write_enable = write_enable;
assign tex_csr_if.write_addr = write_addr;
assign tex_csr_if.write_data = write_data;
`endif
always @(posedge clk) begin
if (reset) begin