Merge branch 'tensor_core' into rtl

hw/rtl/VX_config.vh

@@ -40,6 +40,10 @@
 `define EXT_F_ENABLE
 `endif
 
+`ifndef EXT_T_DISABLE
+`define EXT_T_ENABLE
+`endif
+
 `ifndef XLEN_32
 `ifndef XLEN_64
 `define XLEN_32
@@ -385,6 +389,11 @@
 `define LATENCY_FCVT 5
 `endif
 
+// Tensor Core Latency
+`ifndef LATENCY_HMMA
+`define LATENCY_HMMA 8
+`endif
+
 // Icache Configurable Knobs //////////////////////////////////////////////////
 
 // Cache Enable
@@ -613,6 +622,12 @@
     `define EXT_F_ENABLED   0
 `endif
 
+`ifdef EXT_T_ENABLE
+    `define EXT_T_ENABLED   1
+`else
+    `define EXT_T_ENABLED   0
+`endif
+
 `ifdef EXT_M_ENABLE
     `define EXT_M_ENABLED   1
 `else