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synthesis fixes

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This commit is contained in:
Blaise Tine
2020-03-05 06:58:51 -05:00
parent b038bdb491
commit 66a46f81ce
47 changed files with 633 additions and 2273 deletions
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12
rtl/VX_cache/VX_bank.v
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@@ -176,14 +176,14 @@ module VX_bank (
integer st1_cycle;
always @(*) begin
assign dfpq_hazard_st0 = 0;
assign mrvq_hazard_st0 = 0;
assign reqq_hazard_st0 = 0;
dfpq_hazard_st0 = 0;
mrvq_hazard_st0 = 0;
reqq_hazard_st0 = 0;
for (st1_cycle = 0; st1_cycle < `STAGE_1_CYCLES; st1_cycle = st1_cycle + 1) begin
if (valid_st1[st1_cycle] && going_to_write_st1[st1_cycle]) begin
if (dfpq_addr_st0 [31:`LINE_SELECT_ADDR_START] == addr_st1[st1_cycle][31:`LINE_SELECT_ADDR_START]) assign dfpq_hazard_st0 = 1;
if (mrvq_addr_st0 [31:`LINE_SELECT_ADDR_START] == addr_st1[st1_cycle][31:`LINE_SELECT_ADDR_START]) assign mrvq_hazard_st0 = 1;
if (reqq_req_addr_st0[31:`LINE_SELECT_ADDR_START] == addr_st1[st1_cycle][31:`LINE_SELECT_ADDR_START]) assign reqq_hazard_st0 = 1;
if (dfpq_addr_st0 [31:`LINE_SELECT_ADDR_START] == addr_st1[st1_cycle][31:`LINE_SELECT_ADDR_START]) dfpq_hazard_st0 = 1;
if (mrvq_addr_st0 [31:`LINE_SELECT_ADDR_START] == addr_st1[st1_cycle][31:`LINE_SELECT_ADDR_START]) mrvq_hazard_st0 = 1;
if (reqq_req_addr_st0[31:`LINE_SELECT_ADDR_START] == addr_st1[st1_cycle][31:`LINE_SELECT_ADDR_START]) reqq_hazard_st0 = 1;
end
end
end

1
rtl/VX_cache/VX_cache.v
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@@ -1,6 +1,5 @@
`include "VX_cache_config.v"
module VX_cache (
input wire clk,
input wire reset,

8
rtl/VX_cache/VX_cache_config.v
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@@ -1,12 +1,10 @@
`ifndef VX_CACHE_CONFIG
`define VX_CACHE_CONFIG
`include "../VX_define.v"
`ifndef VX_CACHE_CONFIG
`define VX_CACHE_CONFIG
// ========================================= Configurable Knobs =========================================
// General Cache Knobs
// Size of cache in bytes
`define CACHE_SIZE_BYTES 1024

5
rtl/VX_cache/VX_cache_core_req_bank_sel.v
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@@ -1,5 +1,4 @@
module VX_cache_core_req_bank_sel (
input wire [`NUMBER_REQUESTS-1:0] core_req_valid,
input wire [`NUMBER_REQUESTS-1:0][31:0] core_req_addr,
@@ -16,9 +15,9 @@ module VX_cache_core_req_bank_sel (
for (curr_req = 0; curr_req < `NUMBER_REQUESTS; curr_req = curr_req + 1) begin
if (`NUMBER_BANKS == 1) begin
// If there is only one bank, then only map requests to that bank
assign per_bank_valids[0][curr_req] = core_req_valid[curr_req];
per_bank_valids[0][curr_req] = core_req_valid[curr_req];
end else begin
assign per_bank_valids[core_req_addr[curr_req][`BANK_SELECT_ADDR_RNG]][curr_req] = core_req_valid[curr_req];
per_bank_valids[core_req_addr[curr_req][`BANK_SELECT_ADDR_RNG]][curr_req] = core_req_valid[curr_req];
end
end
end

6
rtl/VX_cache/VX_cache_dram_req_arb.v
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@@ -1,6 +1,5 @@
`include "VX_cache_config.v"
module VX_cache_dram_req_arb (
input wire clk,
input wire reset,
@@ -27,12 +26,13 @@ module VX_cache_dram_req_arb (
);
wire dfqq_req;
wire[31:0] dfqq_req_addr;
wire dfqq_empty;
wire dwb_valid;
wire dfqq_pop = !dwb_valid && dfqq_req; // If no dwb, and dfqq has valids, then pop
wire dfqq_push = (|per_bank_dram_fill_req);
VX_cache_dfq_queue VX_cache_dfq_queue(
.clk (clk),
.reset (reset),
@@ -46,8 +46,6 @@ module VX_cache_dram_req_arb (
.dfqq_full (dfqq_full)
);
wire dwb_valid;
wire[`vx_clog2(`NUMBER_BANKS)-1:0] dwb_bank;
VX_generic_priority_encoder #(.N(`NUMBER_BANKS)) VX_sel_dwb(
.valids(per_bank_dram_wb_req),

1
rtl/VX_cache/VX_cache_req_queue.v
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@@ -1,4 +1,3 @@
`include "VX_cache_config.v"
module VX_cache_req_queue (

15
rtl/VX_cache/VX_cache_wb_sel_merge.v
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@@ -1,6 +1,5 @@
`include "VX_cache_config.v"
module VX_cache_wb_sel_merge (
// Per Bank WB
@@ -48,18 +47,18 @@ module VX_cache_wb_sel_merge (
assign core_wb_req_wb = per_bank_wb_wb [main_bank_index];
assign core_wb_warp_num = per_bank_wb_warp_num[main_bank_index];
genvar this_bank;
integer this_bank;
generate
always @(*) begin
assign core_wb_valid = 0;
assign core_wb_readdata = 0;
core_wb_valid = 0;
core_wb_readdata = 0;
for (this_bank = 0; this_bank < `NUMBER_BANKS; this_bank = this_bank + 1) begin
if (found_bank && (per_bank_wb_valid[this_bank]) && (per_bank_wb_rd[this_bank] == per_bank_wb_rd[main_bank_index]) && (per_bank_wb_warp_num[this_bank] == per_bank_wb_warp_num[main_bank_index])) begin
assign core_wb_valid[per_bank_wb_tid[this_bank]] = 1;
assign core_wb_readdata[per_bank_wb_tid[this_bank]] = per_bank_wb_data[this_bank];
assign per_bank_wb_pop_unqual[this_bank] = 1;
core_wb_valid[per_bank_wb_tid[this_bank]] = 1;
core_wb_readdata[per_bank_wb_tid[this_bank]] = per_bank_wb_data[this_bank];
per_bank_wb_pop_unqual[this_bank] = 1;
end else begin
assign per_bank_wb_pop_unqual[this_bank] = 0;
per_bank_wb_pop_unqual[this_bank] = 0;
end
end
end

72
rtl/VX_cache/quartus/Makefile Executable file
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@@ -0,0 +1,72 @@
PROJECT = VX_cache
TOP_LEVEL_ENTITY = VX_cache
SRC_FILE = ../VX_cache.v
PROJECT_FILES = $(PROJECT).qpf $(PROJECT).qsf
QUARTUS_ROOT ?= /tools/reconfig/intel/18.0
# Part, Family
FAMILY = "Arria 10"
DEVICE = 10AX115N3F40E2SG
# Executable Configuration
SYN_ARGS = --parallel --read_settings_files=on
FIT_ARGS = --part=$(DEVICE) --read_settings_files=on
ASM_ARGS =
STA_ARGS = --do_report_timing
# Build targets
all: $(PROJECT).sta.rpt
syn: $(PROJECT).syn.rpt
fit: $(PROJECT).fit.rpt
asm: $(PROJECT).asm.rpt
sta: $(PROJECT).sta.rpt
smart: smart.log
# Target implementations
STAMP = echo done >
$(PROJECT).syn.rpt: smart.log syn.chg $(SOURCE_FILES)
quartus_syn $(PROJECT) $(SYN_ARGS)
$(STAMP) fit.chg
$(PROJECT).fit.rpt: smart.log fit.chg $(PROJECT).syn.rpt
quartus_fit $(PROJECT) $(FIT_ARGS)
$(STAMP) asm.chg
$(STAMP) sta.chg
$(PROJECT).asm.rpt: smart.log asm.chg $(PROJECT).fit.rpt
quartus_asm $(PROJECT) $(ASM_ARGS)
$(PROJECT).sta.rpt: smart.log sta.chg $(PROJECT).fit.rpt
quartus_sta $(PROJECT) $(STA_ARGS)
smart.log: $(PROJECT_FILES)
quartus_sh --determine_smart_action $(PROJECT) > smart.log
# Project initialization
$(PROJECT_FILES):
quartus_sh -t project.tcl -project $(PROJECT) -family $(FAMILY) -device $(DEVICE) -top $(TOP_LEVEL_ENTITY) -src $(SRC_FILE) -sdc project.sdc -inc "../;../../"
syn.chg:
$(STAMP) syn.chg
fit.chg:
$(STAMP) fit.chg
sta.chg:
$(STAMP) sta.chg
asm.chg:
$(STAMP) asm.chg
program: $(PROJECT).sof
quartus_pgm --no_banner --mode=jtag -o "P;$(PROJECT).sof"
clean:
rm -rf bin *.rpt *.chg *.qsf *.qpf smart.log *.htm *.eqn *.pin *.sof *.pof qdb incremental_db tmp-clearbox

1
rtl/VX_cache/quartus/project.sdc Executable file
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@@ -0,0 +1 @@
create_clock -name {clk} -period "250 MHz" -waveform { 0.0 1.0 } [get_ports {clk}]

41
rtl/VX_cache/quartus/project.tcl Normal file
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@@ -0,0 +1,41 @@
load_package flow
package require cmdline
set options { \
{ "project.arg" "" "Project name" } \
{ "family.arg" "" "Device family name" } \
{ "device.arg" "" "Device name" } \
{ "top.arg" "" "Top level module" } \
{ "sdc.arg" "" "Timing Design Constraints file" } \
{ "src.arg" "" "Verilog source file" } \
{ "inc.arg" "." "Include path" } \
}
array set opts [::cmdline::getoptions quartus(args) $options]
project_new $opts(project) -overwrite
set_global_assignment -name FAMILY $opts(family)
set_global_assignment -name DEVICE $opts(device)
set_global_assignment -name TOP_LEVEL_ENTITY $opts(top)
set_global_assignment -name VERILOG_FILE $opts(src)
set_global_assignment -name SEARCH_PATH $opts(inc)
set_global_assignment -name SDC_FILE $opts(sdc)
set_global_assignment -name PROJECT_OUTPUT_DIRECTORY bin
set_global_assignment -name NUM_PARALLEL_PROCESSORS ALL
set_global_assignment -name VERILOG_INPUT_VERSION SYSTEMVERILOG_2009
proc make_all_pins_virtual {} {
execute_module -tool map
set name_ids [get_names -filter * -node_type pin]
foreach_in_collection name_id $name_ids {
set pin_name [get_name_info -info full_path $name_id]
post_message "Making VIRTUAL_PIN assignment to $pin_name"
set_instance_assignment -to $pin_name -name VIRTUAL_PIN ON
}
export_assignments
}
make_all_pins_virtual
project_close