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cache bank area optimization + multi-porting fix for l2/l3 caches

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Blaise Tine
2021-08-28 21:34:06 -07:00
parent f3ba27b138
commit 6674e8c44a
9 changed files with 388 additions and 236 deletions
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6
hw/rtl/cache/VX_cache_define.vh vendored
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@@ -9,8 +9,10 @@
`define REQS_BITS `LOG2UP(NUM_REQS)
// tag valid tid word_sel
`define MSHR_DATA_WIDTH (CORE_TAG_WIDTH + (1 + `REQS_BITS + `UP(`WORD_SELECT_BITS)) * NUM_PORTS)
`define PORTS_BITS `LOG2UP(NUM_PORTS)
// tag valid tid word_sel
`define MSHR_DATA_WIDTH ((CORE_TAG_WIDTH + 1 + `REQS_BITS + `UP(`WORD_SELECT_BITS)) * NUM_PORTS)
`define WORD_WIDTH (8 * WORD_SIZE)