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getting dogfood tests passing on Verilator!

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This commit is contained in:
Blaise Tine
2020-08-09 18:13:12 -04:00
parent 9e0639b49f
commit 65415d2bbc
43 changed files with 748 additions and 585 deletions
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20
hw/rtl/fp_cores/altera/VX_fp_add.v
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@@ -4,23 +4,23 @@ module VX_fp_add (
input wire clk,
input wire reset,
output wire in_ready,
input wire in_valid,
output wire ready_in,
input wire valid_in,
input wire [`ISTAG_BITS-1:0] in_tag,
input wire [`ISTAG_BITS-1:0] tag_in,
input wire [`NUM_THREADS-1:0][31:0] dataa,
input wire [`NUM_THREADS-1:0][31:0] datab,
output wire [`NUM_THREADS-1:0][31:0] result,
output wire [`ISTAG_BITS-1:0] out_tag,
output wire [`ISTAG_BITS-1:0] tag_out,
input wire out_ready,
output wire out_valid
input wire ready_out,
output wire valid_out
);
wire stall = ~out_ready && out_valid;
wire stall = ~ready_out && valid_out;
wire enable = ~stall;
assign in_ready = enable;
assign ready_in = enable;
genvar i;
@@ -73,8 +73,8 @@ module VX_fp_add (
.clk(clk),
.reset(reset),
.enable(enable),
.in({in_tag, in_valid}),
.out({out_tag, out_valid})
.in ({tag_in, valid_in}),
.out({tag_out, valid_out})
);
endmodule

20
hw/rtl/fp_cores/altera/VX_fp_div.v
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@@ -4,23 +4,23 @@ module VX_fp_div (
input wire clk,
input wire reset,
output wire in_ready,
input wire in_valid,
output wire ready_in,
input wire valid_in,
input wire [`ISTAG_BITS-1:0] in_tag,
input wire [`ISTAG_BITS-1:0] tag_in,
input wire [`NUM_THREADS-1:0][31:0] dataa,
input wire [`NUM_THREADS-1:0][31:0] datab,
output wire [`NUM_THREADS-1:0][31:0] result,
output wire [`ISTAG_BITS-1:0] out_tag,
output wire [`ISTAG_BITS-1:0] tag_out,
input wire out_ready,
output wire out_valid
input wire ready_out,
output wire valid_out
);
wire stall = ~out_ready && out_valid;
wire stall = ~ready_out && valid_out;
wire enable = ~stall;
assign in_ready = enable;
assign ready_in = enable;
genvar i;
@@ -42,8 +42,8 @@ module VX_fp_div (
.clk(clk),
.reset(reset),
.enable(enable),
.in({in_tag, in_valid}),
.out({out_tag, out_valid})
.in ({tag_in, valid_in}),
.out({tag_out, valid_out})
);
endmodule

20
hw/rtl/fp_cores/altera/VX_fp_ftoi.v
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@@ -4,22 +4,22 @@ module VX_fp_ftoi (
input wire clk,
input wire reset,
output wire in_ready,
input wire in_valid,
output wire ready_in,
input wire valid_in,
input wire [`ISTAG_BITS-1:0] in_tag,
input wire [`ISTAG_BITS-1:0] tag_in,
input wire [`NUM_THREADS-1:0][31:0] dataa,
output wire [`NUM_THREADS-1:0][31:0] result,
output wire [`ISTAG_BITS-1:0] out_tag,
output wire [`ISTAG_BITS-1:0] tag_out,
input wire out_ready,
output wire out_valid
input wire ready_out,
output wire valid_out
);
wire stall = ~out_ready && out_valid;
wire stall = ~ready_out && valid_out;
wire enable = ~stall;
assign in_ready = enable;
assign ready_in = enable;
genvar i;
@@ -40,8 +40,8 @@ module VX_fp_ftoi (
.clk(clk),
.reset(reset),
.enable(enable),
.in({in_tag, in_valid}),
.out({out_tag, out_valid})
.in ({tag_in, valid_in}),
.out({tag_out, valid_out})
);
endmodule

20
hw/rtl/fp_cores/altera/VX_fp_ftou.v
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@@ -4,22 +4,22 @@ module VX_fp_ftou (
input wire clk,
input wire reset,
output wire in_ready,
input wire in_valid,
output wire ready_in,
input wire valid_in,
input wire [`ISTAG_BITS-1:0] in_tag,
input wire [`ISTAG_BITS-1:0] tag_in,
input wire [`NUM_THREADS-1:0][31:0] dataa,
output wire [`NUM_THREADS-1:0][31:0] result,
output wire [`ISTAG_BITS-1:0] out_tag,
output wire [`ISTAG_BITS-1:0] tag_out,
input wire out_ready,
output wire out_valid
input wire ready_out,
output wire valid_out
);
wire stall = ~out_ready && out_valid;
wire stall = ~ready_out && valid_out;
wire enable = ~stall;
assign in_ready = enable;
assign ready_in = enable;
genvar i;
@@ -40,8 +40,8 @@ module VX_fp_ftou (
.clk(clk),
.reset(reset),
.enable(enable),
.in({in_tag, in_valid}),
.out({out_tag, out_valid})
.in ({tag_in, valid_in}),
.out({tag_out, valid_out})
);
endmodule

20
hw/rtl/fp_cores/altera/VX_fp_itof.v
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@@ -4,22 +4,22 @@ module VX_fp_itof (
input wire clk,
input wire reset,
output wire in_ready,
input wire in_valid,
output wire ready_in,
input wire valid_in,
input wire [`ISTAG_BITS-1:0] in_tag,
input wire [`ISTAG_BITS-1:0] tag_in,
input wire [`NUM_THREADS-1:0][31:0] dataa,
output wire [`NUM_THREADS-1:0][31:0] result,
output wire [`ISTAG_BITS-1:0] out_tag,
output wire [`ISTAG_BITS-1:0] tag_out,
input wire out_ready,
output wire out_valid
input wire ready_out,
output wire valid_out
);
wire stall = ~out_ready && out_valid;
wire stall = ~ready_out && valid_out;
wire enable = ~stall;
assign in_ready = enable;
assign ready_in = enable;
genvar i;
@@ -40,8 +40,8 @@ module VX_fp_itof (
.clk(clk),
.reset(reset),
.enable(enable),
.in({in_tag, in_valid}),
.out({out_tag, out_valid})
.in ({tag_in, valid_in}),
.out({tag_out, valid_out})
);
endmodule

22
hw/rtl/fp_cores/altera/VX_fp_madd.v
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@@ -4,10 +4,10 @@ module VX_fp_madd (
input wire clk,
input wire reset,
output wire in_ready,
input wire in_valid,
output wire ready_in,
input wire valid_in,
input wire [`ISTAG_BITS-1:0] in_tag,
input wire [`ISTAG_BITS-1:0] tag_in,
input wire [`NUM_THREADS-1:0][31:0] dataa,
input wire [`NUM_THREADS-1:0][31:0] datab,
@@ -16,13 +16,13 @@ module VX_fp_madd (
input wire negate,
output wire [`ISTAG_BITS-1:0] out_tag,
output wire [`ISTAG_BITS-1:0] tag_out,
input wire out_ready,
output wire out_valid
input wire ready_out,
output wire valid_out
);
wire enable0, enable1;
assign in_ready = enable0 && enable1;
assign ready_in = enable0 && enable1;
wire [`NUM_THREADS-1:0][31:0] result_st0, result_st1;
wire [`ISTAG_BITS-1:0] out_tag_st0, out_tag_st1;
@@ -119,7 +119,7 @@ module VX_fp_madd (
.clk(clk),
.reset(reset),
.enable(enable0),
.in({in_tag, (in_valid && ~negate), (in_valid && negate)}),
.in ({tag_in, (valid_in && ~negate), (valid_in && negate)}),
.out({out_tag_st0, out_valid_st0, in_valid_st0})
);
@@ -134,12 +134,12 @@ module VX_fp_madd (
.out({out_tag_st1, out_valid_st1})
);
wire out_stall = ~out_ready && out_valid;
wire out_stall = ~ready_out && valid_out;
assign enable0 = ~out_stall;
assign enable1 = ~out_stall && ~(out_valid_st0 && out_valid_st1); // stall the negate stage if dual outputs
assign result = out_valid_st0 ? result_st0 : result_st1;
assign out_tag = out_valid_st0 ? out_tag_st0 : out_tag_st1;
assign out_valid = out_valid_st0 || out_valid_st1;
assign tag_out = out_valid_st0 ? out_tag_st0 : out_tag_st1;
assign valid_out = out_valid_st0 || out_valid_st1;
endmodule

22
hw/rtl/fp_cores/altera/VX_fp_msub.v
View File

@@ -4,10 +4,10 @@ module VX_fp_msub (
input wire clk,
input wire reset,
output wire in_ready,
input wire in_valid,
output wire ready_in,
input wire valid_in,
input wire [`ISTAG_BITS-1:0] in_tag,
input wire [`ISTAG_BITS-1:0] tag_in,
input wire [`NUM_THREADS-1:0][31:0] dataa,
input wire [`NUM_THREADS-1:0][31:0] datab,
@@ -16,13 +16,13 @@ module VX_fp_msub (
input wire negate,
output wire [`ISTAG_BITS-1:0] out_tag,
output wire [`ISTAG_BITS-1:0] tag_out,
input wire out_ready,
output wire out_valid
input wire ready_out,
output wire valid_out
);
wire enable0, enable1;
assign in_ready = enable0 && enable1;
assign ready_in = enable0 && enable1;
wire [`NUM_THREADS-1:0][31:0] result_st0, result_st1;
wire [`ISTAG_BITS-1:0] out_tag_st0, out_tag_st1;
@@ -119,7 +119,7 @@ module VX_fp_msub (
.clk(clk),
.reset(reset),
.enable(enable0),
.in({in_tag, (in_valid && ~negate), (in_valid && negate)}),
.in ({tag_in, (valid_in && ~negate), (valid_in && negate)}),
.out({out_tag_st0, out_valid_st0, in_valid_st0})
);
@@ -134,12 +134,12 @@ module VX_fp_msub (
.out({out_tag_st1, out_valid_st1})
);
wire out_stall = ~out_ready && out_valid;
wire out_stall = ~ready_out && valid_out;
assign enable0 = ~out_stall;
assign enable1 = ~out_stall && ~(out_valid_st0 && out_valid_st1); // stall the negate stage if dual outputs
assign result = out_valid_st0 ? result_st0 : result_st1;
assign out_tag = out_valid_st0 ? out_tag_st0 : out_tag_st1;
assign out_valid = out_valid_st0 || out_valid_st1;
assign tag_out = out_valid_st0 ? out_tag_st0 : out_tag_st1;
assign valid_out = out_valid_st0 || out_valid_st1;
endmodule

20
hw/rtl/fp_cores/altera/VX_fp_mul.v
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@@ -4,23 +4,23 @@ module VX_fp_mul (
input wire clk,
input wire reset,
output wire in_ready,
input wire in_valid,
output wire ready_in,
input wire valid_in,
input wire [`ISTAG_BITS-1:0] in_tag,
input wire [`ISTAG_BITS-1:0] tag_in,
input wire [`NUM_THREADS-1:0][31:0] dataa,
input wire [`NUM_THREADS-1:0][31:0] datab,
output wire [`NUM_THREADS-1:0][31:0] result,
output wire [`ISTAG_BITS-1:0] out_tag,
output wire [`ISTAG_BITS-1:0] tag_out,
input wire out_ready,
output wire out_valid
input wire ready_out,
output wire valid_out
);
wire stall = ~out_ready && out_valid;
wire stall = ~ready_out && valid_out;
wire enable = ~stall;
assign in_ready = enable;
assign ready_in = enable;
genvar i;
@@ -73,8 +73,8 @@ module VX_fp_mul (
.clk(clk),
.reset(reset),
.enable(enable),
.in({in_tag, in_valid}),
.out({out_tag, out_valid})
.in ({tag_in, valid_in}),
.out({tag_out, valid_out})
);
endmodule

20
hw/rtl/fp_cores/altera/VX_fp_sqrt.v
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@@ -4,22 +4,22 @@ module VX_fp_sqrt (
input wire clk,
input wire reset,
output wire in_ready,
input wire in_valid,
output wire ready_in,
input wire valid_in,
input wire [`ISTAG_BITS-1:0] in_tag,
input wire [`ISTAG_BITS-1:0] tag_in,
input wire [`NUM_THREADS-1:0][31:0] dataa,
output wire [`NUM_THREADS-1:0][31:0] result,
output wire [`ISTAG_BITS-1:0] out_tag,
output wire [`ISTAG_BITS-1:0] tag_out,
input wire out_ready,
output wire out_valid
input wire ready_out,
output wire valid_out
);
wire stall = ~out_ready && out_valid;
wire stall = ~ready_out && valid_out;
wire enable = ~stall;
assign in_ready = enable;
assign ready_in = enable;
genvar i;
@@ -40,8 +40,8 @@ module VX_fp_sqrt (
.clk(clk),
.reset(reset),
.enable(enable),
.in({in_tag, in_valid}),
.out({out_tag, out_valid})
.in ({tag_in, valid_in}),
.out({tag_out, valid_out})
);
endmodule

20
hw/rtl/fp_cores/altera/VX_fp_sub.v
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@@ -4,23 +4,23 @@ module VX_fp_sub (
input wire clk,
input wire reset,
output wire in_ready,
input wire in_valid,
output wire ready_in,
input wire valid_in,
input wire [`ISTAG_BITS-1:0] in_tag,
input wire [`ISTAG_BITS-1:0] tag_in,
input wire [`NUM_THREADS-1:0][31:0] dataa,
input wire [`NUM_THREADS-1:0][31:0] datab,
output wire [`NUM_THREADS-1:0][31:0] result,
output wire [`ISTAG_BITS-1:0] out_tag,
output wire [`ISTAG_BITS-1:0] tag_out,
input wire out_ready,
output wire out_valid
input wire ready_out,
output wire valid_out
);
wire stall = ~out_ready && out_valid;
wire stall = ~ready_out && valid_out;
wire enable = ~stall;
assign in_ready = enable;
assign ready_in = enable;
genvar i;
@@ -73,8 +73,8 @@ module VX_fp_sub (
.clk(clk),
.reset(reset),
.enable(enable),
.in({in_tag, in_valid}),
.out({out_tag, out_valid})
.in ({tag_in, valid_in}),
.out({tag_out, valid_out})
);
endmodule

20
hw/rtl/fp_cores/altera/VX_fp_utof.v
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@@ -4,22 +4,22 @@ module VX_fp_utof (
input wire clk,
input wire reset,
output wire in_ready,
input wire in_valid,
output wire ready_in,
input wire valid_in,
input wire [`ISTAG_BITS-1:0] in_tag,
input wire [`ISTAG_BITS-1:0] tag_in,
input wire [`NUM_THREADS-1:0][31:0] dataa,
output wire [`NUM_THREADS-1:0][31:0] result,
output wire [`ISTAG_BITS-1:0] out_tag,
output wire [`ISTAG_BITS-1:0] tag_out,
input wire out_ready,
output wire out_valid
input wire ready_out,
output wire valid_out
);
wire stall = ~out_ready && out_valid;
wire stall = ~ready_out && valid_out;
wire enable = ~stall;
assign in_ready = enable;
assign ready_in = enable;
genvar i;
@@ -40,8 +40,8 @@ module VX_fp_utof (
.clk(clk),
.reset(reset),
.enable(enable),
.in({in_tag, in_valid}),
.out({out_tag, out_valid})
.in ({tag_in, valid_in}),
.out({tag_out, valid_out})
);
endmodule