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fixed no shared memory bug, fixed cache debug log

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This commit is contained in:
Blaise Tine
2021-08-02 15:59:33 -07:00
parent 3b7da61245
commit 6525dff158
8 changed files with 144 additions and 96 deletions
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12
hw/rtl/cache/VX_bank.v vendored
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@@ -200,9 +200,9 @@ module VX_bank #(
`ifdef DBG_CACHE_REQ_INFO
if (CORE_TAG_WIDTH != CORE_TAG_ID_BITS && CORE_TAG_ID_BITS != 0) begin
assign {debug_pc_sel, debug_wid_sel} = mshr_enable ? mshr_tag[CORE_TAG_WIDTH-1:CORE_TAG_ID_BITS] : creq_tag[CORE_TAG_WIDTH-1:CORE_TAG_ID_BITS];
assign {debug_wid_sel, debug_pc_sel} = mshr_enable ? mshr_tag[`CACHE_REQ_INFO_RNG] : creq_tag[`CACHE_REQ_INFO_RNG];
end else begin
assign {debug_pc_sel, debug_wid_sel} = 0;
assign {debug_wid_sel, debug_pc_sel} = 0;
end
`endif
@@ -253,9 +253,9 @@ module VX_bank #(
`ifdef DBG_CACHE_REQ_INFO
if (CORE_TAG_WIDTH != CORE_TAG_ID_BITS && CORE_TAG_ID_BITS != 0) begin
assign {debug_pc_st0, debug_wid_st0} = tag_st0[CORE_TAG_WIDTH-1:CORE_TAG_ID_BITS];
assign {debug_wid_st0, debug_pc_st0} = tag_st0[`CACHE_REQ_INFO_RNG];
end else begin
assign {debug_pc_st0, debug_wid_st0} = 0;
assign {debug_wid_st0, debug_pc_st0} = 0;
end
`endif
@@ -322,9 +322,9 @@ module VX_bank #(
`ifdef DBG_CACHE_REQ_INFO
if (CORE_TAG_WIDTH != CORE_TAG_ID_BITS && CORE_TAG_ID_BITS != 0) begin
assign {debug_pc_st1, debug_wid_st1} = tag_st1[CORE_TAG_WIDTH-1:CORE_TAG_ID_BITS];
assign {debug_wid_st1, debug_pc_st1} = tag_st1[`CACHE_REQ_INFO_RNG];
end else begin
assign {debug_pc_st1, debug_wid_st1} = 0;
assign {debug_wid_st1, debug_pc_st1} = 0;
end
`endif