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bram block optimization

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This commit is contained in:
Blaise Tine
2021-08-13 19:31:55 -07:00
parent 4336dcb2a8
commit 646371f9e9
9 changed files with 56 additions and 110 deletions
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70
hw/rtl/libs/VX_dp_ram.v
View File

@@ -14,9 +14,7 @@ module VX_dp_ram #(
input wire clk,
input wire [ADDRW-1:0] waddr,
input wire [ADDRW-1:0] raddr,
input wire wren,
input wire [BYTEENW-1:0] byteen,
input wire rden,
input wire [BYTEENW-1:0] wren,
input wire [DATAW-1:0] din,
output wire [DATAW-1:0] dout
);
@@ -35,14 +33,11 @@ module VX_dp_ram #(
end
always @(posedge clk) begin
if (wren) begin
for (integer i = 0; i < BYTEENW; i++) begin
if (byteen[i])
mem[waddr][i] <= din[i * 8 +: 8];
end
for (integer i = 0; i < BYTEENW; i++) begin
if (wren[i])
mem[waddr][i] <= din[i * 8 +: 8];
end
if (rden)
dout_r <= mem[raddr];
dout_r <= mem[raddr];
end
end else begin
`USE_FAST_BRAM reg [DATAW-1:0] mem [SIZE-1:0];
@@ -52,16 +47,13 @@ module VX_dp_ram #(
end
always @(posedge clk) begin
if (wren && byteen)
if (wren)
mem[waddr] <= din;
if (rden)
dout_r <= mem[raddr];
dout_r <= mem[raddr];
end
end
assign dout = dout_r;
end else begin
`UNUSED_VAR (rden)
if (BYTEENW > 1) begin
`USE_FAST_BRAM reg [BYTEENW-1:0][7:0] mem [SIZE-1:0];
@@ -70,11 +62,9 @@ module VX_dp_ram #(
end
always @(posedge clk) begin
if (wren) begin
for (integer i = 0; i < BYTEENW; i++) begin
if (byteen[i])
mem[waddr][i] <= din[i * 8 +: 8];
end
for (integer i = 0; i < BYTEENW; i++) begin
if (wren[i])
mem[waddr][i] <= din[i * 8 +: 8];
end
end
assign dout = mem[raddr];
@@ -86,7 +76,7 @@ module VX_dp_ram #(
end
always @(posedge clk) begin
if (wren && byteen)
if (wren)
mem[waddr] <= din;
end
assign dout = mem[raddr];
@@ -104,14 +94,11 @@ module VX_dp_ram #(
end
always @(posedge clk) begin
if (wren) begin
for (integer i = 0; i < BYTEENW; i++) begin
if (byteen[i])
mem[waddr][i] <= din[i * 8 +: 8];
end
for (integer i = 0; i < BYTEENW; i++) begin
if (wren[i])
mem[waddr][i] <= din[i * 8 +: 8];
end
if (rden)
dout_r <= mem[raddr];
dout_r <= mem[raddr];
end
end else begin
reg [DATAW-1:0] mem [SIZE-1:0];
@@ -121,16 +108,13 @@ module VX_dp_ram #(
end
always @(posedge clk) begin
if (wren && byteen)
if (wren)
mem[waddr] <= din;
if (rden)
dout_r <= mem[raddr];
dout_r <= mem[raddr];
end
end
assign dout = dout_r;
end else begin
`UNUSED_VAR (rden)
if (RWCHECK) begin
if (BYTEENW > 1) begin
reg [BYTEENW-1:0][7:0] mem [SIZE-1:0];
@@ -140,11 +124,9 @@ module VX_dp_ram #(
end
always @(posedge clk) begin
if (wren) begin
for (integer i = 0; i < BYTEENW; i++) begin
if (byteen[i])
mem[waddr][i] <= din[i * 8 +: 8];
end
for (integer i = 0; i < BYTEENW; i++) begin
if (wren[i])
mem[waddr][i] <= din[i * 8 +: 8];
end
end
assign dout = mem[raddr];
@@ -156,7 +138,7 @@ module VX_dp_ram #(
end
always @(posedge clk) begin
if (wren && byteen)
if (wren)
mem[waddr] <= din;
end
assign dout = mem[raddr];
@@ -170,11 +152,9 @@ module VX_dp_ram #(
end
always @(posedge clk) begin
if (wren) begin
for (integer i = 0; i < BYTEENW; i++) begin
if (byteen[i])
mem[waddr][i] <= din[i * 8 +: 8];
end
for (integer i = 0; i < BYTEENW; i++) begin
if (wren[i])
mem[waddr][i] <= din[i * 8 +: 8];
end
end
assign dout = mem[raddr];
@@ -186,7 +166,7 @@ module VX_dp_ram #(
end
always @(posedge clk) begin
if (wren && byteen)
if (wren)
mem[waddr] <= din;
end
assign dout = mem[raddr];

4
hw/rtl/libs/VX_fifo_queue.v
View File

@@ -164,8 +164,6 @@ module VX_fifo_queue #(
.waddr(wr_ptr_r),
.raddr(rd_ptr_r),
.wren(push),
.byteen(1'b1),
.rden(1'b1),
.din(data_in),
.dout(data_out)
);
@@ -209,8 +207,6 @@ module VX_fifo_queue #(
.waddr(wr_ptr_r),
.raddr(rd_ptr_n_r),
.wren(push),
.byteen(1'b1),
.rden(1'b1),
.din(data_in),
.dout(dout)
);

2
hw/rtl/libs/VX_index_buffer.v
View File

@@ -78,8 +78,6 @@ module VX_index_buffer #(
.waddr(write_addr),
.raddr(read_addr),
.wren(acquire_slot),
.byteen(1'b1),
.rden(1'b1),
.din(write_data),
.dout(read_data)
);

70
hw/rtl/libs/VX_sp_ram.v
View File

@@ -13,9 +13,7 @@ module VX_sp_ram #(
) (
input wire clk,
input wire [ADDRW-1:0] addr,
input wire wren,
input wire [BYTEENW-1:0] byteen,
input wire rden,
input wire [BYTEENW-1:0] wren,
input wire [DATAW-1:0] din,
output wire [DATAW-1:0] dout
);
@@ -34,14 +32,11 @@ module VX_sp_ram #(
end
always @(posedge clk) begin
if (wren) begin
for (integer i = 0; i < BYTEENW; i++) begin
if (byteen[i])
mem[addr][i] <= din[i * 8 +: 8];
end
for (integer i = 0; i < BYTEENW; i++) begin
if (wren[i])
mem[addr][i] <= din[i * 8 +: 8];
end
if (rden)
dout_r <= mem[addr];
dout_r <= mem[addr];
end
end else begin
`USE_FAST_BRAM reg [DATAW-1:0] mem [SIZE-1:0];
@@ -51,15 +46,13 @@ module VX_sp_ram #(
end
always @(posedge clk) begin
if (wren && byteen)
if (wren)
mem[addr] <= din;
if (rden)
dout_r <= mem[addr];
dout_r <= mem[addr];
end
end
assign dout = dout_r;
end else begin
`UNUSED_VAR (rden)
if (BYTEENW > 1) begin
`USE_FAST_BRAM reg [BYTEENW-1:0][7:0] mem [SIZE-1:0];
@@ -68,11 +61,9 @@ module VX_sp_ram #(
end
always @(posedge clk) begin
if (wren) begin
for (integer i = 0; i < BYTEENW; i++) begin
if (byteen[i])
mem[addr][i] <= din[i * 8 +: 8];
end
for (integer i = 0; i < BYTEENW; i++) begin
if (wren[i])
mem[addr][i] <= din[i * 8 +: 8];
end
end
assign dout = mem[addr];
@@ -84,7 +75,7 @@ module VX_sp_ram #(
end
always @(posedge clk) begin
if (wren && byteen)
if (wren)
mem[addr] <= din;
end
assign dout = mem[addr];
@@ -102,14 +93,11 @@ module VX_sp_ram #(
end
always @(posedge clk) begin
if (wren) begin
for (integer i = 0; i < BYTEENW; i++) begin
if (byteen[i])
mem[addr][i] <= din[i * 8 +: 8];
end
for (integer i = 0; i < BYTEENW; i++) begin
if (wren[i])
mem[addr][i] <= din[i * 8 +: 8];
end
if (rden)
dout_r <= mem[addr];
dout_r <= mem[addr];
end
end else begin
reg [DATAW-1:0] mem [SIZE-1:0];
@@ -119,15 +107,13 @@ module VX_sp_ram #(
end
always @(posedge clk) begin
if (wren && byteen)
if (wren)
mem[addr] <= din;
if (rden)
dout_r <= mem[addr];
dout_r <= mem[addr];
end
end
assign dout = dout_r;
end else begin
`UNUSED_VAR (rden)
if (RWCHECK) begin
if (BYTEENW > 1) begin
reg [BYTEENW-1:0][7:0] mem [SIZE-1:0];
@@ -137,11 +123,9 @@ module VX_sp_ram #(
end
always @(posedge clk) begin
if (wren) begin
for (integer i = 0; i < BYTEENW; i++) begin
if (byteen[i])
mem[addr][i] <= din[i * 8 +: 8];
end
for (integer i = 0; i < BYTEENW; i++) begin
if (wren[i])
mem[addr][i] <= din[i * 8 +: 8];
end
end
assign dout = mem[addr];
@@ -153,7 +137,7 @@ module VX_sp_ram #(
end
always @(posedge clk) begin
if (wren && byteen)
if (wren)
mem[addr] <= din;
end
assign dout = mem[addr];
@@ -166,12 +150,10 @@ module VX_sp_ram #(
initial mem = '{default: 0};
end
always @(posedge clk) begin
if (wren) begin
for (integer i = 0; i < BYTEENW; i++) begin
if (byteen[i])
mem[addr][i] <= din[i * 8 +: 8];
end
always @(posedge clk) begin
for (integer i = 0; i < BYTEENW; i++) begin
if (wren[i])
mem[addr][i] <= din[i * 8 +: 8];
end
end
assign dout = mem[addr];
@@ -183,7 +165,7 @@ module VX_sp_ram #(
end
always @(posedge clk) begin
if (wren && byteen)
if (wren)
mem[addr] <= din;
end
assign dout = mem[addr];