diff --git a/RELEASE b/RELEASE new file mode 100644 index 00000000..48ae100a --- /dev/null +++ b/RELEASE @@ -0,0 +1,4 @@ + +Release Notes! + +* 07/01/2020 - LKG FPGA build - Passed basic, demo, vecadd kernels. \ No newline at end of file diff --git a/benchmarks/opencl/vecadd/main.cc b/benchmarks/opencl/vecadd/main.cc index 237924ba..3b6f889b 100644 --- a/benchmarks/opencl/vecadd/main.cc +++ b/benchmarks/opencl/vecadd/main.cc @@ -4,7 +4,7 @@ #include #include -#define SIZE 4 +#define SIZE 4096 #define NUM_WORK_GROUPS 2 #define KERNEL_NAME "vecadd" @@ -30,28 +30,6 @@ _ret; \ }) -/*#include -#ifdef __cplusplus -extern "C" { -#endif -int _pocl_register_kernel(const char* name, const void* pfn, uint32_t num_args, uint32_t num_locals, const uint8_t* arg_types, const uint32_t* local_sizes); -void _pocl_kernel_vecadd_workgroup(uint8_t* args, uint8_t*, uint32_t, uint32_t, uint32_t); -#ifdef __cplusplus -} -#endif - -namespace { -class auto_register_kernel_t { -public: - auto_register_kernel_t() { - static uint8_t arg_types[] = {1, 1, 1}; - static uint32_t local_sizes[] = {}; - _pocl_register_kernel("vecadd", (void*)_pocl_kernel_vecadd_workgroup, 3, 0, arg_types, local_sizes); - } -}; -static auto_register_kernel_t __x__; -}*/ - int exitcode = 0; cl_context context = NULL; cl_command_queue commandQueue = NULL; diff --git a/driver/common/vx_utils.cpp b/driver/common/vx_utils.cpp index d4fcf518..d7b8f829 100644 --- a/driver/common/vx_utils.cpp +++ b/driver/common/vx_utils.cpp @@ -4,31 +4,6 @@ #include #include -extern int vx_dev_caps(int caps_id) { - switch (caps_id) { - case VX_CAPS_VERSION: - return 0; - case VX_CAPS_MAX_CORES: - return NUM_CORES; - case VX_CAPS_MAX_WARPS: - return NUM_WARPS; - case VX_CAPS_MAX_THREADS: - return NUM_THREADS; - case VX_CAPS_CACHE_LINESIZE: - return 64; - case VX_CAPS_LOCAL_MEM_SIZE: - return 0xffffffff; - case VX_CAPS_ALLOC_BASE_ADDR: - return 0x10000000; - case VX_CAPS_KERNEL_BASE_ADDR: - return 0x80000000; - default: - std::cout << "invalid caps id: " << caps_id << std::endl; - std::abort(); - return 0; - } -} - extern int vx_upload_kernel_bytes(vx_device_h device, const void* content, size_t size) { int err = 0; @@ -36,7 +11,10 @@ extern int vx_upload_kernel_bytes(vx_device_h device, const void* content, size_ return -1; uint32_t buffer_transfer_size = 65536; - uint32_t kernel_base_addr = vx_dev_caps(VX_CAPS_KERNEL_BASE_ADDR); + unsigned kernel_base_addr; + err = vx_dev_caps(device, VX_CAPS_KERNEL_BASE_ADDR, &kernel_base_addr); + if (err != 0) + return -1; // allocate device buffer vx_buffer_h buffer; @@ -47,7 +25,7 @@ extern int vx_upload_kernel_bytes(vx_device_h device, const void* content, size_ // get buffer address auto buf_ptr = (uint8_t*)vx_host_ptr(buffer); - #if defined(USE_SIMX) +#if defined(USE_SIMX) // default startup routine ((uint32_t*)buf_ptr)[0] = 0xf1401073; ((uint32_t*)buf_ptr)[1] = 0xf1401073; diff --git a/driver/include/vortex.h b/driver/include/vortex.h index 2f379b11..a9597253 100644 --- a/driver/include/vortex.h +++ b/driver/include/vortex.h @@ -21,15 +21,15 @@ typedef void* vx_buffer_h; #define VX_CAPS_ALLOC_BASE_ADDR 0x6 #define VX_CAPS_KERNEL_BASE_ADDR 0x7 -// return device configurations -int vx_dev_caps(int caps_id); - // open the device and connect to it int vx_dev_open(vx_device_h* hdevice); // Close the device when all the operations are done int vx_dev_close(vx_device_h hdevice); +// return device configurations +int vx_dev_caps(vx_device_h hdevice, unsigned caps_id, unsigned *value); + // Allocate shared buffer with device int vx_alloc_shared_mem(vx_device_h hdevice, size_t size, vx_buffer_h* hbuffer); @@ -58,10 +58,10 @@ int vx_start(vx_device_h hdevice); int vx_ready_wait(vx_device_h hdevice, long long timeout); // set device constant registers -int vx_set_regiters(int state, int value); +int vx_csr_set(vx_device_h hdevice, int core, int address, unsigned value); // get device constant registers -int vx_get_regiters(int state, int* value); +int vx_csr_get(vx_device_h hdevice, int core, int address, unsigned* value); ////////////////////////////// UTILITY FUNCIONS /////////////////////////////// diff --git a/driver/opae/scope.cpp b/driver/opae/scope.cpp index 1f642659..6053d353 100644 --- a/driver/opae/scope.cpp +++ b/driver/opae/scope.cpp @@ -18,8 +18,8 @@ return -1; \ } while (false) -#define MMIO_CSR_SCOPE_CMD (AFU_IMAGE_MMIO_CSR_SCOPE_CMD * 4) -#define MMIO_CSR_SCOPE_DATA (AFU_IMAGE_MMIO_CSR_SCOPE_DATA * 4) +#define MMIO_SCOPE_READ (AFU_IMAGE_MMIO_SCOPE_READ * 4) +#define MMIO_SCOPE_WRITE (AFU_IMAGE_MMIO_SCOPE_WRITE * 4) struct scope_signal_t { int width; @@ -136,7 +136,7 @@ int vx_scope_start(fpga_handle hfpga, uint64_t delay) { if (delay != uint64_t(-1)) { // set start delay uint64_t cmd_delay = ((delay << 3) | 4); - CHECK_RES(fpgaWriteMMIO64(hfpga, 0, MMIO_CSR_SCOPE_CMD, cmd_delay)); + CHECK_RES(fpgaWriteMMIO64(hfpga, 0, MMIO_SCOPE_WRITE, cmd_delay)); std::cout << "scope start delay: " << delay << std::endl; } @@ -150,7 +150,7 @@ int vx_scope_stop(fpga_handle hfpga, uint64_t delay) { if (delay != uint64_t(-1)) { // stop recording uint64_t cmd_stop = ((delay << 3) | 5); - CHECK_RES(fpgaWriteMMIO64(hfpga, 0, MMIO_CSR_SCOPE_CMD, cmd_stop)); + CHECK_RES(fpgaWriteMMIO64(hfpga, 0, MMIO_SCOPE_WRITE, cmd_stop)); std::cout << "scope stop delay: " << delay << std::endl; } @@ -170,9 +170,9 @@ int vx_scope_stop(fpga_handle hfpga, uint64_t delay) { uint64_t frame_width, max_frames, data_valid; // wait for recording to terminate - CHECK_RES(fpgaWriteMMIO64(hfpga, 0, MMIO_CSR_SCOPE_CMD, 0)); + CHECK_RES(fpgaWriteMMIO64(hfpga, 0, MMIO_SCOPE_WRITE, 0)); do { - CHECK_RES(fpgaReadMMIO64(hfpga, 0, MMIO_CSR_SCOPE_DATA, &data_valid)); + CHECK_RES(fpgaReadMMIO64(hfpga, 0, MMIO_SCOPE_READ, &data_valid)); if (data_valid) break; std::this_thread::sleep_for(std::chrono::seconds(1)); @@ -180,15 +180,15 @@ int vx_scope_stop(fpga_handle hfpga, uint64_t delay) { std::cout << "scope trace dump begin..." << std::endl; - CHECK_RES(fpgaWriteMMIO64(hfpga, 0, MMIO_CSR_SCOPE_CMD, 2)); - CHECK_RES(fpgaReadMMIO64(hfpga, 0, MMIO_CSR_SCOPE_DATA, &frame_width)); + CHECK_RES(fpgaWriteMMIO64(hfpga, 0, MMIO_SCOPE_WRITE, 2)); + CHECK_RES(fpgaReadMMIO64(hfpga, 0, MMIO_SCOPE_READ, &frame_width)); std::cout << "scope::frame_width=" << std::dec << frame_width << std::endl; - CHECK_RES(fpgaWriteMMIO64(hfpga, 0, MMIO_CSR_SCOPE_CMD, 3)); - CHECK_RES(fpgaReadMMIO64(hfpga, 0, MMIO_CSR_SCOPE_DATA, &max_frames)); + CHECK_RES(fpgaWriteMMIO64(hfpga, 0, MMIO_SCOPE_WRITE, 3)); + CHECK_RES(fpgaReadMMIO64(hfpga, 0, MMIO_SCOPE_READ, &max_frames)); std::cout << "scope::max_frames=" << std::dec << max_frames << std::endl; - CHECK_RES(fpgaWriteMMIO64(hfpga, 0, MMIO_CSR_SCOPE_CMD, 1)); + CHECK_RES(fpgaWriteMMIO64(hfpga, 0, MMIO_SCOPE_WRITE, 1)); if (fwidth != (int)frame_width) { std::cerr << "invalid frame_width: expecting " << std::dec << fwidth << "!" << std::endl; @@ -209,7 +209,7 @@ int vx_scope_stop(fpga_handle hfpga, uint64_t delay) { ofs << "b1 0" << std::endl; uint64_t delta; - fpga_result res = fpgaReadMMIO64(hfpga, 0, MMIO_CSR_SCOPE_DATA, &delta); + fpga_result res = fpgaReadMMIO64(hfpga, 0, MMIO_SCOPE_READ, &delta); assert(res == FPGA_OK); while (delta != 0) { @@ -228,14 +228,14 @@ int vx_scope_stop(fpga_handle hfpga, uint64_t delay) { do { if (frame_no == (max_frames-1)) { // verify last frame is valid - CHECK_RES(fpgaWriteMMIO64(hfpga, 0, MMIO_CSR_SCOPE_CMD, 0)); - CHECK_RES(fpgaReadMMIO64(hfpga, 0, MMIO_CSR_SCOPE_DATA, &data_valid)); + CHECK_RES(fpgaWriteMMIO64(hfpga, 0, MMIO_SCOPE_WRITE, 0)); + CHECK_RES(fpgaReadMMIO64(hfpga, 0, MMIO_SCOPE_READ, &data_valid)); assert(data_valid == 1); - CHECK_RES(fpgaWriteMMIO64(hfpga, 0, MMIO_CSR_SCOPE_CMD, 1)); + CHECK_RES(fpgaWriteMMIO64(hfpga, 0, MMIO_SCOPE_WRITE, 1)); } uint64_t word; - CHECK_RES(fpgaReadMMIO64(hfpga, 0, MMIO_CSR_SCOPE_DATA, &word)); + CHECK_RES(fpgaReadMMIO64(hfpga, 0, MMIO_SCOPE_READ, &word)); do { int signal_width = scope_signals[signal_id-1].width; @@ -267,8 +267,8 @@ int vx_scope_stop(fpga_handle hfpga, uint64_t delay) { std::cout << "scope trace dump done! - " << (timestamp/2) << " cycles" << std::endl; // verify data not valid - CHECK_RES(fpgaWriteMMIO64(hfpga, 0, MMIO_CSR_SCOPE_CMD, 0)); - CHECK_RES(fpgaReadMMIO64(hfpga, 0, MMIO_CSR_SCOPE_DATA, &data_valid)); + CHECK_RES(fpgaWriteMMIO64(hfpga, 0, MMIO_SCOPE_WRITE, 0)); + CHECK_RES(fpgaReadMMIO64(hfpga, 0, MMIO_SCOPE_READ, &data_valid)); assert(data_valid == 0); return 0; diff --git a/driver/opae/vortex.cpp b/driver/opae/vortex.cpp index ff020636..07e0385c 100755 --- a/driver/opae/vortex.cpp +++ b/driver/opae/vortex.cpp @@ -1,17 +1,24 @@ #include +#include #include #include +#include #include #include #include #include #include #include +#include #include "vortex_afu.h" #ifdef SCOPE #include "scope.h" #endif +#define CACHE_LINESIZE 64 +#define ALLOC_BASE_ADDR 0x10000000 +#define LOCAL_MEM_SIZE 0xffffffff + #define CHECK_RES(_expr) \ do { \ fpga_result res = _expr; \ @@ -24,22 +31,32 @@ /////////////////////////////////////////////////////////////////////////////// -#define CMD_TYPE_READ AFU_IMAGE_CMD_TYPE_READ -#define CMD_TYPE_WRITE AFU_IMAGE_CMD_TYPE_WRITE -#define CMD_TYPE_RUN AFU_IMAGE_CMD_TYPE_RUN -#define CMD_TYPE_CLFLUSH AFU_IMAGE_CMD_TYPE_CLFLUSH +#define CMD_MEM_READ AFU_IMAGE_CMD_MEM_READ +#define CMD_MEM_WRITE AFU_IMAGE_CMD_MEM_WRITE +#define CMD_RUN AFU_IMAGE_CMD_RUN +#define CMD_CLFLUSH AFU_IMAGE_CMD_CLFLUSH +#define CMD_CSR_READ AFU_IMAGE_CMD_CSR_READ +#define CMD_CSR_WRITE AFU_IMAGE_CMD_CSR_WRITE -#define MMIO_CSR_CMD (AFU_IMAGE_MMIO_CSR_CMD * 4) -#define MMIO_CSR_IO_ADDR (AFU_IMAGE_MMIO_CSR_IO_ADDR * 4) -#define MMIO_CSR_MEM_ADDR (AFU_IMAGE_MMIO_CSR_MEM_ADDR * 4) -#define MMIO_CSR_DATA_SIZE (AFU_IMAGE_MMIO_CSR_DATA_SIZE * 4) -#define MMIO_CSR_STATUS (AFU_IMAGE_MMIO_CSR_STATUS * 4) +#define MMIO_CMD_TYPE (AFU_IMAGE_MMIO_CMD_TYPE * 4) +#define MMIO_IO_ADDR (AFU_IMAGE_MMIO_IO_ADDR * 4) +#define MMIO_MEM_ADDR (AFU_IMAGE_MMIO_MEM_ADDR * 4) +#define MMIO_DATA_SIZE (AFU_IMAGE_MMIO_DATA_SIZE * 4) +#define MMIO_STATUS (AFU_IMAGE_MMIO_STATUS * 4) +#define MMIO_CSR_CORE (AFU_IMAGE_MMIO_CSR_CORE * 4) +#define MMIO_CSR_ADDR (AFU_IMAGE_MMIO_CSR_ADDR * 4) +#define MMIO_CSR_DATA (AFU_IMAGE_MMIO_CSR_DATA * 4) +#define MMIO_CSR_READ (AFU_IMAGE_MMIO_CSR_READ * 4) /////////////////////////////////////////////////////////////////////////////// typedef struct vx_device_ { fpga_handle fpga; size_t mem_allocation; + unsigned implementation_id; + unsigned num_cores; + unsigned num_warps; + unsigned num_threads; } vx_device_t; typedef struct vx_buffer_ { @@ -62,21 +79,58 @@ inline bool is_aligned(size_t addr, size_t alignment) { /////////////////////////////////////////////////////////////////////////////// +extern int vx_dev_caps(vx_device_h hdevice, unsigned caps_id, unsigned *value) { + if (nullptr == hdevice) + return -1; + + vx_device_t *device = ((vx_device_t*)hdevice); + + switch (caps_id) { + case VX_CAPS_VERSION: + *value = device->implementation_id; + break; + case VX_CAPS_MAX_CORES: + *value = device->num_cores; + break; + case VX_CAPS_MAX_WARPS: + *value = device->num_warps; + break; + case VX_CAPS_MAX_THREADS: + *value = device->num_threads; + break; + case VX_CAPS_CACHE_LINESIZE: + *value = CACHE_LINESIZE; + break; + case VX_CAPS_LOCAL_MEM_SIZE: + *value = LOCAL_MEM_SIZE; + break; + case VX_CAPS_ALLOC_BASE_ADDR: + *value = ALLOC_BASE_ADDR; + break; + case VX_CAPS_KERNEL_BASE_ADDR: + *value = STARTUP_ADDR; + break; + default: + fprintf(stderr, "invalid caps id: %d\n", caps_id); + std::abort(); + return -1; + } + + return 0; +} + extern int vx_dev_open(vx_device_h* hdevice) { + if (nullptr == hdevice) + return -1; + fpga_properties filter = nullptr; fpga_result res; fpga_guid guid; fpga_token accel_token; uint32_t num_matches; fpga_handle accel_handle; - vx_device_t* device; - - if (nullptr == hdevice) - return -1; - - // ensure that the block size 64 - assert(64 == vx_dev_caps(VX_CAPS_CACHE_LINESIZE)); - + vx_device_t* device; + // Set up a filter that will search for an accelerator fpgaGetProperties(nullptr, &filter); fpgaPropertiesSetObjectType(filter, FPGA_ACCELERATOR); @@ -114,17 +168,35 @@ extern int vx_dev_open(vx_device_h* hdevice) { } device->fpga = accel_handle; - device->mem_allocation = vx_dev_caps(VX_CAPS_ALLOC_BASE_ADDR); + device->mem_allocation = ALLOC_BASE_ADDR; - *hdevice = device; + { + // Load device CAPS + int ret = 0; + ret |= vx_csr_get(device, 0, CSR_IMPL_ID, &device->implementation_id); + ret |= vx_csr_get(device, 0, CSR_NC, &device->num_cores); + ret |= vx_csr_get(device, 0, CSR_NW, &device->num_warps); + ret |= vx_csr_get(device, 0, CSR_NT, &device->num_threads); + if (ret != 0) { + fpgaClose(accel_handle); + return ret; + } + + fprintf(stdout, "DEVCAPS: version=%d, num_cores=%d, num_warps=%d, num_threads=%d\n", + device->implementation_id, device->num_cores, device->num_warps, device->num_threads); + } #ifdef SCOPE { - int ret = vx_scope_start(device->fpga, 0); - if (ret != 0) + int ret = vx_scope_start(accel_handle, 0); + if (ret != 0) { + fpgaClose(accel_handle); return ret; + } } -#endif +#endif + + *hdevice = device; return 0; } @@ -139,6 +211,29 @@ extern int vx_dev_close(vx_device_h hdevice) { vx_scope_stop(device->fpga, 0); #endif + { + // Dump performance stats + uint64_t instrs, cycles; + unsigned value; + + int ret = 0; + ret |= vx_csr_get(hdevice, 0, CSR_INSTR_H, &value); + instrs = value; + ret |= vx_csr_get(hdevice, 0, CSR_INSTR_L, &value); + instrs = (instrs << 32) | value; + + ret |= vx_csr_get(hdevice, 0, CSR_CYCLE_H, &value); + cycles = value; + ret |= vx_csr_get(hdevice, 0, CSR_CYCLE_L, &value); + cycles = (cycles << 32) | value; + + float IPC = (float)(double(instrs) / double(cycles)); + + fprintf(stdout, "PERF: instrs=%ld, cycles=%ld, IPC=%f\n", instrs, cycles, IPC); + + assert(ret == 0); + } + fpgaClose(device->fpga); free(device); @@ -154,10 +249,8 @@ extern int vx_alloc_dev_mem(vx_device_h hdevice, size_t size, size_t* dev_maddr) vx_device_t *device = ((vx_device_t*)hdevice); - int line_size = vx_dev_caps(VX_CAPS_CACHE_LINESIZE); - size_t dev_mem_size = vx_dev_caps(VX_CAPS_LOCAL_MEM_SIZE); - - size_t asize = align_size(size, line_size); + size_t dev_mem_size = LOCAL_MEM_SIZE; + size_t asize = align_size(size, CACHE_LINESIZE); if (device->mem_allocation + asize > dev_mem_size) return -1; @@ -182,9 +275,7 @@ extern int vx_alloc_shared_mem(vx_device_h hdevice, size_t size, vx_buffer_h* hb vx_device_t *device = ((vx_device_t*)hdevice); - int line_size = vx_dev_caps(VX_CAPS_CACHE_LINESIZE); - - size_t asize = align_size(size, line_size); + size_t asize = align_size(size, CACHE_LINESIZE); res = fpgaPrepareBuffer(device->fpga, asize, &host_ptr, &wsid, 0); if (FPGA_OK != res) { @@ -260,7 +351,7 @@ extern int vx_ready_wait(vx_device_h hdevice, long long timeout) { long long sleep_time_ms = (sleep_time.tv_sec * 1000) + (sleep_time.tv_nsec / 1000000); for (;;) { - CHECK_RES(fpgaReadMMIO64(device->fpga, 0, MMIO_CSR_STATUS, &data)); + CHECK_RES(fpgaReadMMIO64(device->fpga, 0, MMIO_STATUS, &data)); if (0 == data || 0 == timeout) { if (data != 0) { fprintf(stdout, "ready-wait timed out: status=%ld\n", data); @@ -282,17 +373,15 @@ extern int vx_copy_to_dev(vx_buffer_h hbuffer, size_t dev_maddr, size_t size, si vx_buffer_t *buffer = ((vx_buffer_t*)hbuffer); vx_device_t *device = ((vx_device_t*)buffer->hdevice); - int line_size = vx_dev_caps(VX_CAPS_CACHE_LINESIZE); - size_t dev_mem_size = vx_dev_caps(VX_CAPS_LOCAL_MEM_SIZE); - - size_t asize = align_size(size, line_size); + size_t dev_mem_size = LOCAL_MEM_SIZE; + size_t asize = align_size(size, CACHE_LINESIZE); // check alignment - if (!is_aligned(dev_maddr, line_size)) + if (!is_aligned(dev_maddr, CACHE_LINESIZE)) return -1; - if (!is_aligned(buffer->io_addr + src_offset, line_size)) + if (!is_aligned(buffer->io_addr + src_offset, CACHE_LINESIZE)) return -1; - + // bound checking if (src_offset + asize > buffer->size) return -1; @@ -303,12 +392,12 @@ extern int vx_copy_to_dev(vx_buffer_h hbuffer, size_t dev_maddr, size_t size, si if (vx_ready_wait(buffer->hdevice, -1) != 0) return -1; - auto ls_shift = (int)std::log2(line_size); + auto ls_shift = (int)std::log2(CACHE_LINESIZE); - CHECK_RES(fpgaWriteMMIO64(device->fpga, 0, MMIO_CSR_IO_ADDR, (buffer->io_addr + src_offset) >> ls_shift)); - CHECK_RES(fpgaWriteMMIO64(device->fpga, 0, MMIO_CSR_MEM_ADDR, dev_maddr >> ls_shift)); - CHECK_RES(fpgaWriteMMIO64(device->fpga, 0, MMIO_CSR_DATA_SIZE, asize >> ls_shift)); - CHECK_RES(fpgaWriteMMIO64(device->fpga, 0, MMIO_CSR_CMD, CMD_TYPE_WRITE)); + CHECK_RES(fpgaWriteMMIO64(device->fpga, 0, MMIO_IO_ADDR, (buffer->io_addr + src_offset) >> ls_shift)); + CHECK_RES(fpgaWriteMMIO64(device->fpga, 0, MMIO_MEM_ADDR, dev_maddr >> ls_shift)); + CHECK_RES(fpgaWriteMMIO64(device->fpga, 0, MMIO_DATA_SIZE, asize >> ls_shift)); + CHECK_RES(fpgaWriteMMIO64(device->fpga, 0, MMIO_CMD_TYPE, CMD_MEM_WRITE)); // Wait for the write operation to finish if (vx_ready_wait(buffer->hdevice, -1) != 0) @@ -325,15 +414,13 @@ extern int vx_copy_from_dev(vx_buffer_h hbuffer, size_t dev_maddr, size_t size, vx_buffer_t *buffer = ((vx_buffer_t*)hbuffer); vx_device_t *device = ((vx_device_t*)buffer->hdevice); - int line_size = vx_dev_caps(VX_CAPS_CACHE_LINESIZE); - size_t dev_mem_size = vx_dev_caps(VX_CAPS_LOCAL_MEM_SIZE); - - size_t asize = align_size(size, line_size); + size_t dev_mem_size = LOCAL_MEM_SIZE; + size_t asize = align_size(size, CACHE_LINESIZE); // check alignment - if (!is_aligned(dev_maddr, line_size)) + if (!is_aligned(dev_maddr, CACHE_LINESIZE)) return -1; - if (!is_aligned(buffer->io_addr + dest_offset, line_size)) + if (!is_aligned(buffer->io_addr + dest_offset, CACHE_LINESIZE)) return -1; // bound checking @@ -346,12 +433,12 @@ extern int vx_copy_from_dev(vx_buffer_h hbuffer, size_t dev_maddr, size_t size, if (vx_ready_wait(buffer->hdevice, -1) != 0) return -1; - auto ls_shift = (int)std::log2(line_size); + auto ls_shift = (int)std::log2(CACHE_LINESIZE); - CHECK_RES(fpgaWriteMMIO64(device->fpga, 0, MMIO_CSR_IO_ADDR, (buffer->io_addr + dest_offset) >> ls_shift)); - CHECK_RES(fpgaWriteMMIO64(device->fpga, 0, MMIO_CSR_MEM_ADDR, dev_maddr >> ls_shift)); - CHECK_RES(fpgaWriteMMIO64(device->fpga, 0, MMIO_CSR_DATA_SIZE, asize >> ls_shift)); - CHECK_RES(fpgaWriteMMIO64(device->fpga, 0, MMIO_CSR_CMD, CMD_TYPE_READ)); + CHECK_RES(fpgaWriteMMIO64(device->fpga, 0, MMIO_IO_ADDR, (buffer->io_addr + dest_offset) >> ls_shift)); + CHECK_RES(fpgaWriteMMIO64(device->fpga, 0, MMIO_MEM_ADDR, dev_maddr >> ls_shift)); + CHECK_RES(fpgaWriteMMIO64(device->fpga, 0, MMIO_DATA_SIZE, asize >> ls_shift)); + CHECK_RES(fpgaWriteMMIO64(device->fpga, 0, MMIO_CMD_TYPE, CMD_MEM_READ)); // Wait for the write operation to finish if (vx_ready_wait(buffer->hdevice, -1) != 0) @@ -367,23 +454,21 @@ extern int vx_flush_caches(vx_device_h hdevice, size_t dev_maddr, size_t size) { vx_device_t* device = ((vx_device_t*)hdevice); - int line_size = vx_dev_caps(VX_CAPS_CACHE_LINESIZE); - - size_t asize = align_size(size, line_size); + size_t asize = align_size(size, CACHE_LINESIZE); // check alignment - if (!is_aligned(dev_maddr, line_size)) + if (!is_aligned(dev_maddr, CACHE_LINESIZE)) return -1; // Ensure ready for new command if (vx_ready_wait(hdevice, -1) != 0) return -1; - auto ls_shift = (int)std::log2(line_size); + auto ls_shift = (int)std::log2(CACHE_LINESIZE); - CHECK_RES(fpgaWriteMMIO64(device->fpga, 0, MMIO_CSR_MEM_ADDR, dev_maddr >> ls_shift)); - CHECK_RES(fpgaWriteMMIO64(device->fpga, 0, MMIO_CSR_DATA_SIZE, asize >> ls_shift)); - CHECK_RES(fpgaWriteMMIO64(device->fpga, 0, MMIO_CSR_CMD, CMD_TYPE_CLFLUSH)); + CHECK_RES(fpgaWriteMMIO64(device->fpga, 0, MMIO_MEM_ADDR, dev_maddr >> ls_shift)); + CHECK_RES(fpgaWriteMMIO64(device->fpga, 0, MMIO_DATA_SIZE, asize >> ls_shift)); + CHECK_RES(fpgaWriteMMIO64(device->fpga, 0, MMIO_CMD_TYPE, CMD_CLFLUSH)); // Wait for the write operation to finish if (vx_ready_wait(hdevice, -1) != 0) @@ -396,13 +481,62 @@ extern int vx_start(vx_device_h hdevice) { if (nullptr == hdevice) return -1; + vx_device_t *device = ((vx_device_t*)hdevice); + // Ensure ready for new command if (vx_ready_wait(hdevice, -1) != 0) return -1; - // start execution + // start execution + CHECK_RES(fpgaWriteMMIO64(device->fpga, 0, MMIO_CMD_TYPE, CMD_RUN)); + + return 0; +} + +// set device constant registers +extern int vx_csr_set(vx_device_h hdevice, int core, int address, unsigned value) { + if (nullptr == hdevice) + return -1; + vx_device_t *device = ((vx_device_t*)hdevice); - CHECK_RES(fpgaWriteMMIO64(device->fpga, 0, MMIO_CSR_CMD, CMD_TYPE_RUN)); + + // Ensure ready for new command + if (vx_ready_wait(hdevice, -1) != 0) + return -1; + + // write CSR value + CHECK_RES(fpgaWriteMMIO64(device->fpga, 0, MMIO_CSR_CORE, core)); + CHECK_RES(fpgaWriteMMIO64(device->fpga, 0, MMIO_CSR_ADDR, address)); + CHECK_RES(fpgaWriteMMIO64(device->fpga, 0, MMIO_CSR_DATA, value)); + CHECK_RES(fpgaWriteMMIO64(device->fpga, 0, MMIO_CMD_TYPE, CMD_CSR_WRITE)); + + return 0; +} + +// get device constant registers +extern int vx_csr_get(vx_device_h hdevice, int core, int address, unsigned* value) { + if (nullptr == hdevice || nullptr == value) + return -1; + + vx_device_t *device = ((vx_device_t*)hdevice); + + // Ensure ready for new command + if (vx_ready_wait(hdevice, -1) != 0) + return -1; + + + // write CSR value + CHECK_RES(fpgaWriteMMIO64(device->fpga, 0, MMIO_CSR_CORE, core)); + CHECK_RES(fpgaWriteMMIO64(device->fpga, 0, MMIO_CSR_ADDR, address)); + CHECK_RES(fpgaWriteMMIO64(device->fpga, 0, MMIO_CMD_TYPE, CMD_CSR_READ)); + + // Ensure ready for new command + if (vx_ready_wait(hdevice, -1) != 0) + return -1; + + uint64_t value64; + CHECK_RES(fpgaReadMMIO64(device->fpga, 0, MMIO_CSR_READ, &value64)); + *value = (unsigned)value64; return 0; } \ No newline at end of file diff --git a/driver/rtlsim/Makefile b/driver/rtlsim/Makefile index 4129ade5..d0890c4c 100644 --- a/driver/rtlsim/Makefile +++ b/driver/rtlsim/Makefile @@ -34,7 +34,7 @@ TOP = Vortex SRCS = vortex.cpp ../common/vx_utils.cpp ../../hw/simulate/simulator.cpp -RTL_INCLUDE = -I../../hw/rtl -I../../hw/rtl/libs -I../../hw/rtl/interfaces -I../../hw/rtl/pipe_regs -I../../hw/rtl/cache +RTL_INCLUDE = -I../../hw/rtl -I../../hw/rtl/libs -I../../hw/rtl/interfaces -I../../hw/rtl/cache VL_FLAGS += --language 1800-2009 --assert -Wall -Wpedantic $(CONFIGS) VL_FLAGS += -Wno-DECLFILENAME @@ -56,8 +56,10 @@ endif # AFU ifdef AFU TOP = vortex_afu_sim - VL_FLAGS += -DNOPAE -DSCOPE - CFLAGS += -DNOPAE -DSCOPE + VL_FLAGS += -DNOPAE + CFLAGS += -DNOPAE + #VL_FLAGS += -DSCOPE + #CFLAGS += -DSCOPE RTL_INCLUDE += -I../../hw/opae -I../../hw/opae/ccip endif diff --git a/driver/rtlsim/vortex.cpp b/driver/rtlsim/vortex.cpp index 5550c821..51c3bb8c 100644 --- a/driver/rtlsim/vortex.cpp +++ b/driver/rtlsim/vortex.cpp @@ -7,14 +7,19 @@ #include #include +#include #include #include +#define CACHE_LINESIZE 64 +#define ALLOC_BASE_ADDR 0x10000000 +#define LOCAL_MEM_SIZE 0xffffffff + /////////////////////////////////////////////////////////////////////////////// -static size_t align_size(size_t size) { - uint32_t cache_block_size = vx_dev_caps(VX_CAPS_CACHE_LINESIZE); - return cache_block_size * ((size + cache_block_size - 1) / cache_block_size); +inline size_t align_size(size_t size, size_t alignment) { + assert(0 == (alignment & (alignment - 1))); + return (size + alignment - 1) & ~(alignment - 1); } /////////////////////////////////////////////////////////////////////////////// @@ -26,7 +31,7 @@ public: vx_buffer(size_t size, vx_device* device) : size_(size) , device_(device) { - auto aligned_asize = align_size(size); + auto aligned_asize = align_size(size, CACHE_LINESIZE); data_ = malloc(aligned_asize); } @@ -59,7 +64,7 @@ private: class vx_device { public: vx_device() { - mem_allocation_ = vx_dev_caps(VX_CAPS_ALLOC_BASE_ADDR); + mem_allocation_ = ALLOC_BASE_ADDR; simulator_.attach_ram(&ram_); } @@ -70,8 +75,8 @@ public: } int alloc_local_mem(size_t size, size_t* dev_maddr) { - size_t asize = align_size(size); - auto dev_mem_size = vx_dev_caps(VX_CAPS_LOCAL_MEM_SIZE); + auto dev_mem_size = LOCAL_MEM_SIZE; + size_t asize = align_size(size, CACHE_LINESIZE); if (mem_allocation_ + asize > dev_mem_size) return -1; *dev_maddr = mem_allocation_; @@ -80,7 +85,7 @@ public: } int upload(void* src, size_t dest_addr, size_t size, size_t src_offset) { - size_t asize = align_size(size); + size_t asize = align_size(size, CACHE_LINESIZE); if (dest_addr + asize > ram_.size()) return -1; @@ -94,7 +99,7 @@ public: } int download(const void* dest, size_t src_addr, size_t size, size_t dest_offset) { - size_t asize = align_size(size); + size_t asize = align_size(size, CACHE_LINESIZE); if (src_addr + asize > ram_.size()) return -1; @@ -156,6 +161,44 @@ private: /////////////////////////////////////////////////////////////////////////////// +extern int vx_dev_caps(vx_device_h hdevice, unsigned caps_id, unsigned *value) { + if (nullptr == hdevice) + return -1; + + switch (caps_id) { + case VX_CAPS_VERSION: + *value = IMPLEMENTATION_ID; + break; + case VX_CAPS_MAX_CORES: + *value = NUM_CORES; + break; + case VX_CAPS_MAX_WARPS: + *value = NUM_WARPS; + break; + case VX_CAPS_MAX_THREADS: + *value = NUM_THREADS; + break; + case VX_CAPS_CACHE_LINESIZE: + *value = CACHE_LINESIZE; + break; + case VX_CAPS_LOCAL_MEM_SIZE: + *value = 0xffffffff; + break; + case VX_CAPS_ALLOC_BASE_ADDR: + *value = 0x10000000; + break; + case VX_CAPS_KERNEL_BASE_ADDR: + *value = STARTUP_ADDR; + break; + default: + std::cout << "invalid caps id: " << caps_id << std::endl; + std::abort(); + return -1; + } + + return 0; +} + extern int vx_dev_open(vx_device_h* hdevice) { if (nullptr == hdevice) return -1; diff --git a/driver/simx/vortex.cpp b/driver/simx/vortex.cpp index 394e1db2..981ca5c1 100644 --- a/driver/simx/vortex.cpp +++ b/driver/simx/vortex.cpp @@ -11,13 +11,16 @@ #include #include -#define PAGE_SIZE 4096 +#define CACHE_LINESIZE 64 +#define PAGE_SIZE 4096 +#define ALLOC_BASE_ADDR 0x10000000 +#define LOCAL_MEM_SIZE 0xffffffff /////////////////////////////////////////////////////////////////////////////// -static size_t align_size(size_t size) { - uint32_t cache_block_size = vx_dev_caps(VX_CAPS_CACHE_LINESIZE); - return cache_block_size * ((size + cache_block_size - 1) / cache_block_size); +inline size_t align_size(size_t size, size_t alignment) { + assert(0 == (alignment & (alignment - 1))); + return (size + alignment - 1) & ~(alignment - 1); } /////////////////////////////////////////////////////////////////////////////// @@ -29,7 +32,7 @@ public: vx_buffer(size_t size, vx_device* device) : size_(size) , device_(device) { - auto aligned_asize = align_size(size); + auto aligned_asize = align_size(size, CACHE_LINESIZE); data_ = malloc(aligned_asize); } @@ -65,7 +68,7 @@ public: : is_done_(false) , is_running_(false) , thread_(__thread_proc__, this) { - mem_allocation_ = vx_dev_caps(VX_CAPS_ALLOC_BASE_ADDR); + mem_allocation_ = ALLOC_BASE_ADDR; } ~vx_device() { @@ -77,8 +80,8 @@ public: } int alloc_local_mem(size_t size, size_t* dev_maddr) { - auto asize = align_size(size); - auto dev_mem_size = vx_dev_caps(VX_CAPS_LOCAL_MEM_SIZE); + auto dev_mem_size = LOCAL_MEM_SIZE; + auto asize = align_size(size, CACHE_LINESIZE); if (mem_allocation_ + asize > dev_mem_size) return -1; *dev_maddr = mem_allocation_; @@ -87,7 +90,7 @@ public: } int upload(void* src, size_t dest_addr, size_t size, size_t src_offset) { - auto asize = align_size(size); + auto asize = align_size(size, CACHE_LINESIZE); if (dest_addr + asize > ram_.size()) return -1; @@ -101,7 +104,7 @@ public: } int download(const void* dest, size_t src_addr, size_t size, size_t dest_offset) { - size_t asize = align_size(size); + size_t asize = align_size(size, CACHE_LINESIZE); if (src_addr + asize > ram_.size()) return -1; @@ -216,6 +219,44 @@ extern int vx_dev_close(vx_device_h hdevice) { return 0; } +extern int vx_dev_caps(vx_device_h hdevice, unsigned caps_id, unsigned *value) { + if (nullptr == hdevice) + return -1; + + switch (caps_id) { + case VX_CAPS_VERSION: + *value = IMPLEMENTATION_ID; + break; + case VX_CAPS_MAX_CORES: + *value = NUM_CORES; + break; + case VX_CAPS_MAX_WARPS: + *value = NUM_WARPS; + break; + case VX_CAPS_MAX_THREADS: + *value = NUM_THREADS; + break; + case VX_CAPS_CACHE_LINESIZE: + *value = CACHE_LINESIZE; + break; + case VX_CAPS_LOCAL_MEM_SIZE: + *value = LOCAL_MEM_SIZE; + break; + case VX_CAPS_ALLOC_BASE_ADDR: + *value = ALLOC_BASE_ADDR; + break; + case VX_CAPS_KERNEL_BASE_ADDR: + *value = STARTUP_ADDR; + break; + default: + std::cout << "invalid caps id: " << caps_id << std::endl; + std::abort(); + return -1; + } + + return 0; +} + extern int vx_alloc_dev_mem(vx_device_h hdevice, size_t size, size_t* dev_maddr) { if (nullptr == hdevice || nullptr == dev_maddr diff --git a/driver/stub/vortex.cpp b/driver/stub/vortex.cpp index 13f09ae5..532e64d7 100644 --- a/driver/stub/vortex.cpp +++ b/driver/stub/vortex.cpp @@ -8,6 +8,10 @@ extern int vx_dev_close(vx_device_h /*hdevice*/) { return -1; } +extern int vx_dev_caps(vx_device_h /*hdevice*/, unsigned /*caps_id*/, unsigned* /*value*/) { + return -1; +} + extern int vx_alloc_dev_mem(vx_device_h /*hdevice*/, size_t /*size*/, size_t* /*dev_maddr*/) { return -1; } diff --git a/driver/tests/basic/basic.cpp b/driver/tests/basic/basic.cpp index 7301e12d..92a785f4 100755 --- a/driver/tests/basic/basic.cpp +++ b/driver/tests/basic/basic.cpp @@ -179,7 +179,12 @@ int main(int argc, char *argv[]) { count = 1; } - uint32_t max_cores = vx_dev_caps(VX_CAPS_MAX_CORES); + // open device connection + std::cout << "open device connection" << std::endl; + RT_CHECK(vx_dev_open(&device)); + + unsigned max_cores; + RT_CHECK(vx_dev_caps(device, VX_CAPS_MAX_CORES, &max_cores)); uint32_t num_points = max_cores * count; uint32_t num_blocks = (num_points * sizeof(uint32_t) + 63) / 64; uint32_t buf_size = num_blocks * 64; @@ -187,10 +192,6 @@ int main(int argc, char *argv[]) { std::cout << "number of points: " << num_points << std::endl; std::cout << "buffer size: " << buf_size << " bytes" << std::endl; - // open device connection - std::cout << "open device connection" << std::endl; - RT_CHECK(vx_dev_open(&device)); - // allocate device memory RT_CHECK(vx_alloc_dev_mem(device, buf_size, &value)); kernel_arg.src_ptr = value; diff --git a/driver/tests/demo/demo.cpp b/driver/tests/demo/demo.cpp index 71f42e0b..2d5b47f8 100644 --- a/driver/tests/demo/demo.cpp +++ b/driver/tests/demo/demo.cpp @@ -110,9 +110,14 @@ int main(int argc, char *argv[]) { count = 1; } - uint32_t max_cores = vx_dev_caps(VX_CAPS_MAX_CORES); - uint32_t max_warps = vx_dev_caps(VX_CAPS_MAX_WARPS); - uint32_t max_threads = vx_dev_caps(VX_CAPS_MAX_THREADS); + // open device connection + std::cout << "open device connection" << std::endl; + RT_CHECK(vx_dev_open(&device)); + + unsigned max_cores, max_warps, max_threads; + RT_CHECK(vx_dev_caps(device, VX_CAPS_MAX_CORES, &max_cores)); + RT_CHECK(vx_dev_caps(device, VX_CAPS_MAX_WARPS, &max_warps)); + RT_CHECK(vx_dev_caps(device, VX_CAPS_MAX_THREADS, &max_threads)); uint32_t num_points = count * max_cores * max_warps * max_threads; uint32_t buf_size = num_points * sizeof(uint32_t); @@ -120,10 +125,6 @@ int main(int argc, char *argv[]) { std::cout << "number of points: " << num_points << std::endl; std::cout << "buffer size: " << buf_size << " bytes" << std::endl; - // open device connection - std::cout << "open device connection" << std::endl; - RT_CHECK(vx_dev_open(&device)); - // upload program std::cout << "upload program" << std::endl; RT_CHECK(vx_upload_kernel_file(device, kernel_file)); diff --git a/driver/tests/demo/kernel.bin b/driver/tests/demo/kernel.bin index aea7c061..06939d4c 100644 Binary files a/driver/tests/demo/kernel.bin and b/driver/tests/demo/kernel.bin differ diff --git a/hw/modelsim/Makefile b/hw/modelsim/Makefile index 16cec83a..6a7b6244 100644 --- a/hw/modelsim/Makefile +++ b/hw/modelsim/Makefile @@ -69,8 +69,8 @@ SRC = \ ../rtl/cache/VX_generic_pe.v \ ../rtl/cache/cache_set.v \ ../rtl/cache/VX_cache_data_per_index.v \ -../rtl/pipe_regs/VX_d_e_reg.v \ -../rtl/pipe_regs/VX_f_d_reg.v \ +../rtl/VX_d_e_reg.v \ +../rtl/VX_f_d_reg.v \ ../models/memory/cln28hpm/rf2_128x128_wm1/rf2_128x128_wm1.v \ ../models/memory/cln28hpm/rf2_256x128_wm1/rf2_256x128_wm1.v \ ../models/memory/cln28hpm/rf2_256x19_wm0/rf2_256x19_wm0.v \ diff --git a/hw/opae/README b/hw/opae/README index fc164bfc..86e6f862 100644 --- a/hw/opae/README +++ b/hw/opae/README @@ -62,6 +62,7 @@ make ase # tests ./run_ase.sh build_ase_1c ../../driver/tests/basic/basic ./run_ase.sh build_ase_1c ../../driver/tests/demo/demo +./run_ase.sh build_ase_1c ../../benchmarks/opencl/vecadd/vecadd # modify "vsim_run.tcl" to dump VCD trace vcd file vortex.vcd diff --git a/hw/opae/run_ase.sh b/hw/opae/run_ase.sh index 9a0fbf64..9e3b5d6c 100755 --- a/hw/opae/run_ase.sh +++ b/hw/opae/run_ase.sh @@ -7,6 +7,9 @@ BUILD_DIR=$1 PROGRAM=$(basename "$2") PROGRAM_DIR=`dirname $2` +POCL_RT_PATH=$SCRIPT_DIR/../../benchmarks/opencl/runtime/lib +VORTEX_DRV_PATH=$SCRIPT_DIR/../../driver/opae/ase + # Export ASE_WORKDIR variable export ASE_WORKDIR=$SCRIPT_DIR/$BUILD_DIR/work @@ -33,5 +36,5 @@ done # run application pushd $PROGRAM_DIR echo " [DBG] running ./$PROGRAM $*" -ASE_LOG=0 LD_LIBRARY_PATH=../../opae/ase:$LD_LIBRARY_PATH ./$PROGRAM $* +ASE_LOG=0 LD_LIBRARY_PATH=$POCL_RT_PATH:$VORTEX_DRV_PATH:$LD_LIBRARY_PATH ./$PROGRAM $* popd \ No newline at end of file diff --git a/hw/opae/sources.txt b/hw/opae/sources.txt index 6058a31a..0b448e88 100644 --- a/hw/opae/sources.txt +++ b/hw/opae/sources.txt @@ -48,6 +48,8 @@ QI:vortex_afu.qsf ../rtl/interfaces/VX_cache_snp_req_if.v ../rtl/interfaces/VX_cache_snp_rsp_if.v ../rtl/interfaces/VX_csr_req_if.v +../rtl/interfaces/VX_csr_io_req_if.v +../rtl/interfaces/VX_csr_io_rsp_if.v ../rtl/interfaces/VX_exec_unit_req_if.v ../rtl/interfaces/VX_backend_req_if.v ../rtl/interfaces/VX_gpr_read_if.v @@ -67,6 +69,7 @@ QI:vortex_afu.qsf ../rtl/libs/VX_priority_encoder.v ../rtl/libs/VX_generic_queue.v ../rtl/libs/VX_indexable_queue.v +../rtl/libs/VX_fair_arbiter.v ../rtl/libs/VX_fixed_arbiter.v ../rtl/libs/VX_rr_arbiter.v ../rtl/libs/VX_countones.v @@ -89,6 +92,8 @@ QI:vortex_afu.qsf ../rtl/VX_writeback.v ../rtl/VX_csr_pipe.v ../rtl/VX_csr_data.v +../rtl/VX_csr_arb.v +../rtl/VX_csr_io_arb.v ../rtl/VX_warp_sched.v ../rtl/VX_gpr_ram.v ../rtl/VX_gpr_stage.v @@ -98,10 +103,9 @@ QI:vortex_afu.qsf ../rtl/VX_inst_multiplex.v ../rtl/VX_dcache_arb.v ../rtl/VX_mem_arb.v - -../rtl/pipe_regs/VX_f_d_reg.v -../rtl/pipe_regs/VX_i_d_reg.v -../rtl/pipe_regs/VX_d_e_reg.v +../rtl/VX_f_d_reg.v +../rtl/VX_i_d_reg.v +../rtl/VX_d_e_reg.v ccip_interface_reg.sv ccip_std_afu.sv diff --git a/hw/opae/vortex_afu.json b/hw/opae/vortex_afu.json index 98dcecfd..fb1e908c 100644 --- a/hw/opae/vortex_afu.json +++ b/hw/opae/vortex_afu.json @@ -5,18 +5,24 @@ "clock-frequency-high": "auto", "clock-frequency-low": "auto", - "mmio-csr-cmd": 10, - "mmio-csr-io-addr": 12, - "mmio-csr-mem-addr": 14, - "mmio-csr-data-size": 16, - "mmio-csr-status": 18, - "mmio-csr-scope-cmd": 20, - "mmio-csr-scope-data": 22, + "cmd-mem-read": 1, + "cmd-mem-write": 2, + "cmd-run": 3, + "cmd-clflush": 4, + "cmd-csr-read": 5, + "cmd-csr-write": 6, - "cmd-type-read": 1, - "cmd-type-write": 2, - "cmd-type-run": 3, - "cmd-type-clflush": 4, + "mmio-cmd-type": 10, + "mmio-io-addr": 12, + "mmio-mem-addr": 14, + "mmio-data-size": 16, + "mmio-status": 18, + "mmio-scope-read": 20, + "mmio-scope-write": 22, + "mmio-csr-core": 24, + "mmio-csr-addr": 26, + "mmio-csr-data": 28, + "mmio-csr-read": 30, "afu-top-interface": { diff --git a/hw/opae/vortex_afu.sv b/hw/opae/vortex_afu.sv index 0650c0ac..5f13fd77 100644 --- a/hw/opae/vortex_afu.sv +++ b/hw/opae/vortex_afu.sv @@ -53,19 +53,26 @@ localparam CCI_RW_QUEUE_SIZE = 1024; localparam AFU_ID_L = 16'h0002; // AFU ID Lower localparam AFU_ID_H = 16'h0004; // AFU ID Higher -localparam CMD_TYPE_READ = `AFU_IMAGE_CMD_TYPE_READ; -localparam CMD_TYPE_WRITE = `AFU_IMAGE_CMD_TYPE_WRITE; -localparam CMD_TYPE_RUN = `AFU_IMAGE_CMD_TYPE_RUN; -localparam CMD_TYPE_CLFLUSH = `AFU_IMAGE_CMD_TYPE_CLFLUSH; +localparam CMD_MEM_READ = `AFU_IMAGE_CMD_MEM_READ; +localparam CMD_MEM_WRITE = `AFU_IMAGE_CMD_MEM_WRITE; +localparam CMD_RUN = `AFU_IMAGE_CMD_RUN; +localparam CMD_CLFLUSH = `AFU_IMAGE_CMD_CLFLUSH; +localparam CMD_CSR_READ = `AFU_IMAGE_CMD_CSR_READ; +localparam CMD_CSR_WRITE = `AFU_IMAGE_CMD_CSR_WRITE; -localparam MMIO_CSR_CMD = `AFU_IMAGE_MMIO_CSR_CMD; -localparam MMIO_CSR_IO_ADDR = `AFU_IMAGE_MMIO_CSR_IO_ADDR; -localparam MMIO_CSR_MEM_ADDR = `AFU_IMAGE_MMIO_CSR_MEM_ADDR; -localparam MMIO_CSR_DATA_SIZE = `AFU_IMAGE_MMIO_CSR_DATA_SIZE; -localparam MMIO_CSR_STATUS = `AFU_IMAGE_MMIO_CSR_STATUS; +localparam MMIO_CMD_TYPE = `AFU_IMAGE_MMIO_CMD_TYPE; +localparam MMIO_IO_ADDR = `AFU_IMAGE_MMIO_IO_ADDR; +localparam MMIO_MEM_ADDR = `AFU_IMAGE_MMIO_MEM_ADDR; +localparam MMIO_DATA_SIZE = `AFU_IMAGE_MMIO_DATA_SIZE; +localparam MMIO_STATUS = `AFU_IMAGE_MMIO_STATUS; -localparam MMIO_CSR_SCOPE_CMD = `AFU_IMAGE_MMIO_CSR_SCOPE_CMD; -localparam MMIO_CSR_SCOPE_DATA= `AFU_IMAGE_MMIO_CSR_SCOPE_DATA; +localparam MMIO_SCOPE_READ = `AFU_IMAGE_MMIO_SCOPE_READ; +localparam MMIO_SCOPE_WRITE = `AFU_IMAGE_MMIO_SCOPE_WRITE; + +localparam MMIO_CSR_CORE = `AFU_IMAGE_MMIO_CSR_CORE; +localparam MMIO_CSR_ADDR = `AFU_IMAGE_MMIO_CSR_ADDR; +localparam MMIO_CSR_DATA = `AFU_IMAGE_MMIO_CSR_DATA; +localparam MMIO_CSR_READ = `AFU_IMAGE_MMIO_CSR_READ; logic [127:0] afu_id = `AFU_ACCEL_UUID; @@ -75,7 +82,9 @@ typedef enum logic[3:0] { STATE_WRITE, STATE_START, STATE_RUN, - STATE_CLFLUSH + STATE_CLFLUSH, + STATE_CSR_READ, + STATE_CSR_WRITE } state_t; typedef logic [$clog2(CCI_RD_WINDOW_SIZE)-1:0] t_cci_rdq_tag; @@ -114,6 +123,17 @@ logic [`VX_SNP_TAG_WIDTH-1:0] vx_snp_rsp_tag; `DEBUG_END logic vx_snp_rsp_ready; +logic vx_csr_io_req_valid; +logic [`VX_CSR_ID_WIDTH-1:0] vx_csr_io_req_coreid; +logic [11:0] vx_csr_io_req_addr; +logic vx_csr_io_req_rw; +logic [31:0] vx_csr_io_req_data; +logic vx_csr_io_req_ready; + +logic vx_csr_io_rsp_valid; +logic [31:0] vx_csr_io_rsp_data; +logic vx_csr_io_rsp_ready; + logic vx_reset; logic vx_busy; @@ -134,20 +154,25 @@ logic avs_rdq_empty; logic avs_rdq_full; `DEBUG_END -// CSR variables ////////////////////////////////////////////////////////////// +// CMD variables ////////////////////////////////////////////////////////////// -logic [2:0] csr_cmd; -t_ccip_clAddr csr_io_addr; -logic[DRAM_ADDR_WIDTH-1:0] csr_mem_addr; -logic[DRAM_ADDR_WIDTH-1:0] csr_data_size; +logic [2:0] cmd_type; +t_ccip_clAddr cmd_io_addr; +logic[DRAM_ADDR_WIDTH-1:0] cmd_mem_addr; +logic[DRAM_ADDR_WIDTH-1:0] cmd_data_size; `ifdef SCOPE -logic [63:0] csr_scope_cmd; -logic [63:0] csr_scope_data; -logic csr_scope_read; -logic csr_scope_write; +logic [63:0] cmd_scope_rdata; +logic [63:0] cmd_scope_wdata; +logic cmd_scope_read; +logic cmd_scope_write; `endif +logic [`VX_CSR_ID_WIDTH-1:0] cmd_csr_core; +logic [11:0] cmd_csr_addr; +logic [31:0] cmd_csr_rdata; +logic [31:0] cmd_csr_wdata; + // MMIO controller //////////////////////////////////////////////////////////// `IGNORE_WARNINGS_BEGIN @@ -159,9 +184,9 @@ t_if_ccip_c2_Tx mmio_tx; assign af2cp_sTxPort.c2 = mmio_tx; `ifdef SCOPE -assign csr_scope_cmd = 64'(cp2af_sRxPort.c0.data); -assign csr_scope_write = cp2af_sRxPort.c0.mmioWrValid && (MMIO_CSR_SCOPE_CMD == mmio_hdr.address); -assign csr_scope_read = cp2af_sRxPort.c0.mmioRdValid && (MMIO_CSR_SCOPE_DATA == mmio_hdr.address); +assign cmd_scope_wdata = 64'(cp2af_sRxPort.c0.data); +assign cmd_scope_read = cp2af_sRxPort.c0.mmioRdValid && (MMIO_SCOPE_READ == mmio_hdr.address); +assign cmd_scope_write = cp2af_sRxPort.c0.mmioWrValid && (MMIO_SCOPE_WRITE == mmio_hdr.address); `endif always_ff @(posedge clk) @@ -170,57 +195,69 @@ begin mmio_tx.hdr <= 0; mmio_tx.data <= 0; mmio_tx.mmioRdValid <= 0; - csr_cmd <= 0; - csr_io_addr <= 0; - csr_mem_addr <= 0; - csr_data_size <= 0; + cmd_type <= 0; + cmd_io_addr <= 0; + cmd_mem_addr <= 0; + cmd_data_size <= 0; end else begin - csr_cmd <= 0; + cmd_type <= 0; mmio_tx.mmioRdValid <= 0; // serve MMIO write request if (cp2af_sRxPort.c0.mmioWrValid) begin case (mmio_hdr.address) - MMIO_CSR_IO_ADDR: begin - csr_io_addr <= t_ccip_clAddr'(cp2af_sRxPort.c0.data); + MMIO_IO_ADDR: begin + cmd_io_addr <= t_ccip_clAddr'(cp2af_sRxPort.c0.data); `ifdef DBG_PRINT_OPAE - $display("%t: CSR_IO_ADDR: 0x%0h", $time, t_ccip_clAddr'(cp2af_sRxPort.c0.data)); + $display("%t: MMIO_IO_ADDR: 0x%0h", $time, t_ccip_clAddr'(cp2af_sRxPort.c0.data)); `endif end - MMIO_CSR_MEM_ADDR: begin - csr_mem_addr <= t_local_mem_addr'(cp2af_sRxPort.c0.data); + MMIO_MEM_ADDR: begin + cmd_mem_addr <= t_local_mem_addr'(cp2af_sRxPort.c0.data); `ifdef DBG_PRINT_OPAE - $display("%t: CSR_MEM_ADDR: 0x%0h", $time, t_local_mem_addr'(cp2af_sRxPort.c0.data)); + $display("%t: MMIO_MEM_ADDR: 0x%0h", $time, t_local_mem_addr'(cp2af_sRxPort.c0.data)); `endif end - MMIO_CSR_DATA_SIZE: begin - csr_data_size <= $bits(csr_data_size)'(cp2af_sRxPort.c0.data); + MMIO_DATA_SIZE: begin + cmd_data_size <= $bits(cmd_data_size)'(cp2af_sRxPort.c0.data); `ifdef DBG_PRINT_OPAE - $display("%t: CSR_DATA_SIZE: %0d", $time, $bits(csr_data_size)'(cp2af_sRxPort.c0.data)); + $display("%t: MMIO_DATA_SIZE: %0d", $time, $bits(cmd_data_size)'(cp2af_sRxPort.c0.data)); `endif end - MMIO_CSR_CMD: begin - csr_cmd <= $bits(csr_cmd)'(cp2af_sRxPort.c0.data); + MMIO_CMD_TYPE: begin + cmd_type <= $bits(cmd_type)'(cp2af_sRxPort.c0.data); `ifdef DBG_PRINT_OPAE - $display("%t: CSR_CMD: %0d", $time, $bits(csr_cmd)'(cp2af_sRxPort.c0.data)); + $display("%t: MMIO_CMD_TYPE: %0d", $time, $bits(cmd_type)'(cp2af_sRxPort.c0.data)); `endif end `ifdef SCOPE - MMIO_CSR_SCOPE_CMD: begin + MMIO_SCOPE_WRITE: begin `ifdef DBG_PRINT_OPAE - $display("%t: CSR_SCOPE_CMD: %0h", $time, 64'(cp2af_sRxPort.c0.data)); + $display("%t: MMIO_SCOPE_WRITE: %0h", $time, 64'(cp2af_sRxPort.c0.data)); `endif end `endif - default: begin - // user-defined CSRs - //if (mmio_hdr.addres >= MMIO_CSR_USER) begin - // write Vortex CRS - //end - end + MMIO_CSR_CORE: begin + cmd_csr_core <= $bits(cmd_csr_core)'(cp2af_sRxPort.c0.data); + `ifdef DBG_PRINT_OPAE + $display("%t: MMIO_CSR_CORE: %0h", $time, $bits(cmd_csr_core)'(cp2af_sRxPort.c0.data)); + `endif + end + MMIO_CSR_ADDR: begin + cmd_csr_addr <= $bits(cmd_csr_addr)'(cp2af_sRxPort.c0.data); + `ifdef DBG_PRINT_OPAE + $display("%t: MMIO_CSR_ADDR: %0h", $time, $bits(cmd_csr_addr)'(cp2af_sRxPort.c0.data)); + `endif + end + MMIO_CSR_DATA: begin + cmd_csr_wdata <= $bits(cmd_csr_wdata)'(cp2af_sRxPort.c0.data); + `ifdef DBG_PRINT_OPAE + $display("%t: MMIO_CSR_DATA: %0h", $time, $bits(cmd_csr_wdata)'(cp2af_sRxPort.c0.data)); + `endif + end endcase end @@ -243,22 +280,28 @@ begin AFU_ID_H: mmio_tx.data <= afu_id[127:64]; // afu id hi 16'h0006: mmio_tx.data <= 64'h0; // next AFU 16'h0008: mmio_tx.data <= 64'h0; // reserved - MMIO_CSR_STATUS: begin + MMIO_STATUS: begin `ifdef DBG_PRINT_OPAE if (state != state_t'(mmio_tx.data)) begin - $display("%t: STATUS: state=%0d", $time, state); + $display("%t: MMIO_STATUS: state=%0d", $time, state); end `endif mmio_tx.data <= 64'(state); end `ifdef SCOPE - MMIO_CSR_SCOPE_DATA: begin - mmio_tx.data <= csr_scope_data; + MMIO_SCOPE_READ: begin + mmio_tx.data <= cmd_scope_rdata; `ifdef DBG_PRINT_OPAE - $display("%t: SCOPE: data=%0h", $time, csr_scope_data); + $display("%t: MMIO_SCOPE_READ: data=%0h", $time, cmd_scope_rdata); `endif end `endif + MMIO_CSR_READ: begin + mmio_tx.data <= 64'(cmd_csr_rdata); + `ifdef DBG_PRINT_OPAE + $display("%t: MMIO_CSR_READ: data=%0h", $time, cmd_csr_rdata); + `endif + end default: mmio_tx.data <= 64'h0; endcase mmio_tx.mmioRdValid <= 1; // post response @@ -271,6 +314,7 @@ end logic cmd_read_done; logic cmd_write_done; logic cmd_clflush_done; +logic cmd_csr_done; logic cmd_run_done; always_ff @(posedge clk) @@ -285,32 +329,44 @@ begin case (state) STATE_IDLE: begin - case (csr_cmd) - CMD_TYPE_READ: begin + case (cmd_type) + CMD_MEM_READ: begin `ifdef DBG_PRINT_OPAE - $display("%t: STATE READ: ia=%0h da=%0h sz=%0d", $time, csr_io_addr, csr_mem_addr, csr_data_size); + $display("%t: STATE READ: ia=%0h addr=%0h size=%0d", $time, cmd_io_addr, cmd_mem_addr, cmd_data_size); `endif state <= STATE_READ; end - CMD_TYPE_WRITE: begin + CMD_MEM_WRITE: begin `ifdef DBG_PRINT_OPAE - $display("%t: STATE WRITE: ia=%0h da=%0h sz=%0d", $time, csr_io_addr, csr_mem_addr, csr_data_size); + $display("%t: STATE WRITE: ia=%0h addr=%0h size=%0d", $time, cmd_io_addr, cmd_mem_addr, cmd_data_size); `endif state <= STATE_WRITE; end - CMD_TYPE_RUN: begin + CMD_RUN: begin `ifdef DBG_PRINT_OPAE $display("%t: STATE START", $time); `endif vx_reset <= 1; state <= STATE_START; end - CMD_TYPE_CLFLUSH: begin + CMD_CLFLUSH: begin `ifdef DBG_PRINT_OPAE - $display("%t: STATE CFLUSH: da=%0h sz=%0d", $time, csr_mem_addr, csr_data_size); + $display("%t: STATE CFLUSH: addr=%0h size=%0d", $time, cmd_mem_addr, cmd_data_size); `endif state <= STATE_CLFLUSH; end + CMD_CSR_READ: begin + `ifdef DBG_PRINT_OPAE + $display("%t: STATE CSR_READ: addr=%0h", $time, cmd_csr_addr); + `endif + state <= STATE_CSR_READ; + end + CMD_CSR_WRITE: begin + `ifdef DBG_PRINT_OPAE + $display("%t: STATE CSR_WRITE: addr=%0h data=%0d", $time, cmd_csr_addr, cmd_csr_wdata); + `endif + state <= STATE_CSR_WRITE; + end default: begin state <= state; end @@ -345,6 +401,18 @@ begin end end + STATE_CSR_READ: begin + if (cmd_csr_done) begin + state <= STATE_IDLE; + end + end + + STATE_CSR_WRITE: begin + if (cmd_csr_done) begin + state <= STATE_IDLE; + end + end + default: begin state <= state; end @@ -385,7 +453,7 @@ assign cci_dram_rd_req_enable = (state == STATE_READ) assign cci_dram_wr_req_enable = (state == STATE_WRITE) && !cci_rdq_empty - && (cci_dram_wr_req_ctr < csr_data_size); + && (cci_dram_wr_req_ctr < cmd_data_size); assign vx_dram_req_enable = vortex_enabled && (avs_pending_reads < AVS_RD_QUEUE_SIZE); assign vx_dram_rd_req_enable = vx_dram_req_enable && vx_dram_req_valid && !vx_dram_req_rw; @@ -414,19 +482,19 @@ end always_comb begin case (state) - CMD_TYPE_READ: avs_address = cci_dram_rd_req_addr; - CMD_TYPE_WRITE: avs_address = cci_dram_wr_req_addr + ((DRAM_ADDR_WIDTH)'(t_cci_rdq_tag'(cci_rdq_dout))); + CMD_MEM_READ: avs_address = cci_dram_rd_req_addr; + CMD_MEM_WRITE: avs_address = cci_dram_wr_req_addr + ((DRAM_ADDR_WIDTH)'(t_cci_rdq_tag'(cci_rdq_dout))); default: avs_address = vx_dram_req_addr[`VX_DRAM_ADDR_WIDTH-1:`VX_DRAM_ADDR_WIDTH-DRAM_ADDR_WIDTH]; endcase case (state) - CMD_TYPE_READ: avs_byteenable = 64'hffffffffffffffff; - CMD_TYPE_WRITE: avs_byteenable = 64'hffffffffffffffff; + CMD_MEM_READ: avs_byteenable = 64'hffffffffffffffff; + CMD_MEM_WRITE: avs_byteenable = 64'hffffffffffffffff; default: avs_byteenable = vx_dram_req_byteen_; endcase case (state) - CMD_TYPE_WRITE: avs_writedata = cci_rdq_dout[$bits(t_ccip_clData) + $bits(t_cci_rdq_tag)-1:$bits(t_cci_rdq_tag)]; + CMD_MEM_WRITE: avs_writedata = cci_rdq_dout[$bits(t_ccip_clData) + $bits(t_cci_rdq_tag)-1:$bits(t_cci_rdq_tag)]; default: avs_writedata = (DRAM_LINE_WIDTH)'(vx_dram_req_data) << vx_dram_req_offset; endcase end @@ -434,7 +502,7 @@ end assign avs_read = cci_dram_rd_req_enable || vx_dram_rd_req_enable; assign avs_write = cci_dram_wr_req_enable || vx_dram_wr_req_enable; -assign cmd_write_done = (cci_dram_wr_req_ctr >= csr_data_size); +assign cmd_write_done = (cci_dram_wr_req_ctr >= cmd_data_size); always_ff @(posedge clk) begin @@ -451,12 +519,12 @@ begin else begin if (state == STATE_IDLE) begin - if (CMD_TYPE_READ == csr_cmd) begin - cci_dram_rd_req_addr <= csr_mem_addr; - cci_dram_rd_req_ctr <= csr_data_size; + if (CMD_MEM_READ == cmd_type) begin + cci_dram_rd_req_addr <= cmd_mem_addr; + cci_dram_rd_req_ctr <= cmd_data_size; end - else if (CMD_TYPE_WRITE == csr_cmd) begin - cci_dram_wr_req_addr <= csr_mem_addr; + else if (CMD_MEM_WRITE == cmd_type) begin + cci_dram_wr_req_addr <= cmd_mem_addr; cci_dram_wr_req_ctr <= 0; end end @@ -598,17 +666,17 @@ begin else begin if ((STATE_IDLE == state) - && (CMD_TYPE_WRITE == csr_cmd)) begin - cci_rd_req_addr <= csr_io_addr; + && (CMD_MEM_WRITE == cmd_type)) begin + cci_rd_req_addr <= cmd_io_addr; cci_rd_req_ctr <= 0; cci_rd_rsp_ctr <= 0; cci_pending_reads <= 0; - cci_rd_req_enable <= (csr_data_size != 0); + cci_rd_req_enable <= (cmd_data_size != 0); cci_rd_req_wait <= 0; end cci_rd_req_enable <= (STATE_WRITE == state) - && (cci_rd_req_ctr_next < csr_data_size) + && (cci_rd_req_ctr_next < cmd_data_size) && (cci_pending_reads_next < CCI_RD_QUEUE_SIZE); if (cci_rd_req_fire) begin @@ -618,7 +686,7 @@ begin cci_rd_req_wait <= 1; // end current request batch end `ifdef DBG_PRINT_OPAE - $display("%t: CCI Rd Req: addr=%0h, rem=%0d, pending=%0d", $time, cci_rd_req_addr, (csr_data_size - cci_rd_req_ctr_next), cci_pending_reads_next); + $display("%t: CCI Rd Req: addr=%0h, rem=%0d, pending=%0d", $time, cci_rd_req_addr, (cmd_data_size - cci_rd_req_ctr_next), cci_pending_reads_next); `endif end @@ -695,9 +763,9 @@ begin else begin if ((STATE_IDLE == state) - && (CMD_TYPE_READ == csr_cmd)) begin - cci_wr_req_addr <= csr_io_addr; - cci_wr_req_ctr <= csr_data_size; + && (CMD_MEM_READ == cmd_type)) begin + cci_wr_req_addr <= cmd_io_addr; + cci_wr_req_ctr <= cmd_data_size; cci_pending_writes <= 0; end @@ -733,11 +801,11 @@ logic [`VX_DRAM_ADDR_WIDTH-1:0] snp_rsp_ctr, snp_rsp_ctr_next; logic vx_snp_req_fire, vx_snp_rsp_fire; if (`VX_DRAM_LINE_WIDTH != DRAM_LINE_WIDTH) begin - assign snp_req_baseaddr = {csr_mem_addr, (`VX_DRAM_ADDR_WIDTH - DRAM_ADDR_WIDTH)'(0)}; - assign snp_req_size = {csr_data_size, (`VX_DRAM_ADDR_WIDTH - DRAM_ADDR_WIDTH)'(0)}; + assign snp_req_baseaddr = {cmd_mem_addr, (`VX_DRAM_ADDR_WIDTH - DRAM_ADDR_WIDTH)'(0)}; + assign snp_req_size = {cmd_data_size, (`VX_DRAM_ADDR_WIDTH - DRAM_ADDR_WIDTH)'(0)}; end else begin - assign snp_req_baseaddr = csr_mem_addr; - assign snp_req_size = csr_data_size; + assign snp_req_baseaddr = cmd_mem_addr; + assign snp_req_size = cmd_data_size; end assign vx_snp_req_fire = vx_snp_req_valid && vx_snp_req_ready; @@ -761,7 +829,7 @@ begin else begin if ((STATE_IDLE == state) - && (CMD_TYPE_CLFLUSH == csr_cmd)) begin + && (CMD_CLFLUSH == cmd_type)) begin vx_snp_req_addr <= snp_req_baseaddr; vx_snp_req_tag <= 0; snp_req_ctr <= 0; @@ -802,6 +870,42 @@ begin end end +// CSRs/////////////////////////////////////////////////////////////////////// + +logic csr_io_req_sent; + +assign vx_csr_io_req_valid = !csr_io_req_sent + && ((STATE_CSR_READ == state || STATE_CSR_WRITE == state)); +assign vx_csr_io_req_coreid = cmd_csr_core; +assign vx_csr_io_req_rw = (STATE_CSR_WRITE == state); +assign vx_csr_io_req_addr = cmd_csr_addr; +assign vx_csr_io_req_data = cmd_csr_wdata; + +assign vx_csr_io_rsp_ready = 1; + +assign cmd_csr_done = (STATE_CSR_WRITE == state) ? vx_csr_io_req_ready : vx_csr_io_rsp_valid; + +always_ff @(posedge clk) +begin + if (SoftReset) begin + csr_io_req_sent <= 0; + cmd_csr_rdata <= 0; + end + else begin + if (vx_csr_io_req_valid && vx_csr_io_req_ready) begin + csr_io_req_sent <= 1; + end + if (cmd_csr_done) begin + csr_io_req_sent <= 0; + end + if ((STATE_CSR_READ == state) + && vx_csr_io_rsp_ready + && vx_csr_io_rsp_valid) begin + cmd_csr_rdata <= vx_csr_io_rsp_data; + end + end +end + // Vortex ///////////////////////////////////////////////////////////////////// assign cmd_run_done = !vx_busy; @@ -815,7 +919,7 @@ Vortex #() vortex ( `SCOPE_SIGNALS_BE_BIND .clk (clk), - .reset (vx_reset), + .reset (SoftReset | vx_reset), // DRAM request .dram_req_valid (vx_dram_req_valid), @@ -858,6 +962,19 @@ Vortex #() vortex ( .io_rsp_data (0), .io_rsp_tag (0), `UNUSED_PIN (io_rsp_ready), + + // CSR I/O Request + .csr_io_req_valid (vx_csr_io_req_valid), + .csr_io_req_coreid(vx_csr_io_req_coreid), + .csr_io_req_addr (vx_csr_io_req_addr), + .csr_io_req_rw (vx_csr_io_req_rw), + .csr_io_req_data (vx_csr_io_req_data), + .csr_io_req_ready (vx_csr_io_req_ready), + + // CSR I/O Response + .csr_io_rsp_valid (vx_csr_io_rsp_valid), + .csr_io_rsp_data (vx_csr_io_rsp_data), + .csr_io_rsp_ready (vx_csr_io_rsp_ready), // status .busy (vx_busy), @@ -944,10 +1061,10 @@ VX_scope #( .stop (0), .changed (scope_data_in_ste[1]), .data_in (scope_data_in_ste[SCOPE_DATAW+1:2]), - .bus_in (csr_scope_cmd), - .bus_out (csr_scope_data), - .bus_read (csr_scope_read), - .bus_write(csr_scope_write) + .bus_in (cmd_scope_wdata), + .bus_out (cmd_scope_rdata), + .bus_read (cmd_scope_read), + .bus_write(cmd_scope_write) ); `endif diff --git a/hw/opae/vortex_afu.vh b/hw/opae/vortex_afu.vh index 8d437c38..910ea3af 100644 --- a/hw/opae/vortex_afu.vh +++ b/hw/opae/vortex_afu.vh @@ -12,17 +12,25 @@ `define AFU_ACCEL_NAME "vortex_afu" `define AFU_ACCEL_UUID 128'h35f9452b_25c2_434c_93d5_6f8c60db361c -`define AFU_IMAGE_CMD_TYPE_CLFLUSH 4 -`define AFU_IMAGE_CMD_TYPE_READ 1 -`define AFU_IMAGE_CMD_TYPE_RUN 3 -`define AFU_IMAGE_CMD_TYPE_WRITE 2 -`define AFU_IMAGE_MMIO_CSR_CMD 10 -`define AFU_IMAGE_MMIO_CSR_DATA_SIZE 12 -`define AFU_IMAGE_MMIO_CSR_IO_ADDR 14 -`define AFU_IMAGE_MMIO_CSR_MEM_ADDR 16 -`define AFU_IMAGE_MMIO_CSR_STATUS 18 -`define AFU_IMAGE_MMIO_CSR_SCOPE_CMD 20 -`define AFU_IMAGE_MMIO_CSR_SCOPE_DATA 22 + +`define AFU_IMAGE_CMD_CLFLUSH 4 +`define AFU_IMAGE_CMD_CSR_READ 5 +`define AFU_IMAGE_CMD_CSR_WRITE 6 +`define AFU_IMAGE_CMD_MEM_READ 1 +`define AFU_IMAGE_CMD_MEM_WRITE 2 +`define AFU_IMAGE_CMD_RUN 3 +`define AFU_IMAGE_MMIO_CMD_TYPE 10 +`define AFU_IMAGE_MMIO_CSR_CORE 24 +`define AFU_IMAGE_MMIO_CSR_ADDR 26 +`define AFU_IMAGE_MMIO_CSR_DATA 28 +`define AFU_IMAGE_MMIO_CSR_READ 30 +`define AFU_IMAGE_MMIO_DATA_SIZE 16 +`define AFU_IMAGE_MMIO_IO_ADDR 12 +`define AFU_IMAGE_MMIO_MEM_ADDR 14 +`define AFU_IMAGE_MMIO_SCOPE_READ 20 +`define AFU_IMAGE_MMIO_SCOPE_WRITE 22 +`define AFU_IMAGE_MMIO_STATUS 18 + `define AFU_IMAGE_POWER 0 `define AFU_TOP_IFC "ccip_std_afu_avalon_mm" diff --git a/hw/rtl/VX_alu_unit.v b/hw/rtl/VX_alu_unit.v index ccc9b1ab..d1b30016 100644 --- a/hw/rtl/VX_alu_unit.v +++ b/hw/rtl/VX_alu_unit.v @@ -13,9 +13,6 @@ module VX_alu_unit ( output reg [31:0] alu_result, output reg alu_stall ); - localparam DIV_PIPELINE_LEN = 18; - localparam MUL_PIPELINE_LEN = 1; - wire[31:0] div_result_unsigned; wire[31:0] div_result_signed; @@ -28,7 +25,7 @@ module VX_alu_unit ( wire[31:0] alu_in2 = (src_rs2 == `RS2_IMMED) ? itype_immed : src_b; wire[31:0] upper_immed_s = {upper_immed, {12{1'b0}}}; - + reg [7:0] inst_delay; reg [7:0] curr_inst_delay; @@ -37,11 +34,11 @@ module VX_alu_unit ( `ALU_DIV, `ALU_DIVU, `ALU_REM, - `ALU_REMU: inst_delay = DIV_PIPELINE_LEN; + `ALU_REMU: inst_delay = `DIV_LATENCY; `ALU_MUL, `ALU_MULH, `ALU_MULHSU, - `ALU_MULHU: inst_delay = MUL_PIPELINE_LEN; + `ALU_MULHU: inst_delay = `MUL_LATENCY; default: inst_delay = 0; endcase end @@ -73,7 +70,6 @@ module VX_alu_unit ( `ALU_SUBU: alu_result = (alu_in1 >= alu_in2) ? 32'h0 : 32'hffffffff; `ALU_LUI: alu_result = upper_immed_s; `ALU_AUIPC: alu_result = $signed(curr_PC) + $signed(upper_immed_s); - // TODO: profitable to roll these exceptional cases into inst_delay_tmp to avoid pipeline when possible? `ALU_MUL: alu_result = mul_result[31:0]; `ALU_MULH: alu_result = mul_result[63:32]; `ALU_MULHSU: alu_result = mul_result[63:32]; @@ -83,7 +79,7 @@ module VX_alu_unit ( `ALU_REM: alu_result = (alu_in2 == 0) ? alu_in1 : rem_result_signed; `ALU_REMU: alu_result = (alu_in2 == 0) ? alu_in1 : rem_result_unsigned; default: alu_result = 32'h0; - endcase // alu_op + endcase end VX_divide #( @@ -91,7 +87,7 @@ module VX_alu_unit ( .WIDTHD(32), .NSIGNED(0), .DSIGNED(0), - .PIPELINE(DIV_PIPELINE_LEN) + .PIPELINE(`DIV_LATENCY) ) udiv ( .clk(clk), .reset(reset), @@ -106,7 +102,7 @@ module VX_alu_unit ( .WIDTHD(32), .NSIGNED(1), .DSIGNED(1), - .PIPELINE(DIV_PIPELINE_LEN) + .PIPELINE(`DIV_LATENCY) ) sdiv ( .clk(clk), .reset(reset), @@ -124,7 +120,7 @@ module VX_alu_unit ( .WIDTHB(33), .WIDTHP(64), .SIGNED(1), - .PIPELINE(MUL_PIPELINE_LEN) + .PIPELINE(`MUL_LATENCY) ) multiplier ( .clk(clk), .reset(reset), diff --git a/hw/rtl/VX_back_end.v b/hw/rtl/VX_back_end.v index 34990009..3da014ce 100644 --- a/hw/rtl/VX_back_end.v +++ b/hw/rtl/VX_back_end.v @@ -9,6 +9,9 @@ module VX_back_end #( input wire clk, input wire reset, + VX_csr_io_req_if csr_io_req_if, + VX_csr_io_rsp_if csr_io_rsp_if, + input wire schedule_delay, VX_cache_core_req_if dcache_req_if, @@ -31,6 +34,7 @@ module VX_back_end #( wire no_slot_mem; wire no_slot_exec; + // LSU input + output VX_lsu_req_if lsu_req_if(); VX_wb_if mem_wb_if(); @@ -63,7 +67,7 @@ module VX_back_end #( // End new .memory_delay (mem_delay), .exec_delay (exec_delay), - .gpr_stage_delay (gpr_stage_delay) + .delay (gpr_stage_delay) ); assign ebreak = exec_unit_req_if.is_etype && (| exec_unit_req_if.valid); @@ -76,7 +80,7 @@ module VX_back_end #( .clk (clk), .reset (reset), .lsu_req_if (lsu_req_if), - .mem_wb_if_p1 (mem_wb_if), + .mem_wb_if (mem_wb_if), .dcache_req_if (dcache_req_if), .dcache_rsp_if (dcache_rsp_if), .delay (mem_delay), @@ -99,15 +103,34 @@ module VX_back_end #( .warp_ctl_if (warp_ctl_if) ); + VX_csr_req_if issued_csr_req_if(); + + VX_wb_if csr_pipe_rsp_if(); + + VX_csr_arb csr_arb ( + .clk (clk), + .reset (reset), + + .csr_pipe_stall (stall_gpr_csr), + + .csr_core_req_if (csr_req_if), + .csr_io_req_if (csr_io_req_if), + .issued_csr_req_if(issued_csr_req_if), + + .csr_pipe_rsp_if (csr_pipe_rsp_if), + .csr_wb_if (csr_wb_if), + .csr_io_rsp_if (csr_io_rsp_if) + ); + VX_csr_pipe #( .CORE_ID(CORE_ID) ) csr_pipe ( .clk (clk), .reset (reset), .no_slot_csr (no_slot_csr), - .csr_req_if (csr_req_if), + .csr_req_if (issued_csr_req_if), .writeback_if (writeback_if), - .csr_wb_if (csr_wb_if), + .csr_wb_if (csr_pipe_rsp_if), .stall_gpr_csr (stall_gpr_csr) ); diff --git a/hw/rtl/VX_cluster.v b/hw/rtl/VX_cluster.v index d9539660..2633bf7d 100644 --- a/hw/rtl/VX_cluster.v +++ b/hw/rtl/VX_cluster.v @@ -56,6 +56,19 @@ module VX_cluster #( input wire [`L2CORE_TAG_WIDTH-1:0] io_rsp_tag, output wire io_rsp_ready, + // CSR I/O Request + input wire csr_io_req_valid, + input wire [`NC_BITS-1:0] csr_io_req_coreid, + input wire [11:0] csr_io_req_addr, + input wire csr_io_req_rw, + input wire [31:0] csr_io_req_data, + output wire csr_io_req_ready, + + // CSR I/O Response + output wire csr_io_rsp_valid, + output wire [31:0] csr_io_rsp_data, + input wire csr_io_rsp_ready, + // Status output wire busy, output wire ebreak @@ -109,10 +122,21 @@ module VX_cluster #( wire [`NUM_CORES-1:0][31:0] per_core_io_rsp_data; wire [`NUM_CORES-1:0] per_core_io_rsp_ready; + wire [`NUM_CORES-1:0] per_core_csr_io_req_valid; + wire [`NUM_CORES-1:0][11:0] per_core_csr_io_req_addr; + wire [`NUM_CORES-1:0] per_core_csr_io_req_rw; + wire [`NUM_CORES-1:0][31:0] per_core_csr_io_req_data; + wire [`NUM_CORES-1:0] per_core_csr_io_req_ready; + + wire [`NUM_CORES-1:0] per_core_csr_io_rsp_valid; + wire [`NUM_CORES-1:0][31:0] per_core_csr_io_rsp_data; + wire [`NUM_CORES-1:0] per_core_csr_io_rsp_ready; + wire [`NUM_CORES-1:0] per_core_busy; wire [`NUM_CORES-1:0] per_core_ebreak; genvar i; + for (i = 0; i < `NUM_CORES; i++) begin VX_core #( .CORE_ID(i + (CLUSTER_ID * `NUM_CORES)) @@ -174,6 +198,16 @@ module VX_cluster #( .io_rsp_tag (per_core_io_rsp_tag [i]), .io_rsp_ready (per_core_io_rsp_ready [i]), + .csr_io_req_valid (per_core_csr_io_req_valid [i]), + .csr_io_req_rw (per_core_csr_io_req_rw [i]), + .csr_io_req_addr (per_core_csr_io_req_addr [i]), + .csr_io_req_data (per_core_csr_io_req_data [i]), + .csr_io_req_ready (per_core_csr_io_req_ready [i]), + + .csr_io_rsp_valid (per_core_csr_io_rsp_valid [i]), + .csr_io_rsp_data (per_core_csr_io_rsp_data [i]), + .csr_io_rsp_ready (per_core_csr_io_rsp_ready [i]), + .busy (per_core_busy [i]), .ebreak (per_core_ebreak [i]) ); @@ -217,7 +251,40 @@ module VX_cluster #( .out_mem_rsp_tag (io_rsp_tag), .out_mem_rsp_data (io_rsp_data), .out_mem_rsp_ready (io_rsp_ready) - ); + ); + + VX_csr_io_arb #( + .NUM_REQUESTS (`NUM_CORES) + ) csr_io_arb ( + .clk (clk), + .reset (reset), + + .request_id (csr_io_req_coreid), + + // input requests + .in_csr_io_req_valid (csr_io_req_valid), + .in_csr_io_req_addr (csr_io_req_addr), + .in_csr_io_req_rw (csr_io_req_rw), + .in_csr_io_req_data (csr_io_req_data), + .in_csr_io_req_ready (csr_io_req_ready), + + // input responses + .in_csr_io_rsp_valid (per_core_csr_io_rsp_valid), + .in_csr_io_rsp_data (per_core_csr_io_rsp_data), + .in_csr_io_rsp_ready (per_core_csr_io_rsp_ready), + + // output request + .out_csr_io_req_valid (per_core_csr_io_req_valid), + .out_csr_io_req_addr (per_core_csr_io_req_addr), + .out_csr_io_req_rw (per_core_csr_io_req_rw), + .out_csr_io_req_data (per_core_csr_io_req_data), + .out_csr_io_req_ready (per_core_csr_io_req_ready), + + // output response + .out_csr_io_rsp_valid (csr_io_rsp_valid), + .out_csr_io_rsp_data (csr_io_rsp_data), + .out_csr_io_rsp_ready (csr_io_rsp_ready) + ); assign busy = (| per_core_busy); assign ebreak = (& per_core_ebreak); @@ -537,4 +604,4 @@ module VX_cluster #( end -endmodule \ No newline at end of file +endmodule diff --git a/hw/rtl/VX_config.vh b/hw/rtl/VX_config.vh index 4f6377a0..6a5f7386 100644 --- a/hw/rtl/VX_config.vh +++ b/hw/rtl/VX_config.vh @@ -59,21 +59,33 @@ `define L3_ENABLE (`NUM_CLUSTERS > 1) `endif -`define CSR_LTID 12'h020 -`define CSR_LWID 12'h021 -`define CSR_GTID 12'hF14 // reserved Hardware Thread ID (mhartid) -`define CSR_GWID 12'h023 -`define CSR_GCID 12'h024 -`define CSR_NT 12'h025 -`define CSR_NW 12'h026 -`define CSR_NC 12'h027 +// Configuration Values ======================================================= -`define CSR_CYCLL 12'hC00 -`define CSR_CYCLH 12'hC80 -`define CSR_INSTL 12'hC02 -`define CSR_INSTH 12'hC82 +`define VENDOR_ID 0 +`define ARCHITECTURE_ID 0 +`define IMPLEMENTATION_ID 0 -// ========================= Dcache Configurable Knobs ======================== +// CSR Addresses ============================================================== + +`define CSR_VEND_ID 12'hF11 +`define CSR_ARCH_ID 12'hF12 +`define CSR_IMPL_ID 12'hF13 +`define CSR_GTID 12'hF14 + +`define CSR_LTID 12'h020 +`define CSR_LWID 12'h021 +`define CSR_GWID 12'h023 +`define CSR_GCID 12'h024 +`define CSR_NT 12'h025 +`define CSR_NW 12'h026 +`define CSR_NC 12'h027 + +`define CSR_CYCLE_L 12'hC00 +`define CSR_CYCLE_H 12'hC80 +`define CSR_INSTR_L 12'hC02 +`define CSR_INSTR_H 12'hC82 + +// Dcache Configurable Knobs ================================================== // Size of cache in bytes `ifndef DCACHE_SIZE @@ -144,7 +156,7 @@ `define DPRFQ_STRIDE 0 `endif -// ========================== Icache Configurable Knobs ======================= +// Icache Configurable Knobs ================================================== // Size of cache in bytes `ifndef ICACHE_SIZE @@ -210,7 +222,7 @@ `define IPRFQ_STRIDE 0 `endif -// =========================== SM Configurable Knobs ========================== +// SM Configurable Knobs ====================================================== // Size of cache in bytes `ifndef SCACHE_SIZE @@ -247,7 +259,7 @@ `define SCWBQ_SIZE `SCREQ_SIZE `endif -// ======================== L2cache Configurable Knobs ======================== +// L2cache Configurable Knobs ================================================= // Size of cache in bytes `ifndef L2CACHE_SIZE @@ -318,7 +330,7 @@ `define L2PRFQ_STRIDE 0 `endif -// ======================== L3cache Configurable Knobs ======================== +// L3cache Configurable Knobs ================================================= // Size of cache in bytes `ifndef L3CACHE_SIZE diff --git a/hw/rtl/VX_core.v b/hw/rtl/VX_core.v index 33ae9635..c437c398 100644 --- a/hw/rtl/VX_core.v +++ b/hw/rtl/VX_core.v @@ -70,12 +70,22 @@ module VX_core #( input wire [`DCORE_TAG_WIDTH-1:0] io_rsp_tag, output wire io_rsp_ready, + // CSR I/O request + input wire csr_io_req_valid, + input wire [11:0] csr_io_req_addr, + input wire csr_io_req_rw, + input wire [31:0] csr_io_req_data, + output wire csr_io_req_ready, + + // CSR I/O response + output wire csr_io_rsp_valid, + output wire [31:0] csr_io_rsp_data, + input wire csr_io_rsp_ready, + // Status output wire busy, output wire ebreak ); - // Dcache Interfaces - VX_cache_dram_req_if #( .DRAM_LINE_WIDTH(`DDRAM_LINE_WIDTH), .DRAM_ADDR_WIDTH(`DDRAM_ADDR_WIDTH), @@ -87,18 +97,18 @@ module VX_core #( .DRAM_TAG_WIDTH(`DDRAM_TAG_WIDTH) ) dcache_dram_rsp_if(); - assign D_dram_req_valid = dcache_dram_req_if.dram_req_valid; - assign D_dram_req_rw = dcache_dram_req_if.dram_req_rw; - assign D_dram_req_byteen= dcache_dram_req_if.dram_req_byteen; - assign D_dram_req_addr = dcache_dram_req_if.dram_req_addr; - assign D_dram_req_data = dcache_dram_req_if.dram_req_data; - assign D_dram_req_tag = dcache_dram_req_if.dram_req_tag; - assign dcache_dram_req_if.dram_req_ready = D_dram_req_ready; + assign D_dram_req_valid = dcache_dram_req_if.valid; + assign D_dram_req_rw = dcache_dram_req_if.rw; + assign D_dram_req_byteen= dcache_dram_req_if.byteen; + assign D_dram_req_addr = dcache_dram_req_if.addr; + assign D_dram_req_data = dcache_dram_req_if.data; + assign D_dram_req_tag = dcache_dram_req_if.tag; + assign dcache_dram_req_if.ready = D_dram_req_ready; - assign dcache_dram_rsp_if.dram_rsp_valid = D_dram_rsp_valid; - assign dcache_dram_rsp_if.dram_rsp_data = D_dram_rsp_data; - assign dcache_dram_rsp_if.dram_rsp_tag = D_dram_rsp_tag; - assign D_dram_rsp_ready = dcache_dram_rsp_if.dram_rsp_ready; + assign dcache_dram_rsp_if.valid = D_dram_rsp_valid; + assign dcache_dram_rsp_if.data = D_dram_rsp_data; + assign dcache_dram_rsp_if.tag = D_dram_rsp_tag; + assign D_dram_rsp_ready = dcache_dram_rsp_if.ready; VX_cache_core_req_if #( .NUM_REQUESTS(`DNUM_REQUESTS), @@ -114,18 +124,18 @@ module VX_core #( .CORE_TAG_ID_BITS(`DCORE_TAG_ID_BITS) ) core_dcache_rsp_if(), arb_dcache_rsp_if(), arb_io_rsp_if(); - assign io_req_valid = arb_io_req_if.core_req_valid[0]; - assign io_req_rw = arb_io_req_if.core_req_rw[0]; - assign io_req_byteen = arb_io_req_if.core_req_byteen[0]; - assign io_req_addr = arb_io_req_if.core_req_addr[0]; - assign io_req_data = arb_io_req_if.core_req_data[0]; - assign io_req_tag = arb_io_req_if.core_req_tag[0]; - assign arb_io_req_if.core_req_ready = io_req_ready; + assign io_req_valid = arb_io_req_if.valid[0]; + assign io_req_rw = arb_io_req_if.rw[0]; + assign io_req_byteen = arb_io_req_if.byteen[0]; + assign io_req_addr = arb_io_req_if.addr[0]; + assign io_req_data = arb_io_req_if.data[0]; + assign io_req_tag = arb_io_req_if.tag[0]; + assign arb_io_req_if.ready = io_req_ready; - assign arb_io_rsp_if.core_rsp_valid = {{(`NUM_THREADS-1){1'b0}}, io_rsp_valid}; - assign arb_io_rsp_if.core_rsp_data[0] = io_rsp_data; - assign arb_io_rsp_if.core_rsp_tag = io_rsp_tag; - assign io_rsp_ready = arb_io_rsp_if.core_rsp_ready; + assign arb_io_rsp_if.valid = {{(`NUM_THREADS-1){1'b0}}, io_rsp_valid}; + assign arb_io_rsp_if.data[0] = io_rsp_data; + assign arb_io_rsp_if.tag = io_rsp_tag; + assign io_rsp_ready = arb_io_rsp_if.ready; // Icache interfaces @@ -140,18 +150,18 @@ module VX_core #( .DRAM_TAG_WIDTH(`IDRAM_TAG_WIDTH) ) icache_dram_rsp_if(); - assign I_dram_req_valid = icache_dram_req_if.dram_req_valid; - assign I_dram_req_rw = icache_dram_req_if.dram_req_rw; - assign I_dram_req_byteen= icache_dram_req_if.dram_req_byteen; - assign I_dram_req_addr = icache_dram_req_if.dram_req_addr; - assign I_dram_req_data = icache_dram_req_if.dram_req_data; - assign I_dram_req_tag = icache_dram_req_if.dram_req_tag; - assign icache_dram_req_if.dram_req_ready = I_dram_req_ready; + assign I_dram_req_valid = icache_dram_req_if.valid; + assign I_dram_req_rw = icache_dram_req_if.rw; + assign I_dram_req_byteen= icache_dram_req_if.byteen; + assign I_dram_req_addr = icache_dram_req_if.addr; + assign I_dram_req_data = icache_dram_req_if.data; + assign I_dram_req_tag = icache_dram_req_if.tag; + assign icache_dram_req_if.ready = I_dram_req_ready; - assign icache_dram_rsp_if.dram_rsp_valid = I_dram_rsp_valid; - assign icache_dram_rsp_if.dram_rsp_data = I_dram_rsp_data; - assign icache_dram_rsp_if.dram_rsp_tag = I_dram_rsp_tag; - assign I_dram_rsp_ready = icache_dram_rsp_if.dram_rsp_ready; + assign icache_dram_rsp_if.valid = I_dram_rsp_valid; + assign icache_dram_rsp_if.data = I_dram_rsp_data; + assign icache_dram_rsp_if.tag = I_dram_rsp_tag; + assign I_dram_rsp_ready = icache_dram_rsp_if.ready; VX_cache_core_req_if #( .NUM_REQUESTS(`INUM_REQUESTS), @@ -179,34 +189,46 @@ module VX_core #( .reset(reset), // Dcache core request - .dcache_req_valid (core_dcache_req_if.core_req_valid), - .dcache_req_rw (core_dcache_req_if.core_req_rw), - .dcache_req_byteen (core_dcache_req_if.core_req_byteen), - .dcache_req_addr (core_dcache_req_if.core_req_addr), - .dcache_req_data (core_dcache_req_if.core_req_data), - .dcache_req_tag (core_dcache_req_if.core_req_tag), - .dcache_req_ready (core_dcache_req_if.core_req_ready), + .dcache_req_valid (core_dcache_req_if.valid), + .dcache_req_rw (core_dcache_req_if.rw), + .dcache_req_byteen (core_dcache_req_if.byteen), + .dcache_req_addr (core_dcache_req_if.addr), + .dcache_req_data (core_dcache_req_if.data), + .dcache_req_tag (core_dcache_req_if.tag), + .dcache_req_ready (core_dcache_req_if.ready), // Dcache core reponse - .dcache_rsp_valid (core_dcache_rsp_if.core_rsp_valid), - .dcache_rsp_data (core_dcache_rsp_if.core_rsp_data), - .dcache_rsp_tag (core_dcache_rsp_if.core_rsp_tag), - .dcache_rsp_ready (core_dcache_rsp_if.core_rsp_ready), + .dcache_rsp_valid (core_dcache_rsp_if.valid), + .dcache_rsp_data (core_dcache_rsp_if.data), + .dcache_rsp_tag (core_dcache_rsp_if.tag), + .dcache_rsp_ready (core_dcache_rsp_if.ready), // Dcache core request - .icache_req_valid (core_icache_req_if.core_req_valid), - .icache_req_rw (core_icache_req_if.core_req_rw), - .icache_req_byteen (core_icache_req_if.core_req_byteen), - .icache_req_addr (core_icache_req_if.core_req_addr), - .icache_req_data (core_icache_req_if.core_req_data), - .icache_req_tag (core_icache_req_if.core_req_tag), - .icache_req_ready (core_icache_req_if.core_req_ready), + .icache_req_valid (core_icache_req_if.valid), + .icache_req_rw (core_icache_req_if.rw), + .icache_req_byteen (core_icache_req_if.byteen), + .icache_req_addr (core_icache_req_if.addr), + .icache_req_data (core_icache_req_if.data), + .icache_req_tag (core_icache_req_if.tag), + .icache_req_ready (core_icache_req_if.ready), // Dcache core reponse - .icache_rsp_valid (core_icache_rsp_if.core_rsp_valid), - .icache_rsp_data (core_icache_rsp_if.core_rsp_data), - .icache_rsp_tag (core_icache_rsp_if.core_rsp_tag), - .icache_rsp_ready (core_icache_rsp_if.core_rsp_ready), + .icache_rsp_valid (core_icache_rsp_if.valid), + .icache_rsp_data (core_icache_rsp_if.data), + .icache_rsp_tag (core_icache_rsp_if.tag), + .icache_rsp_ready (core_icache_rsp_if.ready), + + // CSR I/O request + .csr_io_req_valid (csr_io_req_valid), + .csr_io_req_rw (csr_io_req_rw), + .csr_io_req_addr (csr_io_req_addr), + .csr_io_req_data (csr_io_req_data), + .csr_io_req_ready (csr_io_req_ready), + + // CSR I/O response + .csr_io_rsp_valid (csr_io_rsp_valid), + .csr_io_rsp_data (csr_io_rsp_data), + .csr_io_rsp_ready (csr_io_rsp_ready), // Status .busy(busy), @@ -224,15 +246,15 @@ module VX_core #( .SNP_TAG_WIDTH(`DSNP_TAG_WIDTH) ) dcache_snp_rsp_if(); - assign dcache_snp_req_if.snp_req_valid = snp_req_valid; - assign dcache_snp_req_if.snp_req_addr = snp_req_addr; - assign dcache_snp_req_if.snp_req_invalidate = snp_req_invalidate; - assign dcache_snp_req_if.snp_req_tag = snp_req_tag; - assign snp_req_ready = dcache_snp_req_if.snp_req_ready; + assign dcache_snp_req_if.valid = snp_req_valid; + assign dcache_snp_req_if.addr = snp_req_addr; + assign dcache_snp_req_if.invalidate = snp_req_invalidate; + assign dcache_snp_req_if.tag = snp_req_tag; + assign snp_req_ready = dcache_snp_req_if.ready; - assign snp_rsp_valid = dcache_snp_rsp_if.snp_rsp_valid; - assign snp_rsp_tag = dcache_snp_rsp_if.snp_rsp_tag; - assign dcache_snp_rsp_if.snp_rsp_ready = snp_rsp_ready; + assign snp_rsp_valid = dcache_snp_rsp_if.valid; + assign snp_rsp_tag = dcache_snp_rsp_if.tag; + assign dcache_snp_rsp_if.ready = snp_rsp_ready; VX_mem_unit #( .CORE_ID(CORE_ID) @@ -262,8 +284,8 @@ module VX_core #( ); // select io address - wire is_io_addr = ({core_dcache_req_if.core_req_addr[0], 2'b0} >= `IO_BUS_BASE_ADDR); - wire io_select = (| core_dcache_req_if.core_req_valid) ? is_io_addr : 0; + wire is_io_addr = ({core_dcache_req_if.addr[0], 2'b0} >= `IO_BUS_BASE_ADDR); + wire io_select = (| core_dcache_req_if.valid) ? is_io_addr : 0; VX_dcache_arb dcache_io_arb ( .req_select (io_select), diff --git a/hw/rtl/VX_csr_arb.v b/hw/rtl/VX_csr_arb.v new file mode 100644 index 00000000..58327ee3 --- /dev/null +++ b/hw/rtl/VX_csr_arb.v @@ -0,0 +1,51 @@ +`include "VX_define.vh" + +module VX_csr_arb ( + input wire clk, + input wire reset, + + input wire csr_pipe_stall, + + VX_csr_req_if csr_core_req_if, + VX_csr_io_req_if csr_io_req_if, + VX_csr_req_if issued_csr_req_if, + + VX_wb_if csr_pipe_rsp_if, + VX_wb_if csr_wb_if, + VX_csr_io_rsp_if csr_io_rsp_if +); + + `UNUSED_VAR (clk) + `UNUSED_VAR (reset) + + wire pick_core = (| csr_core_req_if.valid); + + // Mux between core and io + assign issued_csr_req_if.valid = pick_core ? csr_core_req_if.valid : {`NUM_THREADS{csr_io_req_if.valid}}; + assign issued_csr_req_if.is_csr = pick_core ? csr_core_req_if.is_csr : 1'b1; + assign issued_csr_req_if.alu_op = pick_core ? csr_core_req_if.alu_op : (csr_io_req_if.rw ? `ALU_CSR_RW : `ALU_CSR_RS); + assign issued_csr_req_if.csr_addr = pick_core ? csr_core_req_if.csr_addr : csr_io_req_if.addr; + assign issued_csr_req_if.csr_immed = pick_core ? csr_core_req_if.csr_immed : 0; + assign issued_csr_req_if.csr_mask = pick_core ? csr_core_req_if.csr_mask : (csr_io_req_if.rw ? csr_io_req_if.data : 32'b0); + assign issued_csr_req_if.is_io = !pick_core; + assign issued_csr_req_if.warp_num = csr_core_req_if.warp_num; + assign issued_csr_req_if.rd = csr_core_req_if.rd; + assign issued_csr_req_if.wb = csr_core_req_if.wb; + + assign csr_io_req_if.ready = !(csr_pipe_stall || pick_core); + + // Core Writeback + assign csr_wb_if.valid = csr_pipe_rsp_if.valid & {`NUM_THREADS{~csr_pipe_rsp_if.is_io}}; + assign csr_wb_if.data = csr_pipe_rsp_if.data; + assign csr_wb_if.warp_num = csr_pipe_rsp_if.warp_num; + assign csr_wb_if.rd = csr_pipe_rsp_if.rd; + assign csr_wb_if.wb = csr_pipe_rsp_if.wb; + assign csr_wb_if.curr_PC = csr_pipe_rsp_if.curr_PC; + + // CSR I/O response + assign csr_io_rsp_if.valid = csr_pipe_rsp_if.valid[0] & csr_pipe_rsp_if.is_io; + assign csr_io_rsp_if.data = csr_pipe_rsp_if.data[0]; + wire x = csr_io_rsp_if.ready; + `UNUSED_VAR(x) + +endmodule diff --git a/hw/rtl/VX_csr_data.v b/hw/rtl/VX_csr_data.v index b8144358..7488129e 100644 --- a/hw/rtl/VX_csr_data.v +++ b/hw/rtl/VX_csr_data.v @@ -43,18 +43,21 @@ module VX_csr_data #( always @(*) begin case (read_addr) - `CSR_LWID : read_data = 32'(warp_num); - `CSR_GTID , - `CSR_GWID : read_data = CORE_ID * `NUM_WARPS + 32'(warp_num); - `CSR_GCID : read_data = CORE_ID; - `CSR_NT : read_data = `NUM_THREADS; - `CSR_NW : read_data = `NUM_WARPS; - `CSR_NC : read_data = `NUM_CORES * `NUM_CLUSTERS; - `CSR_CYCLL : read_data = num_cycles[31:0]; - `CSR_CYCLH : read_data = num_cycles[63:32]; - `CSR_INSTL : read_data = num_instrs[31:0]; - `CSR_INSTH : read_data = num_instrs[63:32]; - default: read_data = 32'(csr_table[rd_addr]); + `CSR_LWID : read_data = 32'(warp_num); + `CSR_GTID , + `CSR_GWID : read_data = CORE_ID * `NUM_WARPS + 32'(warp_num); + `CSR_GCID : read_data = CORE_ID; + `CSR_NT : read_data = `NUM_THREADS; + `CSR_NW : read_data = `NUM_WARPS; + `CSR_NC : read_data = `NUM_CORES * `NUM_CLUSTERS; + `CSR_CYCLE_L : read_data = num_cycles[31:0]; + `CSR_CYCLE_H : read_data = num_cycles[63:32]; + `CSR_INSTR_L : read_data = num_instrs[31:0]; + `CSR_INSTR_H : read_data = num_instrs[63:32]; + `CSR_VEND_ID : read_data = `VENDOR_ID; + `CSR_ARCH_ID : read_data = `ARCHITECTURE_ID; + `CSR_IMPL_ID : read_data = `IMPLEMENTATION_ID; + default : read_data = 32'(csr_table[rd_addr]); endcase end diff --git a/hw/rtl/VX_csr_io_arb.v b/hw/rtl/VX_csr_io_arb.v new file mode 100644 index 00000000..bf0d7041 --- /dev/null +++ b/hw/rtl/VX_csr_io_arb.v @@ -0,0 +1,86 @@ +`include "VX_define.vh" + +module VX_csr_io_arb #( + parameter NUM_REQUESTS = 1, + parameter REQS_BITS = `CLOG2(NUM_REQUESTS) +) ( + input wire clk, + input wire reset, + + input wire [REQS_BITS-1:0] request_id, + + // input requests + input wire in_csr_io_req_valid, + input wire [11:0] in_csr_io_req_addr, + input wire in_csr_io_req_rw, + input wire [31:0] in_csr_io_req_data, + output wire in_csr_io_req_ready, + + // input response + input wire [NUM_REQUESTS-1:0] in_csr_io_rsp_valid, + input wire [NUM_REQUESTS-1:0][31:0] in_csr_io_rsp_data, + output wire [NUM_REQUESTS-1:0] in_csr_io_rsp_ready, + + // output request + output wire [NUM_REQUESTS-1:0] out_csr_io_req_valid, + output wire [NUM_REQUESTS-1:0][11:0] out_csr_io_req_addr, + output wire [NUM_REQUESTS-1:0] out_csr_io_req_rw, + output wire [NUM_REQUESTS-1:0][31:0] out_csr_io_req_data, + input wire [NUM_REQUESTS-1:0] out_csr_io_req_ready, + + // output response + output wire out_csr_io_rsp_valid, + output wire [31:0] out_csr_io_rsp_data, + input wire out_csr_io_rsp_ready +); + if (NUM_REQUESTS == 1) begin + + `UNUSED_VAR (clk) + `UNUSED_VAR (reset) + + assign out_csr_io_req_valid = in_csr_io_req_valid; + assign out_csr_io_req_rw = in_csr_io_req_rw; + assign out_csr_io_req_addr = in_csr_io_req_addr; + assign out_csr_io_req_data = in_csr_io_req_data; + assign in_csr_io_req_ready = out_csr_io_req_ready; + + assign out_csr_io_rsp_valid = in_csr_io_rsp_valid; + assign out_csr_io_rsp_data = in_csr_io_rsp_data; + assign in_csr_io_rsp_ready = out_csr_io_rsp_ready; + + end else begin + + genvar i; + + for (i = 0; i < NUM_REQUESTS; i++) begin + assign out_csr_io_req_valid[i] = in_csr_io_req_valid && (request_id == `REQS_BITS'(i)); + assign out_csr_io_req_rw[i] = in_csr_io_req_rw; + assign out_csr_io_req_addr[i] = in_csr_io_req_addr; + assign out_csr_io_req_data[i] = in_csr_io_req_data; + end + + assign in_csr_io_req_ready = out_csr_io_req_ready[request_id]; + + reg [REQS_BITS-1:0] bus_rsp_sel; + + VX_fixed_arbiter #( + .N(NUM_REQUESTS) + ) arbiter ( + .clk (clk), + .reset (reset), + .requests (in_csr_io_rsp_valid), + .grant_index (bus_rsp_sel), + `UNUSED_PIN (grant_valid), + `UNUSED_PIN (grant_onehot) + ); + + assign out_csr_io_rsp_valid = in_csr_io_rsp_valid [bus_rsp_sel]; + assign out_csr_io_rsp_data = in_csr_io_rsp_data [bus_rsp_sel]; + + for (i = 0; i < NUM_REQUESTS; i++) begin + assign in_csr_io_rsp_ready[i] = out_csr_io_rsp_ready && (bus_rsp_sel == `REQS_BITS'(i)); + end + + end + +endmodule \ No newline at end of file diff --git a/hw/rtl/VX_csr_pipe.v b/hw/rtl/VX_csr_pipe.v index c3ad37d3..aa6980ab 100644 --- a/hw/rtl/VX_csr_pipe.v +++ b/hw/rtl/VX_csr_pipe.v @@ -17,7 +17,7 @@ module VX_csr_pipe #( wire[4:0] rd_s2; wire[1:0] wb_s2; wire is_csr_s2; - wire[`CSR_ADDR_SIZE-1:0] csr_address_s2; + wire[`CSR_ADDR_SIZE-1:0] csr_addr_s2; wire[31:0] csr_read_data_s2; wire[31:0] csr_updated_data_s2; @@ -29,17 +29,16 @@ module VX_csr_pipe #( ) csr_data ( .clk (clk), .reset (reset), - .read_addr (csr_req_if.csr_address), + .read_addr (csr_req_if.csr_addr), .read_data (csr_read_data_unqual), .write_enable (is_csr_s2), .write_data (csr_updated_data_s2[`CSR_WIDTH-1:0]), - .write_addr (csr_address_s2), + .write_addr (csr_addr_s2), .warp_num (csr_req_if.warp_num), .wb_valid (| writeback_if.valid) ); - // wire hazard = (csr_address_s2 == csr_req_if.csr_address) & (warp_num_s2 == csr_req_if.warp_num) & |(valid_s2) & is_csr_s2; - wire car_hazard = (csr_address_s2 == csr_req_if.csr_address) & (warp_num_s2 == csr_req_if.warp_num) & |(valid_s2) & is_csr_s2; + wire car_hazard = (csr_addr_s2 == csr_req_if.csr_addr) & (warp_num_s2 == csr_req_if.warp_num) & |(valid_s2) & is_csr_s2; assign csr_read_data = car_hazard ? csr_updated_data_s2 : csr_read_data_unqual; @@ -55,14 +54,14 @@ module VX_csr_pipe #( end VX_generic_register #( - .N(32 + 32 + 12 + 1 + 2 + 5 + (`NW_BITS-1+1) + `NUM_THREADS) + .N(32 + 32 + 12 + 1 + 1 + 2 + 5 + (`NW_BITS-1+1) + `NUM_THREADS) ) csr_reg_s2 ( .clk (clk), .reset(reset), .stall(no_slot_csr), .flush(1'b0), - .in ({csr_req_if.valid, csr_req_if.warp_num, csr_req_if.rd, csr_req_if.wb, csr_req_if.is_csr, csr_req_if.csr_address, csr_read_data , csr_updated_data }), - .out ({valid_s2 , warp_num_s2 , rd_s2 , wb_s2 , is_csr_s2 , csr_address_s2 , csr_read_data_s2, csr_updated_data_s2}) + .in ({csr_req_if.valid, csr_req_if.warp_num, csr_req_if.rd, csr_req_if.wb, csr_req_if.is_csr, csr_req_if.csr_addr, csr_req_if.is_io, csr_read_data , csr_updated_data }), + .out ({valid_s2 , warp_num_s2 , rd_s2 , wb_s2 , is_csr_s2 , csr_addr_s2 , csr_wb_if.is_io , csr_read_data_s2, csr_updated_data_s2}) ); assign csr_wb_if.valid = valid_s2; @@ -72,9 +71,9 @@ module VX_csr_pipe #( genvar i; for (i = 0; i < `NUM_THREADS; i++) begin - assign csr_wb_if.data[i] = (csr_address_s2 == `CSR_LTID) ? i : - (csr_address_s2 == `CSR_GTID) ? (csr_read_data_s2 * `NUM_THREADS + i) : - csr_read_data_s2; + assign csr_wb_if.data[i] = (csr_addr_s2 == `CSR_LTID) ? i : + (csr_addr_s2 == `CSR_GTID) ? (csr_read_data_s2 * `NUM_THREADS + i) : + csr_read_data_s2; end assign stall_gpr_csr = no_slot_csr && csr_req_if.is_csr && (| csr_req_if.valid); diff --git a/hw/rtl/VX_dcache_arb.v b/hw/rtl/VX_dcache_arb.v index 264c91e1..1431be60 100644 --- a/hw/rtl/VX_dcache_arb.v +++ b/hw/rtl/VX_dcache_arb.v @@ -21,28 +21,28 @@ module VX_dcache_arb ( // output response VX_cache_core_rsp_if out_core_rsp_if ); - assign out0_core_req_if.core_req_valid = in_core_req_if.core_req_valid & {`NUM_THREADS{~req_select}}; - assign out0_core_req_if.core_req_rw = in_core_req_if.core_req_rw; - assign out0_core_req_if.core_req_byteen = in_core_req_if.core_req_byteen; - assign out0_core_req_if.core_req_addr = in_core_req_if.core_req_addr; - assign out0_core_req_if.core_req_data = in_core_req_if.core_req_data; - assign out0_core_req_if.core_req_tag = in_core_req_if.core_req_tag; + assign out0_core_req_if.valid = in_core_req_if.valid & {`NUM_THREADS{~req_select}}; + assign out0_core_req_if.rw = in_core_req_if.rw; + assign out0_core_req_if.byteen = in_core_req_if.byteen; + assign out0_core_req_if.addr = in_core_req_if.addr; + assign out0_core_req_if.data = in_core_req_if.data; + assign out0_core_req_if.tag = in_core_req_if.tag; - assign out1_core_req_if.core_req_valid = in_core_req_if.core_req_valid & {`NUM_THREADS{req_select}}; - assign out1_core_req_if.core_req_rw = in_core_req_if.core_req_rw; - assign out1_core_req_if.core_req_byteen = in_core_req_if.core_req_byteen; - assign out1_core_req_if.core_req_addr = in_core_req_if.core_req_addr; - assign out1_core_req_if.core_req_data = in_core_req_if.core_req_data; - assign out1_core_req_if.core_req_tag = in_core_req_if.core_req_tag; + assign out1_core_req_if.valid = in_core_req_if.valid & {`NUM_THREADS{req_select}}; + assign out1_core_req_if.rw = in_core_req_if.rw; + assign out1_core_req_if.byteen = in_core_req_if.byteen; + assign out1_core_req_if.addr = in_core_req_if.addr; + assign out1_core_req_if.data = in_core_req_if.data; + assign out1_core_req_if.tag = in_core_req_if.tag; - assign in_core_req_if.core_req_ready = req_select ? out1_core_req_if.core_req_ready : out0_core_req_if.core_req_ready; + assign in_core_req_if.ready = req_select ? out1_core_req_if.ready : out0_core_req_if.ready; - wire rsp_select0 = (| in0_core_rsp_if.core_rsp_valid); + wire rsp_select0 = (| in0_core_rsp_if.valid); - assign out_core_rsp_if.core_rsp_valid = rsp_select0 ? in0_core_rsp_if.core_rsp_valid : in1_core_rsp_if.core_rsp_valid; - assign out_core_rsp_if.core_rsp_data = rsp_select0 ? in0_core_rsp_if.core_rsp_data : in1_core_rsp_if.core_rsp_data; - assign out_core_rsp_if.core_rsp_tag = rsp_select0 ? in0_core_rsp_if.core_rsp_tag : in1_core_rsp_if.core_rsp_tag; - assign in0_core_rsp_if.core_rsp_ready = out_core_rsp_if.core_rsp_ready && rsp_select0; - assign in1_core_rsp_if.core_rsp_ready = out_core_rsp_if.core_rsp_ready && !rsp_select0; + assign out_core_rsp_if.valid = rsp_select0 ? in0_core_rsp_if.valid : in1_core_rsp_if.valid; + assign out_core_rsp_if.data = rsp_select0 ? in0_core_rsp_if.data : in1_core_rsp_if.data; + assign out_core_rsp_if.tag = rsp_select0 ? in0_core_rsp_if.tag : in1_core_rsp_if.tag; + assign in0_core_rsp_if.ready = out_core_rsp_if.ready && rsp_select0; + assign in1_core_rsp_if.ready = out_core_rsp_if.ready && !rsp_select0; endmodule \ No newline at end of file diff --git a/hw/rtl/VX_decode.v b/hw/rtl/VX_decode.v index 0c8d4410..deb3f44b 100644 --- a/hw/rtl/VX_decode.v +++ b/hw/rtl/VX_decode.v @@ -12,7 +12,7 @@ module VX_decode( ); wire in_valid = (| fd_inst_meta_de.valid); wire[31:0] in_instruction = fd_inst_meta_de.instruction; - wire[31:0] in_curr_PC = fd_inst_meta_de.inst_pc; + wire[31:0] in_curr_PC = fd_inst_meta_de.curr_PC; wire[`NW_BITS-1:0] in_warp_num = fd_inst_meta_de.warp_num; assign frE_to_bckE_req_if.curr_PC = in_curr_PC; @@ -104,7 +104,7 @@ module VX_decode( assign is_lui = (curr_opcode == `INST_LUI); assign is_auipc = (curr_opcode == `INST_AUIPC); assign is_csr = (curr_opcode == `INST_SYS) && (func3 != 0); - assign is_csr_immed = (is_csr) && (func3[2] == 1); + assign is_csr_immed = is_csr && (func3[2] == 1); assign is_gpgpu = (curr_opcode == `INST_GPGPU); @@ -114,8 +114,8 @@ module VX_decode( assign is_split = is_gpgpu && (func3 == 2); // Goes to BE assign is_join = is_gpgpu && (func3 == 3); // Doesn't go to BE - assign join_if.is_join = is_join && in_valid; - assign join_if.join_warp_num = in_warp_num; + assign join_if.is_join = is_join && in_valid; + assign join_if.warp_num = in_warp_num; assign frE_to_bckE_req_if.is_wspawn = is_wspawn; assign frE_to_bckE_req_if.is_tmc = is_tmc; @@ -204,7 +204,7 @@ module VX_decode( assign csr_cond1 = func3 != 3'h0; assign csr_cond2 = u_12 >= 12'h2; - assign frE_to_bckE_req_if.csr_address = (csr_cond1 && csr_cond2) ? u_12 : 12'h55; + assign frE_to_bckE_req_if.csr_addr = (csr_cond1 && csr_cond2) ? u_12 : 12'h55; // ITYPE IMEED assign alu_shift_i = (func3 == 3'h1) || (func3 == 3'h5); @@ -227,7 +227,7 @@ module VX_decode( case (curr_opcode) `INST_B: begin // $display("BRANCH IN DECODE"); - temp_branch_stall = 1'b1 && in_valid; + temp_branch_stall = in_valid; case (func3) 3'h0: temp_branch_type = `BR_EQ; 3'h1: temp_branch_type = `BR_NE; @@ -240,15 +240,15 @@ module VX_decode( end `INST_JAL: begin temp_branch_type = `BR_NO; - temp_branch_stall = 1'b1 && in_valid; + temp_branch_stall = in_valid; end `INST_JALR: begin temp_branch_type = `BR_NO; - temp_branch_stall = 1'b1 && in_valid; + temp_branch_stall = in_valid; end default: begin temp_branch_type = `BR_NO; - temp_branch_stall = 1'b0 && in_valid; + temp_branch_stall = 1'b0; end endcase end diff --git a/hw/rtl/VX_define.vh b/hw/rtl/VX_define.vh index b36c1751..21da158e 100644 --- a/hw/rtl/VX_define.vh +++ b/hw/rtl/VX_define.vh @@ -72,6 +72,10 @@ `define CSR_WIDTH 12 +`define DIV_LATENCY 22 + +`define MUL_LATENCY 2 + /////////////////////////////////////////////////////////////////////////////// `define BYTE_EN_NO 3'h7 @@ -284,6 +288,7 @@ `define VX_DRAM_TAG_WIDTH `L3DRAM_TAG_WIDTH `define VX_SNP_TAG_WIDTH `L3SNP_TAG_WIDTH `define VX_CORE_TAG_WIDTH `L3CORE_TAG_WIDTH +`define VX_CSR_ID_WIDTH `CLOG2(`NUM_CLUSTERS * `NUM_CORES) `define DRAM_TO_BYTE_ADDR(x) {x, (32-$bits(x))'(0)} diff --git a/hw/rtl/VX_exec_unit.v b/hw/rtl/VX_exec_unit.v index 51f2da61..0b4259b5 100644 --- a/hw/rtl/VX_exec_unit.v +++ b/hw/rtl/VX_exec_unit.v @@ -15,18 +15,18 @@ module VX_exec_unit ( output wire delay ); - wire[`NUM_THREADS-1:0][31:0] in_a_reg_data; - wire[`NUM_THREADS-1:0][31:0] in_b_reg_data; - wire[4:0] in_alu_op; - wire in_rs2_src; - wire[31:0] in_itype_immed; + wire [`NUM_THREADS-1:0][31:0] in_a_reg_data; + wire [`NUM_THREADS-1:0][31:0] in_b_reg_data; + wire [4:0] in_alu_op; + wire in_rs2_src; + wire [31:0] in_itype_immed; `DEBUG_BEGIN - wire[2:0] in_branch_type; + wire [2:0] in_branch_type; `DEBUG_END - wire[19:0] in_upper_immed; - wire in_jal; - wire[31:0] in_jal_offset; - wire[31:0] in_curr_PC; + wire [19:0] in_upper_immed; + wire in_jal; + wire [31:0] in_jal_offset; + wire [31:0] in_curr_PC; assign in_a_reg_data = exec_unit_req_if.a_reg_data; assign in_b_reg_data = exec_unit_req_if.b_reg_data; @@ -39,12 +39,12 @@ module VX_exec_unit ( assign in_jal_offset = exec_unit_req_if.jal_offset; assign in_curr_PC = exec_unit_req_if.curr_PC; - wire[`NUM_THREADS-1:0][31:0] alu_result; - wire[`NUM_THREADS-1:0] alu_stall; + wire [`NUM_THREADS-1:0][31:0] alu_result; + wire [`NUM_THREADS-1:0] alu_stall; genvar i; generate - for (i = 0; i < `NUM_THREADS; i++) begin : alu_defs + for (i = 0; i < `NUM_THREADS; i++) begin VX_alu_unit alu_unit ( .clk (clk), .reset (reset), @@ -61,25 +61,21 @@ module VX_exec_unit ( end endgenerate - wire internal_stall; - assign internal_stall = (| alu_stall); + wire internal_stall = (| alu_stall); assign delay = no_slot_exec || internal_stall; -`DEBUG_BEGIN wire [$clog2(`NUM_THREADS)-1:0] jal_branch_use_index; - wire jal_branch_found_valid; -`DEBUG_END VX_priority_encoder #( .N(`NUM_THREADS) ) choose_alu_result ( - .data_in (exec_unit_req_if.valid), - .data_out (jal_branch_use_index), - .valid_out (jal_branch_found_valid) + .data_in (exec_unit_req_if.valid), + .data_out (jal_branch_use_index), + `UNUSED_PIN (valid_out) ); - wire[31:0] branch_use_alu_result = alu_result[jal_branch_use_index]; + wire [31:0] branch_use_alu_result = alu_result[jal_branch_use_index]; reg temp_branch_dir; always @(*) @@ -96,7 +92,7 @@ module VX_exec_unit ( endcase // in_branch_type end - wire[`NUM_THREADS-1:0][31:0] duplicate_PC_data; + wire [`NUM_THREADS-1:0][31:0] duplicate_PC_data; generate for (i = 0; i < `NUM_THREADS; i++) begin @@ -116,15 +112,15 @@ module VX_exec_unit ( assign inst_exec_wb_if.curr_PC = in_curr_PC; // Jal rsp - assign jal_rsp_temp_if.jal = in_jal; - assign jal_rsp_temp_if.jal_dest = $signed(in_a_reg_data[jal_branch_use_index]) + $signed(in_jal_offset); - assign jal_rsp_temp_if.jal_warp_num = exec_unit_req_if.warp_num; + assign jal_rsp_temp_if.valid = in_jal; + assign jal_rsp_temp_if.dest = $signed(in_a_reg_data[jal_branch_use_index]) + $signed(in_jal_offset); + assign jal_rsp_temp_if.warp_num = exec_unit_req_if.warp_num; // Branch rsp - assign branch_rsp_temp_if.valid_branch = (exec_unit_req_if.branch_type != `BR_NO) && (| exec_unit_req_if.valid); - assign branch_rsp_temp_if.branch_dir = temp_branch_dir; - assign branch_rsp_temp_if.branch_warp_num = exec_unit_req_if.warp_num; - assign branch_rsp_temp_if.branch_dest = $signed(exec_unit_req_if.curr_PC) + ($signed(exec_unit_req_if.itype_immed) << 1); // itype_immed = branch_offset + assign branch_rsp_temp_if.valid = (exec_unit_req_if.branch_type != `BR_NO) && (| exec_unit_req_if.valid); + assign branch_rsp_temp_if.dir = temp_branch_dir; + assign branch_rsp_temp_if.warp_num = exec_unit_req_if.warp_num; + assign branch_rsp_temp_if.dest = $signed(exec_unit_req_if.curr_PC) + ($signed(exec_unit_req_if.itype_immed) << 1); // itype_immed = branch_offset VX_generic_register #( .N(33 + `NW_BITS-1 + 1) @@ -133,8 +129,8 @@ module VX_exec_unit ( .reset (reset), .stall (1'b0), .flush (1'b0), - .in ({jal_rsp_temp_if.jal, jal_rsp_temp_if.jal_dest, jal_rsp_temp_if.jal_warp_num}), - .out ({jal_rsp_if.jal , jal_rsp_if.jal_dest , jal_rsp_if.jal_warp_num}) + .in ({jal_rsp_temp_if.valid, jal_rsp_temp_if.dest, jal_rsp_temp_if.warp_num}), + .out ({jal_rsp_if.valid , jal_rsp_if.dest , jal_rsp_if.warp_num}) ); VX_generic_register #( @@ -144,8 +140,8 @@ module VX_exec_unit ( .reset (reset), .stall (1'b0), .flush (1'b0), - .in ({branch_rsp_temp_if.valid_branch, branch_rsp_temp_if.branch_dir, branch_rsp_temp_if.branch_warp_num, branch_rsp_temp_if.branch_dest}), - .out ({branch_rsp_if.valid_branch , branch_rsp_if.branch_dir , branch_rsp_if.branch_warp_num , branch_rsp_if.branch_dest }) + .in ({branch_rsp_temp_if.valid, branch_rsp_temp_if.dir, branch_rsp_temp_if.warp_num, branch_rsp_temp_if.dest}), + .out ({branch_rsp_if.valid , branch_rsp_if.dir , branch_rsp_if.warp_num , branch_rsp_if.dest }) ); endmodule : VX_exec_unit \ No newline at end of file diff --git a/hw/rtl/VX_fetch.v b/hw/rtl/VX_fetch.v index 1247dac0..810f0317 100644 --- a/hw/rtl/VX_fetch.v +++ b/hw/rtl/VX_fetch.v @@ -57,7 +57,7 @@ module VX_fetch ( // Join .is_join (join_if.is_join), - .join_warp_num (join_if.join_warp_num), + .join_warp_num (join_if.warp_num), // Split .is_split (warp_ctl_if.is_split), @@ -68,15 +68,15 @@ module VX_fetch ( .split_warp_num (warp_ctl_if.warp_num), // JAL - .jal (jal_rsp_if.jal), - .jal_dest (jal_rsp_if.jal_dest), - .jal_warp_num (jal_rsp_if.jal_warp_num), + .jal (jal_rsp_if.valid), + .dest (jal_rsp_if.dest), + .jal_warp_num (jal_rsp_if.warp_num), // Branch - .branch_valid (branch_rsp_if.valid_branch), - .branch_dir (branch_rsp_if.branch_dir), - .branch_dest (branch_rsp_if.branch_dest), - .branch_warp_num (branch_rsp_if.branch_warp_num), + .branch_valid (branch_rsp_if.valid), + .branch_dir (branch_rsp_if.dir), + .branch_dest (branch_rsp_if.dest), + .branch_warp_num (branch_rsp_if.warp_num), // Outputs .thread_mask (thread_mask), @@ -89,7 +89,7 @@ module VX_fetch ( assign fe_inst_meta_fi.warp_num = warp_num; assign fe_inst_meta_fi.valid = thread_mask; assign fe_inst_meta_fi.instruction = 32'h0; - assign fe_inst_meta_fi.inst_pc = warp_pc; + assign fe_inst_meta_fi.curr_PC = warp_pc; `DEBUG_BEGIN wire start_mat_add = scheduled_warp && (warp_pc == 32'h80000ed8) && (warp_num == 0); diff --git a/hw/rtl/VX_front_end.v b/hw/rtl/VX_front_end.v index 9d17227c..8ceba8df 100644 --- a/hw/rtl/VX_front_end.v +++ b/hw/rtl/VX_front_end.v @@ -54,12 +54,15 @@ module VX_front_end #( .fe_inst_meta_fi (fe_inst_meta_fi) ); - VX_f_d_reg f_i_reg ( - .clk (clk), - .reset (reset), - .freeze (icache_stage_delay), - .fe_inst_meta_fd (fe_inst_meta_fi), - .fd_inst_meta_de (fe_inst_meta_fi2) + VX_generic_register #( + .N(64+`NW_BITS-1+1+`NUM_THREADS) + ) f_d_reg ( + .clk (clk), + .reset (reset), + .stall (icache_stage_delay), + .flush (1'b0), + .in ({fe_inst_meta_fi.instruction, fe_inst_meta_fi.curr_PC, fe_inst_meta_fi.warp_num, fe_inst_meta_fi.valid}), + .out ({fe_inst_meta_fi2.instruction, fe_inst_meta_fi2.curr_PC, fe_inst_meta_fi2.warp_num, fe_inst_meta_fi2.valid}) ); VX_icache_stage #( @@ -79,12 +82,15 @@ module VX_front_end #( .icache_req_if (icache_req_if) ); - VX_i_d_reg i_d_reg ( - .clk (clk), - .reset (reset), - .freeze (total_freeze), - .fe_inst_meta_fd (fe_inst_meta_id), - .fd_inst_meta_de (fd_inst_meta_de) + VX_generic_register #( + .N(64 + `NW_BITS-1 + 1 + `NUM_THREADS) + ) i_d_reg ( + .clk (clk), + .reset (reset), + .stall (total_freeze), + .flush (1'b0), + .in ({fe_inst_meta_id.instruction, fe_inst_meta_id.curr_PC, fe_inst_meta_id.warp_num, fe_inst_meta_id.valid}), + .out ({fd_inst_meta_de.instruction, fd_inst_meta_de.curr_PC, fd_inst_meta_de.warp_num, fd_inst_meta_de.valid}) ); VX_decode decode ( @@ -94,16 +100,16 @@ module VX_front_end #( .join_if (join_if) ); - wire no_br_stall = 0; - - VX_d_e_reg d_e_reg ( - .clk (clk), - .reset (reset), - .branch_stall (no_br_stall), - .freeze (total_freeze), - .frE_to_bckE_req_if (frE_to_bckE_req_if), - .bckE_req_if (bckE_req_if) - ); + VX_generic_register #( + .N(233 + `NW_BITS-1 + 1 + `NUM_THREADS) + ) d_e_reg ( + .clk (clk), + .reset (reset), + .stall (total_freeze), + .flush (1'b0), + .in ({frE_to_bckE_req_if.csr_addr, frE_to_bckE_req_if.is_jal, frE_to_bckE_req_if.is_etype, frE_to_bckE_req_if.is_csr, frE_to_bckE_req_if.csr_immed, frE_to_bckE_req_if.csr_mask, frE_to_bckE_req_if.rd, frE_to_bckE_req_if.rs1, frE_to_bckE_req_if.rs2, frE_to_bckE_req_if.alu_op, frE_to_bckE_req_if.wb, frE_to_bckE_req_if.rs2_src, frE_to_bckE_req_if.itype_immed, frE_to_bckE_req_if.mem_read, frE_to_bckE_req_if.mem_write, frE_to_bckE_req_if.branch_type, frE_to_bckE_req_if.upper_immed, frE_to_bckE_req_if.curr_PC, frE_to_bckE_req_if.jal, frE_to_bckE_req_if.jal_offset, frE_to_bckE_req_if.next_PC, frE_to_bckE_req_if.valid, frE_to_bckE_req_if.warp_num, frE_to_bckE_req_if.is_wspawn, frE_to_bckE_req_if.is_tmc, frE_to_bckE_req_if.is_split, frE_to_bckE_req_if.is_barrier}), + .out ({bckE_req_if.csr_addr , bckE_req_if.is_jal , bckE_req_if.is_etype ,bckE_req_if.is_csr , bckE_req_if.csr_immed , bckE_req_if.csr_mask , bckE_req_if.rd , bckE_req_if.rs1 , bckE_req_if.rs2 , bckE_req_if.alu_op , bckE_req_if.wb , bckE_req_if.rs2_src , bckE_req_if.itype_immed , bckE_req_if.mem_read , bckE_req_if.mem_write , bckE_req_if.branch_type , bckE_req_if.upper_immed , bckE_req_if.curr_PC , bckE_req_if.jal , bckE_req_if.jal_offset , bckE_req_if.next_PC , bckE_req_if.valid , bckE_req_if.warp_num , bckE_req_if.is_wspawn , bckE_req_if.is_tmc , bckE_req_if.is_split , bckE_req_if.is_barrier }) + ); endmodule diff --git a/hw/rtl/VX_gpr_stage.v b/hw/rtl/VX_gpr_stage.v index 67c52a52..e0f5f865 100644 --- a/hw/rtl/VX_gpr_stage.v +++ b/hw/rtl/VX_gpr_stage.v @@ -8,7 +8,7 @@ module VX_gpr_stage ( input wire memory_delay, input wire exec_delay, input wire stall_gpr_csr, - output wire gpr_stage_delay, + output wire delay, // decodee inputs VX_backend_req_if bckE_req_if, @@ -30,6 +30,8 @@ module VX_gpr_stage ( wire is_jal = bckE_req_if.is_jal; `DEBUG_END + assign csr_req_if.is_io = 1'b0; // GPR only issues csr requests coming from core + VX_gpr_read_if gpr_read_if(); assign gpr_read_if.rs1 = bckE_req_if.rs1; assign gpr_read_if.rs2 = bckE_req_if.rs2; @@ -79,7 +81,7 @@ module VX_gpr_stage ( wire stall_csr = stall_gpr_csr && bckE_req_if.is_csr && (| bckE_req_if.valid); - assign gpr_stage_delay = stall_lsu || stall_exec || stall_csr; + assign delay = stall_lsu || stall_exec || stall_csr; `ifdef ASIC wire delayed_lsu_last_cycle; @@ -97,10 +99,10 @@ module VX_gpr_stage ( ); wire [`NUM_THREADS-1:0][31:0] temp_store_data; - wire [`NUM_THREADS-1:0][31:0] temp_base_address; // A reg data + wire [`NUM_THREADS-1:0][31:0] temp_base_addr; // A reg data wire [`NUM_THREADS-1:0][31:0] real_store_data; - wire [`NUM_THREADS-1:0][31:0] real_base_address; // A reg data + wire [`NUM_THREADS-1:0][31:0] real_base_addr; // A reg data wire store_curr_real = !delayed_lsu_last_cycle && stall_lsu; @@ -111,15 +113,15 @@ module VX_gpr_stage ( .reset (reset), .stall (!store_curr_real), .flush (stall_rest), - .in ({real_store_data, real_base_address}), - .out ({temp_store_data, temp_base_address}) + .in ({real_store_data, real_base_addr}), + .out ({temp_store_data, temp_base_addr}) ); - assign real_store_data = lsu_req_temp_if.store_data; - assign real_base_address = lsu_req_temp_if.base_address; + assign real_store_data = lsu_req_temp_if.store_data; + assign real_base_addr = lsu_req_temp_if.base_addr; - assign lsu_req_if.store_data = (delayed_lsu_last_cycle) ? temp_store_data : real_store_data; - assign lsu_req_if.base_address = (delayed_lsu_last_cycle) ? temp_base_address : real_base_address; + assign lsu_req_if.store_data = (delayed_lsu_last_cycle) ? temp_store_data : real_store_data; + assign lsu_req_if.base_addr = (delayed_lsu_last_cycle) ? temp_base_addr : real_base_addr; VX_generic_register #( .N(77 + `NW_BITS-1 + 1 + (`NUM_THREADS)) @@ -139,11 +141,11 @@ module VX_gpr_stage ( .reset (reset), .stall (stall_exec), .flush (flush_exec), - .in ({exec_unit_req_temp_if.valid, exec_unit_req_temp_if.warp_num, exec_unit_req_temp_if.curr_PC, exec_unit_req_temp_if.next_PC, exec_unit_req_temp_if.rd, exec_unit_req_temp_if.wb, exec_unit_req_temp_if.alu_op, exec_unit_req_temp_if.rs1, exec_unit_req_temp_if.rs2, exec_unit_req_temp_if.rs2_src, exec_unit_req_temp_if.itype_immed, exec_unit_req_temp_if.upper_immed, exec_unit_req_temp_if.branch_type, exec_unit_req_temp_if.is_jal, exec_unit_req_temp_if.jal, exec_unit_req_temp_if.jal_offset, exec_unit_req_temp_if.is_etype, exec_unit_req_temp_if.wspawn, exec_unit_req_temp_if.is_csr, exec_unit_req_temp_if.csr_address, exec_unit_req_temp_if.csr_immed, exec_unit_req_temp_if.csr_mask}), - .out ({exec_unit_req_if.valid , exec_unit_req_if.warp_num , exec_unit_req_if.curr_PC , exec_unit_req_if.next_PC , exec_unit_req_if.rd , exec_unit_req_if.wb , exec_unit_req_if.alu_op , exec_unit_req_if.rs1 , exec_unit_req_if.rs2 , exec_unit_req_if.rs2_src , exec_unit_req_if.itype_immed , exec_unit_req_if.upper_immed , exec_unit_req_if.branch_type , exec_unit_req_if.is_jal , exec_unit_req_if.jal , exec_unit_req_if.jal_offset , exec_unit_req_if.is_etype , exec_unit_req_if.wspawn , exec_unit_req_if.is_csr , exec_unit_req_if.csr_address , exec_unit_req_if.csr_immed , exec_unit_req_if.csr_mask }) + .in ({exec_unit_req_temp_if.valid, exec_unit_req_temp_if.warp_num, exec_unit_req_temp_if.curr_PC, exec_unit_req_temp_if.next_PC, exec_unit_req_temp_if.rd, exec_unit_req_temp_if.wb, exec_unit_req_temp_if.alu_op, exec_unit_req_temp_if.rs1, exec_unit_req_temp_if.rs2, exec_unit_req_temp_if.rs2_src, exec_unit_req_temp_if.itype_immed, exec_unit_req_temp_if.upper_immed, exec_unit_req_temp_if.branch_type, exec_unit_req_temp_if.is_jal, exec_unit_req_temp_if.jal, exec_unit_req_temp_if.jal_offset, exec_unit_req_temp_if.is_etype, exec_unit_req_temp_if.wspawn, exec_unit_req_temp_if.is_csr, exec_unit_req_temp_if.csr_addr, exec_unit_req_temp_if.csr_immed, exec_unit_req_temp_if.csr_mask}), + .out ({exec_unit_req_if.valid , exec_unit_req_if.warp_num , exec_unit_req_if.curr_PC , exec_unit_req_if.next_PC , exec_unit_req_if.rd , exec_unit_req_if.wb , exec_unit_req_if.alu_op , exec_unit_req_if.rs1 , exec_unit_req_if.rs2 , exec_unit_req_if.rs2_src , exec_unit_req_if.itype_immed , exec_unit_req_if.upper_immed , exec_unit_req_if.branch_type , exec_unit_req_if.is_jal , exec_unit_req_if.jal , exec_unit_req_if.jal_offset , exec_unit_req_if.is_etype , exec_unit_req_if.wspawn , exec_unit_req_if.is_csr , exec_unit_req_if.csr_addr , exec_unit_req_if.csr_immed , exec_unit_req_if.csr_mask }) ); - assign exec_unit_req_if.a_reg_data = real_base_address; + assign exec_unit_req_if.a_reg_data = real_base_addr; assign exec_unit_req_if.b_reg_data = real_store_data; VX_generic_register #( @@ -157,7 +159,7 @@ module VX_gpr_stage ( .out ({gpu_inst_req_if.valid , gpu_inst_req_if.warp_num , gpu_inst_req_if.is_wspawn , gpu_inst_req_if.is_tmc , gpu_inst_req_if.is_split , gpu_inst_req_if.is_barrier , gpu_inst_req_if.next_PC }) ); - assign gpu_inst_req_if.a_reg_data = real_base_address; + assign gpu_inst_req_if.a_reg_data = real_base_addr; assign gpu_inst_req_if.rd2 = real_store_data; VX_generic_register #( @@ -167,10 +169,11 @@ module VX_gpr_stage ( .reset (reset), .stall (stall_gpr_csr), .flush (flush_rest), - .in ({csr_req_temp_if.valid, csr_req_temp_if.warp_num, csr_req_temp_if.rd, csr_req_temp_if.wb, csr_req_temp_if.alu_op, csr_req_temp_if.is_csr, csr_req_temp_if.csr_address, csr_req_temp_if.csr_immed, csr_req_temp_if.csr_mask}), - .out ({csr_req_if.valid , csr_req_if.warp_num , csr_req_if.rd , csr_req_if.wb , csr_req_if.alu_op , csr_req_if.is_csr , csr_req_if.csr_address , csr_req_if.csr_immed , csr_req_if.csr_mask }) + .in ({csr_req_temp_if.valid, csr_req_temp_if.warp_num, csr_req_temp_if.rd, csr_req_temp_if.wb, csr_req_temp_if.alu_op, csr_req_temp_if.is_csr, csr_req_temp_if.csr_addr, csr_req_temp_if.csr_immed, csr_req_temp_if.csr_mask}), + .out ({csr_req_if.valid , csr_req_if.warp_num , csr_req_if.rd , csr_req_if.wb , csr_req_if.alu_op , csr_req_if.is_csr , csr_req_if.csr_addr , csr_req_if.csr_immed , csr_req_if.csr_mask }) ); + `else // 341 @@ -181,8 +184,8 @@ module VX_gpr_stage ( .reset (reset), .stall (stall_lsu), .flush (flush_lsu), - .in ({lsu_req_temp_if.valid, lsu_req_temp_if.curr_PC, lsu_req_temp_if.warp_num, lsu_req_temp_if.store_data, lsu_req_temp_if.base_address, lsu_req_temp_if.offset, lsu_req_temp_if.mem_read, lsu_req_temp_if.mem_write, lsu_req_temp_if.rd, lsu_req_temp_if.wb}), - .out ({lsu_req_if.valid , lsu_req_if.curr_PC , lsu_req_if.warp_num , lsu_req_if.store_data , lsu_req_if.base_address , lsu_req_if.offset , lsu_req_if.mem_read , lsu_req_if.mem_write , lsu_req_if.rd , lsu_req_if.wb }) + .in ({lsu_req_temp_if.valid, lsu_req_temp_if.curr_PC, lsu_req_temp_if.warp_num, lsu_req_temp_if.store_data, lsu_req_temp_if.base_addr, lsu_req_temp_if.offset, lsu_req_temp_if.mem_read, lsu_req_temp_if.mem_write, lsu_req_temp_if.rd, lsu_req_temp_if.wb}), + .out ({lsu_req_if.valid , lsu_req_if.curr_PC , lsu_req_if.warp_num , lsu_req_if.store_data , lsu_req_if.base_addr , lsu_req_if.offset , lsu_req_if.mem_read , lsu_req_if.mem_write , lsu_req_if.rd , lsu_req_if.wb }) ); VX_generic_register #( @@ -192,8 +195,8 @@ module VX_gpr_stage ( .reset (reset), .stall (stall_exec), .flush (flush_exec), - .in ({exec_unit_req_temp_if.valid, exec_unit_req_temp_if.warp_num, exec_unit_req_temp_if.curr_PC, exec_unit_req_temp_if.next_PC, exec_unit_req_temp_if.rd, exec_unit_req_temp_if.wb, exec_unit_req_temp_if.a_reg_data, exec_unit_req_temp_if.b_reg_data, exec_unit_req_temp_if.alu_op, exec_unit_req_temp_if.rs1, exec_unit_req_temp_if.rs2, exec_unit_req_temp_if.rs2_src, exec_unit_req_temp_if.itype_immed, exec_unit_req_temp_if.upper_immed, exec_unit_req_temp_if.branch_type, exec_unit_req_temp_if.is_jal, exec_unit_req_temp_if.jal, exec_unit_req_temp_if.jal_offset, exec_unit_req_temp_if.is_etype, exec_unit_req_temp_if.wspawn, exec_unit_req_temp_if.is_csr, exec_unit_req_temp_if.csr_address, exec_unit_req_temp_if.csr_immed, exec_unit_req_temp_if.csr_mask}), - .out ({exec_unit_req_if.valid , exec_unit_req_if.warp_num , exec_unit_req_if.curr_PC , exec_unit_req_if.next_PC , exec_unit_req_if.rd , exec_unit_req_if.wb , exec_unit_req_if.a_reg_data , exec_unit_req_if.b_reg_data , exec_unit_req_if.alu_op , exec_unit_req_if.rs1 , exec_unit_req_if.rs2 , exec_unit_req_if.rs2_src , exec_unit_req_if.itype_immed , exec_unit_req_if.upper_immed , exec_unit_req_if.branch_type , exec_unit_req_if.is_jal , exec_unit_req_if.jal , exec_unit_req_if.jal_offset , exec_unit_req_if.is_etype , exec_unit_req_if.wspawn , exec_unit_req_if.is_csr , exec_unit_req_if.csr_address , exec_unit_req_if.csr_immed , exec_unit_req_if.csr_mask }) + .in ({exec_unit_req_temp_if.valid, exec_unit_req_temp_if.warp_num, exec_unit_req_temp_if.curr_PC, exec_unit_req_temp_if.next_PC, exec_unit_req_temp_if.rd, exec_unit_req_temp_if.wb, exec_unit_req_temp_if.a_reg_data, exec_unit_req_temp_if.b_reg_data, exec_unit_req_temp_if.alu_op, exec_unit_req_temp_if.rs1, exec_unit_req_temp_if.rs2, exec_unit_req_temp_if.rs2_src, exec_unit_req_temp_if.itype_immed, exec_unit_req_temp_if.upper_immed, exec_unit_req_temp_if.branch_type, exec_unit_req_temp_if.is_jal, exec_unit_req_temp_if.jal, exec_unit_req_temp_if.jal_offset, exec_unit_req_temp_if.is_etype, exec_unit_req_temp_if.wspawn, exec_unit_req_temp_if.is_csr, exec_unit_req_temp_if.csr_addr, exec_unit_req_temp_if.csr_immed, exec_unit_req_temp_if.csr_mask}), + .out ({exec_unit_req_if.valid , exec_unit_req_if.warp_num , exec_unit_req_if.curr_PC , exec_unit_req_if.next_PC , exec_unit_req_if.rd , exec_unit_req_if.wb , exec_unit_req_if.a_reg_data , exec_unit_req_if.b_reg_data , exec_unit_req_if.alu_op , exec_unit_req_if.rs1 , exec_unit_req_if.rs2 , exec_unit_req_if.rs2_src , exec_unit_req_if.itype_immed , exec_unit_req_if.upper_immed , exec_unit_req_if.branch_type , exec_unit_req_if.is_jal , exec_unit_req_if.jal , exec_unit_req_if.jal_offset , exec_unit_req_if.is_etype , exec_unit_req_if.wspawn , exec_unit_req_if.is_csr , exec_unit_req_if.csr_addr , exec_unit_req_if.csr_immed , exec_unit_req_if.csr_mask }) ); VX_generic_register #( @@ -214,10 +217,10 @@ module VX_gpr_stage ( .reset (reset), .stall (stall_gpr_csr), .flush (flush_rest), - .in ({csr_req_temp_if.valid, csr_req_temp_if.warp_num, csr_req_temp_if.rd, csr_req_temp_if.wb, csr_req_temp_if.alu_op, csr_req_temp_if.is_csr, csr_req_temp_if.csr_address, csr_req_temp_if.csr_immed, csr_req_temp_if.csr_mask}), - .out ({csr_req_if.valid , csr_req_if.warp_num , csr_req_if.rd , csr_req_if.wb , csr_req_if.alu_op , csr_req_if.is_csr , csr_req_if.csr_address , csr_req_if.csr_immed , csr_req_if.csr_mask }) + .in ({csr_req_temp_if.valid, csr_req_temp_if.warp_num, csr_req_temp_if.rd, csr_req_temp_if.wb, csr_req_temp_if.alu_op, csr_req_temp_if.is_csr, csr_req_temp_if.csr_addr, csr_req_temp_if.csr_immed, csr_req_temp_if.csr_mask}), + .out ({csr_req_if.valid , csr_req_if.warp_num , csr_req_if.rd , csr_req_if.wb , csr_req_if.alu_op , csr_req_if.is_csr , csr_req_if.csr_addr , csr_req_if.csr_immed , csr_req_if.csr_mask }) ); `endif -endmodule : VX_gpr_stage \ No newline at end of file +endmodule : VX_gpr_stage diff --git a/hw/rtl/VX_icache_stage.v b/hw/rtl/VX_icache_stage.v index 3985fe05..5232f943 100644 --- a/hw/rtl/VX_icache_stage.v +++ b/hw/rtl/VX_icache_stage.v @@ -25,10 +25,10 @@ module VX_icache_stage #( wire [`LOG2UP(`ICREQ_SIZE)-1:0] mrq_write_addr, mrq_read_addr, dbg_mrq_write_addr; wire mrq_full; - wire mrq_push = icache_req_if.core_req_valid && icache_req_if.core_req_ready; - wire mrq_pop = icache_rsp_if.core_rsp_valid && icache_rsp_if.core_rsp_ready; + wire mrq_push = icache_req_if.valid && icache_req_if.ready; + wire mrq_pop = icache_rsp_if.valid && icache_rsp_if.ready; - assign mrq_read_addr = icache_rsp_if.core_rsp_tag[0][`LOG2UP(`ICREQ_SIZE)-1:0]; + assign mrq_read_addr = icache_rsp_if.tag[0][`LOG2UP(`ICREQ_SIZE)-1:0]; VX_indexable_queue #( .DATAW (`LOG2UP(`ICREQ_SIZE) + 32 + `NW_BITS), @@ -36,13 +36,13 @@ module VX_icache_stage #( ) mem_req_queue ( .clk (clk), .reset (reset), - .write_data ({mrq_write_addr, fe_inst_meta_fi.inst_pc, fe_inst_meta_fi.warp_num}), + .write_data ({mrq_write_addr, fe_inst_meta_fi.curr_PC, fe_inst_meta_fi.warp_num}), .write_addr (mrq_write_addr), .push (mrq_push), .full (mrq_full), .pop (mrq_pop), .read_addr (mrq_read_addr), - .read_data ({dbg_mrq_write_addr, fe_inst_meta_id.inst_pc, fe_inst_meta_id.warp_num}), + .read_data ({dbg_mrq_write_addr, fe_inst_meta_id.curr_PC, fe_inst_meta_id.warp_num}), `UNUSED_PIN (empty) ); @@ -56,48 +56,48 @@ module VX_icache_stage #( end // Icache Request - assign icache_req_if.core_req_valid = valid_inst && !mrq_full; - assign icache_req_if.core_req_rw = 0; - assign icache_req_if.core_req_byteen = 4'b1111; - assign icache_req_if.core_req_addr = fe_inst_meta_fi.inst_pc[31:2]; - assign icache_req_if.core_req_data = 0; + assign icache_req_if.valid = valid_inst && !mrq_full; + assign icache_req_if.rw = 0; + assign icache_req_if.byteen = 4'b1111; + assign icache_req_if.addr = fe_inst_meta_fi.curr_PC[31:2]; + assign icache_req_if.data = 0; // Can't accept new request - assign icache_stage_delay = mrq_full || !icache_req_if.core_req_ready; + assign icache_stage_delay = mrq_full || !icache_req_if.ready; `ifdef DBG_CORE_REQ_INFO - assign icache_req_if.core_req_tag = {fe_inst_meta_fi.inst_pc, 2'b1, 5'b0, fe_inst_meta_fi.warp_num, mrq_write_addr}; + assign icache_req_if.tag = {fe_inst_meta_fi.curr_PC, 2'b1, 5'b0, fe_inst_meta_fi.warp_num, mrq_write_addr}; `else - assign icache_req_if.core_req_tag = mrq_write_addr; + assign icache_req_if.tag = mrq_write_addr; `endif - assign fe_inst_meta_id.instruction = icache_rsp_if.core_rsp_valid ? icache_rsp_if.core_rsp_data[0] : 0; - assign fe_inst_meta_id.valid = icache_rsp_if.core_rsp_valid ? valid_threads[fe_inst_meta_id.warp_num] : 0; + assign fe_inst_meta_id.instruction = icache_rsp_if.valid ? icache_rsp_if.data[0] : 0; + assign fe_inst_meta_id.valid = icache_rsp_if.valid ? valid_threads[fe_inst_meta_id.warp_num] : 0; assign icache_stage_response = mrq_pop; assign icache_stage_wid = fe_inst_meta_id.warp_num; // Can't accept new response - assign icache_rsp_if.core_rsp_ready = !total_freeze; + assign icache_rsp_if.ready = !total_freeze; - `SCOPE_ASSIGN(scope_icache_req_valid, icache_req_if.core_req_valid); + `SCOPE_ASSIGN(scope_icache_req_valid, icache_req_if.valid); `SCOPE_ASSIGN(scope_icache_req_warp_num, fe_inst_meta_fi.warp_num); - `SCOPE_ASSIGN(scope_icache_req_addr, {icache_req_if.core_req_addr, 2'b0}); - `SCOPE_ASSIGN(scope_icache_req_tag, icache_req_if.core_req_tag); - `SCOPE_ASSIGN(scope_icache_req_ready, icache_req_if.core_req_ready); + `SCOPE_ASSIGN(scope_icache_req_addr, {icache_req_if.addr, 2'b0}); + `SCOPE_ASSIGN(scope_icache_req_tag, icache_req_if.tag); + `SCOPE_ASSIGN(scope_icache_req_ready, icache_req_if.ready); - `SCOPE_ASSIGN(scope_icache_rsp_valid, icache_rsp_if.core_rsp_valid); - `SCOPE_ASSIGN(scope_icache_rsp_data, icache_rsp_if.core_rsp_data); - `SCOPE_ASSIGN(scope_icache_rsp_tag, icache_rsp_if.core_rsp_tag); - `SCOPE_ASSIGN(scope_icache_rsp_ready, icache_rsp_if.core_rsp_ready); + `SCOPE_ASSIGN(scope_icache_rsp_valid, icache_rsp_if.valid); + `SCOPE_ASSIGN(scope_icache_rsp_data, icache_rsp_if.data); + `SCOPE_ASSIGN(scope_icache_rsp_tag, icache_rsp_if.tag); + `SCOPE_ASSIGN(scope_icache_rsp_ready, icache_rsp_if.ready); `ifdef DBG_PRINT_CORE_ICACHE always @(posedge clk) begin - if (icache_req_if.core_req_valid && icache_req_if.core_req_ready) begin - $display("%t: I%0d$ req: tag=%0h, pc=%0h, warp=%0d", $time, CORE_ID, mrq_write_addr, fe_inst_meta_fi.inst_pc, fe_inst_meta_fi.warp_num); + if (icache_req_if.valid && icache_req_if.ready) begin + $display("%t: I%0d$ req: tag=%0h, pc=%0h, warp=%0d", $time, CORE_ID, mrq_write_addr, fe_inst_meta_fi.curr_PC, fe_inst_meta_fi.warp_num); end - if (icache_rsp_if.core_rsp_valid && icache_rsp_if.core_rsp_ready) begin - $display("%t: I%0d$ rsp: tag=%0h, pc=%0h, warp=%0d, instr=%0h", $time, CORE_ID, mrq_read_addr, fe_inst_meta_id.inst_pc, fe_inst_meta_id.warp_num, fe_inst_meta_id.instruction); + if (icache_rsp_if.valid && icache_rsp_if.ready) begin + $display("%t: I%0d$ rsp: tag=%0h, pc=%0h, warp=%0d, instr=%0h", $time, CORE_ID, mrq_read_addr, fe_inst_meta_id.curr_PC, fe_inst_meta_id.warp_num, fe_inst_meta_id.instruction); end end `endif diff --git a/hw/rtl/VX_inst_multiplex.v b/hw/rtl/VX_inst_multiplex.v index 57cf3387..73225085 100644 --- a/hw/rtl/VX_inst_multiplex.v +++ b/hw/rtl/VX_inst_multiplex.v @@ -33,7 +33,7 @@ module VX_inst_multiplex ( // LSU Unit assign lsu_req_if.valid = bckE_req_if.valid & is_mem_mask; assign lsu_req_if.warp_num = bckE_req_if.warp_num; - assign lsu_req_if.base_address = gpr_read_if.a_reg_data; + assign lsu_req_if.base_addr = gpr_read_if.a_reg_data; assign lsu_req_if.store_data = gpr_read_if.b_reg_data; assign lsu_req_if.offset = bckE_req_if.itype_immed; @@ -83,7 +83,7 @@ module VX_inst_multiplex ( assign csr_req_if.wb = bckE_req_if.wb; assign csr_req_if.alu_op = bckE_req_if.alu_op; assign csr_req_if.is_csr = bckE_req_if.is_csr; - assign csr_req_if.csr_address = bckE_req_if.csr_address; + assign csr_req_if.csr_addr = bckE_req_if.csr_addr; assign csr_req_if.csr_immed = bckE_req_if.csr_immed; assign csr_req_if.csr_mask = bckE_req_if.csr_mask; diff --git a/hw/rtl/VX_lsu_unit.v b/hw/rtl/VX_lsu_unit.v index 640640b3..d1296680 100644 --- a/hw/rtl/VX_lsu_unit.v +++ b/hw/rtl/VX_lsu_unit.v @@ -12,7 +12,7 @@ module VX_lsu_unit #( VX_lsu_req_if lsu_req_if, // Write back to GPR - VX_wb_if mem_wb_if_p1, + VX_wb_if mem_wb_if, // Dcache interface VX_cache_core_req_if dcache_req_if, @@ -21,92 +21,98 @@ module VX_lsu_unit #( output wire delay ); - VX_wb_if mem_wb_if(); + VX_wb_if mem_wb_unqual_if(); - wire[`NUM_THREADS-1:0][31:0] use_address; - wire[`NUM_THREADS-1:0][31:0] use_store_data; - wire[`NUM_THREADS-1:0] use_valid; - wire[`BYTE_EN_BITS-1:0] use_mem_read; - wire[`BYTE_EN_BITS-1:0] use_mem_write; - wire[4:0] use_rd; - wire[`NW_BITS-1:0] use_warp_num; - wire[1:0] use_wb; - wire[31:0] use_pc; + wire [`NUM_THREADS-1:0] use_valid; + wire use_req_rw; + wire [`NUM_THREADS-1:0][29:0] use_req_addr; + wire [`NUM_THREADS-1:0][1:0] use_req_offset; + wire [`NUM_THREADS-1:0][3:0] use_req_byteen; + wire [`NUM_THREADS-1:0][31:0] use_req_data; + wire [`BYTE_EN_BITS-1:0] use_mem_read; + wire [4:0] use_rd; + wire [`NW_BITS-1:0] use_warp_num; + wire [1:0] use_wb; + wire [31:0] use_pc; genvar i; // Generate Full Addresses - wire[`NUM_THREADS-1:0][31:0] full_address; + wire[`NUM_THREADS-1:0][31:0] full_address; for (i = 0; i < `NUM_THREADS; i++) begin - assign full_address[i] = lsu_req_if.base_address[i] + lsu_req_if.offset; + assign full_address[i] = lsu_req_if.base_addr[i] + lsu_req_if.offset; end - VX_generic_register #( - .N(45 + `NW_BITS-1 + 1 + `NUM_THREADS*65) - ) lsu_buffer ( - .clk (clk), - .reset (reset), - .stall (delay), - .flush (1'b0), - .in ({full_address,lsu_req_if.store_data, lsu_req_if.valid, lsu_req_if.mem_read, lsu_req_if.mem_write, lsu_req_if.rd, lsu_req_if.warp_num, lsu_req_if.wb, lsu_req_if.curr_PC}), - .out ({use_address, use_store_data , use_valid , use_mem_read , use_mem_write , use_rd , use_warp_num , use_wb , use_pc }) - ); - - wire core_req_rw = (use_mem_write != `BYTE_EN_NO); - - wire [`NUM_THREADS-1:0][4:0] mem_req_offset; - wire [`NUM_THREADS-1:0][29:0] mem_req_addr; - wire [`NUM_THREADS-1:0][3:0] mem_req_byteen; - wire [`NUM_THREADS-1:0][31:0] mem_req_data; - - wire [`NUM_THREADS-1:0][4:0] mem_rsp_offset; - wire[2:0] core_rsp_mem_read; + wire mem_req_rw = (lsu_req_if.mem_write != `BYTE_EN_NO); reg [3:0] wmask; always @(*) begin - case ((core_req_rw ? use_mem_write[1:0] : use_mem_read[1:0])) + case ((mem_req_rw ? lsu_req_if.mem_write[1:0] : lsu_req_if.mem_read[1:0])) 0: wmask = 4'b0001; 1: wmask = 4'b0011; default : wmask = 4'b1111; endcase end - for (i = 0; i < `NUM_THREADS; ++i) begin - assign mem_req_addr[i] = use_address[i][31:2]; - assign mem_req_offset[i] = (5'(use_address[i][1:0])) << 3; - assign mem_req_byteen[i] = (wmask << use_address[i][1:0]); - assign mem_req_data[i] = (use_store_data[i] << mem_req_offset[i]); - end + wire [`NUM_THREADS-1:0][29:0] mem_req_addr; + wire [`NUM_THREADS-1:0][1:0] mem_req_offset; + wire [`NUM_THREADS-1:0][3:0] mem_req_byteen; + wire [`NUM_THREADS-1:0][31:0] mem_req_data; + + for (i = 0; i < `NUM_THREADS; i++) begin + assign mem_req_addr[i] = full_address[i][31:2]; + assign mem_req_offset[i] = full_address[i][1:0]; + assign mem_req_byteen[i] = wmask << full_address[i][1:0]; + assign mem_req_data[i] = lsu_req_if.store_data[i] << {mem_req_offset[i], 3'b0}; + end + +`IGNORE_WARNINGS_BEGIN + wire[`NUM_THREADS-1:0][31:0] use_address; +`IGNORE_WARNINGS_END + + VX_generic_register #( + .N((`NUM_THREADS * 1) + (`NUM_THREADS * 32) + `BYTE_EN_BITS + 1 + (`NUM_THREADS * (30 + 2 + 4 + 32)) + 5 + `NW_BITS + 2 + 32) + ) lsu_buffer ( + .clk (clk), + .reset (reset), + .stall (delay), + .flush (1'b0), + .in ({lsu_req_if.valid, full_address, lsu_req_if.mem_read, mem_req_rw, mem_req_addr, mem_req_offset, mem_req_byteen, mem_req_data, lsu_req_if.rd, lsu_req_if.warp_num, lsu_req_if.wb, lsu_req_if.curr_PC}), + .out ({use_valid , use_address, use_mem_read , use_req_rw, use_req_addr, use_req_offset, use_req_byteen, use_req_data, use_rd , use_warp_num , use_wb , use_pc}) + ); + + wire [`NUM_THREADS-1:0][1:0] mem_rsp_offset; + wire [`BYTE_EN_BITS-1:0] core_rsp_mem_read; reg [`NUM_THREADS-1:0] mem_rsp_mask[`DCREQ_SIZE-1:0]; wire [`LOG2UP(`DCREQ_SIZE)-1:0] mrq_write_addr, mrq_read_addr, dbg_mrq_write_addr; wire mrq_full; - wire mrq_push = (| dcache_req_if.core_req_valid) && dcache_req_if.core_req_ready - && (0 == core_req_rw); // only push read requests + wire mrq_push = (| dcache_req_if.valid) && dcache_req_if.ready + && (0 == use_req_rw); // only push read requests - wire mrq_pop_part = (| dcache_rsp_if.core_rsp_valid) && dcache_rsp_if.core_rsp_ready; + wire mrq_pop_part = (| dcache_rsp_if.valid) && dcache_rsp_if.ready; - assign mrq_read_addr = dcache_rsp_if.core_rsp_tag[0][`LOG2UP(`DCREQ_SIZE)-1:0]; + assign mrq_read_addr = dcache_rsp_if.tag[0][`LOG2UP(`DCREQ_SIZE)-1:0]; - wire [`NUM_THREADS-1:0] mem_rsp_mask_upd = mem_rsp_mask[mrq_read_addr] & ~dcache_rsp_if.core_rsp_valid; + wire [`NUM_THREADS-1:0] mem_rsp_mask_upd = mem_rsp_mask[mrq_read_addr] & ~dcache_rsp_if.valid; wire mrq_pop = mrq_pop_part && (0 == mem_rsp_mask_upd); VX_indexable_queue #( - .DATAW (`LOG2UP(`DCREQ_SIZE) + 32 + 2 + (`NUM_THREADS * 5) + `BYTE_EN_BITS + 5 + `NW_BITS), + .DATAW (`LOG2UP(`DCREQ_SIZE) + 32 + 2 + (`NUM_THREADS * 2) + `BYTE_EN_BITS + 5 + `NW_BITS), .SIZE (`DCREQ_SIZE) ) mem_req_queue ( .clk (clk), .reset (reset), - .write_data ({mrq_write_addr, use_pc, use_wb, mem_req_offset, use_mem_read, use_rd, use_warp_num}), + .write_data ({mrq_write_addr, use_pc, use_wb, use_req_offset, use_mem_read, use_rd, use_warp_num}), .write_addr (mrq_write_addr), .push (mrq_push), .full (mrq_full), .pop (mrq_pop), .read_addr (mrq_read_addr), - .read_data ({dbg_mrq_write_addr, mem_wb_if.curr_PC, mem_wb_if.wb, mem_rsp_offset, core_rsp_mem_read, mem_wb_if.rd, mem_wb_if.warp_num}), + .read_data ({dbg_mrq_write_addr, mem_wb_unqual_if.curr_PC, mem_wb_unqual_if.wb, mem_rsp_offset, core_rsp_mem_read, mem_wb_unqual_if.rd, mem_wb_unqual_if.warp_num}), `UNUSED_PIN (empty) ); @@ -122,80 +128,80 @@ module VX_lsu_unit #( // Core Request - assign dcache_req_if.core_req_valid = use_valid & {`NUM_THREADS{~mrq_full}}; - assign dcache_req_if.core_req_rw = {`NUM_THREADS{core_req_rw}}; - assign dcache_req_if.core_req_byteen= mem_req_byteen; - assign dcache_req_if.core_req_addr = mem_req_addr; - assign dcache_req_if.core_req_data = mem_req_data; + assign dcache_req_if.valid = use_valid & {`NUM_THREADS{~mrq_full}}; + assign dcache_req_if.rw = {`NUM_THREADS{use_req_rw}}; + assign dcache_req_if.byteen = use_req_byteen; + assign dcache_req_if.addr = use_req_addr; + assign dcache_req_if.data = use_req_data; `ifdef DBG_CORE_REQ_INFO - assign dcache_req_if.core_req_tag = {use_pc, use_wb, use_rd, use_warp_num, mrq_write_addr}; + assign dcache_req_if.tag = {use_pc, use_wb, use_rd, use_warp_num, mrq_write_addr}; `else - assign dcache_req_if.core_req_tag = mrq_write_addr; + assign dcache_req_if.tag = mrq_write_addr; `endif // Can't accept new request - assign delay = mrq_full || !dcache_req_if.core_req_ready; + assign delay = mrq_full || !dcache_req_if.ready; // Core Response reg [`NUM_THREADS-1:0][31:0] core_rsp_data; wire [`NUM_THREADS-1:0][31:0] rsp_data_shifted; - for (i = 0; i < `NUM_THREADS; ++i) begin - assign rsp_data_shifted[i] = (dcache_rsp_if.core_rsp_data[i] >> mem_rsp_offset[i]); + for (i = 0; i < `NUM_THREADS; i++) begin + assign rsp_data_shifted[i] = dcache_rsp_if.data[i] >> {mem_rsp_offset[i], 3'b0}; always @(*) begin case (core_rsp_mem_read) - `BYTE_EN_SB: core_rsp_data[i] = rsp_data_shifted[i][7] ? (rsp_data_shifted[i] | 32'hFFFFFF00) : (rsp_data_shifted[i] & 32'h000000FF); - `BYTE_EN_SH: core_rsp_data[i] = rsp_data_shifted[i][15] ? (rsp_data_shifted[i] | 32'hFFFF0000) : (rsp_data_shifted[i] & 32'h0000FFFF); - `BYTE_EN_UB: core_rsp_data[i] = (rsp_data_shifted[i] & 32'h000000FF); - `BYTE_EN_UH: core_rsp_data[i] = (rsp_data_shifted[i] & 32'h0000FFFF); + `BYTE_EN_SB: core_rsp_data[i] = {{24{rsp_data_shifted[i][7]}}, rsp_data_shifted[i][7:0]}; + `BYTE_EN_SH: core_rsp_data[i] = {{16{rsp_data_shifted[i][15]}}, rsp_data_shifted[i][15:0]}; + `BYTE_EN_UB: core_rsp_data[i] = 32'(rsp_data_shifted[i][7:0]); + `BYTE_EN_UH: core_rsp_data[i] = 32'(rsp_data_shifted[i][15:0]); default : core_rsp_data[i] = rsp_data_shifted[i]; endcase end end - assign mem_wb_if.valid = dcache_rsp_if.core_rsp_valid; - assign mem_wb_if.data = core_rsp_data; + assign mem_wb_unqual_if.valid = dcache_rsp_if.valid; + assign mem_wb_unqual_if.data = core_rsp_data; // Can't accept new response - assign dcache_rsp_if.core_rsp_ready = !(no_slot_mem & (|mem_wb_if_p1.valid)); + assign dcache_rsp_if.ready = !(no_slot_mem & (|mem_wb_if.valid)); // From LSU to WB localparam WB_REQ_SIZE = (`NUM_THREADS) + (`NUM_THREADS * 32) + (`NW_BITS) + (5) + (2) + 32; - VX_generic_register #(.N(WB_REQ_SIZE)) lsu_to_wb( + VX_generic_register #(.N(WB_REQ_SIZE)) lsu_to_wb ( .clk (clk), .reset (reset), .stall (no_slot_mem), .flush (1'b0), - .in ({mem_wb_if.valid , mem_wb_if.data , mem_wb_if.warp_num , mem_wb_if.rd , mem_wb_if.wb , mem_wb_if.curr_PC }), - .out ({mem_wb_if_p1.valid, mem_wb_if_p1.data, mem_wb_if_p1.warp_num, mem_wb_if_p1.rd, mem_wb_if_p1.wb, mem_wb_if_p1.curr_PC}) + .in ({mem_wb_unqual_if.valid, mem_wb_unqual_if.data, mem_wb_unqual_if.warp_num, mem_wb_unqual_if.rd, mem_wb_unqual_if.wb, mem_wb_unqual_if.curr_PC}), + .out ({mem_wb_if.valid, mem_wb_if.data, mem_wb_if.warp_num, mem_wb_if.rd, mem_wb_if.wb, mem_wb_if.curr_PC}) ); - `SCOPE_ASSIGN(scope_dcache_req_valid, dcache_req_if.core_req_valid); + `SCOPE_ASSIGN(scope_dcache_req_valid, dcache_req_if.valid); `SCOPE_ASSIGN(scope_dcache_req_warp_num, use_warp_num); `SCOPE_ASSIGN(scope_dcache_req_curr_PC, use_pc); `SCOPE_ASSIGN(scope_dcache_req_addr, use_address); `SCOPE_ASSIGN(scope_dcache_req_rw, core_req_rw); - `SCOPE_ASSIGN(scope_dcache_req_byteen,dcache_req_if.core_req_byteen); - `SCOPE_ASSIGN(scope_dcache_req_data, dcache_req_if.core_req_data); - `SCOPE_ASSIGN(scope_dcache_req_tag, dcache_req_if.core_req_tag); - `SCOPE_ASSIGN(scope_dcache_req_ready, dcache_req_if.core_req_ready); + `SCOPE_ASSIGN(scope_dcache_req_byteen,dcache_req_if.byteen); + `SCOPE_ASSIGN(scope_dcache_req_data, dcache_req_if.data); + `SCOPE_ASSIGN(scope_dcache_req_tag, dcache_req_if.tag); + `SCOPE_ASSIGN(scope_dcache_req_ready, dcache_req_if.ready); - `SCOPE_ASSIGN(scope_dcache_rsp_valid, dcache_rsp_if.core_rsp_valid); - `SCOPE_ASSIGN(scope_dcache_rsp_data, dcache_rsp_if.core_rsp_data); - `SCOPE_ASSIGN(scope_dcache_rsp_tag, dcache_rsp_if.core_rsp_tag); - `SCOPE_ASSIGN(scope_dcache_rsp_ready, dcache_rsp_if.core_rsp_ready); + `SCOPE_ASSIGN(scope_dcache_rsp_valid, dcache_rsp_if.valid); + `SCOPE_ASSIGN(scope_dcache_rsp_data, dcache_rsp_if.data); + `SCOPE_ASSIGN(scope_dcache_rsp_tag, dcache_rsp_if.tag); + `SCOPE_ASSIGN(scope_dcache_rsp_ready, dcache_rsp_if.ready); `ifdef DBG_PRINT_CORE_DCACHE always @(posedge clk) begin - if ((| dcache_req_if.core_req_valid) && dcache_req_if.core_req_ready) begin - $display("%t: D%0d$ req: valid=%b, addr=%0h, tag=%0h, r=%0d, w=%0d, pc=%0h, rd=%0d, warp=%0d, byteen=%0h, data=%0h", - $time, CORE_ID, use_valid, use_address, mrq_write_addr, use_mem_read, use_mem_write, use_pc, use_rd, use_warp_num, mem_req_byteen, mem_req_data); + if ((| dcache_req_if.valid) && dcache_req_if.ready) begin + $display("%t: D%0d$ req: valid=%b, addr=%0h, tag=%0h, rw=%0b, pc=%0h, rd=%0d, warp=%0d, byteen=%0h, data=%0h", + $time, CORE_ID, use_valid, use_address, mrq_write_addr, use_req_rw, use_pc, use_rd, use_warp_num, use_req_byteen, use_req_data); end - if ((| dcache_rsp_if.core_rsp_valid) && dcache_rsp_if.core_rsp_ready) begin + if ((| dcache_rsp_if.valid) && dcache_rsp_if.ready) begin $display("%t: D%0d$ rsp: valid=%b, tag=%0h, pc=%0h, rd=%0d, warp=%0d, data=%0h", - $time, CORE_ID, mem_wb_if.valid, mrq_read_addr, mem_wb_if.curr_PC, mem_wb_if.rd, mem_wb_if.warp_num, mem_wb_if.data); + $time, CORE_ID, mem_wb_unqual_if.valid, mrq_read_addr, mem_wb_unqual_if.curr_PC, mem_wb_unqual_if.rd, mem_wb_unqual_if.warp_num, mem_wb_unqual_if.data); end end `endif diff --git a/hw/rtl/VX_mem_unit.v b/hw/rtl/VX_mem_unit.v index 6b3c3888..af626723 100644 --- a/hw/rtl/VX_mem_unit.v +++ b/hw/rtl/VX_mem_unit.v @@ -41,8 +41,8 @@ module VX_mem_unit # ( ) core_dcache_rsp_qual_if(), core_smem_rsp_if(); // select shared memory address - wire is_smem_addr = (({core_dcache_req_if.core_req_addr[0], 2'b0} - `SHARED_MEM_BASE_ADDR) <= `SCACHE_SIZE); - wire smem_select = (| core_dcache_req_if.core_req_valid) ? is_smem_addr : 0; + wire is_smem_addr = (({core_dcache_req_if.addr[0], 2'b0} - `SHARED_MEM_BASE_ADDR) <= `SCACHE_SIZE); + wire smem_select = (| core_dcache_req_if.valid) ? is_smem_addr : 0; VX_dcache_arb dcache_smem_arb ( .req_select (smem_select), @@ -84,19 +84,19 @@ module VX_mem_unit # ( .reset (reset), // Core request - .core_req_valid (core_smem_req_if.core_req_valid), - .core_req_rw (core_smem_req_if.core_req_rw), - .core_req_byteen (core_smem_req_if.core_req_byteen), - .core_req_addr (core_smem_req_if.core_req_addr), - .core_req_data (core_smem_req_if.core_req_data), - .core_req_tag (core_smem_req_if.core_req_tag), - .core_req_ready (core_smem_req_if.core_req_ready), + .core_req_valid (core_smem_req_if.valid), + .core_req_rw (core_smem_req_if.rw), + .core_req_byteen (core_smem_req_if.byteen), + .core_req_addr (core_smem_req_if.addr), + .core_req_data (core_smem_req_if.data), + .core_req_tag (core_smem_req_if.tag), + .core_req_ready (core_smem_req_if.ready), // Core response - .core_rsp_valid (core_smem_rsp_if.core_rsp_valid), - .core_rsp_data (core_smem_rsp_if.core_rsp_data), - .core_rsp_tag (core_smem_rsp_if.core_rsp_tag), - .core_rsp_ready (core_smem_rsp_if.core_rsp_ready), + .core_rsp_valid (core_smem_rsp_if.valid), + .core_rsp_data (core_smem_rsp_if.data), + .core_rsp_tag (core_smem_rsp_if.tag), + .core_rsp_ready (core_smem_rsp_if.ready), // DRAM request `UNUSED_PIN (dram_req_valid), @@ -169,46 +169,46 @@ module VX_mem_unit # ( .reset (reset), // Core req - .core_req_valid (core_dcache_req_qual_if.core_req_valid), - .core_req_rw (core_dcache_req_qual_if.core_req_rw), - .core_req_byteen (core_dcache_req_qual_if.core_req_byteen), - .core_req_addr (core_dcache_req_qual_if.core_req_addr), - .core_req_data (core_dcache_req_qual_if.core_req_data), - .core_req_tag (core_dcache_req_qual_if.core_req_tag), - .core_req_ready (core_dcache_req_qual_if.core_req_ready), + .core_req_valid (core_dcache_req_qual_if.valid), + .core_req_rw (core_dcache_req_qual_if.rw), + .core_req_byteen (core_dcache_req_qual_if.byteen), + .core_req_addr (core_dcache_req_qual_if.addr), + .core_req_data (core_dcache_req_qual_if.data), + .core_req_tag (core_dcache_req_qual_if.tag), + .core_req_ready (core_dcache_req_qual_if.ready), // Core response - .core_rsp_valid (core_dcache_rsp_qual_if.core_rsp_valid), - .core_rsp_data (core_dcache_rsp_qual_if.core_rsp_data), - .core_rsp_tag (core_dcache_rsp_qual_if.core_rsp_tag), - .core_rsp_ready (core_dcache_rsp_qual_if.core_rsp_ready), + .core_rsp_valid (core_dcache_rsp_qual_if.valid), + .core_rsp_data (core_dcache_rsp_qual_if.data), + .core_rsp_tag (core_dcache_rsp_qual_if.tag), + .core_rsp_ready (core_dcache_rsp_qual_if.ready), // DRAM request - .dram_req_valid (dcache_dram_req_if.dram_req_valid), - .dram_req_rw (dcache_dram_req_if.dram_req_rw), - .dram_req_byteen (dcache_dram_req_if.dram_req_byteen), - .dram_req_addr (dcache_dram_req_if.dram_req_addr), - .dram_req_data (dcache_dram_req_if.dram_req_data), - .dram_req_tag (dcache_dram_req_if.dram_req_tag), - .dram_req_ready (dcache_dram_req_if.dram_req_ready), + .dram_req_valid (dcache_dram_req_if.valid), + .dram_req_rw (dcache_dram_req_if.rw), + .dram_req_byteen (dcache_dram_req_if.byteen), + .dram_req_addr (dcache_dram_req_if.addr), + .dram_req_data (dcache_dram_req_if.data), + .dram_req_tag (dcache_dram_req_if.tag), + .dram_req_ready (dcache_dram_req_if.ready), // DRAM response - .dram_rsp_valid (dcache_dram_rsp_if.dram_rsp_valid), - .dram_rsp_data (dcache_dram_rsp_if.dram_rsp_data), - .dram_rsp_tag (dcache_dram_rsp_if.dram_rsp_tag), - .dram_rsp_ready (dcache_dram_rsp_if.dram_rsp_ready), + .dram_rsp_valid (dcache_dram_rsp_if.valid), + .dram_rsp_data (dcache_dram_rsp_if.data), + .dram_rsp_tag (dcache_dram_rsp_if.tag), + .dram_rsp_ready (dcache_dram_rsp_if.ready), // Snoop request - .snp_req_valid (dcache_snp_req_if.snp_req_valid), - .snp_req_addr (dcache_snp_req_if.snp_req_addr), - .snp_req_invalidate (dcache_snp_req_if.snp_req_invalidate), - .snp_req_tag (dcache_snp_req_if.snp_req_tag), - .snp_req_ready (dcache_snp_req_if.snp_req_ready), + .snp_req_valid (dcache_snp_req_if.valid), + .snp_req_addr (dcache_snp_req_if.addr), + .snp_req_invalidate (dcache_snp_req_if.invalidate), + .snp_req_tag (dcache_snp_req_if.tag), + .snp_req_ready (dcache_snp_req_if.ready), // Snoop response - .snp_rsp_valid (dcache_snp_rsp_if.snp_rsp_valid), - .snp_rsp_tag (dcache_snp_rsp_if.snp_rsp_tag), - .snp_rsp_ready (dcache_snp_rsp_if.snp_rsp_ready), + .snp_rsp_valid (dcache_snp_rsp_if.valid), + .snp_rsp_tag (dcache_snp_rsp_if.tag), + .snp_rsp_ready (dcache_snp_rsp_if.ready), // Snoop forward out `UNUSED_PIN (snp_fwdout_valid), @@ -253,34 +253,34 @@ module VX_mem_unit # ( .reset (reset), // Core request - .core_req_valid (core_icache_req_if.core_req_valid), - .core_req_rw (core_icache_req_if.core_req_rw), - .core_req_byteen (core_icache_req_if.core_req_byteen), - .core_req_addr (core_icache_req_if.core_req_addr), - .core_req_data (core_icache_req_if.core_req_data), - .core_req_tag (core_icache_req_if.core_req_tag), - .core_req_ready (core_icache_req_if.core_req_ready), + .core_req_valid (core_icache_req_if.valid), + .core_req_rw (core_icache_req_if.rw), + .core_req_byteen (core_icache_req_if.byteen), + .core_req_addr (core_icache_req_if.addr), + .core_req_data (core_icache_req_if.data), + .core_req_tag (core_icache_req_if.tag), + .core_req_ready (core_icache_req_if.ready), // Core response - .core_rsp_valid (core_icache_rsp_if.core_rsp_valid), - .core_rsp_data (core_icache_rsp_if.core_rsp_data), - .core_rsp_tag (core_icache_rsp_if.core_rsp_tag), - .core_rsp_ready (core_icache_rsp_if.core_rsp_ready), + .core_rsp_valid (core_icache_rsp_if.valid), + .core_rsp_data (core_icache_rsp_if.data), + .core_rsp_tag (core_icache_rsp_if.tag), + .core_rsp_ready (core_icache_rsp_if.ready), // DRAM Req - .dram_req_valid (icache_dram_req_if.dram_req_valid), - .dram_req_rw (icache_dram_req_if.dram_req_rw), - .dram_req_byteen (icache_dram_req_if.dram_req_byteen), - .dram_req_addr (icache_dram_req_if.dram_req_addr), - .dram_req_data (icache_dram_req_if.dram_req_data), - .dram_req_tag (icache_dram_req_if.dram_req_tag), - .dram_req_ready (icache_dram_req_if.dram_req_ready), + .dram_req_valid (icache_dram_req_if.valid), + .dram_req_rw (icache_dram_req_if.rw), + .dram_req_byteen (icache_dram_req_if.byteen), + .dram_req_addr (icache_dram_req_if.addr), + .dram_req_data (icache_dram_req_if.data), + .dram_req_tag (icache_dram_req_if.tag), + .dram_req_ready (icache_dram_req_if.ready), // DRAM response - .dram_rsp_valid (icache_dram_rsp_if.dram_rsp_valid), - .dram_rsp_data (icache_dram_rsp_if.dram_rsp_data), - .dram_rsp_tag (icache_dram_rsp_if.dram_rsp_tag), - .dram_rsp_ready (icache_dram_rsp_if.dram_rsp_ready), + .dram_rsp_valid (icache_dram_rsp_if.valid), + .dram_rsp_data (icache_dram_rsp_if.data), + .dram_rsp_tag (icache_dram_rsp_if.tag), + .dram_rsp_ready (icache_dram_rsp_if.ready), // Snoop request .snp_req_valid (0), diff --git a/hw/rtl/VX_pipeline.v b/hw/rtl/VX_pipeline.v index 2a5271c9..72c6ee2d 100644 --- a/hw/rtl/VX_pipeline.v +++ b/hw/rtl/VX_pipeline.v @@ -40,7 +40,19 @@ module VX_pipeline #( input wire icache_rsp_valid, input wire [31:0] icache_rsp_data, input wire [`ICORE_TAG_WIDTH-1:0] icache_rsp_tag, - output wire icache_rsp_ready, + output wire icache_rsp_ready, + + // CSR I/O Request + input wire csr_io_req_valid, + input wire[11:0] csr_io_req_addr, + input wire csr_io_req_rw, + input wire[31:0] csr_io_req_data, + output wire csr_io_req_ready, + + // CSR I/O Response + output wire csr_io_rsp_valid, + output wire[31:0] csr_io_rsp_data, + input wire csr_io_rsp_ready, // Status output wire busy, @@ -86,6 +98,20 @@ module VX_pipeline #( .CORE_TAG_ID_BITS(`ICORE_TAG_ID_BITS) ) core_icache_rsp_if(); + + // CSR I/O + VX_csr_io_req_if csr_io_req_if(); + assign csr_io_req_if.valid = csr_io_req_valid; + assign csr_io_req_if.rw = csr_io_req_rw; + assign csr_io_req_if.addr = csr_io_req_addr; + assign csr_io_req_if.data = csr_io_req_data; + assign csr_io_req_ready = csr_io_req_if.ready; + + VX_csr_io_rsp_if csr_io_rsp_if(); + assign csr_io_rsp_valid = csr_io_rsp_if.valid; + assign csr_io_rsp_data = csr_io_rsp_if.data; + assign csr_io_rsp_if.ready = csr_io_rsp_ready; + // Front-end to Back-end VX_backend_req_if bckE_req_if(); @@ -134,6 +160,8 @@ module VX_pipeline #( .clk (clk), .reset (reset), + .csr_io_req_if (csr_io_req_if), + .csr_io_rsp_if (csr_io_rsp_if), .schedule_delay (schedule_delay), .warp_ctl_if (warp_ctl_if), .bckE_req_if (bckE_req_if), @@ -148,31 +176,31 @@ module VX_pipeline #( .ebreak (ebreak) ); - assign dcache_req_valid = core_dcache_req_if.core_req_valid; - assign dcache_req_rw = core_dcache_req_if.core_req_rw; - assign dcache_req_byteen = core_dcache_req_if.core_req_byteen; - assign dcache_req_addr = core_dcache_req_if.core_req_addr; - assign dcache_req_data = core_dcache_req_if.core_req_data; - assign dcache_req_tag = core_dcache_req_if.core_req_tag; - assign core_dcache_req_if.core_req_ready = dcache_req_ready; + assign dcache_req_valid = core_dcache_req_if.valid; + assign dcache_req_rw = core_dcache_req_if.rw; + assign dcache_req_byteen = core_dcache_req_if.byteen; + assign dcache_req_addr = core_dcache_req_if.addr; + assign dcache_req_data = core_dcache_req_if.data; + assign dcache_req_tag = core_dcache_req_if.tag; + assign core_dcache_req_if.ready = dcache_req_ready; - assign core_dcache_rsp_if.core_rsp_valid = dcache_rsp_valid; - assign core_dcache_rsp_if.core_rsp_data = dcache_rsp_data; - assign core_dcache_rsp_if.core_rsp_tag = dcache_rsp_tag; - assign dcache_rsp_ready = core_dcache_rsp_if.core_rsp_ready; + assign core_dcache_rsp_if.valid = dcache_rsp_valid; + assign core_dcache_rsp_if.data = dcache_rsp_data; + assign core_dcache_rsp_if.tag = dcache_rsp_tag; + assign dcache_rsp_ready = core_dcache_rsp_if.ready; - assign icache_req_valid = core_icache_req_if.core_req_valid; - assign icache_req_rw = core_icache_req_if.core_req_rw; - assign icache_req_byteen = core_icache_req_if.core_req_byteen; - assign icache_req_addr = core_icache_req_if.core_req_addr; - assign icache_req_data = core_icache_req_if.core_req_data; - assign icache_req_tag = core_icache_req_if.core_req_tag; - assign core_icache_req_if.core_req_ready = icache_req_ready; + assign icache_req_valid = core_icache_req_if.valid; + assign icache_req_rw = core_icache_req_if.rw; + assign icache_req_byteen = core_icache_req_if.byteen; + assign icache_req_addr = core_icache_req_if.addr; + assign icache_req_data = core_icache_req_if.data; + assign icache_req_tag = core_icache_req_if.tag; + assign core_icache_req_if.ready = icache_req_ready; - assign core_icache_rsp_if.core_rsp_valid = icache_rsp_valid; - assign core_icache_rsp_if.core_rsp_data = icache_rsp_data; - assign core_icache_rsp_if.core_rsp_tag = icache_rsp_tag; - assign icache_rsp_ready = core_icache_rsp_if.core_rsp_ready; + assign core_icache_rsp_if.valid = icache_rsp_valid; + assign core_icache_rsp_if.data = icache_rsp_data; + assign core_icache_rsp_if.tag = icache_rsp_tag; + assign icache_rsp_ready = core_icache_rsp_if.ready; `SCOPE_ASSIGN(scope_busy, busy); `SCOPE_ASSIGN(scope_schedule_delay, schedule_delay); @@ -191,4 +219,4 @@ module VX_pipeline #( end `endif -endmodule \ No newline at end of file +endmodule diff --git a/hw/rtl/VX_scheduler.v b/hw/rtl/VX_scheduler.v index fb31cbd9..52810bcc 100644 --- a/hw/rtl/VX_scheduler.v +++ b/hw/rtl/VX_scheduler.v @@ -51,6 +51,7 @@ module VX_scheduler ( integer i, w; wire acquire_rd = (| bckE_req_if.valid) && (bckE_req_if.wb != 0) && (bckE_req_if.rd != 0) && !schedule_delay; + wire release_rd = (| writeback_if.valid) && (writeback_if.wb != 0) && (writeback_if.rd != 0); wire [`NUM_THREADS-1:0] valid_wb_new_mask = rename_table[writeback_if.warp_num][writeback_if.rd] & ~writeback_if.valid; diff --git a/hw/rtl/VX_warp.v b/hw/rtl/VX_warp.v index 53e4e549..b780d760 100644 --- a/hw/rtl/VX_warp.v +++ b/hw/rtl/VX_warp.v @@ -9,7 +9,7 @@ module VX_warp ( input wire[`NUM_THREADS-1:0] thread_mask, input wire change_mask, input wire jal, - input wire[31:0] jal_dest, + input wire[31:0] dest, input wire branch_dir, input wire[31:0] branch_dest, input wire wspawn, @@ -43,7 +43,7 @@ module VX_warp ( always @(*) begin if (jal == 1'b1) begin - temp_PC = jal_dest; + temp_PC = dest; end else if (branch_dir) begin temp_PC = branch_dest; end else begin diff --git a/hw/rtl/VX_warp_sched.v b/hw/rtl/VX_warp_sched.v index 6869f3b0..9621d47b 100644 --- a/hw/rtl/VX_warp_sched.v +++ b/hw/rtl/VX_warp_sched.v @@ -1,14 +1,14 @@ `include "VX_define.vh" module VX_warp_sched ( - input wire clk, // Clock - input wire reset, - input wire stall, + input wire clk, + input wire reset, + input wire stall, // Wspawn - input wire wspawn, - input wire[31:0] wsapwn_pc, - input wire[`NUM_WARPS-1:0] wspawn_new_active, + input wire wspawn, + input wire[31:0] wsapwn_pc, + input wire[`NUM_WARPS-1:0] wspawn_new_active, // CTM input wire ctm, @@ -28,38 +28,38 @@ module VX_warp_sched ( // WSTALL input wire wstall, - input wire[`NW_BITS-1:0] wstall_warp_num, + input wire [`NW_BITS-1:0] wstall_warp_num, // Split input wire is_split, input wire dont_split, - input wire[`NUM_THREADS-1:0] split_new_mask, - input wire[`NUM_THREADS-1:0] split_later_mask, - input wire[31:0] split_save_pc, - input wire[`NW_BITS-1:0] split_warp_num, + input wire [`NUM_THREADS-1:0] split_new_mask, + input wire [`NUM_THREADS-1:0] split_later_mask, + input wire [31:0] split_save_pc, + input wire [`NW_BITS-1:0] split_warp_num, // Join input wire is_join, - input wire[`NW_BITS-1:0] join_warp_num, + input wire [`NW_BITS-1:0] join_warp_num, // JAL input wire jal, - input wire[31:0] jal_dest, - input wire[`NW_BITS-1:0] jal_warp_num, + input wire [31:0] dest, + input wire [`NW_BITS-1:0] jal_warp_num, // Branch input wire branch_valid, input wire branch_dir, - input wire[31:0] branch_dest, - input wire[`NW_BITS-1:0] branch_warp_num, + input wire [31:0] branch_dest, + input wire [`NW_BITS-1:0] branch_warp_num, - output wire[`NUM_THREADS-1:0] thread_mask, - output wire[`NW_BITS-1:0] warp_num, - output wire[31:0] warp_pc, + output wire [`NUM_THREADS-1:0] thread_mask, + output wire [`NW_BITS-1:0] warp_num, + output wire [31:0] warp_pc, output wire busy, output wire scheduled_warp, - input wire[`NW_BITS-1:0] icache_stage_wid, + input wire [`NW_BITS-1:0] icache_stage_wid, input wire icache_stage_response ); wire update_use_wspawn; @@ -203,24 +203,24 @@ module VX_warp_sched ( // Jal if (jal) begin - warp_pcs[jal_warp_num] <= jal_dest; + warp_pcs[jal_warp_num] <= dest; warp_stalled[jal_warp_num] <= 0; end // Branch if (branch_valid) begin - if (branch_dir) warp_pcs[branch_warp_num] <= branch_dest; + if (branch_dir) begin + warp_pcs[branch_warp_num] <= branch_dest; + end warp_stalled[branch_warp_num] <= 0; end // Lock/Release if (scheduled_warp && !stall) begin warp_lock[warp_num] <= 1'b1; - // warp_lock <= {`NUM_WARPS{1'b1}}; end if (icache_stage_response) begin warp_lock[icache_stage_wid] <= 1'b0; - // warp_lock <= {`NUM_WARPS{1'b0}}; end end @@ -282,8 +282,6 @@ module VX_warp_sched ( end endgenerate - // wire should_stall = stall || (jal && (warp_to_schedule == jal_warp_num)) || (branch_dir && (warp_to_schedule == branch_warp_num)); - wire should_jal = (jal && (warp_to_schedule == jal_warp_num)); wire should_bra = (branch_valid && branch_dir && (warp_to_schedule == branch_warp_num)); @@ -308,7 +306,7 @@ module VX_warp_sched ( assign use_active = (count_visible_active != 0) ? visible_active : (warp_active & (~warp_stalled) & (~total_barrier_stall) & (~warp_lock)); // Choosing a warp to schedule - VX_rr_arbiter #( + VX_fixed_arbiter #( .N(`NUM_WARPS) ) choose_schedule ( .clk (clk), diff --git a/hw/rtl/Vortex.v b/hw/rtl/Vortex.v index 09e381a0..dfbf0e4a 100644 --- a/hw/rtl/Vortex.v +++ b/hw/rtl/Vortex.v @@ -54,6 +54,19 @@ module Vortex ( input wire [`VX_CORE_TAG_WIDTH-1:0] io_rsp_tag, output wire io_rsp_ready, + // CSR I/O Request + input wire csr_io_req_valid, + input wire [`VX_CSR_ID_WIDTH-1:0] csr_io_req_coreid, + input wire [11:0] csr_io_req_addr, + input wire csr_io_req_rw, + input wire [31:0] csr_io_req_data, + output wire csr_io_req_ready, + + // CSR I/O Response + output wire csr_io_rsp_valid, + output wire [31:0] csr_io_rsp_data, + input wire csr_io_rsp_ready, + // Status output wire busy, output wire ebreak @@ -61,7 +74,7 @@ module Vortex ( if (`NUM_CLUSTERS == 1) begin VX_cluster #( - .CLUSTER_ID(`L3CACHE_ID) + .CLUSTER_ID(0) ) cluster ( `SCOPE_SIGNALS_ISTAGE_BIND `SCOPE_SIGNALS_LSU_BIND @@ -109,50 +122,74 @@ module Vortex ( .io_rsp_tag (io_rsp_tag), .io_rsp_ready (io_rsp_ready), + .csr_io_req_valid (csr_io_req_valid), + .csr_io_req_coreid (csr_io_req_coreid), + .csr_io_req_rw (csr_io_req_rw), + .csr_io_req_addr (csr_io_req_addr), + .csr_io_req_data (csr_io_req_data), + .csr_io_req_ready (csr_io_req_ready), + + .csr_io_rsp_valid (csr_io_rsp_valid), + .csr_io_rsp_data (csr_io_rsp_data), + .csr_io_rsp_ready (csr_io_rsp_ready), + .busy (busy), .ebreak (ebreak) ); end else begin - wire [`NUM_CLUSTERS-1:0] per_cluster_dram_req_valid; - wire [`NUM_CLUSTERS-1:0] per_cluster_dram_req_rw; - wire [`NUM_CLUSTERS-1:0][`L2DRAM_BYTEEN_WIDTH-1:0] per_cluster_dram_req_byteen; - wire [`NUM_CLUSTERS-1:0][`L2DRAM_ADDR_WIDTH-1:0] per_cluster_dram_req_addr; - wire [`NUM_CLUSTERS-1:0][`L2DRAM_LINE_WIDTH-1:0] per_cluster_dram_req_data; - wire [`NUM_CLUSTERS-1:0][`L2DRAM_TAG_WIDTH-1:0] per_cluster_dram_req_tag; - wire l3_core_req_ready; + wire per_cluster_dram_req_valid [`NUM_CLUSTERS-1:0]; + wire per_cluster_dram_req_rw [`NUM_CLUSTERS-1:0]; + wire [`L2DRAM_BYTEEN_WIDTH-1:0] per_cluster_dram_req_byteen [`NUM_CLUSTERS-1:0]; + wire [`L2DRAM_ADDR_WIDTH-1:0] per_cluster_dram_req_addr [`NUM_CLUSTERS-1:0]; + wire [`L2DRAM_LINE_WIDTH-1:0] per_cluster_dram_req_data [`NUM_CLUSTERS-1:0]; + wire [`L2DRAM_TAG_WIDTH-1:0] per_cluster_dram_req_tag [`NUM_CLUSTERS-1:0]; + wire l3_core_req_ready; - wire [`NUM_CLUSTERS-1:0] per_cluster_dram_rsp_valid; - wire [`NUM_CLUSTERS-1:0][`L3DRAM_LINE_WIDTH-1:0] per_cluster_dram_rsp_data; - wire [`NUM_CLUSTERS-1:0][`L3DRAM_TAG_WIDTH-1:0] per_cluster_dram_rsp_tag; - wire [`NUM_CLUSTERS-1:0] per_cluster_dram_rsp_ready; + wire per_cluster_dram_rsp_valid [`NUM_CLUSTERS-1:0]; + wire [`L2DRAM_LINE_WIDTH-1:0] per_cluster_dram_rsp_data [`NUM_CLUSTERS-1:0]; + wire [`L2DRAM_TAG_WIDTH-1:0] per_cluster_dram_rsp_tag [`NUM_CLUSTERS-1:0]; + wire per_cluster_dram_rsp_ready [`NUM_CLUSTERS-1:0]; - wire [`NUM_CLUSTERS-1:0] per_cluster_snp_req_valid; - wire [`NUM_CLUSTERS-1:0][`L2DRAM_ADDR_WIDTH-1:0] per_cluster_snp_req_addr; - wire [`NUM_CLUSTERS-1:0] per_cluster_snp_req_invalidate; - wire [`NUM_CLUSTERS-1:0][`L2SNP_TAG_WIDTH-1:0] per_cluster_snp_req_tag; - wire [`NUM_CLUSTERS-1:0] per_cluster_snp_req_ready; + wire per_cluster_snp_req_valid [`NUM_CLUSTERS-1:0]; + wire [`L2DRAM_ADDR_WIDTH-1:0] per_cluster_snp_req_addr [`NUM_CLUSTERS-1:0]; + wire per_cluster_snp_req_invalidate [`NUM_CLUSTERS-1:0]; + wire [`L2SNP_TAG_WIDTH-1:0] per_cluster_snp_req_tag [`NUM_CLUSTERS-1:0]; + wire per_cluster_snp_req_ready [`NUM_CLUSTERS-1:0]; - wire [`NUM_CLUSTERS-1:0] per_cluster_snp_rsp_valid; - wire [`NUM_CLUSTERS-1:0][`L2SNP_TAG_WIDTH-1:0] per_cluster_snp_rsp_tag; - wire [`NUM_CLUSTERS-1:0] per_cluster_snp_rsp_ready; + wire per_cluster_snp_rsp_valid [`NUM_CLUSTERS-1:0]; + wire [`L2SNP_TAG_WIDTH-1:0] per_cluster_snp_rsp_tag [`NUM_CLUSTERS-1:0]; + wire per_cluster_snp_rsp_ready [`NUM_CLUSTERS-1:0]; - wire [`NUM_CLUSTERS-1:0] per_cluster_io_req_valid; - wire [`NUM_CLUSTERS-1:0] per_cluster_io_req_rw; - wire [`NUM_CLUSTERS-1:0][3:0] per_cluster_io_req_byteen; - wire [`NUM_CLUSTERS-1:0][29:0] per_cluster_io_req_addr; - wire [`NUM_CLUSTERS-1:0][31:0] per_cluster_io_req_data; - wire [`NUM_CLUSTERS-1:0][`L2CORE_TAG_WIDTH-1:0] per_cluster_io_req_tag; - wire [`NUM_CLUSTERS-1:0] per_cluster_io_req_ready; + wire per_cluster_io_req_valid [`NUM_CLUSTERS-1:0]; + wire per_cluster_io_req_rw [`NUM_CLUSTERS-1:0]; + wire [3:0] per_cluster_io_req_byteen [`NUM_CLUSTERS-1:0]; + wire [29:0] per_cluster_io_req_addr [`NUM_CLUSTERS-1:0]; + wire [31:0] per_cluster_io_req_data [`NUM_CLUSTERS-1:0]; + wire [`L2CORE_TAG_WIDTH-1:0] per_cluster_io_req_tag [`NUM_CLUSTERS-1:0]; + wire per_cluster_io_req_ready [`NUM_CLUSTERS-1:0]; - wire [`NUM_CLUSTERS-1:0] per_cluster_io_rsp_valid; - wire [`NUM_CLUSTERS-1:0][`L2CORE_TAG_WIDTH-1:0] per_cluster_io_rsp_tag; - wire [`NUM_CLUSTERS-1:0][31:0] per_cluster_io_rsp_data; - wire [`NUM_CLUSTERS-1:0] per_cluster_io_rsp_ready; + wire per_cluster_io_rsp_valid [`NUM_CLUSTERS-1:0]; + wire [`L2CORE_TAG_WIDTH-1:0] per_cluster_io_rsp_tag [`NUM_CLUSTERS-1:0]; + wire [31:0] per_cluster_io_rsp_data [`NUM_CLUSTERS-1:0]; + wire per_cluster_io_rsp_ready [`NUM_CLUSTERS-1:0]; - wire [`NUM_CLUSTERS-1:0] per_cluster_busy; - wire [`NUM_CLUSTERS-1:0] per_cluster_ebreak; + wire per_cluster_csr_io_req_valid [`NUM_CLUSTERS-1:0]; + wire [11:0] per_cluster_csr_io_req_addr [`NUM_CLUSTERS-1:0]; + wire per_cluster_csr_io_req_rw [`NUM_CLUSTERS-1:0]; + wire [31:0] per_cluster_csr_io_req_data [`NUM_CLUSTERS-1:0]; + wire per_cluster_csr_io_req_ready [`NUM_CLUSTERS-1:0]; + + wire per_cluster_csr_io_rsp_valid [`NUM_CLUSTERS-1:0]; + wire [31:0] per_cluster_csr_io_rsp_data [`NUM_CLUSTERS-1:0]; + wire per_cluster_csr_io_rsp_ready [`NUM_CLUSTERS-1:0]; + + wire per_cluster_busy [`NUM_CLUSTERS-1:0]; + wire per_cluster_ebreak [`NUM_CLUSTERS-1:0]; + + wire [`CLOG2(`NUM_CLUSTERS)-1:0] csr_io_request_id = `CLOG2(`NUM_CLUSTERS)'(csr_io_req_coreid >> `CLOG2(`NUM_CLUSTERS)); + wire [`NC_BITS-1:0] per_cluster_csr_io_req_coreid = `NC_BITS'(csr_io_req_coreid); genvar i; for (i = 0; i < `NUM_CLUSTERS; i++) begin @@ -205,6 +242,17 @@ module Vortex ( .io_rsp_tag (per_cluster_io_rsp_tag [i]), .io_rsp_ready (per_cluster_io_rsp_ready [i]), + .csr_io_req_valid (per_cluster_csr_io_req_valid[i]), + .csr_io_req_coreid (per_cluster_csr_io_req_coreid), + .csr_io_req_rw (per_cluster_csr_io_req_rw [i]), + .csr_io_req_addr (per_cluster_csr_io_req_addr[i]), + .csr_io_req_data (per_cluster_csr_io_req_data[i]), + .csr_io_req_ready (per_cluster_csr_io_req_ready[i]), + + .csr_io_rsp_valid (per_cluster_csr_io_rsp_valid[i]), + .csr_io_rsp_data (per_cluster_csr_io_rsp_data[i]), + .csr_io_rsp_ready (per_cluster_csr_io_rsp_ready[i]), + .busy (per_cluster_busy [i]), .ebreak (per_cluster_ebreak [i]) ); @@ -216,38 +264,71 @@ module Vortex ( .TAG_IN_WIDTH (`L2CORE_TAG_WIDTH), .TAG_OUT_WIDTH (`L3CORE_TAG_WIDTH) ) io_arb ( - .clk (clk), - .reset (reset), + .clk (clk), + .reset (reset), // input requests - .in_mem_req_valid (per_cluster_io_req_valid), - .in_mem_req_rw (per_cluster_io_req_rw), - .in_mem_req_byteen (per_cluster_io_req_byteen), - .in_mem_req_addr (per_cluster_io_req_addr), - .in_mem_req_data (per_cluster_io_req_data), - .in_mem_req_tag (per_cluster_io_req_tag), - .in_mem_req_ready (per_cluster_io_req_ready), + .in_mem_req_valid (per_cluster_io_req_valid), + .in_mem_req_rw (per_cluster_io_req_rw), + .in_mem_req_byteen (per_cluster_io_req_byteen), + .in_mem_req_addr (per_cluster_io_req_addr), + .in_mem_req_data (per_cluster_io_req_data), + .in_mem_req_tag (per_cluster_io_req_tag), + .in_mem_req_ready (per_cluster_io_req_ready), // input responses - .in_mem_rsp_valid (per_cluster_io_rsp_valid), - .in_mem_rsp_data (per_cluster_io_rsp_data), - .in_mem_rsp_tag (per_cluster_io_rsp_tag), - .in_mem_rsp_ready (per_cluster_io_rsp_ready), + .in_mem_rsp_valid (per_cluster_io_rsp_valid), + .in_mem_rsp_data (per_cluster_io_rsp_data), + .in_mem_rsp_tag (per_cluster_io_rsp_tag), + .in_mem_rsp_ready (per_cluster_io_rsp_ready), // output request - .out_mem_req_valid (io_req_valid), - .out_mem_req_rw (io_req_rw), - .out_mem_req_byteen (io_req_byteen), - .out_mem_req_addr (io_req_addr), - .out_mem_req_data (io_req_data), - .out_mem_req_tag (io_req_tag), - .out_mem_req_ready (io_req_ready), + .out_mem_req_valid (io_req_valid), + .out_mem_req_rw (io_req_rw), + .out_mem_req_byteen (io_req_byteen), + .out_mem_req_addr (io_req_addr), + .out_mem_req_data (io_req_data), + .out_mem_req_tag (io_req_tag), + .out_mem_req_ready (io_req_ready), // output response - .out_mem_rsp_valid (io_rsp_valid), - .out_mem_rsp_tag (io_rsp_tag), - .out_mem_rsp_data (io_rsp_data), - .out_mem_rsp_ready (io_rsp_ready) + .out_mem_rsp_valid (io_rsp_valid), + .out_mem_rsp_tag (io_rsp_tag), + .out_mem_rsp_data (io_rsp_data), + .out_mem_rsp_ready (io_rsp_ready) + ); + + VX_csr_io_arb #( + .NUM_REQUESTS (`NUM_CLUSTERS) + ) csr_io_arb ( + .clk (clk), + .reset (reset), + + .request_id (csr_io_request_id), + + // input requests + .in_csr_io_req_valid (csr_io_req_valid), + .in_csr_io_req_addr (csr_io_req_addr), + .in_csr_io_req_rw (csr_io_req_rw), + .in_csr_io_req_data (csr_io_req_data), + .in_csr_io_req_ready (csr_io_req_ready), + + // input responses + .in_csr_io_rsp_valid (per_cluster_csr_io_rsp_valid), + .in_csr_io_rsp_data (per_cluster_csr_io_rsp_data), + .in_csr_io_rsp_ready (per_cluster_csr_io_rsp_ready), + + // output request + .out_csr_io_req_valid (per_cluster_csr_io_req_valid), + .out_csr_io_req_addr (per_cluster_csr_io_req_addr), + .out_csr_io_req_rw (per_cluster_csr_io_req_rw), + .out_csr_io_req_data (per_cluster_csr_io_req_data), + .out_csr_io_req_ready (per_cluster_csr_io_req_ready), + + // output response + .out_csr_io_rsp_valid (csr_io_rsp_valid), + .out_csr_io_rsp_data (csr_io_rsp_data), + .out_csr_io_rsp_ready (csr_io_rsp_ready) ); assign busy = (| per_cluster_busy); @@ -255,27 +336,27 @@ module Vortex ( // L3 Cache /////////////////////////////////////////////////////////// - wire [`L3NUM_REQUESTS-1:0] l3_core_req_valid; - wire [`L3NUM_REQUESTS-1:0] l3_core_req_rw; - wire [`L3NUM_REQUESTS-1:0][`L2DRAM_BYTEEN_WIDTH-1:0] l3_core_req_byteen; - wire [`L3NUM_REQUESTS-1:0][`L2DRAM_ADDR_WIDTH-1:0] l3_core_req_addr; - wire [`L3NUM_REQUESTS-1:0][`L2DRAM_LINE_WIDTH-1:0] l3_core_req_data; - wire [`L3NUM_REQUESTS-1:0][`L2DRAM_TAG_WIDTH-1:0] l3_core_req_tag; + wire l3_core_req_valid [`L3NUM_REQUESTS-1:0]; + wire l3_core_req_rw [`L3NUM_REQUESTS-1:0]; + wire [`L2DRAM_BYTEEN_WIDTH-1:0] l3_core_req_byteen [`L3NUM_REQUESTS-1:0]; + wire [`L2DRAM_ADDR_WIDTH-1:0] l3_core_req_addr [`L3NUM_REQUESTS-1:0]; + wire [`L2DRAM_LINE_WIDTH-1:0] l3_core_req_data [`L3NUM_REQUESTS-1:0]; + wire [`L2DRAM_TAG_WIDTH-1:0] l3_core_req_tag [`L3NUM_REQUESTS-1:0]; - wire [`L3NUM_REQUESTS-1:0] l3_core_rsp_valid; - wire [`L3NUM_REQUESTS-1:0][`L2DRAM_LINE_WIDTH-1:0] l3_core_rsp_data; - wire [`L3NUM_REQUESTS-1:0][`L2DRAM_TAG_WIDTH-1:0] l3_core_rsp_tag; - wire l3_core_rsp_ready; + wire l3_core_rsp_valid [`L3NUM_REQUESTS-1:0]; + wire [`L2DRAM_LINE_WIDTH-1:0] l3_core_rsp_data [`L3NUM_REQUESTS-1:0]; + wire [`L2DRAM_TAG_WIDTH-1:0] l3_core_rsp_tag [`L3NUM_REQUESTS-1:0]; + wire l3_core_rsp_ready; - wire [`NUM_CLUSTERS-1:0] l3_snp_fwdout_valid; - wire [`NUM_CLUSTERS-1:0][`L2DRAM_ADDR_WIDTH-1:0] l3_snp_fwdout_addr; - wire [`NUM_CLUSTERS-1:0] l3_snp_fwdout_invalidate; - wire [`NUM_CLUSTERS-1:0][`L2SNP_TAG_WIDTH-1:0] l3_snp_fwdout_tag; - wire [`NUM_CLUSTERS-1:0] l3_snp_fwdout_ready; + wire l3_snp_fwdout_valid [`NUM_CLUSTERS-1:0]; + wire [`L2DRAM_ADDR_WIDTH-1:0] l3_snp_fwdout_addr [`NUM_CLUSTERS-1:0]; + wire l3_snp_fwdout_invalidate [`NUM_CLUSTERS-1:0]; + wire [`L2SNP_TAG_WIDTH-1:0] l3_snp_fwdout_tag [`NUM_CLUSTERS-1:0]; + wire l3_snp_fwdout_ready [`NUM_CLUSTERS-1:0]; - wire [`NUM_CLUSTERS-1:0] l3_snp_fwdin_valid; - wire [`NUM_CLUSTERS-1:0][`L2SNP_TAG_WIDTH-1:0] l3_snp_fwdin_tag; - wire [`NUM_CLUSTERS-1:0] l3_snp_fwdin_ready; + wire l3_snp_fwdin_valid [`NUM_CLUSTERS-1:0]; + wire [`L2SNP_TAG_WIDTH-1:0] l3_snp_fwdin_tag [`NUM_CLUSTERS-1:0]; + wire l3_snp_fwdin_ready [`NUM_CLUSTERS-1:0]; for (i = 0; i < `L3NUM_REQUESTS; i++) begin // Core Request diff --git a/hw/rtl/cache/VX_cache_core_rsp_merge.v b/hw/rtl/cache/VX_cache_core_rsp_merge.v index 2f835ce1..849d8907 100644 --- a/hw/rtl/cache/VX_cache_core_rsp_merge.v +++ b/hw/rtl/cache/VX_cache_core_rsp_merge.v @@ -29,12 +29,7 @@ module VX_cache_core_rsp_merge #( input wire core_rsp_ready ); - reg [NUM_BANKS-1:0] per_bank_core_rsp_pop_unqual; - - assign per_bank_core_rsp_ready = per_bank_core_rsp_pop_unqual & {NUM_BANKS{core_rsp_ready}}; - wire [`BANK_BITS-1:0] main_bank_index; - wire grant_valid; VX_fair_arbiter #( .N(NUM_BANKS) ) sel_bank ( @@ -42,10 +37,14 @@ module VX_cache_core_rsp_merge #( .reset (reset), .requests (per_bank_core_rsp_valid), .grant_index (main_bank_index), - .grant_valid (grant_valid), + `UNUSED_PIN (grant_valid), `UNUSED_PIN (grant_onehot) ); + reg [NUM_BANKS-1:0] per_bank_core_rsp_pop_unqual; + + assign per_bank_core_rsp_ready = per_bank_core_rsp_pop_unqual & {NUM_BANKS{core_rsp_ready}}; + integer i; if (CORE_TAG_ID_BITS != 0) begin @@ -54,7 +53,7 @@ module VX_cache_core_rsp_merge #( core_rsp_valid = 0; core_rsp_data = 0; for (i = 0; i < NUM_BANKS; i++) begin - if (grant_valid && per_bank_core_rsp_valid[i] + if (per_bank_core_rsp_valid[i] && (per_bank_core_rsp_tag[i][CORE_TAG_ID_BITS-1:0] == per_bank_core_rsp_tag[main_bank_index][CORE_TAG_ID_BITS-1:0])) begin core_rsp_valid[per_bank_core_rsp_tid[i]] = 1; core_rsp_data[per_bank_core_rsp_tid[i]] = per_bank_core_rsp_data[i]; @@ -70,7 +69,7 @@ module VX_cache_core_rsp_merge #( core_rsp_data = 0; core_rsp_tag = 0; for (i = 0; i < NUM_BANKS; i++) begin - if (grant_valid && per_bank_core_rsp_valid[i] + if (per_bank_core_rsp_valid[i] && !core_rsp_valid[per_bank_core_rsp_tid[i]] && ((main_bank_index == `BANK_BITS'(i)) || (per_bank_core_rsp_tid[i] != per_bank_core_rsp_tid[main_bank_index]))) begin diff --git a/hw/rtl/cache/VX_cache_miss_resrv.v b/hw/rtl/cache/VX_cache_miss_resrv.v index d4e6d5ee..c851629c 100644 --- a/hw/rtl/cache/VX_cache_miss_resrv.v +++ b/hw/rtl/cache/VX_cache_miss_resrv.v @@ -66,7 +66,7 @@ module VX_cache_miss_resrv #( reg [`LOG2UP(MRVQ_SIZE+1)-1:0] size; - `STATIC_ASSERT(MRVQ_SIZE > 5, "invalid size"); + `STATIC_ASSERT(MRVQ_SIZE > 5, "invalid size") assign miss_resrv_full = (size == $bits(size)'(MRVQ_SIZE)); assign miss_resrv_stop = (size > $bits(size)'(MRVQ_SIZE-5)); // need to add 5 cycles to prevent pipeline lock diff --git a/hw/rtl/cache/VX_snp_forwarder.v b/hw/rtl/cache/VX_snp_forwarder.v index 7af7f80c..f54b6eba 100644 --- a/hw/rtl/cache/VX_snp_forwarder.v +++ b/hw/rtl/cache/VX_snp_forwarder.v @@ -37,7 +37,7 @@ module VX_snp_forwarder #( input wire [NUM_REQUESTS-1:0][`LOG2UP(SNRQ_SIZE)-1:0] snp_fwdin_tag, output wire [NUM_REQUESTS-1:0] snp_fwdin_ready ); - `STATIC_ASSERT(NUM_REQUESTS > 1, "invalid value"); + `STATIC_ASSERT(NUM_REQUESTS > 1, "invalid value") reg [`REQS_BITS:0] pending_cntrs [SNRQ_SIZE-1:0]; @@ -88,7 +88,7 @@ module VX_snp_forwarder #( genvar i; for (i = 0; i < NUM_REQUESTS; i++) begin - assign snp_fwdout_valid[i] = snp_req_valid && !sfq_full; + assign snp_fwdout_valid[i] = snp_req_valid && snp_req_ready; assign snp_fwdout_addr[i] = snp_req_addr; assign snp_fwdout_invalidate[i] = snp_req_invalidate; assign snp_fwdout_tag[i] = sfq_write_addr; diff --git a/hw/rtl/interfaces/VX_backend_req_if.v b/hw/rtl/interfaces/VX_backend_req_if.v index 31ab83a8..f153f1b6 100644 --- a/hw/rtl/interfaces/VX_backend_req_if.v +++ b/hw/rtl/interfaces/VX_backend_req_if.v @@ -5,7 +5,10 @@ interface VX_backend_req_if (); - wire [11:0] csr_address; + wire [`NUM_THREADS-1:0] valid; + wire [`NW_BITS-1:0] warp_num; + wire [31:0] curr_PC; + wire [11:0] csr_addr; wire is_csr; wire csr_immed; wire [31:0] csr_mask; @@ -20,14 +23,11 @@ interface VX_backend_req_if (); wire [`BYTE_EN_BITS-1:0] mem_write; wire [2:0] branch_type; wire [19:0] upper_immed; - wire [31:0] curr_PC; wire is_etype; wire is_jal; wire jal; wire [31:0] jal_offset; - wire [31:0] next_PC; - wire [`NUM_THREADS-1:0] valid; - wire [`NW_BITS-1:0] warp_num; + wire [31:0] next_PC; // GPGPU stuff wire is_wspawn; diff --git a/hw/rtl/interfaces/VX_branch_rsp_if.v b/hw/rtl/interfaces/VX_branch_rsp_if.v index 45370ca1..a8f01d44 100644 --- a/hw/rtl/interfaces/VX_branch_rsp_if.v +++ b/hw/rtl/interfaces/VX_branch_rsp_if.v @@ -5,10 +5,10 @@ interface VX_branch_rsp_if (); - wire valid_branch; - wire branch_dir; - wire [31:0] branch_dest; - wire [`NW_BITS-1:0] branch_warp_num; + wire valid; + wire dir; + wire [31:0] dest; + wire [`NW_BITS-1:0] warp_num; endinterface diff --git a/hw/rtl/interfaces/VX_cache_core_req_if.v b/hw/rtl/interfaces/VX_cache_core_req_if.v index 451418d3..57de39f4 100644 --- a/hw/rtl/interfaces/VX_cache_core_req_if.v +++ b/hw/rtl/interfaces/VX_cache_core_req_if.v @@ -10,13 +10,13 @@ interface VX_cache_core_req_if #( parameter CORE_TAG_ID_BITS = 0 ) (); - wire [NUM_REQUESTS-1:0] core_req_valid; - wire [NUM_REQUESTS-1:0] core_req_rw; - wire [NUM_REQUESTS-1:0][WORD_SIZE-1:0] core_req_byteen; - wire [NUM_REQUESTS-1:0][`WORD_ADDR_WIDTH-1:0] core_req_addr; - wire [NUM_REQUESTS-1:0][`WORD_WIDTH-1:0] core_req_data; - wire [`CORE_REQ_TAG_COUNT-1:0][CORE_TAG_WIDTH-1:0] core_req_tag; - wire core_req_ready; + wire [NUM_REQUESTS-1:0] valid; + wire [NUM_REQUESTS-1:0] rw; + wire [NUM_REQUESTS-1:0][WORD_SIZE-1:0] byteen; + wire [NUM_REQUESTS-1:0][`WORD_ADDR_WIDTH-1:0] addr; + wire [NUM_REQUESTS-1:0][`WORD_WIDTH-1:0] data; + wire [`CORE_REQ_TAG_COUNT-1:0][CORE_TAG_WIDTH-1:0] tag; + wire ready; endinterface diff --git a/hw/rtl/interfaces/VX_cache_core_rsp_if.v b/hw/rtl/interfaces/VX_cache_core_rsp_if.v index 7de31217..5b70f5ee 100644 --- a/hw/rtl/interfaces/VX_cache_core_rsp_if.v +++ b/hw/rtl/interfaces/VX_cache_core_rsp_if.v @@ -10,10 +10,10 @@ interface VX_cache_core_rsp_if #( parameter CORE_TAG_ID_BITS = 0 ) (); - wire [NUM_REQUESTS-1:0] core_rsp_valid; - wire [NUM_REQUESTS-1:0][`WORD_WIDTH-1:0] core_rsp_data; - wire [`CORE_REQ_TAG_COUNT-1:0][CORE_TAG_WIDTH-1:0] core_rsp_tag; - wire core_rsp_ready; + wire [NUM_REQUESTS-1:0] valid; + wire [NUM_REQUESTS-1:0][`WORD_WIDTH-1:0] data; + wire [`CORE_REQ_TAG_COUNT-1:0][CORE_TAG_WIDTH-1:0] tag; + wire ready; endinterface diff --git a/hw/rtl/interfaces/VX_cache_dram_req_if.v b/hw/rtl/interfaces/VX_cache_dram_req_if.v index 5de4fefc..d92b9912 100644 --- a/hw/rtl/interfaces/VX_cache_dram_req_if.v +++ b/hw/rtl/interfaces/VX_cache_dram_req_if.v @@ -9,13 +9,13 @@ interface VX_cache_dram_req_if #( parameter DRAM_TAG_WIDTH = 1 ) (); - wire dram_req_valid; - wire dram_req_rw; - wire [(DRAM_LINE_WIDTH/8)-1:0] dram_req_byteen; - wire [DRAM_ADDR_WIDTH-1:0] dram_req_addr; - wire [DRAM_LINE_WIDTH-1:0] dram_req_data; - wire [DRAM_TAG_WIDTH-1:0] dram_req_tag; - wire dram_req_ready; + wire valid; + wire rw; + wire [(DRAM_LINE_WIDTH/8)-1:0] byteen; + wire [DRAM_ADDR_WIDTH-1:0] addr; + wire [DRAM_LINE_WIDTH-1:0] data; + wire [DRAM_TAG_WIDTH-1:0] tag; + wire ready; endinterface diff --git a/hw/rtl/interfaces/VX_cache_dram_rsp_if.v b/hw/rtl/interfaces/VX_cache_dram_rsp_if.v index ac299c27..9e994d3a 100644 --- a/hw/rtl/interfaces/VX_cache_dram_rsp_if.v +++ b/hw/rtl/interfaces/VX_cache_dram_rsp_if.v @@ -8,10 +8,10 @@ interface VX_cache_dram_rsp_if #( parameter DRAM_TAG_WIDTH = 1 ) (); - wire dram_rsp_valid; - wire [DRAM_LINE_WIDTH-1:0] dram_rsp_data; - wire [DRAM_TAG_WIDTH-1:0] dram_rsp_tag; - wire dram_rsp_ready; + wire valid; + wire [DRAM_LINE_WIDTH-1:0] data; + wire [DRAM_TAG_WIDTH-1:0] tag; + wire ready; endinterface diff --git a/hw/rtl/interfaces/VX_cache_snp_req_if.v b/hw/rtl/interfaces/VX_cache_snp_req_if.v index fce768b8..6134b02d 100644 --- a/hw/rtl/interfaces/VX_cache_snp_req_if.v +++ b/hw/rtl/interfaces/VX_cache_snp_req_if.v @@ -8,11 +8,11 @@ interface VX_cache_snp_req_if #( parameter SNP_TAG_WIDTH = 0 ) (); - wire snp_req_valid; - wire [DRAM_ADDR_WIDTH-1:0] snp_req_addr; - wire snp_req_invalidate; - wire [SNP_TAG_WIDTH-1:0] snp_req_tag; - wire snp_req_ready; + wire valid; + wire [DRAM_ADDR_WIDTH-1:0] addr; + wire invalidate; + wire [SNP_TAG_WIDTH-1:0] tag; + wire ready; endinterface diff --git a/hw/rtl/interfaces/VX_cache_snp_rsp_if.v b/hw/rtl/interfaces/VX_cache_snp_rsp_if.v index 12f6f733..a553c48d 100644 --- a/hw/rtl/interfaces/VX_cache_snp_rsp_if.v +++ b/hw/rtl/interfaces/VX_cache_snp_rsp_if.v @@ -7,9 +7,9 @@ interface VX_cache_snp_rsp_if #( parameter SNP_TAG_WIDTH = 0 ) (); - wire snp_rsp_valid; - wire [SNP_TAG_WIDTH-1:0] snp_rsp_tag; - wire snp_rsp_ready; + wire valid; + wire [SNP_TAG_WIDTH-1:0] tag; + wire ready; endinterface diff --git a/hw/rtl/interfaces/VX_csr_io_req_if.v b/hw/rtl/interfaces/VX_csr_io_req_if.v new file mode 100644 index 00000000..ce8d2fed --- /dev/null +++ b/hw/rtl/interfaces/VX_csr_io_req_if.v @@ -0,0 +1,16 @@ +`ifndef VX_CSR_IO_REQ_IF +`define VX_CSR_IO_REQ_IF + +`include "VX_define.vh" + +interface VX_csr_io_req_if (); + + wire valid; + wire rw; + wire [11:0] addr; + wire [31:0] data; + wire ready; + +endinterface + +`endif diff --git a/hw/rtl/interfaces/VX_csr_io_rsp_if.v b/hw/rtl/interfaces/VX_csr_io_rsp_if.v new file mode 100644 index 00000000..7c4c8f6d --- /dev/null +++ b/hw/rtl/interfaces/VX_csr_io_rsp_if.v @@ -0,0 +1,14 @@ +`ifndef VX_CSR_IO_RSP_IF +`define VX_CSR_IO_RSP_IF + +`include "VX_define.vh" + +interface VX_csr_io_rsp_if (); + + wire valid; + wire [31:0] data; + wire ready; + +endinterface + +`endif diff --git a/hw/rtl/interfaces/VX_csr_req_if.v b/hw/rtl/interfaces/VX_csr_req_if.v index 60f5f2c2..6eeddf74 100644 --- a/hw/rtl/interfaces/VX_csr_req_if.v +++ b/hw/rtl/interfaces/VX_csr_req_if.v @@ -11,10 +11,12 @@ interface VX_csr_req_if (); wire [1:0] wb; wire [4:0] alu_op; wire is_csr; - wire [11:0] csr_address; + wire [11:0] csr_addr; wire csr_immed; wire [31:0] csr_mask; + wire is_io; + endinterface -`endif \ No newline at end of file +`endif diff --git a/hw/rtl/interfaces/VX_exec_unit_req_if.v b/hw/rtl/interfaces/VX_exec_unit_req_if.v index b87fe1b0..918cb456 100644 --- a/hw/rtl/interfaces/VX_exec_unit_req_if.v +++ b/hw/rtl/interfaces/VX_exec_unit_req_if.v @@ -38,7 +38,7 @@ interface VX_exec_unit_req_if (); // CSR info wire is_csr; - wire [11:0] csr_address; + wire [11:0] csr_addr; wire csr_immed; wire [31:0] csr_mask; diff --git a/hw/rtl/interfaces/VX_inst_meta_if.v b/hw/rtl/interfaces/VX_inst_meta_if.v index 9cab988f..8ebfa87f 100644 --- a/hw/rtl/interfaces/VX_inst_meta_if.v +++ b/hw/rtl/interfaces/VX_inst_meta_if.v @@ -5,10 +5,10 @@ interface VX_inst_meta_if (); - wire [31:0] instruction; - wire [31:0] inst_pc; - wire [`NW_BITS-1:0] warp_num; wire [`NUM_THREADS-1:0] valid; + wire [31:0] curr_PC; + wire [`NW_BITS-1:0] warp_num; + wire [31:0] instruction; endinterface diff --git a/hw/rtl/interfaces/VX_jal_rsp_if.v b/hw/rtl/interfaces/VX_jal_rsp_if.v index 61e0d73b..3f6796a0 100644 --- a/hw/rtl/interfaces/VX_jal_rsp_if.v +++ b/hw/rtl/interfaces/VX_jal_rsp_if.v @@ -6,9 +6,9 @@ interface VX_jal_rsp_if (); - wire jal; - wire [31:0] jal_dest; - wire [`NW_BITS-1:0] jal_warp_num; + wire valid; + wire [31:0] dest; + wire [`NW_BITS-1:0] warp_num; endinterface diff --git a/hw/rtl/interfaces/VX_join_if.v b/hw/rtl/interfaces/VX_join_if.v index 337fc0c0..bc48bfee 100644 --- a/hw/rtl/interfaces/VX_join_if.v +++ b/hw/rtl/interfaces/VX_join_if.v @@ -7,7 +7,7 @@ interface VX_join_if (); wire is_join; - wire [`NW_BITS-1:0] join_warp_num; + wire [`NW_BITS-1:0] warp_num; endinterface diff --git a/hw/rtl/interfaces/VX_lsu_req_if.v b/hw/rtl/interfaces/VX_lsu_req_if.v index 636b6afd..216853cf 100644 --- a/hw/rtl/interfaces/VX_lsu_req_if.v +++ b/hw/rtl/interfaces/VX_lsu_req_if.v @@ -10,8 +10,8 @@ interface VX_lsu_req_if (); wire [31:0] curr_PC; wire [`NW_BITS-1:0] warp_num; wire [`NUM_THREADS-1:0][31:0] store_data; - wire [`NUM_THREADS-1:0][31:0] base_address; // A reg data - wire [31:0] offset; // itype_immed + wire [`NUM_THREADS-1:0][31:0] base_addr; // A reg data + wire [31:0] offset; // itype_immed wire [`BYTE_EN_BITS-1:0] mem_read; wire [`BYTE_EN_BITS-1:0] mem_write; wire [4:0] rd; // dest register diff --git a/hw/rtl/interfaces/VX_wb_if.v b/hw/rtl/interfaces/VX_wb_if.v index 0d17e4c4..96b8acef 100644 --- a/hw/rtl/interfaces/VX_wb_if.v +++ b/hw/rtl/interfaces/VX_wb_if.v @@ -10,8 +10,9 @@ interface VX_wb_if (); wire [`NW_BITS-1:0] warp_num; wire [4:0] rd; wire [1:0] wb; - wire [31:0] curr_PC; + wire [31:0] curr_PC; + wire is_io; endinterface -`endif \ No newline at end of file +`endif diff --git a/hw/rtl/libs/VX_divide.v b/hw/rtl/libs/VX_divide.v index 09da8dd8..510abf26 100644 --- a/hw/rtl/libs/VX_divide.v +++ b/hw/rtl/libs/VX_divide.v @@ -10,11 +10,11 @@ module VX_divide #( input wire clk, input wire reset, - input [WIDTHN-1:0] numer, - input [WIDTHD-1:0] denom, + input wire [WIDTHN-1:0] numer, + input wire [WIDTHD-1:0] denom, - output reg [WIDTHN-1:0] quotient, - output reg [WIDTHD-1:0] remainder + output wire [WIDTHN-1:0] quotient, + output wire [WIDTHD-1:0] remainder ); `ifdef QUARTUS @@ -35,8 +35,8 @@ module VX_divide #( quartus_div.lpm_widthd = WIDTHD, quartus_div.lpm_nrepresentation = NSIGNED ? "SIGNED" : "UNSIGNED", quartus_div.lpm_drepresentation = DSIGNED ? "SIGNED" : "UNSIGNED", - quartus_div.lpm_hint = "LPM_REMAINDERPOSITIVE=FALSE,MAXIMIZE_SPEED=9", - quartus_div.lpm_pipeline = PIPELINE; + quartus_div.lpm_hint = "MAXIMIZE_SPEED=6,LPM_REMAINDERPOSITIVE=FALSE", + quartus_div.lpm_pipeline = PIPELINE; `else diff --git a/hw/rtl/libs/VX_encoder_onehot.v b/hw/rtl/libs/VX_encoder_onehot.v index e5e06ff0..a4e0e72e 100644 --- a/hw/rtl/libs/VX_encoder_onehot.v +++ b/hw/rtl/libs/VX_encoder_onehot.v @@ -3,20 +3,19 @@ module VX_encoder_onehot #( parameter N = 6 ) ( - input wire [N-1:0] onehot, - output reg valid, - output reg [`LOG2UP(N)-1:0] value + input wire [N-1:0] onehot, + output reg [`LOG2UP(N)-1:0] binary, + output reg valid ); integer i; always @(*) begin valid = 1'b0; - value = {`LOG2UP(N){1'bx}}; + binary = `LOG2UP(N)'(0); for (i = 0; i < N; i++) begin if (onehot[i]) begin valid = 1'b1; - value = `LOG2UP(N)'(i); - break; + binary = `LOG2UP(N)'(i); end end end diff --git a/hw/rtl/libs/VX_fair_arbiter.v b/hw/rtl/libs/VX_fair_arbiter.v index ca32a5fc..9ffc1ecd 100644 --- a/hw/rtl/libs/VX_fair_arbiter.v +++ b/hw/rtl/libs/VX_fair_arbiter.v @@ -1,7 +1,7 @@ `include "VX_define.vh" module VX_fair_arbiter #( - parameter N = 0 + parameter N = 1 ) ( input wire clk, input wire reset, @@ -11,7 +11,6 @@ module VX_fair_arbiter #( output wire grant_valid ); - if (N == 1) begin `UNUSED_VAR (clk) @@ -20,8 +19,7 @@ module VX_fair_arbiter #( assign grant_onehot = requests; assign grant_valid = requests[0]; - end else begin - + end else begin reg [N-1:0] requests_use; wire [N-1:0] update_value; @@ -48,7 +46,7 @@ module VX_fair_arbiter #( reg [N-1:0] grant_onehot_r; - VX_priority_encoder # ( + VX_priority_encoder #( .N(N) ) priority_encoder ( .data_in (requests_use), @@ -61,7 +59,7 @@ module VX_fair_arbiter #( grant_onehot_r[grant_index] = 1; end assign grant_onehot = grant_onehot_r; - assign late_value = ((refill_original ^ requests) & ~refill_original); + assign late_value = ((refill_original ^ requests) & ~refill_original); assign update_value = (requests_use & ~grant_onehot_r) | late_value; end diff --git a/hw/rtl/libs/VX_fixed_arbiter.v b/hw/rtl/libs/VX_fixed_arbiter.v index 0ce69146..7f6fbfa3 100644 --- a/hw/rtl/libs/VX_fixed_arbiter.v +++ b/hw/rtl/libs/VX_fixed_arbiter.v @@ -1,7 +1,7 @@ `include "VX_define.vh" module VX_fixed_arbiter #( - parameter N = 0 + parameter N = 1 ) ( input wire clk, input wire reset, diff --git a/hw/rtl/libs/VX_generic_queue.v b/hw/rtl/libs/VX_generic_queue.v index 52e12831..a666948b 100644 --- a/hw/rtl/libs/VX_generic_queue.v +++ b/hw/rtl/libs/VX_generic_queue.v @@ -1,7 +1,7 @@ `include "VX_define.vh" module VX_generic_queue #( - parameter DATAW, + parameter DATAW = 1, parameter SIZE = 16, parameter BUFFERED_OUTPUT = 1 ) ( @@ -15,7 +15,7 @@ module VX_generic_queue #( output wire full, output wire [`LOG2UP(SIZE+1)-1:0] size ); - `STATIC_ASSERT(`ISPOW2(SIZE), "must be 0 or power of 2!"); + `STATIC_ASSERT(`ISPOW2(SIZE), "must be 0 or power of 2!") reg [`LOG2UP(SIZE+1)-1:0] size_r; wire reading; diff --git a/hw/rtl/libs/VX_generic_register.v b/hw/rtl/libs/VX_generic_register.v index 869efdd4..7234b0a2 100644 --- a/hw/rtl/libs/VX_generic_register.v +++ b/hw/rtl/libs/VX_generic_register.v @@ -1,7 +1,7 @@ `include "VX_define.vh" module VX_generic_register #( - parameter N, + parameter N = 1, parameter PASSTHRU = 0 ) ( input wire clk, diff --git a/hw/rtl/libs/VX_indexable_queue.v b/hw/rtl/libs/VX_indexable_queue.v index b6749e81..886b05f6 100644 --- a/hw/rtl/libs/VX_indexable_queue.v +++ b/hw/rtl/libs/VX_indexable_queue.v @@ -1,8 +1,8 @@ `include "VX_define.vh" module VX_indexable_queue #( - parameter DATAW, - parameter SIZE + parameter DATAW = 1, + parameter SIZE = 1 ) ( input wire clk, input wire reset, diff --git a/hw/rtl/libs/VX_matrix_arbiter.v b/hw/rtl/libs/VX_matrix_arbiter.v index 1d578166..8c467974 100644 --- a/hw/rtl/libs/VX_matrix_arbiter.v +++ b/hw/rtl/libs/VX_matrix_arbiter.v @@ -1,7 +1,7 @@ `include "VX_define.vh" module VX_matrix_arbiter #( - parameter N = 0 + parameter N = 1 ) ( input wire clk, input wire reset, @@ -27,8 +27,8 @@ module VX_matrix_arbiter #( genvar i, j; - for (i = 0; i < N; ++i) begin - for (j = 0; j < N; ++j) begin + for (i = 0; i < N; i++) begin + for (j = 0; j < N; j++) begin if (j > i) begin assign pri[j][i] = requests[i] && state[i][j]; end @@ -43,8 +43,8 @@ module VX_matrix_arbiter #( assign grant_onehot[i] = requests[i] && !(| pri[i]); end - for (i = 0; i < N; ++i) begin - for (j = i + 1; j < N; ++j) begin + for (i = 0; i < N; i++) begin + for (j = i + 1; j < N; j++) begin always @(posedge clk) begin if (reset) begin state[i][j] <= 0; diff --git a/hw/rtl/libs/VX_mult.v b/hw/rtl/libs/VX_mult.v index 466f4213..1dd77aea 100644 --- a/hw/rtl/libs/VX_mult.v +++ b/hw/rtl/libs/VX_mult.v @@ -7,13 +7,12 @@ module VX_mult #( parameter SIGNED = 0, parameter PIPELINE = 0 ) ( - input clk, - input reset, + input wire clk, + input wire reset, - input [WIDTHA-1:0] dataa, - input [WIDTHB-1:0] datab, - - output reg [WIDTHP-1:0] result + input wire [WIDTHA-1:0] dataa, + input wire [WIDTHB-1:0] datab, + output wire [WIDTHP-1:0] result ); `ifdef QUARTUS @@ -23,9 +22,9 @@ module VX_mult #( .dataa (dataa), .datab (datab), .result (result), + .sclr (reset), .aclr (1'b0), .clken (1'b1), - .sclr (1'b0), .sum (1'b0) ); @@ -35,7 +34,7 @@ module VX_mult #( quartus_mult.lpm_widthp = WIDTHP, quartus_mult.lpm_representation = SIGNED ? "SIGNED" : "UNSIGNED", quartus_mult.lpm_pipeline = PIPELINE, - quartus_mult.lpm_hint = "MAXIMIZE_SPEED=9"; + quartus_mult.lpm_hint = "DEDICATED_MULTIPLIER_CIRCUITRY=YES,MAXIMIZE_SPEED=9"; `else wire [WIDTHP-1:0] result_unqual; diff --git a/hw/rtl/libs/VX_priority_encoder.v b/hw/rtl/libs/VX_priority_encoder.v index e98a17d6..24c91724 100644 --- a/hw/rtl/libs/VX_priority_encoder.v +++ b/hw/rtl/libs/VX_priority_encoder.v @@ -1,7 +1,7 @@ `include "VX_define.vh" module VX_priority_encoder #( - parameter N + parameter N = 1 ) ( input wire [N-1:0] data_in, output reg [`LOG2UP(N)-1:0] data_out, diff --git a/hw/rtl/libs/VX_rr_arbiter.v b/hw/rtl/libs/VX_rr_arbiter.v index d093cd60..fb19e108 100644 --- a/hw/rtl/libs/VX_rr_arbiter.v +++ b/hw/rtl/libs/VX_rr_arbiter.v @@ -1,7 +1,7 @@ `include "VX_define.vh" module VX_rr_arbiter #( - parameter N = 0 + parameter N = 1 ) ( input wire clk, input wire reset, @@ -29,9 +29,9 @@ module VX_rr_arbiter #( integer i, j; always @(*) begin - for (i = 0; i < N; ++i) begin + for (i = 0; i < N; i++) begin grant_table[i] = `CLOG2(N)'(i); - for (j = 0; j < N; ++j) begin + for (j = 0; j < N; j++) begin if (requests[(i+j) % N]) begin grant_table[i] = `CLOG2(N)'((i+j) % N); end diff --git a/hw/rtl/pipe_regs/VX_d_e_reg.v b/hw/rtl/pipe_regs/VX_d_e_reg.v deleted file mode 100644 index 35139f4d..00000000 --- a/hw/rtl/pipe_regs/VX_d_e_reg.v +++ /dev/null @@ -1,30 +0,0 @@ -`include "VX_define.vh" - -module VX_d_e_reg ( - input wire clk, - input wire reset, - input wire branch_stall, - input wire freeze, - VX_backend_req_if frE_to_bckE_req_if, - VX_backend_req_if bckE_req_if -); - - wire stall = freeze; - wire flush = (branch_stall != 0); - - VX_generic_register #( - .N(233 + `NW_BITS-1 + 1 + `NUM_THREADS) - ) d_e_reg ( - .clk (clk), - .reset (reset), - .stall (stall), - .flush (flush), - .in ({frE_to_bckE_req_if.csr_address, frE_to_bckE_req_if.is_jal, frE_to_bckE_req_if.is_etype, frE_to_bckE_req_if.is_csr, frE_to_bckE_req_if.csr_immed, frE_to_bckE_req_if.csr_mask, frE_to_bckE_req_if.rd, frE_to_bckE_req_if.rs1, frE_to_bckE_req_if.rs2, frE_to_bckE_req_if.alu_op, frE_to_bckE_req_if.wb, frE_to_bckE_req_if.rs2_src, frE_to_bckE_req_if.itype_immed, frE_to_bckE_req_if.mem_read, frE_to_bckE_req_if.mem_write, frE_to_bckE_req_if.branch_type, frE_to_bckE_req_if.upper_immed, frE_to_bckE_req_if.curr_PC, frE_to_bckE_req_if.jal, frE_to_bckE_req_if.jal_offset, frE_to_bckE_req_if.next_PC, frE_to_bckE_req_if.valid, frE_to_bckE_req_if.warp_num, frE_to_bckE_req_if.is_wspawn, frE_to_bckE_req_if.is_tmc, frE_to_bckE_req_if.is_split, frE_to_bckE_req_if.is_barrier}), - .out ({bckE_req_if.csr_address , bckE_req_if.is_jal , bckE_req_if.is_etype ,bckE_req_if.is_csr , bckE_req_if.csr_immed , bckE_req_if.csr_mask , bckE_req_if.rd , bckE_req_if.rs1 , bckE_req_if.rs2 , bckE_req_if.alu_op , bckE_req_if.wb , bckE_req_if.rs2_src , bckE_req_if.itype_immed , bckE_req_if.mem_read , bckE_req_if.mem_write , bckE_req_if.branch_type , bckE_req_if.upper_immed , bckE_req_if.curr_PC , bckE_req_if.jal , bckE_req_if.jal_offset , bckE_req_if.next_PC , bckE_req_if.valid , bckE_req_if.warp_num , bckE_req_if.is_wspawn , bckE_req_if.is_tmc , bckE_req_if.is_split , bckE_req_if.is_barrier }) - ); - -endmodule - - - - diff --git a/hw/rtl/pipe_regs/VX_f_d_reg.v b/hw/rtl/pipe_regs/VX_f_d_reg.v deleted file mode 100644 index a2dfba0c..00000000 --- a/hw/rtl/pipe_regs/VX_f_d_reg.v +++ /dev/null @@ -1,27 +0,0 @@ -`include "VX_define.vh" - -module VX_f_d_reg ( - input wire clk, - input wire reset, - input wire freeze, - - VX_inst_meta_if fe_inst_meta_fd, - VX_inst_meta_if fd_inst_meta_de - -); - - wire flush = 1'b0; - wire stall = freeze == 1'b1; - - VX_generic_register #( - .N(64+`NW_BITS-1+1+`NUM_THREADS) - ) f_d_reg ( - .clk (clk), - .reset (reset), - .stall (stall), - .flush (flush), - .in ({fe_inst_meta_fd.instruction, fe_inst_meta_fd.inst_pc, fe_inst_meta_fd.warp_num, fe_inst_meta_fd.valid}), - .out ({fd_inst_meta_de.instruction, fd_inst_meta_de.inst_pc, fd_inst_meta_de.warp_num, fd_inst_meta_de.valid}) - ); - -endmodule \ No newline at end of file diff --git a/hw/rtl/pipe_regs/VX_i_d_reg.v b/hw/rtl/pipe_regs/VX_i_d_reg.v deleted file mode 100644 index 9963883f..00000000 --- a/hw/rtl/pipe_regs/VX_i_d_reg.v +++ /dev/null @@ -1,27 +0,0 @@ -`include "VX_define.vh" - -module VX_i_d_reg ( - input wire clk, - input wire reset, - input wire freeze, - - VX_inst_meta_if fe_inst_meta_fd, - VX_inst_meta_if fd_inst_meta_de - -); - - wire flush = 1'b0; - wire stall = freeze == 1'b1; - - VX_generic_register #( - .N(64 + `NW_BITS-1 + 1 + `NUM_THREADS) - ) i_d_reg ( - .clk (clk), - .reset (reset), - .stall (stall), - .flush (flush), - .in ({fe_inst_meta_fd.instruction, fe_inst_meta_fd.inst_pc, fe_inst_meta_fd.warp_num, fe_inst_meta_fd.valid}), - .out ({fd_inst_meta_de.instruction, fd_inst_meta_de.inst_pc, fd_inst_meta_de.warp_num, fd_inst_meta_de.valid}) - ); - -endmodule \ No newline at end of file diff --git a/hw/simulate/Makefile b/hw/simulate/Makefile index 21814760..7b665714 100644 --- a/hw/simulate/Makefile +++ b/hw/simulate/Makefile @@ -15,7 +15,7 @@ DBG_PRINT_FLAGS += -DDBG_PRINT_OPAE #DBG_FLAGS += $(DBG_PRINT_FLAGS) DBG_FLAGS += -DDBG_CORE_REQ_INFO -INCLUDE = -I../rtl/ -I../rtl/libs -I../rtl/interfaces -I../rtl/pipe_regs -I../rtl/cache -I../rtl/simulate +INCLUDE = -I../rtl/ -I../rtl/libs -I../rtl/interfaces -I../rtl/cache -I../rtl/simulate SRCS = simulator.cpp testbench.cpp diff --git a/hw/syn/quartus/.gitignore b/hw/syn/quartus/.gitignore index fedeee42..eac68fed 100644 --- a/hw/syn/quartus/.gitignore +++ b/hw/syn/quartus/.gitignore @@ -8,4 +8,7 @@ !/vortex/Makefile /pipeline/* -!/pipeline/Makefile \ No newline at end of file +!/pipeline/Makefile + +/core/* +!/core/Makefile diff --git a/hw/syn/quartus/core/Makefile b/hw/syn/quartus/core/Makefile index 69ab23ab..0968b478 100644 --- a/hw/syn/quartus/core/Makefile +++ b/hw/syn/quartus/core/Makefile @@ -49,7 +49,7 @@ smart.log: $(PROJECT_FILES) # Project initialization $(PROJECT_FILES): - quartus_sh -t ../project.tcl -project $(PROJECT) -family $(FAMILY) -device $(DEVICE) -top $(TOP_LEVEL_ENTITY) -src $(SRC_FILE) -sdc ../project.sdc -inc "../../../rtl;../../../rtl/libs;../../../rtl/interfaces;../../../rtl/pipe_regs;../../../rtl/cache" + quartus_sh -t ../project.tcl -project $(PROJECT) -family $(FAMILY) -device $(DEVICE) -top $(TOP_LEVEL_ENTITY) -src $(SRC_FILE) -sdc ../project.sdc -inc "../../../rtl;../../../rtl/libs;../../../rtl/interfaces;../../../rtl/cache" syn.chg: $(STAMP) syn.chg diff --git a/hw/syn/quartus/pipeline/Makefile b/hw/syn/quartus/pipeline/Makefile index b2ed2d5e..49232fe8 100644 --- a/hw/syn/quartus/pipeline/Makefile +++ b/hw/syn/quartus/pipeline/Makefile @@ -49,7 +49,7 @@ smart.log: $(PROJECT_FILES) # Project initialization $(PROJECT_FILES): - quartus_sh -t ../project.tcl -project $(PROJECT) -family $(FAMILY) -device $(DEVICE) -top $(TOP_LEVEL_ENTITY) -src $(SRC_FILE) -sdc ../project.sdc -inc "../../../rtl;../../../rtl/libs;../../../rtl/interfaces;../../../rtl/pipe_regs" + quartus_sh -t ../project.tcl -project $(PROJECT) -family $(FAMILY) -device $(DEVICE) -top $(TOP_LEVEL_ENTITY) -src $(SRC_FILE) -sdc ../project.sdc -inc "../../../rtl;../../../rtl/libs;../../../rtl/interfaces" syn.chg: $(STAMP) syn.chg diff --git a/hw/syn/quartus/top/Makefile b/hw/syn/quartus/top/Makefile index dbb4844f..c6219230 100644 --- a/hw/syn/quartus/top/Makefile +++ b/hw/syn/quartus/top/Makefile @@ -49,7 +49,7 @@ smart.log: $(PROJECT_FILES) # Project initialization $(PROJECT_FILES): - quartus_sh -t ../project.tcl -project $(PROJECT) -family $(FAMILY) -device $(DEVICE) -top $(TOP_LEVEL_ENTITY) -src $(SRC_FILE) -set "NOPAE" -sdc ../project.sdc -inc "../../../rtl;../../../rtl/libs;../../../rtl/interfaces;../../../rtl/pipe_regs;../../../rtl/cache;../../../opae;../../../opae/ccip" + quartus_sh -t ../project.tcl -project $(PROJECT) -family $(FAMILY) -device $(DEVICE) -top $(TOP_LEVEL_ENTITY) -src $(SRC_FILE) -set "NOPAE" -sdc ../project.sdc -inc "../../../rtl;../../../rtl/libs;../../../rtl/interfaces;../../../rtl/cache;../../../opae;../../../opae/ccip" syn.chg: $(STAMP) syn.chg diff --git a/hw/syn/quartus/vortex/Makefile b/hw/syn/quartus/vortex/Makefile index 4e9badb1..f8db7cc8 100644 --- a/hw/syn/quartus/vortex/Makefile +++ b/hw/syn/quartus/vortex/Makefile @@ -49,7 +49,7 @@ smart.log: $(PROJECT_FILES) # Project initialization $(PROJECT_FILES): - quartus_sh -t ../project.tcl -project $(PROJECT) -family $(FAMILY) -device $(DEVICE) -top $(TOP_LEVEL_ENTITY) -src $(SRC_FILE) -sdc ../project.sdc -inc "../../../rtl;../../../rtl/libs;../../../rtl/interfaces;../../../rtl/pipe_regs;../../../rtl/cache" + quartus_sh -t ../project.tcl -project $(PROJECT) -family $(FAMILY) -device $(DEVICE) -top $(TOP_LEVEL_ENTITY) -src $(SRC_FILE) -sdc ../project.sdc -inc "../../../rtl;../../../rtl/libs;../../../rtl/interfaces;../../../rtl/cache" syn.chg: $(STAMP) syn.chg diff --git a/hw/syn/yosys/synth.sh b/hw/syn/yosys/synth.sh new file mode 100755 index 00000000..621866f1 --- /dev/null +++ b/hw/syn/yosys/synth.sh @@ -0,0 +1,32 @@ +#!/bin/bash + +dir_list='../../rtl/libs ../../rtl/cache ../../rtl/interfaces ../../rtl' + +inc_list="" +for dir in $dir_list; do + inc_list="$inc_list -I$dir" +done + +echo "inc_list=$inc_list" + +{ + # read design sources + for dir in $dir_list; do + for file in $(find $dir -name '*.v' -o -name '*.sv' -type f) + do + echo "read_verilog -sv $inc_list $file" + done + done + + echo "hierarchy -check -top Vortex" + + # insertation of global reset + echo "add -global_input reset 1" + echo "proc -global_arst reset" + + echo "synth -run coarse; opt -fine" + echo "tee -o brams.log memory_bram -rules scripts/brams.txt;;" + echo "write_verilog -noexpr -noattr synth.v" +} > synth.ys + +yosys -l synth.log synth.ys \ No newline at end of file diff --git a/hw/syn/yosys/synthesis.ys b/hw/syn/yosys/synthesis.ys deleted file mode 100644 index fd208160..00000000 --- a/hw/syn/yosys/synthesis.ys +++ /dev/null @@ -1,27 +0,0 @@ -# load design -read_verilog -sv -I../../rtl -I../../rtl/libs -I../../rtl/interfaces -I../../rtl/pipe_regs -I../../rtl/cache ../../rtl/Vortex.v - -# high-level synthesis -proc; opt; fsm;; memory -nomap; opt - -# substitute block rams -techmap -map map_rams.v - -# map remaining memories -memory_map - -# low-level synthesis -techmap; opt; flatten;; abc -lut6 -techmap -map map_xl_cells.v - -# add clock buffers -select -set xl_clocks t:FDRE %x:+FDRE[C] t:FDRE %d -iopadmap -inpad BUFGP O:I @xl_clocks - -# add io buffers -select -set xl_nonclocks w:* t:BUFGP %x:+BUFGP[I] %d -iopadmap -outpad OBUF I:O -inpad IBUF O:I @xl_nonclocks - -# write synthesis results -write_edif synth.edif - diff --git a/hw/unit_tests/cache/.Makefile.swp b/hw/unit_tests/cache/.Makefile.swp new file mode 100644 index 00000000..fe645a32 Binary files /dev/null and b/hw/unit_tests/cache/.Makefile.swp differ diff --git a/hw/unit_tests/cache/Makefile b/hw/unit_tests/cache/Makefile new file mode 100644 index 00000000..9aba4010 --- /dev/null +++ b/hw/unit_tests/cache/Makefile @@ -0,0 +1,43 @@ +PARAM += -DCACHE_SIZE=4096 -DWORD_SIZE=4 -DBANK_LINE_SIZE=16 -DNUM_BANKS=4 -DCREQ_SIZE=4 -DMRVQ_SIZE=16 -DDFPQ_SIZE=16 -DSNRQ_SIZE=16 -DCWBQ_SIZE=4 -DDWBQ_SIZE=4 -DFQQ_SIZE=4 + + + +# control RTL debug print states +DBG_PRINT_FLAGS = -DDBG_PRINT_CORE_ICACHE \ + -DDBG_PRINT_CORE_DCACHE \ + -DDBG_PRINT_CACHE_BANK \ + -DDBG_PRINT_CACHE_SNP \ + -DDBG_PRINT_CACHE_MSRQ \ + -DDBG_PRINT_DRAM \ + -DDBG_PRINT_OPAE + +#DBG_PRINT=$(DBG_PRINT_FLAGS) + +INCLUDE = -I../../rtl/ -I../../rtl/cache -I../../rtl/libs + + +SRCS = cachesim.cpp testbench.cpp + +all: build + +CF += -std=c++11 -fms-extensions -I../.. + +VF += --language 1800-2009 --assert -Wall --trace #-Wpedantic +VF += -Wno-DECLFILENAME +VF += --x-initial unique +VF += -exe $(SRCS) $(INCLUDE) + +DBG += -DVCD_OUTPUT $(DBG_PRINT) + + +gen: + verilator $(VF) -DNDEBUG -cc VX_cache.v $(PARAM) -CFLAGS '$(CF) -DNDEBUG $(PARAM)' --exe $(SRCS) + +build: gen + (cd obj_dir && make -j -f VVX_cache.mk) + +run: build + (cd obj_dir && ./VVX_cache) + +clean: + rm -rf obj_dir diff --git a/hw/unit_tests/cache/cachesim.cpp b/hw/unit_tests/cache/cachesim.cpp new file mode 100644 index 00000000..26d67b76 --- /dev/null +++ b/hw/unit_tests/cache/cachesim.cpp @@ -0,0 +1,270 @@ +#include "cachesim.h" +#include +#include +#include +#include + +uint64_t timestamp = 0; + +double sc_time_stamp() { + return timestamp; +} + +CacheSim::CacheSim() { + // force random values for uninitialized signals + Verilated::randReset(2); + + ram_ = nullptr; + cache_ = new VVX_cache(); + + dram_rsp_active_ = false; + snp_req_active_ = false; + +//#ifdef VCD_OUTPUT + Verilated::traceEverOn(true); + trace_ = new VerilatedVcdC; + cache_->trace(trace_, 99); + trace_->open("trace.vcd"); +//#endif +} + +CacheSim::~CacheSim() { +//#ifdef VCD_OUTPUT + trace_->close(); +//#endif + delete cache_; +} + +void CacheSim::attach_ram(RAM* ram) { + ram_ = ram; + dram_rsp_vec_.clear(); +} + +void CacheSim::reset() { +#ifndef NDEBUG + std::cout << timestamp << ": [sim] reset()" << std::endl; +#endif + + cache_->reset = 1; + this->step(); + cache_->reset = 0; + this->step(); + dram_rsp_vec_.clear(); + +} + +void CacheSim::step() { + cache_->clk = 0; + this->eval(); + + cache_->clk = 1; + this->eval(); + + //this->eval_reqs(); + //this->eval_rsps(); + this->eval_dram_bus(); +} + +void CacheSim::eval() { + cache_->eval(); +//#ifdef VCD_OUTPUT + trace_->dump(timestamp); +//#endif + ++timestamp; +} + +void CacheSim::run(){ +#ifndef NDEBUG + std::cout << timestamp << ": [sim] run()" << std::endl; +#endif + // reset the device + this->reset(); + this->step(); + + // execute program + while (!core_reqq_.empty()) { + + for(int i = 0; i < 10; ++i){ + if(i == 1){ + this->clear_req(); //invalidate reqs + } + this->step(); + } + + } +} + +void CacheSim::clear_req(){ + cache_->core_req_valid = 0; +} + +/* +void CacheSim::send_req(core_req_t *req){ + core_reqq_.push(req); +} + +bool CacheSim::get_core_req_ready(){ + return cache_->core_req_ready; +} + +bool CacheSim::get_core_rsp_ready(){ + return cache_->core_rsp_ready; +} +*/ + +void CacheSim::set_core_req(){ + cache_->core_req_valid = 0xf; + cache_->core_req_rw = 0xf; + cache_->core_req_byteen = 0xffff; + cache_->core_req_addr[0] = 0x00; + cache_->core_req_addr[1] = 0xab; + cache_->core_req_addr[2] = 0xcd; + cache_->core_req_addr[3] = 0xe1; + cache_->core_req_data[0] = 0xffffffff; + cache_->core_req_data[1] = 0x11111111; + cache_->core_req_data[2] = 0x22222222; + cache_->core_req_data[3] = 0x33333333; + cache_->core_req_tag = 0xff; +} + +void CacheSim::set_core_req2(){ + cache_->core_req_valid = 0xf; //b1000 + cache_->core_req_rw = 0x0; //b0000 + cache_->core_req_byteen = 0xffff; + cache_->core_req_addr[0] = 0x00; + cache_->core_req_addr[1] = 0xab; + cache_->core_req_addr[2] = 0xcd; + cache_->core_req_addr[3] = 0xe1; + cache_->core_req_data[0] = 0x1111111; + cache_->core_req_data[1] = 0x4444444; + cache_->core_req_data[2] = 0x5555555; + cache_->core_req_data[3] = 0x6666666; + cache_->core_req_tag = 0xff; +} + + +void CacheSim::get_core_rsp(){ + std::cout << std::hex << "core_rsp_valid: " << cache_->core_rsp_valid << std::endl; + std::cout << std::hex << "core_rsp_data: " << cache_->core_rsp_data << std::endl; + std::cout << std::hex << "core_rsp_tag: " << cache_->core_rsp_tag << std::endl; + + char check = cache_->core_req_valid; + std::cout << "core_req_valid: " << check << std::endl; + std::cout << std::hex << "core_req_data: " << cache_->core_req_data << std::endl; + std::cout << std::hex << "core_req_tag: " << cache_->core_req_tag << std::endl; +} + +void CacheSim::get_dram_req(){ + std::cout << std::hex << "dram_req_valid: " << cache_->dram_req_valid << std::endl; + std::cout << std::hex << "dram_req_rw: " << cache_->dram_req_rw << std::endl; + std::cout << std::hex << "dram_req_byteen: " << cache_->dram_req_byteen << std::endl; + std::cout << std::hex << "dram_req_addr: " << cache_->dram_req_addr << std::endl; + std::cout << std::hex << "dram_req_data: " << cache_->dram_req_data << std::endl; + std::cout << std::hex << "dram_req_tag: " << cache_->dram_req_tag << std::endl; +} + +void CacheSim::get_dram_rsp(){ + std::cout << std::hex << "dram_rsp_valid: " << cache_->dram_rsp_valid << std::endl; + std::cout << std::hex << "dram_rsp_data: " << cache_->dram_rsp_data << std::endl; + std::cout << std::hex << "dram_rsp_tag: " << cache_->dram_rsp_tag << std::endl; + std::cout << std::hex << "dram_rsp_ready: " << cache_->dram_rsp_ready << std::endl; +} + + + +void CacheSim::eval_reqs(){ + //check to see if cache is accepting reqs + /*if(!core_reqq_.empty() && cache_->core_req_ready){ + core_req_t *req = core_reqq_.front(); + cache_->core_req_valid = req->valid; + cache_->core_req_rw = req->rw; + cache_->core_req_byteen = req->byteen; + cache_->core_req_addr = req->addr; + cache_->core_req_data = req->data; + cache_->core_req_tag = req->tag; + }*/ +} + +void CacheSim::eval_rsps(){ + //check to see if a request has been responded to + //if core_rsp tag equal to the front queue tag pop it from the queue + //while the req tag == rsp tag +} + +void CacheSim::eval_dram_bus() { + if (ram_ == nullptr) { + cache_->dram_req_ready = 0; + return; + } + + // schedule DRAM responses + int dequeue_index = -1; + for (int i = 0; i < dram_rsp_vec_.size(); i++) { + if (dram_rsp_vec_[i].cycles_left > 0) { + dram_rsp_vec_[i].cycles_left -= 1; + } + if ((dequeue_index == -1) + && (dram_rsp_vec_[i].cycles_left == 0)) { + dequeue_index = i; + } + } + + // send DRAM response + if (dram_rsp_active_ + && cache_->dram_rsp_valid + && cache_->dram_rsp_ready) { + dram_rsp_active_ = false; + } + if (!dram_rsp_active_) { + if (dequeue_index != -1) { //time to respond to the request + cache_->dram_rsp_valid = 1; + + //copy data from the rsp queue to the cache module + memcpy((uint8_t*)cache_->dram_rsp_data, dram_rsp_vec_[dequeue_index].data, GLOBAL_BLOCK_SIZE); + + cache_->dram_rsp_tag = dram_rsp_vec_[dequeue_index].tag; + free(dram_rsp_vec_[dequeue_index].data); //take data out of the queue + dram_rsp_vec_.erase(dram_rsp_vec_.begin() + dequeue_index); + dram_rsp_active_ = true; + } else { + cache_->dram_rsp_valid = 0; + } + } + + // handle DRAM stalls + bool dram_stalled = false; +#ifdef ENABLE_DRAM_STALLS + if (0 == ((timestamp/2) % DRAM_STALLS_MODULO)) { + dram_stalled = true; + } else + if (dram_rsp_vec_.size() >= DRAM_RQ_SIZE) { + dram_stalled = true; + } +#endif + + // process DRAM requests + if (!dram_stalled) { + if (cache_->dram_req_valid) { + if (cache_->dram_req_rw) { //write = 1 + uint64_t byteen = cache_->dram_req_byteen; + unsigned base_addr = (cache_->dram_req_addr * GLOBAL_BLOCK_SIZE); + uint8_t* data = (uint8_t*)(cache_->dram_req_data); + for (int i = 0; i < GLOBAL_BLOCK_SIZE; i++) { + if ((byteen >> i) & 0x1) { + (*ram_)[base_addr + i] = data[i]; + } + } + } else { + dram_req_t dram_req; + dram_req.cycles_left = DRAM_LATENCY; + dram_req.data = (uint8_t*)malloc(GLOBAL_BLOCK_SIZE); + dram_req.tag = cache_->dram_req_tag; + ram_->read(cache_->dram_req_addr * GLOBAL_BLOCK_SIZE, GLOBAL_BLOCK_SIZE, dram_req.data); + dram_rsp_vec_.push_back(dram_req); + } + } + } + + cache_->dram_req_ready = ~dram_stalled; +} + diff --git a/hw/unit_tests/cache/cachesim.h b/hw/unit_tests/cache/cachesim.h new file mode 100644 index 00000000..97e1b896 --- /dev/null +++ b/hw/unit_tests/cache/cachesim.h @@ -0,0 +1,89 @@ +#pragma once + +#include "VVX_cache.h" +#include "VVX_cache__Syms.h" +#include "verilated.h" + +//#ifdef VCD_OUTPUT +#include +//#endif + +//#include +#include "ram.h" +#include +#include +#include + +#define ENABLE_DRAM_STALLS +#define DRAM_LATENCY 100 +#define DRAM_RQ_SIZE 16 +#define DRAM_STALLS_MODULO 16 +#define GLOBAL_BLOCK_SIZE 16 + +typedef struct { + int cycles_left; + uint8_t *data; + unsigned tag; +} dram_req_t; + +typedef struct { + bool valid = 1; + unsigned rw; + unsigned byteen; + unsigned int *addr[4]; + unsigned int *data[4]; + unsigned tag; + bool responded; +} core_req_t; + +class CacheSim { +public: + + CacheSim(); + virtual ~CacheSim(); + + bool busy(); + + void reset(); + void step(); + void wait(uint32_t cycles); + void attach_ram(RAM* ram); + + void run(); //run until all reqs are empty + void clear_req(); + void send_req(core_req_t *req); + + void set_core_req(); + void set_core_req2(); + + //display funcs + + void get_dram_req(); + void get_core_rsp(); + bool get_core_req_ready(); + bool get_core_rsp_ready(); + void get_dram_rsp(); + + +private: + + void eval(); + + void eval_reqs(); + void eval_rsps(); + void eval_dram_bus(); + + std::queue core_reqq_; + std::vector dram_rsp_vec_; + int dram_rsp_active_; + + uint32_t snp_req_active_; + uint32_t snp_req_size_; + uint32_t pending_snp_reqs_; + + VVX_cache *cache_; + RAM *ram_; +//#ifdef VCD_OUTPUT + VerilatedVcdC *trace_; +//#endif +}; diff --git a/hw/unit_tests/cache/obj_dir/VVX_cache b/hw/unit_tests/cache/obj_dir/VVX_cache new file mode 100755 index 00000000..bc2057b7 Binary files /dev/null and b/hw/unit_tests/cache/obj_dir/VVX_cache differ diff --git a/hw/unit_tests/cache/obj_dir/VVX_cache.cpp b/hw/unit_tests/cache/obj_dir/VVX_cache.cpp new file mode 100644 index 00000000..58721aa6 --- /dev/null +++ b/hw/unit_tests/cache/obj_dir/VVX_cache.cpp @@ -0,0 +1,28288 @@ +// Verilated -*- C++ -*- +// DESCRIPTION: Verilator output: Design implementation internals +// See VVX_cache.h for the primary calling header + +#include "VVX_cache.h" +#include "VVX_cache__Syms.h" + +//========== +CData/*1:0*/ VVX_cache::__Vtable1_VX_cache__DOT__cache_dram_req_arb__DOT__dram_fill_arb__DOT__qual_request_index[16]; +CData/*0:0*/ VVX_cache::__Vtable1_VX_cache__DOT__cache_dram_req_arb__DOT__dram_fill_arb__DOT__qual_has_request[16]; +IData/*31:0*/ VVX_cache::__Vtable1_VX_cache__DOT__cache_dram_req_arb__DOT__dram_fill_arb__DOT__sel_bank__DOT__genblk2__DOT__priority_encoder__DOT__i[16]; +CData/*1:0*/ VVX_cache::__Vtable2_VX_cache__DOT__cache_dram_req_arb__DOT__dwb_bank[16]; +CData/*0:0*/ VVX_cache::__Vtable2_VX_cache__DOT__cache_dram_req_arb__DOT__dwb_valid[16]; +IData/*31:0*/ VVX_cache::__Vtable2_VX_cache__DOT__cache_dram_req_arb__DOT__sel_dwb__DOT__genblk2__DOT__priority_encoder__DOT__i[16]; +CData/*1:0*/ VVX_cache::__Vtable3_VX_cache__DOT__cache_core_rsp_merge__DOT__main_bank_index[16]; +CData/*0:0*/ VVX_cache::__Vtable3_VX_cache__DOT__cache_core_rsp_merge__DOT__sel_bank__DOT__grant_valid[16]; +IData/*31:0*/ VVX_cache::__Vtable3_VX_cache__DOT__cache_core_rsp_merge__DOT__sel_bank__DOT__genblk2__DOT__priority_encoder__DOT__i[16]; +CData/*1:0*/ VVX_cache::__Vtable4_VX_cache__DOT__snp_rsp_arb__DOT__fsq_bank[16]; +CData/*0:0*/ VVX_cache::__Vtable4_VX_cache__DOT__snp_rsp_arb__DOT__fsq_valid[16]; +IData/*31:0*/ VVX_cache::__Vtable4_VX_cache__DOT__snp_rsp_arb__DOT__sel_ffsq__DOT__genblk2__DOT__priority_encoder__DOT__i[16]; +CData/*1:0*/ VVX_cache::__Vtable5_VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__core_req_arb__DOT__qual_request_index[16]; +CData/*0:0*/ VVX_cache::__Vtable5_VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__core_req_arb__DOT__qual_has_request[16]; +IData/*31:0*/ VVX_cache::__Vtable5_VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__core_req_arb__DOT__sel_bank__DOT__genblk2__DOT__priority_encoder__DOT__i[16]; +CData/*1:0*/ VVX_cache::__Vtable6_VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__core_req_arb__DOT__qual_request_index[16]; +CData/*0:0*/ VVX_cache::__Vtable6_VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__core_req_arb__DOT__qual_has_request[16]; +IData/*31:0*/ VVX_cache::__Vtable6_VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__core_req_arb__DOT__sel_bank__DOT__genblk2__DOT__priority_encoder__DOT__i[16]; +CData/*1:0*/ VVX_cache::__Vtable7_VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__core_req_arb__DOT__qual_request_index[16]; +CData/*0:0*/ VVX_cache::__Vtable7_VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__core_req_arb__DOT__qual_has_request[16]; +IData/*31:0*/ VVX_cache::__Vtable7_VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__core_req_arb__DOT__sel_bank__DOT__genblk2__DOT__priority_encoder__DOT__i[16]; +CData/*1:0*/ VVX_cache::__Vtable8_VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__core_req_arb__DOT__qual_request_index[16]; +CData/*0:0*/ VVX_cache::__Vtable8_VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__core_req_arb__DOT__qual_has_request[16]; +IData/*31:0*/ VVX_cache::__Vtable8_VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__core_req_arb__DOT__sel_bank__DOT__genblk2__DOT__priority_encoder__DOT__i[16]; + +VL_CTOR_IMP(VVX_cache) { + VVX_cache__Syms* __restrict vlSymsp = __VlSymsp = new VVX_cache__Syms(this, name()); + VVX_cache* __restrict vlTOPp VL_ATTR_UNUSED = vlSymsp->TOPp; + // Reset internal values + + // Reset structure values + _ctor_var_reset(); +} + +void VVX_cache::__Vconfigure(VVX_cache__Syms* vlSymsp, bool first) { + if (0 && first) {} // Prevent unused + this->__VlSymsp = vlSymsp; +} + +VVX_cache::~VVX_cache() { + delete __VlSymsp; __VlSymsp=NULL; +} + +void VVX_cache::eval_step() { + VL_DEBUG_IF(VL_DBG_MSGF("+++++TOP Evaluate VVX_cache::eval\n"); ); + VVX_cache__Syms* __restrict vlSymsp = this->__VlSymsp; // Setup global symbol table + VVX_cache* __restrict vlTOPp VL_ATTR_UNUSED = vlSymsp->TOPp; +#ifdef VL_DEBUG + // Debug assertions + _eval_debug_assertions(); +#endif // VL_DEBUG + // Initialize + if (VL_UNLIKELY(!vlSymsp->__Vm_didInit)) _eval_initial_loop(vlSymsp); +#ifdef VM_TRACE + // Tracing +#endif // VM_TRACE + // Evaluate till stable + int __VclockLoop = 0; + QData __Vchange = 1; + do { + VL_DEBUG_IF(VL_DBG_MSGF("+ Clock loop\n");); + vlSymsp->__Vm_activity = true; + _eval(vlSymsp); + if (VL_UNLIKELY(++__VclockLoop > 100)) { + // About to fail, so enable debug to see what's not settling. + // Note you must run make with OPT=-DVL_DEBUG for debug prints. + int __Vsaved_debug = Verilated::debug(); + Verilated::debug(1); + __Vchange = _change_request(vlSymsp); + Verilated::debug(__Vsaved_debug); + VL_FATAL_MT("../../rtl/cache/VX_cache.v", 3, "", + "Verilated model didn't converge\n" + "- See DIDNOTCONVERGE in the Verilator manual"); + } else { + __Vchange = _change_request(vlSymsp); + } + } while (VL_UNLIKELY(__Vchange)); +} + +void VVX_cache::_eval_initial_loop(VVX_cache__Syms* __restrict vlSymsp) { + vlSymsp->__Vm_didInit = true; + _eval_initial(vlSymsp); + vlSymsp->__Vm_activity = true; + // Evaluate till stable + int __VclockLoop = 0; + QData __Vchange = 1; + do { + _eval_settle(vlSymsp); + _eval(vlSymsp); + if (VL_UNLIKELY(++__VclockLoop > 100)) { + // About to fail, so enable debug to see what's not settling. + // Note you must run make with OPT=-DVL_DEBUG for debug prints. + int __Vsaved_debug = Verilated::debug(); + Verilated::debug(1); + __Vchange = _change_request(vlSymsp); + Verilated::debug(__Vsaved_debug); + VL_FATAL_MT("../../rtl/cache/VX_cache.v", 3, "", + "Verilated model didn't DC converge\n" + "- See DIDNOTCONVERGE in the Verilator manual"); + } else { + __Vchange = _change_request(vlSymsp); + } + } while (VL_UNLIKELY(__Vchange)); +} + +void VVX_cache::_initial__TOP__1(VVX_cache__Syms* __restrict vlSymsp) { + VL_DEBUG_IF(VL_DBG_MSGF("+ VVX_cache::_initial__TOP__1\n"); ); + VVX_cache* __restrict vlTOPp VL_ATTR_UNUSED = vlSymsp->TOPp; + // Body + vlTOPp->snp_fwdout_valid = 0U; + vlTOPp->snp_fwdout_addr = VL_ULL(0); + vlTOPp->snp_fwdout_invalidate = 0U; + vlTOPp->snp_fwdout_tag = 0U; + vlTOPp->snp_fwdin_ready = 0U; +} + +VL_INLINE_OPT void VVX_cache::_combo__TOP__2(VVX_cache__Syms* __restrict vlSymsp) { + VL_DEBUG_IF(VL_DBG_MSGF("+ VVX_cache::_combo__TOP__2\n"); ); + VVX_cache* __restrict vlTOPp VL_ATTR_UNUSED = vlSymsp->TOPp; + // Body + vlTOPp->VX_cache__DOT____Vcellout__cache_core_req_bank_sel__per_bank_valid = 0U; + vlTOPp->VX_cache__DOT____Vcellout__cache_core_req_bank_sel__per_bank_valid + = (((~ ((IData)(1U) << (0xcU & vlTOPp->core_req_addr[0U]))) + & (IData)(vlTOPp->VX_cache__DOT____Vcellout__cache_core_req_bank_sel__per_bank_valid)) + | ((1U & (IData)(vlTOPp->core_req_valid)) + << (0xcU & vlTOPp->core_req_addr[0U]))); + vlTOPp->VX_cache__DOT____Vcellout__cache_core_req_bank_sel__per_bank_valid + = (((~ ((IData)(1U) << (0xfU & ((IData)(1U) + + (0xcU & ( + vlTOPp->core_req_addr[1U] + << 2U)))))) + & (IData)(vlTOPp->VX_cache__DOT____Vcellout__cache_core_req_bank_sel__per_bank_valid)) + | ((1U & ((IData)(vlTOPp->core_req_valid) + >> 1U)) << (0xfU & ((IData)(1U) + + (0xcU & + (vlTOPp->core_req_addr[1U] + << 2U)))))); + vlTOPp->VX_cache__DOT____Vcellout__cache_core_req_bank_sel__per_bank_valid + = (((~ ((IData)(1U) << (0xfU & ((IData)(2U) + + (0xcU & ( + (vlTOPp->core_req_addr[2U] + << 4U) + | (0xcU + & (vlTOPp->core_req_addr[1U] + >> 0x1cU)))))))) + & (IData)(vlTOPp->VX_cache__DOT____Vcellout__cache_core_req_bank_sel__per_bank_valid)) + | ((1U & ((IData)(vlTOPp->core_req_valid) + >> 2U)) << (0xfU & ((IData)(2U) + + (0xcU & + ((vlTOPp->core_req_addr[2U] + << 4U) + | (0xcU + & (vlTOPp->core_req_addr[1U] + >> 0x1cU)))))))); + vlTOPp->VX_cache__DOT____Vcellout__cache_core_req_bank_sel__per_bank_valid + = (((~ ((IData)(1U) << (0xfU & ((IData)(3U) + + (0xcU & ( + (vlTOPp->core_req_addr[3U] + << 6U) + | (0x3cU + & (vlTOPp->core_req_addr[2U] + >> 0x1aU)))))))) + & (IData)(vlTOPp->VX_cache__DOT____Vcellout__cache_core_req_bank_sel__per_bank_valid)) + | ((1U & ((IData)(vlTOPp->core_req_valid) + >> 3U)) << (0xfU & ((IData)(3U) + + (0xcU & + ((vlTOPp->core_req_addr[3U] + << 6U) + | (0x3cU + & (vlTOPp->core_req_addr[2U] + >> 0x1aU)))))))); + vlTOPp->VX_cache__DOT__cache_core_req_bank_sel__DOT__genblk2__DOT__per_bank_ready_sel = 0xfU; + vlTOPp->VX_cache__DOT__cache_core_req_bank_sel__DOT__genblk2__DOT__per_bank_ready_sel + = ((~ ((IData)(1U) << (3U & ((vlTOPp->core_req_addr[1U] + << 0x1eU) | ( + vlTOPp->core_req_addr[0U] + >> 2U))))) + & (IData)(vlTOPp->VX_cache__DOT__cache_core_req_bank_sel__DOT__genblk2__DOT__per_bank_ready_sel)); + vlTOPp->VX_cache__DOT__cache_core_req_bank_sel__DOT__genblk2__DOT__per_bank_ready_sel + = ((~ ((IData)(1U) << (3U & vlTOPp->core_req_addr[1U]))) + & (IData)(vlTOPp->VX_cache__DOT__cache_core_req_bank_sel__DOT__genblk2__DOT__per_bank_ready_sel)); + vlTOPp->VX_cache__DOT__cache_core_req_bank_sel__DOT__genblk2__DOT__per_bank_ready_sel + = ((~ ((IData)(1U) << (3U & ((vlTOPp->core_req_addr[2U] + << 2U) | (vlTOPp->core_req_addr[1U] + >> 0x1eU))))) + & (IData)(vlTOPp->VX_cache__DOT__cache_core_req_bank_sel__DOT__genblk2__DOT__per_bank_ready_sel)); + vlTOPp->VX_cache__DOT__cache_core_req_bank_sel__DOT__genblk2__DOT__per_bank_ready_sel + = ((~ ((IData)(1U) << (3U & ((vlTOPp->core_req_addr[3U] + << 4U) | (vlTOPp->core_req_addr[2U] + >> 0x1cU))))) + & (IData)(vlTOPp->VX_cache__DOT__cache_core_req_bank_sel__DOT__genblk2__DOT__per_bank_ready_sel)); +} + +void VVX_cache::_settle__TOP__3(VVX_cache__Syms* __restrict vlSymsp) { + VL_DEBUG_IF(VL_DBG_MSGF("+ VVX_cache::_settle__TOP__3\n"); ); + VVX_cache* __restrict vlTOPp VL_ATTR_UNUSED = vlSymsp->TOPp; + // Variables + WData/*191:0*/ __Vtemp146[6]; + WData/*255:0*/ __Vtemp147[8]; + WData/*191:0*/ __Vtemp160[6]; + WData/*255:0*/ __Vtemp161[8]; + WData/*191:0*/ __Vtemp174[6]; + WData/*255:0*/ __Vtemp175[8]; + WData/*191:0*/ __Vtemp188[6]; + WData/*255:0*/ __Vtemp189[8]; + WData/*127:0*/ __Vtemp191[4]; + WData/*287:0*/ __Vtemp198[9]; + WData/*287:0*/ __Vtemp199[9]; + WData/*319:0*/ __Vtemp201[10]; + WData/*127:0*/ __Vtemp204[4]; + WData/*287:0*/ __Vtemp211[9]; + WData/*287:0*/ __Vtemp212[9]; + WData/*319:0*/ __Vtemp214[10]; + WData/*127:0*/ __Vtemp217[4]; + WData/*287:0*/ __Vtemp224[9]; + WData/*287:0*/ __Vtemp225[9]; + WData/*319:0*/ __Vtemp227[10]; + WData/*127:0*/ __Vtemp230[4]; + WData/*287:0*/ __Vtemp237[9]; + WData/*287:0*/ __Vtemp238[9]; + WData/*319:0*/ __Vtemp240[10]; + // Body + vlTOPp->VX_cache__DOT____Vcellout__cache_core_req_bank_sel__per_bank_valid = 0U; + vlTOPp->VX_cache__DOT____Vcellout__cache_core_req_bank_sel__per_bank_valid + = (((~ ((IData)(1U) << (0xcU & vlTOPp->core_req_addr[0U]))) + & (IData)(vlTOPp->VX_cache__DOT____Vcellout__cache_core_req_bank_sel__per_bank_valid)) + | ((1U & (IData)(vlTOPp->core_req_valid)) + << (0xcU & vlTOPp->core_req_addr[0U]))); + vlTOPp->VX_cache__DOT____Vcellout__cache_core_req_bank_sel__per_bank_valid + = (((~ ((IData)(1U) << (0xfU & ((IData)(1U) + + (0xcU & ( + vlTOPp->core_req_addr[1U] + << 2U)))))) + & (IData)(vlTOPp->VX_cache__DOT____Vcellout__cache_core_req_bank_sel__per_bank_valid)) + | ((1U & ((IData)(vlTOPp->core_req_valid) + >> 1U)) << (0xfU & ((IData)(1U) + + (0xcU & + (vlTOPp->core_req_addr[1U] + << 2U)))))); + vlTOPp->VX_cache__DOT____Vcellout__cache_core_req_bank_sel__per_bank_valid + = (((~ ((IData)(1U) << (0xfU & ((IData)(2U) + + (0xcU & ( + (vlTOPp->core_req_addr[2U] + << 4U) + | (0xcU + & (vlTOPp->core_req_addr[1U] + >> 0x1cU)))))))) + & (IData)(vlTOPp->VX_cache__DOT____Vcellout__cache_core_req_bank_sel__per_bank_valid)) + | ((1U & ((IData)(vlTOPp->core_req_valid) + >> 2U)) << (0xfU & ((IData)(2U) + + (0xcU & + ((vlTOPp->core_req_addr[2U] + << 4U) + | (0xcU + & (vlTOPp->core_req_addr[1U] + >> 0x1cU)))))))); + vlTOPp->VX_cache__DOT____Vcellout__cache_core_req_bank_sel__per_bank_valid + = (((~ ((IData)(1U) << (0xfU & ((IData)(3U) + + (0xcU & ( + (vlTOPp->core_req_addr[3U] + << 6U) + | (0x3cU + & (vlTOPp->core_req_addr[2U] + >> 0x1aU)))))))) + & (IData)(vlTOPp->VX_cache__DOT____Vcellout__cache_core_req_bank_sel__per_bank_valid)) + | ((1U & ((IData)(vlTOPp->core_req_valid) + >> 3U)) << (0xfU & ((IData)(3U) + + (0xcU & + ((vlTOPp->core_req_addr[3U] + << 6U) + | (0x3cU + & (vlTOPp->core_req_addr[2U] + >> 0x1aU)))))))); + vlTOPp->VX_cache__DOT__cache_core_req_bank_sel__DOT__genblk2__DOT__per_bank_ready_sel = 0xfU; + vlTOPp->VX_cache__DOT__cache_core_req_bank_sel__DOT__genblk2__DOT__per_bank_ready_sel + = ((~ ((IData)(1U) << (3U & ((vlTOPp->core_req_addr[1U] + << 0x1eU) | ( + vlTOPp->core_req_addr[0U] + >> 2U))))) + & (IData)(vlTOPp->VX_cache__DOT__cache_core_req_bank_sel__DOT__genblk2__DOT__per_bank_ready_sel)); + vlTOPp->VX_cache__DOT__cache_core_req_bank_sel__DOT__genblk2__DOT__per_bank_ready_sel + = ((~ ((IData)(1U) << (3U & vlTOPp->core_req_addr[1U]))) + & (IData)(vlTOPp->VX_cache__DOT__cache_core_req_bank_sel__DOT__genblk2__DOT__per_bank_ready_sel)); + vlTOPp->VX_cache__DOT__cache_core_req_bank_sel__DOT__genblk2__DOT__per_bank_ready_sel + = ((~ ((IData)(1U) << (3U & ((vlTOPp->core_req_addr[2U] + << 2U) | (vlTOPp->core_req_addr[1U] + >> 0x1eU))))) + & (IData)(vlTOPp->VX_cache__DOT__cache_core_req_bank_sel__DOT__genblk2__DOT__per_bank_ready_sel)); + vlTOPp->VX_cache__DOT__cache_core_req_bank_sel__DOT__genblk2__DOT__per_bank_ready_sel + = ((~ ((IData)(1U) << (3U & ((vlTOPp->core_req_addr[3U] + << 4U) | (vlTOPp->core_req_addr[2U] + >> 0x1cU))))) + & (IData)(vlTOPp->VX_cache__DOT__cache_core_req_bank_sel__DOT__genblk2__DOT__per_bank_ready_sel)); + vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT____Vcellinp__dfp_queue__data_in[0U] + = vlTOPp->dram_rsp_data[0U]; + vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT____Vcellinp__dfp_queue__data_in[1U] + = vlTOPp->dram_rsp_data[1U]; + vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT____Vcellinp__dfp_queue__data_in[2U] + = vlTOPp->dram_rsp_data[2U]; + vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT____Vcellinp__dfp_queue__data_in[3U] + = vlTOPp->dram_rsp_data[3U]; + vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT____Vcellinp__dfp_queue__data_in[4U] + = (0x3ffffffU & (vlTOPp->dram_rsp_tag >> 2U)); + vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT____Vcellinp__dfp_queue__data_in[0U] + = vlTOPp->dram_rsp_data[0U]; + vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT____Vcellinp__dfp_queue__data_in[1U] + = vlTOPp->dram_rsp_data[1U]; + vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT____Vcellinp__dfp_queue__data_in[2U] + = vlTOPp->dram_rsp_data[2U]; + vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT____Vcellinp__dfp_queue__data_in[3U] + = vlTOPp->dram_rsp_data[3U]; + vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT____Vcellinp__dfp_queue__data_in[4U] + = (0x3ffffffU & (vlTOPp->dram_rsp_tag >> 2U)); + vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT____Vcellinp__dfp_queue__data_in[0U] + = vlTOPp->dram_rsp_data[0U]; + vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT____Vcellinp__dfp_queue__data_in[1U] + = vlTOPp->dram_rsp_data[1U]; + vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT____Vcellinp__dfp_queue__data_in[2U] + = vlTOPp->dram_rsp_data[2U]; + vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT____Vcellinp__dfp_queue__data_in[3U] + = vlTOPp->dram_rsp_data[3U]; + vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT____Vcellinp__dfp_queue__data_in[4U] + = (0x3ffffffU & (vlTOPp->dram_rsp_tag >> 2U)); + vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT____Vcellinp__dfp_queue__data_in[0U] + = vlTOPp->dram_rsp_data[0U]; + vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT____Vcellinp__dfp_queue__data_in[1U] + = vlTOPp->dram_rsp_data[1U]; + vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT____Vcellinp__dfp_queue__data_in[2U] + = vlTOPp->dram_rsp_data[2U]; + vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT____Vcellinp__dfp_queue__data_in[3U] + = vlTOPp->dram_rsp_data[3U]; + vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT____Vcellinp__dfp_queue__data_in[4U] + = (0x3ffffffU & (vlTOPp->dram_rsp_tag >> 2U)); + vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT____Vcellinp__snp_req_queue__data_in + = (((QData)((IData)((0x3ffffffU & (vlTOPp->snp_req_addr + >> 2U)))) + << 0x1dU) | (QData)((IData)((((IData)(vlTOPp->snp_req_invalidate) + << 0x1cU) + | vlTOPp->snp_req_tag)))); + vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT____Vcellinp__snp_req_queue__data_in + = (((QData)((IData)((0x3ffffffU & (vlTOPp->snp_req_addr + >> 2U)))) + << 0x1dU) | (QData)((IData)((((IData)(vlTOPp->snp_req_invalidate) + << 0x1cU) + | vlTOPp->snp_req_tag)))); + vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT____Vcellinp__snp_req_queue__data_in + = (((QData)((IData)((0x3ffffffU & (vlTOPp->snp_req_addr + >> 2U)))) + << 0x1dU) | (QData)((IData)((((IData)(vlTOPp->snp_req_invalidate) + << 0x1cU) + | vlTOPp->snp_req_tag)))); + vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT____Vcellinp__snp_req_queue__data_in + = (((QData)((IData)((0x3ffffffU & (vlTOPp->snp_req_addr + >> 2U)))) + << 0x1dU) | (QData)((IData)((((IData)(vlTOPp->snp_req_invalidate) + << 0x1cU) + | vlTOPp->snp_req_tag)))); + vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__going_to_write_st1[0U] + = (1U & (vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__s0_1_c0__DOT__value[7U] + >> 0xfU)); + vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__going_to_write_st1[0U] + = (1U & (vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__s0_1_c0__DOT__value[7U] + >> 0xfU)); + vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__going_to_write_st1[0U] + = (1U & (vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__s0_1_c0__DOT__value[7U] + >> 0xfU)); + vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__going_to_write_st1[0U] + = (1U & (vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__s0_1_c0__DOT__value[7U] + >> 0xfU)); + vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__snp_req_queue__DOT__writing + = (((IData)(vlTOPp->snp_req_valid) & (0U == + (3U & vlTOPp->snp_req_addr))) + & (~ (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__snp_req_queue__DOT__genblk3__DOT__genblk2__DOT__full_r))); + vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__dfp_queue__DOT__writing + = (((IData)(vlTOPp->dram_rsp_valid) & (0U == + (3U + & vlTOPp->dram_rsp_tag))) + & (~ (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__dfp_queue__DOT__genblk3__DOT__genblk2__DOT__full_r))); + vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__snp_req_queue__DOT__writing + = (((IData)(vlTOPp->snp_req_valid) & (1U == + (3U & vlTOPp->snp_req_addr))) + & (~ (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__snp_req_queue__DOT__genblk3__DOT__genblk2__DOT__full_r))); + vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__dfp_queue__DOT__writing + = (((IData)(vlTOPp->dram_rsp_valid) & (1U == + (3U + & vlTOPp->dram_rsp_tag))) + & (~ (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__dfp_queue__DOT__genblk3__DOT__genblk2__DOT__full_r))); + vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__snp_req_queue__DOT__writing + = (((IData)(vlTOPp->snp_req_valid) & (2U == + (3U & vlTOPp->snp_req_addr))) + & (~ (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__snp_req_queue__DOT__genblk3__DOT__genblk2__DOT__full_r))); + vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__dfp_queue__DOT__writing + = (((IData)(vlTOPp->dram_rsp_valid) & (2U == + (3U + & vlTOPp->dram_rsp_tag))) + & (~ (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__dfp_queue__DOT__genblk3__DOT__genblk2__DOT__full_r))); + vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__snp_req_queue__DOT__writing + = (((IData)(vlTOPp->snp_req_valid) & (3U == + (3U & vlTOPp->snp_req_addr))) + & (~ (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__snp_req_queue__DOT__genblk3__DOT__genblk2__DOT__full_r))); + vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__dfp_queue__DOT__writing + = (((IData)(vlTOPp->dram_rsp_valid) & (3U == + (3U + & vlTOPp->dram_rsp_tag))) + & (~ (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__dfp_queue__DOT__genblk3__DOT__genblk2__DOT__full_r))); + vlTOPp->VX_cache__DOT__cache_dram_req_arb__DOT__prfqq__DOT__update_use + = (((0U == (IData)(vlTOPp->VX_cache__DOT__cache_dram_req_arb__DOT__prfqq__DOT__use_valid)) + | (0U == ((IData)(vlTOPp->VX_cache__DOT__cache_dram_req_arb__DOT__prfqq__DOT__use_valid) + - (IData)(1U)))) & (IData)(vlTOPp->VX_cache__DOT__cache_dram_req_arb__DOT__prfqq__DOT__pfq_queue__DOT__size_r)); + vlTOPp->VX_cache__DOT__per_bank_dram_fill_rsp_ready + = ((0xeU & (IData)(vlTOPp->VX_cache__DOT__per_bank_dram_fill_rsp_ready)) + | (1U & (~ (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__dfp_queue__DOT__genblk3__DOT__genblk2__DOT__full_r)))); + vlTOPp->VX_cache__DOT__per_bank_dram_fill_rsp_ready + = ((0xdU & (IData)(vlTOPp->VX_cache__DOT__per_bank_dram_fill_rsp_ready)) + | (2U & ((~ (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__dfp_queue__DOT__genblk3__DOT__genblk2__DOT__full_r)) + << 1U))); + vlTOPp->VX_cache__DOT__per_bank_dram_fill_rsp_ready + = ((0xbU & (IData)(vlTOPp->VX_cache__DOT__per_bank_dram_fill_rsp_ready)) + | (4U & ((~ (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__dfp_queue__DOT__genblk3__DOT__genblk2__DOT__full_r)) + << 2U))); + vlTOPp->VX_cache__DOT__per_bank_dram_fill_rsp_ready + = ((7U & (IData)(vlTOPp->VX_cache__DOT__per_bank_dram_fill_rsp_ready)) + | (8U & ((~ (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__dfp_queue__DOT__genblk3__DOT__genblk2__DOT__full_r)) + << 3U))); + vlTOPp->VX_cache__DOT__per_bank_snp_req_ready = + ((0xeU & (IData)(vlTOPp->VX_cache__DOT__per_bank_snp_req_ready)) + | (1U & (~ (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__snp_req_queue__DOT__genblk3__DOT__genblk2__DOT__full_r)))); + vlTOPp->VX_cache__DOT__per_bank_snp_req_ready = + ((0xdU & (IData)(vlTOPp->VX_cache__DOT__per_bank_snp_req_ready)) + | (2U & ((~ (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__snp_req_queue__DOT__genblk3__DOT__genblk2__DOT__full_r)) + << 1U))); + vlTOPp->VX_cache__DOT__per_bank_snp_req_ready = + ((0xbU & (IData)(vlTOPp->VX_cache__DOT__per_bank_snp_req_ready)) + | (4U & ((~ (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__snp_req_queue__DOT__genblk3__DOT__genblk2__DOT__full_r)) + << 2U))); + vlTOPp->VX_cache__DOT__per_bank_snp_req_ready = + ((7U & (IData)(vlTOPp->VX_cache__DOT__per_bank_snp_req_ready)) + | (8U & ((~ (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__snp_req_queue__DOT__genblk3__DOT__genblk2__DOT__full_r)) + << 3U))); + vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__mrvq_rw_st0 + = (1U & (vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cache_miss_resrv__DOT__metadata_table + [vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr][0U] + >> 8U)); + vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__mrvq_rw_st0 + = (1U & (vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__cache_miss_resrv__DOT__metadata_table + [vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr][0U] + >> 8U)); + vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__mrvq_rw_st0 + = (1U & (vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__cache_miss_resrv__DOT__metadata_table + [vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr][0U] + >> 8U)); + vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__mrvq_rw_st0 + = (1U & (vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cache_miss_resrv__DOT__metadata_table + [vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr][0U] + >> 8U)); + vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT____Vcellout__snp_req_queue__data_out + = ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__snp_req_queue__DOT__genblk3__DOT__genblk2__DOT__bypass_r) + ? vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__snp_req_queue__DOT__genblk3__DOT__genblk2__DOT__curr_r + : vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__snp_req_queue__DOT__genblk3__DOT__genblk2__DOT__head_r); + vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT____Vcellout__snp_req_queue__data_out + = ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__snp_req_queue__DOT__genblk3__DOT__genblk2__DOT__bypass_r) + ? vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__snp_req_queue__DOT__genblk3__DOT__genblk2__DOT__curr_r + : vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__snp_req_queue__DOT__genblk3__DOT__genblk2__DOT__head_r); + vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT____Vcellout__snp_req_queue__data_out + = ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__snp_req_queue__DOT__genblk3__DOT__genblk2__DOT__bypass_r) + ? vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__snp_req_queue__DOT__genblk3__DOT__genblk2__DOT__curr_r + : vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__snp_req_queue__DOT__genblk3__DOT__genblk2__DOT__head_r); + vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT____Vcellout__snp_req_queue__data_out + = ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__snp_req_queue__DOT__genblk3__DOT__genblk2__DOT__bypass_r) + ? vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__snp_req_queue__DOT__genblk3__DOT__genblk2__DOT__curr_r + : vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__snp_req_queue__DOT__genblk3__DOT__genblk2__DOT__head_r); + vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__core_req_arb__DOT____Vcellout__reqq_queue__data_out[0U] + = ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__bypass_r) + ? vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__curr_r[0U] + : vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__head_r[0U]); + vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__core_req_arb__DOT____Vcellout__reqq_queue__data_out[1U] + = ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__bypass_r) + ? vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__curr_r[1U] + : vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__head_r[1U]); + vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__core_req_arb__DOT____Vcellout__reqq_queue__data_out[2U] + = ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__bypass_r) + ? vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__curr_r[2U] + : vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__head_r[2U]); + vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__core_req_arb__DOT____Vcellout__reqq_queue__data_out[3U] + = ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__bypass_r) + ? vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__curr_r[3U] + : vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__head_r[3U]); + vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__core_req_arb__DOT____Vcellout__reqq_queue__data_out[4U] + = ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__bypass_r) + ? vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__curr_r[4U] + : vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__head_r[4U]); + vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__core_req_arb__DOT____Vcellout__reqq_queue__data_out[5U] + = ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__bypass_r) + ? vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__curr_r[5U] + : vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__head_r[5U]); + vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__core_req_arb__DOT____Vcellout__reqq_queue__data_out[6U] + = ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__bypass_r) + ? vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__curr_r[6U] + : vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__head_r[6U]); + vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__core_req_arb__DOT____Vcellout__reqq_queue__data_out[7U] + = ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__bypass_r) + ? vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__curr_r[7U] + : vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__head_r[7U]); + vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__core_req_arb__DOT____Vcellout__reqq_queue__data_out[8U] + = ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__bypass_r) + ? vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__curr_r[8U] + : vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__head_r[8U]); + vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__core_req_arb__DOT____Vcellout__reqq_queue__data_out[9U] + = ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__bypass_r) + ? vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__curr_r[9U] + : vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__head_r[9U]); + vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__core_req_arb__DOT____Vcellout__reqq_queue__data_out[0U] + = ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__bypass_r) + ? vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__curr_r[0U] + : vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__head_r[0U]); + vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__core_req_arb__DOT____Vcellout__reqq_queue__data_out[1U] + = ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__bypass_r) + ? vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__curr_r[1U] + : vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__head_r[1U]); + vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__core_req_arb__DOT____Vcellout__reqq_queue__data_out[2U] + = ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__bypass_r) + ? vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__curr_r[2U] + : vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__head_r[2U]); + vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__core_req_arb__DOT____Vcellout__reqq_queue__data_out[3U] + = ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__bypass_r) + ? vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__curr_r[3U] + : vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__head_r[3U]); + vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__core_req_arb__DOT____Vcellout__reqq_queue__data_out[4U] + = ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__bypass_r) + ? vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__curr_r[4U] + : vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__head_r[4U]); + vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__core_req_arb__DOT____Vcellout__reqq_queue__data_out[5U] + = ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__bypass_r) + ? vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__curr_r[5U] + : vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__head_r[5U]); + vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__core_req_arb__DOT____Vcellout__reqq_queue__data_out[6U] + = ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__bypass_r) + ? vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__curr_r[6U] + : vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__head_r[6U]); + vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__core_req_arb__DOT____Vcellout__reqq_queue__data_out[7U] + = ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__bypass_r) + ? vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__curr_r[7U] + : vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__head_r[7U]); + vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__core_req_arb__DOT____Vcellout__reqq_queue__data_out[8U] + = ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__bypass_r) + ? vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__curr_r[8U] + : vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__head_r[8U]); + vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__core_req_arb__DOT____Vcellout__reqq_queue__data_out[9U] + = ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__bypass_r) + ? vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__curr_r[9U] + : vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__head_r[9U]); + vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__core_req_arb__DOT____Vcellout__reqq_queue__data_out[0U] + = ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__bypass_r) + ? vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__curr_r[0U] + : vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__head_r[0U]); + vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__core_req_arb__DOT____Vcellout__reqq_queue__data_out[1U] + = ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__bypass_r) + ? vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__curr_r[1U] + : vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__head_r[1U]); + vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__core_req_arb__DOT____Vcellout__reqq_queue__data_out[2U] + = ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__bypass_r) + ? vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__curr_r[2U] + : vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__head_r[2U]); + vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__core_req_arb__DOT____Vcellout__reqq_queue__data_out[3U] + = ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__bypass_r) + ? vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__curr_r[3U] + : vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__head_r[3U]); + vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__core_req_arb__DOT____Vcellout__reqq_queue__data_out[4U] + = ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__bypass_r) + ? vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__curr_r[4U] + : vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__head_r[4U]); + vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__core_req_arb__DOT____Vcellout__reqq_queue__data_out[5U] + = ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__bypass_r) + ? vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__curr_r[5U] + : vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__head_r[5U]); + vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__core_req_arb__DOT____Vcellout__reqq_queue__data_out[6U] + = ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__bypass_r) + ? vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__curr_r[6U] + : vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__head_r[6U]); + vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__core_req_arb__DOT____Vcellout__reqq_queue__data_out[7U] + = ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__bypass_r) + ? vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__curr_r[7U] + : vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__head_r[7U]); + vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__core_req_arb__DOT____Vcellout__reqq_queue__data_out[8U] + = ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__bypass_r) + ? vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__curr_r[8U] + : vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__head_r[8U]); + vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__core_req_arb__DOT____Vcellout__reqq_queue__data_out[9U] + = ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__bypass_r) + ? vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__curr_r[9U] + : vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__head_r[9U]); + vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__core_req_arb__DOT____Vcellout__reqq_queue__data_out[0U] + = ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__bypass_r) + ? vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__curr_r[0U] + : vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__head_r[0U]); + vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__core_req_arb__DOT____Vcellout__reqq_queue__data_out[1U] + = ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__bypass_r) + ? vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__curr_r[1U] + : vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__head_r[1U]); + vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__core_req_arb__DOT____Vcellout__reqq_queue__data_out[2U] + = ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__bypass_r) + ? vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__curr_r[2U] + : vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__head_r[2U]); + vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__core_req_arb__DOT____Vcellout__reqq_queue__data_out[3U] + = ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__bypass_r) + ? vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__curr_r[3U] + : vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__head_r[3U]); + vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__core_req_arb__DOT____Vcellout__reqq_queue__data_out[4U] + = ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__bypass_r) + ? vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__curr_r[4U] + : vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__head_r[4U]); + vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__core_req_arb__DOT____Vcellout__reqq_queue__data_out[5U] + = ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__bypass_r) + ? vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__curr_r[5U] + : vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__head_r[5U]); + vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__core_req_arb__DOT____Vcellout__reqq_queue__data_out[6U] + = ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__bypass_r) + ? vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__curr_r[6U] + : vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__head_r[6U]); + vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__core_req_arb__DOT____Vcellout__reqq_queue__data_out[7U] + = ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__bypass_r) + ? vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__curr_r[7U] + : vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__head_r[7U]); + vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__core_req_arb__DOT____Vcellout__reqq_queue__data_out[8U] + = ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__bypass_r) + ? vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__curr_r[8U] + : vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__head_r[8U]); + vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__core_req_arb__DOT____Vcellout__reqq_queue__data_out[9U] + = ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__bypass_r) + ? vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__curr_r[9U] + : vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__head_r[9U]); + vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__writedata_st1[0U][0U] + = vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__s0_1_c0__DOT__value[0U]; + vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__writedata_st1[0U][1U] + = vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__s0_1_c0__DOT__value[1U]; + vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__writedata_st1[0U][2U] + = vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__s0_1_c0__DOT__value[2U]; + vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__writedata_st1[0U][3U] + = vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__s0_1_c0__DOT__value[3U]; + vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__writedata_st1[0U][0U] + = vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__s0_1_c0__DOT__value[0U]; + vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__writedata_st1[0U][1U] + = vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__s0_1_c0__DOT__value[1U]; + vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__writedata_st1[0U][2U] + = vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__s0_1_c0__DOT__value[2U]; + vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__writedata_st1[0U][3U] + = vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__s0_1_c0__DOT__value[3U]; + vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__writedata_st1[0U][0U] + = vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__s0_1_c0__DOT__value[0U]; + vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__writedata_st1[0U][1U] + = vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__s0_1_c0__DOT__value[1U]; + vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__writedata_st1[0U][2U] + = vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__s0_1_c0__DOT__value[2U]; + vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__writedata_st1[0U][3U] + = vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__s0_1_c0__DOT__value[3U]; + vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__writedata_st1[0U][0U] + = vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__s0_1_c0__DOT__value[0U]; + vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__writedata_st1[0U][1U] + = vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__s0_1_c0__DOT__value[1U]; + vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__writedata_st1[0U][2U] + = vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__s0_1_c0__DOT__value[2U]; + vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__writedata_st1[0U][3U] + = vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__s0_1_c0__DOT__value[3U]; + vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__writeword_st1[0U] + = ((vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__s0_1_c0__DOT__value[6U] + << 0xeU) | (vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__s0_1_c0__DOT__value[5U] + >> 0x12U)); + vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__writeword_st1[0U] + = ((vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__s0_1_c0__DOT__value[6U] + << 0xeU) | (vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__s0_1_c0__DOT__value[5U] + >> 0x12U)); + vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__writeword_st1[0U] + = ((vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__s0_1_c0__DOT__value[6U] + << 0xeU) | (vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__s0_1_c0__DOT__value[5U] + >> 0x12U)); + vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__writeword_st1[0U] + = ((vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__s0_1_c0__DOT__value[6U] + << 0xeU) | (vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__s0_1_c0__DOT__value[5U] + >> 0x12U)); + vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT____Vcellout__dfp_queue__data_out[0U] + = ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__dfp_queue__DOT__genblk3__DOT__genblk2__DOT__bypass_r) + ? vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__dfp_queue__DOT__genblk3__DOT__genblk2__DOT__curr_r[0U] + : vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__dfp_queue__DOT__genblk3__DOT__genblk2__DOT__head_r[0U]); + vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT____Vcellout__dfp_queue__data_out[1U] + = ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__dfp_queue__DOT__genblk3__DOT__genblk2__DOT__bypass_r) + ? vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__dfp_queue__DOT__genblk3__DOT__genblk2__DOT__curr_r[1U] + : vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__dfp_queue__DOT__genblk3__DOT__genblk2__DOT__head_r[1U]); + vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT____Vcellout__dfp_queue__data_out[2U] + = ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__dfp_queue__DOT__genblk3__DOT__genblk2__DOT__bypass_r) + ? vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__dfp_queue__DOT__genblk3__DOT__genblk2__DOT__curr_r[2U] + : vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__dfp_queue__DOT__genblk3__DOT__genblk2__DOT__head_r[2U]); + vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT____Vcellout__dfp_queue__data_out[3U] + = ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__dfp_queue__DOT__genblk3__DOT__genblk2__DOT__bypass_r) + ? vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__dfp_queue__DOT__genblk3__DOT__genblk2__DOT__curr_r[3U] + : vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__dfp_queue__DOT__genblk3__DOT__genblk2__DOT__head_r[3U]); + vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT____Vcellout__dfp_queue__data_out[4U] + = ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__dfp_queue__DOT__genblk3__DOT__genblk2__DOT__bypass_r) + ? vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__dfp_queue__DOT__genblk3__DOT__genblk2__DOT__curr_r[4U] + : vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__dfp_queue__DOT__genblk3__DOT__genblk2__DOT__head_r[4U]); + vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT____Vcellout__dfp_queue__data_out[0U] + = ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__dfp_queue__DOT__genblk3__DOT__genblk2__DOT__bypass_r) + ? vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__dfp_queue__DOT__genblk3__DOT__genblk2__DOT__curr_r[0U] + : vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__dfp_queue__DOT__genblk3__DOT__genblk2__DOT__head_r[0U]); + vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT____Vcellout__dfp_queue__data_out[1U] + = ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__dfp_queue__DOT__genblk3__DOT__genblk2__DOT__bypass_r) + ? vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__dfp_queue__DOT__genblk3__DOT__genblk2__DOT__curr_r[1U] + : vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__dfp_queue__DOT__genblk3__DOT__genblk2__DOT__head_r[1U]); + vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT____Vcellout__dfp_queue__data_out[2U] + = ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__dfp_queue__DOT__genblk3__DOT__genblk2__DOT__bypass_r) + ? vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__dfp_queue__DOT__genblk3__DOT__genblk2__DOT__curr_r[2U] + : vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__dfp_queue__DOT__genblk3__DOT__genblk2__DOT__head_r[2U]); + vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT____Vcellout__dfp_queue__data_out[3U] + = ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__dfp_queue__DOT__genblk3__DOT__genblk2__DOT__bypass_r) + ? vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__dfp_queue__DOT__genblk3__DOT__genblk2__DOT__curr_r[3U] + : vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__dfp_queue__DOT__genblk3__DOT__genblk2__DOT__head_r[3U]); + vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT____Vcellout__dfp_queue__data_out[4U] + = ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__dfp_queue__DOT__genblk3__DOT__genblk2__DOT__bypass_r) + ? vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__dfp_queue__DOT__genblk3__DOT__genblk2__DOT__curr_r[4U] + : vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__dfp_queue__DOT__genblk3__DOT__genblk2__DOT__head_r[4U]); + vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT____Vcellout__dfp_queue__data_out[0U] + = ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__dfp_queue__DOT__genblk3__DOT__genblk2__DOT__bypass_r) + ? vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__dfp_queue__DOT__genblk3__DOT__genblk2__DOT__curr_r[0U] + : vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__dfp_queue__DOT__genblk3__DOT__genblk2__DOT__head_r[0U]); + vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT____Vcellout__dfp_queue__data_out[1U] + = ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__dfp_queue__DOT__genblk3__DOT__genblk2__DOT__bypass_r) + ? vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__dfp_queue__DOT__genblk3__DOT__genblk2__DOT__curr_r[1U] + : vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__dfp_queue__DOT__genblk3__DOT__genblk2__DOT__head_r[1U]); + vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT____Vcellout__dfp_queue__data_out[2U] + = ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__dfp_queue__DOT__genblk3__DOT__genblk2__DOT__bypass_r) + ? vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__dfp_queue__DOT__genblk3__DOT__genblk2__DOT__curr_r[2U] + : vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__dfp_queue__DOT__genblk3__DOT__genblk2__DOT__head_r[2U]); + vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT____Vcellout__dfp_queue__data_out[3U] + = ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__dfp_queue__DOT__genblk3__DOT__genblk2__DOT__bypass_r) + ? vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__dfp_queue__DOT__genblk3__DOT__genblk2__DOT__curr_r[3U] + : vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__dfp_queue__DOT__genblk3__DOT__genblk2__DOT__head_r[3U]); + vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT____Vcellout__dfp_queue__data_out[4U] + = ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__dfp_queue__DOT__genblk3__DOT__genblk2__DOT__bypass_r) + ? vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__dfp_queue__DOT__genblk3__DOT__genblk2__DOT__curr_r[4U] + : vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__dfp_queue__DOT__genblk3__DOT__genblk2__DOT__head_r[4U]); + vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT____Vcellout__dfp_queue__data_out[0U] + = ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__dfp_queue__DOT__genblk3__DOT__genblk2__DOT__bypass_r) + ? vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__dfp_queue__DOT__genblk3__DOT__genblk2__DOT__curr_r[0U] + : vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__dfp_queue__DOT__genblk3__DOT__genblk2__DOT__head_r[0U]); + vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT____Vcellout__dfp_queue__data_out[1U] + = ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__dfp_queue__DOT__genblk3__DOT__genblk2__DOT__bypass_r) + ? vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__dfp_queue__DOT__genblk3__DOT__genblk2__DOT__curr_r[1U] + : vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__dfp_queue__DOT__genblk3__DOT__genblk2__DOT__head_r[1U]); + vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT____Vcellout__dfp_queue__data_out[2U] + = ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__dfp_queue__DOT__genblk3__DOT__genblk2__DOT__bypass_r) + ? vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__dfp_queue__DOT__genblk3__DOT__genblk2__DOT__curr_r[2U] + : vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__dfp_queue__DOT__genblk3__DOT__genblk2__DOT__head_r[2U]); + vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT____Vcellout__dfp_queue__data_out[3U] + = ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__dfp_queue__DOT__genblk3__DOT__genblk2__DOT__bypass_r) + ? vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__dfp_queue__DOT__genblk3__DOT__genblk2__DOT__curr_r[3U] + : vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__dfp_queue__DOT__genblk3__DOT__genblk2__DOT__head_r[3U]); + vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT____Vcellout__dfp_queue__data_out[4U] + = ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__dfp_queue__DOT__genblk3__DOT__genblk2__DOT__bypass_r) + ? vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__dfp_queue__DOT__genblk3__DOT__genblk2__DOT__curr_r[4U] + : vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__dfp_queue__DOT__genblk3__DOT__genblk2__DOT__head_r[4U]); + vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__wsel_st1[0U] + = (3U & ((vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__s0_1_c0__DOT__value[7U] + << 0xeU) | (vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__s0_1_c0__DOT__value[6U] + >> 0x12U))); + vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__wsel_st1[0U] + = (3U & ((vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__s0_1_c0__DOT__value[7U] + << 0xeU) | (vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__s0_1_c0__DOT__value[6U] + >> 0x12U))); + vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__wsel_st1[0U] + = (3U & ((vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__s0_1_c0__DOT__value[7U] + << 0xeU) | (vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__s0_1_c0__DOT__value[6U] + >> 0x12U))); + vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__wsel_st1[0U] + = (3U & ((vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__s0_1_c0__DOT__value[7U] + << 0xeU) | (vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__s0_1_c0__DOT__value[6U] + >> 0x12U))); + vlTOPp->VX_cache__DOT__per_bank_core_req_ready + = ((0xeU & (IData)(vlTOPp->VX_cache__DOT__per_bank_core_req_ready)) + | (1U & (~ (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__full_r)))); + vlTOPp->VX_cache__DOT__per_bank_core_req_ready + = ((0xdU & (IData)(vlTOPp->VX_cache__DOT__per_bank_core_req_ready)) + | (2U & ((~ (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__full_r)) + << 1U))); + vlTOPp->VX_cache__DOT__per_bank_core_req_ready + = ((0xbU & (IData)(vlTOPp->VX_cache__DOT__per_bank_core_req_ready)) + | (4U & ((~ (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__full_r)) + << 2U))); + vlTOPp->VX_cache__DOT__per_bank_core_req_ready + = ((7U & (IData)(vlTOPp->VX_cache__DOT__per_bank_core_req_ready)) + | (8U & ((~ (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__full_r)) + << 3U))); + vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__inst_meta_st1[0U] + = (VL_ULL(0x1ffffffffffff) & (((QData)((IData)( + vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__s0_1_c0__DOT__value[6U])) + << 0x3fU) | + (((QData)((IData)( + vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__s0_1_c0__DOT__value[5U])) + << 0x1fU) | + ((QData)((IData)( + vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__s0_1_c0__DOT__value[4U])) + >> 1U)))); + vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__inst_meta_st1[0U] + = (VL_ULL(0x1ffffffffffff) & (((QData)((IData)( + vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__s0_1_c0__DOT__value[6U])) + << 0x3fU) | + (((QData)((IData)( + vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__s0_1_c0__DOT__value[5U])) + << 0x1fU) | + ((QData)((IData)( + vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__s0_1_c0__DOT__value[4U])) + >> 1U)))); + vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__inst_meta_st1[0U] + = (VL_ULL(0x1ffffffffffff) & (((QData)((IData)( + vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__s0_1_c0__DOT__value[6U])) + << 0x3fU) | + (((QData)((IData)( + vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__s0_1_c0__DOT__value[5U])) + << 0x1fU) | + ((QData)((IData)( + vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__s0_1_c0__DOT__value[4U])) + >> 1U)))); + vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__inst_meta_st1[0U] + = (VL_ULL(0x1ffffffffffff) & (((QData)((IData)( + vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__s0_1_c0__DOT__value[6U])) + << 0x3fU) | + (((QData)((IData)( + vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__s0_1_c0__DOT__value[5U])) + << 0x1fU) | + ((QData)((IData)( + vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__s0_1_c0__DOT__value[4U])) + >> 1U)))); + vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT____Vcellout__cwb_queue__data_out[0U] + = ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cwb_queue__DOT__genblk3__DOT__genblk2__DOT__bypass_r) + ? vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cwb_queue__DOT__genblk3__DOT__genblk2__DOT__curr_r[0U] + : vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cwb_queue__DOT__genblk3__DOT__genblk2__DOT__head_r[0U]); + vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT____Vcellout__cwb_queue__data_out[1U] + = ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cwb_queue__DOT__genblk3__DOT__genblk2__DOT__bypass_r) + ? vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cwb_queue__DOT__genblk3__DOT__genblk2__DOT__curr_r[1U] + : vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cwb_queue__DOT__genblk3__DOT__genblk2__DOT__head_r[1U]); + vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT____Vcellout__cwb_queue__data_out[2U] + = ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cwb_queue__DOT__genblk3__DOT__genblk2__DOT__bypass_r) + ? vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cwb_queue__DOT__genblk3__DOT__genblk2__DOT__curr_r[2U] + : vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cwb_queue__DOT__genblk3__DOT__genblk2__DOT__head_r[2U]); + vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT____Vcellout__cwb_queue__data_out[0U] + = ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__cwb_queue__DOT__genblk3__DOT__genblk2__DOT__bypass_r) + ? vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__cwb_queue__DOT__genblk3__DOT__genblk2__DOT__curr_r[0U] + : vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__cwb_queue__DOT__genblk3__DOT__genblk2__DOT__head_r[0U]); + vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT____Vcellout__cwb_queue__data_out[1U] + = ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__cwb_queue__DOT__genblk3__DOT__genblk2__DOT__bypass_r) + ? vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__cwb_queue__DOT__genblk3__DOT__genblk2__DOT__curr_r[1U] + : vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__cwb_queue__DOT__genblk3__DOT__genblk2__DOT__head_r[1U]); + vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT____Vcellout__cwb_queue__data_out[2U] + = ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__cwb_queue__DOT__genblk3__DOT__genblk2__DOT__bypass_r) + ? vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__cwb_queue__DOT__genblk3__DOT__genblk2__DOT__curr_r[2U] + : vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__cwb_queue__DOT__genblk3__DOT__genblk2__DOT__head_r[2U]); + vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT____Vcellout__cwb_queue__data_out[0U] + = ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__cwb_queue__DOT__genblk3__DOT__genblk2__DOT__bypass_r) + ? vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__cwb_queue__DOT__genblk3__DOT__genblk2__DOT__curr_r[0U] + : vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__cwb_queue__DOT__genblk3__DOT__genblk2__DOT__head_r[0U]); + vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT____Vcellout__cwb_queue__data_out[1U] + = ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__cwb_queue__DOT__genblk3__DOT__genblk2__DOT__bypass_r) + ? vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__cwb_queue__DOT__genblk3__DOT__genblk2__DOT__curr_r[1U] + : vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__cwb_queue__DOT__genblk3__DOT__genblk2__DOT__head_r[1U]); + vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT____Vcellout__cwb_queue__data_out[2U] + = ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__cwb_queue__DOT__genblk3__DOT__genblk2__DOT__bypass_r) + ? vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__cwb_queue__DOT__genblk3__DOT__genblk2__DOT__curr_r[2U] + : vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__cwb_queue__DOT__genblk3__DOT__genblk2__DOT__head_r[2U]); + vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT____Vcellout__cwb_queue__data_out[0U] + = ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cwb_queue__DOT__genblk3__DOT__genblk2__DOT__bypass_r) + ? vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cwb_queue__DOT__genblk3__DOT__genblk2__DOT__curr_r[0U] + : vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cwb_queue__DOT__genblk3__DOT__genblk2__DOT__head_r[0U]); + vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT____Vcellout__cwb_queue__data_out[1U] + = ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cwb_queue__DOT__genblk3__DOT__genblk2__DOT__bypass_r) + ? vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cwb_queue__DOT__genblk3__DOT__genblk2__DOT__curr_r[1U] + : vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cwb_queue__DOT__genblk3__DOT__genblk2__DOT__head_r[1U]); + vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT____Vcellout__cwb_queue__data_out[2U] + = ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cwb_queue__DOT__genblk3__DOT__genblk2__DOT__bypass_r) + ? vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cwb_queue__DOT__genblk3__DOT__genblk2__DOT__curr_r[2U] + : vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cwb_queue__DOT__genblk3__DOT__genblk2__DOT__head_r[2U]); + vlTOPp->__Vtableidx5 = vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__core_req_arb__DOT__use_per_valids; + vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__core_req_arb__DOT__qual_request_index + = vlTOPp->__Vtable5_VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__core_req_arb__DOT__qual_request_index + [vlTOPp->__Vtableidx5]; + vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__core_req_arb__DOT__qual_has_request + = vlTOPp->__Vtable5_VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__core_req_arb__DOT__qual_has_request + [vlTOPp->__Vtableidx5]; + vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__core_req_arb__DOT__sel_bank__DOT__genblk2__DOT__priority_encoder__DOT__i + = vlTOPp->__Vtable5_VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__core_req_arb__DOT__sel_bank__DOT__genblk2__DOT__priority_encoder__DOT__i + [vlTOPp->__Vtableidx5]; + vlTOPp->__Vtableidx6 = vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__core_req_arb__DOT__use_per_valids; + vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__core_req_arb__DOT__qual_request_index + = vlTOPp->__Vtable6_VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__core_req_arb__DOT__qual_request_index + [vlTOPp->__Vtableidx6]; + vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__core_req_arb__DOT__qual_has_request + = vlTOPp->__Vtable6_VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__core_req_arb__DOT__qual_has_request + [vlTOPp->__Vtableidx6]; + vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__core_req_arb__DOT__sel_bank__DOT__genblk2__DOT__priority_encoder__DOT__i + = vlTOPp->__Vtable6_VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__core_req_arb__DOT__sel_bank__DOT__genblk2__DOT__priority_encoder__DOT__i + [vlTOPp->__Vtableidx6]; + vlTOPp->__Vtableidx7 = vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__core_req_arb__DOT__use_per_valids; + vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__core_req_arb__DOT__qual_request_index + = vlTOPp->__Vtable7_VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__core_req_arb__DOT__qual_request_index + [vlTOPp->__Vtableidx7]; + vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__core_req_arb__DOT__qual_has_request + = vlTOPp->__Vtable7_VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__core_req_arb__DOT__qual_has_request + [vlTOPp->__Vtableidx7]; + vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__core_req_arb__DOT__sel_bank__DOT__genblk2__DOT__priority_encoder__DOT__i + = vlTOPp->__Vtable7_VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__core_req_arb__DOT__sel_bank__DOT__genblk2__DOT__priority_encoder__DOT__i + [vlTOPp->__Vtableidx7]; + vlTOPp->__Vtableidx8 = vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__core_req_arb__DOT__use_per_valids; + vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__core_req_arb__DOT__qual_request_index + = vlTOPp->__Vtable8_VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__core_req_arb__DOT__qual_request_index + [vlTOPp->__Vtableidx8]; + vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__core_req_arb__DOT__qual_has_request + = vlTOPp->__Vtable8_VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__core_req_arb__DOT__qual_has_request + [vlTOPp->__Vtableidx8]; + vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__core_req_arb__DOT__sel_bank__DOT__genblk2__DOT__priority_encoder__DOT__i + = vlTOPp->__Vtable8_VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__core_req_arb__DOT__sel_bank__DOT__genblk2__DOT__priority_encoder__DOT__i + [vlTOPp->__Vtableidx8]; + vlTOPp->VX_cache__DOT__cache_dram_req_arb__DOT__dram_fill_arb__DOT____Vcellout__dfqq_queue__data_out[0U] + = ((IData)(vlTOPp->VX_cache__DOT__cache_dram_req_arb__DOT__dram_fill_arb__DOT__dfqq_queue__DOT__genblk3__DOT__genblk2__DOT__bypass_r) + ? vlTOPp->VX_cache__DOT__cache_dram_req_arb__DOT__dram_fill_arb__DOT__dfqq_queue__DOT__genblk3__DOT__genblk2__DOT__curr_r[0U] + : vlTOPp->VX_cache__DOT__cache_dram_req_arb__DOT__dram_fill_arb__DOT__dfqq_queue__DOT__genblk3__DOT__genblk2__DOT__head_r[0U]); + vlTOPp->VX_cache__DOT__cache_dram_req_arb__DOT__dram_fill_arb__DOT____Vcellout__dfqq_queue__data_out[1U] + = ((IData)(vlTOPp->VX_cache__DOT__cache_dram_req_arb__DOT__dram_fill_arb__DOT__dfqq_queue__DOT__genblk3__DOT__genblk2__DOT__bypass_r) + ? vlTOPp->VX_cache__DOT__cache_dram_req_arb__DOT__dram_fill_arb__DOT__dfqq_queue__DOT__genblk3__DOT__genblk2__DOT__curr_r[1U] + : vlTOPp->VX_cache__DOT__cache_dram_req_arb__DOT__dram_fill_arb__DOT__dfqq_queue__DOT__genblk3__DOT__genblk2__DOT__head_r[1U]); + vlTOPp->VX_cache__DOT__cache_dram_req_arb__DOT__dram_fill_arb__DOT____Vcellout__dfqq_queue__data_out[2U] + = ((IData)(vlTOPp->VX_cache__DOT__cache_dram_req_arb__DOT__dram_fill_arb__DOT__dfqq_queue__DOT__genblk3__DOT__genblk2__DOT__bypass_r) + ? vlTOPp->VX_cache__DOT__cache_dram_req_arb__DOT__dram_fill_arb__DOT__dfqq_queue__DOT__genblk3__DOT__genblk2__DOT__curr_r[2U] + : vlTOPp->VX_cache__DOT__cache_dram_req_arb__DOT__dram_fill_arb__DOT__dfqq_queue__DOT__genblk3__DOT__genblk2__DOT__head_r[2U]); + vlTOPp->VX_cache__DOT__cache_dram_req_arb__DOT__dram_fill_arb__DOT____Vcellout__dfqq_queue__data_out[3U] + = ((IData)(vlTOPp->VX_cache__DOT__cache_dram_req_arb__DOT__dram_fill_arb__DOT__dfqq_queue__DOT__genblk3__DOT__genblk2__DOT__bypass_r) + ? vlTOPp->VX_cache__DOT__cache_dram_req_arb__DOT__dram_fill_arb__DOT__dfqq_queue__DOT__genblk3__DOT__genblk2__DOT__curr_r[3U] + : vlTOPp->VX_cache__DOT__cache_dram_req_arb__DOT__dram_fill_arb__DOT__dfqq_queue__DOT__genblk3__DOT__genblk2__DOT__head_r[3U]); + vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__snp_invalidate_st1[0U] + = (1U & (vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__s0_1_c0__DOT__value[7U] + >> 0x10U)); + vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__snp_invalidate_st1[0U] + = (1U & (vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__s0_1_c0__DOT__value[7U] + >> 0x10U)); + vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__snp_invalidate_st1[0U] + = (1U & (vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__s0_1_c0__DOT__value[7U] + >> 0x10U)); + vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__snp_invalidate_st1[0U] + = (1U & (vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__s0_1_c0__DOT__value[7U] + >> 0x10U)); + vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cache_miss_resrv__DOT__dequeue_possible + = (1U & (((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cache_miss_resrv__DOT__valid_table) + & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cache_miss_resrv__DOT__ready_table)) + >> (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr))); + vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__cache_miss_resrv__DOT__dequeue_possible + = (1U & (((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__cache_miss_resrv__DOT__valid_table) + & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__cache_miss_resrv__DOT__ready_table)) + >> (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr))); + vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__cache_miss_resrv__DOT__dequeue_possible + = (1U & (((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__cache_miss_resrv__DOT__valid_table) + & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__cache_miss_resrv__DOT__ready_table)) + >> (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr))); + vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cache_miss_resrv__DOT__dequeue_possible + = (1U & (((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cache_miss_resrv__DOT__valid_table) + & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cache_miss_resrv__DOT__ready_table)) + >> (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr))); + vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__is_snp_st1[0U] + = (1U & (vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__s0_1_c0__DOT__value[7U] + >> 0x11U)); + vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__is_snp_st1[0U] + = (1U & (vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__s0_1_c0__DOT__value[7U] + >> 0x11U)); + vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__is_snp_st1[0U] + = (1U & (vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__s0_1_c0__DOT__value[7U] + >> 0x11U)); + vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__is_snp_st1[0U] + = (1U & (vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__s0_1_c0__DOT__value[7U] + >> 0x11U)); + vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__is_mrvq_st1[0U] + = (1U & (vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__s0_1_c0__DOT__value[7U] + >> 0x12U)); + vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__is_mrvq_st1[0U] + = (1U & (vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__s0_1_c0__DOT__value[7U] + >> 0x12U)); + vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__is_mrvq_st1[0U] + = (1U & (vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__s0_1_c0__DOT__value[7U] + >> 0x12U)); + vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__is_mrvq_st1[0U] + = (1U & (vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__s0_1_c0__DOT__value[7U] + >> 0x12U)); + vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__is_fill_st1[0U] + = (1U & vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__s0_1_c0__DOT__value[4U]); + vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__is_fill_st1[0U] + = (1U & vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__s0_1_c0__DOT__value[4U]); + vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__is_fill_st1[0U] + = (1U & vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__s0_1_c0__DOT__value[4U]); + vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__is_fill_st1[0U] + = (1U & vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__s0_1_c0__DOT__value[4U]); + vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__valid_st1[0U] + = (1U & (vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__s0_1_c0__DOT__value[7U] + >> 0xeU)); + vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__valid_st1[0U] + = (1U & (vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__s0_1_c0__DOT__value[7U] + >> 0xeU)); + vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__valid_st1[0U] + = (1U & (vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__s0_1_c0__DOT__value[7U] + >> 0xeU)); + vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__valid_st1[0U] + = (1U & (vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__s0_1_c0__DOT__value[7U] + >> 0xeU)); + vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT____Vcellout__dwb_queue__data_out[0U] + = ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__genblk2__DOT__bypass_r) + ? vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__genblk2__DOT__curr_r[0U] + : vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__genblk2__DOT__head_r[0U]); + vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT____Vcellout__dwb_queue__data_out[1U] + = ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__genblk2__DOT__bypass_r) + ? vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__genblk2__DOT__curr_r[1U] + : vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__genblk2__DOT__head_r[1U]); + vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT____Vcellout__dwb_queue__data_out[2U] + = ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__genblk2__DOT__bypass_r) + ? vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__genblk2__DOT__curr_r[2U] + : vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__genblk2__DOT__head_r[2U]); + vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT____Vcellout__dwb_queue__data_out[3U] + = ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__genblk2__DOT__bypass_r) + ? vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__genblk2__DOT__curr_r[3U] + : vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__genblk2__DOT__head_r[3U]); + vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT____Vcellout__dwb_queue__data_out[4U] + = ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__genblk2__DOT__bypass_r) + ? vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__genblk2__DOT__curr_r[4U] + : vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__genblk2__DOT__head_r[4U]); + vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT____Vcellout__dwb_queue__data_out[5U] + = ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__genblk2__DOT__bypass_r) + ? vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__genblk2__DOT__curr_r[5U] + : vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__genblk2__DOT__head_r[5U]); + vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT____Vcellout__dwb_queue__data_out[6U] + = ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__genblk2__DOT__bypass_r) + ? vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__genblk2__DOT__curr_r[6U] + : vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__genblk2__DOT__head_r[6U]); + vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT____Vcellout__dwb_queue__data_out[0U] + = ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__genblk2__DOT__bypass_r) + ? vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__genblk2__DOT__curr_r[0U] + : vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__genblk2__DOT__head_r[0U]); + vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT____Vcellout__dwb_queue__data_out[1U] + = ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__genblk2__DOT__bypass_r) + ? vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__genblk2__DOT__curr_r[1U] + : vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__genblk2__DOT__head_r[1U]); + vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT____Vcellout__dwb_queue__data_out[2U] + = ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__genblk2__DOT__bypass_r) + ? vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__genblk2__DOT__curr_r[2U] + : vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__genblk2__DOT__head_r[2U]); + vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT____Vcellout__dwb_queue__data_out[3U] + = ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__genblk2__DOT__bypass_r) + ? vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__genblk2__DOT__curr_r[3U] + : vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__genblk2__DOT__head_r[3U]); + vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT____Vcellout__dwb_queue__data_out[4U] + = ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__genblk2__DOT__bypass_r) + ? vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__genblk2__DOT__curr_r[4U] + : vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__genblk2__DOT__head_r[4U]); + vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT____Vcellout__dwb_queue__data_out[5U] + = ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__genblk2__DOT__bypass_r) + ? vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__genblk2__DOT__curr_r[5U] + : vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__genblk2__DOT__head_r[5U]); + vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT____Vcellout__dwb_queue__data_out[6U] + = ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__genblk2__DOT__bypass_r) + ? vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__genblk2__DOT__curr_r[6U] + : vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__genblk2__DOT__head_r[6U]); + vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT____Vcellout__dwb_queue__data_out[0U] + = ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__genblk2__DOT__bypass_r) + ? vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__genblk2__DOT__curr_r[0U] + : vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__genblk2__DOT__head_r[0U]); + vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT____Vcellout__dwb_queue__data_out[1U] + = ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__genblk2__DOT__bypass_r) + ? vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__genblk2__DOT__curr_r[1U] + : vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__genblk2__DOT__head_r[1U]); + vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT____Vcellout__dwb_queue__data_out[2U] + = ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__genblk2__DOT__bypass_r) + ? vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__genblk2__DOT__curr_r[2U] + : vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__genblk2__DOT__head_r[2U]); + vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT____Vcellout__dwb_queue__data_out[3U] + = ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__genblk2__DOT__bypass_r) + ? vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__genblk2__DOT__curr_r[3U] + : vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__genblk2__DOT__head_r[3U]); + vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT____Vcellout__dwb_queue__data_out[4U] + = ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__genblk2__DOT__bypass_r) + ? vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__genblk2__DOT__curr_r[4U] + : vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__genblk2__DOT__head_r[4U]); + vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT____Vcellout__dwb_queue__data_out[5U] + = ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__genblk2__DOT__bypass_r) + ? vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__genblk2__DOT__curr_r[5U] + : vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__genblk2__DOT__head_r[5U]); + vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT____Vcellout__dwb_queue__data_out[6U] + = ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__genblk2__DOT__bypass_r) + ? vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__genblk2__DOT__curr_r[6U] + : vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__genblk2__DOT__head_r[6U]); + vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT____Vcellout__dwb_queue__data_out[0U] + = ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__genblk2__DOT__bypass_r) + ? vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__genblk2__DOT__curr_r[0U] + : vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__genblk2__DOT__head_r[0U]); + vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT____Vcellout__dwb_queue__data_out[1U] + = ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__genblk2__DOT__bypass_r) + ? vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__genblk2__DOT__curr_r[1U] + : vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__genblk2__DOT__head_r[1U]); + vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT____Vcellout__dwb_queue__data_out[2U] + = ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__genblk2__DOT__bypass_r) + ? vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__genblk2__DOT__curr_r[2U] + : vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__genblk2__DOT__head_r[2U]); + vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT____Vcellout__dwb_queue__data_out[3U] + = ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__genblk2__DOT__bypass_r) + ? vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__genblk2__DOT__curr_r[3U] + : vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__genblk2__DOT__head_r[3U]); + vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT____Vcellout__dwb_queue__data_out[4U] + = ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__genblk2__DOT__bypass_r) + ? vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__genblk2__DOT__curr_r[4U] + : vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__genblk2__DOT__head_r[4U]); + vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT____Vcellout__dwb_queue__data_out[5U] + = ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__genblk2__DOT__bypass_r) + ? vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__genblk2__DOT__curr_r[5U] + : vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__genblk2__DOT__head_r[5U]); + vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT____Vcellout__dwb_queue__data_out[6U] + = ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__genblk2__DOT__bypass_r) + ? vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__genblk2__DOT__curr_r[6U] + : vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__genblk2__DOT__head_r[6U]); + vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__addr_st1[0U] + = (0x3ffffffU & ((vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__s0_1_c0__DOT__value[7U] + << 0xcU) | (vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__s0_1_c0__DOT__value[6U] + >> 0x14U))); + vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__addr_st1[0U] + = (0x3ffffffU & ((vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__s0_1_c0__DOT__value[7U] + << 0xcU) | (vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__s0_1_c0__DOT__value[6U] + >> 0x14U))); + vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__addr_st1[0U] + = (0x3ffffffU & ((vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__s0_1_c0__DOT__value[7U] + << 0xcU) | (vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__s0_1_c0__DOT__value[6U] + >> 0x14U))); + vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__addr_st1[0U] + = (0x3ffffffU & ((vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__s0_1_c0__DOT__value[7U] + << 0xcU) | (vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__s0_1_c0__DOT__value[6U] + >> 0x14U))); + vlTOPp->VX_cache__DOT__per_bank_core_rsp_valid + = ((0xeU & (IData)(vlTOPp->VX_cache__DOT__per_bank_core_rsp_valid)) + | (1U & (~ (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cwb_queue__DOT__genblk3__DOT__genblk2__DOT__empty_r)))); + vlTOPp->VX_cache__DOT__per_bank_core_rsp_valid + = ((0xdU & (IData)(vlTOPp->VX_cache__DOT__per_bank_core_rsp_valid)) + | (2U & ((~ (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__cwb_queue__DOT__genblk3__DOT__genblk2__DOT__empty_r)) + << 1U))); + vlTOPp->VX_cache__DOT__per_bank_core_rsp_valid + = ((0xbU & (IData)(vlTOPp->VX_cache__DOT__per_bank_core_rsp_valid)) + | (4U & ((~ (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__cwb_queue__DOT__genblk3__DOT__genblk2__DOT__empty_r)) + << 2U))); + vlTOPp->VX_cache__DOT__per_bank_core_rsp_valid + = ((7U & (IData)(vlTOPp->VX_cache__DOT__per_bank_core_rsp_valid)) + | (8U & ((~ (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cwb_queue__DOT__genblk3__DOT__genblk2__DOT__empty_r)) + << 3U))); + vlTOPp->VX_cache__DOT__cache_core_rsp_merge__DOT__sel_bank__DOT__genblk2__DOT__refill + = (0U == (IData)(vlTOPp->VX_cache__DOT__cache_core_rsp_merge__DOT__sel_bank__DOT__genblk2__DOT__requests_use)); + vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT____Vcellinp__cwb_queue__data_in[0U] + = ((vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__st_1e_2__DOT__value[7U] + << 9U) | (vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__st_1e_2__DOT__value[6U] + >> 0x17U)); + vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT____Vcellinp__cwb_queue__data_in[1U] + = (IData)((VL_ULL(0x3ffffffffff) & (((QData)((IData)( + vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__st_1e_2__DOT__value[2U])) + << 0x39U) + | (((QData)((IData)( + vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__st_1e_2__DOT__value[1U])) + << 0x19U) + | ((QData)((IData)( + vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__st_1e_2__DOT__value[0U])) + >> 7U))))); + vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT____Vcellinp__cwb_queue__data_in[2U] + = ((0xc00U & (vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__st_1e_2__DOT__value[0U] + << 0xaU)) | (IData)(((VL_ULL(0x3ffffffffff) + & (((QData)((IData)( + vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__st_1e_2__DOT__value[2U])) + << 0x39U) + | (((QData)((IData)( + vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__st_1e_2__DOT__value[1U])) + << 0x19U) + | ((QData)((IData)( + vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__st_1e_2__DOT__value[0U])) + >> 7U)))) + >> 0x20U))); + vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT____Vcellinp__cwb_queue__data_in[0U] + = ((vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__st_1e_2__DOT__value[7U] + << 9U) | (vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__st_1e_2__DOT__value[6U] + >> 0x17U)); + vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT____Vcellinp__cwb_queue__data_in[1U] + = (IData)((VL_ULL(0x3ffffffffff) & (((QData)((IData)( + vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__st_1e_2__DOT__value[2U])) + << 0x39U) + | (((QData)((IData)( + vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__st_1e_2__DOT__value[1U])) + << 0x19U) + | ((QData)((IData)( + vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__st_1e_2__DOT__value[0U])) + >> 7U))))); + vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT____Vcellinp__cwb_queue__data_in[2U] + = ((0xc00U & (vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__st_1e_2__DOT__value[0U] + << 0xaU)) | (IData)(((VL_ULL(0x3ffffffffff) + & (((QData)((IData)( + vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__st_1e_2__DOT__value[2U])) + << 0x39U) + | (((QData)((IData)( + vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__st_1e_2__DOT__value[1U])) + << 0x19U) + | ((QData)((IData)( + vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__st_1e_2__DOT__value[0U])) + >> 7U)))) + >> 0x20U))); + vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT____Vcellinp__cwb_queue__data_in[0U] + = ((vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__st_1e_2__DOT__value[7U] + << 9U) | (vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__st_1e_2__DOT__value[6U] + >> 0x17U)); + vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT____Vcellinp__cwb_queue__data_in[1U] + = (IData)((VL_ULL(0x3ffffffffff) & (((QData)((IData)( + vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__st_1e_2__DOT__value[2U])) + << 0x39U) + | (((QData)((IData)( + vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__st_1e_2__DOT__value[1U])) + << 0x19U) + | ((QData)((IData)( + vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__st_1e_2__DOT__value[0U])) + >> 7U))))); + vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT____Vcellinp__cwb_queue__data_in[2U] + = ((0xc00U & (vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__st_1e_2__DOT__value[0U] + << 0xaU)) | (IData)(((VL_ULL(0x3ffffffffff) + & (((QData)((IData)( + vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__st_1e_2__DOT__value[2U])) + << 0x39U) + | (((QData)((IData)( + vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__st_1e_2__DOT__value[1U])) + << 0x19U) + | ((QData)((IData)( + vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__st_1e_2__DOT__value[0U])) + >> 7U)))) + >> 0x20U))); + vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT____Vcellinp__cwb_queue__data_in[0U] + = ((vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__st_1e_2__DOT__value[7U] + << 9U) | (vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__st_1e_2__DOT__value[6U] + >> 0x17U)); + vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT____Vcellinp__cwb_queue__data_in[1U] + = (IData)((VL_ULL(0x3ffffffffff) & (((QData)((IData)( + vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__st_1e_2__DOT__value[2U])) + << 0x39U) + | (((QData)((IData)( + vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__st_1e_2__DOT__value[1U])) + << 0x19U) + | ((QData)((IData)( + vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__st_1e_2__DOT__value[0U])) + >> 7U))))); + vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT____Vcellinp__cwb_queue__data_in[2U] + = ((0xc00U & (vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__st_1e_2__DOT__value[0U] + << 0xaU)) | (IData)(((VL_ULL(0x3ffffffffff) + & (((QData)((IData)( + vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__st_1e_2__DOT__value[2U])) + << 0x39U) + | (((QData)((IData)( + vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__st_1e_2__DOT__value[1U])) + << 0x19U) + | ((QData)((IData)( + vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__st_1e_2__DOT__value[0U])) + >> 7U)))) + >> 0x20U))); + vlTOPp->VX_cache__DOT__per_bank_dram_fill_req_addr[0U] + = ((0xf0000000U & vlTOPp->VX_cache__DOT__per_bank_dram_fill_req_addr[0U]) + | (0xffffffcU & ((vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__st_1e_2__DOT__value[9U] + << 9U) | (0x1fcU & (vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__st_1e_2__DOT__value[8U] + >> 0x17U))))); + vlTOPp->VX_cache__DOT__per_bank_dram_fill_req_addr[0U] + = ((0xfffffffU & vlTOPp->VX_cache__DOT__per_bank_dram_fill_req_addr[0U]) + | (0xf0000000U & (0x10000000U | (0xc0000000U + & (vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__st_1e_2__DOT__value[8U] + << 5U))))); + vlTOPp->VX_cache__DOT__per_bank_dram_fill_req_addr[1U] + = ((0xff000000U & vlTOPp->VX_cache__DOT__per_bank_dram_fill_req_addr[1U]) + | (0xffffffU & ((0xfffffe0U & (vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__st_1e_2__DOT__value[9U] + << 5U)) | + (0x1fU & (vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__st_1e_2__DOT__value[8U] + >> 0x1bU))))); + vlTOPp->VX_cache__DOT__per_bank_dram_fill_req_addr[1U] + = ((0xffffffU & vlTOPp->VX_cache__DOT__per_bank_dram_fill_req_addr[1U]) + | (0xff000000U & (0x2000000U | (0xfc000000U + & (vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__st_1e_2__DOT__value[8U] + << 1U))))); + vlTOPp->VX_cache__DOT__per_bank_dram_fill_req_addr[2U] + = ((0xfff00000U & vlTOPp->VX_cache__DOT__per_bank_dram_fill_req_addr[2U]) + | (0xfffffU & ((0xfffffeU & (vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__st_1e_2__DOT__value[9U] + << 1U)) | (1U + & (vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__st_1e_2__DOT__value[8U] + >> 0x1fU))))); + vlTOPp->VX_cache__DOT__per_bank_dram_fill_req_addr[2U] + = ((0xfffffU & vlTOPp->VX_cache__DOT__per_bank_dram_fill_req_addr[2U]) + | (0xfff00000U & (0x300000U | (0xffc00000U + & ((vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__st_1e_2__DOT__value[9U] + << 0x1dU) + | (0x1fc00000U + & (vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__st_1e_2__DOT__value[8U] + >> 3U))))))); + vlTOPp->VX_cache__DOT__per_bank_dram_fill_req_addr[3U] + = (0xffffU & (vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__st_1e_2__DOT__value[9U] + >> 3U)); + vlTOPp->__Vtableidx3 = vlTOPp->VX_cache__DOT__cache_core_rsp_merge__DOT__sel_bank__DOT__genblk2__DOT__requests_use; + vlTOPp->VX_cache__DOT__cache_core_rsp_merge__DOT__main_bank_index + = vlTOPp->__Vtable3_VX_cache__DOT__cache_core_rsp_merge__DOT__main_bank_index + [vlTOPp->__Vtableidx3]; + vlTOPp->VX_cache__DOT__cache_core_rsp_merge__DOT__sel_bank__DOT__grant_valid + = vlTOPp->__Vtable3_VX_cache__DOT__cache_core_rsp_merge__DOT__sel_bank__DOT__grant_valid + [vlTOPp->__Vtableidx3]; + vlTOPp->VX_cache__DOT__cache_core_rsp_merge__DOT__sel_bank__DOT__genblk2__DOT__priority_encoder__DOT__i + = vlTOPp->__Vtable3_VX_cache__DOT__cache_core_rsp_merge__DOT__sel_bank__DOT__genblk2__DOT__priority_encoder__DOT__i + [vlTOPp->__Vtableidx3]; + vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cwbq_push_unqual + = (1U & ((((vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__st_1e_2__DOT__value[9U] + >> 0x13U) & (~ (vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__st_1e_2__DOT__value[2U] + >> 2U))) & (~ ( + vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__st_1e_2__DOT__value[9U] + >> 0x14U))) + & (~ (vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__st_1e_2__DOT__value[9U] + >> 0x17U)))); + vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__cwbq_push_unqual + = (1U & ((((vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__st_1e_2__DOT__value[9U] + >> 0x13U) & (~ (vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__st_1e_2__DOT__value[2U] + >> 2U))) & (~ ( + vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__st_1e_2__DOT__value[9U] + >> 0x14U))) + & (~ (vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__st_1e_2__DOT__value[9U] + >> 0x17U)))); + vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__cwbq_push_unqual + = (1U & ((((vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__st_1e_2__DOT__value[9U] + >> 0x13U) & (~ (vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__st_1e_2__DOT__value[2U] + >> 2U))) & (~ ( + vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__st_1e_2__DOT__value[9U] + >> 0x14U))) + & (~ (vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__st_1e_2__DOT__value[9U] + >> 0x17U)))); + vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cwbq_push_unqual + = (1U & ((((vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__st_1e_2__DOT__value[9U] + >> 0x13U) & (~ (vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__st_1e_2__DOT__value[2U] + >> 2U))) & (~ ( + vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__st_1e_2__DOT__value[9U] + >> 0x14U))) + & (~ (vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__st_1e_2__DOT__value[9U] + >> 0x17U)))); + vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__dwbq_is_snp_in + = (1U & (((vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__st_1e_2__DOT__value[9U] + >> 0x17U) & (vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__st_1e_2__DOT__value[9U] + >> 0x13U)) & (~ (vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__st_1e_2__DOT__value[9U] + >> 0x18U)))); + vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__dwbq_is_dwb_in + = (1U & ((((vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__st_1e_2__DOT__value[9U] + >> 0x13U) & (vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__st_1e_2__DOT__value[2U] + >> 2U)) & (vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__st_1e_2__DOT__value[2U] + >> 1U)) + | (vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__st_1e_2__DOT__value[9U] + >> 0x15U))); + vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__dwbq_is_snp_in + = (1U & (((vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__st_1e_2__DOT__value[9U] + >> 0x17U) & (vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__st_1e_2__DOT__value[9U] + >> 0x13U)) & (~ (vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__st_1e_2__DOT__value[9U] + >> 0x18U)))); + vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__dwbq_is_dwb_in + = (1U & ((((vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__st_1e_2__DOT__value[9U] + >> 0x13U) & (vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__st_1e_2__DOT__value[2U] + >> 2U)) & (vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__st_1e_2__DOT__value[2U] + >> 1U)) + | (vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__st_1e_2__DOT__value[9U] + >> 0x15U))); + vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__dwbq_is_snp_in + = (1U & (((vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__st_1e_2__DOT__value[9U] + >> 0x17U) & (vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__st_1e_2__DOT__value[9U] + >> 0x13U)) & (~ (vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__st_1e_2__DOT__value[9U] + >> 0x18U)))); + vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__dwbq_is_dwb_in + = (1U & ((((vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__st_1e_2__DOT__value[9U] + >> 0x13U) & (vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__st_1e_2__DOT__value[2U] + >> 2U)) & (vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__st_1e_2__DOT__value[2U] + >> 1U)) + | (vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__st_1e_2__DOT__value[9U] + >> 0x15U))); + vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__dwbq_is_snp_in + = (1U & (((vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__st_1e_2__DOT__value[9U] + >> 0x17U) & (vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__st_1e_2__DOT__value[9U] + >> 0x13U)) & (~ (vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__st_1e_2__DOT__value[9U] + >> 0x18U)))); + vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__dwbq_is_dwb_in + = (1U & ((((vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__st_1e_2__DOT__value[9U] + >> 0x13U) & (vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__st_1e_2__DOT__value[2U] + >> 2U)) & (vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__st_1e_2__DOT__value[2U] + >> 1U)) + | (vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__st_1e_2__DOT__value[9U] + >> 0x15U))); + vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__miss_add_because_miss + = (1U & (((vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__st_1e_2__DOT__value[9U] + >> 0x13U) & (~ (vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__st_1e_2__DOT__value[9U] + >> 0x17U))) & (vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__st_1e_2__DOT__value[2U] + >> 2U))); + vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__miss_add_because_miss + = (1U & (((vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__st_1e_2__DOT__value[9U] + >> 0x13U) & (~ (vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__st_1e_2__DOT__value[9U] + >> 0x17U))) & (vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__st_1e_2__DOT__value[2U] + >> 2U))); + vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__miss_add_because_miss + = (1U & (((vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__st_1e_2__DOT__value[9U] + >> 0x13U) & (~ (vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__st_1e_2__DOT__value[9U] + >> 0x17U))) & (vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__st_1e_2__DOT__value[2U] + >> 2U))); + vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__miss_add_because_miss + = (1U & (((vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__st_1e_2__DOT__value[9U] + >> 0x13U) & (~ (vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__st_1e_2__DOT__value[9U] + >> 0x17U))) & (vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__st_1e_2__DOT__value[2U] + >> 2U))); + vlTOPp->VX_cache__DOT__cache_dram_req_arb__DOT__prfqq__DOT__pfq_queue__DOT__reading + = ((IData)(vlTOPp->VX_cache__DOT__cache_dram_req_arb__DOT__prfqq__DOT__update_use) + & (IData)(vlTOPp->VX_cache__DOT__cache_dram_req_arb__DOT__prfqq__DOT__pfq_queue__DOT__size_r)); + vlTOPp->dram_rsp_ready = (0U != (IData)(vlTOPp->VX_cache__DOT__per_bank_dram_fill_rsp_ready)); + vlTOPp->snp_req_ready = (1U & ((IData)(vlTOPp->VX_cache__DOT__per_bank_snp_req_ready) + >> (3U & vlTOPp->snp_req_addr))); + vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__core_req_arb__DOT__out_empty + = (1U & ((~ (IData)((0U != (0xfU & (vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__core_req_arb__DOT____Vcellout__reqq_queue__data_out[9U] + >> 0x16U))))) + | (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__empty_r))); + vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__core_req_arb__DOT__out_empty + = (1U & ((~ (IData)((0U != (0xfU & (vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__core_req_arb__DOT____Vcellout__reqq_queue__data_out[9U] + >> 0x16U))))) + | (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__empty_r))); + vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__core_req_arb__DOT__out_empty + = (1U & ((~ (IData)((0U != (0xfU & (vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__core_req_arb__DOT____Vcellout__reqq_queue__data_out[9U] + >> 0x16U))))) + | (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__empty_r))); + vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__core_req_arb__DOT__out_empty + = (1U & ((~ (IData)((0U != (0xfU & (vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__core_req_arb__DOT____Vcellout__reqq_queue__data_out[9U] + >> 0x16U))))) + | (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__empty_r))); + vlTOPp->core_req_ready = (0xfU == ((IData)(vlTOPp->VX_cache__DOT__per_bank_core_req_ready) + | (IData)(vlTOPp->VX_cache__DOT__cache_core_req_bank_sel__DOT__genblk2__DOT__per_bank_ready_sel))); + vlTOPp->VX_cache__DOT__per_bank_core_rsp_data[0U] + = vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT____Vcellout__cwb_queue__data_out[0U]; + vlTOPp->VX_cache__DOT__per_bank_core_rsp_tid = + ((0xfcU & (IData)(vlTOPp->VX_cache__DOT__per_bank_core_rsp_tid)) + | (3U & (vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT____Vcellout__cwb_queue__data_out[2U] + >> 0xaU))); + vlTOPp->VX_cache__DOT__per_bank_core_rsp_tag[0U] + = (IData)((VL_ULL(0x3ffffffffff) & (((QData)((IData)( + vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT____Vcellout__cwb_queue__data_out[2U])) + << 0x20U) + | (QData)((IData)( + vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT____Vcellout__cwb_queue__data_out[1U]))))); + vlTOPp->VX_cache__DOT__per_bank_core_rsp_tag[1U] + = ((0xfffffc00U & vlTOPp->VX_cache__DOT__per_bank_core_rsp_tag[1U]) + | (IData)(((VL_ULL(0x3ffffffffff) & (((QData)((IData)( + vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT____Vcellout__cwb_queue__data_out[2U])) + << 0x20U) + | (QData)((IData)( + vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT____Vcellout__cwb_queue__data_out[1U])))) + >> 0x20U))); + vlTOPp->VX_cache__DOT__per_bank_core_rsp_data[1U] + = vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT____Vcellout__cwb_queue__data_out[0U]; + vlTOPp->VX_cache__DOT__per_bank_core_rsp_tid = + ((0xf3U & (IData)(vlTOPp->VX_cache__DOT__per_bank_core_rsp_tid)) + | (0xcU & (vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT____Vcellout__cwb_queue__data_out[2U] + >> 8U))); + vlTOPp->VX_cache__DOT__per_bank_core_rsp_tag[1U] + = ((0x3ffU & vlTOPp->VX_cache__DOT__per_bank_core_rsp_tag[1U]) + | (0xfffffc00U & ((IData)((VL_ULL(0x3ffffffffff) + & (((QData)((IData)( + vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT____Vcellout__cwb_queue__data_out[2U])) + << 0x20U) + | (QData)((IData)( + vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT____Vcellout__cwb_queue__data_out[1U]))))) + << 0xaU))); + vlTOPp->VX_cache__DOT__per_bank_core_rsp_tag[2U] + = ((0xfff00000U & vlTOPp->VX_cache__DOT__per_bank_core_rsp_tag[2U]) + | ((0x3ffU & ((IData)((VL_ULL(0x3ffffffffff) + & (((QData)((IData)( + vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT____Vcellout__cwb_queue__data_out[2U])) + << 0x20U) | (QData)((IData)( + vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT____Vcellout__cwb_queue__data_out[1U]))))) + >> 0x16U)) | (0xfffffc00U + & ((IData)(( + (VL_ULL(0x3ffffffffff) + & (((QData)((IData)( + vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT____Vcellout__cwb_queue__data_out[2U])) + << 0x20U) + | (QData)((IData)( + vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT____Vcellout__cwb_queue__data_out[1U])))) + >> 0x20U)) + << 0xaU)))); + vlTOPp->VX_cache__DOT__per_bank_core_rsp_data[2U] + = vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT____Vcellout__cwb_queue__data_out[0U]; + vlTOPp->VX_cache__DOT__per_bank_core_rsp_tid = + ((0xcfU & (IData)(vlTOPp->VX_cache__DOT__per_bank_core_rsp_tid)) + | (0x30U & (vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT____Vcellout__cwb_queue__data_out[2U] + >> 6U))); + vlTOPp->VX_cache__DOT__per_bank_core_rsp_tag[2U] + = ((0xfffffU & vlTOPp->VX_cache__DOT__per_bank_core_rsp_tag[2U]) + | (0xfff00000U & ((IData)((VL_ULL(0x3ffffffffff) + & (((QData)((IData)( + vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT____Vcellout__cwb_queue__data_out[2U])) + << 0x20U) + | (QData)((IData)( + vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT____Vcellout__cwb_queue__data_out[1U]))))) + << 0x14U))); + vlTOPp->VX_cache__DOT__per_bank_core_rsp_tag[3U] + = ((0xc0000000U & vlTOPp->VX_cache__DOT__per_bank_core_rsp_tag[3U]) + | ((0xfffffU & ((IData)((VL_ULL(0x3ffffffffff) + & (((QData)((IData)( + vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT____Vcellout__cwb_queue__data_out[2U])) + << 0x20U) | (QData)((IData)( + vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT____Vcellout__cwb_queue__data_out[1U]))))) + >> 0xcU)) | (0xfff00000U + & ((IData)( + ((VL_ULL(0x3ffffffffff) + & (((QData)((IData)( + vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT____Vcellout__cwb_queue__data_out[2U])) + << 0x20U) + | (QData)((IData)( + vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT____Vcellout__cwb_queue__data_out[1U])))) + >> 0x20U)) + << 0x14U)))); + vlTOPp->VX_cache__DOT__per_bank_core_rsp_data[3U] + = vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT____Vcellout__cwb_queue__data_out[0U]; + vlTOPp->VX_cache__DOT__per_bank_core_rsp_tid = + ((0x3fU & (IData)(vlTOPp->VX_cache__DOT__per_bank_core_rsp_tid)) + | (0xc0U & (vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT____Vcellout__cwb_queue__data_out[2U] + >> 4U))); + vlTOPp->VX_cache__DOT__per_bank_core_rsp_tag[3U] + = ((0x3fffffffU & vlTOPp->VX_cache__DOT__per_bank_core_rsp_tag[3U]) + | (0xc0000000U & ((IData)((VL_ULL(0x3ffffffffff) + & (((QData)((IData)( + vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT____Vcellout__cwb_queue__data_out[2U])) + << 0x20U) + | (QData)((IData)( + vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT____Vcellout__cwb_queue__data_out[1U]))))) + << 0x1eU))); + vlTOPp->VX_cache__DOT__per_bank_core_rsp_tag[4U] + = ((0x3fffffffU & ((IData)((VL_ULL(0x3ffffffffff) + & (((QData)((IData)( + vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT____Vcellout__cwb_queue__data_out[2U])) + << 0x20U) | (QData)((IData)( + vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT____Vcellout__cwb_queue__data_out[1U]))))) + >> 2U)) | (0xc0000000U & + ((IData)(((VL_ULL(0x3ffffffffff) + & (((QData)((IData)( + vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT____Vcellout__cwb_queue__data_out[2U])) + << 0x20U) + | (QData)((IData)( + vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT____Vcellout__cwb_queue__data_out[1U])))) + >> 0x20U)) + << 0x1eU))); + vlTOPp->VX_cache__DOT__per_bank_core_rsp_tag[5U] + = (0x3fffffffU & ((IData)(((VL_ULL(0x3ffffffffff) + & (((QData)((IData)( + vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT____Vcellout__cwb_queue__data_out[2U])) + << 0x20U) | (QData)((IData)( + vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT____Vcellout__cwb_queue__data_out[1U])))) + >> 0x20U)) >> 2U)); + vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__core_req_arb__DOT__sel_bank__DOT__genblk2__DOT__grant_onehot_r = 0U; + vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__core_req_arb__DOT__sel_bank__DOT__genblk2__DOT__grant_onehot_r + = ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__core_req_arb__DOT__sel_bank__DOT__genblk2__DOT__grant_onehot_r) + | ((IData)(1U) << (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__core_req_arb__DOT__qual_request_index))); + vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__reqq_req_rw_st0 + = (1U & ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__core_req_arb__DOT__use_per_rw) + >> (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__core_req_arb__DOT__qual_request_index))); + vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__reqq_req_addr_st0 + = ((0x77U >= (0x7fU & ((IData)(0x1eU) * (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__core_req_arb__DOT__qual_request_index)))) + ? (0x3fffffffU & (((0U == (0x1fU & ((IData)(0x1eU) + * (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__core_req_arb__DOT__qual_request_index)))) + ? 0U : (vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__core_req_arb__DOT__use_per_addr[ + ((IData)(1U) + + (3U & (((IData)(0x1eU) + * (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__core_req_arb__DOT__qual_request_index)) + >> 5U)))] + << ((IData)(0x20U) + - (0x1fU + & ((IData)(0x1eU) + * (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__core_req_arb__DOT__qual_request_index)))))) + | (vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__core_req_arb__DOT__use_per_addr[ + (3U & (((IData)(0x1eU) + * (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__core_req_arb__DOT__qual_request_index)) + >> 5U))] >> + (0x1fU & ((IData)(0x1eU) + * (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__core_req_arb__DOT__qual_request_index)))))) + : 0U); + vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__core_req_arb__DOT__sel_bank__DOT__genblk2__DOT__grant_onehot_r = 0U; + vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__core_req_arb__DOT__sel_bank__DOT__genblk2__DOT__grant_onehot_r + = ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__core_req_arb__DOT__sel_bank__DOT__genblk2__DOT__grant_onehot_r) + | ((IData)(1U) << (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__core_req_arb__DOT__qual_request_index))); + vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__reqq_req_rw_st0 + = (1U & ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__core_req_arb__DOT__use_per_rw) + >> (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__core_req_arb__DOT__qual_request_index))); + vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__reqq_req_addr_st0 + = ((0x77U >= (0x7fU & ((IData)(0x1eU) * (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__core_req_arb__DOT__qual_request_index)))) + ? (0x3fffffffU & (((0U == (0x1fU & ((IData)(0x1eU) + * (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__core_req_arb__DOT__qual_request_index)))) + ? 0U : (vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__core_req_arb__DOT__use_per_addr[ + ((IData)(1U) + + (3U & (((IData)(0x1eU) + * (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__core_req_arb__DOT__qual_request_index)) + >> 5U)))] + << ((IData)(0x20U) + - (0x1fU + & ((IData)(0x1eU) + * (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__core_req_arb__DOT__qual_request_index)))))) + | (vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__core_req_arb__DOT__use_per_addr[ + (3U & (((IData)(0x1eU) + * (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__core_req_arb__DOT__qual_request_index)) + >> 5U))] >> + (0x1fU & ((IData)(0x1eU) + * (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__core_req_arb__DOT__qual_request_index)))))) + : 0U); + vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__core_req_arb__DOT__sel_bank__DOT__genblk2__DOT__grant_onehot_r = 0U; + vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__core_req_arb__DOT__sel_bank__DOT__genblk2__DOT__grant_onehot_r + = ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__core_req_arb__DOT__sel_bank__DOT__genblk2__DOT__grant_onehot_r) + | ((IData)(1U) << (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__core_req_arb__DOT__qual_request_index))); + vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__reqq_req_rw_st0 + = (1U & ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__core_req_arb__DOT__use_per_rw) + >> (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__core_req_arb__DOT__qual_request_index))); + vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__reqq_req_addr_st0 + = ((0x77U >= (0x7fU & ((IData)(0x1eU) * (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__core_req_arb__DOT__qual_request_index)))) + ? (0x3fffffffU & (((0U == (0x1fU & ((IData)(0x1eU) + * (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__core_req_arb__DOT__qual_request_index)))) + ? 0U : (vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__core_req_arb__DOT__use_per_addr[ + ((IData)(1U) + + (3U & (((IData)(0x1eU) + * (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__core_req_arb__DOT__qual_request_index)) + >> 5U)))] + << ((IData)(0x20U) + - (0x1fU + & ((IData)(0x1eU) + * (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__core_req_arb__DOT__qual_request_index)))))) + | (vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__core_req_arb__DOT__use_per_addr[ + (3U & (((IData)(0x1eU) + * (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__core_req_arb__DOT__qual_request_index)) + >> 5U))] >> + (0x1fU & ((IData)(0x1eU) + * (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__core_req_arb__DOT__qual_request_index)))))) + : 0U); + vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__core_req_arb__DOT__sel_bank__DOT__genblk2__DOT__grant_onehot_r = 0U; + vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__core_req_arb__DOT__sel_bank__DOT__genblk2__DOT__grant_onehot_r + = ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__core_req_arb__DOT__sel_bank__DOT__genblk2__DOT__grant_onehot_r) + | ((IData)(1U) << (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__core_req_arb__DOT__qual_request_index))); + vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__reqq_req_rw_st0 + = (1U & ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__core_req_arb__DOT__use_per_rw) + >> (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__core_req_arb__DOT__qual_request_index))); + vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__reqq_req_addr_st0 + = ((0x77U >= (0x7fU & ((IData)(0x1eU) * (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__core_req_arb__DOT__qual_request_index)))) + ? (0x3fffffffU & (((0U == (0x1fU & ((IData)(0x1eU) + * (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__core_req_arb__DOT__qual_request_index)))) + ? 0U : (vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__core_req_arb__DOT__use_per_addr[ + ((IData)(1U) + + (3U & (((IData)(0x1eU) + * (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__core_req_arb__DOT__qual_request_index)) + >> 5U)))] + << ((IData)(0x20U) + - (0x1fU + & ((IData)(0x1eU) + * (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__core_req_arb__DOT__qual_request_index)))))) + | (vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__core_req_arb__DOT__use_per_addr[ + (3U & (((IData)(0x1eU) + * (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__core_req_arb__DOT__qual_request_index)) + >> 5U))] >> + (0x1fU & ((IData)(0x1eU) + * (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__core_req_arb__DOT__qual_request_index)))))) + : 0U); + vlTOPp->VX_cache__DOT__cache_dram_req_arb__DOT__dram_fill_arb__DOT__qual_bank_dram_fill_req_addr[0U] + = ((0U != (IData)(vlTOPp->VX_cache__DOT__cache_dram_req_arb__DOT__dram_fill_arb__DOT__use_per_bank_dram_fill_req_valid)) + ? vlTOPp->VX_cache__DOT__cache_dram_req_arb__DOT__dram_fill_arb__DOT__use_per_bank_dram_fill_req_addr[0U] + : vlTOPp->VX_cache__DOT__cache_dram_req_arb__DOT__dram_fill_arb__DOT____Vcellout__dfqq_queue__data_out[0U]); + vlTOPp->VX_cache__DOT__cache_dram_req_arb__DOT__dram_fill_arb__DOT__qual_bank_dram_fill_req_addr[1U] + = ((0U != (IData)(vlTOPp->VX_cache__DOT__cache_dram_req_arb__DOT__dram_fill_arb__DOT__use_per_bank_dram_fill_req_valid)) + ? vlTOPp->VX_cache__DOT__cache_dram_req_arb__DOT__dram_fill_arb__DOT__use_per_bank_dram_fill_req_addr[1U] + : vlTOPp->VX_cache__DOT__cache_dram_req_arb__DOT__dram_fill_arb__DOT____Vcellout__dfqq_queue__data_out[1U]); + vlTOPp->VX_cache__DOT__cache_dram_req_arb__DOT__dram_fill_arb__DOT__qual_bank_dram_fill_req_addr[2U] + = ((0U != (IData)(vlTOPp->VX_cache__DOT__cache_dram_req_arb__DOT__dram_fill_arb__DOT__use_per_bank_dram_fill_req_valid)) + ? vlTOPp->VX_cache__DOT__cache_dram_req_arb__DOT__dram_fill_arb__DOT__use_per_bank_dram_fill_req_addr[2U] + : vlTOPp->VX_cache__DOT__cache_dram_req_arb__DOT__dram_fill_arb__DOT____Vcellout__dfqq_queue__data_out[2U]); + vlTOPp->VX_cache__DOT__cache_dram_req_arb__DOT__dram_fill_arb__DOT__qual_bank_dram_fill_req_addr[3U] + = (0xffffU & ((0U != (IData)(vlTOPp->VX_cache__DOT__cache_dram_req_arb__DOT__dram_fill_arb__DOT__use_per_bank_dram_fill_req_valid)) + ? vlTOPp->VX_cache__DOT__cache_dram_req_arb__DOT__dram_fill_arb__DOT__use_per_bank_dram_fill_req_addr[3U] + : vlTOPp->VX_cache__DOT__cache_dram_req_arb__DOT__dram_fill_arb__DOT____Vcellout__dfqq_queue__data_out[3U])); + vlTOPp->VX_cache__DOT__cache_dram_req_arb__DOT__dram_fill_arb__DOT__use_per_bqual_bank_dram_fill_req_valid + = (0xfU & ((0U != (IData)(vlTOPp->VX_cache__DOT__cache_dram_req_arb__DOT__dram_fill_arb__DOT__use_per_bank_dram_fill_req_valid)) + ? ((IData)(vlTOPp->VX_cache__DOT__cache_dram_req_arb__DOT__dram_fill_arb__DOT__use_per_bank_dram_fill_req_valid) + & VL_NEGATE_I((IData)((0U != (IData)(vlTOPp->VX_cache__DOT__cache_dram_req_arb__DOT__dram_fill_arb__DOT__use_per_bank_dram_fill_req_valid))))) + : ((vlTOPp->VX_cache__DOT__cache_dram_req_arb__DOT__dram_fill_arb__DOT____Vcellout__dfqq_queue__data_out[3U] + >> 0x10U) & VL_NEGATE_I((IData)( + (1U + & (~ (IData)(vlTOPp->VX_cache__DOT__cache_dram_req_arb__DOT__dram_fill_arb__DOT__dfqq_queue__DOT__genblk3__DOT__genblk2__DOT__empty_r)))))))); + vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__dfpq_pop_unqual + = (1U & ((~ (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cache_miss_resrv__DOT__dequeue_possible)) + & (~ (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__dfp_queue__DOT__genblk3__DOT__genblk2__DOT__empty_r)))); + vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__dfpq_pop_unqual + = (1U & ((~ (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__cache_miss_resrv__DOT__dequeue_possible)) + & (~ (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__dfp_queue__DOT__genblk3__DOT__genblk2__DOT__empty_r)))); + vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__dfpq_pop_unqual + = (1U & ((~ (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__cache_miss_resrv__DOT__dequeue_possible)) + & (~ (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__dfp_queue__DOT__genblk3__DOT__genblk2__DOT__empty_r)))); + vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__dfpq_pop_unqual + = (1U & ((~ (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cache_miss_resrv__DOT__dequeue_possible)) + & (~ (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__dfp_queue__DOT__genblk3__DOT__genblk2__DOT__empty_r)))); + vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__is_fill_in_pipe = 0U; + if (vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__is_fill_st1 + [0U]) { + vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__is_fill_in_pipe = 1U; + } + vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__is_fill_in_pipe = 0U; + if (vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__is_fill_st1 + [0U]) { + vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__is_fill_in_pipe = 1U; + } + vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__is_fill_in_pipe = 0U; + if (vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__is_fill_st1 + [0U]) { + vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__is_fill_in_pipe = 1U; + } + vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__is_fill_in_pipe = 0U; + if (vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__is_fill_st1 + [0U]) { + vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__is_fill_in_pipe = 1U; + } + vlTOPp->VX_cache__DOT__per_bank_snp_rsp_tag[0U] + = ((0xf0000000U & vlTOPp->VX_cache__DOT__per_bank_snp_rsp_tag[0U]) + | (0xfffffffU & vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT____Vcellout__dwb_queue__data_out[0U])); + vlTOPp->VX_cache__DOT__per_bank_dram_wb_req_byteen + = ((VL_ULL(0xffffffffffff0000) & vlTOPp->VX_cache__DOT__per_bank_dram_wb_req_byteen) + | (IData)((IData)((0xffffU & ((vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT____Vcellout__dwb_queue__data_out[6U] + << 0xaU) + | (vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT____Vcellout__dwb_queue__data_out[5U] + >> 0x16U)))))); + vlTOPp->VX_cache__DOT__per_bank_dram_wb_req_data[0U] + = ((vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT____Vcellout__dwb_queue__data_out[1U] + << 4U) | (vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT____Vcellout__dwb_queue__data_out[0U] + >> 0x1cU)); + vlTOPp->VX_cache__DOT__per_bank_dram_wb_req_data[1U] + = ((vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT____Vcellout__dwb_queue__data_out[2U] + << 4U) | (vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT____Vcellout__dwb_queue__data_out[1U] + >> 0x1cU)); + vlTOPp->VX_cache__DOT__per_bank_dram_wb_req_data[2U] + = ((vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT____Vcellout__dwb_queue__data_out[3U] + << 4U) | (vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT____Vcellout__dwb_queue__data_out[2U] + >> 0x1cU)); + vlTOPp->VX_cache__DOT__per_bank_dram_wb_req_data[3U] + = ((vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT____Vcellout__dwb_queue__data_out[4U] + << 4U) | (vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT____Vcellout__dwb_queue__data_out[3U] + >> 0x1cU)); + vlTOPp->VX_cache__DOT__per_bank_dram_wb_req_addr[0U] + = ((0xf0000000U & vlTOPp->VX_cache__DOT__per_bank_dram_wb_req_addr[0U]) + | (0xffffffcU & ((vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT____Vcellout__dwb_queue__data_out[5U] + << 6U) | (0x3cU & (vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT____Vcellout__dwb_queue__data_out[4U] + >> 0x1aU))))); + vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__curr_bank_snp_rsp_valid + = (1U & (((~ (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__genblk2__DOT__empty_r)) + & (vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT____Vcellout__dwb_queue__data_out[6U] + >> 6U)) & ((~ (vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT____Vcellout__dwb_queue__data_out[6U] + >> 7U)) | (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__dwbq_dual_valid_sel)))); + vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__curr_bank_dram_wb_req_valid + = (1U & (((~ (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__genblk2__DOT__empty_r)) + & (vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT____Vcellout__dwb_queue__data_out[6U] + >> 7U)) & ((~ (vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT____Vcellout__dwb_queue__data_out[6U] + >> 6U)) | (~ (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__dwbq_dual_valid_sel))))); + vlTOPp->VX_cache__DOT__per_bank_snp_rsp_tag[0U] + = ((0xfffffffU & vlTOPp->VX_cache__DOT__per_bank_snp_rsp_tag[0U]) + | (0xf0000000U & (vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT____Vcellout__dwb_queue__data_out[0U] + << 0x1cU))); + vlTOPp->VX_cache__DOT__per_bank_snp_rsp_tag[1U] + = ((0xff000000U & vlTOPp->VX_cache__DOT__per_bank_snp_rsp_tag[1U]) + | (0xffffffU & (vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT____Vcellout__dwb_queue__data_out[0U] + >> 4U))); + vlTOPp->VX_cache__DOT__per_bank_dram_wb_req_byteen + = ((VL_ULL(0xffffffff0000ffff) & vlTOPp->VX_cache__DOT__per_bank_dram_wb_req_byteen) + | ((QData)((IData)((0xffffU & ((vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT____Vcellout__dwb_queue__data_out[6U] + << 0xaU) + | (vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT____Vcellout__dwb_queue__data_out[5U] + >> 0x16U))))) + << 0x10U)); + vlTOPp->VX_cache__DOT__per_bank_dram_wb_req_data[4U] + = ((vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT____Vcellout__dwb_queue__data_out[1U] + << 4U) | (vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT____Vcellout__dwb_queue__data_out[0U] + >> 0x1cU)); + vlTOPp->VX_cache__DOT__per_bank_dram_wb_req_data[5U] + = ((vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT____Vcellout__dwb_queue__data_out[2U] + << 4U) | (vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT____Vcellout__dwb_queue__data_out[1U] + >> 0x1cU)); + vlTOPp->VX_cache__DOT__per_bank_dram_wb_req_data[6U] + = ((vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT____Vcellout__dwb_queue__data_out[3U] + << 4U) | (vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT____Vcellout__dwb_queue__data_out[2U] + >> 0x1cU)); + vlTOPp->VX_cache__DOT__per_bank_dram_wb_req_data[7U] + = ((vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT____Vcellout__dwb_queue__data_out[4U] + << 4U) | (vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT____Vcellout__dwb_queue__data_out[3U] + >> 0x1cU)); + vlTOPp->VX_cache__DOT__per_bank_dram_wb_req_addr[0U] + = ((0xfffffffU & vlTOPp->VX_cache__DOT__per_bank_dram_wb_req_addr[0U]) + | (0xf0000000U & (0x10000000U | (0xc0000000U + & (vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT____Vcellout__dwb_queue__data_out[4U] + << 2U))))); + vlTOPp->VX_cache__DOT__per_bank_dram_wb_req_addr[1U] + = ((0xff000000U & vlTOPp->VX_cache__DOT__per_bank_dram_wb_req_addr[1U]) + | (0xffffffU & ((0xffffffcU & (vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT____Vcellout__dwb_queue__data_out[5U] + << 2U)) | + (3U & (vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT____Vcellout__dwb_queue__data_out[4U] + >> 0x1eU))))); + vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__curr_bank_snp_rsp_valid + = (1U & (((~ (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__genblk2__DOT__empty_r)) + & (vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT____Vcellout__dwb_queue__data_out[6U] + >> 6U)) & ((~ (vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT____Vcellout__dwb_queue__data_out[6U] + >> 7U)) | (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__dwbq_dual_valid_sel)))); + vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__curr_bank_dram_wb_req_valid + = (1U & (((~ (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__genblk2__DOT__empty_r)) + & (vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT____Vcellout__dwb_queue__data_out[6U] + >> 7U)) & ((~ (vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT____Vcellout__dwb_queue__data_out[6U] + >> 6U)) | (~ (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__dwbq_dual_valid_sel))))); + vlTOPp->VX_cache__DOT__per_bank_snp_rsp_tag[1U] + = ((0xffffffU & vlTOPp->VX_cache__DOT__per_bank_snp_rsp_tag[1U]) + | (0xff000000U & (vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT____Vcellout__dwb_queue__data_out[0U] + << 0x18U))); + vlTOPp->VX_cache__DOT__per_bank_snp_rsp_tag[2U] + = ((0xfff00000U & vlTOPp->VX_cache__DOT__per_bank_snp_rsp_tag[2U]) + | (0xfffffU & (vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT____Vcellout__dwb_queue__data_out[0U] + >> 8U))); + vlTOPp->VX_cache__DOT__per_bank_dram_wb_req_byteen + = ((VL_ULL(0xffff0000ffffffff) & vlTOPp->VX_cache__DOT__per_bank_dram_wb_req_byteen) + | ((QData)((IData)((0xffffU & ((vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT____Vcellout__dwb_queue__data_out[6U] + << 0xaU) + | (vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT____Vcellout__dwb_queue__data_out[5U] + >> 0x16U))))) + << 0x20U)); + vlTOPp->VX_cache__DOT__per_bank_dram_wb_req_data[8U] + = ((vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT____Vcellout__dwb_queue__data_out[1U] + << 4U) | (vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT____Vcellout__dwb_queue__data_out[0U] + >> 0x1cU)); + vlTOPp->VX_cache__DOT__per_bank_dram_wb_req_data[9U] + = ((vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT____Vcellout__dwb_queue__data_out[2U] + << 4U) | (vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT____Vcellout__dwb_queue__data_out[1U] + >> 0x1cU)); + vlTOPp->VX_cache__DOT__per_bank_dram_wb_req_data[0xaU] + = ((vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT____Vcellout__dwb_queue__data_out[3U] + << 4U) | (vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT____Vcellout__dwb_queue__data_out[2U] + >> 0x1cU)); + vlTOPp->VX_cache__DOT__per_bank_dram_wb_req_data[0xbU] + = ((vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT____Vcellout__dwb_queue__data_out[4U] + << 4U) | (vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT____Vcellout__dwb_queue__data_out[3U] + >> 0x1cU)); + vlTOPp->VX_cache__DOT__per_bank_dram_wb_req_addr[1U] + = ((0xffffffU & vlTOPp->VX_cache__DOT__per_bank_dram_wb_req_addr[1U]) + | (0xff000000U & (0x2000000U | (0xfc000000U + & ((vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT____Vcellout__dwb_queue__data_out[5U] + << 0x1eU) + | (0x3c000000U + & (vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT____Vcellout__dwb_queue__data_out[4U] + >> 2U))))))); + vlTOPp->VX_cache__DOT__per_bank_dram_wb_req_addr[2U] + = ((0xfff00000U & vlTOPp->VX_cache__DOT__per_bank_dram_wb_req_addr[2U]) + | (0xfffffU & (vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT____Vcellout__dwb_queue__data_out[5U] + >> 2U))); + vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__curr_bank_snp_rsp_valid + = (1U & (((~ (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__genblk2__DOT__empty_r)) + & (vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT____Vcellout__dwb_queue__data_out[6U] + >> 6U)) & ((~ (vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT____Vcellout__dwb_queue__data_out[6U] + >> 7U)) | (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__dwbq_dual_valid_sel)))); + vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__curr_bank_dram_wb_req_valid + = (1U & (((~ (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__genblk2__DOT__empty_r)) + & (vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT____Vcellout__dwb_queue__data_out[6U] + >> 7U)) & ((~ (vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT____Vcellout__dwb_queue__data_out[6U] + >> 6U)) | (~ (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__dwbq_dual_valid_sel))))); + vlTOPp->VX_cache__DOT__per_bank_snp_rsp_tag[2U] + = ((0xfffffU & vlTOPp->VX_cache__DOT__per_bank_snp_rsp_tag[2U]) + | (0xfff00000U & (vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT____Vcellout__dwb_queue__data_out[0U] + << 0x14U))); + vlTOPp->VX_cache__DOT__per_bank_snp_rsp_tag[3U] + = (0xffffU & (vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT____Vcellout__dwb_queue__data_out[0U] + >> 0xcU)); + vlTOPp->VX_cache__DOT__per_bank_dram_wb_req_byteen + = ((VL_ULL(0xffffffffffff) & vlTOPp->VX_cache__DOT__per_bank_dram_wb_req_byteen) + | ((QData)((IData)((0xffffU & ((vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT____Vcellout__dwb_queue__data_out[6U] + << 0xaU) + | (vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT____Vcellout__dwb_queue__data_out[5U] + >> 0x16U))))) + << 0x30U)); + vlTOPp->VX_cache__DOT__per_bank_dram_wb_req_data[0xcU] + = ((vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT____Vcellout__dwb_queue__data_out[1U] + << 4U) | (vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT____Vcellout__dwb_queue__data_out[0U] + >> 0x1cU)); + vlTOPp->VX_cache__DOT__per_bank_dram_wb_req_data[0xdU] + = ((vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT____Vcellout__dwb_queue__data_out[2U] + << 4U) | (vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT____Vcellout__dwb_queue__data_out[1U] + >> 0x1cU)); + vlTOPp->VX_cache__DOT__per_bank_dram_wb_req_data[0xeU] + = ((vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT____Vcellout__dwb_queue__data_out[3U] + << 4U) | (vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT____Vcellout__dwb_queue__data_out[2U] + >> 0x1cU)); + vlTOPp->VX_cache__DOT__per_bank_dram_wb_req_data[0xfU] + = ((vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT____Vcellout__dwb_queue__data_out[4U] + << 4U) | (vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT____Vcellout__dwb_queue__data_out[3U] + >> 0x1cU)); + vlTOPp->VX_cache__DOT__per_bank_dram_wb_req_addr[2U] + = ((0xfffffU & vlTOPp->VX_cache__DOT__per_bank_dram_wb_req_addr[2U]) + | (0xfff00000U & (0x300000U | (0xffc00000U + & ((vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT____Vcellout__dwb_queue__data_out[5U] + << 0x1aU) + | (0x3c00000U + & (vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT____Vcellout__dwb_queue__data_out[4U] + >> 6U))))))); + vlTOPp->VX_cache__DOT__per_bank_dram_wb_req_addr[3U] + = (0xffffU & (vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT____Vcellout__dwb_queue__data_out[5U] + >> 6U)); + vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__curr_bank_snp_rsp_valid + = (1U & (((~ (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__genblk2__DOT__empty_r)) + & (vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT____Vcellout__dwb_queue__data_out[6U] + >> 6U)) & ((~ (vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT____Vcellout__dwb_queue__data_out[6U] + >> 7U)) | (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__dwbq_dual_valid_sel)))); + vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__curr_bank_dram_wb_req_valid + = (1U & (((~ (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__genblk2__DOT__empty_r)) + & (vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT____Vcellout__dwb_queue__data_out[6U] + >> 7U)) & ((~ (vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT____Vcellout__dwb_queue__data_out[6U] + >> 6U)) | (~ (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__dwbq_dual_valid_sel))))); + vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cache_miss_resrv__DOT__valid_address_match + = ((0xfffeU & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cache_miss_resrv__DOT__valid_address_match)) + | ((1U & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cache_miss_resrv__DOT__valid_table)) + ? (1U & ((0x3ffffffU & vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cache_miss_resrv__DOT__addr_table[0U]) + == vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__addr_st1 + [0U])) : 0U)); + vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cache_miss_resrv__DOT__valid_address_match + = ((0xfffdU & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cache_miss_resrv__DOT__valid_address_match)) + | (((2U & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cache_miss_resrv__DOT__valid_table)) + ? (1U & ((0x3ffffffU & ((vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cache_miss_resrv__DOT__addr_table[1U] + << 6U) | ( + vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cache_miss_resrv__DOT__addr_table[0U] + >> 0x1aU))) + == vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__addr_st1 + [0U])) : 0U) << 1U)); + vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cache_miss_resrv__DOT__valid_address_match + = ((0xfffbU & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cache_miss_resrv__DOT__valid_address_match)) + | (((4U & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cache_miss_resrv__DOT__valid_table)) + ? (1U & ((0x3ffffffU & ((vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cache_miss_resrv__DOT__addr_table[2U] + << 0xcU) | + (vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cache_miss_resrv__DOT__addr_table[1U] + >> 0x14U))) + == vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__addr_st1 + [0U])) : 0U) << 2U)); + vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cache_miss_resrv__DOT__valid_address_match + = ((0xfff7U & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cache_miss_resrv__DOT__valid_address_match)) + | (((8U & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cache_miss_resrv__DOT__valid_table)) + ? (1U & ((0x3ffffffU & ((vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cache_miss_resrv__DOT__addr_table[3U] + << 0x12U) + | (vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cache_miss_resrv__DOT__addr_table[2U] + >> 0xeU))) + == vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__addr_st1 + [0U])) : 0U) << 3U)); + vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cache_miss_resrv__DOT__valid_address_match + = ((0xffefU & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cache_miss_resrv__DOT__valid_address_match)) + | (((0x10U & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cache_miss_resrv__DOT__valid_table)) + ? (1U & ((0x3ffffffU & ((vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cache_miss_resrv__DOT__addr_table[4U] + << 0x18U) + | (vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cache_miss_resrv__DOT__addr_table[3U] + >> 8U))) + == vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__addr_st1 + [0U])) : 0U) << 4U)); + vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cache_miss_resrv__DOT__valid_address_match + = ((0xffdfU & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cache_miss_resrv__DOT__valid_address_match)) + | (((0x20U & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cache_miss_resrv__DOT__valid_table)) + ? (1U & ((0x3ffffffU & ((vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cache_miss_resrv__DOT__addr_table[5U] + << 0x1eU) + | (vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cache_miss_resrv__DOT__addr_table[4U] + >> 2U))) + == vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__addr_st1 + [0U])) : 0U) << 5U)); + vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cache_miss_resrv__DOT__valid_address_match + = ((0xffbfU & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cache_miss_resrv__DOT__valid_address_match)) + | (((0x40U & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cache_miss_resrv__DOT__valid_table)) + ? (1U & ((0x3ffffffU & ((vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cache_miss_resrv__DOT__addr_table[5U] + << 4U) | ( + vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cache_miss_resrv__DOT__addr_table[4U] + >> 0x1cU))) + == vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__addr_st1 + [0U])) : 0U) << 6U)); + vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cache_miss_resrv__DOT__valid_address_match + = ((0xff7fU & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cache_miss_resrv__DOT__valid_address_match)) + | (((0x80U & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cache_miss_resrv__DOT__valid_table)) + ? (1U & ((0x3ffffffU & ((vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cache_miss_resrv__DOT__addr_table[6U] + << 0xaU) | + (vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cache_miss_resrv__DOT__addr_table[5U] + >> 0x16U))) + == vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__addr_st1 + [0U])) : 0U) << 7U)); + vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cache_miss_resrv__DOT__valid_address_match + = ((0xfeffU & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cache_miss_resrv__DOT__valid_address_match)) + | (((0x100U & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cache_miss_resrv__DOT__valid_table)) + ? (1U & ((0x3ffffffU & ((vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cache_miss_resrv__DOT__addr_table[7U] + << 0x10U) + | (vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cache_miss_resrv__DOT__addr_table[6U] + >> 0x10U))) + == vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__addr_st1 + [0U])) : 0U) << 8U)); + vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cache_miss_resrv__DOT__valid_address_match + = ((0xfdffU & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cache_miss_resrv__DOT__valid_address_match)) + | (((0x200U & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cache_miss_resrv__DOT__valid_table)) + ? (1U & ((0x3ffffffU & ((vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cache_miss_resrv__DOT__addr_table[8U] + << 0x16U) + | (vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cache_miss_resrv__DOT__addr_table[7U] + >> 0xaU))) + == vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__addr_st1 + [0U])) : 0U) << 9U)); + vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cache_miss_resrv__DOT__valid_address_match + = ((0xfbffU & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cache_miss_resrv__DOT__valid_address_match)) + | (((0x400U & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cache_miss_resrv__DOT__valid_table)) + ? (1U & ((0x3ffffffU & ((vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cache_miss_resrv__DOT__addr_table[9U] + << 0x1cU) + | (vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cache_miss_resrv__DOT__addr_table[8U] + >> 4U))) + == vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__addr_st1 + [0U])) : 0U) << 0xaU)); + vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cache_miss_resrv__DOT__valid_address_match + = ((0xf7ffU & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cache_miss_resrv__DOT__valid_address_match)) + | (((0x800U & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cache_miss_resrv__DOT__valid_table)) + ? (1U & ((0x3ffffffU & ((vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cache_miss_resrv__DOT__addr_table[9U] + << 2U) | ( + vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cache_miss_resrv__DOT__addr_table[8U] + >> 0x1eU))) + == vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__addr_st1 + [0U])) : 0U) << 0xbU)); + vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cache_miss_resrv__DOT__valid_address_match + = ((0xefffU & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cache_miss_resrv__DOT__valid_address_match)) + | (((0x1000U & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cache_miss_resrv__DOT__valid_table)) + ? (1U & ((0x3ffffffU & ((vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cache_miss_resrv__DOT__addr_table[0xaU] + << 8U) | ( + vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cache_miss_resrv__DOT__addr_table[9U] + >> 0x18U))) + == vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__addr_st1 + [0U])) : 0U) << 0xcU)); + vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cache_miss_resrv__DOT__valid_address_match + = ((0xdfffU & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cache_miss_resrv__DOT__valid_address_match)) + | (((0x2000U & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cache_miss_resrv__DOT__valid_table)) + ? (1U & ((0x3ffffffU & ((vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cache_miss_resrv__DOT__addr_table[0xbU] + << 0xeU) | + (vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cache_miss_resrv__DOT__addr_table[0xaU] + >> 0x12U))) + == vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__addr_st1 + [0U])) : 0U) << 0xdU)); + vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cache_miss_resrv__DOT__valid_address_match + = ((0xbfffU & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cache_miss_resrv__DOT__valid_address_match)) + | (((0x4000U & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cache_miss_resrv__DOT__valid_table)) + ? (1U & ((0x3ffffffU & ((vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cache_miss_resrv__DOT__addr_table[0xcU] + << 0x14U) + | (vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cache_miss_resrv__DOT__addr_table[0xbU] + >> 0xcU))) + == vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__addr_st1 + [0U])) : 0U) << 0xeU)); + vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cache_miss_resrv__DOT__valid_address_match + = ((0x7fffU & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cache_miss_resrv__DOT__valid_address_match)) + | (((0x8000U & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cache_miss_resrv__DOT__valid_table)) + ? (1U & ((0x3ffffffU & (vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cache_miss_resrv__DOT__addr_table[0xcU] + >> 6U)) == + vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__addr_st1 + [0U])) : 0U) << 0xfU)); + vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__tag_data_access__DOT____Vcellinp__s0_1_c0__in[0U] + = vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__data + [(0x3fU & vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__addr_st1 + [0U])][0U]; + vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__tag_data_access__DOT____Vcellinp__s0_1_c0__in[1U] + = vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__data + [(0x3fU & vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__addr_st1 + [0U])][1U]; + vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__tag_data_access__DOT____Vcellinp__s0_1_c0__in[2U] + = vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__data + [(0x3fU & vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__addr_st1 + [0U])][2U]; + vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__tag_data_access__DOT____Vcellinp__s0_1_c0__in[3U] + = vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__data + [(0x3fU & vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__addr_st1 + [0U])][3U]; + vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__tag_data_access__DOT____Vcellinp__s0_1_c0__in[4U] + = ((0xfff00000U & (vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__dirtyb + [(0x3fU & vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__addr_st1 + [0U])] << 0x14U)) | vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__tag + [(0x3fU & vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__addr_st1 + [0U])]); + vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__tag_data_access__DOT____Vcellinp__s0_1_c0__in[5U] + = ((0x20U & ((IData)((vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__valid + >> (0x3fU & vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__addr_st1 + [0U]))) << 5U)) | + ((0x10U & ((IData)((vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__dirty + >> (0x3fU & vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__addr_st1 + [0U]))) << 4U)) + | (0xfffffU & (vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__dirtyb + [(0x3fU & vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__addr_st1 + [0U])] >> 0xcU)))); + vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__cache_miss_resrv__DOT__valid_address_match + = ((0xfffeU & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__cache_miss_resrv__DOT__valid_address_match)) + | ((1U & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__cache_miss_resrv__DOT__valid_table)) + ? (1U & ((0x3ffffffU & vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__cache_miss_resrv__DOT__addr_table[0U]) + == vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__addr_st1 + [0U])) : 0U)); + vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__cache_miss_resrv__DOT__valid_address_match + = ((0xfffdU & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__cache_miss_resrv__DOT__valid_address_match)) + | (((2U & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__cache_miss_resrv__DOT__valid_table)) + ? (1U & ((0x3ffffffU & ((vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__cache_miss_resrv__DOT__addr_table[1U] + << 6U) | ( + vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__cache_miss_resrv__DOT__addr_table[0U] + >> 0x1aU))) + == vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__addr_st1 + [0U])) : 0U) << 1U)); + vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__cache_miss_resrv__DOT__valid_address_match + = ((0xfffbU & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__cache_miss_resrv__DOT__valid_address_match)) + | (((4U & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__cache_miss_resrv__DOT__valid_table)) + ? (1U & ((0x3ffffffU & ((vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__cache_miss_resrv__DOT__addr_table[2U] + << 0xcU) | + (vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__cache_miss_resrv__DOT__addr_table[1U] + >> 0x14U))) + == vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__addr_st1 + [0U])) : 0U) << 2U)); + vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__cache_miss_resrv__DOT__valid_address_match + = ((0xfff7U & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__cache_miss_resrv__DOT__valid_address_match)) + | (((8U & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__cache_miss_resrv__DOT__valid_table)) + ? (1U & ((0x3ffffffU & ((vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__cache_miss_resrv__DOT__addr_table[3U] + << 0x12U) + | (vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__cache_miss_resrv__DOT__addr_table[2U] + >> 0xeU))) + == vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__addr_st1 + [0U])) : 0U) << 3U)); + vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__cache_miss_resrv__DOT__valid_address_match + = ((0xffefU & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__cache_miss_resrv__DOT__valid_address_match)) + | (((0x10U & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__cache_miss_resrv__DOT__valid_table)) + ? (1U & ((0x3ffffffU & ((vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__cache_miss_resrv__DOT__addr_table[4U] + << 0x18U) + | (vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__cache_miss_resrv__DOT__addr_table[3U] + >> 8U))) + == vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__addr_st1 + [0U])) : 0U) << 4U)); + vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__cache_miss_resrv__DOT__valid_address_match + = ((0xffdfU & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__cache_miss_resrv__DOT__valid_address_match)) + | (((0x20U & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__cache_miss_resrv__DOT__valid_table)) + ? (1U & ((0x3ffffffU & ((vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__cache_miss_resrv__DOT__addr_table[5U] + << 0x1eU) + | (vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__cache_miss_resrv__DOT__addr_table[4U] + >> 2U))) + == vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__addr_st1 + [0U])) : 0U) << 5U)); + vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__cache_miss_resrv__DOT__valid_address_match + = ((0xffbfU & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__cache_miss_resrv__DOT__valid_address_match)) + | (((0x40U & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__cache_miss_resrv__DOT__valid_table)) + ? (1U & ((0x3ffffffU & ((vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__cache_miss_resrv__DOT__addr_table[5U] + << 4U) | ( + vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__cache_miss_resrv__DOT__addr_table[4U] + >> 0x1cU))) + == vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__addr_st1 + [0U])) : 0U) << 6U)); + vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__cache_miss_resrv__DOT__valid_address_match + = ((0xff7fU & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__cache_miss_resrv__DOT__valid_address_match)) + | (((0x80U & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__cache_miss_resrv__DOT__valid_table)) + ? (1U & ((0x3ffffffU & ((vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__cache_miss_resrv__DOT__addr_table[6U] + << 0xaU) | + (vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__cache_miss_resrv__DOT__addr_table[5U] + >> 0x16U))) + == vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__addr_st1 + [0U])) : 0U) << 7U)); + vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__cache_miss_resrv__DOT__valid_address_match + = ((0xfeffU & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__cache_miss_resrv__DOT__valid_address_match)) + | (((0x100U & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__cache_miss_resrv__DOT__valid_table)) + ? (1U & ((0x3ffffffU & ((vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__cache_miss_resrv__DOT__addr_table[7U] + << 0x10U) + | (vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__cache_miss_resrv__DOT__addr_table[6U] + >> 0x10U))) + == vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__addr_st1 + [0U])) : 0U) << 8U)); + vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__cache_miss_resrv__DOT__valid_address_match + = ((0xfdffU & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__cache_miss_resrv__DOT__valid_address_match)) + | (((0x200U & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__cache_miss_resrv__DOT__valid_table)) + ? (1U & ((0x3ffffffU & ((vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__cache_miss_resrv__DOT__addr_table[8U] + << 0x16U) + | (vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__cache_miss_resrv__DOT__addr_table[7U] + >> 0xaU))) + == vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__addr_st1 + [0U])) : 0U) << 9U)); + vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__cache_miss_resrv__DOT__valid_address_match + = ((0xfbffU & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__cache_miss_resrv__DOT__valid_address_match)) + | (((0x400U & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__cache_miss_resrv__DOT__valid_table)) + ? (1U & ((0x3ffffffU & ((vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__cache_miss_resrv__DOT__addr_table[9U] + << 0x1cU) + | (vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__cache_miss_resrv__DOT__addr_table[8U] + >> 4U))) + == vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__addr_st1 + [0U])) : 0U) << 0xaU)); + vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__cache_miss_resrv__DOT__valid_address_match + = ((0xf7ffU & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__cache_miss_resrv__DOT__valid_address_match)) + | (((0x800U & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__cache_miss_resrv__DOT__valid_table)) + ? (1U & ((0x3ffffffU & ((vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__cache_miss_resrv__DOT__addr_table[9U] + << 2U) | ( + vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__cache_miss_resrv__DOT__addr_table[8U] + >> 0x1eU))) + == vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__addr_st1 + [0U])) : 0U) << 0xbU)); + vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__cache_miss_resrv__DOT__valid_address_match + = ((0xefffU & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__cache_miss_resrv__DOT__valid_address_match)) + | (((0x1000U & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__cache_miss_resrv__DOT__valid_table)) + ? (1U & ((0x3ffffffU & ((vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__cache_miss_resrv__DOT__addr_table[0xaU] + << 8U) | ( + vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__cache_miss_resrv__DOT__addr_table[9U] + >> 0x18U))) + == vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__addr_st1 + [0U])) : 0U) << 0xcU)); + vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__cache_miss_resrv__DOT__valid_address_match + = ((0xdfffU & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__cache_miss_resrv__DOT__valid_address_match)) + | (((0x2000U & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__cache_miss_resrv__DOT__valid_table)) + ? (1U & ((0x3ffffffU & ((vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__cache_miss_resrv__DOT__addr_table[0xbU] + << 0xeU) | + (vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__cache_miss_resrv__DOT__addr_table[0xaU] + >> 0x12U))) + == vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__addr_st1 + [0U])) : 0U) << 0xdU)); + vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__cache_miss_resrv__DOT__valid_address_match + = ((0xbfffU & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__cache_miss_resrv__DOT__valid_address_match)) + | (((0x4000U & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__cache_miss_resrv__DOT__valid_table)) + ? (1U & ((0x3ffffffU & ((vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__cache_miss_resrv__DOT__addr_table[0xcU] + << 0x14U) + | (vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__cache_miss_resrv__DOT__addr_table[0xbU] + >> 0xcU))) + == vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__addr_st1 + [0U])) : 0U) << 0xeU)); + vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__cache_miss_resrv__DOT__valid_address_match + = ((0x7fffU & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__cache_miss_resrv__DOT__valid_address_match)) + | (((0x8000U & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__cache_miss_resrv__DOT__valid_table)) + ? (1U & ((0x3ffffffU & (vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__cache_miss_resrv__DOT__addr_table[0xcU] + >> 6U)) == + vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__addr_st1 + [0U])) : 0U) << 0xfU)); + vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__tag_data_access__DOT____Vcellinp__s0_1_c0__in[0U] + = vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__data + [(0x3fU & vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__addr_st1 + [0U])][0U]; + vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__tag_data_access__DOT____Vcellinp__s0_1_c0__in[1U] + = vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__data + [(0x3fU & vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__addr_st1 + [0U])][1U]; + vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__tag_data_access__DOT____Vcellinp__s0_1_c0__in[2U] + = vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__data + [(0x3fU & vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__addr_st1 + [0U])][2U]; + vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__tag_data_access__DOT____Vcellinp__s0_1_c0__in[3U] + = vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__data + [(0x3fU & vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__addr_st1 + [0U])][3U]; + vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__tag_data_access__DOT____Vcellinp__s0_1_c0__in[4U] + = ((0xfff00000U & (vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__dirtyb + [(0x3fU & vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__addr_st1 + [0U])] << 0x14U)) | vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__tag + [(0x3fU & vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__addr_st1 + [0U])]); + vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__tag_data_access__DOT____Vcellinp__s0_1_c0__in[5U] + = ((0x20U & ((IData)((vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__valid + >> (0x3fU & vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__addr_st1 + [0U]))) << 5U)) | + ((0x10U & ((IData)((vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__dirty + >> (0x3fU & vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__addr_st1 + [0U]))) << 4U)) + | (0xfffffU & (vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__dirtyb + [(0x3fU & vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__addr_st1 + [0U])] >> 0xcU)))); + vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__cache_miss_resrv__DOT__valid_address_match + = ((0xfffeU & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__cache_miss_resrv__DOT__valid_address_match)) + | ((1U & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__cache_miss_resrv__DOT__valid_table)) + ? (1U & ((0x3ffffffU & vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__cache_miss_resrv__DOT__addr_table[0U]) + == vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__addr_st1 + [0U])) : 0U)); + vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__cache_miss_resrv__DOT__valid_address_match + = ((0xfffdU & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__cache_miss_resrv__DOT__valid_address_match)) + | (((2U & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__cache_miss_resrv__DOT__valid_table)) + ? (1U & ((0x3ffffffU & ((vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__cache_miss_resrv__DOT__addr_table[1U] + << 6U) | ( + vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__cache_miss_resrv__DOT__addr_table[0U] + >> 0x1aU))) + == vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__addr_st1 + [0U])) : 0U) << 1U)); + vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__cache_miss_resrv__DOT__valid_address_match + = ((0xfffbU & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__cache_miss_resrv__DOT__valid_address_match)) + | (((4U & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__cache_miss_resrv__DOT__valid_table)) + ? (1U & ((0x3ffffffU & ((vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__cache_miss_resrv__DOT__addr_table[2U] + << 0xcU) | + (vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__cache_miss_resrv__DOT__addr_table[1U] + >> 0x14U))) + == vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__addr_st1 + [0U])) : 0U) << 2U)); + vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__cache_miss_resrv__DOT__valid_address_match + = ((0xfff7U & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__cache_miss_resrv__DOT__valid_address_match)) + | (((8U & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__cache_miss_resrv__DOT__valid_table)) + ? (1U & ((0x3ffffffU & ((vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__cache_miss_resrv__DOT__addr_table[3U] + << 0x12U) + | (vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__cache_miss_resrv__DOT__addr_table[2U] + >> 0xeU))) + == vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__addr_st1 + [0U])) : 0U) << 3U)); + vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__cache_miss_resrv__DOT__valid_address_match + = ((0xffefU & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__cache_miss_resrv__DOT__valid_address_match)) + | (((0x10U & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__cache_miss_resrv__DOT__valid_table)) + ? (1U & ((0x3ffffffU & ((vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__cache_miss_resrv__DOT__addr_table[4U] + << 0x18U) + | (vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__cache_miss_resrv__DOT__addr_table[3U] + >> 8U))) + == vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__addr_st1 + [0U])) : 0U) << 4U)); + vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__cache_miss_resrv__DOT__valid_address_match + = ((0xffdfU & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__cache_miss_resrv__DOT__valid_address_match)) + | (((0x20U & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__cache_miss_resrv__DOT__valid_table)) + ? (1U & ((0x3ffffffU & ((vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__cache_miss_resrv__DOT__addr_table[5U] + << 0x1eU) + | (vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__cache_miss_resrv__DOT__addr_table[4U] + >> 2U))) + == vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__addr_st1 + [0U])) : 0U) << 5U)); + vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__cache_miss_resrv__DOT__valid_address_match + = ((0xffbfU & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__cache_miss_resrv__DOT__valid_address_match)) + | (((0x40U & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__cache_miss_resrv__DOT__valid_table)) + ? (1U & ((0x3ffffffU & ((vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__cache_miss_resrv__DOT__addr_table[5U] + << 4U) | ( + vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__cache_miss_resrv__DOT__addr_table[4U] + >> 0x1cU))) + == vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__addr_st1 + [0U])) : 0U) << 6U)); + vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__cache_miss_resrv__DOT__valid_address_match + = ((0xff7fU & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__cache_miss_resrv__DOT__valid_address_match)) + | (((0x80U & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__cache_miss_resrv__DOT__valid_table)) + ? (1U & ((0x3ffffffU & ((vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__cache_miss_resrv__DOT__addr_table[6U] + << 0xaU) | + (vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__cache_miss_resrv__DOT__addr_table[5U] + >> 0x16U))) + == vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__addr_st1 + [0U])) : 0U) << 7U)); + vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__cache_miss_resrv__DOT__valid_address_match + = ((0xfeffU & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__cache_miss_resrv__DOT__valid_address_match)) + | (((0x100U & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__cache_miss_resrv__DOT__valid_table)) + ? (1U & ((0x3ffffffU & ((vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__cache_miss_resrv__DOT__addr_table[7U] + << 0x10U) + | (vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__cache_miss_resrv__DOT__addr_table[6U] + >> 0x10U))) + == vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__addr_st1 + [0U])) : 0U) << 8U)); + vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__cache_miss_resrv__DOT__valid_address_match + = ((0xfdffU & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__cache_miss_resrv__DOT__valid_address_match)) + | (((0x200U & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__cache_miss_resrv__DOT__valid_table)) + ? (1U & ((0x3ffffffU & ((vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__cache_miss_resrv__DOT__addr_table[8U] + << 0x16U) + | (vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__cache_miss_resrv__DOT__addr_table[7U] + >> 0xaU))) + == vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__addr_st1 + [0U])) : 0U) << 9U)); + vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__cache_miss_resrv__DOT__valid_address_match + = ((0xfbffU & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__cache_miss_resrv__DOT__valid_address_match)) + | (((0x400U & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__cache_miss_resrv__DOT__valid_table)) + ? (1U & ((0x3ffffffU & ((vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__cache_miss_resrv__DOT__addr_table[9U] + << 0x1cU) + | (vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__cache_miss_resrv__DOT__addr_table[8U] + >> 4U))) + == vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__addr_st1 + [0U])) : 0U) << 0xaU)); + vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__cache_miss_resrv__DOT__valid_address_match + = ((0xf7ffU & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__cache_miss_resrv__DOT__valid_address_match)) + | (((0x800U & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__cache_miss_resrv__DOT__valid_table)) + ? (1U & ((0x3ffffffU & ((vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__cache_miss_resrv__DOT__addr_table[9U] + << 2U) | ( + vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__cache_miss_resrv__DOT__addr_table[8U] + >> 0x1eU))) + == vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__addr_st1 + [0U])) : 0U) << 0xbU)); + vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__cache_miss_resrv__DOT__valid_address_match + = ((0xefffU & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__cache_miss_resrv__DOT__valid_address_match)) + | (((0x1000U & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__cache_miss_resrv__DOT__valid_table)) + ? (1U & ((0x3ffffffU & ((vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__cache_miss_resrv__DOT__addr_table[0xaU] + << 8U) | ( + vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__cache_miss_resrv__DOT__addr_table[9U] + >> 0x18U))) + == vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__addr_st1 + [0U])) : 0U) << 0xcU)); + vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__cache_miss_resrv__DOT__valid_address_match + = ((0xdfffU & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__cache_miss_resrv__DOT__valid_address_match)) + | (((0x2000U & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__cache_miss_resrv__DOT__valid_table)) + ? (1U & ((0x3ffffffU & ((vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__cache_miss_resrv__DOT__addr_table[0xbU] + << 0xeU) | + (vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__cache_miss_resrv__DOT__addr_table[0xaU] + >> 0x12U))) + == vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__addr_st1 + [0U])) : 0U) << 0xdU)); + vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__cache_miss_resrv__DOT__valid_address_match + = ((0xbfffU & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__cache_miss_resrv__DOT__valid_address_match)) + | (((0x4000U & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__cache_miss_resrv__DOT__valid_table)) + ? (1U & ((0x3ffffffU & ((vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__cache_miss_resrv__DOT__addr_table[0xcU] + << 0x14U) + | (vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__cache_miss_resrv__DOT__addr_table[0xbU] + >> 0xcU))) + == vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__addr_st1 + [0U])) : 0U) << 0xeU)); + vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__cache_miss_resrv__DOT__valid_address_match + = ((0x7fffU & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__cache_miss_resrv__DOT__valid_address_match)) + | (((0x8000U & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__cache_miss_resrv__DOT__valid_table)) + ? (1U & ((0x3ffffffU & (vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__cache_miss_resrv__DOT__addr_table[0xcU] + >> 6U)) == + vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__addr_st1 + [0U])) : 0U) << 0xfU)); + vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__tag_data_access__DOT____Vcellinp__s0_1_c0__in[0U] + = vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__data + [(0x3fU & vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__addr_st1 + [0U])][0U]; + vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__tag_data_access__DOT____Vcellinp__s0_1_c0__in[1U] + = vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__data + [(0x3fU & vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__addr_st1 + [0U])][1U]; + vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__tag_data_access__DOT____Vcellinp__s0_1_c0__in[2U] + = vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__data + [(0x3fU & vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__addr_st1 + [0U])][2U]; + vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__tag_data_access__DOT____Vcellinp__s0_1_c0__in[3U] + = vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__data + [(0x3fU & vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__addr_st1 + [0U])][3U]; + vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__tag_data_access__DOT____Vcellinp__s0_1_c0__in[4U] + = ((0xfff00000U & (vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__dirtyb + [(0x3fU & vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__addr_st1 + [0U])] << 0x14U)) | vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__tag + [(0x3fU & vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__addr_st1 + [0U])]); + vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__tag_data_access__DOT____Vcellinp__s0_1_c0__in[5U] + = ((0x20U & ((IData)((vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__valid + >> (0x3fU & vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__addr_st1 + [0U]))) << 5U)) | + ((0x10U & ((IData)((vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__dirty + >> (0x3fU & vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__addr_st1 + [0U]))) << 4U)) + | (0xfffffU & (vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__dirtyb + [(0x3fU & vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__addr_st1 + [0U])] >> 0xcU)))); + vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cache_miss_resrv__DOT__valid_address_match + = ((0xfffeU & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cache_miss_resrv__DOT__valid_address_match)) + | ((1U & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cache_miss_resrv__DOT__valid_table)) + ? (1U & ((0x3ffffffU & vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cache_miss_resrv__DOT__addr_table[0U]) + == vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__addr_st1 + [0U])) : 0U)); + vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cache_miss_resrv__DOT__valid_address_match + = ((0xfffdU & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cache_miss_resrv__DOT__valid_address_match)) + | (((2U & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cache_miss_resrv__DOT__valid_table)) + ? (1U & ((0x3ffffffU & ((vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cache_miss_resrv__DOT__addr_table[1U] + << 6U) | ( + vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cache_miss_resrv__DOT__addr_table[0U] + >> 0x1aU))) + == vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__addr_st1 + [0U])) : 0U) << 1U)); + vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cache_miss_resrv__DOT__valid_address_match + = ((0xfffbU & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cache_miss_resrv__DOT__valid_address_match)) + | (((4U & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cache_miss_resrv__DOT__valid_table)) + ? (1U & ((0x3ffffffU & ((vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cache_miss_resrv__DOT__addr_table[2U] + << 0xcU) | + (vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cache_miss_resrv__DOT__addr_table[1U] + >> 0x14U))) + == vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__addr_st1 + [0U])) : 0U) << 2U)); + vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cache_miss_resrv__DOT__valid_address_match + = ((0xfff7U & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cache_miss_resrv__DOT__valid_address_match)) + | (((8U & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cache_miss_resrv__DOT__valid_table)) + ? (1U & ((0x3ffffffU & ((vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cache_miss_resrv__DOT__addr_table[3U] + << 0x12U) + | (vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cache_miss_resrv__DOT__addr_table[2U] + >> 0xeU))) + == vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__addr_st1 + [0U])) : 0U) << 3U)); + vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cache_miss_resrv__DOT__valid_address_match + = ((0xffefU & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cache_miss_resrv__DOT__valid_address_match)) + | (((0x10U & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cache_miss_resrv__DOT__valid_table)) + ? (1U & ((0x3ffffffU & ((vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cache_miss_resrv__DOT__addr_table[4U] + << 0x18U) + | (vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cache_miss_resrv__DOT__addr_table[3U] + >> 8U))) + == vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__addr_st1 + [0U])) : 0U) << 4U)); + vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cache_miss_resrv__DOT__valid_address_match + = ((0xffdfU & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cache_miss_resrv__DOT__valid_address_match)) + | (((0x20U & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cache_miss_resrv__DOT__valid_table)) + ? (1U & ((0x3ffffffU & ((vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cache_miss_resrv__DOT__addr_table[5U] + << 0x1eU) + | (vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cache_miss_resrv__DOT__addr_table[4U] + >> 2U))) + == vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__addr_st1 + [0U])) : 0U) << 5U)); + vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cache_miss_resrv__DOT__valid_address_match + = ((0xffbfU & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cache_miss_resrv__DOT__valid_address_match)) + | (((0x40U & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cache_miss_resrv__DOT__valid_table)) + ? (1U & ((0x3ffffffU & ((vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cache_miss_resrv__DOT__addr_table[5U] + << 4U) | ( + vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cache_miss_resrv__DOT__addr_table[4U] + >> 0x1cU))) + == vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__addr_st1 + [0U])) : 0U) << 6U)); + vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cache_miss_resrv__DOT__valid_address_match + = ((0xff7fU & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cache_miss_resrv__DOT__valid_address_match)) + | (((0x80U & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cache_miss_resrv__DOT__valid_table)) + ? (1U & ((0x3ffffffU & ((vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cache_miss_resrv__DOT__addr_table[6U] + << 0xaU) | + (vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cache_miss_resrv__DOT__addr_table[5U] + >> 0x16U))) + == vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__addr_st1 + [0U])) : 0U) << 7U)); + vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cache_miss_resrv__DOT__valid_address_match + = ((0xfeffU & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cache_miss_resrv__DOT__valid_address_match)) + | (((0x100U & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cache_miss_resrv__DOT__valid_table)) + ? (1U & ((0x3ffffffU & ((vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cache_miss_resrv__DOT__addr_table[7U] + << 0x10U) + | (vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cache_miss_resrv__DOT__addr_table[6U] + >> 0x10U))) + == vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__addr_st1 + [0U])) : 0U) << 8U)); + vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cache_miss_resrv__DOT__valid_address_match + = ((0xfdffU & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cache_miss_resrv__DOT__valid_address_match)) + | (((0x200U & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cache_miss_resrv__DOT__valid_table)) + ? (1U & ((0x3ffffffU & ((vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cache_miss_resrv__DOT__addr_table[8U] + << 0x16U) + | (vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cache_miss_resrv__DOT__addr_table[7U] + >> 0xaU))) + == vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__addr_st1 + [0U])) : 0U) << 9U)); + vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cache_miss_resrv__DOT__valid_address_match + = ((0xfbffU & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cache_miss_resrv__DOT__valid_address_match)) + | (((0x400U & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cache_miss_resrv__DOT__valid_table)) + ? (1U & ((0x3ffffffU & ((vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cache_miss_resrv__DOT__addr_table[9U] + << 0x1cU) + | (vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cache_miss_resrv__DOT__addr_table[8U] + >> 4U))) + == vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__addr_st1 + [0U])) : 0U) << 0xaU)); + vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cache_miss_resrv__DOT__valid_address_match + = ((0xf7ffU & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cache_miss_resrv__DOT__valid_address_match)) + | (((0x800U & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cache_miss_resrv__DOT__valid_table)) + ? (1U & ((0x3ffffffU & ((vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cache_miss_resrv__DOT__addr_table[9U] + << 2U) | ( + vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cache_miss_resrv__DOT__addr_table[8U] + >> 0x1eU))) + == vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__addr_st1 + [0U])) : 0U) << 0xbU)); + vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cache_miss_resrv__DOT__valid_address_match + = ((0xefffU & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cache_miss_resrv__DOT__valid_address_match)) + | (((0x1000U & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cache_miss_resrv__DOT__valid_table)) + ? (1U & ((0x3ffffffU & ((vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cache_miss_resrv__DOT__addr_table[0xaU] + << 8U) | ( + vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cache_miss_resrv__DOT__addr_table[9U] + >> 0x18U))) + == vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__addr_st1 + [0U])) : 0U) << 0xcU)); + vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cache_miss_resrv__DOT__valid_address_match + = ((0xdfffU & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cache_miss_resrv__DOT__valid_address_match)) + | (((0x2000U & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cache_miss_resrv__DOT__valid_table)) + ? (1U & ((0x3ffffffU & ((vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cache_miss_resrv__DOT__addr_table[0xbU] + << 0xeU) | + (vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cache_miss_resrv__DOT__addr_table[0xaU] + >> 0x12U))) + == vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__addr_st1 + [0U])) : 0U) << 0xdU)); + vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cache_miss_resrv__DOT__valid_address_match + = ((0xbfffU & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cache_miss_resrv__DOT__valid_address_match)) + | (((0x4000U & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cache_miss_resrv__DOT__valid_table)) + ? (1U & ((0x3ffffffU & ((vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cache_miss_resrv__DOT__addr_table[0xcU] + << 0x14U) + | (vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cache_miss_resrv__DOT__addr_table[0xbU] + >> 0xcU))) + == vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__addr_st1 + [0U])) : 0U) << 0xeU)); + vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cache_miss_resrv__DOT__valid_address_match + = ((0x7fffU & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cache_miss_resrv__DOT__valid_address_match)) + | (((0x8000U & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cache_miss_resrv__DOT__valid_table)) + ? (1U & ((0x3ffffffU & (vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cache_miss_resrv__DOT__addr_table[0xcU] + >> 6U)) == + vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__addr_st1 + [0U])) : 0U) << 0xfU)); + vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__tag_data_access__DOT____Vcellinp__s0_1_c0__in[0U] + = vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__data + [(0x3fU & vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__addr_st1 + [0U])][0U]; + vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__tag_data_access__DOT____Vcellinp__s0_1_c0__in[1U] + = vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__data + [(0x3fU & vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__addr_st1 + [0U])][1U]; + vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__tag_data_access__DOT____Vcellinp__s0_1_c0__in[2U] + = vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__data + [(0x3fU & vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__addr_st1 + [0U])][2U]; + vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__tag_data_access__DOT____Vcellinp__s0_1_c0__in[3U] + = vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__data + [(0x3fU & vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__addr_st1 + [0U])][3U]; + vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__tag_data_access__DOT____Vcellinp__s0_1_c0__in[4U] + = ((0xfff00000U & (vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__dirtyb + [(0x3fU & vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__addr_st1 + [0U])] << 0x14U)) | vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__tag + [(0x3fU & vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__addr_st1 + [0U])]); + vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__tag_data_access__DOT____Vcellinp__s0_1_c0__in[5U] + = ((0x20U & ((IData)((vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__valid + >> (0x3fU & vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__addr_st1 + [0U]))) << 5U)) | + ((0x10U & ((IData)((vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__dirty + >> (0x3fU & vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__addr_st1 + [0U]))) << 4U)) + | (0xfffffU & (vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__dirtyb + [(0x3fU & vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__addr_st1 + [0U])] >> 0xcU)))); + vlTOPp->VX_cache__DOT__cache_core_rsp_merge__DOT__sel_bank__DOT__genblk2__DOT__grant_onehot_r = 0U; + vlTOPp->VX_cache__DOT__cache_core_rsp_merge__DOT__sel_bank__DOT__genblk2__DOT__grant_onehot_r + = ((IData)(vlTOPp->VX_cache__DOT__cache_core_rsp_merge__DOT__sel_bank__DOT__genblk2__DOT__grant_onehot_r) + | ((IData)(1U) << (IData)(vlTOPp->VX_cache__DOT__cache_core_rsp_merge__DOT__main_bank_index))); + vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cwbq_push_stall + = ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cwbq_push_unqual) + & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cwb_queue__DOT__genblk3__DOT__genblk2__DOT__full_r)); + vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__cwbq_push_stall + = ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__cwbq_push_unqual) + & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__cwb_queue__DOT__genblk3__DOT__genblk2__DOT__full_r)); + vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__cwbq_push_stall + = ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__cwbq_push_unqual) + & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__cwb_queue__DOT__genblk3__DOT__genblk2__DOT__full_r)); + vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cwbq_push_stall + = ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cwbq_push_unqual) + & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cwb_queue__DOT__genblk3__DOT__genblk2__DOT__full_r)); + vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT____Vcellinp__dwb_queue__data_in[0U] + = ((0xf0000000U & (vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__st_1e_2__DOT__value[2U] + << 5U)) | (0xfffffffU & + ((vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__st_1e_2__DOT__value[1U] + << 0x19U) | + (vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__st_1e_2__DOT__value[0U] + >> 7U)))); + vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT____Vcellinp__dwb_queue__data_in[1U] + = ((0xfffffffU & ((0xfffffe0U & (vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__st_1e_2__DOT__value[3U] + << 5U)) | + (vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__st_1e_2__DOT__value[2U] + >> 0x1bU))) | (0xf0000000U + & (vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__st_1e_2__DOT__value[3U] + << 5U))); + vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT____Vcellinp__dwb_queue__data_in[2U] + = ((0xfffffffU & ((0xfffffe0U & (vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__st_1e_2__DOT__value[4U] + << 5U)) | + (vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__st_1e_2__DOT__value[3U] + >> 0x1bU))) | (0xf0000000U + & (vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__st_1e_2__DOT__value[4U] + << 5U))); + vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT____Vcellinp__dwb_queue__data_in[3U] + = ((0xfffffffU & ((0xfffffe0U & (vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__st_1e_2__DOT__value[5U] + << 5U)) | + (vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__st_1e_2__DOT__value[4U] + >> 0x1bU))) | (0xf0000000U + & (vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__st_1e_2__DOT__value[5U] + << 5U))); + vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT____Vcellinp__dwb_queue__data_in[4U] + = ((0xf0000000U & (vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__st_1e_2__DOT__value[8U] + << 3U)) | (0xfffffffU & + ((0xfffffe0U + & (vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__st_1e_2__DOT__value[6U] + << 5U)) + | (vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__st_1e_2__DOT__value[5U] + >> 0x1bU)))); + vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT____Vcellinp__dwb_queue__data_in[5U] + = ((0xffc00000U & (vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__st_1e_2__DOT__value[1U] + << 5U)) | (0xfffffffU & + ((0x3ffffcU & + (vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__st_1e_2__DOT__value[2U] + >> 1U)) | + (3U & ((0xffffff8U + & (vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__st_1e_2__DOT__value[9U] + << 3U)) + | (vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__st_1e_2__DOT__value[8U] + >> 0x1dU)))))); + vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT____Vcellinp__dwb_queue__data_in[6U] + = ((0xffffff80U & ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__dwbq_is_dwb_in) + << 7U)) | ((0xffffffc0U + & ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__dwbq_is_snp_in) + << 6U)) | + (0x3fU & ((0x3fffe0U + & (vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__st_1e_2__DOT__value[2U] + << 5U)) + | (vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__st_1e_2__DOT__value[1U] + >> 0x1bU))))); + vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__dwbq_push_unqual + = ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__dwbq_is_dwb_in) + | (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__dwbq_is_snp_in)); + vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT____Vcellinp__dwb_queue__data_in[0U] + = ((0xf0000000U & (vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__st_1e_2__DOT__value[2U] + << 5U)) | (0xfffffffU & + ((vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__st_1e_2__DOT__value[1U] + << 0x19U) | + (vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__st_1e_2__DOT__value[0U] + >> 7U)))); + vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT____Vcellinp__dwb_queue__data_in[1U] + = ((0xfffffffU & ((0xfffffe0U & (vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__st_1e_2__DOT__value[3U] + << 5U)) | + (vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__st_1e_2__DOT__value[2U] + >> 0x1bU))) | (0xf0000000U + & (vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__st_1e_2__DOT__value[3U] + << 5U))); + vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT____Vcellinp__dwb_queue__data_in[2U] + = ((0xfffffffU & ((0xfffffe0U & (vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__st_1e_2__DOT__value[4U] + << 5U)) | + (vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__st_1e_2__DOT__value[3U] + >> 0x1bU))) | (0xf0000000U + & (vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__st_1e_2__DOT__value[4U] + << 5U))); + vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT____Vcellinp__dwb_queue__data_in[3U] + = ((0xfffffffU & ((0xfffffe0U & (vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__st_1e_2__DOT__value[5U] + << 5U)) | + (vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__st_1e_2__DOT__value[4U] + >> 0x1bU))) | (0xf0000000U + & (vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__st_1e_2__DOT__value[5U] + << 5U))); + vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT____Vcellinp__dwb_queue__data_in[4U] + = ((0xf0000000U & (vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__st_1e_2__DOT__value[8U] + << 3U)) | (0xfffffffU & + ((0xfffffe0U + & (vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__st_1e_2__DOT__value[6U] + << 5U)) + | (vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__st_1e_2__DOT__value[5U] + >> 0x1bU)))); + vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT____Vcellinp__dwb_queue__data_in[5U] + = ((0xffc00000U & (vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__st_1e_2__DOT__value[1U] + << 5U)) | (0xfffffffU & + ((0x3ffffcU & + (vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__st_1e_2__DOT__value[2U] + >> 1U)) | + (3U & ((0xffffff8U + & (vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__st_1e_2__DOT__value[9U] + << 3U)) + | (vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__st_1e_2__DOT__value[8U] + >> 0x1dU)))))); + vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT____Vcellinp__dwb_queue__data_in[6U] + = ((0xffffff80U & ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__dwbq_is_dwb_in) + << 7U)) | ((0xffffffc0U + & ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__dwbq_is_snp_in) + << 6U)) | + (0x3fU & ((0x3fffe0U + & (vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__st_1e_2__DOT__value[2U] + << 5U)) + | (vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__st_1e_2__DOT__value[1U] + >> 0x1bU))))); + vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__dwbq_push_unqual + = ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__dwbq_is_dwb_in) + | (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__dwbq_is_snp_in)); + vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT____Vcellinp__dwb_queue__data_in[0U] + = ((0xf0000000U & (vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__st_1e_2__DOT__value[2U] + << 5U)) | (0xfffffffU & + ((vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__st_1e_2__DOT__value[1U] + << 0x19U) | + (vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__st_1e_2__DOT__value[0U] + >> 7U)))); + vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT____Vcellinp__dwb_queue__data_in[1U] + = ((0xfffffffU & ((0xfffffe0U & (vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__st_1e_2__DOT__value[3U] + << 5U)) | + (vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__st_1e_2__DOT__value[2U] + >> 0x1bU))) | (0xf0000000U + & (vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__st_1e_2__DOT__value[3U] + << 5U))); + vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT____Vcellinp__dwb_queue__data_in[2U] + = ((0xfffffffU & ((0xfffffe0U & (vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__st_1e_2__DOT__value[4U] + << 5U)) | + (vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__st_1e_2__DOT__value[3U] + >> 0x1bU))) | (0xf0000000U + & (vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__st_1e_2__DOT__value[4U] + << 5U))); + vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT____Vcellinp__dwb_queue__data_in[3U] + = ((0xfffffffU & ((0xfffffe0U & (vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__st_1e_2__DOT__value[5U] + << 5U)) | + (vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__st_1e_2__DOT__value[4U] + >> 0x1bU))) | (0xf0000000U + & (vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__st_1e_2__DOT__value[5U] + << 5U))); + vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT____Vcellinp__dwb_queue__data_in[4U] + = ((0xf0000000U & (vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__st_1e_2__DOT__value[8U] + << 3U)) | (0xfffffffU & + ((0xfffffe0U + & (vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__st_1e_2__DOT__value[6U] + << 5U)) + | (vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__st_1e_2__DOT__value[5U] + >> 0x1bU)))); + vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT____Vcellinp__dwb_queue__data_in[5U] + = ((0xffc00000U & (vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__st_1e_2__DOT__value[1U] + << 5U)) | (0xfffffffU & + ((0x3ffffcU & + (vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__st_1e_2__DOT__value[2U] + >> 1U)) | + (3U & ((0xffffff8U + & (vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__st_1e_2__DOT__value[9U] + << 3U)) + | (vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__st_1e_2__DOT__value[8U] + >> 0x1dU)))))); + vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT____Vcellinp__dwb_queue__data_in[6U] + = ((0xffffff80U & ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__dwbq_is_dwb_in) + << 7U)) | ((0xffffffc0U + & ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__dwbq_is_snp_in) + << 6U)) | + (0x3fU & ((0x3fffe0U + & (vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__st_1e_2__DOT__value[2U] + << 5U)) + | (vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__st_1e_2__DOT__value[1U] + >> 0x1bU))))); + vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__dwbq_push_unqual + = ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__dwbq_is_dwb_in) + | (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__dwbq_is_snp_in)); + vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT____Vcellinp__dwb_queue__data_in[0U] + = ((0xf0000000U & (vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__st_1e_2__DOT__value[2U] + << 5U)) | (0xfffffffU & + ((vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__st_1e_2__DOT__value[1U] + << 0x19U) | + (vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__st_1e_2__DOT__value[0U] + >> 7U)))); + vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT____Vcellinp__dwb_queue__data_in[1U] + = ((0xfffffffU & ((0xfffffe0U & (vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__st_1e_2__DOT__value[3U] + << 5U)) | + (vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__st_1e_2__DOT__value[2U] + >> 0x1bU))) | (0xf0000000U + & (vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__st_1e_2__DOT__value[3U] + << 5U))); + vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT____Vcellinp__dwb_queue__data_in[2U] + = ((0xfffffffU & ((0xfffffe0U & (vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__st_1e_2__DOT__value[4U] + << 5U)) | + (vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__st_1e_2__DOT__value[3U] + >> 0x1bU))) | (0xf0000000U + & (vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__st_1e_2__DOT__value[4U] + << 5U))); + vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT____Vcellinp__dwb_queue__data_in[3U] + = ((0xfffffffU & ((0xfffffe0U & (vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__st_1e_2__DOT__value[5U] + << 5U)) | + (vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__st_1e_2__DOT__value[4U] + >> 0x1bU))) | (0xf0000000U + & (vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__st_1e_2__DOT__value[5U] + << 5U))); + vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT____Vcellinp__dwb_queue__data_in[4U] + = ((0xf0000000U & (vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__st_1e_2__DOT__value[8U] + << 3U)) | (0xfffffffU & + ((0xfffffe0U + & (vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__st_1e_2__DOT__value[6U] + << 5U)) + | (vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__st_1e_2__DOT__value[5U] + >> 0x1bU)))); + vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT____Vcellinp__dwb_queue__data_in[5U] + = ((0xffc00000U & (vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__st_1e_2__DOT__value[1U] + << 5U)) | (0xfffffffU & + ((0x3ffffcU & + (vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__st_1e_2__DOT__value[2U] + >> 1U)) | + (3U & ((0xffffff8U + & (vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__st_1e_2__DOT__value[9U] + << 3U)) + | (vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__st_1e_2__DOT__value[8U] + >> 0x1dU)))))); + vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT____Vcellinp__dwb_queue__data_in[6U] + = ((0xffffff80U & ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__dwbq_is_dwb_in) + << 7U)) | ((0xffffffc0U + & ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__dwbq_is_snp_in) + << 6U)) | + (0x3fU & ((0x3fffe0U + & (vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__st_1e_2__DOT__value[2U] + << 5U)) + | (vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__st_1e_2__DOT__value[1U] + >> 0x1bU))))); + vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__dwbq_push_unqual + = ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__dwbq_is_dwb_in) + | (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__dwbq_is_snp_in)); + vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__miss_add_unqual + = (1U & ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__miss_add_because_miss) + | (vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__st_1e_2__DOT__value[9U] + >> 0x18U))); + vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__miss_add_unqual + = (1U & ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__miss_add_because_miss) + | (vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__st_1e_2__DOT__value[9U] + >> 0x18U))); + vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__miss_add_unqual + = (1U & ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__miss_add_because_miss) + | (vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__st_1e_2__DOT__value[9U] + >> 0x18U))); + vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__miss_add_unqual + = (1U & ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__miss_add_because_miss) + | (vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__st_1e_2__DOT__value[9U] + >> 0x18U))); + vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__core_req_arb__DOT__pop_qual + = (1U & ((~ (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__core_req_arb__DOT__out_empty)) + & (~ (IData)((0U != (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__core_req_arb__DOT__use_per_valids)))))); + vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__core_req_arb__DOT__pop_qual + = (1U & ((~ (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__core_req_arb__DOT__out_empty)) + & (~ (IData)((0U != (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__core_req_arb__DOT__use_per_valids)))))); + vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__core_req_arb__DOT__pop_qual + = (1U & ((~ (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__core_req_arb__DOT__out_empty)) + & (~ (IData)((0U != (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__core_req_arb__DOT__use_per_valids)))))); + vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__core_req_arb__DOT__pop_qual + = (1U & ((~ (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__core_req_arb__DOT__out_empty)) + & (~ (IData)((0U != (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__core_req_arb__DOT__use_per_valids)))))); + vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__curr_bank_core_req_valid + = (0xfU & ((IData)(vlTOPp->VX_cache__DOT____Vcellout__cache_core_req_bank_sel__per_bank_valid) + & VL_NEGATE_I((IData)((IData)(vlTOPp->core_req_ready))))); + vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__curr_bank_core_req_valid + = (0xfU & (((IData)(vlTOPp->VX_cache__DOT____Vcellout__cache_core_req_bank_sel__per_bank_valid) + >> 4U) & VL_NEGATE_I((IData)((IData)(vlTOPp->core_req_ready))))); + vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__curr_bank_core_req_valid + = (0xfU & (((IData)(vlTOPp->VX_cache__DOT____Vcellout__cache_core_req_bank_sel__per_bank_valid) + >> 8U) & VL_NEGATE_I((IData)((IData)(vlTOPp->core_req_ready))))); + vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__curr_bank_core_req_valid + = (0xfU & (((IData)(vlTOPp->VX_cache__DOT____Vcellout__cache_core_req_bank_sel__per_bank_valid) + >> 0xcU) & VL_NEGATE_I((IData)((IData)(vlTOPp->core_req_ready))))); + vlTOPp->core_rsp_tag = ((0xa7U >= (0xffU & ((IData)(0x2aU) + * (IData)(vlTOPp->VX_cache__DOT__cache_core_rsp_merge__DOT__main_bank_index)))) + ? (VL_ULL(0x3ffffffffff) + & (((0U == (0x1fU & + ((IData)(0x2aU) + * (IData)(vlTOPp->VX_cache__DOT__cache_core_rsp_merge__DOT__main_bank_index)))) + ? VL_ULL(0) : + ((QData)((IData)( + vlTOPp->VX_cache__DOT__per_bank_core_rsp_tag[ + ((IData)(2U) + + + (7U + & (((IData)(0x2aU) + * (IData)(vlTOPp->VX_cache__DOT__cache_core_rsp_merge__DOT__main_bank_index)) + >> 5U)))])) + << ((IData)(0x40U) + - (0x1fU & + ((IData)(0x2aU) + * (IData)(vlTOPp->VX_cache__DOT__cache_core_rsp_merge__DOT__main_bank_index)))))) + | (((QData)((IData)( + vlTOPp->VX_cache__DOT__per_bank_core_rsp_tag[ + ((IData)(1U) + + + (7U + & (((IData)(0x2aU) + * (IData)(vlTOPp->VX_cache__DOT__cache_core_rsp_merge__DOT__main_bank_index)) + >> 5U)))])) + << ((0U == (0x1fU + & ((IData)(0x2aU) + * (IData)(vlTOPp->VX_cache__DOT__cache_core_rsp_merge__DOT__main_bank_index)))) + ? 0x20U + : ((IData)(0x20U) + - (0x1fU + & ((IData)(0x2aU) + * (IData)(vlTOPp->VX_cache__DOT__cache_core_rsp_merge__DOT__main_bank_index)))))) + | ((QData)((IData)( + vlTOPp->VX_cache__DOT__per_bank_core_rsp_tag[ + (7U + & (((IData)(0x2aU) + * (IData)(vlTOPp->VX_cache__DOT__cache_core_rsp_merge__DOT__main_bank_index)) + >> 5U))])) + >> (0x1fU + & ((IData)(0x2aU) + * (IData)(vlTOPp->VX_cache__DOT__cache_core_rsp_merge__DOT__main_bank_index))))))) + : VL_ULL(0)); + vlTOPp->core_rsp_valid = 0U; + if (((IData)(vlTOPp->VX_cache__DOT__per_bank_core_rsp_valid) + & ((0xffU & vlTOPp->VX_cache__DOT__per_bank_core_rsp_tag[0U]) + == ((0xa7U >= (0xffU & ((IData)(0x2aU) + * (IData)(vlTOPp->VX_cache__DOT__cache_core_rsp_merge__DOT__main_bank_index)))) + ? (0xffU & (((0U == (0x1fU & ((IData)(0x2aU) + * (IData)(vlTOPp->VX_cache__DOT__cache_core_rsp_merge__DOT__main_bank_index)))) + ? 0U : (vlTOPp->VX_cache__DOT__per_bank_core_rsp_tag[ + ((IData)(1U) + + (7U & (((IData)(0x2aU) + * (IData)(vlTOPp->VX_cache__DOT__cache_core_rsp_merge__DOT__main_bank_index)) + >> 5U)))] + << ((IData)(0x20U) + - (0x1fU + & ((IData)(0x2aU) + * (IData)(vlTOPp->VX_cache__DOT__cache_core_rsp_merge__DOT__main_bank_index)))))) + | (vlTOPp->VX_cache__DOT__per_bank_core_rsp_tag[ + (7U & (((IData)(0x2aU) + * (IData)(vlTOPp->VX_cache__DOT__cache_core_rsp_merge__DOT__main_bank_index)) + >> 5U))] >> + (0x1fU & ((IData)(0x2aU) + * (IData)(vlTOPp->VX_cache__DOT__cache_core_rsp_merge__DOT__main_bank_index)))))) + : 0U)))) { + vlTOPp->core_rsp_valid = ((IData)(vlTOPp->core_rsp_valid) + | ((IData)(1U) << + (3U & (IData)(vlTOPp->VX_cache__DOT__per_bank_core_rsp_tid)))); + } + if ((((IData)(vlTOPp->VX_cache__DOT__per_bank_core_rsp_valid) + >> 1U) & ((0xffU & ((vlTOPp->VX_cache__DOT__per_bank_core_rsp_tag[2U] + << 0x16U) | (vlTOPp->VX_cache__DOT__per_bank_core_rsp_tag[1U] + >> 0xaU))) + == ((0xa7U >= (0xffU & ((IData)(0x2aU) + * (IData)(vlTOPp->VX_cache__DOT__cache_core_rsp_merge__DOT__main_bank_index)))) + ? (0xffU & (((0U == (0x1fU + & ((IData)(0x2aU) + * (IData)(vlTOPp->VX_cache__DOT__cache_core_rsp_merge__DOT__main_bank_index)))) + ? 0U : (vlTOPp->VX_cache__DOT__per_bank_core_rsp_tag[ + ((IData)(1U) + + (7U + & (((IData)(0x2aU) + * (IData)(vlTOPp->VX_cache__DOT__cache_core_rsp_merge__DOT__main_bank_index)) + >> 5U)))] + << ((IData)(0x20U) + - + (0x1fU + & ((IData)(0x2aU) + * (IData)(vlTOPp->VX_cache__DOT__cache_core_rsp_merge__DOT__main_bank_index)))))) + | (vlTOPp->VX_cache__DOT__per_bank_core_rsp_tag[ + (7U & (((IData)(0x2aU) + * (IData)(vlTOPp->VX_cache__DOT__cache_core_rsp_merge__DOT__main_bank_index)) + >> 5U))] + >> (0x1fU & + ((IData)(0x2aU) + * (IData)(vlTOPp->VX_cache__DOT__cache_core_rsp_merge__DOT__main_bank_index)))))) + : 0U)))) { + vlTOPp->core_rsp_valid = ((IData)(vlTOPp->core_rsp_valid) + | ((IData)(1U) << + (3U & ((IData)(vlTOPp->VX_cache__DOT__per_bank_core_rsp_tid) + >> 2U)))); + } + if ((((IData)(vlTOPp->VX_cache__DOT__per_bank_core_rsp_valid) + >> 2U) & ((0xffU & ((vlTOPp->VX_cache__DOT__per_bank_core_rsp_tag[3U] + << 0xcU) | (vlTOPp->VX_cache__DOT__per_bank_core_rsp_tag[2U] + >> 0x14U))) + == ((0xa7U >= (0xffU & ((IData)(0x2aU) + * (IData)(vlTOPp->VX_cache__DOT__cache_core_rsp_merge__DOT__main_bank_index)))) + ? (0xffU & (((0U == (0x1fU + & ((IData)(0x2aU) + * (IData)(vlTOPp->VX_cache__DOT__cache_core_rsp_merge__DOT__main_bank_index)))) + ? 0U : (vlTOPp->VX_cache__DOT__per_bank_core_rsp_tag[ + ((IData)(1U) + + (7U + & (((IData)(0x2aU) + * (IData)(vlTOPp->VX_cache__DOT__cache_core_rsp_merge__DOT__main_bank_index)) + >> 5U)))] + << ((IData)(0x20U) + - + (0x1fU + & ((IData)(0x2aU) + * (IData)(vlTOPp->VX_cache__DOT__cache_core_rsp_merge__DOT__main_bank_index)))))) + | (vlTOPp->VX_cache__DOT__per_bank_core_rsp_tag[ + (7U & (((IData)(0x2aU) + * (IData)(vlTOPp->VX_cache__DOT__cache_core_rsp_merge__DOT__main_bank_index)) + >> 5U))] + >> (0x1fU & + ((IData)(0x2aU) + * (IData)(vlTOPp->VX_cache__DOT__cache_core_rsp_merge__DOT__main_bank_index)))))) + : 0U)))) { + vlTOPp->core_rsp_valid = ((IData)(vlTOPp->core_rsp_valid) + | ((IData)(1U) << + (3U & ((IData)(vlTOPp->VX_cache__DOT__per_bank_core_rsp_tid) + >> 4U)))); + } + if ((((IData)(vlTOPp->VX_cache__DOT__per_bank_core_rsp_valid) + >> 3U) & ((0xffU & ((vlTOPp->VX_cache__DOT__per_bank_core_rsp_tag[4U] + << 2U) | (vlTOPp->VX_cache__DOT__per_bank_core_rsp_tag[3U] + >> 0x1eU))) + == ((0xa7U >= (0xffU & ((IData)(0x2aU) + * (IData)(vlTOPp->VX_cache__DOT__cache_core_rsp_merge__DOT__main_bank_index)))) + ? (0xffU & (((0U == (0x1fU + & ((IData)(0x2aU) + * (IData)(vlTOPp->VX_cache__DOT__cache_core_rsp_merge__DOT__main_bank_index)))) + ? 0U : (vlTOPp->VX_cache__DOT__per_bank_core_rsp_tag[ + ((IData)(1U) + + (7U + & (((IData)(0x2aU) + * (IData)(vlTOPp->VX_cache__DOT__cache_core_rsp_merge__DOT__main_bank_index)) + >> 5U)))] + << ((IData)(0x20U) + - + (0x1fU + & ((IData)(0x2aU) + * (IData)(vlTOPp->VX_cache__DOT__cache_core_rsp_merge__DOT__main_bank_index)))))) + | (vlTOPp->VX_cache__DOT__per_bank_core_rsp_tag[ + (7U & (((IData)(0x2aU) + * (IData)(vlTOPp->VX_cache__DOT__cache_core_rsp_merge__DOT__main_bank_index)) + >> 5U))] + >> (0x1fU & + ((IData)(0x2aU) + * (IData)(vlTOPp->VX_cache__DOT__cache_core_rsp_merge__DOT__main_bank_index)))))) + : 0U)))) { + vlTOPp->core_rsp_valid = ((IData)(vlTOPp->core_rsp_valid) + | ((IData)(1U) << + (3U & ((IData)(vlTOPp->VX_cache__DOT__per_bank_core_rsp_tid) + >> 6U)))); + } + vlTOPp->VX_cache__DOT____Vcellout__cache_core_rsp_merge__core_rsp_data[0U] = 0U; + vlTOPp->VX_cache__DOT____Vcellout__cache_core_rsp_merge__core_rsp_data[1U] = 0U; + vlTOPp->VX_cache__DOT____Vcellout__cache_core_rsp_merge__core_rsp_data[2U] = 0U; + vlTOPp->VX_cache__DOT____Vcellout__cache_core_rsp_merge__core_rsp_data[3U] = 0U; + if (((IData)(vlTOPp->VX_cache__DOT__per_bank_core_rsp_valid) + & ((0xffU & vlTOPp->VX_cache__DOT__per_bank_core_rsp_tag[0U]) + == ((0xa7U >= (0xffU & ((IData)(0x2aU) + * (IData)(vlTOPp->VX_cache__DOT__cache_core_rsp_merge__DOT__main_bank_index)))) + ? (0xffU & (((0U == (0x1fU & ((IData)(0x2aU) + * (IData)(vlTOPp->VX_cache__DOT__cache_core_rsp_merge__DOT__main_bank_index)))) + ? 0U : (vlTOPp->VX_cache__DOT__per_bank_core_rsp_tag[ + ((IData)(1U) + + (7U & (((IData)(0x2aU) + * (IData)(vlTOPp->VX_cache__DOT__cache_core_rsp_merge__DOT__main_bank_index)) + >> 5U)))] + << ((IData)(0x20U) + - (0x1fU + & ((IData)(0x2aU) + * (IData)(vlTOPp->VX_cache__DOT__cache_core_rsp_merge__DOT__main_bank_index)))))) + | (vlTOPp->VX_cache__DOT__per_bank_core_rsp_tag[ + (7U & (((IData)(0x2aU) + * (IData)(vlTOPp->VX_cache__DOT__cache_core_rsp_merge__DOT__main_bank_index)) + >> 5U))] >> + (0x1fU & ((IData)(0x2aU) + * (IData)(vlTOPp->VX_cache__DOT__cache_core_rsp_merge__DOT__main_bank_index)))))) + : 0U)))) { + VL_ASSIGNSEL_WIII(32,(0x60U & ((IData)(vlTOPp->VX_cache__DOT__per_bank_core_rsp_tid) + << 5U)), vlTOPp->VX_cache__DOT____Vcellout__cache_core_rsp_merge__core_rsp_data, + vlTOPp->VX_cache__DOT__per_bank_core_rsp_data[0U]); + } + if ((((IData)(vlTOPp->VX_cache__DOT__per_bank_core_rsp_valid) + >> 1U) & ((0xffU & ((vlTOPp->VX_cache__DOT__per_bank_core_rsp_tag[2U] + << 0x16U) | (vlTOPp->VX_cache__DOT__per_bank_core_rsp_tag[1U] + >> 0xaU))) + == ((0xa7U >= (0xffU & ((IData)(0x2aU) + * (IData)(vlTOPp->VX_cache__DOT__cache_core_rsp_merge__DOT__main_bank_index)))) + ? (0xffU & (((0U == (0x1fU + & ((IData)(0x2aU) + * (IData)(vlTOPp->VX_cache__DOT__cache_core_rsp_merge__DOT__main_bank_index)))) + ? 0U : (vlTOPp->VX_cache__DOT__per_bank_core_rsp_tag[ + ((IData)(1U) + + (7U + & (((IData)(0x2aU) + * (IData)(vlTOPp->VX_cache__DOT__cache_core_rsp_merge__DOT__main_bank_index)) + >> 5U)))] + << ((IData)(0x20U) + - + (0x1fU + & ((IData)(0x2aU) + * (IData)(vlTOPp->VX_cache__DOT__cache_core_rsp_merge__DOT__main_bank_index)))))) + | (vlTOPp->VX_cache__DOT__per_bank_core_rsp_tag[ + (7U & (((IData)(0x2aU) + * (IData)(vlTOPp->VX_cache__DOT__cache_core_rsp_merge__DOT__main_bank_index)) + >> 5U))] + >> (0x1fU & + ((IData)(0x2aU) + * (IData)(vlTOPp->VX_cache__DOT__cache_core_rsp_merge__DOT__main_bank_index)))))) + : 0U)))) { + VL_ASSIGNSEL_WIII(32,(0x60U & ((IData)(vlTOPp->VX_cache__DOT__per_bank_core_rsp_tid) + << 3U)), vlTOPp->VX_cache__DOT____Vcellout__cache_core_rsp_merge__core_rsp_data, + vlTOPp->VX_cache__DOT__per_bank_core_rsp_data[1U]); + } + if ((((IData)(vlTOPp->VX_cache__DOT__per_bank_core_rsp_valid) + >> 2U) & ((0xffU & ((vlTOPp->VX_cache__DOT__per_bank_core_rsp_tag[3U] + << 0xcU) | (vlTOPp->VX_cache__DOT__per_bank_core_rsp_tag[2U] + >> 0x14U))) + == ((0xa7U >= (0xffU & ((IData)(0x2aU) + * (IData)(vlTOPp->VX_cache__DOT__cache_core_rsp_merge__DOT__main_bank_index)))) + ? (0xffU & (((0U == (0x1fU + & ((IData)(0x2aU) + * (IData)(vlTOPp->VX_cache__DOT__cache_core_rsp_merge__DOT__main_bank_index)))) + ? 0U : (vlTOPp->VX_cache__DOT__per_bank_core_rsp_tag[ + ((IData)(1U) + + (7U + & (((IData)(0x2aU) + * (IData)(vlTOPp->VX_cache__DOT__cache_core_rsp_merge__DOT__main_bank_index)) + >> 5U)))] + << ((IData)(0x20U) + - + (0x1fU + & ((IData)(0x2aU) + * (IData)(vlTOPp->VX_cache__DOT__cache_core_rsp_merge__DOT__main_bank_index)))))) + | (vlTOPp->VX_cache__DOT__per_bank_core_rsp_tag[ + (7U & (((IData)(0x2aU) + * (IData)(vlTOPp->VX_cache__DOT__cache_core_rsp_merge__DOT__main_bank_index)) + >> 5U))] + >> (0x1fU & + ((IData)(0x2aU) + * (IData)(vlTOPp->VX_cache__DOT__cache_core_rsp_merge__DOT__main_bank_index)))))) + : 0U)))) { + VL_ASSIGNSEL_WIII(32,(0x60U & ((IData)(vlTOPp->VX_cache__DOT__per_bank_core_rsp_tid) + << 1U)), vlTOPp->VX_cache__DOT____Vcellout__cache_core_rsp_merge__core_rsp_data, + vlTOPp->VX_cache__DOT__per_bank_core_rsp_data[2U]); + } + if ((((IData)(vlTOPp->VX_cache__DOT__per_bank_core_rsp_valid) + >> 3U) & ((0xffU & ((vlTOPp->VX_cache__DOT__per_bank_core_rsp_tag[4U] + << 2U) | (vlTOPp->VX_cache__DOT__per_bank_core_rsp_tag[3U] + >> 0x1eU))) + == ((0xa7U >= (0xffU & ((IData)(0x2aU) + * (IData)(vlTOPp->VX_cache__DOT__cache_core_rsp_merge__DOT__main_bank_index)))) + ? (0xffU & (((0U == (0x1fU + & ((IData)(0x2aU) + * (IData)(vlTOPp->VX_cache__DOT__cache_core_rsp_merge__DOT__main_bank_index)))) + ? 0U : (vlTOPp->VX_cache__DOT__per_bank_core_rsp_tag[ + ((IData)(1U) + + (7U + & (((IData)(0x2aU) + * (IData)(vlTOPp->VX_cache__DOT__cache_core_rsp_merge__DOT__main_bank_index)) + >> 5U)))] + << ((IData)(0x20U) + - + (0x1fU + & ((IData)(0x2aU) + * (IData)(vlTOPp->VX_cache__DOT__cache_core_rsp_merge__DOT__main_bank_index)))))) + | (vlTOPp->VX_cache__DOT__per_bank_core_rsp_tag[ + (7U & (((IData)(0x2aU) + * (IData)(vlTOPp->VX_cache__DOT__cache_core_rsp_merge__DOT__main_bank_index)) + >> 5U))] + >> (0x1fU & + ((IData)(0x2aU) + * (IData)(vlTOPp->VX_cache__DOT__cache_core_rsp_merge__DOT__main_bank_index)))))) + : 0U)))) { + VL_ASSIGNSEL_WIII(32,(0x60U & ((IData)(vlTOPp->VX_cache__DOT__per_bank_core_rsp_tid) + >> 1U)), vlTOPp->VX_cache__DOT____Vcellout__cache_core_rsp_merge__core_rsp_data, + vlTOPp->VX_cache__DOT__per_bank_core_rsp_data[3U]); + } + vlTOPp->VX_cache__DOT__cache_core_rsp_merge__DOT__per_bank_core_rsp_pop_unqual + = ((0xeU & (IData)(vlTOPp->VX_cache__DOT__cache_core_rsp_merge__DOT__per_bank_core_rsp_pop_unqual)) + | ((IData)(vlTOPp->VX_cache__DOT__per_bank_core_rsp_valid) + & ((0xffU & vlTOPp->VX_cache__DOT__per_bank_core_rsp_tag[0U]) + == ((0xa7U >= (0xffU & ((IData)(0x2aU) + * (IData)(vlTOPp->VX_cache__DOT__cache_core_rsp_merge__DOT__main_bank_index)))) + ? (0xffU & (((0U == (0x1fU & + ((IData)(0x2aU) + * (IData)(vlTOPp->VX_cache__DOT__cache_core_rsp_merge__DOT__main_bank_index)))) + ? 0U : (vlTOPp->VX_cache__DOT__per_bank_core_rsp_tag[ + ((IData)(1U) + + (7U + & (((IData)(0x2aU) + * (IData)(vlTOPp->VX_cache__DOT__cache_core_rsp_merge__DOT__main_bank_index)) + >> 5U)))] + << ((IData)(0x20U) + - (0x1fU + & ((IData)(0x2aU) + * (IData)(vlTOPp->VX_cache__DOT__cache_core_rsp_merge__DOT__main_bank_index)))))) + | (vlTOPp->VX_cache__DOT__per_bank_core_rsp_tag[ + (7U & (((IData)(0x2aU) + * (IData)(vlTOPp->VX_cache__DOT__cache_core_rsp_merge__DOT__main_bank_index)) + >> 5U))] + >> (0x1fU & ((IData)(0x2aU) + * (IData)(vlTOPp->VX_cache__DOT__cache_core_rsp_merge__DOT__main_bank_index)))))) + : 0U)))); + vlTOPp->VX_cache__DOT__cache_core_rsp_merge__DOT__per_bank_core_rsp_pop_unqual + = ((0xdU & (IData)(vlTOPp->VX_cache__DOT__cache_core_rsp_merge__DOT__per_bank_core_rsp_pop_unqual)) + | (0xfffffffeU & ((IData)(vlTOPp->VX_cache__DOT__per_bank_core_rsp_valid) + & (((0xffU & ((vlTOPp->VX_cache__DOT__per_bank_core_rsp_tag[2U] + << 0x16U) + | (vlTOPp->VX_cache__DOT__per_bank_core_rsp_tag[1U] + >> 0xaU))) + == ((0xa7U >= (0xffU + & ((IData)(0x2aU) + * (IData)(vlTOPp->VX_cache__DOT__cache_core_rsp_merge__DOT__main_bank_index)))) + ? (0xffU & (( + (0U + == + (0x1fU + & ((IData)(0x2aU) + * (IData)(vlTOPp->VX_cache__DOT__cache_core_rsp_merge__DOT__main_bank_index)))) + ? 0U + : + (vlTOPp->VX_cache__DOT__per_bank_core_rsp_tag[ + ((IData)(1U) + + + (7U + & (((IData)(0x2aU) + * (IData)(vlTOPp->VX_cache__DOT__cache_core_rsp_merge__DOT__main_bank_index)) + >> 5U)))] + << + ((IData)(0x20U) + - + (0x1fU + & ((IData)(0x2aU) + * (IData)(vlTOPp->VX_cache__DOT__cache_core_rsp_merge__DOT__main_bank_index)))))) + | (vlTOPp->VX_cache__DOT__per_bank_core_rsp_tag[ + (7U + & (((IData)(0x2aU) + * (IData)(vlTOPp->VX_cache__DOT__cache_core_rsp_merge__DOT__main_bank_index)) + >> 5U))] + >> + (0x1fU + & ((IData)(0x2aU) + * (IData)(vlTOPp->VX_cache__DOT__cache_core_rsp_merge__DOT__main_bank_index)))))) + : 0U)) << 1U)))); + vlTOPp->VX_cache__DOT__cache_core_rsp_merge__DOT__per_bank_core_rsp_pop_unqual + = ((0xbU & (IData)(vlTOPp->VX_cache__DOT__cache_core_rsp_merge__DOT__per_bank_core_rsp_pop_unqual)) + | (0xfffffffcU & ((IData)(vlTOPp->VX_cache__DOT__per_bank_core_rsp_valid) + & (((0xffU & ((vlTOPp->VX_cache__DOT__per_bank_core_rsp_tag[3U] + << 0xcU) + | (vlTOPp->VX_cache__DOT__per_bank_core_rsp_tag[2U] + >> 0x14U))) + == ((0xa7U >= (0xffU + & ((IData)(0x2aU) + * (IData)(vlTOPp->VX_cache__DOT__cache_core_rsp_merge__DOT__main_bank_index)))) + ? (0xffU & (( + (0U + == + (0x1fU + & ((IData)(0x2aU) + * (IData)(vlTOPp->VX_cache__DOT__cache_core_rsp_merge__DOT__main_bank_index)))) + ? 0U + : + (vlTOPp->VX_cache__DOT__per_bank_core_rsp_tag[ + ((IData)(1U) + + + (7U + & (((IData)(0x2aU) + * (IData)(vlTOPp->VX_cache__DOT__cache_core_rsp_merge__DOT__main_bank_index)) + >> 5U)))] + << + ((IData)(0x20U) + - + (0x1fU + & ((IData)(0x2aU) + * (IData)(vlTOPp->VX_cache__DOT__cache_core_rsp_merge__DOT__main_bank_index)))))) + | (vlTOPp->VX_cache__DOT__per_bank_core_rsp_tag[ + (7U + & (((IData)(0x2aU) + * (IData)(vlTOPp->VX_cache__DOT__cache_core_rsp_merge__DOT__main_bank_index)) + >> 5U))] + >> + (0x1fU + & ((IData)(0x2aU) + * (IData)(vlTOPp->VX_cache__DOT__cache_core_rsp_merge__DOT__main_bank_index)))))) + : 0U)) << 2U)))); + vlTOPp->VX_cache__DOT__cache_core_rsp_merge__DOT__per_bank_core_rsp_pop_unqual + = ((7U & (IData)(vlTOPp->VX_cache__DOT__cache_core_rsp_merge__DOT__per_bank_core_rsp_pop_unqual)) + | (0xfffffff8U & ((IData)(vlTOPp->VX_cache__DOT__per_bank_core_rsp_valid) + & (((0xffU & ((vlTOPp->VX_cache__DOT__per_bank_core_rsp_tag[4U] + << 2U) + | (vlTOPp->VX_cache__DOT__per_bank_core_rsp_tag[3U] + >> 0x1eU))) + == ((0xa7U >= (0xffU + & ((IData)(0x2aU) + * (IData)(vlTOPp->VX_cache__DOT__cache_core_rsp_merge__DOT__main_bank_index)))) + ? (0xffU & (( + (0U + == + (0x1fU + & ((IData)(0x2aU) + * (IData)(vlTOPp->VX_cache__DOT__cache_core_rsp_merge__DOT__main_bank_index)))) + ? 0U + : + (vlTOPp->VX_cache__DOT__per_bank_core_rsp_tag[ + ((IData)(1U) + + + (7U + & (((IData)(0x2aU) + * (IData)(vlTOPp->VX_cache__DOT__cache_core_rsp_merge__DOT__main_bank_index)) + >> 5U)))] + << + ((IData)(0x20U) + - + (0x1fU + & ((IData)(0x2aU) + * (IData)(vlTOPp->VX_cache__DOT__cache_core_rsp_merge__DOT__main_bank_index)))))) + | (vlTOPp->VX_cache__DOT__per_bank_core_rsp_tag[ + (7U + & (((IData)(0x2aU) + * (IData)(vlTOPp->VX_cache__DOT__cache_core_rsp_merge__DOT__main_bank_index)) + >> 5U))] + >> + (0x1fU + & ((IData)(0x2aU) + * (IData)(vlTOPp->VX_cache__DOT__cache_core_rsp_merge__DOT__main_bank_index)))))) + : 0U)) << 3U)))); + vlTOPp->__Vtableidx1 = vlTOPp->VX_cache__DOT__cache_dram_req_arb__DOT__dram_fill_arb__DOT__use_per_bqual_bank_dram_fill_req_valid; + vlTOPp->VX_cache__DOT__cache_dram_req_arb__DOT__dram_fill_arb__DOT__qual_request_index + = vlTOPp->__Vtable1_VX_cache__DOT__cache_dram_req_arb__DOT__dram_fill_arb__DOT__qual_request_index + [vlTOPp->__Vtableidx1]; + vlTOPp->VX_cache__DOT__cache_dram_req_arb__DOT__dram_fill_arb__DOT__qual_has_request + = vlTOPp->__Vtable1_VX_cache__DOT__cache_dram_req_arb__DOT__dram_fill_arb__DOT__qual_has_request + [vlTOPp->__Vtableidx1]; + vlTOPp->VX_cache__DOT__cache_dram_req_arb__DOT__dram_fill_arb__DOT__sel_bank__DOT__genblk2__DOT__priority_encoder__DOT__i + = vlTOPp->__Vtable1_VX_cache__DOT__cache_dram_req_arb__DOT__dram_fill_arb__DOT__sel_bank__DOT__genblk2__DOT__priority_encoder__DOT__i + [vlTOPp->__Vtableidx1]; + vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__reqq_pop_unqual + = (((((((0xbU >= (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cache_miss_resrv__DOT__size)) + & (~ (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cache_miss_resrv__DOT__dequeue_possible))) + & (~ (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__dfpq_pop_unqual))) + & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__core_req_arb__DOT__qual_has_request)) + & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__core_req_arb__DOT__qual_has_request)) + & (~ vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__is_fill_st1 + [0U])) & (~ (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__is_fill_in_pipe))); + vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__reqq_pop_unqual + = (((((((0xbU >= (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__cache_miss_resrv__DOT__size)) + & (~ (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__cache_miss_resrv__DOT__dequeue_possible))) + & (~ (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__dfpq_pop_unqual))) + & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__core_req_arb__DOT__qual_has_request)) + & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__core_req_arb__DOT__qual_has_request)) + & (~ vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__is_fill_st1 + [0U])) & (~ (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__is_fill_in_pipe))); + vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__reqq_pop_unqual + = (((((((0xbU >= (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__cache_miss_resrv__DOT__size)) + & (~ (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__cache_miss_resrv__DOT__dequeue_possible))) + & (~ (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__dfpq_pop_unqual))) + & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__core_req_arb__DOT__qual_has_request)) + & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__core_req_arb__DOT__qual_has_request)) + & (~ vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__is_fill_st1 + [0U])) & (~ (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__is_fill_in_pipe))); + vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__reqq_pop_unqual + = (((((((0xbU >= (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cache_miss_resrv__DOT__size)) + & (~ (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cache_miss_resrv__DOT__dequeue_possible))) + & (~ (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__dfpq_pop_unqual))) + & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__core_req_arb__DOT__qual_has_request)) + & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__core_req_arb__DOT__qual_has_request)) + & (~ vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__is_fill_st1 + [0U])) & (~ (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__is_fill_in_pipe))); + vlTOPp->VX_cache__DOT__per_bank_snp_rsp_valid = + ((0xeU & (IData)(vlTOPp->VX_cache__DOT__per_bank_snp_rsp_valid)) + | (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__curr_bank_snp_rsp_valid)); + vlTOPp->VX_cache__DOT__per_bank_dram_wb_req_valid + = ((0xeU & (IData)(vlTOPp->VX_cache__DOT__per_bank_dram_wb_req_valid)) + | (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__curr_bank_dram_wb_req_valid)); + vlTOPp->VX_cache__DOT__per_bank_snp_rsp_valid = + ((0xdU & (IData)(vlTOPp->VX_cache__DOT__per_bank_snp_rsp_valid)) + | ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__curr_bank_snp_rsp_valid) + << 1U)); + vlTOPp->VX_cache__DOT__per_bank_dram_wb_req_valid + = ((0xdU & (IData)(vlTOPp->VX_cache__DOT__per_bank_dram_wb_req_valid)) + | ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__curr_bank_dram_wb_req_valid) + << 1U)); + vlTOPp->VX_cache__DOT__per_bank_snp_rsp_valid = + ((0xbU & (IData)(vlTOPp->VX_cache__DOT__per_bank_snp_rsp_valid)) + | ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__curr_bank_snp_rsp_valid) + << 2U)); + vlTOPp->VX_cache__DOT__per_bank_dram_wb_req_valid + = ((0xbU & (IData)(vlTOPp->VX_cache__DOT__per_bank_dram_wb_req_valid)) + | ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__curr_bank_dram_wb_req_valid) + << 2U)); + vlTOPp->VX_cache__DOT__per_bank_snp_rsp_valid = + ((7U & (IData)(vlTOPp->VX_cache__DOT__per_bank_snp_rsp_valid)) + | ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__curr_bank_snp_rsp_valid) + << 3U)); + vlTOPp->VX_cache__DOT__per_bank_dram_wb_req_valid + = ((7U & (IData)(vlTOPp->VX_cache__DOT__per_bank_dram_wb_req_valid)) + | ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__curr_bank_dram_wb_req_valid) + << 3U)); + vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cache_miss_resrv__DOT__make_ready + = ((0xfffeU & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cache_miss_resrv__DOT__make_ready)) + | (vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__is_fill_st1 + [0U] & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cache_miss_resrv__DOT__valid_address_match))); + vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cache_miss_resrv__DOT__make_ready + = ((0xfffdU & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cache_miss_resrv__DOT__make_ready)) + | (0xfffffffeU & ((vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__is_fill_st1 + [0U] << 1U) & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cache_miss_resrv__DOT__valid_address_match)))); + vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cache_miss_resrv__DOT__make_ready + = ((0xfffbU & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cache_miss_resrv__DOT__make_ready)) + | (0xfffffffcU & ((vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__is_fill_st1 + [0U] << 2U) & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cache_miss_resrv__DOT__valid_address_match)))); + vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cache_miss_resrv__DOT__make_ready + = ((0xfff7U & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cache_miss_resrv__DOT__make_ready)) + | (0xfffffff8U & ((vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__is_fill_st1 + [0U] << 3U) & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cache_miss_resrv__DOT__valid_address_match)))); + vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cache_miss_resrv__DOT__make_ready + = ((0xffefU & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cache_miss_resrv__DOT__make_ready)) + | (0xfffffff0U & ((vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__is_fill_st1 + [0U] << 4U) & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cache_miss_resrv__DOT__valid_address_match)))); + vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cache_miss_resrv__DOT__make_ready + = ((0xffdfU & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cache_miss_resrv__DOT__make_ready)) + | (0xffffffe0U & ((vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__is_fill_st1 + [0U] << 5U) & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cache_miss_resrv__DOT__valid_address_match)))); + vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cache_miss_resrv__DOT__make_ready + = ((0xffbfU & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cache_miss_resrv__DOT__make_ready)) + | (0xffffffc0U & ((vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__is_fill_st1 + [0U] << 6U) & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cache_miss_resrv__DOT__valid_address_match)))); + vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cache_miss_resrv__DOT__make_ready + = ((0xff7fU & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cache_miss_resrv__DOT__make_ready)) + | (0xffffff80U & ((vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__is_fill_st1 + [0U] << 7U) & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cache_miss_resrv__DOT__valid_address_match)))); + vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cache_miss_resrv__DOT__make_ready + = ((0xfeffU & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cache_miss_resrv__DOT__make_ready)) + | (0xffffff00U & ((vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__is_fill_st1 + [0U] << 8U) & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cache_miss_resrv__DOT__valid_address_match)))); + vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cache_miss_resrv__DOT__make_ready + = ((0xfdffU & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cache_miss_resrv__DOT__make_ready)) + | (0xfffffe00U & ((vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__is_fill_st1 + [0U] << 9U) & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cache_miss_resrv__DOT__valid_address_match)))); + vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cache_miss_resrv__DOT__make_ready + = ((0xfbffU & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cache_miss_resrv__DOT__make_ready)) + | (0xfffffc00U & ((vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__is_fill_st1 + [0U] << 0xaU) & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cache_miss_resrv__DOT__valid_address_match)))); + vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cache_miss_resrv__DOT__make_ready + = ((0xf7ffU & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cache_miss_resrv__DOT__make_ready)) + | (0xfffff800U & ((vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__is_fill_st1 + [0U] << 0xbU) & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cache_miss_resrv__DOT__valid_address_match)))); + vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cache_miss_resrv__DOT__make_ready + = ((0xefffU & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cache_miss_resrv__DOT__make_ready)) + | (0xfffff000U & ((vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__is_fill_st1 + [0U] << 0xcU) & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cache_miss_resrv__DOT__valid_address_match)))); + vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cache_miss_resrv__DOT__make_ready + = ((0xdfffU & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cache_miss_resrv__DOT__make_ready)) + | (0xffffe000U & ((vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__is_fill_st1 + [0U] << 0xdU) & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cache_miss_resrv__DOT__valid_address_match)))); + vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cache_miss_resrv__DOT__make_ready + = ((0xbfffU & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cache_miss_resrv__DOT__make_ready)) + | (0xffffc000U & ((vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__is_fill_st1 + [0U] << 0xeU) & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cache_miss_resrv__DOT__valid_address_match)))); + vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cache_miss_resrv__DOT__make_ready + = ((0x7fffU & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cache_miss_resrv__DOT__make_ready)) + | (0xffff8000U & ((vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__is_fill_st1 + [0U] << 0xfU) & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cache_miss_resrv__DOT__valid_address_match)))); + vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__tag_data_access__DOT__read_dirtyb_st1c[0U] + = (0xffffU & ((vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__tag_data_access__DOT____Vcellinp__s0_1_c0__in[5U] + << 0xcU) | (vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__tag_data_access__DOT____Vcellinp__s0_1_c0__in[4U] + >> 0x14U))); + vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__tag_data_access__DOT__read_data_st1c[0U][0U] + = vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__tag_data_access__DOT____Vcellinp__s0_1_c0__in[0U]; + vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__tag_data_access__DOT__read_data_st1c[0U][1U] + = vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__tag_data_access__DOT____Vcellinp__s0_1_c0__in[1U]; + vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__tag_data_access__DOT__read_data_st1c[0U][2U] + = vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__tag_data_access__DOT____Vcellinp__s0_1_c0__in[2U]; + vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__tag_data_access__DOT__read_data_st1c[0U][3U] + = vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__tag_data_access__DOT____Vcellinp__s0_1_c0__in[3U]; + vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__tag_data_access__DOT__read_dirty_st1c[0U] + = (1U & (vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__tag_data_access__DOT____Vcellinp__s0_1_c0__in[5U] + >> 4U)); + vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__tag_data_access__DOT__read_valid_st1c[0U] + = (1U & (vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__tag_data_access__DOT____Vcellinp__s0_1_c0__in[5U] + >> 5U)); + vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__tag_data_access__DOT__read_tag_st1c[0U] + = (0xfffffU & vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__tag_data_access__DOT____Vcellinp__s0_1_c0__in[4U]); + vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__cache_miss_resrv__DOT__make_ready + = ((0xfffeU & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__cache_miss_resrv__DOT__make_ready)) + | (vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__is_fill_st1 + [0U] & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__cache_miss_resrv__DOT__valid_address_match))); + vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__cache_miss_resrv__DOT__make_ready + = ((0xfffdU & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__cache_miss_resrv__DOT__make_ready)) + | (0xfffffffeU & ((vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__is_fill_st1 + [0U] << 1U) & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__cache_miss_resrv__DOT__valid_address_match)))); + vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__cache_miss_resrv__DOT__make_ready + = ((0xfffbU & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__cache_miss_resrv__DOT__make_ready)) + | (0xfffffffcU & ((vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__is_fill_st1 + [0U] << 2U) & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__cache_miss_resrv__DOT__valid_address_match)))); + vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__cache_miss_resrv__DOT__make_ready + = ((0xfff7U & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__cache_miss_resrv__DOT__make_ready)) + | (0xfffffff8U & ((vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__is_fill_st1 + [0U] << 3U) & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__cache_miss_resrv__DOT__valid_address_match)))); + vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__cache_miss_resrv__DOT__make_ready + = ((0xffefU & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__cache_miss_resrv__DOT__make_ready)) + | (0xfffffff0U & ((vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__is_fill_st1 + [0U] << 4U) & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__cache_miss_resrv__DOT__valid_address_match)))); + vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__cache_miss_resrv__DOT__make_ready + = ((0xffdfU & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__cache_miss_resrv__DOT__make_ready)) + | (0xffffffe0U & ((vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__is_fill_st1 + [0U] << 5U) & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__cache_miss_resrv__DOT__valid_address_match)))); + vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__cache_miss_resrv__DOT__make_ready + = ((0xffbfU & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__cache_miss_resrv__DOT__make_ready)) + | (0xffffffc0U & ((vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__is_fill_st1 + [0U] << 6U) & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__cache_miss_resrv__DOT__valid_address_match)))); + vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__cache_miss_resrv__DOT__make_ready + = ((0xff7fU & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__cache_miss_resrv__DOT__make_ready)) + | (0xffffff80U & ((vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__is_fill_st1 + [0U] << 7U) & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__cache_miss_resrv__DOT__valid_address_match)))); + vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__cache_miss_resrv__DOT__make_ready + = ((0xfeffU & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__cache_miss_resrv__DOT__make_ready)) + | (0xffffff00U & ((vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__is_fill_st1 + [0U] << 8U) & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__cache_miss_resrv__DOT__valid_address_match)))); + vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__cache_miss_resrv__DOT__make_ready + = ((0xfdffU & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__cache_miss_resrv__DOT__make_ready)) + | (0xfffffe00U & ((vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__is_fill_st1 + [0U] << 9U) & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__cache_miss_resrv__DOT__valid_address_match)))); + vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__cache_miss_resrv__DOT__make_ready + = ((0xfbffU & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__cache_miss_resrv__DOT__make_ready)) + | (0xfffffc00U & ((vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__is_fill_st1 + [0U] << 0xaU) & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__cache_miss_resrv__DOT__valid_address_match)))); + vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__cache_miss_resrv__DOT__make_ready + = ((0xf7ffU & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__cache_miss_resrv__DOT__make_ready)) + | (0xfffff800U & ((vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__is_fill_st1 + [0U] << 0xbU) & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__cache_miss_resrv__DOT__valid_address_match)))); + vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__cache_miss_resrv__DOT__make_ready + = ((0xefffU & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__cache_miss_resrv__DOT__make_ready)) + | (0xfffff000U & ((vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__is_fill_st1 + [0U] << 0xcU) & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__cache_miss_resrv__DOT__valid_address_match)))); + vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__cache_miss_resrv__DOT__make_ready + = ((0xdfffU & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__cache_miss_resrv__DOT__make_ready)) + | (0xffffe000U & ((vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__is_fill_st1 + [0U] << 0xdU) & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__cache_miss_resrv__DOT__valid_address_match)))); + vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__cache_miss_resrv__DOT__make_ready + = ((0xbfffU & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__cache_miss_resrv__DOT__make_ready)) + | (0xffffc000U & ((vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__is_fill_st1 + [0U] << 0xeU) & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__cache_miss_resrv__DOT__valid_address_match)))); + vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__cache_miss_resrv__DOT__make_ready + = ((0x7fffU & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__cache_miss_resrv__DOT__make_ready)) + | (0xffff8000U & ((vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__is_fill_st1 + [0U] << 0xfU) & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__cache_miss_resrv__DOT__valid_address_match)))); + vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__tag_data_access__DOT__read_dirtyb_st1c[0U] + = (0xffffU & ((vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__tag_data_access__DOT____Vcellinp__s0_1_c0__in[5U] + << 0xcU) | (vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__tag_data_access__DOT____Vcellinp__s0_1_c0__in[4U] + >> 0x14U))); + vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__tag_data_access__DOT__read_data_st1c[0U][0U] + = vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__tag_data_access__DOT____Vcellinp__s0_1_c0__in[0U]; + vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__tag_data_access__DOT__read_data_st1c[0U][1U] + = vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__tag_data_access__DOT____Vcellinp__s0_1_c0__in[1U]; + vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__tag_data_access__DOT__read_data_st1c[0U][2U] + = vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__tag_data_access__DOT____Vcellinp__s0_1_c0__in[2U]; + vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__tag_data_access__DOT__read_data_st1c[0U][3U] + = vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__tag_data_access__DOT____Vcellinp__s0_1_c0__in[3U]; + vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__tag_data_access__DOT__read_dirty_st1c[0U] + = (1U & (vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__tag_data_access__DOT____Vcellinp__s0_1_c0__in[5U] + >> 4U)); + vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__tag_data_access__DOT__read_valid_st1c[0U] + = (1U & (vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__tag_data_access__DOT____Vcellinp__s0_1_c0__in[5U] + >> 5U)); + vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__tag_data_access__DOT__read_tag_st1c[0U] + = (0xfffffU & vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__tag_data_access__DOT____Vcellinp__s0_1_c0__in[4U]); + vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__cache_miss_resrv__DOT__make_ready + = ((0xfffeU & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__cache_miss_resrv__DOT__make_ready)) + | (vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__is_fill_st1 + [0U] & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__cache_miss_resrv__DOT__valid_address_match))); + vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__cache_miss_resrv__DOT__make_ready + = ((0xfffdU & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__cache_miss_resrv__DOT__make_ready)) + | (0xfffffffeU & ((vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__is_fill_st1 + [0U] << 1U) & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__cache_miss_resrv__DOT__valid_address_match)))); + vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__cache_miss_resrv__DOT__make_ready + = ((0xfffbU & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__cache_miss_resrv__DOT__make_ready)) + | (0xfffffffcU & ((vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__is_fill_st1 + [0U] << 2U) & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__cache_miss_resrv__DOT__valid_address_match)))); + vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__cache_miss_resrv__DOT__make_ready + = ((0xfff7U & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__cache_miss_resrv__DOT__make_ready)) + | (0xfffffff8U & ((vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__is_fill_st1 + [0U] << 3U) & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__cache_miss_resrv__DOT__valid_address_match)))); + vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__cache_miss_resrv__DOT__make_ready + = ((0xffefU & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__cache_miss_resrv__DOT__make_ready)) + | (0xfffffff0U & ((vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__is_fill_st1 + [0U] << 4U) & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__cache_miss_resrv__DOT__valid_address_match)))); + vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__cache_miss_resrv__DOT__make_ready + = ((0xffdfU & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__cache_miss_resrv__DOT__make_ready)) + | (0xffffffe0U & ((vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__is_fill_st1 + [0U] << 5U) & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__cache_miss_resrv__DOT__valid_address_match)))); + vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__cache_miss_resrv__DOT__make_ready + = ((0xffbfU & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__cache_miss_resrv__DOT__make_ready)) + | (0xffffffc0U & ((vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__is_fill_st1 + [0U] << 6U) & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__cache_miss_resrv__DOT__valid_address_match)))); + vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__cache_miss_resrv__DOT__make_ready + = ((0xff7fU & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__cache_miss_resrv__DOT__make_ready)) + | (0xffffff80U & ((vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__is_fill_st1 + [0U] << 7U) & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__cache_miss_resrv__DOT__valid_address_match)))); + vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__cache_miss_resrv__DOT__make_ready + = ((0xfeffU & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__cache_miss_resrv__DOT__make_ready)) + | (0xffffff00U & ((vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__is_fill_st1 + [0U] << 8U) & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__cache_miss_resrv__DOT__valid_address_match)))); + vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__cache_miss_resrv__DOT__make_ready + = ((0xfdffU & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__cache_miss_resrv__DOT__make_ready)) + | (0xfffffe00U & ((vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__is_fill_st1 + [0U] << 9U) & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__cache_miss_resrv__DOT__valid_address_match)))); + vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__cache_miss_resrv__DOT__make_ready + = ((0xfbffU & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__cache_miss_resrv__DOT__make_ready)) + | (0xfffffc00U & ((vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__is_fill_st1 + [0U] << 0xaU) & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__cache_miss_resrv__DOT__valid_address_match)))); + vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__cache_miss_resrv__DOT__make_ready + = ((0xf7ffU & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__cache_miss_resrv__DOT__make_ready)) + | (0xfffff800U & ((vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__is_fill_st1 + [0U] << 0xbU) & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__cache_miss_resrv__DOT__valid_address_match)))); + vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__cache_miss_resrv__DOT__make_ready + = ((0xefffU & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__cache_miss_resrv__DOT__make_ready)) + | (0xfffff000U & ((vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__is_fill_st1 + [0U] << 0xcU) & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__cache_miss_resrv__DOT__valid_address_match)))); + vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__cache_miss_resrv__DOT__make_ready + = ((0xdfffU & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__cache_miss_resrv__DOT__make_ready)) + | (0xffffe000U & ((vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__is_fill_st1 + [0U] << 0xdU) & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__cache_miss_resrv__DOT__valid_address_match)))); + vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__cache_miss_resrv__DOT__make_ready + = ((0xbfffU & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__cache_miss_resrv__DOT__make_ready)) + | (0xffffc000U & ((vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__is_fill_st1 + [0U] << 0xeU) & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__cache_miss_resrv__DOT__valid_address_match)))); + vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__cache_miss_resrv__DOT__make_ready + = ((0x7fffU & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__cache_miss_resrv__DOT__make_ready)) + | (0xffff8000U & ((vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__is_fill_st1 + [0U] << 0xfU) & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__cache_miss_resrv__DOT__valid_address_match)))); + vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__tag_data_access__DOT__read_dirtyb_st1c[0U] + = (0xffffU & ((vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__tag_data_access__DOT____Vcellinp__s0_1_c0__in[5U] + << 0xcU) | (vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__tag_data_access__DOT____Vcellinp__s0_1_c0__in[4U] + >> 0x14U))); + vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__tag_data_access__DOT__read_data_st1c[0U][0U] + = vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__tag_data_access__DOT____Vcellinp__s0_1_c0__in[0U]; + vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__tag_data_access__DOT__read_data_st1c[0U][1U] + = vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__tag_data_access__DOT____Vcellinp__s0_1_c0__in[1U]; + vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__tag_data_access__DOT__read_data_st1c[0U][2U] + = vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__tag_data_access__DOT____Vcellinp__s0_1_c0__in[2U]; + vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__tag_data_access__DOT__read_data_st1c[0U][3U] + = vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__tag_data_access__DOT____Vcellinp__s0_1_c0__in[3U]; + vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__tag_data_access__DOT__read_dirty_st1c[0U] + = (1U & (vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__tag_data_access__DOT____Vcellinp__s0_1_c0__in[5U] + >> 4U)); + vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__tag_data_access__DOT__read_valid_st1c[0U] + = (1U & (vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__tag_data_access__DOT____Vcellinp__s0_1_c0__in[5U] + >> 5U)); + vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__tag_data_access__DOT__read_tag_st1c[0U] + = (0xfffffU & vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__tag_data_access__DOT____Vcellinp__s0_1_c0__in[4U]); + vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cache_miss_resrv__DOT__make_ready + = ((0xfffeU & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cache_miss_resrv__DOT__make_ready)) + | (vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__is_fill_st1 + [0U] & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cache_miss_resrv__DOT__valid_address_match))); + vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cache_miss_resrv__DOT__make_ready + = ((0xfffdU & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cache_miss_resrv__DOT__make_ready)) + | (0xfffffffeU & ((vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__is_fill_st1 + [0U] << 1U) & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cache_miss_resrv__DOT__valid_address_match)))); + vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cache_miss_resrv__DOT__make_ready + = ((0xfffbU & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cache_miss_resrv__DOT__make_ready)) + | (0xfffffffcU & ((vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__is_fill_st1 + [0U] << 2U) & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cache_miss_resrv__DOT__valid_address_match)))); + vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cache_miss_resrv__DOT__make_ready + = ((0xfff7U & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cache_miss_resrv__DOT__make_ready)) + | (0xfffffff8U & ((vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__is_fill_st1 + [0U] << 3U) & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cache_miss_resrv__DOT__valid_address_match)))); + vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cache_miss_resrv__DOT__make_ready + = ((0xffefU & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cache_miss_resrv__DOT__make_ready)) + | (0xfffffff0U & ((vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__is_fill_st1 + [0U] << 4U) & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cache_miss_resrv__DOT__valid_address_match)))); + vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cache_miss_resrv__DOT__make_ready + = ((0xffdfU & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cache_miss_resrv__DOT__make_ready)) + | (0xffffffe0U & ((vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__is_fill_st1 + [0U] << 5U) & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cache_miss_resrv__DOT__valid_address_match)))); + vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cache_miss_resrv__DOT__make_ready + = ((0xffbfU & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cache_miss_resrv__DOT__make_ready)) + | (0xffffffc0U & ((vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__is_fill_st1 + [0U] << 6U) & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cache_miss_resrv__DOT__valid_address_match)))); + vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cache_miss_resrv__DOT__make_ready + = ((0xff7fU & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cache_miss_resrv__DOT__make_ready)) + | (0xffffff80U & ((vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__is_fill_st1 + [0U] << 7U) & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cache_miss_resrv__DOT__valid_address_match)))); + vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cache_miss_resrv__DOT__make_ready + = ((0xfeffU & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cache_miss_resrv__DOT__make_ready)) + | (0xffffff00U & ((vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__is_fill_st1 + [0U] << 8U) & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cache_miss_resrv__DOT__valid_address_match)))); + vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cache_miss_resrv__DOT__make_ready + = ((0xfdffU & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cache_miss_resrv__DOT__make_ready)) + | (0xfffffe00U & ((vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__is_fill_st1 + [0U] << 9U) & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cache_miss_resrv__DOT__valid_address_match)))); + vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cache_miss_resrv__DOT__make_ready + = ((0xfbffU & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cache_miss_resrv__DOT__make_ready)) + | (0xfffffc00U & ((vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__is_fill_st1 + [0U] << 0xaU) & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cache_miss_resrv__DOT__valid_address_match)))); + vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cache_miss_resrv__DOT__make_ready + = ((0xf7ffU & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cache_miss_resrv__DOT__make_ready)) + | (0xfffff800U & ((vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__is_fill_st1 + [0U] << 0xbU) & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cache_miss_resrv__DOT__valid_address_match)))); + vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cache_miss_resrv__DOT__make_ready + = ((0xefffU & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cache_miss_resrv__DOT__make_ready)) + | (0xfffff000U & ((vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__is_fill_st1 + [0U] << 0xcU) & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cache_miss_resrv__DOT__valid_address_match)))); + vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cache_miss_resrv__DOT__make_ready + = ((0xdfffU & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cache_miss_resrv__DOT__make_ready)) + | (0xffffe000U & ((vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__is_fill_st1 + [0U] << 0xdU) & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cache_miss_resrv__DOT__valid_address_match)))); + vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cache_miss_resrv__DOT__make_ready + = ((0xbfffU & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cache_miss_resrv__DOT__make_ready)) + | (0xffffc000U & ((vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__is_fill_st1 + [0U] << 0xeU) & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cache_miss_resrv__DOT__valid_address_match)))); + vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cache_miss_resrv__DOT__make_ready + = ((0x7fffU & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cache_miss_resrv__DOT__make_ready)) + | (0xffff8000U & ((vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__is_fill_st1 + [0U] << 0xfU) & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cache_miss_resrv__DOT__valid_address_match)))); + vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__tag_data_access__DOT__read_dirtyb_st1c[0U] + = (0xffffU & ((vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__tag_data_access__DOT____Vcellinp__s0_1_c0__in[5U] + << 0xcU) | (vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__tag_data_access__DOT____Vcellinp__s0_1_c0__in[4U] + >> 0x14U))); + vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__tag_data_access__DOT__read_data_st1c[0U][0U] + = vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__tag_data_access__DOT____Vcellinp__s0_1_c0__in[0U]; + vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__tag_data_access__DOT__read_data_st1c[0U][1U] + = vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__tag_data_access__DOT____Vcellinp__s0_1_c0__in[1U]; + vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__tag_data_access__DOT__read_data_st1c[0U][2U] + = vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__tag_data_access__DOT____Vcellinp__s0_1_c0__in[2U]; + vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__tag_data_access__DOT__read_data_st1c[0U][3U] + = vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__tag_data_access__DOT____Vcellinp__s0_1_c0__in[3U]; + vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__tag_data_access__DOT__read_dirty_st1c[0U] + = (1U & (vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__tag_data_access__DOT____Vcellinp__s0_1_c0__in[5U] + >> 4U)); + vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__tag_data_access__DOT__read_valid_st1c[0U] + = (1U & (vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__tag_data_access__DOT____Vcellinp__s0_1_c0__in[5U] + >> 5U)); + vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__tag_data_access__DOT__read_tag_st1c[0U] + = (0xfffffU & vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__tag_data_access__DOT____Vcellinp__s0_1_c0__in[4U]); + vlTOPp->VX_cache__DOT__cache_core_rsp_merge__DOT__sel_bank__DOT__genblk2__DOT__update_value + = (((IData)(vlTOPp->VX_cache__DOT__cache_core_rsp_merge__DOT__sel_bank__DOT__genblk2__DOT__requests_use) + & (~ (IData)(vlTOPp->VX_cache__DOT__cache_core_rsp_merge__DOT__sel_bank__DOT__genblk2__DOT__grant_onehot_r))) + | (((IData)(vlTOPp->VX_cache__DOT__cache_core_rsp_merge__DOT__sel_bank__DOT__genblk2__DOT__refill_original) + ^ (IData)(vlTOPp->VX_cache__DOT__per_bank_core_rsp_valid)) + & (~ (IData)(vlTOPp->VX_cache__DOT__cache_core_rsp_merge__DOT__sel_bank__DOT__genblk2__DOT__refill_original)))); + vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__dwbq_push_stall + = ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__dwbq_push_unqual) + & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__genblk2__DOT__full_r)); + vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__dwbq_push_stall + = ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__dwbq_push_unqual) + & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__genblk2__DOT__full_r)); + vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__dwbq_push_stall + = ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__dwbq_push_unqual) + & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__genblk2__DOT__full_r)); + vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__dwbq_push_stall + = ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__dwbq_push_unqual) + & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__genblk2__DOT__full_r)); + vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__mrvq_init_ready_state_st2 + = (1U & (((vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__st_1e_2__DOT__value[9U] + >> 0x19U) | (((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__miss_add_unqual) + & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__dfpq_pop_unqual)) + & ((0x3ffffffU & (( + vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__st_1e_2__DOT__value[9U] + << 7U) + | (vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__st_1e_2__DOT__value[8U] + >> 0x19U))) + == (0x3ffffffU & + vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT____Vcellout__dfp_queue__data_out[4U])))) + | (((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__miss_add_unqual) + & vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__is_fill_st1 + [0U]) & ((0x3ffffffU & ((vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__st_1e_2__DOT__value[9U] + << 7U) + | (vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__st_1e_2__DOT__value[8U] + >> 0x19U))) + == vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__addr_st1 + [0U])))); + vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__dram_fill_req_stall + = ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__miss_add_unqual) + & (IData)(vlTOPp->VX_cache__DOT__cache_dram_req_arb__DOT__dram_fill_arb__DOT__dfqq_queue__DOT__genblk3__DOT__genblk2__DOT__full_r)); + vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__mrvq_push_stall + = ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__miss_add_unqual) + & (0x10U == (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cache_miss_resrv__DOT__size))); + vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__recover_mrvq_state_st2 + = ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__miss_add_unqual) + & (vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__st_1e_2__DOT__value[9U] + >> 0x1aU)); + vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__mrvq_init_ready_state_st2 + = (1U & (((vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__st_1e_2__DOT__value[9U] + >> 0x19U) | (((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__miss_add_unqual) + & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__dfpq_pop_unqual)) + & ((0x3ffffffU & (( + vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__st_1e_2__DOT__value[9U] + << 7U) + | (vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__st_1e_2__DOT__value[8U] + >> 0x19U))) + == (0x3ffffffU & + vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT____Vcellout__dfp_queue__data_out[4U])))) + | (((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__miss_add_unqual) + & vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__is_fill_st1 + [0U]) & ((0x3ffffffU & ((vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__st_1e_2__DOT__value[9U] + << 7U) + | (vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__st_1e_2__DOT__value[8U] + >> 0x19U))) + == vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__addr_st1 + [0U])))); + vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__dram_fill_req_stall + = ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__miss_add_unqual) + & (IData)(vlTOPp->VX_cache__DOT__cache_dram_req_arb__DOT__dram_fill_arb__DOT__dfqq_queue__DOT__genblk3__DOT__genblk2__DOT__full_r)); + vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__mrvq_push_stall + = ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__miss_add_unqual) + & (0x10U == (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__cache_miss_resrv__DOT__size))); + vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__recover_mrvq_state_st2 + = ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__miss_add_unqual) + & (vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__st_1e_2__DOT__value[9U] + >> 0x1aU)); + vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__mrvq_init_ready_state_st2 + = (1U & (((vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__st_1e_2__DOT__value[9U] + >> 0x19U) | (((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__miss_add_unqual) + & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__dfpq_pop_unqual)) + & ((0x3ffffffU & (( + vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__st_1e_2__DOT__value[9U] + << 7U) + | (vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__st_1e_2__DOT__value[8U] + >> 0x19U))) + == (0x3ffffffU & + vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT____Vcellout__dfp_queue__data_out[4U])))) + | (((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__miss_add_unqual) + & vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__is_fill_st1 + [0U]) & ((0x3ffffffU & ((vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__st_1e_2__DOT__value[9U] + << 7U) + | (vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__st_1e_2__DOT__value[8U] + >> 0x19U))) + == vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__addr_st1 + [0U])))); + vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__dram_fill_req_stall + = ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__miss_add_unqual) + & (IData)(vlTOPp->VX_cache__DOT__cache_dram_req_arb__DOT__dram_fill_arb__DOT__dfqq_queue__DOT__genblk3__DOT__genblk2__DOT__full_r)); + vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__mrvq_push_stall + = ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__miss_add_unqual) + & (0x10U == (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__cache_miss_resrv__DOT__size))); + vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__recover_mrvq_state_st2 + = ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__miss_add_unqual) + & (vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__st_1e_2__DOT__value[9U] + >> 0x1aU)); + vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__mrvq_init_ready_state_st2 + = (1U & (((vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__st_1e_2__DOT__value[9U] + >> 0x19U) | (((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__miss_add_unqual) + & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__dfpq_pop_unqual)) + & ((0x3ffffffU & (( + vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__st_1e_2__DOT__value[9U] + << 7U) + | (vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__st_1e_2__DOT__value[8U] + >> 0x19U))) + == (0x3ffffffU & + vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT____Vcellout__dfp_queue__data_out[4U])))) + | (((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__miss_add_unqual) + & vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__is_fill_st1 + [0U]) & ((0x3ffffffU & ((vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__st_1e_2__DOT__value[9U] + << 7U) + | (vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__st_1e_2__DOT__value[8U] + >> 0x19U))) + == vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__addr_st1 + [0U])))); + vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__dram_fill_req_stall + = ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__miss_add_unqual) + & (IData)(vlTOPp->VX_cache__DOT__cache_dram_req_arb__DOT__dram_fill_arb__DOT__dfqq_queue__DOT__genblk3__DOT__genblk2__DOT__full_r)); + vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__mrvq_push_stall + = ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__miss_add_unqual) + & (0x10U == (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cache_miss_resrv__DOT__size))); + vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__recover_mrvq_state_st2 + = ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__miss_add_unqual) + & (vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__st_1e_2__DOT__value[9U] + >> 0x1aU)); + vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__reading + = ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__core_req_arb__DOT__pop_qual) + & (~ (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__empty_r))); + vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__reading + = ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__core_req_arb__DOT__pop_qual) + & (~ (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__empty_r))); + vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__reading + = ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__core_req_arb__DOT__pop_qual) + & (~ (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__empty_r))); + vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__reading + = ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__core_req_arb__DOT__pop_qual) + & (~ (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__empty_r))); + vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__writing + = ((((0U != (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__curr_bank_core_req_valid)) + & (~ (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__full_r))) + & (~ (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__full_r))) + & (~ (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__full_r))); + vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__core_req_arb__DOT____Vcellinp__reqq_queue__data_in[0U] + = (IData)(vlTOPp->core_req_tag); + vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__core_req_arb__DOT____Vcellinp__reqq_queue__data_in[1U] + = ((0xfffffc00U & (vlTOPp->core_req_data[0U] + << 0xaU)) | (IData)((vlTOPp->core_req_tag + >> 0x20U))); + vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__core_req_arb__DOT____Vcellinp__reqq_queue__data_in[2U] + = ((0x3ffU & (vlTOPp->core_req_data[0U] >> 0x16U)) + | (0xfffffc00U & (vlTOPp->core_req_data[1U] + << 0xaU))); + vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__core_req_arb__DOT____Vcellinp__reqq_queue__data_in[3U] + = ((0x3ffU & (vlTOPp->core_req_data[1U] >> 0x16U)) + | (0xfffffc00U & (vlTOPp->core_req_data[2U] + << 0xaU))); + vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__core_req_arb__DOT____Vcellinp__reqq_queue__data_in[4U] + = ((0x3ffU & (vlTOPp->core_req_data[2U] >> 0x16U)) + | (0xfffffc00U & (vlTOPp->core_req_data[3U] + << 0xaU))); + vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__core_req_arb__DOT____Vcellinp__reqq_queue__data_in[5U] + = ((0xfffffc00U & (vlTOPp->core_req_addr[0U] + << 0xaU)) | (0x3ffU & (vlTOPp->core_req_data[3U] + >> 0x16U))); + vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__core_req_arb__DOT____Vcellinp__reqq_queue__data_in[6U] + = ((0x3ffU & (vlTOPp->core_req_addr[0U] >> 0x16U)) + | (0xfffffc00U & (vlTOPp->core_req_addr[1U] + << 0xaU))); + vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__core_req_arb__DOT____Vcellinp__reqq_queue__data_in[7U] + = ((0x3ffU & (vlTOPp->core_req_addr[1U] >> 0x16U)) + | (0xfffffc00U & (vlTOPp->core_req_addr[2U] + << 0xaU))); + vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__core_req_arb__DOT____Vcellinp__reqq_queue__data_in[8U] + = ((0x3ffU & (vlTOPp->core_req_addr[2U] >> 0x16U)) + | (0xfffffc00U & (vlTOPp->core_req_addr[3U] + << 0xaU))); + vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__core_req_arb__DOT____Vcellinp__reqq_queue__data_in[9U] + = ((0xffc00000U & ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__curr_bank_core_req_valid) + << 0x16U)) | ((0xfffc0000U + & ((IData)(vlTOPp->core_req_rw) + << 0x12U)) + | ((0xfffffffcU + & ((IData)(vlTOPp->core_req_byteen) + << 2U)) + | (0x3ffU + & (vlTOPp->core_req_addr[3U] + >> 0x16U))))); + vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__writing + = ((((0U != (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__curr_bank_core_req_valid)) + & (~ (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__full_r))) + & (~ (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__full_r))) + & (~ (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__full_r))); + vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__core_req_arb__DOT____Vcellinp__reqq_queue__data_in[0U] + = (IData)(vlTOPp->core_req_tag); + vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__core_req_arb__DOT____Vcellinp__reqq_queue__data_in[1U] + = ((0xfffffc00U & (vlTOPp->core_req_data[0U] + << 0xaU)) | (IData)((vlTOPp->core_req_tag + >> 0x20U))); + vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__core_req_arb__DOT____Vcellinp__reqq_queue__data_in[2U] + = ((0x3ffU & (vlTOPp->core_req_data[0U] >> 0x16U)) + | (0xfffffc00U & (vlTOPp->core_req_data[1U] + << 0xaU))); + vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__core_req_arb__DOT____Vcellinp__reqq_queue__data_in[3U] + = ((0x3ffU & (vlTOPp->core_req_data[1U] >> 0x16U)) + | (0xfffffc00U & (vlTOPp->core_req_data[2U] + << 0xaU))); + vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__core_req_arb__DOT____Vcellinp__reqq_queue__data_in[4U] + = ((0x3ffU & (vlTOPp->core_req_data[2U] >> 0x16U)) + | (0xfffffc00U & (vlTOPp->core_req_data[3U] + << 0xaU))); + vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__core_req_arb__DOT____Vcellinp__reqq_queue__data_in[5U] + = ((0xfffffc00U & (vlTOPp->core_req_addr[0U] + << 0xaU)) | (0x3ffU & (vlTOPp->core_req_data[3U] + >> 0x16U))); + vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__core_req_arb__DOT____Vcellinp__reqq_queue__data_in[6U] + = ((0x3ffU & (vlTOPp->core_req_addr[0U] >> 0x16U)) + | (0xfffffc00U & (vlTOPp->core_req_addr[1U] + << 0xaU))); + vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__core_req_arb__DOT____Vcellinp__reqq_queue__data_in[7U] + = ((0x3ffU & (vlTOPp->core_req_addr[1U] >> 0x16U)) + | (0xfffffc00U & (vlTOPp->core_req_addr[2U] + << 0xaU))); + vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__core_req_arb__DOT____Vcellinp__reqq_queue__data_in[8U] + = ((0x3ffU & (vlTOPp->core_req_addr[2U] >> 0x16U)) + | (0xfffffc00U & (vlTOPp->core_req_addr[3U] + << 0xaU))); + vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__core_req_arb__DOT____Vcellinp__reqq_queue__data_in[9U] + = ((0xffc00000U & ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__curr_bank_core_req_valid) + << 0x16U)) | ((0xfffc0000U + & ((IData)(vlTOPp->core_req_rw) + << 0x12U)) + | ((0xfffffffcU + & ((IData)(vlTOPp->core_req_byteen) + << 2U)) + | (0x3ffU + & (vlTOPp->core_req_addr[3U] + >> 0x16U))))); + vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__writing + = ((((0U != (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__curr_bank_core_req_valid)) + & (~ (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__full_r))) + & (~ (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__full_r))) + & (~ (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__full_r))); + vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__core_req_arb__DOT____Vcellinp__reqq_queue__data_in[0U] + = (IData)(vlTOPp->core_req_tag); + vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__core_req_arb__DOT____Vcellinp__reqq_queue__data_in[1U] + = ((0xfffffc00U & (vlTOPp->core_req_data[0U] + << 0xaU)) | (IData)((vlTOPp->core_req_tag + >> 0x20U))); + vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__core_req_arb__DOT____Vcellinp__reqq_queue__data_in[2U] + = ((0x3ffU & (vlTOPp->core_req_data[0U] >> 0x16U)) + | (0xfffffc00U & (vlTOPp->core_req_data[1U] + << 0xaU))); + vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__core_req_arb__DOT____Vcellinp__reqq_queue__data_in[3U] + = ((0x3ffU & (vlTOPp->core_req_data[1U] >> 0x16U)) + | (0xfffffc00U & (vlTOPp->core_req_data[2U] + << 0xaU))); + vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__core_req_arb__DOT____Vcellinp__reqq_queue__data_in[4U] + = ((0x3ffU & (vlTOPp->core_req_data[2U] >> 0x16U)) + | (0xfffffc00U & (vlTOPp->core_req_data[3U] + << 0xaU))); + vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__core_req_arb__DOT____Vcellinp__reqq_queue__data_in[5U] + = ((0xfffffc00U & (vlTOPp->core_req_addr[0U] + << 0xaU)) | (0x3ffU & (vlTOPp->core_req_data[3U] + >> 0x16U))); + vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__core_req_arb__DOT____Vcellinp__reqq_queue__data_in[6U] + = ((0x3ffU & (vlTOPp->core_req_addr[0U] >> 0x16U)) + | (0xfffffc00U & (vlTOPp->core_req_addr[1U] + << 0xaU))); + vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__core_req_arb__DOT____Vcellinp__reqq_queue__data_in[7U] + = ((0x3ffU & (vlTOPp->core_req_addr[1U] >> 0x16U)) + | (0xfffffc00U & (vlTOPp->core_req_addr[2U] + << 0xaU))); + vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__core_req_arb__DOT____Vcellinp__reqq_queue__data_in[8U] + = ((0x3ffU & (vlTOPp->core_req_addr[2U] >> 0x16U)) + | (0xfffffc00U & (vlTOPp->core_req_addr[3U] + << 0xaU))); + vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__core_req_arb__DOT____Vcellinp__reqq_queue__data_in[9U] + = ((0xffc00000U & ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__curr_bank_core_req_valid) + << 0x16U)) | ((0xfffc0000U + & ((IData)(vlTOPp->core_req_rw) + << 0x12U)) + | ((0xfffffffcU + & ((IData)(vlTOPp->core_req_byteen) + << 2U)) + | (0x3ffU + & (vlTOPp->core_req_addr[3U] + >> 0x16U))))); + vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__writing + = ((((0U != (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__curr_bank_core_req_valid)) + & (~ (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__full_r))) + & (~ (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__full_r))) + & (~ (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__full_r))); + vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__core_req_arb__DOT____Vcellinp__reqq_queue__data_in[0U] + = (IData)(vlTOPp->core_req_tag); + vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__core_req_arb__DOT____Vcellinp__reqq_queue__data_in[1U] + = ((0xfffffc00U & (vlTOPp->core_req_data[0U] + << 0xaU)) | (IData)((vlTOPp->core_req_tag + >> 0x20U))); + vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__core_req_arb__DOT____Vcellinp__reqq_queue__data_in[2U] + = ((0x3ffU & (vlTOPp->core_req_data[0U] >> 0x16U)) + | (0xfffffc00U & (vlTOPp->core_req_data[1U] + << 0xaU))); + vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__core_req_arb__DOT____Vcellinp__reqq_queue__data_in[3U] + = ((0x3ffU & (vlTOPp->core_req_data[1U] >> 0x16U)) + | (0xfffffc00U & (vlTOPp->core_req_data[2U] + << 0xaU))); + vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__core_req_arb__DOT____Vcellinp__reqq_queue__data_in[4U] + = ((0x3ffU & (vlTOPp->core_req_data[2U] >> 0x16U)) + | (0xfffffc00U & (vlTOPp->core_req_data[3U] + << 0xaU))); + vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__core_req_arb__DOT____Vcellinp__reqq_queue__data_in[5U] + = ((0xfffffc00U & (vlTOPp->core_req_addr[0U] + << 0xaU)) | (0x3ffU & (vlTOPp->core_req_data[3U] + >> 0x16U))); + vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__core_req_arb__DOT____Vcellinp__reqq_queue__data_in[6U] + = ((0x3ffU & (vlTOPp->core_req_addr[0U] >> 0x16U)) + | (0xfffffc00U & (vlTOPp->core_req_addr[1U] + << 0xaU))); + vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__core_req_arb__DOT____Vcellinp__reqq_queue__data_in[7U] + = ((0x3ffU & (vlTOPp->core_req_addr[1U] >> 0x16U)) + | (0xfffffc00U & (vlTOPp->core_req_addr[2U] + << 0xaU))); + vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__core_req_arb__DOT____Vcellinp__reqq_queue__data_in[8U] + = ((0x3ffU & (vlTOPp->core_req_addr[2U] >> 0x16U)) + | (0xfffffc00U & (vlTOPp->core_req_addr[3U] + << 0xaU))); + vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__core_req_arb__DOT____Vcellinp__reqq_queue__data_in[9U] + = ((0xffc00000U & ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__curr_bank_core_req_valid) + << 0x16U)) | ((0xfffc0000U + & ((IData)(vlTOPp->core_req_rw) + << 0x12U)) + | ((0xfffffffcU + & ((IData)(vlTOPp->core_req_byteen) + << 2U)) + | (0x3ffU + & (vlTOPp->core_req_addr[3U] + >> 0x16U))))); + vlTOPp->core_rsp_data[0U] = vlTOPp->VX_cache__DOT____Vcellout__cache_core_rsp_merge__core_rsp_data[0U]; + vlTOPp->core_rsp_data[1U] = vlTOPp->VX_cache__DOT____Vcellout__cache_core_rsp_merge__core_rsp_data[1U]; + vlTOPp->core_rsp_data[2U] = vlTOPp->VX_cache__DOT____Vcellout__cache_core_rsp_merge__core_rsp_data[2U]; + vlTOPp->core_rsp_data[3U] = vlTOPp->VX_cache__DOT____Vcellout__cache_core_rsp_merge__core_rsp_data[3U]; + vlTOPp->VX_cache__DOT__per_bank_core_rsp_ready + = ((IData)(vlTOPp->VX_cache__DOT__cache_core_rsp_merge__DOT__per_bank_core_rsp_pop_unqual) + & VL_NEGATE_I((IData)((IData)(vlTOPp->core_rsp_ready)))); + vlTOPp->VX_cache__DOT__cache_dram_req_arb__DOT__dram_fill_arb__DOT__sel_bank__DOT__genblk2__DOT__grant_onehot_r = 0U; + vlTOPp->VX_cache__DOT__cache_dram_req_arb__DOT__dram_fill_arb__DOT__sel_bank__DOT__genblk2__DOT__grant_onehot_r + = ((IData)(vlTOPp->VX_cache__DOT__cache_dram_req_arb__DOT__dram_fill_arb__DOT__sel_bank__DOT__genblk2__DOT__grant_onehot_r) + | ((IData)(1U) << (IData)(vlTOPp->VX_cache__DOT__cache_dram_req_arb__DOT__dram_fill_arb__DOT__qual_request_index))); + vlTOPp->VX_cache__DOT__cache_dram_req_arb__DOT__dfqq_req + = (1U & ((IData)(vlTOPp->VX_cache__DOT__cache_dram_req_arb__DOT__dram_fill_arb__DOT__use_per_bqual_bank_dram_fill_req_valid) + >> (IData)(vlTOPp->VX_cache__DOT__cache_dram_req_arb__DOT__dram_fill_arb__DOT__qual_request_index))); + vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__snrq_pop_unqual + = (((((((0xbU >= (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cache_miss_resrv__DOT__size)) + & (~ (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__reqq_pop_unqual))) + & (~ (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__reqq_pop_unqual))) + & (~ (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cache_miss_resrv__DOT__dequeue_possible))) + & (~ (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__dfpq_pop_unqual))) + & (~ (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__snp_req_queue__DOT__genblk3__DOT__genblk2__DOT__empty_r))) + & (~ (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__core_req_arb__DOT__qual_has_request))); + vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__snrq_pop_unqual + = (((((((0xbU >= (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__cache_miss_resrv__DOT__size)) + & (~ (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__reqq_pop_unqual))) + & (~ (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__reqq_pop_unqual))) + & (~ (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__cache_miss_resrv__DOT__dequeue_possible))) + & (~ (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__dfpq_pop_unqual))) + & (~ (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__snp_req_queue__DOT__genblk3__DOT__genblk2__DOT__empty_r))) + & (~ (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__core_req_arb__DOT__qual_has_request))); + vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__snrq_pop_unqual + = (((((((0xbU >= (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__cache_miss_resrv__DOT__size)) + & (~ (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__reqq_pop_unqual))) + & (~ (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__reqq_pop_unqual))) + & (~ (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__cache_miss_resrv__DOT__dequeue_possible))) + & (~ (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__dfpq_pop_unqual))) + & (~ (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__snp_req_queue__DOT__genblk3__DOT__genblk2__DOT__empty_r))) + & (~ (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__core_req_arb__DOT__qual_has_request))); + vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__snrq_pop_unqual + = (((((((0xbU >= (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cache_miss_resrv__DOT__size)) + & (~ (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__reqq_pop_unqual))) + & (~ (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__reqq_pop_unqual))) + & (~ (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cache_miss_resrv__DOT__dequeue_possible))) + & (~ (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__dfpq_pop_unqual))) + & (~ (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__snp_req_queue__DOT__genblk3__DOT__genblk2__DOT__empty_r))) + & (~ (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__core_req_arb__DOT__qual_has_request))); + vlTOPp->__Vtableidx4 = vlTOPp->VX_cache__DOT__per_bank_snp_rsp_valid; + vlTOPp->VX_cache__DOT__snp_rsp_arb__DOT__fsq_bank + = vlTOPp->__Vtable4_VX_cache__DOT__snp_rsp_arb__DOT__fsq_bank + [vlTOPp->__Vtableidx4]; + vlTOPp->VX_cache__DOT__snp_rsp_arb__DOT__fsq_valid + = vlTOPp->__Vtable4_VX_cache__DOT__snp_rsp_arb__DOT__fsq_valid + [vlTOPp->__Vtableidx4]; + vlTOPp->VX_cache__DOT__snp_rsp_arb__DOT__sel_ffsq__DOT__genblk2__DOT__priority_encoder__DOT__i + = vlTOPp->__Vtable4_VX_cache__DOT__snp_rsp_arb__DOT__sel_ffsq__DOT__genblk2__DOT__priority_encoder__DOT__i + [vlTOPp->__Vtableidx4]; + vlTOPp->__Vtableidx2 = vlTOPp->VX_cache__DOT__per_bank_dram_wb_req_valid; + vlTOPp->VX_cache__DOT__cache_dram_req_arb__DOT__dwb_bank + = vlTOPp->__Vtable2_VX_cache__DOT__cache_dram_req_arb__DOT__dwb_bank + [vlTOPp->__Vtableidx2]; + vlTOPp->VX_cache__DOT__cache_dram_req_arb__DOT__dwb_valid + = vlTOPp->__Vtable2_VX_cache__DOT__cache_dram_req_arb__DOT__dwb_valid + [vlTOPp->__Vtableidx2]; + vlTOPp->VX_cache__DOT__cache_dram_req_arb__DOT__sel_dwb__DOT__genblk2__DOT__priority_encoder__DOT__i + = vlTOPp->__Vtable2_VX_cache__DOT__cache_dram_req_arb__DOT__sel_dwb__DOT__genblk2__DOT__priority_encoder__DOT__i + [vlTOPp->__Vtableidx2]; + vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__dirty_st1e + = ((vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__valid_st1 + [0U] & vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__tag_data_access__DOT__read_valid_st1c + [0U]) & vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__tag_data_access__DOT__read_dirty_st1c + [0U]); + vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__tag_data_access__DOT__tags_match + = ((0xfffffU & (vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__addr_st1 + [0U] >> 6U)) == vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__tag_data_access__DOT__read_tag_st1c + [0U]); + vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__dirty_st1e + = ((vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__valid_st1 + [0U] & vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__tag_data_access__DOT__read_valid_st1c + [0U]) & vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__tag_data_access__DOT__read_dirty_st1c + [0U]); + vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__tag_data_access__DOT__tags_match + = ((0xfffffU & (vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__addr_st1 + [0U] >> 6U)) == vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__tag_data_access__DOT__read_tag_st1c + [0U]); + vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__dirty_st1e + = ((vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__valid_st1 + [0U] & vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__tag_data_access__DOT__read_valid_st1c + [0U]) & vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__tag_data_access__DOT__read_dirty_st1c + [0U]); + vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__tag_data_access__DOT__tags_match + = ((0xfffffU & (vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__addr_st1 + [0U] >> 6U)) == vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__tag_data_access__DOT__read_tag_st1c + [0U]); + vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__dirty_st1e + = ((vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__valid_st1 + [0U] & vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__tag_data_access__DOT__read_valid_st1c + [0U]) & vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__tag_data_access__DOT__read_dirty_st1c + [0U]); + vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__tag_data_access__DOT__tags_match + = ((0xfffffU & (vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__addr_st1 + [0U] >> 6U)) == vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__tag_data_access__DOT__read_tag_st1c + [0U]); + vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__miss_add + = (((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__miss_add_unqual) + & (0x10U != (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cache_miss_resrv__DOT__size))) + & (~ (((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cwbq_push_stall) + | (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__dwbq_push_stall)) + | (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__dram_fill_req_stall)))); + vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__dwb_queue__DOT__writing + = ((((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__dwbq_push_unqual) + & (~ (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__genblk2__DOT__full_r))) + & (~ (((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cwbq_push_stall) + | (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__mrvq_push_stall)) + | (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__dram_fill_req_stall)))) + & (~ (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__genblk2__DOT__full_r))); + vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cwb_queue__DOT__writing + = (((((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cwbq_push_unqual) + & (~ (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cwb_queue__DOT__genblk3__DOT__genblk2__DOT__full_r))) + & (~ (vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__st_1e_2__DOT__value[0U] + >> 6U))) & (~ (((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__dwbq_push_stall) + | (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__mrvq_push_stall)) + | (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__dram_fill_req_stall)))) + & (~ (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cwb_queue__DOT__genblk3__DOT__genblk2__DOT__full_r))); + vlTOPp->VX_cache__DOT__per_bank_dram_fill_req_valid + = ((0xeU & (IData)(vlTOPp->VX_cache__DOT__per_bank_dram_fill_req_valid)) + | (((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__miss_add_unqual) + & ((~ (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__mrvq_init_ready_state_st2)) + | ((vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__st_1e_2__DOT__value[9U] + >> 0x1aU) & (~ (vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__st_1e_2__DOT__value[9U] + >> 0x1bU))))) + & (~ (((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__dwbq_push_stall) + | (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__mrvq_push_stall)) + | (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cwbq_push_stall))))); + vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__stall_bank_pipe + = ((((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cwbq_push_stall) + | (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__dwbq_push_stall)) + | (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__mrvq_push_stall)) + | (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__dram_fill_req_stall)); + vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__force_request_miss_st1e + = (((vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__valid_st1 + [0U] & (~ vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__is_mrvq_st1 + [0U])) & ((0U != (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cache_miss_resrv__DOT__valid_address_match)) + | ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__miss_add_because_miss) + & (((0x3ffffffU & + ((vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__st_1e_2__DOT__value[9U] + << 7U) | ( + vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__st_1e_2__DOT__value[8U] + >> 0x19U))) + == vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__addr_st1 + [0U]) & (~ (vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__st_1e_2__DOT__value[9U] + >> 0x14U)))))) + | ((vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__valid_st1 + [0U] & vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__is_mrvq_st1 + [0U]) & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__recover_mrvq_state_st2))); + vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__miss_add + = (((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__miss_add_unqual) + & (0x10U != (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__cache_miss_resrv__DOT__size))) + & (~ (((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__cwbq_push_stall) + | (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__dwbq_push_stall)) + | (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__dram_fill_req_stall)))); + vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__dwb_queue__DOT__writing + = ((((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__dwbq_push_unqual) + & (~ (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__genblk2__DOT__full_r))) + & (~ (((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__cwbq_push_stall) + | (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__mrvq_push_stall)) + | (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__dram_fill_req_stall)))) + & (~ (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__genblk2__DOT__full_r))); + vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__cwb_queue__DOT__writing + = (((((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__cwbq_push_unqual) + & (~ (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__cwb_queue__DOT__genblk3__DOT__genblk2__DOT__full_r))) + & (~ (vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__st_1e_2__DOT__value[0U] + >> 6U))) & (~ (((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__dwbq_push_stall) + | (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__mrvq_push_stall)) + | (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__dram_fill_req_stall)))) + & (~ (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__cwb_queue__DOT__genblk3__DOT__genblk2__DOT__full_r))); + vlTOPp->VX_cache__DOT__per_bank_dram_fill_req_valid + = ((0xdU & (IData)(vlTOPp->VX_cache__DOT__per_bank_dram_fill_req_valid)) + | ((((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__miss_add_unqual) + << 1U) & (((~ (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__mrvq_init_ready_state_st2)) + << 1U) | (0x7eU & ((vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__st_1e_2__DOT__value[9U] + >> 0x19U) + & ((~ + (vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__st_1e_2__DOT__value[9U] + >> 0x1bU)) + << 1U))))) + & ((~ (((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__dwbq_push_stall) + | (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__mrvq_push_stall)) + | (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__cwbq_push_stall))) + << 1U))); + vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__stall_bank_pipe + = ((((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__cwbq_push_stall) + | (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__dwbq_push_stall)) + | (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__mrvq_push_stall)) + | (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__dram_fill_req_stall)); + vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__force_request_miss_st1e + = (((vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__valid_st1 + [0U] & (~ vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__is_mrvq_st1 + [0U])) & ((0U != (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__cache_miss_resrv__DOT__valid_address_match)) + | ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__miss_add_because_miss) + & (((0x3ffffffU & + ((vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__st_1e_2__DOT__value[9U] + << 7U) | ( + vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__st_1e_2__DOT__value[8U] + >> 0x19U))) + == vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__addr_st1 + [0U]) & (~ (vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__st_1e_2__DOT__value[9U] + >> 0x14U)))))) + | ((vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__valid_st1 + [0U] & vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__is_mrvq_st1 + [0U]) & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__recover_mrvq_state_st2))); + vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__miss_add + = (((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__miss_add_unqual) + & (0x10U != (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__cache_miss_resrv__DOT__size))) + & (~ (((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__cwbq_push_stall) + | (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__dwbq_push_stall)) + | (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__dram_fill_req_stall)))); + vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__dwb_queue__DOT__writing + = ((((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__dwbq_push_unqual) + & (~ (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__genblk2__DOT__full_r))) + & (~ (((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__cwbq_push_stall) + | (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__mrvq_push_stall)) + | (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__dram_fill_req_stall)))) + & (~ (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__genblk2__DOT__full_r))); + vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__cwb_queue__DOT__writing + = (((((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__cwbq_push_unqual) + & (~ (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__cwb_queue__DOT__genblk3__DOT__genblk2__DOT__full_r))) + & (~ (vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__st_1e_2__DOT__value[0U] + >> 6U))) & (~ (((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__dwbq_push_stall) + | (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__mrvq_push_stall)) + | (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__dram_fill_req_stall)))) + & (~ (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__cwb_queue__DOT__genblk3__DOT__genblk2__DOT__full_r))); + vlTOPp->VX_cache__DOT__per_bank_dram_fill_req_valid + = ((0xbU & (IData)(vlTOPp->VX_cache__DOT__per_bank_dram_fill_req_valid)) + | ((((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__miss_add_unqual) + << 2U) & (((~ (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__mrvq_init_ready_state_st2)) + << 2U) | (0xfcU & ((vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__st_1e_2__DOT__value[9U] + >> 0x18U) + & ((~ + (vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__st_1e_2__DOT__value[9U] + >> 0x1bU)) + << 2U))))) + & ((~ (((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__dwbq_push_stall) + | (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__mrvq_push_stall)) + | (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__cwbq_push_stall))) + << 2U))); + vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__stall_bank_pipe + = ((((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__cwbq_push_stall) + | (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__dwbq_push_stall)) + | (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__mrvq_push_stall)) + | (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__dram_fill_req_stall)); + vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__force_request_miss_st1e + = (((vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__valid_st1 + [0U] & (~ vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__is_mrvq_st1 + [0U])) & ((0U != (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__cache_miss_resrv__DOT__valid_address_match)) + | ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__miss_add_because_miss) + & (((0x3ffffffU & + ((vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__st_1e_2__DOT__value[9U] + << 7U) | ( + vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__st_1e_2__DOT__value[8U] + >> 0x19U))) + == vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__addr_st1 + [0U]) & (~ (vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__st_1e_2__DOT__value[9U] + >> 0x14U)))))) + | ((vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__valid_st1 + [0U] & vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__is_mrvq_st1 + [0U]) & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__recover_mrvq_state_st2))); + vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__miss_add + = (((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__miss_add_unqual) + & (0x10U != (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cache_miss_resrv__DOT__size))) + & (~ (((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cwbq_push_stall) + | (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__dwbq_push_stall)) + | (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__dram_fill_req_stall)))); + vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__dwb_queue__DOT__writing + = ((((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__dwbq_push_unqual) + & (~ (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__genblk2__DOT__full_r))) + & (~ (((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cwbq_push_stall) + | (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__mrvq_push_stall)) + | (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__dram_fill_req_stall)))) + & (~ (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__genblk2__DOT__full_r))); + vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cwb_queue__DOT__writing + = (((((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cwbq_push_unqual) + & (~ (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cwb_queue__DOT__genblk3__DOT__genblk2__DOT__full_r))) + & (~ (vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__st_1e_2__DOT__value[0U] + >> 6U))) & (~ (((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__dwbq_push_stall) + | (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__mrvq_push_stall)) + | (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__dram_fill_req_stall)))) + & (~ (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cwb_queue__DOT__genblk3__DOT__genblk2__DOT__full_r))); + vlTOPp->VX_cache__DOT__per_bank_dram_fill_req_valid + = ((7U & (IData)(vlTOPp->VX_cache__DOT__per_bank_dram_fill_req_valid)) + | ((((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__miss_add_unqual) + << 3U) & (((~ (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__mrvq_init_ready_state_st2)) + << 3U) | (0x1f8U & ((vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__st_1e_2__DOT__value[9U] + >> 0x17U) + & ((~ + (vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__st_1e_2__DOT__value[9U] + >> 0x1bU)) + << 3U))))) + & ((~ (((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__dwbq_push_stall) + | (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__mrvq_push_stall)) + | (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cwbq_push_stall))) + << 3U))); + vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__stall_bank_pipe + = ((((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cwbq_push_stall) + | (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__dwbq_push_stall)) + | (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__mrvq_push_stall)) + | (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__dram_fill_req_stall)); + vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__force_request_miss_st1e + = (((vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__valid_st1 + [0U] & (~ vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__is_mrvq_st1 + [0U])) & ((0U != (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cache_miss_resrv__DOT__valid_address_match)) + | ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__miss_add_because_miss) + & (((0x3ffffffU & + ((vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__st_1e_2__DOT__value[9U] + << 7U) | ( + vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__st_1e_2__DOT__value[8U] + >> 0x19U))) + == vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__addr_st1 + [0U]) & (~ (vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__st_1e_2__DOT__value[9U] + >> 0x14U)))))) + | ((vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__valid_st1 + [0U] & vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__is_mrvq_st1 + [0U]) & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__recover_mrvq_state_st2))); + vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cwb_queue__DOT__reading + = (1U & (((~ (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cwb_queue__DOT__genblk3__DOT__genblk2__DOT__empty_r)) + & (IData)(vlTOPp->VX_cache__DOT__per_bank_core_rsp_ready)) + & (~ (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cwb_queue__DOT__genblk3__DOT__genblk2__DOT__empty_r)))); + vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__cwb_queue__DOT__reading + = (1U & (((~ (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__cwb_queue__DOT__genblk3__DOT__genblk2__DOT__empty_r)) + & ((IData)(vlTOPp->VX_cache__DOT__per_bank_core_rsp_ready) + >> 1U)) & (~ (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__cwb_queue__DOT__genblk3__DOT__genblk2__DOT__empty_r)))); + vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__cwb_queue__DOT__reading + = (1U & (((~ (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__cwb_queue__DOT__genblk3__DOT__genblk2__DOT__empty_r)) + & ((IData)(vlTOPp->VX_cache__DOT__per_bank_core_rsp_ready) + >> 2U)) & (~ (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__cwb_queue__DOT__genblk3__DOT__genblk2__DOT__empty_r)))); + vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cwb_queue__DOT__reading + = (1U & (((~ (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cwb_queue__DOT__genblk3__DOT__genblk2__DOT__empty_r)) + & ((IData)(vlTOPp->VX_cache__DOT__per_bank_core_rsp_ready) + >> 3U)) & (~ (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cwb_queue__DOT__genblk3__DOT__genblk2__DOT__empty_r)))); + vlTOPp->snp_rsp_valid = vlTOPp->VX_cache__DOT__snp_rsp_arb__DOT__fsq_valid; + vlTOPp->VX_cache__DOT__snp_rsp_arb__DOT__sel_ffsq__DOT__genblk2__DOT__grant_onehot_r = 0U; + vlTOPp->VX_cache__DOT__snp_rsp_arb__DOT__sel_ffsq__DOT__genblk2__DOT__grant_onehot_r + = ((IData)(vlTOPp->VX_cache__DOT__snp_rsp_arb__DOT__sel_ffsq__DOT__genblk2__DOT__grant_onehot_r) + | ((IData)(1U) << (IData)(vlTOPp->VX_cache__DOT__snp_rsp_arb__DOT__fsq_bank))); + vlTOPp->snp_rsp_tag = ((0x6fU >= (0x7fU & ((IData)(0x1cU) + * (IData)(vlTOPp->VX_cache__DOT__snp_rsp_arb__DOT__fsq_bank)))) + ? (0xfffffffU & (((0U == + (0x1fU + & ((IData)(0x1cU) + * (IData)(vlTOPp->VX_cache__DOT__snp_rsp_arb__DOT__fsq_bank)))) + ? 0U + : (vlTOPp->VX_cache__DOT__per_bank_snp_rsp_tag[ + ((IData)(1U) + + + (3U + & (((IData)(0x1cU) + * (IData)(vlTOPp->VX_cache__DOT__snp_rsp_arb__DOT__fsq_bank)) + >> 5U)))] + << + ((IData)(0x20U) + - + (0x1fU + & ((IData)(0x1cU) + * (IData)(vlTOPp->VX_cache__DOT__snp_rsp_arb__DOT__fsq_bank)))))) + | (vlTOPp->VX_cache__DOT__per_bank_snp_rsp_tag[ + (3U + & (((IData)(0x1cU) + * (IData)(vlTOPp->VX_cache__DOT__snp_rsp_arb__DOT__fsq_bank)) + >> 5U))] + >> + (0x1fU + & ((IData)(0x1cU) + * (IData)(vlTOPp->VX_cache__DOT__snp_rsp_arb__DOT__fsq_bank)))))) + : 0U); + vlTOPp->VX_cache__DOT__per_bank_snp_rsp_ready = + ((0xeU & (IData)(vlTOPp->VX_cache__DOT__per_bank_snp_rsp_ready)) + | ((IData)(vlTOPp->snp_rsp_ready) & (0U == (IData)(vlTOPp->VX_cache__DOT__snp_rsp_arb__DOT__fsq_bank)))); + vlTOPp->VX_cache__DOT__per_bank_snp_rsp_ready = + ((0xdU & (IData)(vlTOPp->VX_cache__DOT__per_bank_snp_rsp_ready)) + | (((IData)(vlTOPp->snp_rsp_ready) & (1U == (IData)(vlTOPp->VX_cache__DOT__snp_rsp_arb__DOT__fsq_bank))) + << 1U)); + vlTOPp->VX_cache__DOT__per_bank_snp_rsp_ready = + ((0xbU & (IData)(vlTOPp->VX_cache__DOT__per_bank_snp_rsp_ready)) + | (((IData)(vlTOPp->snp_rsp_ready) & (2U == (IData)(vlTOPp->VX_cache__DOT__snp_rsp_arb__DOT__fsq_bank))) + << 2U)); + vlTOPp->VX_cache__DOT__per_bank_snp_rsp_ready = + ((7U & (IData)(vlTOPp->VX_cache__DOT__per_bank_snp_rsp_ready)) + | (((IData)(vlTOPp->snp_rsp_ready) & (3U == (IData)(vlTOPp->VX_cache__DOT__snp_rsp_arb__DOT__fsq_bank))) + << 3U)); + vlTOPp->dram_req_rw = vlTOPp->VX_cache__DOT__cache_dram_req_arb__DOT__dwb_valid; + vlTOPp->dram_req_valid = ((IData)(vlTOPp->VX_cache__DOT__cache_dram_req_arb__DOT__dwb_valid) + | (IData)(vlTOPp->VX_cache__DOT__cache_dram_req_arb__DOT__dfqq_req)); + vlTOPp->VX_cache__DOT__cache_dram_req_arb__DOT__dfqq_pop + = (((~ (IData)(vlTOPp->VX_cache__DOT__cache_dram_req_arb__DOT__dwb_valid)) + & (IData)(vlTOPp->VX_cache__DOT__cache_dram_req_arb__DOT__dfqq_req)) + & (IData)(vlTOPp->dram_req_ready)); + vlTOPp->VX_cache__DOT__cache_dram_req_arb__DOT__sel_dwb__DOT__genblk2__DOT__grant_onehot_r = 0U; + vlTOPp->VX_cache__DOT__cache_dram_req_arb__DOT__sel_dwb__DOT__genblk2__DOT__grant_onehot_r + = ((IData)(vlTOPp->VX_cache__DOT__cache_dram_req_arb__DOT__sel_dwb__DOT__genblk2__DOT__grant_onehot_r) + | ((IData)(1U) << (IData)(vlTOPp->VX_cache__DOT__cache_dram_req_arb__DOT__dwb_bank))); + vlTOPp->dram_req_byteen = ((IData)(vlTOPp->VX_cache__DOT__cache_dram_req_arb__DOT__dwb_valid) + ? (0xffffU & (IData)( + (vlTOPp->VX_cache__DOT__per_bank_dram_wb_req_byteen + >> + (0x3fU + & ((IData)(vlTOPp->VX_cache__DOT__cache_dram_req_arb__DOT__dwb_bank) + << 4U))))) + : 0xffffU); + vlTOPp->dram_req_data[0U] = ((IData)(vlTOPp->VX_cache__DOT__cache_dram_req_arb__DOT__dwb_valid) + ? (((0U == (0x1fU + & ((IData)(vlTOPp->VX_cache__DOT__cache_dram_req_arb__DOT__dwb_bank) + << 7U))) + ? 0U : (vlTOPp->VX_cache__DOT__per_bank_dram_wb_req_data[ + ((IData)(1U) + + (0xcU + & ((IData)(vlTOPp->VX_cache__DOT__cache_dram_req_arb__DOT__dwb_bank) + << 2U)))] + << ((IData)(0x20U) + - + (0x1fU + & ((IData)(vlTOPp->VX_cache__DOT__cache_dram_req_arb__DOT__dwb_bank) + << 7U))))) + | (vlTOPp->VX_cache__DOT__per_bank_dram_wb_req_data[ + (0xcU & ((IData)(vlTOPp->VX_cache__DOT__cache_dram_req_arb__DOT__dwb_bank) + << 2U))] + >> (0x1fU & + ((IData)(vlTOPp->VX_cache__DOT__cache_dram_req_arb__DOT__dwb_bank) + << 7U)))) + : 0U); + vlTOPp->dram_req_data[1U] = ((IData)(vlTOPp->VX_cache__DOT__cache_dram_req_arb__DOT__dwb_valid) + ? (((0U == (0x1fU + & ((IData)(vlTOPp->VX_cache__DOT__cache_dram_req_arb__DOT__dwb_bank) + << 7U))) + ? 0U : (vlTOPp->VX_cache__DOT__per_bank_dram_wb_req_data[ + ((IData)(2U) + + (0xcU + & ((IData)(vlTOPp->VX_cache__DOT__cache_dram_req_arb__DOT__dwb_bank) + << 2U)))] + << ((IData)(0x20U) + - + (0x1fU + & ((IData)(vlTOPp->VX_cache__DOT__cache_dram_req_arb__DOT__dwb_bank) + << 7U))))) + | (vlTOPp->VX_cache__DOT__per_bank_dram_wb_req_data[ + ((IData)(1U) + + (0xcU & + ((IData)(vlTOPp->VX_cache__DOT__cache_dram_req_arb__DOT__dwb_bank) + << 2U)))] + >> (0x1fU & + ((IData)(vlTOPp->VX_cache__DOT__cache_dram_req_arb__DOT__dwb_bank) + << 7U)))) + : 0U); + vlTOPp->dram_req_data[2U] = ((IData)(vlTOPp->VX_cache__DOT__cache_dram_req_arb__DOT__dwb_valid) + ? (((0U == (0x1fU + & ((IData)(vlTOPp->VX_cache__DOT__cache_dram_req_arb__DOT__dwb_bank) + << 7U))) + ? 0U : (vlTOPp->VX_cache__DOT__per_bank_dram_wb_req_data[ + ((IData)(3U) + + (0xcU + & ((IData)(vlTOPp->VX_cache__DOT__cache_dram_req_arb__DOT__dwb_bank) + << 2U)))] + << ((IData)(0x20U) + - + (0x1fU + & ((IData)(vlTOPp->VX_cache__DOT__cache_dram_req_arb__DOT__dwb_bank) + << 7U))))) + | (vlTOPp->VX_cache__DOT__per_bank_dram_wb_req_data[ + ((IData)(2U) + + (0xcU & + ((IData)(vlTOPp->VX_cache__DOT__cache_dram_req_arb__DOT__dwb_bank) + << 2U)))] + >> (0x1fU & + ((IData)(vlTOPp->VX_cache__DOT__cache_dram_req_arb__DOT__dwb_bank) + << 7U)))) + : 0U); + vlTOPp->dram_req_data[3U] = ((IData)(vlTOPp->VX_cache__DOT__cache_dram_req_arb__DOT__dwb_valid) + ? (((0U == (0x1fU + & ((IData)(vlTOPp->VX_cache__DOT__cache_dram_req_arb__DOT__dwb_bank) + << 7U))) + ? 0U : (vlTOPp->VX_cache__DOT__per_bank_dram_wb_req_data[ + ((IData)(4U) + + (0xcU + & ((IData)(vlTOPp->VX_cache__DOT__cache_dram_req_arb__DOT__dwb_bank) + << 2U)))] + << ((IData)(0x20U) + - + (0x1fU + & ((IData)(vlTOPp->VX_cache__DOT__cache_dram_req_arb__DOT__dwb_bank) + << 7U))))) + | (vlTOPp->VX_cache__DOT__per_bank_dram_wb_req_data[ + ((IData)(3U) + + (0xcU & + ((IData)(vlTOPp->VX_cache__DOT__cache_dram_req_arb__DOT__dwb_bank) + << 2U)))] + >> (0x1fU & + ((IData)(vlTOPp->VX_cache__DOT__cache_dram_req_arb__DOT__dwb_bank) + << 7U)))) + : 0U); + vlTOPp->dram_req_addr = (0xfffffffU & ((IData)(vlTOPp->VX_cache__DOT__cache_dram_req_arb__DOT__dwb_valid) + ? ((0x6fU + >= + (0x7fU + & ((IData)(0x1cU) + * (IData)(vlTOPp->VX_cache__DOT__cache_dram_req_arb__DOT__dwb_bank)))) + ? ( + ((0U + == + (0x1fU + & ((IData)(0x1cU) + * (IData)(vlTOPp->VX_cache__DOT__cache_dram_req_arb__DOT__dwb_bank)))) + ? 0U + : + (vlTOPp->VX_cache__DOT__per_bank_dram_wb_req_addr[ + ((IData)(1U) + + + (3U + & (((IData)(0x1cU) + * (IData)(vlTOPp->VX_cache__DOT__cache_dram_req_arb__DOT__dwb_bank)) + >> 5U)))] + << + ((IData)(0x20U) + - + (0x1fU + & ((IData)(0x1cU) + * (IData)(vlTOPp->VX_cache__DOT__cache_dram_req_arb__DOT__dwb_bank)))))) + | (vlTOPp->VX_cache__DOT__per_bank_dram_wb_req_addr[ + (3U + & (((IData)(0x1cU) + * (IData)(vlTOPp->VX_cache__DOT__cache_dram_req_arb__DOT__dwb_bank)) + >> 5U))] + >> + (0x1fU + & ((IData)(0x1cU) + * (IData)(vlTOPp->VX_cache__DOT__cache_dram_req_arb__DOT__dwb_bank))))) + : 0U) + : ((IData)(vlTOPp->VX_cache__DOT__cache_dram_req_arb__DOT__dfqq_req) + ? ( + (0x6fU + >= + (0x7fU + & ((IData)(0x1cU) + * (IData)(vlTOPp->VX_cache__DOT__cache_dram_req_arb__DOT__dram_fill_arb__DOT__qual_request_index)))) + ? + (((0U + == + (0x1fU + & ((IData)(0x1cU) + * (IData)(vlTOPp->VX_cache__DOT__cache_dram_req_arb__DOT__dram_fill_arb__DOT__qual_request_index)))) + ? 0U + : + (vlTOPp->VX_cache__DOT__cache_dram_req_arb__DOT__dram_fill_arb__DOT__qual_bank_dram_fill_req_addr[ + ((IData)(1U) + + + (3U + & (((IData)(0x1cU) + * (IData)(vlTOPp->VX_cache__DOT__cache_dram_req_arb__DOT__dram_fill_arb__DOT__qual_request_index)) + >> 5U)))] + << + ((IData)(0x20U) + - + (0x1fU + & ((IData)(0x1cU) + * (IData)(vlTOPp->VX_cache__DOT__cache_dram_req_arb__DOT__dram_fill_arb__DOT__qual_request_index)))))) + | (vlTOPp->VX_cache__DOT__cache_dram_req_arb__DOT__dram_fill_arb__DOT__qual_bank_dram_fill_req_addr[ + (3U + & (((IData)(0x1cU) + * (IData)(vlTOPp->VX_cache__DOT__cache_dram_req_arb__DOT__dram_fill_arb__DOT__qual_request_index)) + >> 5U))] + >> + (0x1fU + & ((IData)(0x1cU) + * (IData)(vlTOPp->VX_cache__DOT__cache_dram_req_arb__DOT__dram_fill_arb__DOT__qual_request_index))))) + : 0U) + : vlTOPp->VX_cache__DOT__cache_dram_req_arb__DOT__prfqq__DOT__use_addr))); + vlTOPp->VX_cache__DOT__per_bank_dram_wb_req_ready + = ((0xeU & (IData)(vlTOPp->VX_cache__DOT__per_bank_dram_wb_req_ready)) + | ((IData)(vlTOPp->dram_req_ready) & (0U + == (IData)(vlTOPp->VX_cache__DOT__cache_dram_req_arb__DOT__dwb_bank)))); + vlTOPp->VX_cache__DOT__per_bank_dram_wb_req_ready + = ((0xdU & (IData)(vlTOPp->VX_cache__DOT__per_bank_dram_wb_req_ready)) + | (((IData)(vlTOPp->dram_req_ready) & (1U + == (IData)(vlTOPp->VX_cache__DOT__cache_dram_req_arb__DOT__dwb_bank))) + << 1U)); + vlTOPp->VX_cache__DOT__per_bank_dram_wb_req_ready + = ((0xbU & (IData)(vlTOPp->VX_cache__DOT__per_bank_dram_wb_req_ready)) + | (((IData)(vlTOPp->dram_req_ready) & (2U + == (IData)(vlTOPp->VX_cache__DOT__cache_dram_req_arb__DOT__dwb_bank))) + << 2U)); + vlTOPp->VX_cache__DOT__per_bank_dram_wb_req_ready + = ((7U & (IData)(vlTOPp->VX_cache__DOT__per_bank_dram_wb_req_ready)) + | (((IData)(vlTOPp->dram_req_ready) & (3U + == (IData)(vlTOPp->VX_cache__DOT__cache_dram_req_arb__DOT__dwb_bank))) + << 3U)); + vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__tag_data_access__DOT__real_writefill + = ((vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__valid_st1 + [0U] & vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__is_fill_st1 + [0U]) & ((~ vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__tag_data_access__DOT__read_valid_st1c + [0U]) | (vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__tag_data_access__DOT__read_valid_st1c + [0U] & (~ (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__tag_data_access__DOT__tags_match))))); + vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__tag_data_access__DOT__real_miss + = ((((vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__valid_st1 + [0U] & (~ vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__is_snp_st1 + [0U])) & (~ vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__tag_data_access__DOT__read_valid_st1c + [0U])) & (~ vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__is_fill_st1 + [0U])) | + ((((vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__valid_st1 + [0U] & (~ vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__is_snp_st1 + [0U])) & vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__tag_data_access__DOT__read_valid_st1c + [0U]) & (~ vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__is_fill_st1 + [0U])) & (~ (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__tag_data_access__DOT__tags_match)))); + vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__tag_data_access__DOT__real_writefill + = ((vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__valid_st1 + [0U] & vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__is_fill_st1 + [0U]) & ((~ vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__tag_data_access__DOT__read_valid_st1c + [0U]) | (vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__tag_data_access__DOT__read_valid_st1c + [0U] & (~ (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__tag_data_access__DOT__tags_match))))); + vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__tag_data_access__DOT__real_miss + = ((((vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__valid_st1 + [0U] & (~ vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__is_snp_st1 + [0U])) & (~ vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__tag_data_access__DOT__read_valid_st1c + [0U])) & (~ vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__is_fill_st1 + [0U])) | + ((((vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__valid_st1 + [0U] & (~ vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__is_snp_st1 + [0U])) & vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__tag_data_access__DOT__read_valid_st1c + [0U]) & (~ vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__is_fill_st1 + [0U])) & (~ (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__tag_data_access__DOT__tags_match)))); + vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__tag_data_access__DOT__real_writefill + = ((vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__valid_st1 + [0U] & vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__is_fill_st1 + [0U]) & ((~ vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__tag_data_access__DOT__read_valid_st1c + [0U]) | (vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__tag_data_access__DOT__read_valid_st1c + [0U] & (~ (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__tag_data_access__DOT__tags_match))))); + vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__tag_data_access__DOT__real_miss + = ((((vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__valid_st1 + [0U] & (~ vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__is_snp_st1 + [0U])) & (~ vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__tag_data_access__DOT__read_valid_st1c + [0U])) & (~ vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__is_fill_st1 + [0U])) | + ((((vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__valid_st1 + [0U] & (~ vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__is_snp_st1 + [0U])) & vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__tag_data_access__DOT__read_valid_st1c + [0U]) & (~ vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__is_fill_st1 + [0U])) & (~ (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__tag_data_access__DOT__tags_match)))); + vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__tag_data_access__DOT__real_writefill + = ((vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__valid_st1 + [0U] & vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__is_fill_st1 + [0U]) & ((~ vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__tag_data_access__DOT__read_valid_st1c + [0U]) | (vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__tag_data_access__DOT__read_valid_st1c + [0U] & (~ (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__tag_data_access__DOT__tags_match))))); + vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__tag_data_access__DOT__real_miss + = ((((vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__valid_st1 + [0U] & (~ vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__is_snp_st1 + [0U])) & (~ vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__tag_data_access__DOT__read_valid_st1c + [0U])) & (~ vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__is_fill_st1 + [0U])) | + ((((vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__valid_st1 + [0U] & (~ vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__is_snp_st1 + [0U])) & vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__tag_data_access__DOT__read_valid_st1c + [0U]) & (~ vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__is_fill_st1 + [0U])) & (~ (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__tag_data_access__DOT__tags_match)))); + vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__miss_add_is_mrvq + = (1U & (((vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__st_1e_2__DOT__value[9U] + >> 0x13U) & (vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__st_1e_2__DOT__value[9U] + >> 0x1aU)) & (~ (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__stall_bank_pipe)))); + vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__reqq_pop + = ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__reqq_pop_unqual) + & (~ (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__stall_bank_pipe))); + vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__dfpq_pop + = ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__dfpq_pop_unqual) + & (~ (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__stall_bank_pipe))); + vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__snrq_pop + = ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__snrq_pop_unqual) + & (~ (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__stall_bank_pipe))); + vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__mrvq_pop + = (((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cache_miss_resrv__DOT__dequeue_possible) + & (~ (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__stall_bank_pipe))) + & (~ (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__recover_mrvq_state_st2))); + vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__snp_to_mrvq_st1e + = ((vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__valid_st1 + [0U] & vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__is_snp_st1 + [0U]) & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__force_request_miss_st1e)); + vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__tag_data_access__DOT__snoop_hit_no_pending + = (((((vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__valid_st1 + [0U] & vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__is_snp_st1 + [0U]) & vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__tag_data_access__DOT__read_valid_st1c + [0U]) & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__tag_data_access__DOT__tags_match)) + & (vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__tag_data_access__DOT__read_dirty_st1c + [0U] | vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__snp_invalidate_st1 + [0U])) & (~ (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__force_request_miss_st1e))); + vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__miss_add_is_mrvq + = (1U & (((vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__st_1e_2__DOT__value[9U] + >> 0x13U) & (vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__st_1e_2__DOT__value[9U] + >> 0x1aU)) & (~ (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__stall_bank_pipe)))); + vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__reqq_pop + = ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__reqq_pop_unqual) + & (~ (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__stall_bank_pipe))); + vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__dfpq_pop + = ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__dfpq_pop_unqual) + & (~ (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__stall_bank_pipe))); + vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__snrq_pop + = ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__snrq_pop_unqual) + & (~ (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__stall_bank_pipe))); + vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__mrvq_pop + = (((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__cache_miss_resrv__DOT__dequeue_possible) + & (~ (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__stall_bank_pipe))) + & (~ (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__recover_mrvq_state_st2))); + vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__snp_to_mrvq_st1e + = ((vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__valid_st1 + [0U] & vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__is_snp_st1 + [0U]) & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__force_request_miss_st1e)); + vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__tag_data_access__DOT__snoop_hit_no_pending + = (((((vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__valid_st1 + [0U] & vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__is_snp_st1 + [0U]) & vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__tag_data_access__DOT__read_valid_st1c + [0U]) & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__tag_data_access__DOT__tags_match)) + & (vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__tag_data_access__DOT__read_dirty_st1c + [0U] | vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__snp_invalidate_st1 + [0U])) & (~ (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__force_request_miss_st1e))); + vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__miss_add_is_mrvq + = (1U & (((vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__st_1e_2__DOT__value[9U] + >> 0x13U) & (vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__st_1e_2__DOT__value[9U] + >> 0x1aU)) & (~ (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__stall_bank_pipe)))); + vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__reqq_pop + = ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__reqq_pop_unqual) + & (~ (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__stall_bank_pipe))); + vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__dfpq_pop + = ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__dfpq_pop_unqual) + & (~ (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__stall_bank_pipe))); + vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__snrq_pop + = ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__snrq_pop_unqual) + & (~ (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__stall_bank_pipe))); + vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__mrvq_pop + = (((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__cache_miss_resrv__DOT__dequeue_possible) + & (~ (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__stall_bank_pipe))) + & (~ (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__recover_mrvq_state_st2))); + vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__snp_to_mrvq_st1e + = ((vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__valid_st1 + [0U] & vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__is_snp_st1 + [0U]) & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__force_request_miss_st1e)); + vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__tag_data_access__DOT__snoop_hit_no_pending + = (((((vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__valid_st1 + [0U] & vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__is_snp_st1 + [0U]) & vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__tag_data_access__DOT__read_valid_st1c + [0U]) & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__tag_data_access__DOT__tags_match)) + & (vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__tag_data_access__DOT__read_dirty_st1c + [0U] | vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__snp_invalidate_st1 + [0U])) & (~ (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__force_request_miss_st1e))); + vlTOPp->VX_cache__DOT__cache_dram_req_arb__DOT__dram_fill_arb__DOT____Vcellinp__dfqq_queue__data_in[0U] + = vlTOPp->VX_cache__DOT__per_bank_dram_fill_req_addr[0U]; + vlTOPp->VX_cache__DOT__cache_dram_req_arb__DOT__dram_fill_arb__DOT____Vcellinp__dfqq_queue__data_in[1U] + = vlTOPp->VX_cache__DOT__per_bank_dram_fill_req_addr[1U]; + vlTOPp->VX_cache__DOT__cache_dram_req_arb__DOT__dram_fill_arb__DOT____Vcellinp__dfqq_queue__data_in[2U] + = vlTOPp->VX_cache__DOT__per_bank_dram_fill_req_addr[2U]; + vlTOPp->VX_cache__DOT__cache_dram_req_arb__DOT__dram_fill_arb__DOT____Vcellinp__dfqq_queue__data_in[3U] + = ((0xffff0000U & ((IData)(vlTOPp->VX_cache__DOT__per_bank_dram_fill_req_valid) + << 0x10U)) | vlTOPp->VX_cache__DOT__per_bank_dram_fill_req_addr[3U]); + vlTOPp->VX_cache__DOT__cache_dram_req_arb__DOT__dram_fill_arb__DOT__dfqq_queue__DOT__writing + = (((0U != (IData)(vlTOPp->VX_cache__DOT__per_bank_dram_fill_req_valid)) + & (~ (IData)(vlTOPp->VX_cache__DOT__cache_dram_req_arb__DOT__dram_fill_arb__DOT__dfqq_queue__DOT__genblk3__DOT__genblk2__DOT__full_r))) + & (~ (IData)(vlTOPp->VX_cache__DOT__cache_dram_req_arb__DOT__dram_fill_arb__DOT__dfqq_queue__DOT__genblk3__DOT__genblk2__DOT__full_r))); + vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__miss_add_is_mrvq + = (1U & (((vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__st_1e_2__DOT__value[9U] + >> 0x13U) & (vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__st_1e_2__DOT__value[9U] + >> 0x1aU)) & (~ (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__stall_bank_pipe)))); + vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__reqq_pop + = ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__reqq_pop_unqual) + & (~ (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__stall_bank_pipe))); + vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__dfpq_pop + = ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__dfpq_pop_unqual) + & (~ (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__stall_bank_pipe))); + vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__snrq_pop + = ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__snrq_pop_unqual) + & (~ (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__stall_bank_pipe))); + vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__mrvq_pop + = (((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cache_miss_resrv__DOT__dequeue_possible) + & (~ (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__stall_bank_pipe))) + & (~ (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__recover_mrvq_state_st2))); + vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__snp_to_mrvq_st1e + = ((vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__valid_st1 + [0U] & vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__is_snp_st1 + [0U]) & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__force_request_miss_st1e)); + vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__tag_data_access__DOT__snoop_hit_no_pending + = (((((vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__valid_st1 + [0U] & vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__is_snp_st1 + [0U]) & vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__tag_data_access__DOT__read_valid_st1c + [0U]) & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__tag_data_access__DOT__tags_match)) + & (vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__tag_data_access__DOT__read_dirty_st1c + [0U] | vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__snp_invalidate_st1 + [0U])) & (~ (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__force_request_miss_st1e))); + vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__snp_rsp_fire + = ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__curr_bank_snp_rsp_valid) + & (IData)(vlTOPp->VX_cache__DOT__per_bank_snp_rsp_ready)); + vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__snp_rsp_fire + = ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__curr_bank_snp_rsp_valid) + & ((IData)(vlTOPp->VX_cache__DOT__per_bank_snp_rsp_ready) + >> 1U)); + vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__snp_rsp_fire + = ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__curr_bank_snp_rsp_valid) + & ((IData)(vlTOPp->VX_cache__DOT__per_bank_snp_rsp_ready) + >> 2U)); + vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__snp_rsp_fire + = ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__curr_bank_snp_rsp_valid) + & ((IData)(vlTOPp->VX_cache__DOT__per_bank_snp_rsp_ready) + >> 3U)); + vlTOPp->VX_cache__DOT__cache_dram_req_arb__DOT__prfqq__DOT__pfq_queue__DOT__writing + = ((((IData)(vlTOPp->dram_req_valid) & (~ (IData)(vlTOPp->dram_req_rw))) + & (~ (IData)(vlTOPp->VX_cache__DOT__cache_dram_req_arb__DOT__prfqq__DOT__pfq_queue__DOT__size_r))) + & (~ (IData)(vlTOPp->VX_cache__DOT__cache_dram_req_arb__DOT__prfqq__DOT__pfq_queue__DOT__size_r))); + vlTOPp->VX_cache__DOT__cache_dram_req_arb__DOT__dram_fill_arb__DOT__dfqq_queue__DOT__reading + = ((((IData)(vlTOPp->VX_cache__DOT__cache_dram_req_arb__DOT__dfqq_pop) + & (~ (IData)((0U != (IData)(vlTOPp->VX_cache__DOT__cache_dram_req_arb__DOT__dram_fill_arb__DOT__use_per_bank_dram_fill_req_valid))))) + & (~ ((~ (IData)((0U != (0xfU & (vlTOPp->VX_cache__DOT__cache_dram_req_arb__DOT__dram_fill_arb__DOT____Vcellout__dfqq_queue__data_out[3U] + >> 0x10U))))) + | (IData)(vlTOPp->VX_cache__DOT__cache_dram_req_arb__DOT__dram_fill_arb__DOT__dfqq_queue__DOT__genblk3__DOT__genblk2__DOT__empty_r)))) + & (~ (IData)(vlTOPp->VX_cache__DOT__cache_dram_req_arb__DOT__dram_fill_arb__DOT__dfqq_queue__DOT__genblk3__DOT__genblk2__DOT__empty_r))); + vlTOPp->dram_req_tag = vlTOPp->dram_req_addr; + vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__dram_wb_req_fire + = ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__curr_bank_dram_wb_req_valid) + & (IData)(vlTOPp->VX_cache__DOT__per_bank_dram_wb_req_ready)); + vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__dram_wb_req_fire + = ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__curr_bank_dram_wb_req_valid) + & ((IData)(vlTOPp->VX_cache__DOT__per_bank_dram_wb_req_ready) + >> 1U)); + vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__dram_wb_req_fire + = ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__curr_bank_dram_wb_req_valid) + & ((IData)(vlTOPp->VX_cache__DOT__per_bank_dram_wb_req_ready) + >> 2U)); + vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__dram_wb_req_fire + = ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__curr_bank_dram_wb_req_valid) + & ((IData)(vlTOPp->VX_cache__DOT__per_bank_dram_wb_req_ready) + >> 3U)); + vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__tag_data_access__DOT__data_write[0U] + = ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__tag_data_access__DOT__real_writefill) + ? vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__writedata_st1 + [0U][0U] : vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__writeword_st1 + [0U]); + vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__tag_data_access__DOT__data_write[1U] + = ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__tag_data_access__DOT__real_writefill) + ? vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__writedata_st1 + [0U][1U] : vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__writeword_st1 + [0U]); + vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__tag_data_access__DOT__data_write[2U] + = ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__tag_data_access__DOT__real_writefill) + ? vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__writedata_st1 + [0U][2U] : vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__writeword_st1 + [0U]); + vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__tag_data_access__DOT__data_write[3U] + = ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__tag_data_access__DOT__real_writefill) + ? vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__writedata_st1 + [0U][3U] : vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__writeword_st1 + [0U]); + vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__tag_data_access__DOT__data_write[0U] + = ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__tag_data_access__DOT__real_writefill) + ? vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__writedata_st1 + [0U][0U] : vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__writeword_st1 + [0U]); + vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__tag_data_access__DOT__data_write[1U] + = ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__tag_data_access__DOT__real_writefill) + ? vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__writedata_st1 + [0U][1U] : vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__writeword_st1 + [0U]); + vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__tag_data_access__DOT__data_write[2U] + = ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__tag_data_access__DOT__real_writefill) + ? vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__writedata_st1 + [0U][2U] : vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__writeword_st1 + [0U]); + vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__tag_data_access__DOT__data_write[3U] + = ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__tag_data_access__DOT__real_writefill) + ? vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__writedata_st1 + [0U][3U] : vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__writeword_st1 + [0U]); + vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__tag_data_access__DOT__data_write[0U] + = ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__tag_data_access__DOT__real_writefill) + ? vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__writedata_st1 + [0U][0U] : vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__writeword_st1 + [0U]); + vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__tag_data_access__DOT__data_write[1U] + = ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__tag_data_access__DOT__real_writefill) + ? vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__writedata_st1 + [0U][1U] : vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__writeword_st1 + [0U]); + vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__tag_data_access__DOT__data_write[2U] + = ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__tag_data_access__DOT__real_writefill) + ? vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__writedata_st1 + [0U][2U] : vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__writeword_st1 + [0U]); + vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__tag_data_access__DOT__data_write[3U] + = ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__tag_data_access__DOT__real_writefill) + ? vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__writedata_st1 + [0U][3U] : vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__writeword_st1 + [0U]); + vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__tag_data_access__DOT__data_write[0U] + = ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__tag_data_access__DOT__real_writefill) + ? vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__writedata_st1 + [0U][0U] : vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__writeword_st1 + [0U]); + vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__tag_data_access__DOT__data_write[1U] + = ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__tag_data_access__DOT__real_writefill) + ? vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__writedata_st1 + [0U][1U] : vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__writeword_st1 + [0U]); + vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__tag_data_access__DOT__data_write[2U] + = ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__tag_data_access__DOT__real_writefill) + ? vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__writedata_st1 + [0U][2U] : vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__writeword_st1 + [0U]); + vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__tag_data_access__DOT__data_write[3U] + = ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__tag_data_access__DOT__real_writefill) + ? vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__writedata_st1 + [0U][3U] : vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__writeword_st1 + [0U]); + vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cache_miss_resrv__DOT__increment_head + = ((~ (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__miss_add)) + & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__miss_add_is_mrvq)); + vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cache_miss_resrv__DOT__mrvq_push + = (((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__miss_add) + & (0x10U != (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cache_miss_resrv__DOT__size))) + & (~ (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__miss_add_is_mrvq))); + vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__dfp_queue__DOT__reading + = ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__dfpq_pop) + & (~ (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__dfp_queue__DOT__genblk3__DOT__genblk2__DOT__empty_r))); + vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__snp_req_queue__DOT__reading + = ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__snrq_pop) + & (~ (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__snp_req_queue__DOT__genblk3__DOT__genblk2__DOT__empty_r))); + vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cache_miss_resrv__DOT__mrvq_pop + = ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__mrvq_pop) + & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cache_miss_resrv__DOT__dequeue_possible)); + __Vtemp146[4U] = ((0xfffffffeU & ((IData)(((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cache_miss_resrv__DOT__dequeue_possible) + ? ( + (VL_ULL(0x1ffffffffff80) + & (((QData)((IData)( + vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cache_miss_resrv__DOT__metadata_table + [vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr][2U])) + << 0x3eU) + | (((QData)((IData)( + vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cache_miss_resrv__DOT__metadata_table + [vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr][1U])) + << 0x1eU) + | (VL_ULL(0x3fffffffffffff80) + & ((QData)((IData)( + vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cache_miss_resrv__DOT__metadata_table + [vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr][0U])) + >> 2U))))) + | (QData)((IData)( + (((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__mrvq_rw_st0) + << 6U) + | ((0x3cU + & ((vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cache_miss_resrv__DOT__metadata_table + [vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr][1U] + << 0x1eU) + | (0x3ffffffcU + & (vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cache_miss_resrv__DOT__metadata_table + [vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr][0U] + >> 2U)))) + | (3U + & ((vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cache_miss_resrv__DOT__metadata_table + [vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr][2U] + << 0xdU) + | (vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cache_miss_resrv__DOT__metadata_table + [vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr][1U] + >> 0x13U)))))))) + : ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__reqq_pop_unqual) + ? + ((vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__core_req_arb__DOT__use_per_tag + << 7U) + | (QData)((IData)( + (((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__reqq_req_rw_st0) + << 6U) + | ((0x3cU + & (((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__core_req_arb__DOT__use_per_byteen) + >> + (0xfU + & ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__core_req_arb__DOT__qual_request_index) + << 2U))) + << 2U)) + | (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__core_req_arb__DOT__qual_request_index)))))) + : + ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__snrq_pop_unqual) + ? + ((QData)((IData)( + (0xfffffffU + & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT____Vcellout__snp_req_queue__data_out)))) + << 7U) + : VL_ULL(0))))) + << 1U)) | (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__dfpq_pop_unqual)); + __Vtemp146[5U] = ((1U & ((IData)(((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cache_miss_resrv__DOT__dequeue_possible) + ? ((VL_ULL(0x1ffffffffff80) + & (((QData)((IData)( + vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cache_miss_resrv__DOT__metadata_table + [vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr][2U])) + << 0x3eU) + | (((QData)((IData)( + vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cache_miss_resrv__DOT__metadata_table + [vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr][1U])) + << 0x1eU) + | (VL_ULL(0x3fffffffffffff80) + & ((QData)((IData)( + vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cache_miss_resrv__DOT__metadata_table + [vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr][0U])) + >> 2U))))) + | (QData)((IData)( + (((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__mrvq_rw_st0) + << 6U) + | ((0x3cU + & ((vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cache_miss_resrv__DOT__metadata_table + [vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr][1U] + << 0x1eU) + | (0x3ffffffcU + & (vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cache_miss_resrv__DOT__metadata_table + [vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr][0U] + >> 2U)))) + | (3U + & ((vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cache_miss_resrv__DOT__metadata_table + [vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr][2U] + << 0xdU) + | (vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cache_miss_resrv__DOT__metadata_table + [vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr][1U] + >> 0x13U)))))))) + : ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__reqq_pop_unqual) + ? ((vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__core_req_arb__DOT__use_per_tag + << 7U) + | (QData)((IData)( + (((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__reqq_req_rw_st0) + << 6U) + | ((0x3cU + & (((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__core_req_arb__DOT__use_per_byteen) + >> + (0xfU + & ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__core_req_arb__DOT__qual_request_index) + << 2U))) + << 2U)) + | (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__core_req_arb__DOT__qual_request_index)))))) + : ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__snrq_pop_unqual) + ? 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1U + : + (((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cache_miss_resrv__DOT__dequeue_possible) + & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__mrvq_rw_st0)) + ? 1U + : + (((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__reqq_pop_unqual) + & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__reqq_req_rw_st0)) + ? 1U + : 0U))) + << 0x1dU) + | ((((((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__dfpq_pop) + | (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__mrvq_pop)) + | (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__reqq_pop)) + | (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__snrq_pop)) + << 0x1cU) + | ((0xffffffcU + & (((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__dfpq_pop_unqual) + ? + (0x3ffffffU + & vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT____Vcellout__dfp_queue__data_out[4U]) + : + ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cache_miss_resrv__DOT__dequeue_possible) + ? + ((0x19fU + >= + (0x1ffU + & ((IData)(0x1aU) + * (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr)))) + ? + (0x3ffffffU + & (((0U + == + (0x1fU + & ((IData)(0x1aU) + * (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr)))) + ? 0U + : + (vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cache_miss_resrv__DOT__addr_table[ + ((IData)(1U) + + + (0xfU + & (((IData)(0x1aU) + * (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr)) + >> 5U)))] + << + ((IData)(0x20U) + - + (0x1fU + & ((IData)(0x1aU) + * (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr)))))) + | (vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cache_miss_resrv__DOT__addr_table[ + (0xfU + & (((IData)(0x1aU) + * (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr)) + >> 5U))] + >> + (0x1fU + & ((IData)(0x1aU) + * (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr)))))) + : 0U) + : + ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__reqq_pop_unqual) + ? + (0x3ffffffU + & (vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__reqq_req_addr_st0 + >> 4U)) + : + ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__snrq_pop_unqual) + ? + (0x3ffffffU + & (IData)( + (vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT____Vcellout__snp_req_queue__data_out + >> 0x1dU))) + : 0U)))) + << 2U)) + | (3U + & ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__reqq_pop_unqual) + ? + (3U + & vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__reqq_req_addr_st0) + : + ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cache_miss_resrv__DOT__dequeue_possible) + ? + (3U + & ((vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cache_miss_resrv__DOT__metadata_table + [vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr][1U] + << 0x1eU) + | (vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cache_miss_resrv__DOT__metadata_table + [vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr][0U] + >> 2U))) + : 0U)))))))))) + << 0x20U) + | (QData)((IData)( + ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cache_miss_resrv__DOT__dequeue_possible) + ? + ((vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cache_miss_resrv__DOT__metadata_table + [vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr][2U] + << 0xbU) + | (vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cache_miss_resrv__DOT__metadata_table + [vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr][1U] + >> 0x15U)) + : + ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__reqq_pop_unqual) + ? + (((0U + == + (0x1fU + & ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__core_req_arb__DOT__qual_request_index) + << 5U))) + ? 0U + : + (vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__core_req_arb__DOT__use_per_writedata[ + ((IData)(1U) + + + (3U + & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__core_req_arb__DOT__qual_request_index)))] + << + ((IData)(0x20U) + - + (0x1fU + & ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__core_req_arb__DOT__qual_request_index) + << 5U))))) + | (vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__core_req_arb__DOT__use_per_writedata[ + (3U + & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__core_req_arb__DOT__qual_request_index))] + >> + (0x1fU + & ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__core_req_arb__DOT__qual_request_index) + << 5U)))) + : 0U)))))) + >> 0xeU)) | (0xfffc0000U + & ((IData)( + ((((QData)((IData)( + ((0x80000000U + & (((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cache_miss_resrv__DOT__dequeue_possible) + ? + (1U + & (vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cache_miss_resrv__DOT__metadata_table + [vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr][0U] + >> 1U)) + : + ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__snrq_pop_unqual) + ? 1U + : 0U)) + << 0x1fU)) + | ((0x40000000U + & (((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cache_miss_resrv__DOT__dequeue_possible) + ? + (1U + & vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cache_miss_resrv__DOT__metadata_table + [vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr][0U]) + : + ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__snrq_pop_unqual) + ? + (1U + & (IData)( + (vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT____Vcellout__snp_req_queue__data_out + >> 0x1cU))) + : 0U)) + << 0x1eU)) + | ((((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__dfpq_pop_unqual) + ? 1U + : + (((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cache_miss_resrv__DOT__dequeue_possible) + & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__mrvq_rw_st0)) + ? 1U + : + (((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__reqq_pop_unqual) + & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__reqq_req_rw_st0)) + ? 1U + : 0U))) + << 0x1dU) + | ((((((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__dfpq_pop) + | (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__mrvq_pop)) + | (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__reqq_pop)) + | (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__snrq_pop)) + << 0x1cU) + | ((0xffffffcU + & (((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__dfpq_pop_unqual) + ? + (0x3ffffffU + & vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT____Vcellout__dfp_queue__data_out[4U]) + : + ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cache_miss_resrv__DOT__dequeue_possible) + ? + ((0x19fU + >= + (0x1ffU + & ((IData)(0x1aU) + * (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr)))) + ? + (0x3ffffffU + & (((0U + == + (0x1fU + & ((IData)(0x1aU) + * (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr)))) + ? 0U + : + (vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cache_miss_resrv__DOT__addr_table[ + ((IData)(1U) + + + (0xfU + & (((IData)(0x1aU) + * (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr)) + >> 5U)))] + << + ((IData)(0x20U) + - + (0x1fU + & ((IData)(0x1aU) + * (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr)))))) + | (vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cache_miss_resrv__DOT__addr_table[ + (0xfU + & (((IData)(0x1aU) + * (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr)) + >> 5U))] + >> + (0x1fU + & ((IData)(0x1aU) + * (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr)))))) + : 0U) + : + ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__reqq_pop_unqual) + ? + (0x3ffffffU + & (vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__reqq_req_addr_st0 + >> 4U)) + : + ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__snrq_pop_unqual) + ? + (0x3ffffffU + & (IData)( + (vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT____Vcellout__snp_req_queue__data_out + >> 0x1dU))) + : 0U)))) + << 2U)) + | (3U + & ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__reqq_pop_unqual) + ? + (3U + & vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__reqq_req_addr_st0) + : + ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cache_miss_resrv__DOT__dequeue_possible) + ? + (3U + & ((vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cache_miss_resrv__DOT__metadata_table + [vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr][1U] + << 0x1eU) + | (vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cache_miss_resrv__DOT__metadata_table + [vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr][0U] + >> 2U))) + : 0U)))))))))) + << 0x20U) + | (QData)((IData)( + ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cache_miss_resrv__DOT__dequeue_possible) + ? + ((vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cache_miss_resrv__DOT__metadata_table + [vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr][2U] + << 0xbU) + | (vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cache_miss_resrv__DOT__metadata_table + [vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr][1U] + >> 0x15U)) + : + ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__reqq_pop_unqual) + ? + (((0U + == + (0x1fU + & ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__core_req_arb__DOT__qual_request_index) + << 5U))) + ? 0U + : + (vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__core_req_arb__DOT__use_per_writedata[ + ((IData)(1U) + + + (3U + & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__core_req_arb__DOT__qual_request_index)))] + << + ((IData)(0x20U) + - + (0x1fU + & ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__core_req_arb__DOT__qual_request_index) + << 5U))))) + | (vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__core_req_arb__DOT__use_per_writedata[ + (3U + & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__core_req_arb__DOT__qual_request_index))] + >> + (0x1fU + & ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__core_req_arb__DOT__qual_request_index) + << 5U)))) + : 0U))))) + >> 0x20U)) + << 0x12U))); + __Vtemp147[7U] = (0x3ffffU & ((IData)(((((QData)((IData)( + ((0x80000000U + & (((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cache_miss_resrv__DOT__dequeue_possible) + ? + (1U + & (vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cache_miss_resrv__DOT__metadata_table + [vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr][0U] + >> 1U)) + : + ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__snrq_pop_unqual) + ? 1U + : 0U)) + << 0x1fU)) + | ((0x40000000U + & (((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cache_miss_resrv__DOT__dequeue_possible) + ? + (1U + & vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cache_miss_resrv__DOT__metadata_table + [vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr][0U]) + : + ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__snrq_pop_unqual) + ? + (1U + & (IData)( + (vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT____Vcellout__snp_req_queue__data_out + >> 0x1cU))) + : 0U)) + << 0x1eU)) + | ((((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__dfpq_pop_unqual) + ? 1U + : + (((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cache_miss_resrv__DOT__dequeue_possible) + & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__mrvq_rw_st0)) + ? 1U + : + (((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__reqq_pop_unqual) + & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__reqq_req_rw_st0)) + ? 1U + : 0U))) + << 0x1dU) + | ((((((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__dfpq_pop) + | (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__mrvq_pop)) + | (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__reqq_pop)) + | (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__snrq_pop)) + << 0x1cU) + | ((0xffffffcU + & (((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__dfpq_pop_unqual) + ? + (0x3ffffffU + & vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT____Vcellout__dfp_queue__data_out[4U]) + : + ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cache_miss_resrv__DOT__dequeue_possible) + ? + ((0x19fU + >= + (0x1ffU + & ((IData)(0x1aU) + * (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr)))) + ? + (0x3ffffffU + & (((0U + == + (0x1fU + & ((IData)(0x1aU) + * (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr)))) + ? 0U + : + (vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cache_miss_resrv__DOT__addr_table[ + ((IData)(1U) + + + (0xfU + & (((IData)(0x1aU) + * (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr)) + >> 5U)))] + << + ((IData)(0x20U) + - + (0x1fU + & ((IData)(0x1aU) + * (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr)))))) + | (vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cache_miss_resrv__DOT__addr_table[ + (0xfU + & (((IData)(0x1aU) + * (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr)) + >> 5U))] + >> + (0x1fU + & ((IData)(0x1aU) + * (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr)))))) + : 0U) + : + ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__reqq_pop_unqual) + ? + (0x3ffffffU + & (vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__reqq_req_addr_st0 + >> 4U)) + : + ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__snrq_pop_unqual) + ? + (0x3ffffffU + & (IData)( + (vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT____Vcellout__snp_req_queue__data_out + >> 0x1dU))) + : 0U)))) + << 2U)) + | (3U + & ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__reqq_pop_unqual) + ? + (3U + & vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__reqq_req_addr_st0) + : + ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cache_miss_resrv__DOT__dequeue_possible) + ? + (3U + & ((vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cache_miss_resrv__DOT__metadata_table + [vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr][1U] + << 0x1eU) + | (vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cache_miss_resrv__DOT__metadata_table + [vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr][0U] + >> 2U))) + : 0U)))))))))) + << 0x20U) + | (QData)((IData)( + ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cache_miss_resrv__DOT__dequeue_possible) + ? + ((vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cache_miss_resrv__DOT__metadata_table + [vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr][2U] + << 0xbU) + | (vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cache_miss_resrv__DOT__metadata_table + [vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr][1U] + >> 0x15U)) + : + ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__reqq_pop_unqual) + ? + (((0U + == + (0x1fU + & ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__core_req_arb__DOT__qual_request_index) + << 5U))) + ? 0U + : + (vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__core_req_arb__DOT__use_per_writedata[ + ((IData)(1U) + + + (3U + & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__core_req_arb__DOT__qual_request_index)))] + << + ((IData)(0x20U) + - + (0x1fU + & ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__core_req_arb__DOT__qual_request_index) + << 5U))))) + | (vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__core_req_arb__DOT__use_per_writedata[ + (3U + & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__core_req_arb__DOT__qual_request_index))] + >> + (0x1fU + & ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__core_req_arb__DOT__qual_request_index) + << 5U)))) + : 0U))))) + >> 0x20U)) + >> 0xeU)); + vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT____Vcellinp__s0_1_c0__in[0U] + = ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__dfpq_pop_unqual) + ? vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT____Vcellout__dfp_queue__data_out[0U] + : 0x39U); + vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT____Vcellinp__s0_1_c0__in[1U] + = ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__dfpq_pop_unqual) + ? vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT____Vcellout__dfp_queue__data_out[1U] + : 0U); + vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT____Vcellinp__s0_1_c0__in[2U] + = ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__dfpq_pop_unqual) + ? vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT____Vcellout__dfp_queue__data_out[2U] + : 0U); + vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT____Vcellinp__s0_1_c0__in[3U] + = ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__dfpq_pop_unqual) + ? vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT____Vcellout__dfp_queue__data_out[3U] + : 0U); + vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT____Vcellinp__s0_1_c0__in[4U] + = __Vtemp146[4U]; + vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT____Vcellinp__s0_1_c0__in[5U] + = __Vtemp147[5U]; + vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT____Vcellinp__s0_1_c0__in[6U] + = __Vtemp147[6U]; + vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT____Vcellinp__s0_1_c0__in[7U] + = ((0xfffc0000U & ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cache_miss_resrv__DOT__dequeue_possible) + << 0x12U)) | __Vtemp147[7U]); + vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__miss_st1e + = (((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__tag_data_access__DOT__real_miss) + | (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__tag_data_access__DOT__snoop_hit_no_pending)) + | (((((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__force_request_miss_st1e) + & (~ vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__is_snp_st1 + [0U])) & (~ vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__is_fill_st1 + [0U])) & vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__valid_st1 + [0U]) & (~ (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__tag_data_access__DOT__real_miss)))); + vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__cache_miss_resrv__DOT__increment_head + = ((~ (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__miss_add)) + & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__miss_add_is_mrvq)); + vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__cache_miss_resrv__DOT__mrvq_push + = (((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__miss_add) + & (0x10U != (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__cache_miss_resrv__DOT__size))) + & (~ (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__miss_add_is_mrvq))); + vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__dfp_queue__DOT__reading + = ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__dfpq_pop) + & (~ (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__dfp_queue__DOT__genblk3__DOT__genblk2__DOT__empty_r))); + vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__snp_req_queue__DOT__reading + = ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__snrq_pop) + & (~ (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__snp_req_queue__DOT__genblk3__DOT__genblk2__DOT__empty_r))); + vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__cache_miss_resrv__DOT__mrvq_pop + = ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__mrvq_pop) + & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__cache_miss_resrv__DOT__dequeue_possible)); + __Vtemp160[4U] = ((0xfffffffeU & ((IData)(((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__cache_miss_resrv__DOT__dequeue_possible) + ? ( + (VL_ULL(0x1ffffffffff80) + & (((QData)((IData)( + vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__cache_miss_resrv__DOT__metadata_table + [vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr][2U])) + << 0x3eU) + | (((QData)((IData)( + vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__cache_miss_resrv__DOT__metadata_table + [vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr][1U])) + << 0x1eU) + | (VL_ULL(0x3fffffffffffff80) + & ((QData)((IData)( + vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__cache_miss_resrv__DOT__metadata_table + [vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr][0U])) + >> 2U))))) + | (QData)((IData)( + (((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__mrvq_rw_st0) + << 6U) + | ((0x3cU + & ((vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__cache_miss_resrv__DOT__metadata_table + [vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr][1U] + << 0x1eU) + | (0x3ffffffcU + & (vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__cache_miss_resrv__DOT__metadata_table + [vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr][0U] + >> 2U)))) + | (3U + & ((vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__cache_miss_resrv__DOT__metadata_table + [vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr][2U] + << 0xdU) + | (vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__cache_miss_resrv__DOT__metadata_table + [vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr][1U] + >> 0x13U)))))))) + : ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__reqq_pop_unqual) + ? + ((vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__core_req_arb__DOT__use_per_tag + << 7U) + | (QData)((IData)( + (((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__reqq_req_rw_st0) + << 6U) + | ((0x3cU + & (((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__core_req_arb__DOT__use_per_byteen) + >> + (0xfU + & ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__core_req_arb__DOT__qual_request_index) + << 2U))) + << 2U)) + | (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__core_req_arb__DOT__qual_request_index)))))) + : + ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__snrq_pop_unqual) + ? + ((QData)((IData)( + (0xfffffffU + & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT____Vcellout__snp_req_queue__data_out)))) + << 7U) + : VL_ULL(0))))) + << 1U)) | (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__dfpq_pop_unqual)); + __Vtemp160[5U] = ((1U & ((IData)(((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__cache_miss_resrv__DOT__dequeue_possible) + ? ((VL_ULL(0x1ffffffffff80) + & (((QData)((IData)( + vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__cache_miss_resrv__DOT__metadata_table + [vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr][2U])) + << 0x3eU) + | (((QData)((IData)( + vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__cache_miss_resrv__DOT__metadata_table + [vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr][1U])) + << 0x1eU) + | (VL_ULL(0x3fffffffffffff80) + & ((QData)((IData)( + vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__cache_miss_resrv__DOT__metadata_table + [vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr][0U])) + >> 2U))))) + | (QData)((IData)( + (((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__mrvq_rw_st0) + << 6U) + | ((0x3cU + & ((vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__cache_miss_resrv__DOT__metadata_table + [vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr][1U] + << 0x1eU) + | (0x3ffffffcU + & (vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__cache_miss_resrv__DOT__metadata_table + [vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr][0U] + >> 2U)))) + | (3U + & ((vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__cache_miss_resrv__DOT__metadata_table + [vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr][2U] + << 0xdU) + | (vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__cache_miss_resrv__DOT__metadata_table + [vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr][1U] + >> 0x13U)))))))) + : ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__reqq_pop_unqual) + ? ((vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__core_req_arb__DOT__use_per_tag + << 7U) + | (QData)((IData)( + (((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__reqq_req_rw_st0) + << 6U) + | ((0x3cU + & (((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__core_req_arb__DOT__use_per_byteen) + >> + (0xfU + & ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__core_req_arb__DOT__qual_request_index) + << 2U))) + << 2U)) + | (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__core_req_arb__DOT__qual_request_index)))))) + : ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__snrq_pop_unqual) + ? ((QData)((IData)( + (0xfffffffU + & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT____Vcellout__snp_req_queue__data_out)))) + << 7U) + : VL_ULL(0))))) + >> 0x1fU)) | (0xfffffffeU + & ((IData)( + (((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__cache_miss_resrv__DOT__dequeue_possible) + ? + ((VL_ULL(0x1ffffffffff80) + & (((QData)((IData)( + vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__cache_miss_resrv__DOT__metadata_table + [vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr][2U])) + << 0x3eU) + | (((QData)((IData)( + vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__cache_miss_resrv__DOT__metadata_table + [vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr][1U])) + << 0x1eU) + | (VL_ULL(0x3fffffffffffff80) + & ((QData)((IData)( + vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__cache_miss_resrv__DOT__metadata_table + [vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr][0U])) + >> 2U))))) + | (QData)((IData)( + (((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__mrvq_rw_st0) + << 6U) + | ((0x3cU + & ((vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__cache_miss_resrv__DOT__metadata_table + [vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr][1U] + << 0x1eU) + | (0x3ffffffcU + & (vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__cache_miss_resrv__DOT__metadata_table + [vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr][0U] + >> 2U)))) + | (3U + & ((vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__cache_miss_resrv__DOT__metadata_table + [vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr][2U] + << 0xdU) + | (vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__cache_miss_resrv__DOT__metadata_table + [vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr][1U] + >> 0x13U)))))))) + : + ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__reqq_pop_unqual) + ? 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1U + : + (((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__cache_miss_resrv__DOT__dequeue_possible) + & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__mrvq_rw_st0)) + ? 1U + : + (((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__reqq_pop_unqual) + & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__reqq_req_rw_st0)) + ? 1U + : 0U))) + << 0x1dU) + | ((((((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__dfpq_pop) + | (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__mrvq_pop)) + | (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__reqq_pop)) + | (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__snrq_pop)) + << 0x1cU) + | ((0xffffffcU + & (((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__dfpq_pop_unqual) + ? + (0x3ffffffU + & vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT____Vcellout__dfp_queue__data_out[4U]) + : + ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__cache_miss_resrv__DOT__dequeue_possible) + ? + ((0x19fU + >= + (0x1ffU + & ((IData)(0x1aU) + * (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr)))) + ? + (0x3ffffffU + & (((0U + == + (0x1fU + & ((IData)(0x1aU) + * (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr)))) + ? 0U + : + (vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__cache_miss_resrv__DOT__addr_table[ + ((IData)(1U) + + + (0xfU + & (((IData)(0x1aU) + * (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr)) + >> 5U)))] + << + ((IData)(0x20U) + - + (0x1fU + & ((IData)(0x1aU) + * (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr)))))) + | (vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__cache_miss_resrv__DOT__addr_table[ + (0xfU + & (((IData)(0x1aU) + * (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr)) + >> 5U))] + >> + (0x1fU + & ((IData)(0x1aU) + * (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr)))))) + : 0U) + : + ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__reqq_pop_unqual) + ? + (0x3ffffffU + & (vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__reqq_req_addr_st0 + >> 4U)) + : + ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__snrq_pop_unqual) + ? + (0x3ffffffU + & (IData)( + (vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT____Vcellout__snp_req_queue__data_out + >> 0x1dU))) + : 0U)))) + << 2U)) + | (3U + & ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__reqq_pop_unqual) + ? + (3U + & vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__reqq_req_addr_st0) + : + ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__cache_miss_resrv__DOT__dequeue_possible) + ? + (3U + & ((vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__cache_miss_resrv__DOT__metadata_table + [vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr][1U] + << 0x1eU) + | (vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__cache_miss_resrv__DOT__metadata_table + [vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr][0U] + >> 2U))) + : 0U)))))))))) + << 0x20U) + | (QData)((IData)( + ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__cache_miss_resrv__DOT__dequeue_possible) + ? + ((vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__cache_miss_resrv__DOT__metadata_table + [vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr][2U] + << 0xbU) + | (vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__cache_miss_resrv__DOT__metadata_table + [vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr][1U] + >> 0x15U)) + : + ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__reqq_pop_unqual) + ? + (((0U + == + (0x1fU + & ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__core_req_arb__DOT__qual_request_index) + << 5U))) + ? 0U + : + (vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__core_req_arb__DOT__use_per_writedata[ + ((IData)(1U) + + + (3U + & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__core_req_arb__DOT__qual_request_index)))] + << + ((IData)(0x20U) + - + (0x1fU + & ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__core_req_arb__DOT__qual_request_index) + << 5U))))) + | (vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__core_req_arb__DOT__use_per_writedata[ + (3U + & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__core_req_arb__DOT__qual_request_index))] + >> + (0x1fU + & ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__core_req_arb__DOT__qual_request_index) + << 5U)))) + : 0U)))))) + >> 0xeU)) | (0xfffc0000U + & ((IData)( + ((((QData)((IData)( + ((0x80000000U + & (((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__cache_miss_resrv__DOT__dequeue_possible) + ? + (1U + & (vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__cache_miss_resrv__DOT__metadata_table + [vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr][0U] + >> 1U)) + : + ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__snrq_pop_unqual) + ? 1U + : 0U)) + << 0x1fU)) + | ((0x40000000U + & (((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__cache_miss_resrv__DOT__dequeue_possible) + ? + (1U + & vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__cache_miss_resrv__DOT__metadata_table + [vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr][0U]) + : + ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__snrq_pop_unqual) + ? + (1U + & (IData)( + (vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT____Vcellout__snp_req_queue__data_out + >> 0x1cU))) + : 0U)) + << 0x1eU)) + | ((((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__dfpq_pop_unqual) + ? 1U + : + (((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__cache_miss_resrv__DOT__dequeue_possible) + & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__mrvq_rw_st0)) + ? 1U + : + (((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__reqq_pop_unqual) + & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__reqq_req_rw_st0)) + ? 1U + : 0U))) + << 0x1dU) + | ((((((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__dfpq_pop) + | (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__mrvq_pop)) + | (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__reqq_pop)) + | (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__snrq_pop)) + << 0x1cU) + | ((0xffffffcU + & (((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__dfpq_pop_unqual) + ? + (0x3ffffffU + & vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT____Vcellout__dfp_queue__data_out[4U]) + : + ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__cache_miss_resrv__DOT__dequeue_possible) + ? + ((0x19fU + >= + (0x1ffU + & ((IData)(0x1aU) + * (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr)))) + ? + (0x3ffffffU + & (((0U + == + (0x1fU + & ((IData)(0x1aU) + * (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr)))) + ? 0U + : + (vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__cache_miss_resrv__DOT__addr_table[ + ((IData)(1U) + + + (0xfU + & (((IData)(0x1aU) + * (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr)) + >> 5U)))] + << + ((IData)(0x20U) + - + (0x1fU + & ((IData)(0x1aU) + * (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr)))))) + | (vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__cache_miss_resrv__DOT__addr_table[ + (0xfU + & (((IData)(0x1aU) + * (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr)) + >> 5U))] + >> + (0x1fU + & ((IData)(0x1aU) + * (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr)))))) + : 0U) + : + ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__reqq_pop_unqual) + ? + (0x3ffffffU + & (vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__reqq_req_addr_st0 + >> 4U)) + : + ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__snrq_pop_unqual) + ? + (0x3ffffffU + & (IData)( + (vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT____Vcellout__snp_req_queue__data_out + >> 0x1dU))) + : 0U)))) + << 2U)) + | (3U + & ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__reqq_pop_unqual) + ? + (3U + & vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__reqq_req_addr_st0) + : + ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__cache_miss_resrv__DOT__dequeue_possible) + ? + (3U + & ((vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__cache_miss_resrv__DOT__metadata_table + [vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr][1U] + << 0x1eU) + | (vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__cache_miss_resrv__DOT__metadata_table + [vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr][0U] + >> 2U))) + : 0U)))))))))) + << 0x20U) + | (QData)((IData)( + ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__cache_miss_resrv__DOT__dequeue_possible) + ? + ((vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__cache_miss_resrv__DOT__metadata_table + [vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr][2U] + << 0xbU) + | (vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__cache_miss_resrv__DOT__metadata_table + [vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr][1U] + >> 0x15U)) + : + ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__reqq_pop_unqual) + ? + (((0U + == + (0x1fU + & ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__core_req_arb__DOT__qual_request_index) + << 5U))) + ? 0U + : + (vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__core_req_arb__DOT__use_per_writedata[ + ((IData)(1U) + + + (3U + & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__core_req_arb__DOT__qual_request_index)))] + << + ((IData)(0x20U) + - + (0x1fU + & ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__core_req_arb__DOT__qual_request_index) + << 5U))))) + | (vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__core_req_arb__DOT__use_per_writedata[ + (3U + & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__core_req_arb__DOT__qual_request_index))] + >> + (0x1fU + & ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__core_req_arb__DOT__qual_request_index) + << 5U)))) + : 0U))))) + >> 0x20U)) + << 0x12U))); + __Vtemp161[7U] = (0x3ffffU & ((IData)(((((QData)((IData)( + ((0x80000000U + & (((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__cache_miss_resrv__DOT__dequeue_possible) + ? + (1U + & (vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__cache_miss_resrv__DOT__metadata_table + [vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr][0U] + >> 1U)) + : + ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__snrq_pop_unqual) + ? 1U + : 0U)) + << 0x1fU)) + | ((0x40000000U + & (((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__cache_miss_resrv__DOT__dequeue_possible) + ? + (1U + & vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__cache_miss_resrv__DOT__metadata_table + [vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr][0U]) + : + ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__snrq_pop_unqual) + ? + (1U + & (IData)( + (vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT____Vcellout__snp_req_queue__data_out + >> 0x1cU))) + : 0U)) + << 0x1eU)) + | ((((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__dfpq_pop_unqual) + ? 1U + : + (((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__cache_miss_resrv__DOT__dequeue_possible) + & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__mrvq_rw_st0)) + ? 1U + : + (((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__reqq_pop_unqual) + & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__reqq_req_rw_st0)) + ? 1U + : 0U))) + << 0x1dU) + | ((((((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__dfpq_pop) + | (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__mrvq_pop)) + | (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__reqq_pop)) + | (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__snrq_pop)) + << 0x1cU) + | ((0xffffffcU + & (((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__dfpq_pop_unqual) + ? + (0x3ffffffU + & vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT____Vcellout__dfp_queue__data_out[4U]) + : + ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__cache_miss_resrv__DOT__dequeue_possible) + ? + ((0x19fU + >= + (0x1ffU + & ((IData)(0x1aU) + * (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr)))) + ? + (0x3ffffffU + & (((0U + == + (0x1fU + & ((IData)(0x1aU) + * (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr)))) + ? 0U + : + (vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__cache_miss_resrv__DOT__addr_table[ + ((IData)(1U) + + + (0xfU + & (((IData)(0x1aU) + * (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr)) + >> 5U)))] + << + ((IData)(0x20U) + - + (0x1fU + & ((IData)(0x1aU) + * (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr)))))) + | (vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__cache_miss_resrv__DOT__addr_table[ + (0xfU + & (((IData)(0x1aU) + * (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr)) + >> 5U))] + >> + (0x1fU + & ((IData)(0x1aU) + * (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr)))))) + : 0U) + : + ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__reqq_pop_unqual) + ? + (0x3ffffffU + & (vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__reqq_req_addr_st0 + >> 4U)) + : + ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__snrq_pop_unqual) + ? + (0x3ffffffU + & (IData)( + (vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT____Vcellout__snp_req_queue__data_out + >> 0x1dU))) + : 0U)))) + << 2U)) + | (3U + & ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__reqq_pop_unqual) + ? + (3U + & vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__reqq_req_addr_st0) + : + ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__cache_miss_resrv__DOT__dequeue_possible) + ? + (3U + & ((vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__cache_miss_resrv__DOT__metadata_table + [vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr][1U] + << 0x1eU) + | (vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__cache_miss_resrv__DOT__metadata_table + [vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr][0U] + >> 2U))) + : 0U)))))))))) + << 0x20U) + | (QData)((IData)( + ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__cache_miss_resrv__DOT__dequeue_possible) + ? + ((vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__cache_miss_resrv__DOT__metadata_table + [vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr][2U] + << 0xbU) + | (vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__cache_miss_resrv__DOT__metadata_table + [vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr][1U] + >> 0x15U)) + : + ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__reqq_pop_unqual) + ? + (((0U + == + (0x1fU + & ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__core_req_arb__DOT__qual_request_index) + << 5U))) + ? 0U + : + (vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__core_req_arb__DOT__use_per_writedata[ + ((IData)(1U) + + + (3U + & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__core_req_arb__DOT__qual_request_index)))] + << + ((IData)(0x20U) + - + (0x1fU + & ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__core_req_arb__DOT__qual_request_index) + << 5U))))) + | (vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__core_req_arb__DOT__use_per_writedata[ + (3U + & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__core_req_arb__DOT__qual_request_index))] + >> + (0x1fU + & ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__core_req_arb__DOT__qual_request_index) + << 5U)))) + : 0U))))) + >> 0x20U)) + >> 0xeU)); + vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT____Vcellinp__s0_1_c0__in[0U] + = ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__dfpq_pop_unqual) + ? vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT____Vcellout__dfp_queue__data_out[0U] + : 0x39U); + vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT____Vcellinp__s0_1_c0__in[1U] + = ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__dfpq_pop_unqual) + ? vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT____Vcellout__dfp_queue__data_out[1U] + : 0U); + vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT____Vcellinp__s0_1_c0__in[2U] + = ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__dfpq_pop_unqual) + ? vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT____Vcellout__dfp_queue__data_out[2U] + : 0U); + vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT____Vcellinp__s0_1_c0__in[3U] + = ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__dfpq_pop_unqual) + ? vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT____Vcellout__dfp_queue__data_out[3U] + : 0U); + vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT____Vcellinp__s0_1_c0__in[4U] + = __Vtemp160[4U]; + vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT____Vcellinp__s0_1_c0__in[5U] + = __Vtemp161[5U]; + vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT____Vcellinp__s0_1_c0__in[6U] + = __Vtemp161[6U]; + vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT____Vcellinp__s0_1_c0__in[7U] + = ((0xfffc0000U & ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__cache_miss_resrv__DOT__dequeue_possible) + << 0x12U)) | __Vtemp161[7U]); + vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__miss_st1e + = (((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__tag_data_access__DOT__real_miss) + | (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__tag_data_access__DOT__snoop_hit_no_pending)) + | (((((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__force_request_miss_st1e) + & (~ vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__is_snp_st1 + [0U])) & (~ vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__is_fill_st1 + [0U])) & vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__valid_st1 + [0U]) & (~ (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__tag_data_access__DOT__real_miss)))); + vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__cache_miss_resrv__DOT__increment_head + = ((~ (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__miss_add)) + & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__miss_add_is_mrvq)); + vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__cache_miss_resrv__DOT__mrvq_push + = (((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__miss_add) + & (0x10U != (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__cache_miss_resrv__DOT__size))) + & (~ (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__miss_add_is_mrvq))); + vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__dfp_queue__DOT__reading + = ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__dfpq_pop) + & (~ (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__dfp_queue__DOT__genblk3__DOT__genblk2__DOT__empty_r))); + vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__snp_req_queue__DOT__reading + = ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__snrq_pop) + & (~ (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__snp_req_queue__DOT__genblk3__DOT__genblk2__DOT__empty_r))); + vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__cache_miss_resrv__DOT__mrvq_pop + = ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__mrvq_pop) + & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__cache_miss_resrv__DOT__dequeue_possible)); + __Vtemp174[4U] = ((0xfffffffeU & ((IData)(((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__cache_miss_resrv__DOT__dequeue_possible) + ? ( + (VL_ULL(0x1ffffffffff80) + & (((QData)((IData)( + vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__cache_miss_resrv__DOT__metadata_table + [vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr][2U])) + << 0x3eU) + | (((QData)((IData)( + vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__cache_miss_resrv__DOT__metadata_table + [vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr][1U])) + << 0x1eU) + | (VL_ULL(0x3fffffffffffff80) + & ((QData)((IData)( + vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__cache_miss_resrv__DOT__metadata_table + [vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr][0U])) + >> 2U))))) + | (QData)((IData)( + (((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__mrvq_rw_st0) + << 6U) + | ((0x3cU + & ((vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__cache_miss_resrv__DOT__metadata_table + [vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr][1U] + << 0x1eU) + | (0x3ffffffcU + & (vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__cache_miss_resrv__DOT__metadata_table + [vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr][0U] + >> 2U)))) + | (3U + & ((vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__cache_miss_resrv__DOT__metadata_table + [vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr][2U] + << 0xdU) + | (vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__cache_miss_resrv__DOT__metadata_table + [vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr][1U] + >> 0x13U)))))))) + : ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__reqq_pop_unqual) + ? + ((vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__core_req_arb__DOT__use_per_tag + << 7U) + | (QData)((IData)( + (((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__reqq_req_rw_st0) + << 6U) + | ((0x3cU + & (((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__core_req_arb__DOT__use_per_byteen) + >> + (0xfU + & ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__core_req_arb__DOT__qual_request_index) + << 2U))) + << 2U)) + | (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__core_req_arb__DOT__qual_request_index)))))) + : + ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__snrq_pop_unqual) + ? + ((QData)((IData)( + (0xfffffffU + & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT____Vcellout__snp_req_queue__data_out)))) + << 7U) + : VL_ULL(0))))) + << 1U)) | (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__dfpq_pop_unqual)); + __Vtemp174[5U] = ((1U & ((IData)(((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__cache_miss_resrv__DOT__dequeue_possible) + ? ((VL_ULL(0x1ffffffffff80) + & (((QData)((IData)( + vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__cache_miss_resrv__DOT__metadata_table + [vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr][2U])) + << 0x3eU) + | (((QData)((IData)( + vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__cache_miss_resrv__DOT__metadata_table + [vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr][1U])) + << 0x1eU) + | (VL_ULL(0x3fffffffffffff80) + & ((QData)((IData)( + vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__cache_miss_resrv__DOT__metadata_table + [vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr][0U])) + >> 2U))))) + | (QData)((IData)( + (((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__mrvq_rw_st0) + << 6U) + | ((0x3cU + & ((vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__cache_miss_resrv__DOT__metadata_table + [vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr][1U] + << 0x1eU) + | (0x3ffffffcU + & (vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__cache_miss_resrv__DOT__metadata_table + [vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr][0U] + >> 2U)))) + | (3U + & ((vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__cache_miss_resrv__DOT__metadata_table + [vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr][2U] + << 0xdU) + | (vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__cache_miss_resrv__DOT__metadata_table + [vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr][1U] + >> 0x13U)))))))) + : ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__reqq_pop_unqual) + ? ((vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__core_req_arb__DOT__use_per_tag + << 7U) + | (QData)((IData)( + (((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__reqq_req_rw_st0) + << 6U) + | ((0x3cU + & (((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__core_req_arb__DOT__use_per_byteen) + >> + (0xfU + & ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__core_req_arb__DOT__qual_request_index) + << 2U))) + << 2U)) + | (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__core_req_arb__DOT__qual_request_index)))))) + : ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__snrq_pop_unqual) + ? ((QData)((IData)( + (0xfffffffU + & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT____Vcellout__snp_req_queue__data_out)))) + << 7U) + : VL_ULL(0))))) + >> 0x1fU)) | (0xfffffffeU + & ((IData)( + (((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__cache_miss_resrv__DOT__dequeue_possible) + ? + ((VL_ULL(0x1ffffffffff80) + & (((QData)((IData)( + vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__cache_miss_resrv__DOT__metadata_table + [vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr][2U])) + << 0x3eU) + | (((QData)((IData)( + vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__cache_miss_resrv__DOT__metadata_table + [vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr][1U])) + << 0x1eU) + | (VL_ULL(0x3fffffffffffff80) + & ((QData)((IData)( + vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__cache_miss_resrv__DOT__metadata_table + [vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr][0U])) + >> 2U))))) + | (QData)((IData)( + (((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__mrvq_rw_st0) + << 6U) + | ((0x3cU + & ((vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__cache_miss_resrv__DOT__metadata_table + [vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr][1U] + << 0x1eU) + | (0x3ffffffcU + & (vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__cache_miss_resrv__DOT__metadata_table + [vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr][0U] + >> 2U)))) + | (3U + & ((vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__cache_miss_resrv__DOT__metadata_table + [vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr][2U] + << 0xdU) + | (vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__cache_miss_resrv__DOT__metadata_table + [vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr][1U] + >> 0x13U)))))))) + : + ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__reqq_pop_unqual) + ? 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1U + : + (((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__cache_miss_resrv__DOT__dequeue_possible) + & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__mrvq_rw_st0)) + ? 1U + : + (((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__reqq_pop_unqual) + & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__reqq_req_rw_st0)) + ? 1U + : 0U))) + << 0x1dU) + | ((((((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__dfpq_pop) + | (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__mrvq_pop)) + | (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__reqq_pop)) + | (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__snrq_pop)) + << 0x1cU) + | ((0xffffffcU + & (((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__dfpq_pop_unqual) + ? + (0x3ffffffU + & vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT____Vcellout__dfp_queue__data_out[4U]) + : + ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__cache_miss_resrv__DOT__dequeue_possible) + ? + ((0x19fU + >= + (0x1ffU + & ((IData)(0x1aU) + * (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr)))) + ? + (0x3ffffffU + & (((0U + == + (0x1fU + & ((IData)(0x1aU) + * (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr)))) + ? 0U + : + (vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__cache_miss_resrv__DOT__addr_table[ + ((IData)(1U) + + + (0xfU + & (((IData)(0x1aU) + * (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr)) + >> 5U)))] + << + ((IData)(0x20U) + - + (0x1fU + & ((IData)(0x1aU) + * (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr)))))) + | (vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__cache_miss_resrv__DOT__addr_table[ + (0xfU + & (((IData)(0x1aU) + * (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr)) + >> 5U))] + >> + (0x1fU + & ((IData)(0x1aU) + * (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr)))))) + : 0U) + : + ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__reqq_pop_unqual) + ? + (0x3ffffffU + & (vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__reqq_req_addr_st0 + >> 4U)) + : + ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__snrq_pop_unqual) + ? + (0x3ffffffU + & (IData)( + (vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT____Vcellout__snp_req_queue__data_out + >> 0x1dU))) + : 0U)))) + << 2U)) + | (3U + & ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__reqq_pop_unqual) + ? + (3U + & vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__reqq_req_addr_st0) + : + ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__cache_miss_resrv__DOT__dequeue_possible) + ? + (3U + & ((vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__cache_miss_resrv__DOT__metadata_table + [vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr][1U] + << 0x1eU) + | (vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__cache_miss_resrv__DOT__metadata_table + [vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr][0U] + >> 2U))) + : 0U)))))))))) + << 0x20U) + | (QData)((IData)( + ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__cache_miss_resrv__DOT__dequeue_possible) + ? + ((vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__cache_miss_resrv__DOT__metadata_table + [vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr][2U] + << 0xbU) + | (vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__cache_miss_resrv__DOT__metadata_table + [vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr][1U] + >> 0x15U)) + : + ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__reqq_pop_unqual) + ? + (((0U + == + (0x1fU + & ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__core_req_arb__DOT__qual_request_index) + << 5U))) + ? 0U + : + (vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__core_req_arb__DOT__use_per_writedata[ + ((IData)(1U) + + + (3U + & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__core_req_arb__DOT__qual_request_index)))] + << + ((IData)(0x20U) + - + (0x1fU + & ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__core_req_arb__DOT__qual_request_index) + << 5U))))) + | (vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__core_req_arb__DOT__use_per_writedata[ + (3U + & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__core_req_arb__DOT__qual_request_index))] + >> + (0x1fU + & ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__core_req_arb__DOT__qual_request_index) + << 5U)))) + : 0U)))))) + >> 0xeU)) | (0xfffc0000U + & ((IData)( + ((((QData)((IData)( + ((0x80000000U + & (((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__cache_miss_resrv__DOT__dequeue_possible) + ? + (1U + & (vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__cache_miss_resrv__DOT__metadata_table + [vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr][0U] + >> 1U)) + : + ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__snrq_pop_unqual) + ? 1U + : 0U)) + << 0x1fU)) + | ((0x40000000U + & (((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__cache_miss_resrv__DOT__dequeue_possible) + ? + (1U + & vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__cache_miss_resrv__DOT__metadata_table + [vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr][0U]) + : + ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__snrq_pop_unqual) + ? + (1U + & (IData)( + (vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT____Vcellout__snp_req_queue__data_out + >> 0x1cU))) + : 0U)) + << 0x1eU)) + | ((((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__dfpq_pop_unqual) + ? 1U + : + (((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__cache_miss_resrv__DOT__dequeue_possible) + & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__mrvq_rw_st0)) + ? 1U + : + (((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__reqq_pop_unqual) + & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__reqq_req_rw_st0)) + ? 1U + : 0U))) + << 0x1dU) + | ((((((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__dfpq_pop) + | (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__mrvq_pop)) + | (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__reqq_pop)) + | (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__snrq_pop)) + << 0x1cU) + | ((0xffffffcU + & (((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__dfpq_pop_unqual) + ? + (0x3ffffffU + & vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT____Vcellout__dfp_queue__data_out[4U]) + : + ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__cache_miss_resrv__DOT__dequeue_possible) + ? + ((0x19fU + >= + (0x1ffU + & ((IData)(0x1aU) + * (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr)))) + ? + (0x3ffffffU + & (((0U + == + (0x1fU + & ((IData)(0x1aU) + * (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr)))) + ? 0U + : + (vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__cache_miss_resrv__DOT__addr_table[ + ((IData)(1U) + + + (0xfU + & (((IData)(0x1aU) + * (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr)) + >> 5U)))] + << + ((IData)(0x20U) + - + (0x1fU + & ((IData)(0x1aU) + * (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr)))))) + | (vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__cache_miss_resrv__DOT__addr_table[ + (0xfU + & (((IData)(0x1aU) + * (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr)) + >> 5U))] + >> + (0x1fU + & ((IData)(0x1aU) + * (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr)))))) + : 0U) + : + ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__reqq_pop_unqual) + ? + (0x3ffffffU + & (vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__reqq_req_addr_st0 + >> 4U)) + : + ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__snrq_pop_unqual) + ? + (0x3ffffffU + & (IData)( + (vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT____Vcellout__snp_req_queue__data_out + >> 0x1dU))) + : 0U)))) + << 2U)) + | (3U + & ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__reqq_pop_unqual) + ? + (3U + & vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__reqq_req_addr_st0) + : + ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__cache_miss_resrv__DOT__dequeue_possible) + ? + (3U + & ((vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__cache_miss_resrv__DOT__metadata_table + [vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr][1U] + << 0x1eU) + | (vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__cache_miss_resrv__DOT__metadata_table + [vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr][0U] + >> 2U))) + : 0U)))))))))) + << 0x20U) + | (QData)((IData)( + ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__cache_miss_resrv__DOT__dequeue_possible) + ? + ((vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__cache_miss_resrv__DOT__metadata_table + [vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr][2U] + << 0xbU) + | (vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__cache_miss_resrv__DOT__metadata_table + [vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr][1U] + >> 0x15U)) + : + ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__reqq_pop_unqual) + ? + (((0U + == + (0x1fU + & ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__core_req_arb__DOT__qual_request_index) + << 5U))) + ? 0U + : + (vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__core_req_arb__DOT__use_per_writedata[ + ((IData)(1U) + + + (3U + & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__core_req_arb__DOT__qual_request_index)))] + << + ((IData)(0x20U) + - + (0x1fU + & ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__core_req_arb__DOT__qual_request_index) + << 5U))))) + | (vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__core_req_arb__DOT__use_per_writedata[ + (3U + & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__core_req_arb__DOT__qual_request_index))] + >> + (0x1fU + & ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__core_req_arb__DOT__qual_request_index) + << 5U)))) + : 0U))))) + >> 0x20U)) + << 0x12U))); + __Vtemp175[7U] = (0x3ffffU & ((IData)(((((QData)((IData)( + ((0x80000000U + & (((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__cache_miss_resrv__DOT__dequeue_possible) + ? + (1U + & (vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__cache_miss_resrv__DOT__metadata_table + [vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr][0U] + >> 1U)) + : + ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__snrq_pop_unqual) + ? 1U + : 0U)) + << 0x1fU)) + | ((0x40000000U + & (((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__cache_miss_resrv__DOT__dequeue_possible) + ? + (1U + & vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__cache_miss_resrv__DOT__metadata_table + [vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr][0U]) + : + ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__snrq_pop_unqual) + ? + (1U + & (IData)( + (vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT____Vcellout__snp_req_queue__data_out + >> 0x1cU))) + : 0U)) + << 0x1eU)) + | ((((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__dfpq_pop_unqual) + ? 1U + : + (((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__cache_miss_resrv__DOT__dequeue_possible) + & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__mrvq_rw_st0)) + ? 1U + : + (((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__reqq_pop_unqual) + & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__reqq_req_rw_st0)) + ? 1U + : 0U))) + << 0x1dU) + | ((((((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__dfpq_pop) + | (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__mrvq_pop)) + | (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__reqq_pop)) + | (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__snrq_pop)) + << 0x1cU) + | ((0xffffffcU + & (((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__dfpq_pop_unqual) + ? + (0x3ffffffU + & vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT____Vcellout__dfp_queue__data_out[4U]) + : + ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__cache_miss_resrv__DOT__dequeue_possible) + ? + ((0x19fU + >= + (0x1ffU + & ((IData)(0x1aU) + * (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr)))) + ? + (0x3ffffffU + & (((0U + == + (0x1fU + & ((IData)(0x1aU) + * (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr)))) + ? 0U + : + (vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__cache_miss_resrv__DOT__addr_table[ + ((IData)(1U) + + + (0xfU + & (((IData)(0x1aU) + * (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr)) + >> 5U)))] + << + ((IData)(0x20U) + - + (0x1fU + & ((IData)(0x1aU) + * (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr)))))) + | (vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__cache_miss_resrv__DOT__addr_table[ + (0xfU + & (((IData)(0x1aU) + * (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr)) + >> 5U))] + >> + (0x1fU + & ((IData)(0x1aU) + * (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr)))))) + : 0U) + : + ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__reqq_pop_unqual) + ? + (0x3ffffffU + & (vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__reqq_req_addr_st0 + >> 4U)) + : + ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__snrq_pop_unqual) + ? + (0x3ffffffU + & (IData)( + (vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT____Vcellout__snp_req_queue__data_out + >> 0x1dU))) + : 0U)))) + << 2U)) + | (3U + & ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__reqq_pop_unqual) + ? + (3U + & vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__reqq_req_addr_st0) + : + ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__cache_miss_resrv__DOT__dequeue_possible) + ? + (3U + & ((vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__cache_miss_resrv__DOT__metadata_table + [vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr][1U] + << 0x1eU) + | (vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__cache_miss_resrv__DOT__metadata_table + [vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr][0U] + >> 2U))) + : 0U)))))))))) + << 0x20U) + | (QData)((IData)( + ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__cache_miss_resrv__DOT__dequeue_possible) + ? + ((vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__cache_miss_resrv__DOT__metadata_table + [vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr][2U] + << 0xbU) + | (vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__cache_miss_resrv__DOT__metadata_table + [vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr][1U] + >> 0x15U)) + : + ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__reqq_pop_unqual) + ? + (((0U + == + (0x1fU + & ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__core_req_arb__DOT__qual_request_index) + << 5U))) + ? 0U + : + (vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__core_req_arb__DOT__use_per_writedata[ + ((IData)(1U) + + + (3U + & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__core_req_arb__DOT__qual_request_index)))] + << + ((IData)(0x20U) + - + (0x1fU + & ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__core_req_arb__DOT__qual_request_index) + << 5U))))) + | (vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__core_req_arb__DOT__use_per_writedata[ + (3U + & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__core_req_arb__DOT__qual_request_index))] + >> + (0x1fU + & ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__core_req_arb__DOT__qual_request_index) + << 5U)))) + : 0U))))) + >> 0x20U)) + >> 0xeU)); + vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT____Vcellinp__s0_1_c0__in[0U] + = ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__dfpq_pop_unqual) + ? vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT____Vcellout__dfp_queue__data_out[0U] + : 0x39U); + vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT____Vcellinp__s0_1_c0__in[1U] + = ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__dfpq_pop_unqual) + ? vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT____Vcellout__dfp_queue__data_out[1U] + : 0U); + vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT____Vcellinp__s0_1_c0__in[2U] + = ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__dfpq_pop_unqual) + ? vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT____Vcellout__dfp_queue__data_out[2U] + : 0U); + vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT____Vcellinp__s0_1_c0__in[3U] + = ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__dfpq_pop_unqual) + ? vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT____Vcellout__dfp_queue__data_out[3U] + : 0U); + vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT____Vcellinp__s0_1_c0__in[4U] + = __Vtemp174[4U]; + vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT____Vcellinp__s0_1_c0__in[5U] + = __Vtemp175[5U]; + vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT____Vcellinp__s0_1_c0__in[6U] + = __Vtemp175[6U]; + vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT____Vcellinp__s0_1_c0__in[7U] + = ((0xfffc0000U & ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__cache_miss_resrv__DOT__dequeue_possible) + << 0x12U)) | __Vtemp175[7U]); + vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__miss_st1e + = (((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__tag_data_access__DOT__real_miss) + | (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__tag_data_access__DOT__snoop_hit_no_pending)) + | (((((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__force_request_miss_st1e) + & (~ vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__is_snp_st1 + [0U])) & (~ vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__is_fill_st1 + [0U])) & vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__valid_st1 + [0U]) & (~ (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__tag_data_access__DOT__real_miss)))); + vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cache_miss_resrv__DOT__increment_head + = ((~ (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__miss_add)) + & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__miss_add_is_mrvq)); + vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cache_miss_resrv__DOT__mrvq_push + = (((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__miss_add) + & (0x10U != (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cache_miss_resrv__DOT__size))) + & (~ (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__miss_add_is_mrvq))); + vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__dfp_queue__DOT__reading + = ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__dfpq_pop) + & (~ (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__dfp_queue__DOT__genblk3__DOT__genblk2__DOT__empty_r))); + vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__snp_req_queue__DOT__reading + = ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__snrq_pop) + & (~ (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__snp_req_queue__DOT__genblk3__DOT__genblk2__DOT__empty_r))); + vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cache_miss_resrv__DOT__mrvq_pop + = ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__mrvq_pop) + & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cache_miss_resrv__DOT__dequeue_possible)); + __Vtemp188[4U] = ((0xfffffffeU & ((IData)(((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cache_miss_resrv__DOT__dequeue_possible) + ? ( + (VL_ULL(0x1ffffffffff80) + & (((QData)((IData)( + vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cache_miss_resrv__DOT__metadata_table + [vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr][2U])) + << 0x3eU) + | (((QData)((IData)( + vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cache_miss_resrv__DOT__metadata_table + [vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr][1U])) + << 0x1eU) + | (VL_ULL(0x3fffffffffffff80) + & ((QData)((IData)( + vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cache_miss_resrv__DOT__metadata_table + [vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr][0U])) + >> 2U))))) + | (QData)((IData)( + (((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__mrvq_rw_st0) + << 6U) + | ((0x3cU + & ((vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cache_miss_resrv__DOT__metadata_table + [vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr][1U] + << 0x1eU) + | (0x3ffffffcU + & (vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cache_miss_resrv__DOT__metadata_table + [vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr][0U] + >> 2U)))) + | (3U + & ((vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cache_miss_resrv__DOT__metadata_table + [vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr][2U] + << 0xdU) + | (vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cache_miss_resrv__DOT__metadata_table + [vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr][1U] + >> 0x13U)))))))) + : ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__reqq_pop_unqual) + ? + ((vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__core_req_arb__DOT__use_per_tag + << 7U) + | (QData)((IData)( + (((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__reqq_req_rw_st0) + << 6U) + | ((0x3cU + & (((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__core_req_arb__DOT__use_per_byteen) + >> + (0xfU + & ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__core_req_arb__DOT__qual_request_index) + << 2U))) + << 2U)) + | (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__core_req_arb__DOT__qual_request_index)))))) + : + ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__snrq_pop_unqual) + ? + ((QData)((IData)( + (0xfffffffU + & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT____Vcellout__snp_req_queue__data_out)))) + << 7U) + : VL_ULL(0))))) + << 1U)) | (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__dfpq_pop_unqual)); + __Vtemp188[5U] = ((1U & ((IData)(((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cache_miss_resrv__DOT__dequeue_possible) + ? ((VL_ULL(0x1ffffffffff80) + & (((QData)((IData)( + vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cache_miss_resrv__DOT__metadata_table + [vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr][2U])) + << 0x3eU) + | (((QData)((IData)( + vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cache_miss_resrv__DOT__metadata_table + [vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr][1U])) + << 0x1eU) + | (VL_ULL(0x3fffffffffffff80) + & ((QData)((IData)( + vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cache_miss_resrv__DOT__metadata_table + [vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr][0U])) + >> 2U))))) + | (QData)((IData)( + (((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__mrvq_rw_st0) + << 6U) + | ((0x3cU + & ((vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cache_miss_resrv__DOT__metadata_table + [vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr][1U] + << 0x1eU) + | (0x3ffffffcU + & (vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cache_miss_resrv__DOT__metadata_table + [vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr][0U] + >> 2U)))) + | (3U + & ((vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cache_miss_resrv__DOT__metadata_table + [vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr][2U] + << 0xdU) + | (vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cache_miss_resrv__DOT__metadata_table + [vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr][1U] + >> 0x13U)))))))) + : ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__reqq_pop_unqual) + ? ((vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__core_req_arb__DOT__use_per_tag + << 7U) + | (QData)((IData)( + (((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__reqq_req_rw_st0) + << 6U) + | ((0x3cU + & (((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__core_req_arb__DOT__use_per_byteen) + >> + (0xfU + & ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__core_req_arb__DOT__qual_request_index) + << 2U))) + << 2U)) + | (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__core_req_arb__DOT__qual_request_index)))))) + : ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__snrq_pop_unqual) + ? ((QData)((IData)( + (0xfffffffU + & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT____Vcellout__snp_req_queue__data_out)))) + << 7U) + : VL_ULL(0))))) + >> 0x1fU)) | (0xfffffffeU + & ((IData)( + (((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cache_miss_resrv__DOT__dequeue_possible) + ? + ((VL_ULL(0x1ffffffffff80) + & (((QData)((IData)( + vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cache_miss_resrv__DOT__metadata_table + [vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr][2U])) + << 0x3eU) + | (((QData)((IData)( + vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cache_miss_resrv__DOT__metadata_table + [vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr][1U])) + << 0x1eU) + | (VL_ULL(0x3fffffffffffff80) + & ((QData)((IData)( + vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cache_miss_resrv__DOT__metadata_table + [vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr][0U])) + >> 2U))))) + | (QData)((IData)( + (((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__mrvq_rw_st0) + << 6U) + | ((0x3cU + & ((vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cache_miss_resrv__DOT__metadata_table + [vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr][1U] + << 0x1eU) + | (0x3ffffffcU + & (vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cache_miss_resrv__DOT__metadata_table + [vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr][0U] + >> 2U)))) + | (3U + & ((vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cache_miss_resrv__DOT__metadata_table + [vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr][2U] + << 0xdU) + | (vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cache_miss_resrv__DOT__metadata_table + [vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr][1U] + >> 0x13U)))))))) + : + ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__reqq_pop_unqual) + ? + ((vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__core_req_arb__DOT__use_per_tag + << 7U) + | (QData)((IData)( + (((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__reqq_req_rw_st0) + << 6U) + | ((0x3cU + & (((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__core_req_arb__DOT__use_per_byteen) + >> + (0xfU + & ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__core_req_arb__DOT__qual_request_index) + << 2U))) + << 2U)) + | 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(((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cache_miss_resrv__DOT__dequeue_possible) + ? + (1U + & vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cache_miss_resrv__DOT__metadata_table + [vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr][0U]) + : + ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__snrq_pop_unqual) + ? + (1U + & (IData)( + (vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT____Vcellout__snp_req_queue__data_out + >> 0x1cU))) + : 0U)) + << 0x1eU)) + | ((((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__dfpq_pop_unqual) + ? 1U + : + (((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cache_miss_resrv__DOT__dequeue_possible) + & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__mrvq_rw_st0)) + ? 1U + : + (((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__reqq_pop_unqual) + & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__reqq_req_rw_st0)) + ? 1U + : 0U))) + << 0x1dU) + | ((((((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__dfpq_pop) + | (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__mrvq_pop)) + | (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__reqq_pop)) + | (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__snrq_pop)) + << 0x1cU) + | ((0xffffffcU + & (((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__dfpq_pop_unqual) + ? + (0x3ffffffU + & vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT____Vcellout__dfp_queue__data_out[4U]) + : + ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cache_miss_resrv__DOT__dequeue_possible) + ? + ((0x19fU + >= + (0x1ffU + & ((IData)(0x1aU) + * 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((vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cache_miss_resrv__DOT__metadata_table + [vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr][1U] + << 0x1eU) + | (vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cache_miss_resrv__DOT__metadata_table + [vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr][0U] + >> 2U))) + : 0U)))))))))) + << 0x20U) + | (QData)((IData)( + ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cache_miss_resrv__DOT__dequeue_possible) + ? + ((vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cache_miss_resrv__DOT__metadata_table + [vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr][2U] + << 0xbU) + | (vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cache_miss_resrv__DOT__metadata_table + [vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr][1U] + >> 0x15U)) + : + ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__reqq_pop_unqual) + ? + (((0U + == + (0x1fU + & ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__core_req_arb__DOT__qual_request_index) + << 5U))) + ? 0U + : + (vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__core_req_arb__DOT__use_per_writedata[ + ((IData)(1U) + + + (3U + & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__core_req_arb__DOT__qual_request_index)))] + << + ((IData)(0x20U) + - + (0x1fU + & ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__core_req_arb__DOT__qual_request_index) + << 5U))))) + | (vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__core_req_arb__DOT__use_per_writedata[ + (3U + & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__core_req_arb__DOT__qual_request_index))] + >> + (0x1fU + & ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__core_req_arb__DOT__qual_request_index) + << 5U)))) + : 0U)))))) + << 0x12U)) | + __Vtemp188[5U]); + __Vtemp189[6U] = ((0x3ffffU & ((IData)((((QData)((IData)( + ((0x80000000U + & (((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cache_miss_resrv__DOT__dequeue_possible) + ? + (1U + & (vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cache_miss_resrv__DOT__metadata_table + [vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr][0U] + >> 1U)) + : + ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__snrq_pop_unqual) + ? 1U + : 0U)) + << 0x1fU)) + | ((0x40000000U + & (((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cache_miss_resrv__DOT__dequeue_possible) + ? + (1U + & vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cache_miss_resrv__DOT__metadata_table + [vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr][0U]) + : + ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__snrq_pop_unqual) + ? + (1U + & (IData)( + (vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT____Vcellout__snp_req_queue__data_out + >> 0x1cU))) + : 0U)) + << 0x1eU)) + | ((((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__dfpq_pop_unqual) + ? 1U + : + (((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cache_miss_resrv__DOT__dequeue_possible) + & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__mrvq_rw_st0)) + ? 1U + : + (((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__reqq_pop_unqual) + & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__reqq_req_rw_st0)) + ? 1U + : 0U))) + << 0x1dU) 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((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__reqq_pop_unqual) + ? + (0x3ffffffU + & (vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__reqq_req_addr_st0 + >> 4U)) + : + ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__snrq_pop_unqual) + ? + (0x3ffffffU + & (IData)( + (vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT____Vcellout__snp_req_queue__data_out + >> 0x1dU))) + : 0U)))) + << 2U)) + | (3U + & ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__reqq_pop_unqual) + ? + (3U + & vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__reqq_req_addr_st0) + : + ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cache_miss_resrv__DOT__dequeue_possible) + ? + (3U + & ((vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cache_miss_resrv__DOT__metadata_table + [vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr][1U] + << 0x1eU) + | (vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cache_miss_resrv__DOT__metadata_table + [vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr][0U] + >> 2U))) + : 0U)))))))))) + << 0x20U) + | (QData)((IData)( + ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cache_miss_resrv__DOT__dequeue_possible) + ? + ((vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cache_miss_resrv__DOT__metadata_table + [vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr][2U] + << 0xbU) + | (vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cache_miss_resrv__DOT__metadata_table + [vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr][1U] + >> 0x15U)) + : + ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__reqq_pop_unqual) + ? + (((0U + == + (0x1fU + & ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__core_req_arb__DOT__qual_request_index) + << 5U))) + ? 0U + : + (vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__core_req_arb__DOT__use_per_writedata[ + ((IData)(1U) + + + (3U + & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__core_req_arb__DOT__qual_request_index)))] + << + ((IData)(0x20U) + - + (0x1fU + & ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__core_req_arb__DOT__qual_request_index) + << 5U))))) + | (vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__core_req_arb__DOT__use_per_writedata[ + (3U + & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__core_req_arb__DOT__qual_request_index))] + >> + (0x1fU + & ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__core_req_arb__DOT__qual_request_index) + << 5U)))) + : 0U)))))) + >> 0xeU)) | (0xfffc0000U + & ((IData)( + ((((QData)((IData)( + ((0x80000000U + & (((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cache_miss_resrv__DOT__dequeue_possible) + ? + (1U + & (vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cache_miss_resrv__DOT__metadata_table + [vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr][0U] + >> 1U)) + : + ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__snrq_pop_unqual) + ? 1U + : 0U)) + << 0x1fU)) + | ((0x40000000U + & (((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cache_miss_resrv__DOT__dequeue_possible) + ? + (1U + & vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cache_miss_resrv__DOT__metadata_table + [vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr][0U]) + : + ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__snrq_pop_unqual) + ? + (1U + & (IData)( + (vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT____Vcellout__snp_req_queue__data_out + >> 0x1cU))) + : 0U)) + << 0x1eU)) + | ((((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__dfpq_pop_unqual) + ? 1U + : + (((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cache_miss_resrv__DOT__dequeue_possible) + & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__mrvq_rw_st0)) + ? 1U + : + (((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__reqq_pop_unqual) + & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__reqq_req_rw_st0)) + ? 1U + : 0U))) + << 0x1dU) + | ((((((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__dfpq_pop) + | (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__mrvq_pop)) + | (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__reqq_pop)) + | (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__snrq_pop)) + << 0x1cU) + | ((0xffffffcU + & (((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__dfpq_pop_unqual) + ? + (0x3ffffffU + & vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT____Vcellout__dfp_queue__data_out[4U]) + : + ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cache_miss_resrv__DOT__dequeue_possible) + ? + ((0x19fU + >= + (0x1ffU + & ((IData)(0x1aU) + * (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr)))) + ? + (0x3ffffffU + & (((0U + == + (0x1fU + & ((IData)(0x1aU) + * (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr)))) + ? 0U + : + (vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cache_miss_resrv__DOT__addr_table[ + ((IData)(1U) + + + (0xfU + & (((IData)(0x1aU) + * (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr)) + >> 5U)))] + << + ((IData)(0x20U) + - + (0x1fU + & ((IData)(0x1aU) + * (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr)))))) + | (vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cache_miss_resrv__DOT__addr_table[ + (0xfU + & (((IData)(0x1aU) + * (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr)) + >> 5U))] + >> + (0x1fU + & ((IData)(0x1aU) + * (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr)))))) + : 0U) + : + ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__reqq_pop_unqual) + ? + (0x3ffffffU + & (vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__reqq_req_addr_st0 + >> 4U)) + : + ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__snrq_pop_unqual) + ? + (0x3ffffffU + & (IData)( + (vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT____Vcellout__snp_req_queue__data_out + >> 0x1dU))) + : 0U)))) + << 2U)) + | (3U + & ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__reqq_pop_unqual) + ? + (3U + & vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__reqq_req_addr_st0) + : + ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cache_miss_resrv__DOT__dequeue_possible) + ? + (3U + & ((vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cache_miss_resrv__DOT__metadata_table + [vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr][1U] + << 0x1eU) + | (vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cache_miss_resrv__DOT__metadata_table + [vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr][0U] + >> 2U))) + : 0U)))))))))) + << 0x20U) + | (QData)((IData)( + ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cache_miss_resrv__DOT__dequeue_possible) + ? + ((vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cache_miss_resrv__DOT__metadata_table + [vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr][2U] + << 0xbU) + | (vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cache_miss_resrv__DOT__metadata_table + [vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr][1U] + >> 0x15U)) + : + ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__reqq_pop_unqual) + ? + (((0U + == + (0x1fU + & ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__core_req_arb__DOT__qual_request_index) + << 5U))) + ? 0U + : + (vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__core_req_arb__DOT__use_per_writedata[ + ((IData)(1U) + + + (3U + & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__core_req_arb__DOT__qual_request_index)))] + << + ((IData)(0x20U) + - + (0x1fU + & ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__core_req_arb__DOT__qual_request_index) + << 5U))))) + | (vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__core_req_arb__DOT__use_per_writedata[ + (3U + & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__core_req_arb__DOT__qual_request_index))] + >> + (0x1fU + & ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__core_req_arb__DOT__qual_request_index) + << 5U)))) + : 0U))))) + >> 0x20U)) + << 0x12U))); + __Vtemp189[7U] = (0x3ffffU & ((IData)(((((QData)((IData)( + ((0x80000000U + & (((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cache_miss_resrv__DOT__dequeue_possible) + ? + (1U + & (vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cache_miss_resrv__DOT__metadata_table + [vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr][0U] + >> 1U)) + : + ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__snrq_pop_unqual) + ? 1U + : 0U)) + << 0x1fU)) + | ((0x40000000U + & (((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cache_miss_resrv__DOT__dequeue_possible) + ? + (1U + & vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cache_miss_resrv__DOT__metadata_table + [vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr][0U]) + : + ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__snrq_pop_unqual) + ? + (1U + & (IData)( + (vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT____Vcellout__snp_req_queue__data_out + >> 0x1cU))) + : 0U)) + << 0x1eU)) + | ((((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__dfpq_pop_unqual) + ? 1U + : + (((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cache_miss_resrv__DOT__dequeue_possible) + & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__mrvq_rw_st0)) + ? 1U + : + (((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__reqq_pop_unqual) + & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__reqq_req_rw_st0)) + ? 1U + : 0U))) + << 0x1dU) + | ((((((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__dfpq_pop) + | (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__mrvq_pop)) + | (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__reqq_pop)) + | (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__snrq_pop)) + << 0x1cU) + | ((0xffffffcU + & (((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__dfpq_pop_unqual) + ? + (0x3ffffffU + & vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT____Vcellout__dfp_queue__data_out[4U]) + : + ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cache_miss_resrv__DOT__dequeue_possible) + ? + ((0x19fU + >= + (0x1ffU + & ((IData)(0x1aU) + * (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr)))) + ? + (0x3ffffffU + & (((0U + == + (0x1fU + & ((IData)(0x1aU) + * (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr)))) + ? 0U + : + (vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cache_miss_resrv__DOT__addr_table[ + ((IData)(1U) + + + (0xfU + & (((IData)(0x1aU) + * (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr)) + >> 5U)))] + << + ((IData)(0x20U) + - + (0x1fU + & ((IData)(0x1aU) + * (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr)))))) + | (vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cache_miss_resrv__DOT__addr_table[ + (0xfU + & (((IData)(0x1aU) + * (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr)) + >> 5U))] + >> + (0x1fU + & ((IData)(0x1aU) + * (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr)))))) + : 0U) + : + ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__reqq_pop_unqual) + ? + (0x3ffffffU + & (vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__reqq_req_addr_st0 + >> 4U)) + : + ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__snrq_pop_unqual) + ? + (0x3ffffffU + & (IData)( + (vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT____Vcellout__snp_req_queue__data_out + >> 0x1dU))) + : 0U)))) + << 2U)) + | (3U + & ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__reqq_pop_unqual) + ? + (3U + & vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__reqq_req_addr_st0) + : + ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cache_miss_resrv__DOT__dequeue_possible) + ? + (3U + & ((vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cache_miss_resrv__DOT__metadata_table + [vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr][1U] + << 0x1eU) + | (vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cache_miss_resrv__DOT__metadata_table + [vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr][0U] + >> 2U))) + : 0U)))))))))) + << 0x20U) + | (QData)((IData)( + ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cache_miss_resrv__DOT__dequeue_possible) + ? + ((vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cache_miss_resrv__DOT__metadata_table + [vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr][2U] + << 0xbU) + | (vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cache_miss_resrv__DOT__metadata_table + [vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr][1U] + >> 0x15U)) + : + ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__reqq_pop_unqual) + ? + (((0U + == + (0x1fU + & ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__core_req_arb__DOT__qual_request_index) + << 5U))) + ? 0U + : + (vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__core_req_arb__DOT__use_per_writedata[ + ((IData)(1U) + + + (3U + & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__core_req_arb__DOT__qual_request_index)))] + << + ((IData)(0x20U) + - + (0x1fU + & ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__core_req_arb__DOT__qual_request_index) + << 5U))))) + | (vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__core_req_arb__DOT__use_per_writedata[ + (3U + & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__core_req_arb__DOT__qual_request_index))] + >> + (0x1fU + & ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__core_req_arb__DOT__qual_request_index) + << 5U)))) + : 0U))))) + >> 0x20U)) + >> 0xeU)); + vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT____Vcellinp__s0_1_c0__in[0U] + = ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__dfpq_pop_unqual) + ? vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT____Vcellout__dfp_queue__data_out[0U] + : 0x39U); + vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT____Vcellinp__s0_1_c0__in[1U] + = ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__dfpq_pop_unqual) + ? vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT____Vcellout__dfp_queue__data_out[1U] + : 0U); + vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT____Vcellinp__s0_1_c0__in[2U] + = ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__dfpq_pop_unqual) + ? vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT____Vcellout__dfp_queue__data_out[2U] + : 0U); + vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT____Vcellinp__s0_1_c0__in[3U] + = ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__dfpq_pop_unqual) + ? vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT____Vcellout__dfp_queue__data_out[3U] + : 0U); + vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT____Vcellinp__s0_1_c0__in[4U] + = __Vtemp188[4U]; + vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT____Vcellinp__s0_1_c0__in[5U] + = __Vtemp189[5U]; + vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT____Vcellinp__s0_1_c0__in[6U] + = __Vtemp189[6U]; + vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT____Vcellinp__s0_1_c0__in[7U] + = ((0xfffc0000U & ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cache_miss_resrv__DOT__dequeue_possible) + << 0x12U)) | __Vtemp189[7U]); + vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__miss_st1e + = (((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__tag_data_access__DOT__real_miss) + | (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__tag_data_access__DOT__snoop_hit_no_pending)) + | (((((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__force_request_miss_st1e) + & (~ vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__is_snp_st1 + [0U])) & (~ vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__is_fill_st1 + [0U])) & vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__valid_st1 + [0U]) & (~ (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__tag_data_access__DOT__real_miss)))); + vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__dwb_queue__DOT__reading + = ((((((vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT____Vcellout__dwb_queue__data_out[6U] + >> 7U) & (~ (vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT____Vcellout__dwb_queue__data_out[6U] + >> 6U))) & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__dram_wb_req_fire)) + | (((vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT____Vcellout__dwb_queue__data_out[6U] + >> 6U) & (~ (vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT____Vcellout__dwb_queue__data_out[6U] + >> 7U))) & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__snp_rsp_fire))) + | (((vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT____Vcellout__dwb_queue__data_out[6U] + >> 7U) & (vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT____Vcellout__dwb_queue__data_out[6U] + >> 6U)) & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__snp_rsp_fire))) + & (~ (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__genblk2__DOT__empty_r))); + vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__dwb_queue__DOT__reading + = ((((((vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT____Vcellout__dwb_queue__data_out[6U] + >> 7U) & (~ (vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT____Vcellout__dwb_queue__data_out[6U] + >> 6U))) & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__dram_wb_req_fire)) + | (((vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT____Vcellout__dwb_queue__data_out[6U] + >> 6U) & (~ (vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT____Vcellout__dwb_queue__data_out[6U] + >> 7U))) & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__snp_rsp_fire))) + | (((vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT____Vcellout__dwb_queue__data_out[6U] + >> 7U) & (vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT____Vcellout__dwb_queue__data_out[6U] + >> 6U)) & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__snp_rsp_fire))) + & (~ (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__genblk2__DOT__empty_r))); + vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__dwb_queue__DOT__reading + = ((((((vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT____Vcellout__dwb_queue__data_out[6U] + >> 7U) & (~ (vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT____Vcellout__dwb_queue__data_out[6U] + >> 6U))) & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__dram_wb_req_fire)) + | (((vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT____Vcellout__dwb_queue__data_out[6U] + >> 6U) & (~ (vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT____Vcellout__dwb_queue__data_out[6U] + >> 7U))) & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__snp_rsp_fire))) + | (((vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT____Vcellout__dwb_queue__data_out[6U] + >> 7U) & (vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT____Vcellout__dwb_queue__data_out[6U] + >> 6U)) & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__snp_rsp_fire))) + & (~ (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__genblk2__DOT__empty_r))); + vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__dwb_queue__DOT__reading + = ((((((vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT____Vcellout__dwb_queue__data_out[6U] + >> 7U) & (~ (vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT____Vcellout__dwb_queue__data_out[6U] + >> 6U))) & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__dram_wb_req_fire)) + | (((vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT____Vcellout__dwb_queue__data_out[6U] + >> 6U) & (~ (vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT____Vcellout__dwb_queue__data_out[6U] + >> 7U))) & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__snp_rsp_fire))) + | (((vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT____Vcellout__dwb_queue__data_out[6U] + >> 7U) & (vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT____Vcellout__dwb_queue__data_out[6U] + >> 6U)) & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__snp_rsp_fire))) + & (~ (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__genblk2__DOT__empty_r))); + __Vtemp191[0U] = vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__tag_data_access__DOT__read_data_st1c + [0U][0U]; + __Vtemp191[1U] = vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__tag_data_access__DOT__read_data_st1c + [0U][1U]; + __Vtemp191[2U] = vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__tag_data_access__DOT__read_data_st1c + [0U][2U]; + __Vtemp191[3U] = vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__tag_data_access__DOT__read_data_st1c + [0U][3U]; + __Vtemp198[6U] = ((0x7fffffU & (vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__tag_data_access__DOT__read_data_st1c + [0U][3U] >> 9U)) + | (0xff800000U & ((IData)((((QData)((IData)( + vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__writeword_st1 + [0U])) + << 0x20U) + | (QData)((IData)( + (((0U + == + (0x1fU + & (vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__wsel_st1 + [0U] + << 5U))) + ? 0U + : + (__Vtemp191[ + ((IData)(1U) + + + (3U + & vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__wsel_st1 + [0U]))] + << + ((IData)(0x20U) + - + (0x1fU + & (vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__wsel_st1 + [0U] + << 5U))))) + | (__Vtemp191[ + (3U + & vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__wsel_st1 + [0U])] + >> + (0x1fU + & (vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__wsel_st1 + [0U] + << 5U)))))))) + << 0x17U))); + __Vtemp198[7U] = ((0x7fffffU & ((IData)((((QData)((IData)( + vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__writeword_st1 + [0U])) + << 0x20U) + | (QData)((IData)( + (((0U + == + (0x1fU + & (vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__wsel_st1 + [0U] + << 5U))) + ? 0U + : + (__Vtemp191[ + ((IData)(1U) + + + (3U + & vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__wsel_st1 + [0U]))] + << + ((IData)(0x20U) + - + (0x1fU + & (vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__wsel_st1 + [0U] + << 5U))))) + | (__Vtemp191[ + (3U + & vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__wsel_st1 + [0U])] + >> + (0x1fU + & (vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__wsel_st1 + [0U] + << 5U)))))))) + >> 9U)) | (0xff800000U + & ((IData)( + ((((QData)((IData)( + vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__writeword_st1 + [0U])) + << 0x20U) + | (QData)((IData)( + (((0U + == + (0x1fU + & (vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__wsel_st1 + [0U] + << 5U))) + ? 0U + : + (__Vtemp191[ + ((IData)(1U) + + + (3U + & vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__wsel_st1 + [0U]))] + << + ((IData)(0x20U) + - + (0x1fU + & (vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__wsel_st1 + [0U] + << 5U))))) + | (__Vtemp191[ + (3U + & vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__wsel_st1 + [0U])] + >> + (0x1fU + & (vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__wsel_st1 + [0U] + << 5U))))))) + >> 0x20U)) + << 0x17U))); + __Vtemp199[8U] = ((0xff800000U & (vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__wsel_st1 + [0U] << 0x17U)) + | (0x7fffffU & ((IData)(((((QData)((IData)( + vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__writeword_st1 + [0U])) + << 0x20U) + | (QData)((IData)( + (((0U + == + (0x1fU + & (vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__wsel_st1 + [0U] + << 5U))) + ? 0U + : + (__Vtemp191[ + ((IData)(1U) + + + (3U + & vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__wsel_st1 + [0U]))] + << + ((IData)(0x20U) + - + (0x1fU + & (vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__wsel_st1 + [0U] + << 5U))))) + | (__Vtemp191[ + (3U + & vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__wsel_st1 + [0U])] + >> + (0x1fU + & (vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__wsel_st1 + [0U] + << 5U))))))) + >> 0x20U)) + >> 9U))); + __Vtemp201[9U] = ((0xfe000000U & (((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__snp_to_mrvq_st1e) + | ((((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__force_request_miss_st1e) + & (~ vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__is_snp_st1 + [0U])) + & (~ vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__is_fill_st1 + [0U])) + & vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__valid_st1 + [0U])) << 0x19U)) + | (0x1ffffffU & ((0x1000000U + & ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__snp_to_mrvq_st1e) + << 0x18U)) + | ((0x1800000U + & (vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__is_snp_st1 + [0U] + << 0x17U)) + | ((0x1c00000U + & (vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__snp_invalidate_st1 + [0U] + << 0x16U)) + | ((0x1e00000U + & (((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__tag_data_access__DOT__real_writefill) + & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__dirty_st1e)) + << 0x15U)) + | ((0x1f00000U + & (vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__is_fill_st1 + [0U] + << 0x14U)) + | ((0x1f80000U + & ((vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__valid_st1 + [0U] + & (~ + vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__is_fill_st1 + [0U])) + << 0x13U)) + | (vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__addr_st1 + [0U] + >> 7U))))))))); + vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT____Vcellinp__st_1e_2__in[0U] + = (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__inst_meta_st1 + [0U]); + vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT____Vcellinp__st_1e_2__in[1U] + = ((0xfffe0000U & (vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__tag_data_access__DOT__read_dirtyb_st1c + [0U] << 0x11U)) | (IData)( + (vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__inst_meta_st1 + [0U] + >> 0x20U))); + vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT____Vcellinp__st_1e_2__in[2U] + = ((0xff800000U & (vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__tag_data_access__DOT__read_data_st1c + [0U][0U] << 0x17U)) | ((0xfffffff8U + & (vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__tag_data_access__DOT__read_tag_st1c + [0U] + << 3U)) + | ((0xfffffffcU + & ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__miss_st1e) + << 2U)) + | ((0xfffffffeU + & ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__dirty_st1e) + << 1U)) + | (0x1ffffU + & (vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__tag_data_access__DOT__read_dirtyb_st1c + [0U] + >> 0xfU)))))); + vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT____Vcellinp__st_1e_2__in[3U] + = ((0x7fffffU & (vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__tag_data_access__DOT__read_data_st1c + [0U][0U] >> 9U)) | (0xff800000U + & (vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__tag_data_access__DOT__read_data_st1c + [0U][1U] + << 0x17U))); + vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT____Vcellinp__st_1e_2__in[4U] + = ((0x7fffffU & (vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__tag_data_access__DOT__read_data_st1c + [0U][1U] >> 9U)) | (0xff800000U + & (vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__tag_data_access__DOT__read_data_st1c + [0U][2U] + << 0x17U))); + vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT____Vcellinp__st_1e_2__in[5U] + = ((0x7fffffU & (vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__tag_data_access__DOT__read_data_st1c + [0U][2U] >> 9U)) | (0xff800000U + & (vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__tag_data_access__DOT__read_data_st1c + [0U][3U] + << 0x17U))); + vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT____Vcellinp__st_1e_2__in[6U] + = __Vtemp198[6U]; + vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT____Vcellinp__st_1e_2__in[7U] + = __Vtemp198[7U]; + vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT____Vcellinp__st_1e_2__in[8U] + = ((0xfe000000U & (vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__addr_st1 + [0U] << 0x19U)) | __Vtemp199[8U]); + vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT____Vcellinp__st_1e_2__in[9U] + = ((0xf8000000U & ((((vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__valid_st1 + [0U] & vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__is_mrvq_st1 + [0U]) & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__recover_mrvq_state_st2)) + & ((0x3ffffffU & ((vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__st_1e_2__DOT__value[9U] + << 7U) + | (vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__st_1e_2__DOT__value[8U] + >> 0x19U))) + == vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__addr_st1 + [0U])) << 0x1bU)) | + ((0xfc000000U & (vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__is_mrvq_st1 + [0U] << 0x1aU)) | __Vtemp201[9U])); + vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__tag_data_access__DOT__should_write + = ((((((IData)((vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__inst_meta_st1 + [0U] >> 6U)) & vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__valid_st1 + [0U]) & vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__tag_data_access__DOT__read_valid_st1c + [0U]) & (~ (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__miss_st1e))) + & (~ vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__is_snp_st1 + [0U])) & (~ (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__tag_data_access__DOT__real_writefill))); + __Vtemp204[0U] = vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__tag_data_access__DOT__read_data_st1c + [0U][0U]; + __Vtemp204[1U] = vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__tag_data_access__DOT__read_data_st1c + [0U][1U]; + __Vtemp204[2U] = vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__tag_data_access__DOT__read_data_st1c + [0U][2U]; + __Vtemp204[3U] = vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__tag_data_access__DOT__read_data_st1c + [0U][3U]; + __Vtemp211[6U] = ((0x7fffffU & (vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__tag_data_access__DOT__read_data_st1c + [0U][3U] >> 9U)) + | (0xff800000U & ((IData)((((QData)((IData)( + vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__writeword_st1 + [0U])) + << 0x20U) + | (QData)((IData)( + (((0U + == + (0x1fU + & (vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__wsel_st1 + [0U] + << 5U))) + ? 0U + : + (__Vtemp204[ + ((IData)(1U) + + + (3U + & vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__wsel_st1 + [0U]))] + << + ((IData)(0x20U) + - + (0x1fU + & (vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__wsel_st1 + [0U] + << 5U))))) + | (__Vtemp204[ + (3U + & vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__wsel_st1 + [0U])] + >> + (0x1fU + & (vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__wsel_st1 + [0U] + << 5U)))))))) + << 0x17U))); + __Vtemp211[7U] = ((0x7fffffU & ((IData)((((QData)((IData)( + vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__writeword_st1 + [0U])) + << 0x20U) + | (QData)((IData)( + (((0U + == + (0x1fU + & (vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__wsel_st1 + [0U] + << 5U))) + ? 0U + : + (__Vtemp204[ + ((IData)(1U) + + + (3U + & vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__wsel_st1 + [0U]))] + << + ((IData)(0x20U) + - + (0x1fU + & (vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__wsel_st1 + [0U] + << 5U))))) + | (__Vtemp204[ + (3U + & vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__wsel_st1 + [0U])] + >> + (0x1fU + & (vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__wsel_st1 + [0U] + << 5U)))))))) + >> 9U)) | (0xff800000U + & ((IData)( + ((((QData)((IData)( + vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__writeword_st1 + [0U])) + << 0x20U) + | (QData)((IData)( + (((0U + == + (0x1fU + & (vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__wsel_st1 + [0U] + << 5U))) + ? 0U + : + (__Vtemp204[ + ((IData)(1U) + + + (3U + & vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__wsel_st1 + [0U]))] + << + ((IData)(0x20U) + - + (0x1fU + & (vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__wsel_st1 + [0U] + << 5U))))) + | (__Vtemp204[ + (3U + & vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__wsel_st1 + [0U])] + >> + (0x1fU + & (vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__wsel_st1 + [0U] + << 5U))))))) + >> 0x20U)) + << 0x17U))); + __Vtemp212[8U] = ((0xff800000U & (vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__wsel_st1 + [0U] << 0x17U)) + | (0x7fffffU & ((IData)(((((QData)((IData)( + vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__writeword_st1 + [0U])) + << 0x20U) + | (QData)((IData)( + (((0U + == + (0x1fU + & (vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__wsel_st1 + [0U] + << 5U))) + ? 0U + : + (__Vtemp204[ + ((IData)(1U) + + + (3U + & vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__wsel_st1 + [0U]))] + << + ((IData)(0x20U) + - + (0x1fU + & (vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__wsel_st1 + [0U] + << 5U))))) + | (__Vtemp204[ + (3U + & vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__wsel_st1 + [0U])] + >> + (0x1fU + & (vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__wsel_st1 + [0U] + << 5U))))))) + >> 0x20U)) + >> 9U))); + __Vtemp214[9U] = ((0xfe000000U & (((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__snp_to_mrvq_st1e) + | ((((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__force_request_miss_st1e) + & (~ vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__is_snp_st1 + [0U])) + & (~ vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__is_fill_st1 + [0U])) + & vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__valid_st1 + [0U])) << 0x19U)) + | (0x1ffffffU & ((0x1000000U + & ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__snp_to_mrvq_st1e) + << 0x18U)) + | ((0x1800000U + & (vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__is_snp_st1 + [0U] + << 0x17U)) + | ((0x1c00000U + & (vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__snp_invalidate_st1 + [0U] + << 0x16U)) + | ((0x1e00000U + & (((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__tag_data_access__DOT__real_writefill) + & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__dirty_st1e)) + << 0x15U)) + | ((0x1f00000U + & (vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__is_fill_st1 + [0U] + << 0x14U)) + | ((0x1f80000U + & ((vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__valid_st1 + [0U] + & (~ + vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__is_fill_st1 + [0U])) + << 0x13U)) + | (vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__addr_st1 + [0U] + >> 7U))))))))); + vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT____Vcellinp__st_1e_2__in[0U] + = (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__inst_meta_st1 + [0U]); + vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT____Vcellinp__st_1e_2__in[1U] + = ((0xfffe0000U & (vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__tag_data_access__DOT__read_dirtyb_st1c + [0U] << 0x11U)) | (IData)( + (vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__inst_meta_st1 + [0U] + >> 0x20U))); + vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT____Vcellinp__st_1e_2__in[2U] + = ((0xff800000U & (vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__tag_data_access__DOT__read_data_st1c + [0U][0U] << 0x17U)) | ((0xfffffff8U + & (vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__tag_data_access__DOT__read_tag_st1c + [0U] + << 3U)) + | ((0xfffffffcU + & ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__miss_st1e) + << 2U)) + | ((0xfffffffeU + & ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__dirty_st1e) + << 1U)) + | (0x1ffffU + & (vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__tag_data_access__DOT__read_dirtyb_st1c + [0U] + >> 0xfU)))))); + vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT____Vcellinp__st_1e_2__in[3U] + = ((0x7fffffU & (vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__tag_data_access__DOT__read_data_st1c + [0U][0U] >> 9U)) | (0xff800000U + & (vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__tag_data_access__DOT__read_data_st1c + [0U][1U] + << 0x17U))); + vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT____Vcellinp__st_1e_2__in[4U] + = ((0x7fffffU & (vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__tag_data_access__DOT__read_data_st1c + [0U][1U] >> 9U)) | (0xff800000U + & (vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__tag_data_access__DOT__read_data_st1c + [0U][2U] + << 0x17U))); + vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT____Vcellinp__st_1e_2__in[5U] + = ((0x7fffffU & (vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__tag_data_access__DOT__read_data_st1c + [0U][2U] >> 9U)) | (0xff800000U + & (vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__tag_data_access__DOT__read_data_st1c + [0U][3U] + << 0x17U))); + vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT____Vcellinp__st_1e_2__in[6U] + = __Vtemp211[6U]; + vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT____Vcellinp__st_1e_2__in[7U] + = __Vtemp211[7U]; + vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT____Vcellinp__st_1e_2__in[8U] + = ((0xfe000000U & (vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__addr_st1 + [0U] << 0x19U)) | __Vtemp212[8U]); + vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT____Vcellinp__st_1e_2__in[9U] + = ((0xf8000000U & ((((vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__valid_st1 + [0U] & vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__is_mrvq_st1 + [0U]) & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__recover_mrvq_state_st2)) + & ((0x3ffffffU & ((vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__st_1e_2__DOT__value[9U] + << 7U) + | (vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__st_1e_2__DOT__value[8U] + >> 0x19U))) + == vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__addr_st1 + [0U])) << 0x1bU)) | + ((0xfc000000U & (vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__is_mrvq_st1 + [0U] << 0x1aU)) | __Vtemp214[9U])); + vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__tag_data_access__DOT__should_write + = ((((((IData)((vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__inst_meta_st1 + [0U] >> 6U)) & vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__valid_st1 + [0U]) & vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__tag_data_access__DOT__read_valid_st1c + [0U]) & (~ (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__miss_st1e))) + & (~ vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__is_snp_st1 + [0U])) & (~ (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__tag_data_access__DOT__real_writefill))); + __Vtemp217[0U] = vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__tag_data_access__DOT__read_data_st1c + [0U][0U]; + __Vtemp217[1U] = vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__tag_data_access__DOT__read_data_st1c + [0U][1U]; + __Vtemp217[2U] = vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__tag_data_access__DOT__read_data_st1c + [0U][2U]; + __Vtemp217[3U] = vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__tag_data_access__DOT__read_data_st1c + [0U][3U]; + __Vtemp224[6U] = ((0x7fffffU & (vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__tag_data_access__DOT__read_data_st1c + [0U][3U] >> 9U)) + | (0xff800000U & ((IData)((((QData)((IData)( + vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__writeword_st1 + [0U])) + << 0x20U) + | (QData)((IData)( + (((0U + == + (0x1fU + & (vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__wsel_st1 + [0U] + << 5U))) + ? 0U + : + (__Vtemp217[ + ((IData)(1U) + + + (3U + & vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__wsel_st1 + [0U]))] + << + ((IData)(0x20U) + - + (0x1fU + & (vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__wsel_st1 + [0U] + << 5U))))) + | (__Vtemp217[ + (3U + & vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__wsel_st1 + [0U])] + >> + (0x1fU + & (vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__wsel_st1 + [0U] + << 5U)))))))) + << 0x17U))); + __Vtemp224[7U] = ((0x7fffffU & ((IData)((((QData)((IData)( + vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__writeword_st1 + [0U])) + << 0x20U) + | (QData)((IData)( + (((0U + == + (0x1fU + & (vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__wsel_st1 + [0U] + << 5U))) + ? 0U + : + (__Vtemp217[ + ((IData)(1U) + + + (3U + & vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__wsel_st1 + [0U]))] + << + ((IData)(0x20U) + - + (0x1fU + & (vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__wsel_st1 + [0U] + << 5U))))) + | (__Vtemp217[ + (3U + & vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__wsel_st1 + [0U])] + >> + (0x1fU + & (vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__wsel_st1 + [0U] + << 5U)))))))) + >> 9U)) | (0xff800000U + & ((IData)( + ((((QData)((IData)( + vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__writeword_st1 + [0U])) + << 0x20U) + | (QData)((IData)( + (((0U + == + (0x1fU + & (vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__wsel_st1 + [0U] + << 5U))) + ? 0U + : + (__Vtemp217[ + ((IData)(1U) + + + (3U + & vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__wsel_st1 + [0U]))] + << + ((IData)(0x20U) + - + (0x1fU + & (vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__wsel_st1 + [0U] + << 5U))))) + | (__Vtemp217[ + (3U + & vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__wsel_st1 + [0U])] + >> + (0x1fU + & (vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__wsel_st1 + [0U] + << 5U))))))) + >> 0x20U)) + << 0x17U))); + __Vtemp225[8U] = ((0xff800000U & (vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__wsel_st1 + [0U] << 0x17U)) + | (0x7fffffU & ((IData)(((((QData)((IData)( + vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__writeword_st1 + [0U])) + << 0x20U) + | (QData)((IData)( + (((0U + == + (0x1fU + & (vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__wsel_st1 + [0U] + << 5U))) + ? 0U + : + (__Vtemp217[ + ((IData)(1U) + + + (3U + & vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__wsel_st1 + [0U]))] + << + ((IData)(0x20U) + - + (0x1fU + & (vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__wsel_st1 + [0U] + << 5U))))) + | (__Vtemp217[ + (3U + & vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__wsel_st1 + [0U])] + >> + (0x1fU + & (vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__wsel_st1 + [0U] + << 5U))))))) + >> 0x20U)) + >> 9U))); + __Vtemp227[9U] = ((0xfe000000U & (((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__snp_to_mrvq_st1e) + | ((((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__force_request_miss_st1e) + & (~ vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__is_snp_st1 + [0U])) + & (~ vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__is_fill_st1 + [0U])) + & vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__valid_st1 + [0U])) << 0x19U)) + | (0x1ffffffU & ((0x1000000U + & ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__snp_to_mrvq_st1e) + << 0x18U)) + | ((0x1800000U + & (vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__is_snp_st1 + [0U] + << 0x17U)) + | ((0x1c00000U + & (vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__snp_invalidate_st1 + [0U] + << 0x16U)) + | ((0x1e00000U + & (((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__tag_data_access__DOT__real_writefill) + & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__dirty_st1e)) + << 0x15U)) + | ((0x1f00000U + & (vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__is_fill_st1 + [0U] + << 0x14U)) + | ((0x1f80000U + & ((vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__valid_st1 + [0U] + & (~ + vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__is_fill_st1 + [0U])) + << 0x13U)) + | (vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__addr_st1 + [0U] + >> 7U))))))))); + vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT____Vcellinp__st_1e_2__in[0U] + = (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__inst_meta_st1 + [0U]); + vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT____Vcellinp__st_1e_2__in[1U] + = ((0xfffe0000U & (vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__tag_data_access__DOT__read_dirtyb_st1c + [0U] << 0x11U)) | (IData)( + (vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__inst_meta_st1 + [0U] + >> 0x20U))); + vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT____Vcellinp__st_1e_2__in[2U] + = ((0xff800000U & (vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__tag_data_access__DOT__read_data_st1c + [0U][0U] << 0x17U)) | ((0xfffffff8U + & (vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__tag_data_access__DOT__read_tag_st1c + [0U] + << 3U)) + | ((0xfffffffcU + & ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__miss_st1e) + << 2U)) + | ((0xfffffffeU + & ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__dirty_st1e) + << 1U)) + | (0x1ffffU + & (vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__tag_data_access__DOT__read_dirtyb_st1c + [0U] + >> 0xfU)))))); + vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT____Vcellinp__st_1e_2__in[3U] + = ((0x7fffffU & (vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__tag_data_access__DOT__read_data_st1c + [0U][0U] >> 9U)) | (0xff800000U + & (vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__tag_data_access__DOT__read_data_st1c + [0U][1U] + << 0x17U))); + vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT____Vcellinp__st_1e_2__in[4U] + = ((0x7fffffU & (vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__tag_data_access__DOT__read_data_st1c + [0U][1U] >> 9U)) | (0xff800000U + & (vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__tag_data_access__DOT__read_data_st1c + [0U][2U] + << 0x17U))); + vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT____Vcellinp__st_1e_2__in[5U] + = ((0x7fffffU & (vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__tag_data_access__DOT__read_data_st1c + [0U][2U] >> 9U)) | (0xff800000U + & (vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__tag_data_access__DOT__read_data_st1c + [0U][3U] + << 0x17U))); + vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT____Vcellinp__st_1e_2__in[6U] + = __Vtemp224[6U]; + vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT____Vcellinp__st_1e_2__in[7U] + = __Vtemp224[7U]; + vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT____Vcellinp__st_1e_2__in[8U] + = ((0xfe000000U & (vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__addr_st1 + [0U] << 0x19U)) | __Vtemp225[8U]); + vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT____Vcellinp__st_1e_2__in[9U] + = ((0xf8000000U & ((((vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__valid_st1 + [0U] & vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__is_mrvq_st1 + [0U]) & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__recover_mrvq_state_st2)) + & ((0x3ffffffU & ((vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__st_1e_2__DOT__value[9U] + << 7U) + | (vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__st_1e_2__DOT__value[8U] + >> 0x19U))) + == vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__addr_st1 + [0U])) << 0x1bU)) | + ((0xfc000000U & (vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__is_mrvq_st1 + [0U] << 0x1aU)) | __Vtemp227[9U])); + vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__tag_data_access__DOT__should_write + = ((((((IData)((vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__inst_meta_st1 + [0U] >> 6U)) & vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__valid_st1 + [0U]) & vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__tag_data_access__DOT__read_valid_st1c + [0U]) & (~ (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__miss_st1e))) + & (~ vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__is_snp_st1 + [0U])) & (~ (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__tag_data_access__DOT__real_writefill))); + __Vtemp230[0U] = vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__tag_data_access__DOT__read_data_st1c + [0U][0U]; + __Vtemp230[1U] = vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__tag_data_access__DOT__read_data_st1c + [0U][1U]; + __Vtemp230[2U] = vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__tag_data_access__DOT__read_data_st1c + [0U][2U]; + __Vtemp230[3U] = vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__tag_data_access__DOT__read_data_st1c + [0U][3U]; + __Vtemp237[6U] = ((0x7fffffU & (vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__tag_data_access__DOT__read_data_st1c + [0U][3U] >> 9U)) + | (0xff800000U & ((IData)((((QData)((IData)( + vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__writeword_st1 + [0U])) + << 0x20U) + | (QData)((IData)( + (((0U + == + (0x1fU + & (vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__wsel_st1 + [0U] + << 5U))) + ? 0U + : + (__Vtemp230[ + ((IData)(1U) + + + (3U + & vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__wsel_st1 + [0U]))] + << + ((IData)(0x20U) + - + (0x1fU + & (vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__wsel_st1 + [0U] + << 5U))))) + | (__Vtemp230[ + (3U + & vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__wsel_st1 + [0U])] + >> + (0x1fU + & (vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__wsel_st1 + [0U] + << 5U)))))))) + << 0x17U))); + __Vtemp237[7U] = ((0x7fffffU & ((IData)((((QData)((IData)( + vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__writeword_st1 + [0U])) + << 0x20U) + | (QData)((IData)( + (((0U + == + (0x1fU + & (vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__wsel_st1 + [0U] + << 5U))) + ? 0U + : + (__Vtemp230[ + ((IData)(1U) + + + (3U + & vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__wsel_st1 + [0U]))] + << + ((IData)(0x20U) + - + (0x1fU + & (vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__wsel_st1 + [0U] + << 5U))))) + | (__Vtemp230[ + (3U + & vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__wsel_st1 + [0U])] + >> + (0x1fU + & (vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__wsel_st1 + [0U] + << 5U)))))))) + >> 9U)) | (0xff800000U + & ((IData)( + ((((QData)((IData)( + vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__writeword_st1 + [0U])) + << 0x20U) + | (QData)((IData)( + (((0U + == + (0x1fU + & (vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__wsel_st1 + [0U] + << 5U))) + ? 0U + : + (__Vtemp230[ + ((IData)(1U) + + + (3U + & vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__wsel_st1 + [0U]))] + << + ((IData)(0x20U) + - + (0x1fU + & (vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__wsel_st1 + [0U] + << 5U))))) + | (__Vtemp230[ + (3U + & vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__wsel_st1 + [0U])] + >> + (0x1fU + & (vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__wsel_st1 + [0U] + << 5U))))))) + >> 0x20U)) + << 0x17U))); + __Vtemp238[8U] = ((0xff800000U & (vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__wsel_st1 + [0U] << 0x17U)) + | (0x7fffffU & ((IData)(((((QData)((IData)( + vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__writeword_st1 + [0U])) + << 0x20U) + | (QData)((IData)( + (((0U + == + (0x1fU + & (vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__wsel_st1 + [0U] + << 5U))) + ? 0U + : + (__Vtemp230[ + ((IData)(1U) + + + (3U + & vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__wsel_st1 + [0U]))] + << + ((IData)(0x20U) + - + (0x1fU + & (vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__wsel_st1 + [0U] + << 5U))))) + | (__Vtemp230[ + (3U + & vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__wsel_st1 + [0U])] + >> + (0x1fU + & (vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__wsel_st1 + [0U] + << 5U))))))) + >> 0x20U)) + >> 9U))); + __Vtemp240[9U] = ((0xfe000000U & (((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__snp_to_mrvq_st1e) + | ((((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__force_request_miss_st1e) + & (~ vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__is_snp_st1 + [0U])) + & (~ vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__is_fill_st1 + [0U])) + & vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__valid_st1 + [0U])) << 0x19U)) + | (0x1ffffffU & ((0x1000000U + & ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__snp_to_mrvq_st1e) + << 0x18U)) + | ((0x1800000U + & (vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__is_snp_st1 + [0U] + << 0x17U)) + | ((0x1c00000U + & (vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__snp_invalidate_st1 + [0U] + << 0x16U)) + | ((0x1e00000U + & (((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__tag_data_access__DOT__real_writefill) + & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__dirty_st1e)) + << 0x15U)) + | ((0x1f00000U + & (vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__is_fill_st1 + [0U] + << 0x14U)) + | ((0x1f80000U + & ((vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__valid_st1 + [0U] + & (~ + vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__is_fill_st1 + [0U])) + << 0x13U)) + | (vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__addr_st1 + [0U] + >> 7U))))))))); + vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT____Vcellinp__st_1e_2__in[0U] + = (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__inst_meta_st1 + [0U]); + vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT____Vcellinp__st_1e_2__in[1U] + = ((0xfffe0000U & (vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__tag_data_access__DOT__read_dirtyb_st1c + [0U] << 0x11U)) | (IData)( + (vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__inst_meta_st1 + [0U] + >> 0x20U))); + vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT____Vcellinp__st_1e_2__in[2U] + = ((0xff800000U & (vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__tag_data_access__DOT__read_data_st1c + [0U][0U] << 0x17U)) | ((0xfffffff8U + & (vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__tag_data_access__DOT__read_tag_st1c + [0U] + << 3U)) + | ((0xfffffffcU + & ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__miss_st1e) + << 2U)) + | ((0xfffffffeU + & ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__dirty_st1e) + << 1U)) + | (0x1ffffU + & (vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__tag_data_access__DOT__read_dirtyb_st1c + [0U] + >> 0xfU)))))); + vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT____Vcellinp__st_1e_2__in[3U] + = ((0x7fffffU & (vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__tag_data_access__DOT__read_data_st1c + [0U][0U] >> 9U)) | (0xff800000U + & (vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__tag_data_access__DOT__read_data_st1c + [0U][1U] + << 0x17U))); + vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT____Vcellinp__st_1e_2__in[4U] + = ((0x7fffffU & (vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__tag_data_access__DOT__read_data_st1c + [0U][1U] >> 9U)) | (0xff800000U + & (vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__tag_data_access__DOT__read_data_st1c + [0U][2U] + << 0x17U))); + vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT____Vcellinp__st_1e_2__in[5U] + = ((0x7fffffU & (vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__tag_data_access__DOT__read_data_st1c + [0U][2U] >> 9U)) | (0xff800000U + & (vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__tag_data_access__DOT__read_data_st1c + [0U][3U] + << 0x17U))); + vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT____Vcellinp__st_1e_2__in[6U] + = __Vtemp237[6U]; + vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT____Vcellinp__st_1e_2__in[7U] + = __Vtemp237[7U]; + vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT____Vcellinp__st_1e_2__in[8U] + = ((0xfe000000U & (vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__addr_st1 + [0U] << 0x19U)) | __Vtemp238[8U]); + vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT____Vcellinp__st_1e_2__in[9U] + = ((0xf8000000U & ((((vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__valid_st1 + [0U] & vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__is_mrvq_st1 + [0U]) & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__recover_mrvq_state_st2)) + & ((0x3ffffffU & ((vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__st_1e_2__DOT__value[9U] + << 7U) + | (vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__st_1e_2__DOT__value[8U] + >> 0x19U))) + == vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__addr_st1 + [0U])) << 0x1bU)) | + ((0xfc000000U & (vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__is_mrvq_st1 + [0U] << 0x1aU)) | __Vtemp240[9U])); + vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__tag_data_access__DOT__should_write + = ((((((IData)((vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__inst_meta_st1 + [0U] >> 6U)) & vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__valid_st1 + [0U]) & vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__tag_data_access__DOT__read_valid_st1c + [0U]) & (~ (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__miss_st1e))) + & (~ vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__is_snp_st1 + [0U])) & (~ (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__tag_data_access__DOT__real_writefill))); + vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__tag_data_access__DOT__we + = ((0xfff0U & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__tag_data_access__DOT__we)) + | ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__tag_data_access__DOT__real_writefill) + ? 0xfU : (((0U == vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__wsel_st1 + [0U]) & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__tag_data_access__DOT__should_write)) + ? (0xfU & (IData)((vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__inst_meta_st1 + [0U] >> 2U))) + : 0U))); + vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__tag_data_access__DOT__we + = ((0xff0fU & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__tag_data_access__DOT__we)) + | (((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__tag_data_access__DOT__real_writefill) + ? 0xfU : (((1U == vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__wsel_st1 + [0U]) & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__tag_data_access__DOT__should_write)) + ? (0xfU & (IData)((vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__inst_meta_st1 + [0U] + >> 2U))) + : 0U)) << 4U)); + vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__tag_data_access__DOT__we + = ((0xf0ffU & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__tag_data_access__DOT__we)) + | (((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__tag_data_access__DOT__real_writefill) + ? 0xfU : (((2U == vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__wsel_st1 + [0U]) & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__tag_data_access__DOT__should_write)) + ? (0xfU & (IData)((vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__inst_meta_st1 + [0U] + >> 2U))) + : 0U)) << 8U)); + vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__tag_data_access__DOT__we + = ((0xfffU & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__tag_data_access__DOT__we)) + | (((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__tag_data_access__DOT__real_writefill) + ? 0xfU : (((3U == vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__wsel_st1 + [0U]) & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__tag_data_access__DOT__should_write)) + ? (0xfU & (IData)((vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__inst_meta_st1 + [0U] + >> 2U))) + : 0U)) << 0xcU)); + vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__tag_data_access__DOT__we + = ((0xfff0U & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__tag_data_access__DOT__we)) + | ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__tag_data_access__DOT__real_writefill) + ? 0xfU : (((0U == vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__wsel_st1 + [0U]) & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__tag_data_access__DOT__should_write)) + ? (0xfU & (IData)((vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__inst_meta_st1 + [0U] >> 2U))) + : 0U))); + vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__tag_data_access__DOT__we + = ((0xff0fU & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__tag_data_access__DOT__we)) + | (((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__tag_data_access__DOT__real_writefill) + ? 0xfU : (((1U == vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__wsel_st1 + [0U]) & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__tag_data_access__DOT__should_write)) + ? (0xfU & (IData)((vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__inst_meta_st1 + [0U] + >> 2U))) + : 0U)) << 4U)); + vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__tag_data_access__DOT__we + = ((0xf0ffU & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__tag_data_access__DOT__we)) + | (((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__tag_data_access__DOT__real_writefill) + ? 0xfU : (((2U == vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__wsel_st1 + [0U]) & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__tag_data_access__DOT__should_write)) + ? (0xfU & (IData)((vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__inst_meta_st1 + [0U] + >> 2U))) + : 0U)) << 8U)); + vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__tag_data_access__DOT__we + = ((0xfffU & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__tag_data_access__DOT__we)) + | (((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__tag_data_access__DOT__real_writefill) + ? 0xfU : (((3U == vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__wsel_st1 + [0U]) & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__tag_data_access__DOT__should_write)) + ? (0xfU & (IData)((vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__inst_meta_st1 + [0U] + >> 2U))) + : 0U)) << 0xcU)); + vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__tag_data_access__DOT__we + = ((0xfff0U & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__tag_data_access__DOT__we)) + | ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__tag_data_access__DOT__real_writefill) + ? 0xfU : (((0U == vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__wsel_st1 + [0U]) & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__tag_data_access__DOT__should_write)) + ? (0xfU & (IData)((vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__inst_meta_st1 + [0U] >> 2U))) + : 0U))); + vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__tag_data_access__DOT__we + = ((0xff0fU & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__tag_data_access__DOT__we)) + | (((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__tag_data_access__DOT__real_writefill) + ? 0xfU : (((1U == vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__wsel_st1 + [0U]) & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__tag_data_access__DOT__should_write)) + ? (0xfU & (IData)((vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__inst_meta_st1 + [0U] + >> 2U))) + : 0U)) << 4U)); + vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__tag_data_access__DOT__we + = ((0xf0ffU & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__tag_data_access__DOT__we)) + | (((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__tag_data_access__DOT__real_writefill) + ? 0xfU : (((2U == vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__wsel_st1 + [0U]) & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__tag_data_access__DOT__should_write)) + ? (0xfU & (IData)((vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__inst_meta_st1 + [0U] + >> 2U))) + : 0U)) << 8U)); + vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__tag_data_access__DOT__we + = ((0xfffU & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__tag_data_access__DOT__we)) + | (((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__tag_data_access__DOT__real_writefill) + ? 0xfU : (((3U == vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__wsel_st1 + [0U]) & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__tag_data_access__DOT__should_write)) + ? (0xfU & (IData)((vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__inst_meta_st1 + [0U] + >> 2U))) + : 0U)) << 0xcU)); + vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__tag_data_access__DOT__we + = ((0xfff0U & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__tag_data_access__DOT__we)) + | ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__tag_data_access__DOT__real_writefill) + ? 0xfU : (((0U == vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__wsel_st1 + [0U]) & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__tag_data_access__DOT__should_write)) + ? (0xfU & (IData)((vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__inst_meta_st1 + [0U] >> 2U))) + : 0U))); + vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__tag_data_access__DOT__we + = ((0xff0fU & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__tag_data_access__DOT__we)) + | (((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__tag_data_access__DOT__real_writefill) + ? 0xfU : (((1U == vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__wsel_st1 + [0U]) & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__tag_data_access__DOT__should_write)) + ? (0xfU & (IData)((vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__inst_meta_st1 + [0U] + >> 2U))) + : 0U)) << 4U)); + vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__tag_data_access__DOT__we + = ((0xf0ffU & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__tag_data_access__DOT__we)) + | (((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__tag_data_access__DOT__real_writefill) + ? 0xfU : (((2U == vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__wsel_st1 + [0U]) & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__tag_data_access__DOT__should_write)) + ? (0xfU & (IData)((vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__inst_meta_st1 + [0U] + >> 2U))) + : 0U)) << 8U)); + vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__tag_data_access__DOT__we + = ((0xfffU & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__tag_data_access__DOT__we)) + | (((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__tag_data_access__DOT__real_writefill) + ? 0xfU : (((3U == vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__wsel_st1 + [0U]) & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__tag_data_access__DOT__should_write)) + ? (0xfU & (IData)((vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__inst_meta_st1 + [0U] + >> 2U))) + : 0U)) << 0xcU)); + vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__tag_data_access__DOT__use_write_enable + = ((vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__is_fill_st1 + [0U] & (~ (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__tag_data_access__DOT__real_writefill))) + ? 0U : (0xffffU & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__tag_data_access__DOT__we))); + vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__tag_data_access__DOT__use_write_enable + = ((vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__is_fill_st1 + [0U] & (~ (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__tag_data_access__DOT__real_writefill))) + ? 0U : (0xffffU & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__tag_data_access__DOT__we))); + vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__tag_data_access__DOT__use_write_enable + = ((vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__is_fill_st1 + [0U] & (~ (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__tag_data_access__DOT__real_writefill))) + ? 0U : (0xffffU & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__tag_data_access__DOT__we))); + vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__tag_data_access__DOT__use_write_enable + = ((vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__is_fill_st1 + [0U] & (~ (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__tag_data_access__DOT__real_writefill))) + ? 0U : (0xffffU & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__tag_data_access__DOT__we))); +} + +VL_INLINE_OPT void VVX_cache::_sequent__TOP__4(VVX_cache__Syms* __restrict vlSymsp) { + VL_DEBUG_IF(VL_DBG_MSGF("+ VVX_cache::_sequent__TOP__4\n"); ); + VVX_cache* __restrict vlTOPp VL_ATTR_UNUSED = vlSymsp->TOPp; + // Variables + CData/*2:0*/ __Vdly__VX_cache__DOT__cache_dram_req_arb__DOT__dram_fill_arb__DOT__dfqq_queue__DOT__size_r; + CData/*1:0*/ __Vdly__VX_cache__DOT__cache_dram_req_arb__DOT__dram_fill_arb__DOT__dfqq_queue__DOT__genblk3__DOT__genblk2__DOT__wr_ptr_r; + CData/*1:0*/ __Vdly__VX_cache__DOT__cache_dram_req_arb__DOT__dram_fill_arb__DOT__dfqq_queue__DOT__genblk3__DOT__genblk2__DOT__rd_ptr_r; + CData/*1:0*/ __Vdly__VX_cache__DOT__cache_dram_req_arb__DOT__dram_fill_arb__DOT__dfqq_queue__DOT__genblk3__DOT__genblk2__DOT__rd_ptr_next_r; + CData/*0:0*/ __Vdly__VX_cache__DOT__cache_dram_req_arb__DOT__dram_fill_arb__DOT__dfqq_queue__DOT__genblk3__DOT__genblk2__DOT__empty_r; + CData/*1:0*/ __Vdlyvdim0__VX_cache__DOT__cache_dram_req_arb__DOT__dram_fill_arb__DOT__dfqq_queue__DOT__genblk3__DOT__data__v0; + CData/*0:0*/ __Vdlyvset__VX_cache__DOT__cache_dram_req_arb__DOT__dram_fill_arb__DOT__dfqq_queue__DOT__genblk3__DOT__data__v0; + CData/*0:0*/ __Vdly__VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__dwbq_dual_valid_sel; + CData/*4:0*/ __Vdly__VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__snp_req_queue__DOT__size_r; + CData/*3:0*/ __Vdly__VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__snp_req_queue__DOT__genblk3__DOT__genblk2__DOT__wr_ptr_r; + CData/*3:0*/ __Vdly__VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__snp_req_queue__DOT__genblk3__DOT__genblk2__DOT__rd_ptr_r; + CData/*3:0*/ __Vdly__VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__snp_req_queue__DOT__genblk3__DOT__genblk2__DOT__rd_ptr_next_r; + CData/*0:0*/ __Vdly__VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__snp_req_queue__DOT__genblk3__DOT__genblk2__DOT__empty_r; + CData/*3:0*/ __Vdlyvdim0__VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__snp_req_queue__DOT__genblk3__DOT__data__v0; + CData/*0:0*/ __Vdlyvset__VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__snp_req_queue__DOT__genblk3__DOT__data__v0; + CData/*4:0*/ __Vdly__VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__dfp_queue__DOT__size_r; + CData/*3:0*/ __Vdly__VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__dfp_queue__DOT__genblk3__DOT__genblk2__DOT__wr_ptr_r; + CData/*3:0*/ __Vdly__VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__dfp_queue__DOT__genblk3__DOT__genblk2__DOT__rd_ptr_r; + CData/*3:0*/ __Vdly__VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__dfp_queue__DOT__genblk3__DOT__genblk2__DOT__rd_ptr_next_r; + CData/*0:0*/ __Vdly__VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__dfp_queue__DOT__genblk3__DOT__genblk2__DOT__empty_r; + CData/*3:0*/ __Vdlyvdim0__VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__dfp_queue__DOT__genblk3__DOT__data__v0; + CData/*0:0*/ __Vdlyvset__VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__dfp_queue__DOT__genblk3__DOT__data__v0; + CData/*2:0*/ __Vdly__VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__size_r; + CData/*1:0*/ __Vdly__VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__wr_ptr_r; + CData/*1:0*/ __Vdly__VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__rd_ptr_r; + CData/*1:0*/ __Vdly__VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__rd_ptr_next_r; + CData/*0:0*/ __Vdly__VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__empty_r; + CData/*1:0*/ __Vdlyvdim0__VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__data__v0; + CData/*0:0*/ __Vdlyvset__VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__data__v0; + CData/*5:0*/ __Vdlyvdim0__VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__dirtyb__v0; + SData/*15:0*/ __Vdlyvval__VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__dirtyb__v0; + CData/*0:0*/ __Vdlyvset__VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__dirtyb__v0; + CData/*5:0*/ __Vdlyvdim0__VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__dirtyb__v1; + CData/*0:0*/ __Vdlyvset__VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__dirtyb__v1; + CData/*5:0*/ __Vdlyvdim0__VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__data__v0; + CData/*6:0*/ __Vdlyvlsb__VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__data__v0; + CData/*7:0*/ __Vdlyvval__VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__data__v0; + CData/*0:0*/ __Vdlyvset__VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__data__v0; + CData/*5:0*/ __Vdlyvdim0__VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__data__v1; + CData/*6:0*/ __Vdlyvlsb__VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__data__v1; + CData/*7:0*/ __Vdlyvval__VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__data__v1; + CData/*0:0*/ __Vdlyvset__VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__data__v1; + CData/*5:0*/ __Vdlyvdim0__VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__data__v2; + CData/*6:0*/ __Vdlyvlsb__VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__data__v2; + CData/*7:0*/ __Vdlyvval__VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__data__v2; + CData/*0:0*/ __Vdlyvset__VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__data__v2; + CData/*5:0*/ __Vdlyvdim0__VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__data__v3; + CData/*6:0*/ __Vdlyvlsb__VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__data__v3; + CData/*7:0*/ __Vdlyvval__VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__data__v3; + CData/*0:0*/ __Vdlyvset__VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__data__v3; + CData/*5:0*/ __Vdlyvdim0__VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__data__v4; + CData/*6:0*/ __Vdlyvlsb__VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__data__v4; + CData/*7:0*/ __Vdlyvval__VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__data__v4; + CData/*0:0*/ __Vdlyvset__VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__data__v4; + CData/*5:0*/ __Vdlyvdim0__VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__data__v5; + CData/*6:0*/ __Vdlyvlsb__VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__data__v5; + CData/*7:0*/ __Vdlyvval__VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__data__v5; + CData/*0:0*/ __Vdlyvset__VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__data__v5; + CData/*5:0*/ __Vdlyvdim0__VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__data__v6; 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+ QData/*54:0*/ __Vdlyvval__VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__snp_req_queue__DOT__genblk3__DOT__data__v0; + // Body + __Vdly__VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cache_miss_resrv__DOT__tail_ptr + = vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cache_miss_resrv__DOT__tail_ptr; + __Vdly__VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__cache_miss_resrv__DOT__tail_ptr + = vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__cache_miss_resrv__DOT__tail_ptr; + __Vdly__VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__cache_miss_resrv__DOT__tail_ptr + = vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__cache_miss_resrv__DOT__tail_ptr; + __Vdly__VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cache_miss_resrv__DOT__tail_ptr + = vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cache_miss_resrv__DOT__tail_ptr; + __Vdly__VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__snp_req_queue__DOT__genblk3__DOT__genblk2__DOT__rd_ptr_next_r + = vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__snp_req_queue__DOT__genblk3__DOT__genblk2__DOT__rd_ptr_next_r; + __Vdly__VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__snp_req_queue__DOT__genblk3__DOT__genblk2__DOT__rd_ptr_r + = vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__snp_req_queue__DOT__genblk3__DOT__genblk2__DOT__rd_ptr_r; + __Vdly__VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__snp_req_queue__DOT__genblk3__DOT__genblk2__DOT__wr_ptr_r + = vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__snp_req_queue__DOT__genblk3__DOT__genblk2__DOT__wr_ptr_r; + __Vdly__VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__snp_req_queue__DOT__size_r + = vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__snp_req_queue__DOT__size_r; + __Vdly__VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__snp_req_queue__DOT__genblk3__DOT__genblk2__DOT__rd_ptr_next_r + = vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__snp_req_queue__DOT__genblk3__DOT__genblk2__DOT__rd_ptr_next_r; + __Vdly__VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__snp_req_queue__DOT__genblk3__DOT__genblk2__DOT__rd_ptr_r + = vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__snp_req_queue__DOT__genblk3__DOT__genblk2__DOT__rd_ptr_r; + __Vdly__VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__snp_req_queue__DOT__genblk3__DOT__genblk2__DOT__wr_ptr_r + = vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__snp_req_queue__DOT__genblk3__DOT__genblk2__DOT__wr_ptr_r; + __Vdly__VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__snp_req_queue__DOT__size_r + = vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__snp_req_queue__DOT__size_r; + __Vdly__VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__snp_req_queue__DOT__genblk3__DOT__genblk2__DOT__rd_ptr_next_r + = vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__snp_req_queue__DOT__genblk3__DOT__genblk2__DOT__rd_ptr_next_r; + __Vdly__VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__snp_req_queue__DOT__genblk3__DOT__genblk2__DOT__rd_ptr_r + = vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__snp_req_queue__DOT__genblk3__DOT__genblk2__DOT__rd_ptr_r; + __Vdly__VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__snp_req_queue__DOT__genblk3__DOT__genblk2__DOT__wr_ptr_r + = vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__snp_req_queue__DOT__genblk3__DOT__genblk2__DOT__wr_ptr_r; + __Vdly__VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__snp_req_queue__DOT__size_r + = vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__snp_req_queue__DOT__size_r; + __Vdly__VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__snp_req_queue__DOT__genblk3__DOT__genblk2__DOT__rd_ptr_next_r + = vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__snp_req_queue__DOT__genblk3__DOT__genblk2__DOT__rd_ptr_next_r; + __Vdly__VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__snp_req_queue__DOT__genblk3__DOT__genblk2__DOT__rd_ptr_r + = vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__snp_req_queue__DOT__genblk3__DOT__genblk2__DOT__rd_ptr_r; + __Vdly__VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__snp_req_queue__DOT__genblk3__DOT__genblk2__DOT__wr_ptr_r + = vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__snp_req_queue__DOT__genblk3__DOT__genblk2__DOT__wr_ptr_r; + __Vdly__VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__snp_req_queue__DOT__size_r + = vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__snp_req_queue__DOT__size_r; + __Vdlyvset__VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__snp_req_queue__DOT__genblk3__DOT__data__v0 = 0U; + __Vdlyvset__VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__snp_req_queue__DOT__genblk3__DOT__data__v0 = 0U; + __Vdlyvset__VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__snp_req_queue__DOT__genblk3__DOT__data__v0 = 0U; + __Vdlyvset__VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__snp_req_queue__DOT__genblk3__DOT__data__v0 = 0U; + __Vdly__VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__rd_ptr_next_r + = vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__rd_ptr_next_r; + __Vdly__VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__rd_ptr_r + = vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__rd_ptr_r; + __Vdly__VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__wr_ptr_r + = vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__wr_ptr_r; + __Vdly__VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__size_r + = vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__size_r; + __Vdly__VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__rd_ptr_next_r + = vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__rd_ptr_next_r; + __Vdly__VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__rd_ptr_r + = vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__rd_ptr_r; + __Vdly__VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__wr_ptr_r + = vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__wr_ptr_r; + __Vdly__VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__size_r + = vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__size_r; + __Vdly__VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__rd_ptr_next_r + = vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__rd_ptr_next_r; + __Vdly__VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__rd_ptr_r + = vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__rd_ptr_r; + __Vdly__VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__wr_ptr_r + = vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__wr_ptr_r; + __Vdly__VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__size_r + = vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__size_r; + __Vdly__VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__rd_ptr_next_r + = vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__rd_ptr_next_r; + __Vdly__VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__rd_ptr_r + = vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__rd_ptr_r; + __Vdly__VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__wr_ptr_r + = vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__wr_ptr_r; + __Vdly__VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__size_r + = vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__size_r; + __Vdlyvset__VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__data__v0 = 0U; + __Vdlyvset__VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__data__v0 = 0U; + __Vdlyvset__VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__data__v0 = 0U; + __Vdlyvset__VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__data__v0 = 0U; + __Vdly__VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__snp_req_queue__DOT__genblk3__DOT__genblk2__DOT__empty_r + = vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__snp_req_queue__DOT__genblk3__DOT__genblk2__DOT__empty_r; + __Vdly__VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__snp_req_queue__DOT__genblk3__DOT__genblk2__DOT__empty_r + = vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__snp_req_queue__DOT__genblk3__DOT__genblk2__DOT__empty_r; + __Vdly__VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__snp_req_queue__DOT__genblk3__DOT__genblk2__DOT__empty_r + = vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__snp_req_queue__DOT__genblk3__DOT__genblk2__DOT__empty_r; + __Vdly__VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__snp_req_queue__DOT__genblk3__DOT__genblk2__DOT__empty_r + = vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__snp_req_queue__DOT__genblk3__DOT__genblk2__DOT__empty_r; + __Vdly__VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__empty_r + = vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__empty_r; + __Vdly__VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__empty_r + = vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__empty_r; + __Vdly__VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__empty_r + = vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__empty_r; + __Vdly__VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__empty_r + = vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__empty_r; + __Vdly__VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cwb_queue__DOT__genblk3__DOT__genblk2__DOT__rd_ptr_next_r + = vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cwb_queue__DOT__genblk3__DOT__genblk2__DOT__rd_ptr_next_r; + __Vdly__VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cwb_queue__DOT__genblk3__DOT__genblk2__DOT__rd_ptr_r + = vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cwb_queue__DOT__genblk3__DOT__genblk2__DOT__rd_ptr_r; + __Vdly__VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cwb_queue__DOT__genblk3__DOT__genblk2__DOT__wr_ptr_r + = vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cwb_queue__DOT__genblk3__DOT__genblk2__DOT__wr_ptr_r; + __Vdly__VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cwb_queue__DOT__size_r + = vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cwb_queue__DOT__size_r; + __Vdly__VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__cwb_queue__DOT__genblk3__DOT__genblk2__DOT__rd_ptr_next_r + = vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__cwb_queue__DOT__genblk3__DOT__genblk2__DOT__rd_ptr_next_r; + __Vdly__VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__cwb_queue__DOT__genblk3__DOT__genblk2__DOT__rd_ptr_r + = vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__cwb_queue__DOT__genblk3__DOT__genblk2__DOT__rd_ptr_r; + __Vdly__VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__cwb_queue__DOT__genblk3__DOT__genblk2__DOT__wr_ptr_r + = vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__cwb_queue__DOT__genblk3__DOT__genblk2__DOT__wr_ptr_r; + __Vdly__VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__cwb_queue__DOT__size_r + = vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__cwb_queue__DOT__size_r; + __Vdly__VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__cwb_queue__DOT__genblk3__DOT__genblk2__DOT__rd_ptr_next_r + = vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__cwb_queue__DOT__genblk3__DOT__genblk2__DOT__rd_ptr_next_r; + __Vdly__VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__cwb_queue__DOT__genblk3__DOT__genblk2__DOT__rd_ptr_r + = vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__cwb_queue__DOT__genblk3__DOT__genblk2__DOT__rd_ptr_r; + __Vdly__VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__cwb_queue__DOT__genblk3__DOT__genblk2__DOT__wr_ptr_r + = vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__cwb_queue__DOT__genblk3__DOT__genblk2__DOT__wr_ptr_r; + __Vdly__VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__cwb_queue__DOT__size_r + = vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__cwb_queue__DOT__size_r; + __Vdly__VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cwb_queue__DOT__genblk3__DOT__genblk2__DOT__rd_ptr_next_r + = vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cwb_queue__DOT__genblk3__DOT__genblk2__DOT__rd_ptr_next_r; + __Vdly__VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cwb_queue__DOT__genblk3__DOT__genblk2__DOT__rd_ptr_r + = vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cwb_queue__DOT__genblk3__DOT__genblk2__DOT__rd_ptr_r; + __Vdly__VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cwb_queue__DOT__genblk3__DOT__genblk2__DOT__wr_ptr_r + = vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cwb_queue__DOT__genblk3__DOT__genblk2__DOT__wr_ptr_r; + __Vdly__VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cwb_queue__DOT__size_r + = vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cwb_queue__DOT__size_r; + __Vdlyvset__VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cwb_queue__DOT__genblk3__DOT__data__v0 = 0U; + __Vdlyvset__VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__cwb_queue__DOT__genblk3__DOT__data__v0 = 0U; + __Vdlyvset__VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__cwb_queue__DOT__genblk3__DOT__data__v0 = 0U; + __Vdlyvset__VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cwb_queue__DOT__genblk3__DOT__data__v0 = 0U; + __Vdly__VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__dfp_queue__DOT__genblk3__DOT__genblk2__DOT__rd_ptr_next_r + = vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__dfp_queue__DOT__genblk3__DOT__genblk2__DOT__rd_ptr_next_r; + __Vdly__VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__dfp_queue__DOT__genblk3__DOT__genblk2__DOT__rd_ptr_r + = vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__dfp_queue__DOT__genblk3__DOT__genblk2__DOT__rd_ptr_r; + __Vdly__VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__dfp_queue__DOT__genblk3__DOT__genblk2__DOT__wr_ptr_r + = vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__dfp_queue__DOT__genblk3__DOT__genblk2__DOT__wr_ptr_r; + __Vdly__VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__dfp_queue__DOT__size_r + = vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__dfp_queue__DOT__size_r; + __Vdly__VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__dfp_queue__DOT__genblk3__DOT__genblk2__DOT__rd_ptr_next_r + = vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__dfp_queue__DOT__genblk3__DOT__genblk2__DOT__rd_ptr_next_r; + __Vdly__VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__dfp_queue__DOT__genblk3__DOT__genblk2__DOT__rd_ptr_r + = vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__dfp_queue__DOT__genblk3__DOT__genblk2__DOT__rd_ptr_r; + __Vdly__VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__dfp_queue__DOT__genblk3__DOT__genblk2__DOT__wr_ptr_r + = vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__dfp_queue__DOT__genblk3__DOT__genblk2__DOT__wr_ptr_r; + __Vdly__VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__dfp_queue__DOT__size_r + = vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__dfp_queue__DOT__size_r; + __Vdly__VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__dfp_queue__DOT__genblk3__DOT__genblk2__DOT__rd_ptr_next_r + = vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__dfp_queue__DOT__genblk3__DOT__genblk2__DOT__rd_ptr_next_r; + __Vdly__VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__dfp_queue__DOT__genblk3__DOT__genblk2__DOT__rd_ptr_r + = vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__dfp_queue__DOT__genblk3__DOT__genblk2__DOT__rd_ptr_r; + __Vdly__VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__dfp_queue__DOT__genblk3__DOT__genblk2__DOT__wr_ptr_r + = vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__dfp_queue__DOT__genblk3__DOT__genblk2__DOT__wr_ptr_r; + __Vdly__VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__dfp_queue__DOT__size_r + = vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__dfp_queue__DOT__size_r; + __Vdly__VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__dfp_queue__DOT__genblk3__DOT__genblk2__DOT__rd_ptr_next_r + = vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__dfp_queue__DOT__genblk3__DOT__genblk2__DOT__rd_ptr_next_r; + __Vdly__VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__dfp_queue__DOT__genblk3__DOT__genblk2__DOT__rd_ptr_r + = vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__dfp_queue__DOT__genblk3__DOT__genblk2__DOT__rd_ptr_r; + __Vdly__VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__dfp_queue__DOT__genblk3__DOT__genblk2__DOT__wr_ptr_r + = vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__dfp_queue__DOT__genblk3__DOT__genblk2__DOT__wr_ptr_r; + __Vdly__VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__dfp_queue__DOT__size_r + = vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__dfp_queue__DOT__size_r; + __Vdlyvset__VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__dfp_queue__DOT__genblk3__DOT__data__v0 = 0U; + __Vdlyvset__VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__dfp_queue__DOT__genblk3__DOT__data__v0 = 0U; + __Vdlyvset__VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__dfp_queue__DOT__genblk3__DOT__data__v0 = 0U; + __Vdlyvset__VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__dfp_queue__DOT__genblk3__DOT__data__v0 = 0U; + __Vdly__VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cwb_queue__DOT__genblk3__DOT__genblk2__DOT__empty_r + = vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cwb_queue__DOT__genblk3__DOT__genblk2__DOT__empty_r; + __Vdly__VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__cwb_queue__DOT__genblk3__DOT__genblk2__DOT__empty_r + = vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__cwb_queue__DOT__genblk3__DOT__genblk2__DOT__empty_r; + __Vdly__VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__cwb_queue__DOT__genblk3__DOT__genblk2__DOT__empty_r + = vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__cwb_queue__DOT__genblk3__DOT__genblk2__DOT__empty_r; + __Vdly__VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cwb_queue__DOT__genblk3__DOT__genblk2__DOT__empty_r + = vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cwb_queue__DOT__genblk3__DOT__genblk2__DOT__empty_r; + __Vdly__VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__dfp_queue__DOT__genblk3__DOT__genblk2__DOT__empty_r + = vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__dfp_queue__DOT__genblk3__DOT__genblk2__DOT__empty_r; + __Vdly__VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__dfp_queue__DOT__genblk3__DOT__genblk2__DOT__empty_r + = vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__dfp_queue__DOT__genblk3__DOT__genblk2__DOT__empty_r; + __Vdly__VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__dfp_queue__DOT__genblk3__DOT__genblk2__DOT__empty_r + = vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__dfp_queue__DOT__genblk3__DOT__genblk2__DOT__empty_r; + __Vdly__VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__dfp_queue__DOT__genblk3__DOT__genblk2__DOT__empty_r + = vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__dfp_queue__DOT__genblk3__DOT__genblk2__DOT__empty_r; + __Vdly__VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cache_miss_resrv__DOT__size + = vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cache_miss_resrv__DOT__size; + __Vdly__VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__cache_miss_resrv__DOT__size + = vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__cache_miss_resrv__DOT__size; + __Vdly__VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__cache_miss_resrv__DOT__size + = vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__cache_miss_resrv__DOT__size; + __Vdly__VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cache_miss_resrv__DOT__size + = vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cache_miss_resrv__DOT__size; + __Vdly__VX_cache__DOT__cache_dram_req_arb__DOT__dram_fill_arb__DOT__dfqq_queue__DOT__genblk3__DOT__genblk2__DOT__rd_ptr_next_r + = vlTOPp->VX_cache__DOT__cache_dram_req_arb__DOT__dram_fill_arb__DOT__dfqq_queue__DOT__genblk3__DOT__genblk2__DOT__rd_ptr_next_r; + __Vdly__VX_cache__DOT__cache_dram_req_arb__DOT__dram_fill_arb__DOT__dfqq_queue__DOT__genblk3__DOT__genblk2__DOT__rd_ptr_r + = vlTOPp->VX_cache__DOT__cache_dram_req_arb__DOT__dram_fill_arb__DOT__dfqq_queue__DOT__genblk3__DOT__genblk2__DOT__rd_ptr_r; + __Vdly__VX_cache__DOT__cache_dram_req_arb__DOT__dram_fill_arb__DOT__dfqq_queue__DOT__genblk3__DOT__genblk2__DOT__wr_ptr_r + = vlTOPp->VX_cache__DOT__cache_dram_req_arb__DOT__dram_fill_arb__DOT__dfqq_queue__DOT__genblk3__DOT__genblk2__DOT__wr_ptr_r; + __Vdly__VX_cache__DOT__cache_dram_req_arb__DOT__dram_fill_arb__DOT__dfqq_queue__DOT__size_r + = vlTOPp->VX_cache__DOT__cache_dram_req_arb__DOT__dram_fill_arb__DOT__dfqq_queue__DOT__size_r; + __Vdlyvset__VX_cache__DOT__cache_dram_req_arb__DOT__dram_fill_arb__DOT__dfqq_queue__DOT__genblk3__DOT__data__v0 = 0U; + __Vdly__VX_cache__DOT__cache_dram_req_arb__DOT__dram_fill_arb__DOT__dfqq_queue__DOT__genblk3__DOT__genblk2__DOT__empty_r + = vlTOPp->VX_cache__DOT__cache_dram_req_arb__DOT__dram_fill_arb__DOT__dfqq_queue__DOT__genblk3__DOT__genblk2__DOT__empty_r; + __Vdly__VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr + = vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr; + __Vdly__VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr + = vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr; + __Vdly__VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr + = vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr; + __Vdly__VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr + = vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr; + __Vdly__VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cache_miss_resrv__DOT__ready_table + = vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cache_miss_resrv__DOT__ready_table; + __Vdly__VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__cache_miss_resrv__DOT__ready_table + = vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__cache_miss_resrv__DOT__ready_table; + __Vdly__VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__cache_miss_resrv__DOT__ready_table + = vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__cache_miss_resrv__DOT__ready_table; + __Vdly__VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cache_miss_resrv__DOT__ready_table + = vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cache_miss_resrv__DOT__ready_table; + __Vdly__VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__dwbq_dual_valid_sel + = vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__dwbq_dual_valid_sel; + __Vdly__VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__dwbq_dual_valid_sel + = vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__dwbq_dual_valid_sel; + __Vdly__VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__dwbq_dual_valid_sel + = vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__dwbq_dual_valid_sel; + __Vdly__VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__dwbq_dual_valid_sel + = vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__dwbq_dual_valid_sel; + __Vdly__VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__genblk2__DOT__rd_ptr_next_r + = vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__genblk2__DOT__rd_ptr_next_r; + __Vdly__VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__genblk2__DOT__rd_ptr_r + = vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__genblk2__DOT__rd_ptr_r; + __Vdly__VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__genblk2__DOT__wr_ptr_r + = vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__genblk2__DOT__wr_ptr_r; + __Vdly__VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__dwb_queue__DOT__size_r + = vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__dwb_queue__DOT__size_r; + __Vdly__VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__genblk2__DOT__rd_ptr_next_r + = vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__genblk2__DOT__rd_ptr_next_r; + __Vdly__VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__genblk2__DOT__rd_ptr_r + = vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__genblk2__DOT__rd_ptr_r; + __Vdly__VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__genblk2__DOT__wr_ptr_r + = vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__genblk2__DOT__wr_ptr_r; + __Vdly__VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__dwb_queue__DOT__size_r + = vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__dwb_queue__DOT__size_r; + __Vdly__VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__genblk2__DOT__rd_ptr_next_r + = vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__genblk2__DOT__rd_ptr_next_r; + __Vdly__VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__genblk2__DOT__rd_ptr_r + = vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__genblk2__DOT__rd_ptr_r; + __Vdly__VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__genblk2__DOT__wr_ptr_r + = vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__genblk2__DOT__wr_ptr_r; + __Vdly__VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__dwb_queue__DOT__size_r + = vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__dwb_queue__DOT__size_r; + __Vdly__VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__genblk2__DOT__rd_ptr_next_r + = vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__genblk2__DOT__rd_ptr_next_r; + __Vdly__VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__genblk2__DOT__rd_ptr_r + = vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__genblk2__DOT__rd_ptr_r; + __Vdly__VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__genblk2__DOT__wr_ptr_r + = vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__genblk2__DOT__wr_ptr_r; + __Vdly__VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__dwb_queue__DOT__size_r + = vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__dwb_queue__DOT__size_r; + __Vdlyvset__VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__data__v0 = 0U; + __Vdlyvset__VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__data__v0 = 0U; + __Vdlyvset__VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__data__v0 = 0U; + __Vdlyvset__VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__data__v0 = 0U; + __Vdly__VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__genblk2__DOT__empty_r + = vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__genblk2__DOT__empty_r; + __Vdly__VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__genblk2__DOT__empty_r + = vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__genblk2__DOT__empty_r; + __Vdly__VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__genblk2__DOT__empty_r + = vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__genblk2__DOT__empty_r; + __Vdly__VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__genblk2__DOT__empty_r + = vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__genblk2__DOT__empty_r; + __Vdly__VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cache_miss_resrv__DOT__head_ptr + = vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cache_miss_resrv__DOT__head_ptr; + __Vdly__VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__cache_miss_resrv__DOT__head_ptr + = vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__cache_miss_resrv__DOT__head_ptr; + __Vdly__VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__cache_miss_resrv__DOT__head_ptr + = vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__cache_miss_resrv__DOT__head_ptr; + __Vdly__VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cache_miss_resrv__DOT__head_ptr + = vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cache_miss_resrv__DOT__head_ptr; + __Vdlyvset__VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cache_miss_resrv__DOT__metadata_table__v0 = 0U; + __Vdlyvset__VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__cache_miss_resrv__DOT__metadata_table__v0 = 0U; + __Vdlyvset__VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__cache_miss_resrv__DOT__metadata_table__v0 = 0U; + __Vdlyvset__VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cache_miss_resrv__DOT__metadata_table__v0 = 0U; + __Vdlyvset__VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__tag__v0 = 0U; + __Vdlyvset__VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__tag__v0 = 0U; + __Vdlyvset__VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__tag__v0 = 0U; + __Vdlyvset__VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__tag__v0 = 0U; + __Vdlyvset__VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__dirtyb__v0 = 0U; + __Vdlyvset__VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__dirtyb__v1 = 0U; + __Vdlyvset__VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__dirtyb__v0 = 0U; + __Vdlyvset__VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__dirtyb__v1 = 0U; + __Vdlyvset__VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__dirtyb__v0 = 0U; + __Vdlyvset__VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__dirtyb__v1 = 0U; + __Vdlyvset__VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__dirtyb__v0 = 0U; + __Vdlyvset__VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__dirtyb__v1 = 0U; + if (vlTOPp->reset) { + vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__i = 0x40U; + } else { + if ((1U & (~ (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__stall_bank_pipe)))) { + vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__i = 4U; + } + } + if ((1U & (~ (IData)(vlTOPp->reset)))) { + if ((1U & (~ (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__stall_bank_pipe)))) { + vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__j = 4U; + } + } + if (vlTOPp->reset) { + vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__i = 0x40U; + } else { + if ((1U & (~ (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__stall_bank_pipe)))) { + vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__i = 4U; + } + } + if ((1U & (~ (IData)(vlTOPp->reset)))) { + if ((1U & (~ (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__stall_bank_pipe)))) { + vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__j = 4U; + } + } + if (vlTOPp->reset) { + vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__i = 0x40U; + } else { + if ((1U & (~ (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__stall_bank_pipe)))) { + vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__i = 4U; + } + } + if ((1U & (~ (IData)(vlTOPp->reset)))) { + if ((1U & (~ (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__stall_bank_pipe)))) { + vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__j = 4U; + } + } + if (vlTOPp->reset) { + vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__i = 0x40U; + } else { + if ((1U & (~ (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__stall_bank_pipe)))) { + vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__i = 4U; + } + } + if ((1U & (~ (IData)(vlTOPp->reset)))) { + if ((1U & (~ (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__stall_bank_pipe)))) { + vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__j = 4U; + } + } + __Vdlyvset__VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__data__v0 = 0U; + __Vdlyvset__VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__data__v1 = 0U; + __Vdlyvset__VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__data__v2 = 0U; + __Vdlyvset__VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__data__v3 = 0U; + __Vdlyvset__VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__data__v4 = 0U; + __Vdlyvset__VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__data__v5 = 0U; + __Vdlyvset__VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__data__v6 = 0U; + __Vdlyvset__VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__data__v7 = 0U; + __Vdlyvset__VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__data__v8 = 0U; + __Vdlyvset__VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__data__v9 = 0U; + __Vdlyvset__VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__data__v10 = 0U; + __Vdlyvset__VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__data__v11 = 0U; + __Vdlyvset__VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__data__v12 = 0U; + __Vdlyvset__VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__data__v13 = 0U; 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+ vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__core_req_arb__DOT__use_per_writedata[3U] + = ((vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__core_req_arb__DOT____Vcellout__reqq_queue__data_out[5U] + << 0x16U) | (vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__core_req_arb__DOT____Vcellout__reqq_queue__data_out[4U] + >> 0xaU)); + } + } + if ((1U & (~ (IData)(vlTOPp->reset)))) { + if (vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__core_req_arb__DOT__pop_qual) { + vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__core_req_arb__DOT__use_per_byteen + = (0xffffU & (vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__core_req_arb__DOT____Vcellout__reqq_queue__data_out[9U] + >> 2U)); + } + } + if ((1U & (~ (IData)(vlTOPp->reset)))) { + if (vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__core_req_arb__DOT__pop_qual) { + vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__core_req_arb__DOT__use_per_tag + = (VL_ULL(0x3ffffffffff) & (((QData)((IData)( + vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__core_req_arb__DOT____Vcellout__reqq_queue__data_out[1U])) + << 0x20U) + | (QData)((IData)( + vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__core_req_arb__DOT____Vcellout__reqq_queue__data_out[0U])))); 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+ vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__core_req_arb__DOT__use_per_writedata[3U] + = ((vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__core_req_arb__DOT____Vcellout__reqq_queue__data_out[5U] + << 0x16U) | (vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__core_req_arb__DOT____Vcellout__reqq_queue__data_out[4U] + >> 0xaU)); + } + } + if ((1U & (~ (IData)(vlTOPp->reset)))) { + if (vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__core_req_arb__DOT__pop_qual) { + vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__core_req_arb__DOT__use_per_byteen + = (0xffffU & (vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__core_req_arb__DOT____Vcellout__reqq_queue__data_out[9U] + >> 2U)); + } + } + if ((1U & (~ (IData)(vlTOPp->reset)))) { + if (vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__core_req_arb__DOT__pop_qual) { + vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__core_req_arb__DOT__use_per_tag + = (VL_ULL(0x3ffffffffff) & (((QData)((IData)( + vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__core_req_arb__DOT____Vcellout__reqq_queue__data_out[1U])) + << 0x20U) + | (QData)((IData)( + vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__core_req_arb__DOT____Vcellout__reqq_queue__data_out[0U])))); + } + } + if ((1U & (~ (IData)(vlTOPp->reset)))) { + if (vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__core_req_arb__DOT__pop_qual) { + vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__core_req_arb__DOT__use_per_writedata[0U] + = ((vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__core_req_arb__DOT____Vcellout__reqq_queue__data_out[2U] + << 0x16U) | (vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__core_req_arb__DOT____Vcellout__reqq_queue__data_out[1U] + >> 0xaU)); + vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__core_req_arb__DOT__use_per_writedata[1U] + = ((vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__core_req_arb__DOT____Vcellout__reqq_queue__data_out[3U] + << 0x16U) | (vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__core_req_arb__DOT____Vcellout__reqq_queue__data_out[2U] + >> 0xaU)); + vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__core_req_arb__DOT__use_per_writedata[2U] + = ((vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__core_req_arb__DOT____Vcellout__reqq_queue__data_out[4U] + << 0x16U) | (vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__core_req_arb__DOT____Vcellout__reqq_queue__data_out[3U] + >> 0xaU)); + vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__core_req_arb__DOT__use_per_writedata[3U] + = ((vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__core_req_arb__DOT____Vcellout__reqq_queue__data_out[5U] + << 0x16U) | (vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__core_req_arb__DOT____Vcellout__reqq_queue__data_out[4U] + >> 0xaU)); + } + } + if ((1U & (~ (IData)(vlTOPp->reset)))) { + if (vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__core_req_arb__DOT__pop_qual) { + vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__core_req_arb__DOT__use_per_byteen + = (0xffffU & (vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__core_req_arb__DOT____Vcellout__reqq_queue__data_out[9U] + >> 2U)); + } + } + if (vlTOPp->reset) { + vlTOPp->VX_cache__DOT__cache_dram_req_arb__DOT__prfqq__DOT__use_addr = 0U; + } else { + if (vlTOPp->VX_cache__DOT__cache_dram_req_arb__DOT__prfqq__DOT__update_use) { + vlTOPp->VX_cache__DOT__cache_dram_req_arb__DOT__prfqq__DOT__use_addr + = (0xfffffffU & ((IData)(0x10U) + vlTOPp->VX_cache__DOT__cache_dram_req_arb__DOT__prfqq__DOT__pfq_queue__DOT__genblk2__DOT__head_r)); + } + } + if ((1U & (~ (IData)(vlTOPp->reset)))) { + if (vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__core_req_arb__DOT__pop_qual) { + vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__core_req_arb__DOT__use_per_rw + = (0xfU & (vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__core_req_arb__DOT____Vcellout__reqq_queue__data_out[9U] + >> 0x12U)); + } + } + if ((1U & (~ (IData)(vlTOPp->reset)))) { + if (vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__core_req_arb__DOT__pop_qual) { + vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__core_req_arb__DOT__use_per_addr[0U] + = ((vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__core_req_arb__DOT____Vcellout__reqq_queue__data_out[6U] + << 0x16U) | (vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__core_req_arb__DOT____Vcellout__reqq_queue__data_out[5U] + >> 0xaU)); + vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__core_req_arb__DOT__use_per_addr[1U] + = ((vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__core_req_arb__DOT____Vcellout__reqq_queue__data_out[7U] + << 0x16U) | (vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__core_req_arb__DOT____Vcellout__reqq_queue__data_out[6U] + >> 0xaU)); + vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__core_req_arb__DOT__use_per_addr[2U] + = ((vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__core_req_arb__DOT____Vcellout__reqq_queue__data_out[8U] + << 0x16U) | (vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__core_req_arb__DOT____Vcellout__reqq_queue__data_out[7U] + >> 0xaU)); + vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__core_req_arb__DOT__use_per_addr[3U] + = (0xffffffU & ((vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__core_req_arb__DOT____Vcellout__reqq_queue__data_out[9U] + << 0x16U) | (vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__core_req_arb__DOT____Vcellout__reqq_queue__data_out[8U] + >> 0xaU))); + } + } + if ((1U & (~ (IData)(vlTOPp->reset)))) { + if (vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__core_req_arb__DOT__pop_qual) { + vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__core_req_arb__DOT__use_per_rw + = (0xfU & (vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__core_req_arb__DOT____Vcellout__reqq_queue__data_out[9U] + >> 0x12U)); + } + } + if ((1U & (~ (IData)(vlTOPp->reset)))) { + if (vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__core_req_arb__DOT__pop_qual) { + vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__core_req_arb__DOT__use_per_addr[0U] + = ((vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__core_req_arb__DOT____Vcellout__reqq_queue__data_out[6U] + << 0x16U) | (vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__core_req_arb__DOT____Vcellout__reqq_queue__data_out[5U] + >> 0xaU)); + vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__core_req_arb__DOT__use_per_addr[1U] + = ((vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__core_req_arb__DOT____Vcellout__reqq_queue__data_out[7U] + << 0x16U) | (vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__core_req_arb__DOT____Vcellout__reqq_queue__data_out[6U] + >> 0xaU)); + vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__core_req_arb__DOT__use_per_addr[2U] + = ((vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__core_req_arb__DOT____Vcellout__reqq_queue__data_out[8U] + << 0x16U) | (vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__core_req_arb__DOT____Vcellout__reqq_queue__data_out[7U] + >> 0xaU)); + vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__core_req_arb__DOT__use_per_addr[3U] + = (0xffffffU & ((vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__core_req_arb__DOT____Vcellout__reqq_queue__data_out[9U] + << 0x16U) | (vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__core_req_arb__DOT____Vcellout__reqq_queue__data_out[8U] + >> 0xaU))); + } + } + if ((1U & (~ (IData)(vlTOPp->reset)))) { + if (vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__core_req_arb__DOT__pop_qual) { + vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__core_req_arb__DOT__use_per_rw + = (0xfU & (vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__core_req_arb__DOT____Vcellout__reqq_queue__data_out[9U] + >> 0x12U)); + } + } + if ((1U & (~ (IData)(vlTOPp->reset)))) { + if (vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__core_req_arb__DOT__pop_qual) { + vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__core_req_arb__DOT__use_per_addr[0U] + = ((vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__core_req_arb__DOT____Vcellout__reqq_queue__data_out[6U] + << 0x16U) | (vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__core_req_arb__DOT____Vcellout__reqq_queue__data_out[5U] + >> 0xaU)); + vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__core_req_arb__DOT__use_per_addr[1U] + = ((vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__core_req_arb__DOT____Vcellout__reqq_queue__data_out[7U] + << 0x16U) | (vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__core_req_arb__DOT____Vcellout__reqq_queue__data_out[6U] + >> 0xaU)); + vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__core_req_arb__DOT__use_per_addr[2U] + = ((vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__core_req_arb__DOT____Vcellout__reqq_queue__data_out[8U] + << 0x16U) | (vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__core_req_arb__DOT____Vcellout__reqq_queue__data_out[7U] + >> 0xaU)); + vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__core_req_arb__DOT__use_per_addr[3U] + = (0xffffffU & ((vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__core_req_arb__DOT____Vcellout__reqq_queue__data_out[9U] + << 0x16U) | (vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__core_req_arb__DOT____Vcellout__reqq_queue__data_out[8U] + >> 0xaU))); + } + } + if ((1U & (~ (IData)(vlTOPp->reset)))) { + if (vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__core_req_arb__DOT__pop_qual) { + vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__core_req_arb__DOT__use_per_rw + = (0xfU & (vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__core_req_arb__DOT____Vcellout__reqq_queue__data_out[9U] + >> 0x12U)); + } + } + if ((1U & (~ (IData)(vlTOPp->reset)))) { + if (vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__core_req_arb__DOT__pop_qual) { + vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__core_req_arb__DOT__use_per_addr[0U] + = ((vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__core_req_arb__DOT____Vcellout__reqq_queue__data_out[6U] + << 0x16U) | (vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__core_req_arb__DOT____Vcellout__reqq_queue__data_out[5U] + >> 0xaU)); + vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__core_req_arb__DOT__use_per_addr[1U] + = ((vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__core_req_arb__DOT____Vcellout__reqq_queue__data_out[7U] + << 0x16U) | (vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__core_req_arb__DOT____Vcellout__reqq_queue__data_out[6U] + >> 0xaU)); + vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__core_req_arb__DOT__use_per_addr[2U] + = ((vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__core_req_arb__DOT____Vcellout__reqq_queue__data_out[8U] + << 0x16U) | (vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__core_req_arb__DOT____Vcellout__reqq_queue__data_out[7U] + >> 0xaU)); + vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__core_req_arb__DOT__use_per_addr[3U] + = (0xffffffU & ((vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__core_req_arb__DOT____Vcellout__reqq_queue__data_out[9U] + << 0x16U) | (vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__core_req_arb__DOT____Vcellout__reqq_queue__data_out[8U] + >> 0xaU))); + } + } + if (vlTOPp->reset) { + vlTOPp->VX_cache__DOT__cache_dram_req_arb__DOT__dram_fill_arb__DOT__use_per_bank_dram_fill_req_addr[0U] = 0U; + vlTOPp->VX_cache__DOT__cache_dram_req_arb__DOT__dram_fill_arb__DOT__use_per_bank_dram_fill_req_addr[1U] = 0U; + vlTOPp->VX_cache__DOT__cache_dram_req_arb__DOT__dram_fill_arb__DOT__use_per_bank_dram_fill_req_addr[2U] = 0U; + vlTOPp->VX_cache__DOT__cache_dram_req_arb__DOT__dram_fill_arb__DOT__use_per_bank_dram_fill_req_addr[3U] = 0U; + } else { + if (((IData)(vlTOPp->VX_cache__DOT__cache_dram_req_arb__DOT__dfqq_pop) + & (IData)(vlTOPp->VX_cache__DOT__cache_dram_req_arb__DOT__dram_fill_arb__DOT__qual_has_request))) { + vlTOPp->VX_cache__DOT__cache_dram_req_arb__DOT__dram_fill_arb__DOT__use_per_bank_dram_fill_req_addr[0U] + = vlTOPp->VX_cache__DOT__cache_dram_req_arb__DOT__dram_fill_arb__DOT__qual_bank_dram_fill_req_addr[0U]; + vlTOPp->VX_cache__DOT__cache_dram_req_arb__DOT__dram_fill_arb__DOT__use_per_bank_dram_fill_req_addr[1U] + = vlTOPp->VX_cache__DOT__cache_dram_req_arb__DOT__dram_fill_arb__DOT__qual_bank_dram_fill_req_addr[1U]; + vlTOPp->VX_cache__DOT__cache_dram_req_arb__DOT__dram_fill_arb__DOT__use_per_bank_dram_fill_req_addr[2U] + = vlTOPp->VX_cache__DOT__cache_dram_req_arb__DOT__dram_fill_arb__DOT__qual_bank_dram_fill_req_addr[2U]; + vlTOPp->VX_cache__DOT__cache_dram_req_arb__DOT__dram_fill_arb__DOT__use_per_bank_dram_fill_req_addr[3U] + = vlTOPp->VX_cache__DOT__cache_dram_req_arb__DOT__dram_fill_arb__DOT__qual_bank_dram_fill_req_addr[3U]; + } + } + if (vlTOPp->reset) { + __Vdly__VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__snp_req_queue__DOT__size_r = 0U; + vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__snp_req_queue__DOT__genblk3__DOT__genblk2__DOT__head_r = VL_ULL(0); + vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__snp_req_queue__DOT__genblk3__DOT__genblk2__DOT__curr_r = VL_ULL(0); + __Vdly__VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__snp_req_queue__DOT__genblk3__DOT__genblk2__DOT__wr_ptr_r = 0U; + __Vdly__VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__snp_req_queue__DOT__genblk3__DOT__genblk2__DOT__rd_ptr_r = 0U; + __Vdly__VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__snp_req_queue__DOT__genblk3__DOT__genblk2__DOT__rd_ptr_next_r = 1U; + __Vdly__VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__snp_req_queue__DOT__genblk3__DOT__genblk2__DOT__empty_r = 1U; + vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__snp_req_queue__DOT__genblk3__DOT__genblk2__DOT__full_r = 0U; + } else { + if (vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__snp_req_queue__DOT__writing) { + __Vdlyvval__VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__snp_req_queue__DOT__genblk3__DOT__data__v0 + = vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT____Vcellinp__snp_req_queue__data_in; + __Vdlyvset__VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__snp_req_queue__DOT__genblk3__DOT__data__v0 = 1U; + __Vdlyvdim0__VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__snp_req_queue__DOT__genblk3__DOT__data__v0 + = vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__snp_req_queue__DOT__genblk3__DOT__genblk2__DOT__wr_ptr_r; + if ((1U & (~ (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__snp_req_queue__DOT__reading)))) { + __Vdly__VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__snp_req_queue__DOT__genblk3__DOT__genblk2__DOT__empty_r = 0U; + if ((0xfU == (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__snp_req_queue__DOT__size_r))) { + vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__snp_req_queue__DOT__genblk3__DOT__genblk2__DOT__full_r = 1U; + } + __Vdly__VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__snp_req_queue__DOT__size_r + = (0x1fU & ((IData)(1U) + (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__snp_req_queue__DOT__size_r))); + } + __Vdly__VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__snp_req_queue__DOT__genblk3__DOT__genblk2__DOT__wr_ptr_r + = (0xfU & ((IData)(1U) + (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__snp_req_queue__DOT__genblk3__DOT__genblk2__DOT__wr_ptr_r))); + } + vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__snp_req_queue__DOT__genblk3__DOT__genblk2__DOT__curr_r + = vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT____Vcellinp__snp_req_queue__data_in; + if (vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__snp_req_queue__DOT__reading) { + __Vdly__VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__snp_req_queue__DOT__genblk3__DOT__genblk2__DOT__rd_ptr_r + = vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__snp_req_queue__DOT__genblk3__DOT__genblk2__DOT__rd_ptr_next_r; + if ((1U & (~ (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__snp_req_queue__DOT__writing)))) { + if ((1U == (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__snp_req_queue__DOT__size_r))) { + if (Verilated::assertOn()) { + if (VL_UNLIKELY(((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__snp_req_queue__DOT__genblk3__DOT__genblk2__DOT__rd_ptr_next_r) + != (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__snp_req_queue__DOT__genblk3__DOT__genblk2__DOT__wr_ptr_r)))) { + VL_WRITEF("[%0t] %%Error: VX_generic_queue.v:144: Assertion failed in %NVX_cache.genblk5[3].bank.snp_req_queue.genblk3.genblk2: 'assert' failed.\n", + 64,VL_TIME_Q(), + vlSymsp->name()); + VL_STOP_MT("../../rtl/libs/VX_generic_queue.v", 144, ""); + } + } + __Vdly__VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__snp_req_queue__DOT__genblk3__DOT__genblk2__DOT__empty_r = 1U; + } + vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__snp_req_queue__DOT__genblk3__DOT__genblk2__DOT__full_r = 0U; + __Vdly__VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__snp_req_queue__DOT__size_r + = (0x1fU & ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__snp_req_queue__DOT__size_r) + - (IData)(1U))); + } + __Vdly__VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__snp_req_queue__DOT__genblk3__DOT__genblk2__DOT__rd_ptr_next_r + = (0xfU & ((IData)(2U) + (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__snp_req_queue__DOT__genblk3__DOT__genblk2__DOT__rd_ptr_r))); + } + vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__snp_req_queue__DOT__genblk3__DOT__genblk2__DOT__bypass_r + = ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__snp_req_queue__DOT__writing) + & ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__snp_req_queue__DOT__genblk3__DOT__genblk2__DOT__empty_r) + | ((1U == (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__snp_req_queue__DOT__size_r)) + & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__snp_req_queue__DOT__reading)))); + vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__snp_req_queue__DOT__genblk3__DOT__genblk2__DOT__head_r + = vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__snp_req_queue__DOT__genblk3__DOT__data + [((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__snp_req_queue__DOT__reading) + ? (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__snp_req_queue__DOT__genblk3__DOT__genblk2__DOT__rd_ptr_next_r) + : (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__snp_req_queue__DOT__genblk3__DOT__genblk2__DOT__rd_ptr_r))]; + } + if (vlTOPp->reset) { + __Vdly__VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__snp_req_queue__DOT__size_r = 0U; + vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__snp_req_queue__DOT__genblk3__DOT__genblk2__DOT__head_r = VL_ULL(0); + vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__snp_req_queue__DOT__genblk3__DOT__genblk2__DOT__curr_r = VL_ULL(0); + __Vdly__VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__snp_req_queue__DOT__genblk3__DOT__genblk2__DOT__wr_ptr_r = 0U; + __Vdly__VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__snp_req_queue__DOT__genblk3__DOT__genblk2__DOT__rd_ptr_r = 0U; + __Vdly__VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__snp_req_queue__DOT__genblk3__DOT__genblk2__DOT__rd_ptr_next_r = 1U; + __Vdly__VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__snp_req_queue__DOT__genblk3__DOT__genblk2__DOT__empty_r = 1U; + vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__snp_req_queue__DOT__genblk3__DOT__genblk2__DOT__full_r = 0U; + } else { + if (vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__snp_req_queue__DOT__writing) { + __Vdlyvval__VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__snp_req_queue__DOT__genblk3__DOT__data__v0 + = vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT____Vcellinp__snp_req_queue__data_in; + __Vdlyvset__VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__snp_req_queue__DOT__genblk3__DOT__data__v0 = 1U; + __Vdlyvdim0__VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__snp_req_queue__DOT__genblk3__DOT__data__v0 + = vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__snp_req_queue__DOT__genblk3__DOT__genblk2__DOT__wr_ptr_r; + if ((1U & (~ (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__snp_req_queue__DOT__reading)))) { + __Vdly__VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__snp_req_queue__DOT__genblk3__DOT__genblk2__DOT__empty_r = 0U; + if ((0xfU == (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__snp_req_queue__DOT__size_r))) { + vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__snp_req_queue__DOT__genblk3__DOT__genblk2__DOT__full_r = 1U; + } + __Vdly__VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__snp_req_queue__DOT__size_r + = (0x1fU & ((IData)(1U) + (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__snp_req_queue__DOT__size_r))); + } + __Vdly__VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__snp_req_queue__DOT__genblk3__DOT__genblk2__DOT__wr_ptr_r + = (0xfU & ((IData)(1U) + (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__snp_req_queue__DOT__genblk3__DOT__genblk2__DOT__wr_ptr_r))); + } + vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__snp_req_queue__DOT__genblk3__DOT__genblk2__DOT__curr_r + = vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT____Vcellinp__snp_req_queue__data_in; + if (vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__snp_req_queue__DOT__reading) { + __Vdly__VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__snp_req_queue__DOT__genblk3__DOT__genblk2__DOT__rd_ptr_r + = vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__snp_req_queue__DOT__genblk3__DOT__genblk2__DOT__rd_ptr_next_r; + if ((1U & (~ (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__snp_req_queue__DOT__writing)))) { + if ((1U == (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__snp_req_queue__DOT__size_r))) { + if (Verilated::assertOn()) { + if (VL_UNLIKELY(((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__snp_req_queue__DOT__genblk3__DOT__genblk2__DOT__rd_ptr_next_r) + != (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__snp_req_queue__DOT__genblk3__DOT__genblk2__DOT__wr_ptr_r)))) { + VL_WRITEF("[%0t] %%Error: VX_generic_queue.v:144: Assertion failed in %NVX_cache.genblk5[2].bank.snp_req_queue.genblk3.genblk2: 'assert' failed.\n", + 64,VL_TIME_Q(), + vlSymsp->name()); + VL_STOP_MT("../../rtl/libs/VX_generic_queue.v", 144, ""); + } + } + __Vdly__VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__snp_req_queue__DOT__genblk3__DOT__genblk2__DOT__empty_r = 1U; + } + vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__snp_req_queue__DOT__genblk3__DOT__genblk2__DOT__full_r = 0U; + __Vdly__VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__snp_req_queue__DOT__size_r + = (0x1fU & ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__snp_req_queue__DOT__size_r) + - (IData)(1U))); + } + __Vdly__VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__snp_req_queue__DOT__genblk3__DOT__genblk2__DOT__rd_ptr_next_r + = (0xfU & ((IData)(2U) + (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__snp_req_queue__DOT__genblk3__DOT__genblk2__DOT__rd_ptr_r))); + } + vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__snp_req_queue__DOT__genblk3__DOT__genblk2__DOT__bypass_r + = ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__snp_req_queue__DOT__writing) + & ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__snp_req_queue__DOT__genblk3__DOT__genblk2__DOT__empty_r) + | ((1U == (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__snp_req_queue__DOT__size_r)) + & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__snp_req_queue__DOT__reading)))); + vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__snp_req_queue__DOT__genblk3__DOT__genblk2__DOT__head_r + = vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__snp_req_queue__DOT__genblk3__DOT__data + [((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__snp_req_queue__DOT__reading) + ? (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__snp_req_queue__DOT__genblk3__DOT__genblk2__DOT__rd_ptr_next_r) + : (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__snp_req_queue__DOT__genblk3__DOT__genblk2__DOT__rd_ptr_r))]; + } + if (vlTOPp->reset) { + __Vdly__VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__snp_req_queue__DOT__size_r = 0U; + vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__snp_req_queue__DOT__genblk3__DOT__genblk2__DOT__head_r = VL_ULL(0); + vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__snp_req_queue__DOT__genblk3__DOT__genblk2__DOT__curr_r = VL_ULL(0); + __Vdly__VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__snp_req_queue__DOT__genblk3__DOT__genblk2__DOT__wr_ptr_r = 0U; + __Vdly__VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__snp_req_queue__DOT__genblk3__DOT__genblk2__DOT__rd_ptr_r = 0U; + __Vdly__VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__snp_req_queue__DOT__genblk3__DOT__genblk2__DOT__rd_ptr_next_r = 1U; + __Vdly__VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__snp_req_queue__DOT__genblk3__DOT__genblk2__DOT__empty_r = 1U; + vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__snp_req_queue__DOT__genblk3__DOT__genblk2__DOT__full_r = 0U; + } else { + if (vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__snp_req_queue__DOT__writing) { + __Vdlyvval__VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__snp_req_queue__DOT__genblk3__DOT__data__v0 + = vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT____Vcellinp__snp_req_queue__data_in; + __Vdlyvset__VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__snp_req_queue__DOT__genblk3__DOT__data__v0 = 1U; + __Vdlyvdim0__VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__snp_req_queue__DOT__genblk3__DOT__data__v0 + = vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__snp_req_queue__DOT__genblk3__DOT__genblk2__DOT__wr_ptr_r; + if ((1U & (~ (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__snp_req_queue__DOT__reading)))) { + __Vdly__VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__snp_req_queue__DOT__genblk3__DOT__genblk2__DOT__empty_r = 0U; + if ((0xfU == (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__snp_req_queue__DOT__size_r))) { + vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__snp_req_queue__DOT__genblk3__DOT__genblk2__DOT__full_r = 1U; + } + __Vdly__VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__snp_req_queue__DOT__size_r + = (0x1fU & ((IData)(1U) + (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__snp_req_queue__DOT__size_r))); + } + __Vdly__VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__snp_req_queue__DOT__genblk3__DOT__genblk2__DOT__wr_ptr_r + = (0xfU & ((IData)(1U) + (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__snp_req_queue__DOT__genblk3__DOT__genblk2__DOT__wr_ptr_r))); + } + vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__snp_req_queue__DOT__genblk3__DOT__genblk2__DOT__curr_r + = vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT____Vcellinp__snp_req_queue__data_in; + if (vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__snp_req_queue__DOT__reading) { + __Vdly__VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__snp_req_queue__DOT__genblk3__DOT__genblk2__DOT__rd_ptr_r + = vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__snp_req_queue__DOT__genblk3__DOT__genblk2__DOT__rd_ptr_next_r; + if ((1U & (~ (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__snp_req_queue__DOT__writing)))) { + if ((1U == (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__snp_req_queue__DOT__size_r))) { + if (Verilated::assertOn()) { + if (VL_UNLIKELY(((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__snp_req_queue__DOT__genblk3__DOT__genblk2__DOT__rd_ptr_next_r) + != (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__snp_req_queue__DOT__genblk3__DOT__genblk2__DOT__wr_ptr_r)))) { + VL_WRITEF("[%0t] %%Error: VX_generic_queue.v:144: Assertion failed in %NVX_cache.genblk5[1].bank.snp_req_queue.genblk3.genblk2: 'assert' failed.\n", + 64,VL_TIME_Q(), + vlSymsp->name()); + VL_STOP_MT("../../rtl/libs/VX_generic_queue.v", 144, ""); + } + } + __Vdly__VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__snp_req_queue__DOT__genblk3__DOT__genblk2__DOT__empty_r = 1U; + } + vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__snp_req_queue__DOT__genblk3__DOT__genblk2__DOT__full_r = 0U; + __Vdly__VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__snp_req_queue__DOT__size_r + = (0x1fU & ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__snp_req_queue__DOT__size_r) + - (IData)(1U))); + } + __Vdly__VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__snp_req_queue__DOT__genblk3__DOT__genblk2__DOT__rd_ptr_next_r + = (0xfU & ((IData)(2U) + (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__snp_req_queue__DOT__genblk3__DOT__genblk2__DOT__rd_ptr_r))); + } + vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__snp_req_queue__DOT__genblk3__DOT__genblk2__DOT__bypass_r + = ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__snp_req_queue__DOT__writing) + & ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__snp_req_queue__DOT__genblk3__DOT__genblk2__DOT__empty_r) + | ((1U == (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__snp_req_queue__DOT__size_r)) + & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__snp_req_queue__DOT__reading)))); + vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__snp_req_queue__DOT__genblk3__DOT__genblk2__DOT__head_r + = vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__snp_req_queue__DOT__genblk3__DOT__data + [((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__snp_req_queue__DOT__reading) + ? (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__snp_req_queue__DOT__genblk3__DOT__genblk2__DOT__rd_ptr_next_r) + : (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__snp_req_queue__DOT__genblk3__DOT__genblk2__DOT__rd_ptr_r))]; + } + if (vlTOPp->reset) { + __Vdly__VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__snp_req_queue__DOT__size_r = 0U; + vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__snp_req_queue__DOT__genblk3__DOT__genblk2__DOT__head_r = VL_ULL(0); + vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__snp_req_queue__DOT__genblk3__DOT__genblk2__DOT__curr_r = VL_ULL(0); + __Vdly__VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__snp_req_queue__DOT__genblk3__DOT__genblk2__DOT__wr_ptr_r = 0U; + __Vdly__VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__snp_req_queue__DOT__genblk3__DOT__genblk2__DOT__rd_ptr_r = 0U; + __Vdly__VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__snp_req_queue__DOT__genblk3__DOT__genblk2__DOT__rd_ptr_next_r = 1U; + __Vdly__VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__snp_req_queue__DOT__genblk3__DOT__genblk2__DOT__empty_r = 1U; + vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__snp_req_queue__DOT__genblk3__DOT__genblk2__DOT__full_r = 0U; + } else { + if (vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__snp_req_queue__DOT__writing) { + __Vdlyvval__VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__snp_req_queue__DOT__genblk3__DOT__data__v0 + = vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT____Vcellinp__snp_req_queue__data_in; + __Vdlyvset__VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__snp_req_queue__DOT__genblk3__DOT__data__v0 = 1U; + __Vdlyvdim0__VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__snp_req_queue__DOT__genblk3__DOT__data__v0 + = vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__snp_req_queue__DOT__genblk3__DOT__genblk2__DOT__wr_ptr_r; + if ((1U & (~ (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__snp_req_queue__DOT__reading)))) { + __Vdly__VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__snp_req_queue__DOT__genblk3__DOT__genblk2__DOT__empty_r = 0U; + if ((0xfU == (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__snp_req_queue__DOT__size_r))) { + vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__snp_req_queue__DOT__genblk3__DOT__genblk2__DOT__full_r = 1U; + } + __Vdly__VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__snp_req_queue__DOT__size_r + = (0x1fU & ((IData)(1U) + (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__snp_req_queue__DOT__size_r))); + } + __Vdly__VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__snp_req_queue__DOT__genblk3__DOT__genblk2__DOT__wr_ptr_r + = (0xfU & ((IData)(1U) + (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__snp_req_queue__DOT__genblk3__DOT__genblk2__DOT__wr_ptr_r))); + } + vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__snp_req_queue__DOT__genblk3__DOT__genblk2__DOT__curr_r + = vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT____Vcellinp__snp_req_queue__data_in; + if (vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__snp_req_queue__DOT__reading) { + __Vdly__VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__snp_req_queue__DOT__genblk3__DOT__genblk2__DOT__rd_ptr_r + = vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__snp_req_queue__DOT__genblk3__DOT__genblk2__DOT__rd_ptr_next_r; + if ((1U & (~ (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__snp_req_queue__DOT__writing)))) { + if ((1U == (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__snp_req_queue__DOT__size_r))) { + if (Verilated::assertOn()) { + if (VL_UNLIKELY(((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__snp_req_queue__DOT__genblk3__DOT__genblk2__DOT__rd_ptr_next_r) + != (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__snp_req_queue__DOT__genblk3__DOT__genblk2__DOT__wr_ptr_r)))) { + VL_WRITEF("[%0t] %%Error: VX_generic_queue.v:144: Assertion failed in %NVX_cache.genblk5[0].bank.snp_req_queue.genblk3.genblk2: 'assert' failed.\n", + 64,VL_TIME_Q(), + vlSymsp->name()); + VL_STOP_MT("../../rtl/libs/VX_generic_queue.v", 144, ""); + } + } + __Vdly__VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__snp_req_queue__DOT__genblk3__DOT__genblk2__DOT__empty_r = 1U; + } + vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__snp_req_queue__DOT__genblk3__DOT__genblk2__DOT__full_r = 0U; + __Vdly__VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__snp_req_queue__DOT__size_r + = (0x1fU & ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__snp_req_queue__DOT__size_r) + - (IData)(1U))); + } + __Vdly__VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__snp_req_queue__DOT__genblk3__DOT__genblk2__DOT__rd_ptr_next_r + = (0xfU & ((IData)(2U) + (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__snp_req_queue__DOT__genblk3__DOT__genblk2__DOT__rd_ptr_r))); + } + vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__snp_req_queue__DOT__genblk3__DOT__genblk2__DOT__bypass_r + = ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__snp_req_queue__DOT__writing) + & ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__snp_req_queue__DOT__genblk3__DOT__genblk2__DOT__empty_r) + | ((1U == (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__snp_req_queue__DOT__size_r)) + & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__snp_req_queue__DOT__reading)))); + vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__snp_req_queue__DOT__genblk3__DOT__genblk2__DOT__head_r + = vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__snp_req_queue__DOT__genblk3__DOT__data + [((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__snp_req_queue__DOT__reading) + ? (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__snp_req_queue__DOT__genblk3__DOT__genblk2__DOT__rd_ptr_next_r) + : (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__snp_req_queue__DOT__genblk3__DOT__genblk2__DOT__rd_ptr_r))]; + } + if (vlTOPp->reset) { + __Vdly__VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__size_r = 0U; + vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__head_r[0U] = 0U; + vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__head_r[1U] = 0U; + vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__head_r[2U] = 0U; + vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__head_r[3U] = 0U; + vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__head_r[4U] = 0U; + vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__head_r[5U] = 0U; + vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__head_r[6U] = 0U; + vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__head_r[7U] = 0U; + vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__head_r[8U] = 0U; + vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__head_r[9U] = 0U; + vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__curr_r[0U] = 0U; + vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__curr_r[1U] = 0U; + vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__curr_r[2U] = 0U; + vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__curr_r[3U] = 0U; + vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__curr_r[4U] = 0U; + vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__curr_r[5U] = 0U; + vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__curr_r[6U] = 0U; + vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__curr_r[7U] = 0U; + vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__curr_r[8U] = 0U; + vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__curr_r[9U] = 0U; + __Vdly__VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__wr_ptr_r = 0U; + __Vdly__VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__rd_ptr_r = 0U; + __Vdly__VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__rd_ptr_next_r = 1U; + __Vdly__VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__empty_r = 1U; + vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__full_r = 0U; + } else { + if (vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__writing) { + __Vdlyvval__VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__data__v0[0U] + = vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__core_req_arb__DOT____Vcellinp__reqq_queue__data_in[0U]; + __Vdlyvval__VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__data__v0[1U] + = vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__core_req_arb__DOT____Vcellinp__reqq_queue__data_in[1U]; + __Vdlyvval__VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__data__v0[2U] + = vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__core_req_arb__DOT____Vcellinp__reqq_queue__data_in[2U]; + __Vdlyvval__VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__data__v0[3U] + = vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__core_req_arb__DOT____Vcellinp__reqq_queue__data_in[3U]; + __Vdlyvval__VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__data__v0[4U] + = vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__core_req_arb__DOT____Vcellinp__reqq_queue__data_in[4U]; + __Vdlyvval__VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__data__v0[5U] + = vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__core_req_arb__DOT____Vcellinp__reqq_queue__data_in[5U]; + __Vdlyvval__VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__data__v0[6U] + = vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__core_req_arb__DOT____Vcellinp__reqq_queue__data_in[6U]; + __Vdlyvval__VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__data__v0[7U] + = vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__core_req_arb__DOT____Vcellinp__reqq_queue__data_in[7U]; + __Vdlyvval__VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__data__v0[8U] + = vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__core_req_arb__DOT____Vcellinp__reqq_queue__data_in[8U]; + __Vdlyvval__VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__data__v0[9U] + = vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__core_req_arb__DOT____Vcellinp__reqq_queue__data_in[9U]; + __Vdlyvset__VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__data__v0 = 1U; + __Vdlyvdim0__VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__data__v0 + = vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__wr_ptr_r; + if ((1U & (~ (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__reading)))) { + __Vdly__VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__empty_r = 0U; + if ((3U == (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__size_r))) { + vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__full_r = 1U; + } + __Vdly__VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__size_r + = (7U & ((IData)(1U) + (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__size_r))); + } + __Vdly__VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__wr_ptr_r + = (3U & ((IData)(1U) + (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__wr_ptr_r))); + } + vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__curr_r[0U] + = vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__core_req_arb__DOT____Vcellinp__reqq_queue__data_in[0U]; + vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__curr_r[1U] + = vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__core_req_arb__DOT____Vcellinp__reqq_queue__data_in[1U]; + vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__curr_r[2U] + = vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__core_req_arb__DOT____Vcellinp__reqq_queue__data_in[2U]; + vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__curr_r[3U] + = vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__core_req_arb__DOT____Vcellinp__reqq_queue__data_in[3U]; + vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__curr_r[4U] + = vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__core_req_arb__DOT____Vcellinp__reqq_queue__data_in[4U]; + vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__curr_r[5U] + = vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__core_req_arb__DOT____Vcellinp__reqq_queue__data_in[5U]; + vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__curr_r[6U] + = vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__core_req_arb__DOT____Vcellinp__reqq_queue__data_in[6U]; + vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__curr_r[7U] + = vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__core_req_arb__DOT____Vcellinp__reqq_queue__data_in[7U]; + vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__curr_r[8U] + = vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__core_req_arb__DOT____Vcellinp__reqq_queue__data_in[8U]; + vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__curr_r[9U] + = vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__core_req_arb__DOT____Vcellinp__reqq_queue__data_in[9U]; + if (vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__reading) { + __Vdly__VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__rd_ptr_r + = vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__rd_ptr_next_r; + if ((1U & (~ (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__writing)))) { + if ((1U == (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__size_r))) { + if (Verilated::assertOn()) { + if (VL_UNLIKELY(((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__rd_ptr_next_r) + != (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__wr_ptr_r)))) { + VL_WRITEF("[%0t] %%Error: VX_generic_queue.v:144: Assertion failed in %NVX_cache.genblk5[3].bank.core_req_arb.reqq_queue.genblk3.genblk2: 'assert' failed.\n", + 64,VL_TIME_Q(), + vlSymsp->name()); + VL_STOP_MT("../../rtl/libs/VX_generic_queue.v", 144, ""); + } + } + __Vdly__VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__empty_r = 1U; + } + vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__full_r = 0U; + __Vdly__VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__size_r + = (7U & ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__size_r) + - (IData)(1U))); + } + __Vdly__VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__rd_ptr_next_r + = (3U & ((IData)(2U) + (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__rd_ptr_r))); + } + vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__bypass_r + = ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__writing) + & ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__empty_r) + | ((1U == (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__size_r)) + & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__reading)))); + vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__head_r[0U] + = vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__data + [((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__reading) + ? (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__rd_ptr_next_r) + : (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__rd_ptr_r))][0U]; + vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__head_r[1U] + = vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__data + [((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__reading) + ? (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__rd_ptr_next_r) + : (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__rd_ptr_r))][1U]; + vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__head_r[2U] + = vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__data + [((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__reading) + ? (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__rd_ptr_next_r) + : (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__rd_ptr_r))][2U]; + vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__head_r[3U] + = vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__data + [((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__reading) + ? (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__rd_ptr_next_r) + : (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__rd_ptr_r))][3U]; + vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__head_r[4U] + = vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__data + [((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__reading) + ? (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__rd_ptr_next_r) + : (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__rd_ptr_r))][4U]; + vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__head_r[5U] + = vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__data + [((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__reading) + ? (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__rd_ptr_next_r) + : (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__rd_ptr_r))][5U]; + vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__head_r[6U] + = vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__data + [((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__reading) + ? (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__rd_ptr_next_r) + : (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__rd_ptr_r))][6U]; + vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__head_r[7U] + = vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__data + [((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__reading) + ? (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__rd_ptr_next_r) + : (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__rd_ptr_r))][7U]; + vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__head_r[8U] + = vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__data + [((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__reading) + ? (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__rd_ptr_next_r) + : (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__rd_ptr_r))][8U]; + vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__head_r[9U] + = vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__data + [((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__reading) + ? (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__rd_ptr_next_r) + : (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__rd_ptr_r))][9U]; + } + if (vlTOPp->reset) { + __Vdly__VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__size_r = 0U; + vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__head_r[0U] = 0U; + vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__head_r[1U] = 0U; + vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__head_r[2U] = 0U; + vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__head_r[3U] = 0U; + vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__head_r[4U] = 0U; + vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__head_r[5U] = 0U; + vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__head_r[6U] = 0U; + vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__head_r[7U] = 0U; + vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__head_r[8U] = 0U; + vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__head_r[9U] = 0U; + vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__curr_r[0U] = 0U; + vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__curr_r[1U] = 0U; + vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__curr_r[2U] = 0U; + vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__curr_r[3U] = 0U; + vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__curr_r[4U] = 0U; + vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__curr_r[5U] = 0U; + vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__curr_r[6U] = 0U; + vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__curr_r[7U] = 0U; + vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__curr_r[8U] = 0U; + vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__curr_r[9U] = 0U; + __Vdly__VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__wr_ptr_r = 0U; + __Vdly__VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__rd_ptr_r = 0U; + __Vdly__VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__rd_ptr_next_r = 1U; + __Vdly__VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__empty_r = 1U; + vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__full_r = 0U; + } else { + if (vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__writing) { + __Vdlyvval__VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__data__v0[0U] + = vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__core_req_arb__DOT____Vcellinp__reqq_queue__data_in[0U]; + __Vdlyvval__VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__data__v0[1U] + = vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__core_req_arb__DOT____Vcellinp__reqq_queue__data_in[1U]; + __Vdlyvval__VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__data__v0[2U] + = vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__core_req_arb__DOT____Vcellinp__reqq_queue__data_in[2U]; + __Vdlyvval__VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__data__v0[3U] + = vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__core_req_arb__DOT____Vcellinp__reqq_queue__data_in[3U]; + __Vdlyvval__VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__data__v0[4U] + = vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__core_req_arb__DOT____Vcellinp__reqq_queue__data_in[4U]; + __Vdlyvval__VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__data__v0[5U] + = vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__core_req_arb__DOT____Vcellinp__reqq_queue__data_in[5U]; + __Vdlyvval__VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__data__v0[6U] + = vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__core_req_arb__DOT____Vcellinp__reqq_queue__data_in[6U]; + __Vdlyvval__VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__data__v0[7U] + = vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__core_req_arb__DOT____Vcellinp__reqq_queue__data_in[7U]; + __Vdlyvval__VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__data__v0[8U] + = vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__core_req_arb__DOT____Vcellinp__reqq_queue__data_in[8U]; + __Vdlyvval__VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__data__v0[9U] + = vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__core_req_arb__DOT____Vcellinp__reqq_queue__data_in[9U]; + __Vdlyvset__VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__data__v0 = 1U; + __Vdlyvdim0__VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__data__v0 + = vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__wr_ptr_r; + if ((1U & (~ (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__reading)))) { + __Vdly__VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__empty_r = 0U; + if ((3U == (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__size_r))) { + vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__full_r = 1U; + } + __Vdly__VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__size_r + = (7U & ((IData)(1U) + (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__size_r))); + } + __Vdly__VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__wr_ptr_r + = (3U & ((IData)(1U) + (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__wr_ptr_r))); + } + vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__curr_r[0U] + = vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__core_req_arb__DOT____Vcellinp__reqq_queue__data_in[0U]; + vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__curr_r[1U] + = vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__core_req_arb__DOT____Vcellinp__reqq_queue__data_in[1U]; + vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__curr_r[2U] + = vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__core_req_arb__DOT____Vcellinp__reqq_queue__data_in[2U]; + vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__curr_r[3U] + = vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__core_req_arb__DOT____Vcellinp__reqq_queue__data_in[3U]; + vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__curr_r[4U] + = vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__core_req_arb__DOT____Vcellinp__reqq_queue__data_in[4U]; + vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__curr_r[5U] + = vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__core_req_arb__DOT____Vcellinp__reqq_queue__data_in[5U]; + vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__curr_r[6U] + = vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__core_req_arb__DOT____Vcellinp__reqq_queue__data_in[6U]; + vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__curr_r[7U] + = vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__core_req_arb__DOT____Vcellinp__reqq_queue__data_in[7U]; + vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__curr_r[8U] + = vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__core_req_arb__DOT____Vcellinp__reqq_queue__data_in[8U]; + vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__curr_r[9U] + = vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__core_req_arb__DOT____Vcellinp__reqq_queue__data_in[9U]; + if (vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__reading) { + __Vdly__VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__rd_ptr_r + = vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__rd_ptr_next_r; + if ((1U & (~ (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__writing)))) { + if ((1U == (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__size_r))) { + if (Verilated::assertOn()) { + if (VL_UNLIKELY(((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__rd_ptr_next_r) + != (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__wr_ptr_r)))) { + VL_WRITEF("[%0t] %%Error: VX_generic_queue.v:144: Assertion failed in %NVX_cache.genblk5[2].bank.core_req_arb.reqq_queue.genblk3.genblk2: 'assert' failed.\n", + 64,VL_TIME_Q(), + vlSymsp->name()); + VL_STOP_MT("../../rtl/libs/VX_generic_queue.v", 144, ""); + } + } + __Vdly__VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__empty_r = 1U; + } + vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__full_r = 0U; + __Vdly__VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__size_r + = (7U & ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__size_r) + - (IData)(1U))); + } + __Vdly__VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__rd_ptr_next_r + = (3U & ((IData)(2U) + (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__rd_ptr_r))); + } + vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__bypass_r + = ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__writing) + & ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__empty_r) + | ((1U == (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__size_r)) + & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__reading)))); + vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__head_r[0U] + = vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__data + [((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__reading) + ? (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__rd_ptr_next_r) + : (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__rd_ptr_r))][0U]; + vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__head_r[1U] + = vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__data + [((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__reading) + ? (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__rd_ptr_next_r) + : (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__rd_ptr_r))][1U]; + vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__head_r[2U] + = vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__data + [((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__reading) + ? (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__rd_ptr_next_r) + : (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__rd_ptr_r))][2U]; + vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__head_r[3U] + = vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__data + [((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__reading) + ? (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__rd_ptr_next_r) + : (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__rd_ptr_r))][3U]; + vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__head_r[4U] + = vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__data + [((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__reading) + ? (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__rd_ptr_next_r) + : (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__rd_ptr_r))][4U]; + vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__head_r[5U] + = vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__data + [((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__reading) + ? (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__rd_ptr_next_r) + : (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__rd_ptr_r))][5U]; + vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__head_r[6U] + = vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__data + [((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__reading) + ? (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__rd_ptr_next_r) + : (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__rd_ptr_r))][6U]; + vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__head_r[7U] + = vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__data + [((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__reading) + ? (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__rd_ptr_next_r) + : (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__rd_ptr_r))][7U]; + vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__head_r[8U] + = vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__data + [((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__reading) + ? (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__rd_ptr_next_r) + : (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__rd_ptr_r))][8U]; + vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__head_r[9U] + = vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__data + [((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__reading) + ? (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__rd_ptr_next_r) + : (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__rd_ptr_r))][9U]; + } + if (vlTOPp->reset) { + __Vdly__VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__size_r = 0U; + vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__head_r[0U] = 0U; + vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__head_r[1U] = 0U; + vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__head_r[2U] = 0U; + vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__head_r[3U] = 0U; + vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__head_r[4U] = 0U; + vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__head_r[5U] = 0U; + vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__head_r[6U] = 0U; + vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__head_r[7U] = 0U; + vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__head_r[8U] = 0U; + vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__head_r[9U] = 0U; + vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__curr_r[0U] = 0U; + vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__curr_r[1U] = 0U; + vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__curr_r[2U] = 0U; + vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__curr_r[3U] = 0U; + vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__curr_r[4U] = 0U; + vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__curr_r[5U] = 0U; + vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__curr_r[6U] = 0U; + vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__curr_r[7U] = 0U; + vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__curr_r[8U] = 0U; + vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__curr_r[9U] = 0U; + __Vdly__VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__wr_ptr_r = 0U; + __Vdly__VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__rd_ptr_r = 0U; + __Vdly__VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__rd_ptr_next_r = 1U; + __Vdly__VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__empty_r = 1U; + vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__full_r = 0U; + } else { + if (vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__writing) { + __Vdlyvval__VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__data__v0[0U] + = vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__core_req_arb__DOT____Vcellinp__reqq_queue__data_in[0U]; + __Vdlyvval__VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__data__v0[1U] + = vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__core_req_arb__DOT____Vcellinp__reqq_queue__data_in[1U]; + __Vdlyvval__VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__data__v0[2U] + = vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__core_req_arb__DOT____Vcellinp__reqq_queue__data_in[2U]; + __Vdlyvval__VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__data__v0[3U] + = vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__core_req_arb__DOT____Vcellinp__reqq_queue__data_in[3U]; + __Vdlyvval__VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__data__v0[4U] + = vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__core_req_arb__DOT____Vcellinp__reqq_queue__data_in[4U]; + __Vdlyvval__VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__data__v0[5U] + = vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__core_req_arb__DOT____Vcellinp__reqq_queue__data_in[5U]; + __Vdlyvval__VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__data__v0[6U] + = vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__core_req_arb__DOT____Vcellinp__reqq_queue__data_in[6U]; + __Vdlyvval__VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__data__v0[7U] + = vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__core_req_arb__DOT____Vcellinp__reqq_queue__data_in[7U]; + __Vdlyvval__VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__data__v0[8U] + = vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__core_req_arb__DOT____Vcellinp__reqq_queue__data_in[8U]; + __Vdlyvval__VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__data__v0[9U] + = vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__core_req_arb__DOT____Vcellinp__reqq_queue__data_in[9U]; + __Vdlyvset__VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__data__v0 = 1U; + __Vdlyvdim0__VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__data__v0 + = vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__wr_ptr_r; + if ((1U & (~ (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__reading)))) { + __Vdly__VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__empty_r = 0U; + if ((3U == (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__size_r))) { + vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__full_r = 1U; + } + __Vdly__VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__size_r + = (7U & ((IData)(1U) + (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__size_r))); + } + __Vdly__VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__wr_ptr_r + = (3U & ((IData)(1U) + (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__wr_ptr_r))); + } + vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__curr_r[0U] + = vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__core_req_arb__DOT____Vcellinp__reqq_queue__data_in[0U]; + vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__curr_r[1U] + = vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__core_req_arb__DOT____Vcellinp__reqq_queue__data_in[1U]; + vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__curr_r[2U] + = vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__core_req_arb__DOT____Vcellinp__reqq_queue__data_in[2U]; + vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__curr_r[3U] + = vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__core_req_arb__DOT____Vcellinp__reqq_queue__data_in[3U]; + vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__curr_r[4U] + = vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__core_req_arb__DOT____Vcellinp__reqq_queue__data_in[4U]; + vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__curr_r[5U] + = vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__core_req_arb__DOT____Vcellinp__reqq_queue__data_in[5U]; + vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__curr_r[6U] + = vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__core_req_arb__DOT____Vcellinp__reqq_queue__data_in[6U]; + vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__curr_r[7U] + = vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__core_req_arb__DOT____Vcellinp__reqq_queue__data_in[7U]; + vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__curr_r[8U] + = vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__core_req_arb__DOT____Vcellinp__reqq_queue__data_in[8U]; + vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__curr_r[9U] + = vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__core_req_arb__DOT____Vcellinp__reqq_queue__data_in[9U]; + if (vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__reading) { + __Vdly__VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__rd_ptr_r + = vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__rd_ptr_next_r; + if ((1U & (~ (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__writing)))) { + if ((1U == (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__size_r))) { + if (Verilated::assertOn()) { + if (VL_UNLIKELY(((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__rd_ptr_next_r) + != (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__wr_ptr_r)))) { + VL_WRITEF("[%0t] %%Error: VX_generic_queue.v:144: Assertion failed in %NVX_cache.genblk5[1].bank.core_req_arb.reqq_queue.genblk3.genblk2: 'assert' failed.\n", + 64,VL_TIME_Q(), + vlSymsp->name()); + VL_STOP_MT("../../rtl/libs/VX_generic_queue.v", 144, ""); + } + } + __Vdly__VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__empty_r = 1U; + } + vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__full_r = 0U; + __Vdly__VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__size_r + = (7U & ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__size_r) + - (IData)(1U))); + } + __Vdly__VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__rd_ptr_next_r + = (3U & ((IData)(2U) + (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__rd_ptr_r))); + } + vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__bypass_r + = ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__writing) + & ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__empty_r) + | ((1U == (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__size_r)) + & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__reading)))); + vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__head_r[0U] + = vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__data + [((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__reading) + ? (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__rd_ptr_next_r) + : (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__rd_ptr_r))][0U]; + vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__head_r[1U] + = vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__data + [((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__reading) + ? (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__rd_ptr_next_r) + : (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__rd_ptr_r))][1U]; + vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__head_r[2U] + = vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__data + [((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__reading) + ? (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__rd_ptr_next_r) + : (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__rd_ptr_r))][2U]; + vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__head_r[3U] + = vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__data + [((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__reading) + ? (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__rd_ptr_next_r) + : (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__rd_ptr_r))][3U]; + vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__head_r[4U] + = vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__data + [((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__reading) + ? (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__rd_ptr_next_r) + : (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__rd_ptr_r))][4U]; + vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__head_r[5U] + = vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__data + [((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__reading) + ? (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__rd_ptr_next_r) + : (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__rd_ptr_r))][5U]; + vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__head_r[6U] + = vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__data + [((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__reading) + ? (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__rd_ptr_next_r) + : (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__rd_ptr_r))][6U]; + vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__head_r[7U] + = vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__data + [((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__reading) + ? (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__rd_ptr_next_r) + : (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__rd_ptr_r))][7U]; + vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__head_r[8U] + = vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__data + [((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__reading) + ? (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__rd_ptr_next_r) + : (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__rd_ptr_r))][8U]; + vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__head_r[9U] + = vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__data + [((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__reading) + ? (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__rd_ptr_next_r) + : (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__rd_ptr_r))][9U]; + } + if (vlTOPp->reset) { + __Vdly__VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__size_r = 0U; + vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__head_r[0U] = 0U; + vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__head_r[1U] = 0U; + vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__head_r[2U] = 0U; + vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__head_r[3U] = 0U; + vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__head_r[4U] = 0U; + vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__head_r[5U] = 0U; + vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__head_r[6U] = 0U; + vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__head_r[7U] = 0U; + vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__head_r[8U] = 0U; + vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__head_r[9U] = 0U; + vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__curr_r[0U] = 0U; + vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__curr_r[1U] = 0U; + vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__curr_r[2U] = 0U; + vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__curr_r[3U] = 0U; + vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__curr_r[4U] = 0U; + vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__curr_r[5U] = 0U; + vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__curr_r[6U] = 0U; + vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__curr_r[7U] = 0U; + vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__curr_r[8U] = 0U; + vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__curr_r[9U] = 0U; + __Vdly__VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__wr_ptr_r = 0U; + __Vdly__VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__rd_ptr_r = 0U; + __Vdly__VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__rd_ptr_next_r = 1U; + __Vdly__VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__empty_r = 1U; + vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__full_r = 0U; + } else { + if (vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__writing) { + __Vdlyvval__VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__data__v0[0U] + = vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__core_req_arb__DOT____Vcellinp__reqq_queue__data_in[0U]; + __Vdlyvval__VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__data__v0[1U] + = vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__core_req_arb__DOT____Vcellinp__reqq_queue__data_in[1U]; + __Vdlyvval__VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__data__v0[2U] + = vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__core_req_arb__DOT____Vcellinp__reqq_queue__data_in[2U]; + __Vdlyvval__VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__data__v0[3U] + = vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__core_req_arb__DOT____Vcellinp__reqq_queue__data_in[3U]; + __Vdlyvval__VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__data__v0[4U] + = vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__core_req_arb__DOT____Vcellinp__reqq_queue__data_in[4U]; + __Vdlyvval__VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__data__v0[5U] + = vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__core_req_arb__DOT____Vcellinp__reqq_queue__data_in[5U]; + __Vdlyvval__VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__data__v0[6U] + = vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__core_req_arb__DOT____Vcellinp__reqq_queue__data_in[6U]; + __Vdlyvval__VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__data__v0[7U] + = vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__core_req_arb__DOT____Vcellinp__reqq_queue__data_in[7U]; + __Vdlyvval__VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__data__v0[8U] + = vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__core_req_arb__DOT____Vcellinp__reqq_queue__data_in[8U]; + __Vdlyvval__VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__data__v0[9U] + = vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__core_req_arb__DOT____Vcellinp__reqq_queue__data_in[9U]; + __Vdlyvset__VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__data__v0 = 1U; + __Vdlyvdim0__VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__data__v0 + = vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__wr_ptr_r; + if ((1U & (~ (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__reading)))) { + __Vdly__VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__empty_r = 0U; + if ((3U == (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__size_r))) { + vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__full_r = 1U; + } + __Vdly__VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__size_r + = (7U & ((IData)(1U) + (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__size_r))); + } + __Vdly__VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__wr_ptr_r + = (3U & ((IData)(1U) + (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__wr_ptr_r))); + } + vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__curr_r[0U] + = vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__core_req_arb__DOT____Vcellinp__reqq_queue__data_in[0U]; + vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__curr_r[1U] + = vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__core_req_arb__DOT____Vcellinp__reqq_queue__data_in[1U]; + vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__curr_r[2U] + = vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__core_req_arb__DOT____Vcellinp__reqq_queue__data_in[2U]; + vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__curr_r[3U] + = vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__core_req_arb__DOT____Vcellinp__reqq_queue__data_in[3U]; + vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__curr_r[4U] + = vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__core_req_arb__DOT____Vcellinp__reqq_queue__data_in[4U]; + vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__curr_r[5U] + = vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__core_req_arb__DOT____Vcellinp__reqq_queue__data_in[5U]; + vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__curr_r[6U] + = vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__core_req_arb__DOT____Vcellinp__reqq_queue__data_in[6U]; + vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__curr_r[7U] + = vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__core_req_arb__DOT____Vcellinp__reqq_queue__data_in[7U]; + vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__curr_r[8U] + = vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__core_req_arb__DOT____Vcellinp__reqq_queue__data_in[8U]; + vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__curr_r[9U] + = vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__core_req_arb__DOT____Vcellinp__reqq_queue__data_in[9U]; + if (vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__reading) { + __Vdly__VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__rd_ptr_r + = vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__rd_ptr_next_r; + if ((1U & (~ (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__writing)))) { + if ((1U == (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__size_r))) { + if (Verilated::assertOn()) { + if (VL_UNLIKELY(((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__rd_ptr_next_r) + != (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__wr_ptr_r)))) { + VL_WRITEF("[%0t] %%Error: VX_generic_queue.v:144: Assertion failed in %NVX_cache.genblk5[0].bank.core_req_arb.reqq_queue.genblk3.genblk2: 'assert' failed.\n", + 64,VL_TIME_Q(), + vlSymsp->name()); + VL_STOP_MT("../../rtl/libs/VX_generic_queue.v", 144, ""); + } + } + __Vdly__VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__empty_r = 1U; + } + vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__full_r = 0U; + __Vdly__VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__size_r + = (7U & ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__size_r) + - (IData)(1U))); + } + __Vdly__VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__rd_ptr_next_r + = (3U & ((IData)(2U) + (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__rd_ptr_r))); + } + vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__bypass_r + = ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__writing) + & ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__empty_r) + | ((1U == (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__size_r)) + & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__reading)))); + vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__head_r[0U] + = vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__data + [((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__reading) + ? (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__rd_ptr_next_r) + : (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__rd_ptr_r))][0U]; + vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__head_r[1U] + = vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__data + [((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__reading) + ? (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__rd_ptr_next_r) + : (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__rd_ptr_r))][1U]; + vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__head_r[2U] + = vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__data + [((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__reading) + ? (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__rd_ptr_next_r) + : (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__rd_ptr_r))][2U]; + vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__head_r[3U] + = vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__data + [((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__reading) + ? (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__rd_ptr_next_r) + : (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__rd_ptr_r))][3U]; + vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__head_r[4U] + = vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__data + [((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__reading) + ? (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__rd_ptr_next_r) + : (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__rd_ptr_r))][4U]; + vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__head_r[5U] + = vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__data + [((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__reading) + ? (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__rd_ptr_next_r) + : (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__rd_ptr_r))][5U]; + vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__head_r[6U] + = vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__data + [((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__reading) + ? (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__rd_ptr_next_r) + : (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__rd_ptr_r))][6U]; + vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__head_r[7U] + = vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__data + [((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__reading) + ? (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__rd_ptr_next_r) + : (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__rd_ptr_r))][7U]; + vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__head_r[8U] + = vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__data + [((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__reading) + ? (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__rd_ptr_next_r) + : (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__rd_ptr_r))][8U]; + vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__head_r[9U] + = vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__data + [((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__reading) + ? (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__rd_ptr_next_r) + : (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__rd_ptr_r))][9U]; + } + if (vlTOPp->reset) { + vlTOPp->VX_cache__DOT__cache_core_rsp_merge__DOT__sel_bank__DOT__genblk2__DOT__refill_original = 0U; + } else { + if ((0U == (IData)(vlTOPp->VX_cache__DOT__cache_core_rsp_merge__DOT__sel_bank__DOT__genblk2__DOT__requests_use))) { + vlTOPp->VX_cache__DOT__cache_core_rsp_merge__DOT__sel_bank__DOT__genblk2__DOT__refill_original + = vlTOPp->VX_cache__DOT__per_bank_core_rsp_valid; + } + } + if (vlTOPp->reset) { + vlTOPp->VX_cache__DOT__cache_dram_req_arb__DOT__dram_fill_arb__DOT__use_per_bank_dram_fill_req_valid = 0U; + } else { + if (((IData)(vlTOPp->VX_cache__DOT__cache_dram_req_arb__DOT__dfqq_pop) + & (IData)(vlTOPp->VX_cache__DOT__cache_dram_req_arb__DOT__dram_fill_arb__DOT__qual_has_request))) { + vlTOPp->VX_cache__DOT__cache_dram_req_arb__DOT__dram_fill_arb__DOT__use_per_bank_dram_fill_req_valid + = ((IData)(vlTOPp->VX_cache__DOT__cache_dram_req_arb__DOT__dram_fill_arb__DOT__use_per_bqual_bank_dram_fill_req_valid) + & (~ ((IData)(1U) << (IData)(vlTOPp->VX_cache__DOT__cache_dram_req_arb__DOT__dram_fill_arb__DOT__qual_request_index)))); + } + } + if (vlTOPp->reset) { + __Vdly__VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cwb_queue__DOT__size_r = 0U; + vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cwb_queue__DOT__genblk3__DOT__genblk2__DOT__head_r[0U] = 0U; + vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cwb_queue__DOT__genblk3__DOT__genblk2__DOT__head_r[1U] = 0U; + vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cwb_queue__DOT__genblk3__DOT__genblk2__DOT__head_r[2U] = 0U; + vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cwb_queue__DOT__genblk3__DOT__genblk2__DOT__curr_r[0U] = 0U; + vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cwb_queue__DOT__genblk3__DOT__genblk2__DOT__curr_r[1U] = 0U; + vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cwb_queue__DOT__genblk3__DOT__genblk2__DOT__curr_r[2U] = 0U; + __Vdly__VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cwb_queue__DOT__genblk3__DOT__genblk2__DOT__wr_ptr_r = 0U; + __Vdly__VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cwb_queue__DOT__genblk3__DOT__genblk2__DOT__rd_ptr_r = 0U; + __Vdly__VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cwb_queue__DOT__genblk3__DOT__genblk2__DOT__rd_ptr_next_r = 1U; + __Vdly__VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cwb_queue__DOT__genblk3__DOT__genblk2__DOT__empty_r = 1U; + vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cwb_queue__DOT__genblk3__DOT__genblk2__DOT__full_r = 0U; + } else { + if (vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cwb_queue__DOT__writing) { + __Vdlyvval__VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cwb_queue__DOT__genblk3__DOT__data__v0[0U] + = vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT____Vcellinp__cwb_queue__data_in[0U]; + __Vdlyvval__VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cwb_queue__DOT__genblk3__DOT__data__v0[1U] + = vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT____Vcellinp__cwb_queue__data_in[1U]; + __Vdlyvval__VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cwb_queue__DOT__genblk3__DOT__data__v0[2U] + = vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT____Vcellinp__cwb_queue__data_in[2U]; + __Vdlyvset__VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cwb_queue__DOT__genblk3__DOT__data__v0 = 1U; + __Vdlyvdim0__VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cwb_queue__DOT__genblk3__DOT__data__v0 + = vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cwb_queue__DOT__genblk3__DOT__genblk2__DOT__wr_ptr_r; + if ((1U & (~ (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cwb_queue__DOT__reading)))) { + __Vdly__VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cwb_queue__DOT__genblk3__DOT__genblk2__DOT__empty_r = 0U; + if ((3U == (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cwb_queue__DOT__size_r))) { + vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cwb_queue__DOT__genblk3__DOT__genblk2__DOT__full_r = 1U; + } + __Vdly__VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cwb_queue__DOT__size_r + = (7U & ((IData)(1U) + (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cwb_queue__DOT__size_r))); + } + __Vdly__VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cwb_queue__DOT__genblk3__DOT__genblk2__DOT__wr_ptr_r + = (3U & ((IData)(1U) + (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cwb_queue__DOT__genblk3__DOT__genblk2__DOT__wr_ptr_r))); + } + vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cwb_queue__DOT__genblk3__DOT__genblk2__DOT__curr_r[0U] + = vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT____Vcellinp__cwb_queue__data_in[0U]; + vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cwb_queue__DOT__genblk3__DOT__genblk2__DOT__curr_r[1U] + = vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT____Vcellinp__cwb_queue__data_in[1U]; + vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cwb_queue__DOT__genblk3__DOT__genblk2__DOT__curr_r[2U] + = vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT____Vcellinp__cwb_queue__data_in[2U]; + if (vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cwb_queue__DOT__reading) { + __Vdly__VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cwb_queue__DOT__genblk3__DOT__genblk2__DOT__rd_ptr_r + = vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cwb_queue__DOT__genblk3__DOT__genblk2__DOT__rd_ptr_next_r; + if ((1U & (~ (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cwb_queue__DOT__writing)))) { + if ((1U == (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cwb_queue__DOT__size_r))) { + if (Verilated::assertOn()) { + if (VL_UNLIKELY(((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cwb_queue__DOT__genblk3__DOT__genblk2__DOT__rd_ptr_next_r) + != (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cwb_queue__DOT__genblk3__DOT__genblk2__DOT__wr_ptr_r)))) { + VL_WRITEF("[%0t] %%Error: VX_generic_queue.v:144: Assertion failed in %NVX_cache.genblk5[3].bank.cwb_queue.genblk3.genblk2: 'assert' failed.\n", + 64,VL_TIME_Q(), + vlSymsp->name()); + VL_STOP_MT("../../rtl/libs/VX_generic_queue.v", 144, ""); + } + } + __Vdly__VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cwb_queue__DOT__genblk3__DOT__genblk2__DOT__empty_r = 1U; + } + vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cwb_queue__DOT__genblk3__DOT__genblk2__DOT__full_r = 0U; + __Vdly__VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cwb_queue__DOT__size_r + = (7U & ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cwb_queue__DOT__size_r) + - (IData)(1U))); + } + __Vdly__VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cwb_queue__DOT__genblk3__DOT__genblk2__DOT__rd_ptr_next_r + = (3U & ((IData)(2U) + (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cwb_queue__DOT__genblk3__DOT__genblk2__DOT__rd_ptr_r))); + } + vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cwb_queue__DOT__genblk3__DOT__genblk2__DOT__bypass_r + = ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cwb_queue__DOT__writing) + & ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cwb_queue__DOT__genblk3__DOT__genblk2__DOT__empty_r) + | ((1U == (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cwb_queue__DOT__size_r)) + & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cwb_queue__DOT__reading)))); + vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cwb_queue__DOT__genblk3__DOT__genblk2__DOT__head_r[0U] + = vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cwb_queue__DOT__genblk3__DOT__data + [((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cwb_queue__DOT__reading) + ? (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cwb_queue__DOT__genblk3__DOT__genblk2__DOT__rd_ptr_next_r) + : (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cwb_queue__DOT__genblk3__DOT__genblk2__DOT__rd_ptr_r))][0U]; + vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cwb_queue__DOT__genblk3__DOT__genblk2__DOT__head_r[1U] + = vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cwb_queue__DOT__genblk3__DOT__data + [((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cwb_queue__DOT__reading) + ? (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cwb_queue__DOT__genblk3__DOT__genblk2__DOT__rd_ptr_next_r) + : (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cwb_queue__DOT__genblk3__DOT__genblk2__DOT__rd_ptr_r))][1U]; + vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cwb_queue__DOT__genblk3__DOT__genblk2__DOT__head_r[2U] + = vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cwb_queue__DOT__genblk3__DOT__data + [((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cwb_queue__DOT__reading) + ? (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cwb_queue__DOT__genblk3__DOT__genblk2__DOT__rd_ptr_next_r) + : (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cwb_queue__DOT__genblk3__DOT__genblk2__DOT__rd_ptr_r))][2U]; + } + if (vlTOPp->reset) { + __Vdly__VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__cwb_queue__DOT__size_r = 0U; + vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__cwb_queue__DOT__genblk3__DOT__genblk2__DOT__head_r[0U] = 0U; + vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__cwb_queue__DOT__genblk3__DOT__genblk2__DOT__head_r[1U] = 0U; + vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__cwb_queue__DOT__genblk3__DOT__genblk2__DOT__head_r[2U] = 0U; + vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__cwb_queue__DOT__genblk3__DOT__genblk2__DOT__curr_r[0U] = 0U; + vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__cwb_queue__DOT__genblk3__DOT__genblk2__DOT__curr_r[1U] = 0U; + vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__cwb_queue__DOT__genblk3__DOT__genblk2__DOT__curr_r[2U] = 0U; + __Vdly__VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__cwb_queue__DOT__genblk3__DOT__genblk2__DOT__wr_ptr_r = 0U; + __Vdly__VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__cwb_queue__DOT__genblk3__DOT__genblk2__DOT__rd_ptr_r = 0U; + __Vdly__VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__cwb_queue__DOT__genblk3__DOT__genblk2__DOT__rd_ptr_next_r = 1U; + __Vdly__VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__cwb_queue__DOT__genblk3__DOT__genblk2__DOT__empty_r = 1U; + vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__cwb_queue__DOT__genblk3__DOT__genblk2__DOT__full_r = 0U; + } else { + if (vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__cwb_queue__DOT__writing) { + __Vdlyvval__VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__cwb_queue__DOT__genblk3__DOT__data__v0[0U] + = vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT____Vcellinp__cwb_queue__data_in[0U]; + __Vdlyvval__VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__cwb_queue__DOT__genblk3__DOT__data__v0[1U] + = vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT____Vcellinp__cwb_queue__data_in[1U]; + __Vdlyvval__VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__cwb_queue__DOT__genblk3__DOT__data__v0[2U] + = vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT____Vcellinp__cwb_queue__data_in[2U]; + __Vdlyvset__VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__cwb_queue__DOT__genblk3__DOT__data__v0 = 1U; + __Vdlyvdim0__VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__cwb_queue__DOT__genblk3__DOT__data__v0 + = vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__cwb_queue__DOT__genblk3__DOT__genblk2__DOT__wr_ptr_r; + if ((1U & (~ (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__cwb_queue__DOT__reading)))) { + __Vdly__VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__cwb_queue__DOT__genblk3__DOT__genblk2__DOT__empty_r = 0U; + if ((3U == (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__cwb_queue__DOT__size_r))) { + vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__cwb_queue__DOT__genblk3__DOT__genblk2__DOT__full_r = 1U; + } + __Vdly__VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__cwb_queue__DOT__size_r + = (7U & ((IData)(1U) + (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__cwb_queue__DOT__size_r))); + } + __Vdly__VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__cwb_queue__DOT__genblk3__DOT__genblk2__DOT__wr_ptr_r + = (3U & ((IData)(1U) + (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__cwb_queue__DOT__genblk3__DOT__genblk2__DOT__wr_ptr_r))); + } + vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__cwb_queue__DOT__genblk3__DOT__genblk2__DOT__curr_r[0U] + = vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT____Vcellinp__cwb_queue__data_in[0U]; + vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__cwb_queue__DOT__genblk3__DOT__genblk2__DOT__curr_r[1U] + = vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT____Vcellinp__cwb_queue__data_in[1U]; + vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__cwb_queue__DOT__genblk3__DOT__genblk2__DOT__curr_r[2U] + = vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT____Vcellinp__cwb_queue__data_in[2U]; + if (vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__cwb_queue__DOT__reading) { + __Vdly__VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__cwb_queue__DOT__genblk3__DOT__genblk2__DOT__rd_ptr_r + = vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__cwb_queue__DOT__genblk3__DOT__genblk2__DOT__rd_ptr_next_r; + if ((1U & (~ (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__cwb_queue__DOT__writing)))) { + if ((1U == (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__cwb_queue__DOT__size_r))) { + if (Verilated::assertOn()) { + if (VL_UNLIKELY(((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__cwb_queue__DOT__genblk3__DOT__genblk2__DOT__rd_ptr_next_r) + != (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__cwb_queue__DOT__genblk3__DOT__genblk2__DOT__wr_ptr_r)))) { + VL_WRITEF("[%0t] %%Error: VX_generic_queue.v:144: Assertion failed in %NVX_cache.genblk5[2].bank.cwb_queue.genblk3.genblk2: 'assert' failed.\n", + 64,VL_TIME_Q(), + vlSymsp->name()); + VL_STOP_MT("../../rtl/libs/VX_generic_queue.v", 144, ""); + } + } + __Vdly__VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__cwb_queue__DOT__genblk3__DOT__genblk2__DOT__empty_r = 1U; + } + vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__cwb_queue__DOT__genblk3__DOT__genblk2__DOT__full_r = 0U; + __Vdly__VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__cwb_queue__DOT__size_r + = (7U & ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__cwb_queue__DOT__size_r) + - (IData)(1U))); + } + __Vdly__VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__cwb_queue__DOT__genblk3__DOT__genblk2__DOT__rd_ptr_next_r + = (3U & ((IData)(2U) + (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__cwb_queue__DOT__genblk3__DOT__genblk2__DOT__rd_ptr_r))); + } + vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__cwb_queue__DOT__genblk3__DOT__genblk2__DOT__bypass_r + = ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__cwb_queue__DOT__writing) + & ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__cwb_queue__DOT__genblk3__DOT__genblk2__DOT__empty_r) + | ((1U == (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__cwb_queue__DOT__size_r)) + & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__cwb_queue__DOT__reading)))); + vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__cwb_queue__DOT__genblk3__DOT__genblk2__DOT__head_r[0U] + = vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__cwb_queue__DOT__genblk3__DOT__data + [((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__cwb_queue__DOT__reading) + ? (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__cwb_queue__DOT__genblk3__DOT__genblk2__DOT__rd_ptr_next_r) + : (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__cwb_queue__DOT__genblk3__DOT__genblk2__DOT__rd_ptr_r))][0U]; + vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__cwb_queue__DOT__genblk3__DOT__genblk2__DOT__head_r[1U] + = vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__cwb_queue__DOT__genblk3__DOT__data + [((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__cwb_queue__DOT__reading) + ? (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__cwb_queue__DOT__genblk3__DOT__genblk2__DOT__rd_ptr_next_r) + : (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__cwb_queue__DOT__genblk3__DOT__genblk2__DOT__rd_ptr_r))][1U]; + vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__cwb_queue__DOT__genblk3__DOT__genblk2__DOT__head_r[2U] + = vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__cwb_queue__DOT__genblk3__DOT__data + [((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__cwb_queue__DOT__reading) + ? (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__cwb_queue__DOT__genblk3__DOT__genblk2__DOT__rd_ptr_next_r) + : (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__cwb_queue__DOT__genblk3__DOT__genblk2__DOT__rd_ptr_r))][2U]; + } + if (vlTOPp->reset) { + __Vdly__VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__cwb_queue__DOT__size_r = 0U; + vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__cwb_queue__DOT__genblk3__DOT__genblk2__DOT__head_r[0U] = 0U; + vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__cwb_queue__DOT__genblk3__DOT__genblk2__DOT__head_r[1U] = 0U; + vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__cwb_queue__DOT__genblk3__DOT__genblk2__DOT__head_r[2U] = 0U; + vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__cwb_queue__DOT__genblk3__DOT__genblk2__DOT__curr_r[0U] = 0U; + vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__cwb_queue__DOT__genblk3__DOT__genblk2__DOT__curr_r[1U] = 0U; + vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__cwb_queue__DOT__genblk3__DOT__genblk2__DOT__curr_r[2U] = 0U; + __Vdly__VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__cwb_queue__DOT__genblk3__DOT__genblk2__DOT__wr_ptr_r = 0U; + __Vdly__VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__cwb_queue__DOT__genblk3__DOT__genblk2__DOT__rd_ptr_r = 0U; + __Vdly__VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__cwb_queue__DOT__genblk3__DOT__genblk2__DOT__rd_ptr_next_r = 1U; + __Vdly__VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__cwb_queue__DOT__genblk3__DOT__genblk2__DOT__empty_r = 1U; + vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__cwb_queue__DOT__genblk3__DOT__genblk2__DOT__full_r = 0U; + } else { + if (vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__cwb_queue__DOT__writing) { + __Vdlyvval__VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__cwb_queue__DOT__genblk3__DOT__data__v0[0U] + = vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT____Vcellinp__cwb_queue__data_in[0U]; + __Vdlyvval__VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__cwb_queue__DOT__genblk3__DOT__data__v0[1U] + = vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT____Vcellinp__cwb_queue__data_in[1U]; + __Vdlyvval__VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__cwb_queue__DOT__genblk3__DOT__data__v0[2U] + = vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT____Vcellinp__cwb_queue__data_in[2U]; + __Vdlyvset__VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__cwb_queue__DOT__genblk3__DOT__data__v0 = 1U; + __Vdlyvdim0__VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__cwb_queue__DOT__genblk3__DOT__data__v0 + = vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__cwb_queue__DOT__genblk3__DOT__genblk2__DOT__wr_ptr_r; + if ((1U & (~ (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__cwb_queue__DOT__reading)))) { + __Vdly__VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__cwb_queue__DOT__genblk3__DOT__genblk2__DOT__empty_r = 0U; + if ((3U == (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__cwb_queue__DOT__size_r))) { + vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__cwb_queue__DOT__genblk3__DOT__genblk2__DOT__full_r = 1U; + } + __Vdly__VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__cwb_queue__DOT__size_r + = (7U & ((IData)(1U) + (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__cwb_queue__DOT__size_r))); + } + __Vdly__VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__cwb_queue__DOT__genblk3__DOT__genblk2__DOT__wr_ptr_r + = (3U & ((IData)(1U) + (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__cwb_queue__DOT__genblk3__DOT__genblk2__DOT__wr_ptr_r))); + } + vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__cwb_queue__DOT__genblk3__DOT__genblk2__DOT__curr_r[0U] + = vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT____Vcellinp__cwb_queue__data_in[0U]; + vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__cwb_queue__DOT__genblk3__DOT__genblk2__DOT__curr_r[1U] + = vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT____Vcellinp__cwb_queue__data_in[1U]; + vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__cwb_queue__DOT__genblk3__DOT__genblk2__DOT__curr_r[2U] + = vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT____Vcellinp__cwb_queue__data_in[2U]; + if (vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__cwb_queue__DOT__reading) { + __Vdly__VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__cwb_queue__DOT__genblk3__DOT__genblk2__DOT__rd_ptr_r + = vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__cwb_queue__DOT__genblk3__DOT__genblk2__DOT__rd_ptr_next_r; + if ((1U & (~ (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__cwb_queue__DOT__writing)))) { + if ((1U == (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__cwb_queue__DOT__size_r))) { + if (Verilated::assertOn()) { + if (VL_UNLIKELY(((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__cwb_queue__DOT__genblk3__DOT__genblk2__DOT__rd_ptr_next_r) + != (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__cwb_queue__DOT__genblk3__DOT__genblk2__DOT__wr_ptr_r)))) { + VL_WRITEF("[%0t] %%Error: VX_generic_queue.v:144: Assertion failed in %NVX_cache.genblk5[1].bank.cwb_queue.genblk3.genblk2: 'assert' failed.\n", + 64,VL_TIME_Q(), + vlSymsp->name()); + VL_STOP_MT("../../rtl/libs/VX_generic_queue.v", 144, ""); + } + } + __Vdly__VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__cwb_queue__DOT__genblk3__DOT__genblk2__DOT__empty_r = 1U; + } + vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__cwb_queue__DOT__genblk3__DOT__genblk2__DOT__full_r = 0U; + __Vdly__VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__cwb_queue__DOT__size_r + = (7U & ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__cwb_queue__DOT__size_r) + - (IData)(1U))); + } + __Vdly__VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__cwb_queue__DOT__genblk3__DOT__genblk2__DOT__rd_ptr_next_r + = (3U & ((IData)(2U) + (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__cwb_queue__DOT__genblk3__DOT__genblk2__DOT__rd_ptr_r))); + } + vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__cwb_queue__DOT__genblk3__DOT__genblk2__DOT__bypass_r + = ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__cwb_queue__DOT__writing) + & ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__cwb_queue__DOT__genblk3__DOT__genblk2__DOT__empty_r) + | ((1U == (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__cwb_queue__DOT__size_r)) + & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__cwb_queue__DOT__reading)))); + vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__cwb_queue__DOT__genblk3__DOT__genblk2__DOT__head_r[0U] + = vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__cwb_queue__DOT__genblk3__DOT__data + [((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__cwb_queue__DOT__reading) + ? (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__cwb_queue__DOT__genblk3__DOT__genblk2__DOT__rd_ptr_next_r) + : (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__cwb_queue__DOT__genblk3__DOT__genblk2__DOT__rd_ptr_r))][0U]; + vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__cwb_queue__DOT__genblk3__DOT__genblk2__DOT__head_r[1U] + = vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__cwb_queue__DOT__genblk3__DOT__data + [((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__cwb_queue__DOT__reading) + ? (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__cwb_queue__DOT__genblk3__DOT__genblk2__DOT__rd_ptr_next_r) + : (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__cwb_queue__DOT__genblk3__DOT__genblk2__DOT__rd_ptr_r))][1U]; + vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__cwb_queue__DOT__genblk3__DOT__genblk2__DOT__head_r[2U] + = vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__cwb_queue__DOT__genblk3__DOT__data + [((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__cwb_queue__DOT__reading) + ? (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__cwb_queue__DOT__genblk3__DOT__genblk2__DOT__rd_ptr_next_r) + : (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__cwb_queue__DOT__genblk3__DOT__genblk2__DOT__rd_ptr_r))][2U]; + } + if (vlTOPp->reset) { + __Vdly__VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cwb_queue__DOT__size_r = 0U; + vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cwb_queue__DOT__genblk3__DOT__genblk2__DOT__head_r[0U] = 0U; + vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cwb_queue__DOT__genblk3__DOT__genblk2__DOT__head_r[1U] = 0U; + vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cwb_queue__DOT__genblk3__DOT__genblk2__DOT__head_r[2U] = 0U; + vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cwb_queue__DOT__genblk3__DOT__genblk2__DOT__curr_r[0U] = 0U; + vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cwb_queue__DOT__genblk3__DOT__genblk2__DOT__curr_r[1U] = 0U; + vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cwb_queue__DOT__genblk3__DOT__genblk2__DOT__curr_r[2U] = 0U; + __Vdly__VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cwb_queue__DOT__genblk3__DOT__genblk2__DOT__wr_ptr_r = 0U; + __Vdly__VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cwb_queue__DOT__genblk3__DOT__genblk2__DOT__rd_ptr_r = 0U; + __Vdly__VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cwb_queue__DOT__genblk3__DOT__genblk2__DOT__rd_ptr_next_r = 1U; + __Vdly__VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cwb_queue__DOT__genblk3__DOT__genblk2__DOT__empty_r = 1U; + vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cwb_queue__DOT__genblk3__DOT__genblk2__DOT__full_r = 0U; + } else { + if (vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cwb_queue__DOT__writing) { + __Vdlyvval__VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cwb_queue__DOT__genblk3__DOT__data__v0[0U] + = vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT____Vcellinp__cwb_queue__data_in[0U]; + __Vdlyvval__VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cwb_queue__DOT__genblk3__DOT__data__v0[1U] + = vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT____Vcellinp__cwb_queue__data_in[1U]; + __Vdlyvval__VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cwb_queue__DOT__genblk3__DOT__data__v0[2U] + = vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT____Vcellinp__cwb_queue__data_in[2U]; + __Vdlyvset__VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cwb_queue__DOT__genblk3__DOT__data__v0 = 1U; + __Vdlyvdim0__VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cwb_queue__DOT__genblk3__DOT__data__v0 + = vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cwb_queue__DOT__genblk3__DOT__genblk2__DOT__wr_ptr_r; + if ((1U & (~ (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cwb_queue__DOT__reading)))) { + __Vdly__VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cwb_queue__DOT__genblk3__DOT__genblk2__DOT__empty_r = 0U; + if ((3U == (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cwb_queue__DOT__size_r))) { + vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cwb_queue__DOT__genblk3__DOT__genblk2__DOT__full_r = 1U; + } + __Vdly__VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cwb_queue__DOT__size_r + = (7U & ((IData)(1U) + (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cwb_queue__DOT__size_r))); + } + __Vdly__VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cwb_queue__DOT__genblk3__DOT__genblk2__DOT__wr_ptr_r + = (3U & ((IData)(1U) + (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cwb_queue__DOT__genblk3__DOT__genblk2__DOT__wr_ptr_r))); + } + vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cwb_queue__DOT__genblk3__DOT__genblk2__DOT__curr_r[0U] + = vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT____Vcellinp__cwb_queue__data_in[0U]; + vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cwb_queue__DOT__genblk3__DOT__genblk2__DOT__curr_r[1U] + = vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT____Vcellinp__cwb_queue__data_in[1U]; + vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cwb_queue__DOT__genblk3__DOT__genblk2__DOT__curr_r[2U] + = vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT____Vcellinp__cwb_queue__data_in[2U]; + if (vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cwb_queue__DOT__reading) { + __Vdly__VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cwb_queue__DOT__genblk3__DOT__genblk2__DOT__rd_ptr_r + = vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cwb_queue__DOT__genblk3__DOT__genblk2__DOT__rd_ptr_next_r; + if ((1U & (~ (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cwb_queue__DOT__writing)))) { + if ((1U == (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cwb_queue__DOT__size_r))) { + if (Verilated::assertOn()) { + if (VL_UNLIKELY(((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cwb_queue__DOT__genblk3__DOT__genblk2__DOT__rd_ptr_next_r) + != (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cwb_queue__DOT__genblk3__DOT__genblk2__DOT__wr_ptr_r)))) { + VL_WRITEF("[%0t] %%Error: VX_generic_queue.v:144: Assertion failed in %NVX_cache.genblk5[0].bank.cwb_queue.genblk3.genblk2: 'assert' failed.\n", + 64,VL_TIME_Q(), + vlSymsp->name()); + VL_STOP_MT("../../rtl/libs/VX_generic_queue.v", 144, ""); + } + } + __Vdly__VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cwb_queue__DOT__genblk3__DOT__genblk2__DOT__empty_r = 1U; + } + vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cwb_queue__DOT__genblk3__DOT__genblk2__DOT__full_r = 0U; + __Vdly__VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cwb_queue__DOT__size_r + = (7U & ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cwb_queue__DOT__size_r) + - (IData)(1U))); + } + __Vdly__VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cwb_queue__DOT__genblk3__DOT__genblk2__DOT__rd_ptr_next_r + = (3U & ((IData)(2U) + (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cwb_queue__DOT__genblk3__DOT__genblk2__DOT__rd_ptr_r))); + } + vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cwb_queue__DOT__genblk3__DOT__genblk2__DOT__bypass_r + = ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cwb_queue__DOT__writing) + & ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cwb_queue__DOT__genblk3__DOT__genblk2__DOT__empty_r) + | ((1U == (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cwb_queue__DOT__size_r)) + & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cwb_queue__DOT__reading)))); + vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cwb_queue__DOT__genblk3__DOT__genblk2__DOT__head_r[0U] + = vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cwb_queue__DOT__genblk3__DOT__data + [((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cwb_queue__DOT__reading) + ? (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cwb_queue__DOT__genblk3__DOT__genblk2__DOT__rd_ptr_next_r) + : (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cwb_queue__DOT__genblk3__DOT__genblk2__DOT__rd_ptr_r))][0U]; + vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cwb_queue__DOT__genblk3__DOT__genblk2__DOT__head_r[1U] + = vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cwb_queue__DOT__genblk3__DOT__data + [((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cwb_queue__DOT__reading) + ? (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cwb_queue__DOT__genblk3__DOT__genblk2__DOT__rd_ptr_next_r) + : (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cwb_queue__DOT__genblk3__DOT__genblk2__DOT__rd_ptr_r))][1U]; + vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cwb_queue__DOT__genblk3__DOT__genblk2__DOT__head_r[2U] + = vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cwb_queue__DOT__genblk3__DOT__data + [((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cwb_queue__DOT__reading) + ? (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cwb_queue__DOT__genblk3__DOT__genblk2__DOT__rd_ptr_next_r) + : (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cwb_queue__DOT__genblk3__DOT__genblk2__DOT__rd_ptr_r))][2U]; + } + if (vlTOPp->reset) { + vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__core_req_arb__DOT__use_per_valids = 0U; + } else { + if (vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__core_req_arb__DOT__pop_qual) { + vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__core_req_arb__DOT__use_per_valids + = (0xfU & ((vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__core_req_arb__DOT____Vcellout__reqq_queue__data_out[9U] + >> 0x16U) & VL_NEGATE_I((IData)( + (1U + & (~ (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__core_req_arb__DOT__out_empty))))))); + } else { + if (vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__reqq_pop) { + vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__core_req_arb__DOT__use_per_valids + = ((~ ((IData)(1U) << (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__core_req_arb__DOT__qual_request_index))) + & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__core_req_arb__DOT__use_per_valids)); + } + } + } + if (vlTOPp->reset) { + vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__core_req_arb__DOT__use_per_valids = 0U; + } else { + if (vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__core_req_arb__DOT__pop_qual) { + vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__core_req_arb__DOT__use_per_valids + = (0xfU & ((vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__core_req_arb__DOT____Vcellout__reqq_queue__data_out[9U] + >> 0x16U) & VL_NEGATE_I((IData)( + (1U + & (~ (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__core_req_arb__DOT__out_empty))))))); + } else { + if (vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__reqq_pop) { + vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__core_req_arb__DOT__use_per_valids + = ((~ ((IData)(1U) << (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__core_req_arb__DOT__qual_request_index))) + & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__core_req_arb__DOT__use_per_valids)); + } + } + } + if (vlTOPp->reset) { + vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__core_req_arb__DOT__use_per_valids = 0U; + } else { + if (vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__core_req_arb__DOT__pop_qual) { + vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__core_req_arb__DOT__use_per_valids + = (0xfU & ((vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__core_req_arb__DOT____Vcellout__reqq_queue__data_out[9U] + >> 0x16U) & VL_NEGATE_I((IData)( + (1U + & (~ (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__core_req_arb__DOT__out_empty))))))); + } else { + if (vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__reqq_pop) { + vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__core_req_arb__DOT__use_per_valids + = ((~ ((IData)(1U) << (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__core_req_arb__DOT__qual_request_index))) + & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__core_req_arb__DOT__use_per_valids)); + } + } + } + if (vlTOPp->reset) { + vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__core_req_arb__DOT__use_per_valids = 0U; + } else { + if (vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__core_req_arb__DOT__pop_qual) { + vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__core_req_arb__DOT__use_per_valids + = (0xfU & ((vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__core_req_arb__DOT____Vcellout__reqq_queue__data_out[9U] + >> 0x16U) & VL_NEGATE_I((IData)( + (1U + & (~ (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__core_req_arb__DOT__out_empty))))))); + } else { + if (vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__reqq_pop) { + vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__core_req_arb__DOT__use_per_valids + = ((~ ((IData)(1U) << (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__core_req_arb__DOT__qual_request_index))) + & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__core_req_arb__DOT__use_per_valids)); + } + } + } + if (vlTOPp->reset) { + __Vdly__VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__dfp_queue__DOT__size_r = 0U; + vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__dfp_queue__DOT__genblk3__DOT__genblk2__DOT__head_r[0U] = 0U; + vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__dfp_queue__DOT__genblk3__DOT__genblk2__DOT__head_r[1U] = 0U; + vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__dfp_queue__DOT__genblk3__DOT__genblk2__DOT__head_r[2U] = 0U; + vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__dfp_queue__DOT__genblk3__DOT__genblk2__DOT__head_r[3U] = 0U; + vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__dfp_queue__DOT__genblk3__DOT__genblk2__DOT__head_r[4U] = 0U; + vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__dfp_queue__DOT__genblk3__DOT__genblk2__DOT__curr_r[0U] = 0U; + vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__dfp_queue__DOT__genblk3__DOT__genblk2__DOT__curr_r[1U] = 0U; + vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__dfp_queue__DOT__genblk3__DOT__genblk2__DOT__curr_r[2U] = 0U; + vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__dfp_queue__DOT__genblk3__DOT__genblk2__DOT__curr_r[3U] = 0U; + vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__dfp_queue__DOT__genblk3__DOT__genblk2__DOT__curr_r[4U] = 0U; + __Vdly__VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__dfp_queue__DOT__genblk3__DOT__genblk2__DOT__wr_ptr_r = 0U; + __Vdly__VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__dfp_queue__DOT__genblk3__DOT__genblk2__DOT__rd_ptr_r = 0U; + __Vdly__VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__dfp_queue__DOT__genblk3__DOT__genblk2__DOT__rd_ptr_next_r = 1U; + __Vdly__VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__dfp_queue__DOT__genblk3__DOT__genblk2__DOT__empty_r = 1U; + vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__dfp_queue__DOT__genblk3__DOT__genblk2__DOT__full_r = 0U; + } else { + if (vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__dfp_queue__DOT__writing) { + __Vdlyvval__VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__dfp_queue__DOT__genblk3__DOT__data__v0[0U] + = vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT____Vcellinp__dfp_queue__data_in[0U]; + __Vdlyvval__VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__dfp_queue__DOT__genblk3__DOT__data__v0[1U] + = vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT____Vcellinp__dfp_queue__data_in[1U]; + __Vdlyvval__VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__dfp_queue__DOT__genblk3__DOT__data__v0[2U] + = vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT____Vcellinp__dfp_queue__data_in[2U]; + __Vdlyvval__VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__dfp_queue__DOT__genblk3__DOT__data__v0[3U] + = vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT____Vcellinp__dfp_queue__data_in[3U]; + __Vdlyvval__VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__dfp_queue__DOT__genblk3__DOT__data__v0[4U] + = vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT____Vcellinp__dfp_queue__data_in[4U]; + __Vdlyvset__VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__dfp_queue__DOT__genblk3__DOT__data__v0 = 1U; + __Vdlyvdim0__VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__dfp_queue__DOT__genblk3__DOT__data__v0 + = vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__dfp_queue__DOT__genblk3__DOT__genblk2__DOT__wr_ptr_r; + if ((1U & (~ (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__dfp_queue__DOT__reading)))) { + __Vdly__VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__dfp_queue__DOT__genblk3__DOT__genblk2__DOT__empty_r = 0U; + if ((0xfU == (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__dfp_queue__DOT__size_r))) { + vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__dfp_queue__DOT__genblk3__DOT__genblk2__DOT__full_r = 1U; + } + __Vdly__VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__dfp_queue__DOT__size_r + = (0x1fU & ((IData)(1U) + (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__dfp_queue__DOT__size_r))); + } + __Vdly__VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__dfp_queue__DOT__genblk3__DOT__genblk2__DOT__wr_ptr_r + = (0xfU & ((IData)(1U) + (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__dfp_queue__DOT__genblk3__DOT__genblk2__DOT__wr_ptr_r))); + } + vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__dfp_queue__DOT__genblk3__DOT__genblk2__DOT__curr_r[0U] + = vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT____Vcellinp__dfp_queue__data_in[0U]; + vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__dfp_queue__DOT__genblk3__DOT__genblk2__DOT__curr_r[1U] + = vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT____Vcellinp__dfp_queue__data_in[1U]; + vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__dfp_queue__DOT__genblk3__DOT__genblk2__DOT__curr_r[2U] + = vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT____Vcellinp__dfp_queue__data_in[2U]; + vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__dfp_queue__DOT__genblk3__DOT__genblk2__DOT__curr_r[3U] + = vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT____Vcellinp__dfp_queue__data_in[3U]; + vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__dfp_queue__DOT__genblk3__DOT__genblk2__DOT__curr_r[4U] + = vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT____Vcellinp__dfp_queue__data_in[4U]; + if (vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__dfp_queue__DOT__reading) { + __Vdly__VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__dfp_queue__DOT__genblk3__DOT__genblk2__DOT__rd_ptr_r + = vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__dfp_queue__DOT__genblk3__DOT__genblk2__DOT__rd_ptr_next_r; + if ((1U & (~ (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__dfp_queue__DOT__writing)))) { + if ((1U == (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__dfp_queue__DOT__size_r))) { + if (Verilated::assertOn()) { + if (VL_UNLIKELY(((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__dfp_queue__DOT__genblk3__DOT__genblk2__DOT__rd_ptr_next_r) + != (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__dfp_queue__DOT__genblk3__DOT__genblk2__DOT__wr_ptr_r)))) { + VL_WRITEF("[%0t] %%Error: VX_generic_queue.v:144: Assertion failed in %NVX_cache.genblk5[3].bank.dfp_queue.genblk3.genblk2: 'assert' failed.\n", + 64,VL_TIME_Q(), + vlSymsp->name()); + VL_STOP_MT("../../rtl/libs/VX_generic_queue.v", 144, ""); + } + } + __Vdly__VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__dfp_queue__DOT__genblk3__DOT__genblk2__DOT__empty_r = 1U; + } + vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__dfp_queue__DOT__genblk3__DOT__genblk2__DOT__full_r = 0U; + __Vdly__VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__dfp_queue__DOT__size_r + = (0x1fU & ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__dfp_queue__DOT__size_r) + - (IData)(1U))); + } + __Vdly__VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__dfp_queue__DOT__genblk3__DOT__genblk2__DOT__rd_ptr_next_r + = (0xfU & ((IData)(2U) + (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__dfp_queue__DOT__genblk3__DOT__genblk2__DOT__rd_ptr_r))); + } + vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__dfp_queue__DOT__genblk3__DOT__genblk2__DOT__bypass_r + = ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__dfp_queue__DOT__writing) + & ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__dfp_queue__DOT__genblk3__DOT__genblk2__DOT__empty_r) + | ((1U == (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__dfp_queue__DOT__size_r)) + & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__dfp_queue__DOT__reading)))); + vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__dfp_queue__DOT__genblk3__DOT__genblk2__DOT__head_r[0U] + = vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__dfp_queue__DOT__genblk3__DOT__data + [((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__dfp_queue__DOT__reading) + ? (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__dfp_queue__DOT__genblk3__DOT__genblk2__DOT__rd_ptr_next_r) + : (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__dfp_queue__DOT__genblk3__DOT__genblk2__DOT__rd_ptr_r))][0U]; + vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__dfp_queue__DOT__genblk3__DOT__genblk2__DOT__head_r[1U] + = vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__dfp_queue__DOT__genblk3__DOT__data + [((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__dfp_queue__DOT__reading) + ? (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__dfp_queue__DOT__genblk3__DOT__genblk2__DOT__rd_ptr_next_r) + : (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__dfp_queue__DOT__genblk3__DOT__genblk2__DOT__rd_ptr_r))][1U]; + vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__dfp_queue__DOT__genblk3__DOT__genblk2__DOT__head_r[2U] + = vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__dfp_queue__DOT__genblk3__DOT__data + [((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__dfp_queue__DOT__reading) + ? (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__dfp_queue__DOT__genblk3__DOT__genblk2__DOT__rd_ptr_next_r) + : (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__dfp_queue__DOT__genblk3__DOT__genblk2__DOT__rd_ptr_r))][2U]; + vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__dfp_queue__DOT__genblk3__DOT__genblk2__DOT__head_r[3U] + = vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__dfp_queue__DOT__genblk3__DOT__data + [((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__dfp_queue__DOT__reading) + ? (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__dfp_queue__DOT__genblk3__DOT__genblk2__DOT__rd_ptr_next_r) + : (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__dfp_queue__DOT__genblk3__DOT__genblk2__DOT__rd_ptr_r))][3U]; + vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__dfp_queue__DOT__genblk3__DOT__genblk2__DOT__head_r[4U] + = vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__dfp_queue__DOT__genblk3__DOT__data + [((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__dfp_queue__DOT__reading) + ? (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__dfp_queue__DOT__genblk3__DOT__genblk2__DOT__rd_ptr_next_r) + : (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__dfp_queue__DOT__genblk3__DOT__genblk2__DOT__rd_ptr_r))][4U]; + } + if (vlTOPp->reset) { + __Vdly__VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__dfp_queue__DOT__size_r = 0U; + vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__dfp_queue__DOT__genblk3__DOT__genblk2__DOT__head_r[0U] = 0U; + vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__dfp_queue__DOT__genblk3__DOT__genblk2__DOT__head_r[1U] = 0U; + vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__dfp_queue__DOT__genblk3__DOT__genblk2__DOT__head_r[2U] = 0U; + vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__dfp_queue__DOT__genblk3__DOT__genblk2__DOT__head_r[3U] = 0U; + vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__dfp_queue__DOT__genblk3__DOT__genblk2__DOT__head_r[4U] = 0U; + vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__dfp_queue__DOT__genblk3__DOT__genblk2__DOT__curr_r[0U] = 0U; + vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__dfp_queue__DOT__genblk3__DOT__genblk2__DOT__curr_r[1U] = 0U; + vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__dfp_queue__DOT__genblk3__DOT__genblk2__DOT__curr_r[2U] = 0U; + vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__dfp_queue__DOT__genblk3__DOT__genblk2__DOT__curr_r[3U] = 0U; + vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__dfp_queue__DOT__genblk3__DOT__genblk2__DOT__curr_r[4U] = 0U; + __Vdly__VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__dfp_queue__DOT__genblk3__DOT__genblk2__DOT__wr_ptr_r = 0U; + __Vdly__VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__dfp_queue__DOT__genblk3__DOT__genblk2__DOT__rd_ptr_r = 0U; + __Vdly__VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__dfp_queue__DOT__genblk3__DOT__genblk2__DOT__rd_ptr_next_r = 1U; + __Vdly__VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__dfp_queue__DOT__genblk3__DOT__genblk2__DOT__empty_r = 1U; + vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__dfp_queue__DOT__genblk3__DOT__genblk2__DOT__full_r = 0U; + } else { + if (vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__dfp_queue__DOT__writing) { + __Vdlyvval__VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__dfp_queue__DOT__genblk3__DOT__data__v0[0U] + = vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT____Vcellinp__dfp_queue__data_in[0U]; + __Vdlyvval__VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__dfp_queue__DOT__genblk3__DOT__data__v0[1U] + = vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT____Vcellinp__dfp_queue__data_in[1U]; + __Vdlyvval__VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__dfp_queue__DOT__genblk3__DOT__data__v0[2U] + = vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT____Vcellinp__dfp_queue__data_in[2U]; + __Vdlyvval__VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__dfp_queue__DOT__genblk3__DOT__data__v0[3U] + = vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT____Vcellinp__dfp_queue__data_in[3U]; + __Vdlyvval__VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__dfp_queue__DOT__genblk3__DOT__data__v0[4U] + = vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT____Vcellinp__dfp_queue__data_in[4U]; + __Vdlyvset__VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__dfp_queue__DOT__genblk3__DOT__data__v0 = 1U; + __Vdlyvdim0__VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__dfp_queue__DOT__genblk3__DOT__data__v0 + = vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__dfp_queue__DOT__genblk3__DOT__genblk2__DOT__wr_ptr_r; + if ((1U & (~ (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__dfp_queue__DOT__reading)))) { + __Vdly__VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__dfp_queue__DOT__genblk3__DOT__genblk2__DOT__empty_r = 0U; + if ((0xfU == (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__dfp_queue__DOT__size_r))) { + vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__dfp_queue__DOT__genblk3__DOT__genblk2__DOT__full_r = 1U; + } + __Vdly__VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__dfp_queue__DOT__size_r + = (0x1fU & ((IData)(1U) + (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__dfp_queue__DOT__size_r))); + } + __Vdly__VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__dfp_queue__DOT__genblk3__DOT__genblk2__DOT__wr_ptr_r + = (0xfU & ((IData)(1U) + (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__dfp_queue__DOT__genblk3__DOT__genblk2__DOT__wr_ptr_r))); + } + vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__dfp_queue__DOT__genblk3__DOT__genblk2__DOT__curr_r[0U] + = vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT____Vcellinp__dfp_queue__data_in[0U]; + vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__dfp_queue__DOT__genblk3__DOT__genblk2__DOT__curr_r[1U] + = vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT____Vcellinp__dfp_queue__data_in[1U]; + vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__dfp_queue__DOT__genblk3__DOT__genblk2__DOT__curr_r[2U] + = vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT____Vcellinp__dfp_queue__data_in[2U]; + vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__dfp_queue__DOT__genblk3__DOT__genblk2__DOT__curr_r[3U] + = vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT____Vcellinp__dfp_queue__data_in[3U]; + vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__dfp_queue__DOT__genblk3__DOT__genblk2__DOT__curr_r[4U] + = vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT____Vcellinp__dfp_queue__data_in[4U]; + if (vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__dfp_queue__DOT__reading) { + __Vdly__VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__dfp_queue__DOT__genblk3__DOT__genblk2__DOT__rd_ptr_r + = vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__dfp_queue__DOT__genblk3__DOT__genblk2__DOT__rd_ptr_next_r; + if ((1U & (~ (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__dfp_queue__DOT__writing)))) { + if ((1U == (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__dfp_queue__DOT__size_r))) { + if (Verilated::assertOn()) { + if (VL_UNLIKELY(((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__dfp_queue__DOT__genblk3__DOT__genblk2__DOT__rd_ptr_next_r) + != (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__dfp_queue__DOT__genblk3__DOT__genblk2__DOT__wr_ptr_r)))) { + VL_WRITEF("[%0t] %%Error: VX_generic_queue.v:144: Assertion failed in %NVX_cache.genblk5[2].bank.dfp_queue.genblk3.genblk2: 'assert' failed.\n", + 64,VL_TIME_Q(), + vlSymsp->name()); + VL_STOP_MT("../../rtl/libs/VX_generic_queue.v", 144, ""); + } + } + __Vdly__VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__dfp_queue__DOT__genblk3__DOT__genblk2__DOT__empty_r = 1U; + } + vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__dfp_queue__DOT__genblk3__DOT__genblk2__DOT__full_r = 0U; + __Vdly__VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__dfp_queue__DOT__size_r + = (0x1fU & ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__dfp_queue__DOT__size_r) + - (IData)(1U))); + } + __Vdly__VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__dfp_queue__DOT__genblk3__DOT__genblk2__DOT__rd_ptr_next_r + = (0xfU & ((IData)(2U) + (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__dfp_queue__DOT__genblk3__DOT__genblk2__DOT__rd_ptr_r))); + } + vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__dfp_queue__DOT__genblk3__DOT__genblk2__DOT__bypass_r + = ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__dfp_queue__DOT__writing) + & ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__dfp_queue__DOT__genblk3__DOT__genblk2__DOT__empty_r) + | ((1U == (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__dfp_queue__DOT__size_r)) + & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__dfp_queue__DOT__reading)))); + vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__dfp_queue__DOT__genblk3__DOT__genblk2__DOT__head_r[0U] + = vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__dfp_queue__DOT__genblk3__DOT__data + [((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__dfp_queue__DOT__reading) + ? (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__dfp_queue__DOT__genblk3__DOT__genblk2__DOT__rd_ptr_next_r) + : (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__dfp_queue__DOT__genblk3__DOT__genblk2__DOT__rd_ptr_r))][0U]; + vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__dfp_queue__DOT__genblk3__DOT__genblk2__DOT__head_r[1U] + = vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__dfp_queue__DOT__genblk3__DOT__data + [((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__dfp_queue__DOT__reading) + ? (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__dfp_queue__DOT__genblk3__DOT__genblk2__DOT__rd_ptr_next_r) + : (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__dfp_queue__DOT__genblk3__DOT__genblk2__DOT__rd_ptr_r))][1U]; + vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__dfp_queue__DOT__genblk3__DOT__genblk2__DOT__head_r[2U] + = vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__dfp_queue__DOT__genblk3__DOT__data + [((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__dfp_queue__DOT__reading) + ? (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__dfp_queue__DOT__genblk3__DOT__genblk2__DOT__rd_ptr_next_r) + : (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__dfp_queue__DOT__genblk3__DOT__genblk2__DOT__rd_ptr_r))][2U]; + vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__dfp_queue__DOT__genblk3__DOT__genblk2__DOT__head_r[3U] + = vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__dfp_queue__DOT__genblk3__DOT__data + [((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__dfp_queue__DOT__reading) + ? (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__dfp_queue__DOT__genblk3__DOT__genblk2__DOT__rd_ptr_next_r) + : (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__dfp_queue__DOT__genblk3__DOT__genblk2__DOT__rd_ptr_r))][3U]; + vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__dfp_queue__DOT__genblk3__DOT__genblk2__DOT__head_r[4U] + = vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__dfp_queue__DOT__genblk3__DOT__data + [((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__dfp_queue__DOT__reading) + ? (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__dfp_queue__DOT__genblk3__DOT__genblk2__DOT__rd_ptr_next_r) + : (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__dfp_queue__DOT__genblk3__DOT__genblk2__DOT__rd_ptr_r))][4U]; + } + if (vlTOPp->reset) { + __Vdly__VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__dfp_queue__DOT__size_r = 0U; + vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__dfp_queue__DOT__genblk3__DOT__genblk2__DOT__head_r[0U] = 0U; + vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__dfp_queue__DOT__genblk3__DOT__genblk2__DOT__head_r[1U] = 0U; + vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__dfp_queue__DOT__genblk3__DOT__genblk2__DOT__head_r[2U] = 0U; + vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__dfp_queue__DOT__genblk3__DOT__genblk2__DOT__head_r[3U] = 0U; + vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__dfp_queue__DOT__genblk3__DOT__genblk2__DOT__head_r[4U] = 0U; + vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__dfp_queue__DOT__genblk3__DOT__genblk2__DOT__curr_r[0U] = 0U; + vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__dfp_queue__DOT__genblk3__DOT__genblk2__DOT__curr_r[1U] = 0U; + vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__dfp_queue__DOT__genblk3__DOT__genblk2__DOT__curr_r[2U] = 0U; + vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__dfp_queue__DOT__genblk3__DOT__genblk2__DOT__curr_r[3U] = 0U; + vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__dfp_queue__DOT__genblk3__DOT__genblk2__DOT__curr_r[4U] = 0U; + __Vdly__VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__dfp_queue__DOT__genblk3__DOT__genblk2__DOT__wr_ptr_r = 0U; + __Vdly__VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__dfp_queue__DOT__genblk3__DOT__genblk2__DOT__rd_ptr_r = 0U; + __Vdly__VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__dfp_queue__DOT__genblk3__DOT__genblk2__DOT__rd_ptr_next_r = 1U; + __Vdly__VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__dfp_queue__DOT__genblk3__DOT__genblk2__DOT__empty_r = 1U; + vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__dfp_queue__DOT__genblk3__DOT__genblk2__DOT__full_r = 0U; + } else { + if (vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__dfp_queue__DOT__writing) { + __Vdlyvval__VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__dfp_queue__DOT__genblk3__DOT__data__v0[0U] + = vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT____Vcellinp__dfp_queue__data_in[0U]; + __Vdlyvval__VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__dfp_queue__DOT__genblk3__DOT__data__v0[1U] + = vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT____Vcellinp__dfp_queue__data_in[1U]; + __Vdlyvval__VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__dfp_queue__DOT__genblk3__DOT__data__v0[2U] + = vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT____Vcellinp__dfp_queue__data_in[2U]; + __Vdlyvval__VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__dfp_queue__DOT__genblk3__DOT__data__v0[3U] + = vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT____Vcellinp__dfp_queue__data_in[3U]; + __Vdlyvval__VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__dfp_queue__DOT__genblk3__DOT__data__v0[4U] + = vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT____Vcellinp__dfp_queue__data_in[4U]; + __Vdlyvset__VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__dfp_queue__DOT__genblk3__DOT__data__v0 = 1U; + __Vdlyvdim0__VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__dfp_queue__DOT__genblk3__DOT__data__v0 + = vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__dfp_queue__DOT__genblk3__DOT__genblk2__DOT__wr_ptr_r; + if ((1U & (~ (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__dfp_queue__DOT__reading)))) { + __Vdly__VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__dfp_queue__DOT__genblk3__DOT__genblk2__DOT__empty_r = 0U; + if ((0xfU == (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__dfp_queue__DOT__size_r))) { + vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__dfp_queue__DOT__genblk3__DOT__genblk2__DOT__full_r = 1U; + } + __Vdly__VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__dfp_queue__DOT__size_r + = (0x1fU & ((IData)(1U) + (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__dfp_queue__DOT__size_r))); + } + __Vdly__VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__dfp_queue__DOT__genblk3__DOT__genblk2__DOT__wr_ptr_r + = (0xfU & ((IData)(1U) + (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__dfp_queue__DOT__genblk3__DOT__genblk2__DOT__wr_ptr_r))); + } + vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__dfp_queue__DOT__genblk3__DOT__genblk2__DOT__curr_r[0U] + = vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT____Vcellinp__dfp_queue__data_in[0U]; + vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__dfp_queue__DOT__genblk3__DOT__genblk2__DOT__curr_r[1U] + = vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT____Vcellinp__dfp_queue__data_in[1U]; + vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__dfp_queue__DOT__genblk3__DOT__genblk2__DOT__curr_r[2U] + = vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT____Vcellinp__dfp_queue__data_in[2U]; + vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__dfp_queue__DOT__genblk3__DOT__genblk2__DOT__curr_r[3U] + = vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT____Vcellinp__dfp_queue__data_in[3U]; + vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__dfp_queue__DOT__genblk3__DOT__genblk2__DOT__curr_r[4U] + = vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT____Vcellinp__dfp_queue__data_in[4U]; + if (vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__dfp_queue__DOT__reading) { + __Vdly__VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__dfp_queue__DOT__genblk3__DOT__genblk2__DOT__rd_ptr_r + = vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__dfp_queue__DOT__genblk3__DOT__genblk2__DOT__rd_ptr_next_r; + if ((1U & (~ (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__dfp_queue__DOT__writing)))) { + if ((1U == (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__dfp_queue__DOT__size_r))) { + if (Verilated::assertOn()) { + if (VL_UNLIKELY(((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__dfp_queue__DOT__genblk3__DOT__genblk2__DOT__rd_ptr_next_r) + != (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__dfp_queue__DOT__genblk3__DOT__genblk2__DOT__wr_ptr_r)))) { + VL_WRITEF("[%0t] %%Error: VX_generic_queue.v:144: Assertion failed in %NVX_cache.genblk5[1].bank.dfp_queue.genblk3.genblk2: 'assert' failed.\n", + 64,VL_TIME_Q(), + vlSymsp->name()); + VL_STOP_MT("../../rtl/libs/VX_generic_queue.v", 144, ""); + } + } + __Vdly__VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__dfp_queue__DOT__genblk3__DOT__genblk2__DOT__empty_r = 1U; + } + vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__dfp_queue__DOT__genblk3__DOT__genblk2__DOT__full_r = 0U; + __Vdly__VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__dfp_queue__DOT__size_r + = (0x1fU & ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__dfp_queue__DOT__size_r) + - (IData)(1U))); + } + __Vdly__VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__dfp_queue__DOT__genblk3__DOT__genblk2__DOT__rd_ptr_next_r + = (0xfU & ((IData)(2U) + (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__dfp_queue__DOT__genblk3__DOT__genblk2__DOT__rd_ptr_r))); + } + vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__dfp_queue__DOT__genblk3__DOT__genblk2__DOT__bypass_r + = ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__dfp_queue__DOT__writing) + & ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__dfp_queue__DOT__genblk3__DOT__genblk2__DOT__empty_r) + | ((1U == (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__dfp_queue__DOT__size_r)) + & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__dfp_queue__DOT__reading)))); + vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__dfp_queue__DOT__genblk3__DOT__genblk2__DOT__head_r[0U] + = vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__dfp_queue__DOT__genblk3__DOT__data + [((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__dfp_queue__DOT__reading) + ? (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__dfp_queue__DOT__genblk3__DOT__genblk2__DOT__rd_ptr_next_r) + : (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__dfp_queue__DOT__genblk3__DOT__genblk2__DOT__rd_ptr_r))][0U]; + vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__dfp_queue__DOT__genblk3__DOT__genblk2__DOT__head_r[1U] + = vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__dfp_queue__DOT__genblk3__DOT__data + [((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__dfp_queue__DOT__reading) + ? (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__dfp_queue__DOT__genblk3__DOT__genblk2__DOT__rd_ptr_next_r) + : (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__dfp_queue__DOT__genblk3__DOT__genblk2__DOT__rd_ptr_r))][1U]; + vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__dfp_queue__DOT__genblk3__DOT__genblk2__DOT__head_r[2U] + = vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__dfp_queue__DOT__genblk3__DOT__data + [((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__dfp_queue__DOT__reading) + ? (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__dfp_queue__DOT__genblk3__DOT__genblk2__DOT__rd_ptr_next_r) + : (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__dfp_queue__DOT__genblk3__DOT__genblk2__DOT__rd_ptr_r))][2U]; + vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__dfp_queue__DOT__genblk3__DOT__genblk2__DOT__head_r[3U] + = vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__dfp_queue__DOT__genblk3__DOT__data + [((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__dfp_queue__DOT__reading) + ? (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__dfp_queue__DOT__genblk3__DOT__genblk2__DOT__rd_ptr_next_r) + : (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__dfp_queue__DOT__genblk3__DOT__genblk2__DOT__rd_ptr_r))][3U]; + vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__dfp_queue__DOT__genblk3__DOT__genblk2__DOT__head_r[4U] + = vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__dfp_queue__DOT__genblk3__DOT__data + [((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__dfp_queue__DOT__reading) + ? (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__dfp_queue__DOT__genblk3__DOT__genblk2__DOT__rd_ptr_next_r) + : (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__dfp_queue__DOT__genblk3__DOT__genblk2__DOT__rd_ptr_r))][4U]; + } + if (vlTOPp->reset) { + __Vdly__VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__dfp_queue__DOT__size_r = 0U; + vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__dfp_queue__DOT__genblk3__DOT__genblk2__DOT__head_r[0U] = 0U; + vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__dfp_queue__DOT__genblk3__DOT__genblk2__DOT__head_r[1U] = 0U; + vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__dfp_queue__DOT__genblk3__DOT__genblk2__DOT__head_r[2U] = 0U; + vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__dfp_queue__DOT__genblk3__DOT__genblk2__DOT__head_r[3U] = 0U; + vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__dfp_queue__DOT__genblk3__DOT__genblk2__DOT__head_r[4U] = 0U; + vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__dfp_queue__DOT__genblk3__DOT__genblk2__DOT__curr_r[0U] = 0U; + vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__dfp_queue__DOT__genblk3__DOT__genblk2__DOT__curr_r[1U] = 0U; + vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__dfp_queue__DOT__genblk3__DOT__genblk2__DOT__curr_r[2U] = 0U; + vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__dfp_queue__DOT__genblk3__DOT__genblk2__DOT__curr_r[3U] = 0U; + vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__dfp_queue__DOT__genblk3__DOT__genblk2__DOT__curr_r[4U] = 0U; + __Vdly__VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__dfp_queue__DOT__genblk3__DOT__genblk2__DOT__wr_ptr_r = 0U; + __Vdly__VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__dfp_queue__DOT__genblk3__DOT__genblk2__DOT__rd_ptr_r = 0U; + __Vdly__VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__dfp_queue__DOT__genblk3__DOT__genblk2__DOT__rd_ptr_next_r = 1U; + __Vdly__VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__dfp_queue__DOT__genblk3__DOT__genblk2__DOT__empty_r = 1U; + vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__dfp_queue__DOT__genblk3__DOT__genblk2__DOT__full_r = 0U; + } else { + if (vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__dfp_queue__DOT__writing) { + __Vdlyvval__VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__dfp_queue__DOT__genblk3__DOT__data__v0[0U] + = vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT____Vcellinp__dfp_queue__data_in[0U]; + __Vdlyvval__VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__dfp_queue__DOT__genblk3__DOT__data__v0[1U] + = vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT____Vcellinp__dfp_queue__data_in[1U]; + __Vdlyvval__VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__dfp_queue__DOT__genblk3__DOT__data__v0[2U] + = vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT____Vcellinp__dfp_queue__data_in[2U]; + __Vdlyvval__VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__dfp_queue__DOT__genblk3__DOT__data__v0[3U] + = vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT____Vcellinp__dfp_queue__data_in[3U]; + __Vdlyvval__VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__dfp_queue__DOT__genblk3__DOT__data__v0[4U] + = vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT____Vcellinp__dfp_queue__data_in[4U]; + __Vdlyvset__VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__dfp_queue__DOT__genblk3__DOT__data__v0 = 1U; + __Vdlyvdim0__VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__dfp_queue__DOT__genblk3__DOT__data__v0 + = vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__dfp_queue__DOT__genblk3__DOT__genblk2__DOT__wr_ptr_r; + if ((1U & (~ (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__dfp_queue__DOT__reading)))) { + __Vdly__VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__dfp_queue__DOT__genblk3__DOT__genblk2__DOT__empty_r = 0U; + if ((0xfU == (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__dfp_queue__DOT__size_r))) { + vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__dfp_queue__DOT__genblk3__DOT__genblk2__DOT__full_r = 1U; + } + __Vdly__VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__dfp_queue__DOT__size_r + = (0x1fU & ((IData)(1U) + (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__dfp_queue__DOT__size_r))); + } + __Vdly__VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__dfp_queue__DOT__genblk3__DOT__genblk2__DOT__wr_ptr_r + = (0xfU & ((IData)(1U) + (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__dfp_queue__DOT__genblk3__DOT__genblk2__DOT__wr_ptr_r))); + } + vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__dfp_queue__DOT__genblk3__DOT__genblk2__DOT__curr_r[0U] + = vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT____Vcellinp__dfp_queue__data_in[0U]; + vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__dfp_queue__DOT__genblk3__DOT__genblk2__DOT__curr_r[1U] + = vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT____Vcellinp__dfp_queue__data_in[1U]; + vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__dfp_queue__DOT__genblk3__DOT__genblk2__DOT__curr_r[2U] + = vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT____Vcellinp__dfp_queue__data_in[2U]; + vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__dfp_queue__DOT__genblk3__DOT__genblk2__DOT__curr_r[3U] + = vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT____Vcellinp__dfp_queue__data_in[3U]; + vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__dfp_queue__DOT__genblk3__DOT__genblk2__DOT__curr_r[4U] + = vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT____Vcellinp__dfp_queue__data_in[4U]; + if (vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__dfp_queue__DOT__reading) { + __Vdly__VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__dfp_queue__DOT__genblk3__DOT__genblk2__DOT__rd_ptr_r + = vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__dfp_queue__DOT__genblk3__DOT__genblk2__DOT__rd_ptr_next_r; + if ((1U & (~ (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__dfp_queue__DOT__writing)))) { + if ((1U == (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__dfp_queue__DOT__size_r))) { + if (Verilated::assertOn()) { + if (VL_UNLIKELY(((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__dfp_queue__DOT__genblk3__DOT__genblk2__DOT__rd_ptr_next_r) + != (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__dfp_queue__DOT__genblk3__DOT__genblk2__DOT__wr_ptr_r)))) { + VL_WRITEF("[%0t] %%Error: VX_generic_queue.v:144: Assertion failed in %NVX_cache.genblk5[0].bank.dfp_queue.genblk3.genblk2: 'assert' failed.\n", + 64,VL_TIME_Q(), + vlSymsp->name()); + VL_STOP_MT("../../rtl/libs/VX_generic_queue.v", 144, ""); + } + } + __Vdly__VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__dfp_queue__DOT__genblk3__DOT__genblk2__DOT__empty_r = 1U; + } + vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__dfp_queue__DOT__genblk3__DOT__genblk2__DOT__full_r = 0U; + __Vdly__VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__dfp_queue__DOT__size_r + = (0x1fU & ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__dfp_queue__DOT__size_r) + - (IData)(1U))); + } + __Vdly__VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__dfp_queue__DOT__genblk3__DOT__genblk2__DOT__rd_ptr_next_r + = (0xfU & ((IData)(2U) + (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__dfp_queue__DOT__genblk3__DOT__genblk2__DOT__rd_ptr_r))); + } + vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__dfp_queue__DOT__genblk3__DOT__genblk2__DOT__bypass_r + = ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__dfp_queue__DOT__writing) + & ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__dfp_queue__DOT__genblk3__DOT__genblk2__DOT__empty_r) + | ((1U == (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__dfp_queue__DOT__size_r)) + & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__dfp_queue__DOT__reading)))); + vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__dfp_queue__DOT__genblk3__DOT__genblk2__DOT__head_r[0U] + = vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__dfp_queue__DOT__genblk3__DOT__data + [((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__dfp_queue__DOT__reading) + ? (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__dfp_queue__DOT__genblk3__DOT__genblk2__DOT__rd_ptr_next_r) + : (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__dfp_queue__DOT__genblk3__DOT__genblk2__DOT__rd_ptr_r))][0U]; + vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__dfp_queue__DOT__genblk3__DOT__genblk2__DOT__head_r[1U] + = vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__dfp_queue__DOT__genblk3__DOT__data + [((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__dfp_queue__DOT__reading) + ? (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__dfp_queue__DOT__genblk3__DOT__genblk2__DOT__rd_ptr_next_r) + : (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__dfp_queue__DOT__genblk3__DOT__genblk2__DOT__rd_ptr_r))][1U]; + vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__dfp_queue__DOT__genblk3__DOT__genblk2__DOT__head_r[2U] + = vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__dfp_queue__DOT__genblk3__DOT__data + [((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__dfp_queue__DOT__reading) + ? (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__dfp_queue__DOT__genblk3__DOT__genblk2__DOT__rd_ptr_next_r) + : (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__dfp_queue__DOT__genblk3__DOT__genblk2__DOT__rd_ptr_r))][2U]; + vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__dfp_queue__DOT__genblk3__DOT__genblk2__DOT__head_r[3U] + = vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__dfp_queue__DOT__genblk3__DOT__data + [((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__dfp_queue__DOT__reading) + ? (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__dfp_queue__DOT__genblk3__DOT__genblk2__DOT__rd_ptr_next_r) + : (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__dfp_queue__DOT__genblk3__DOT__genblk2__DOT__rd_ptr_r))][3U]; + vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__dfp_queue__DOT__genblk3__DOT__genblk2__DOT__head_r[4U] + = vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__dfp_queue__DOT__genblk3__DOT__data + [((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__dfp_queue__DOT__reading) + ? (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__dfp_queue__DOT__genblk3__DOT__genblk2__DOT__rd_ptr_next_r) + : (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__dfp_queue__DOT__genblk3__DOT__genblk2__DOT__rd_ptr_r))][4U]; + } + if (vlTOPp->reset) { + __Vdly__VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cache_miss_resrv__DOT__size = 0U; + } else { + if ((1U & (~ ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cache_miss_resrv__DOT__mrvq_push) + & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cache_miss_resrv__DOT__increment_head))))) { + if (vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cache_miss_resrv__DOT__mrvq_push) { + __Vdly__VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cache_miss_resrv__DOT__size + = (0x1fU & ((IData)(1U) + (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cache_miss_resrv__DOT__size))); + } + if (vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cache_miss_resrv__DOT__increment_head) { + __Vdly__VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cache_miss_resrv__DOT__size + = (0x1fU & ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cache_miss_resrv__DOT__size) + - (IData)(1U))); + } + } + } + if (vlTOPp->reset) { + __Vdly__VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__cache_miss_resrv__DOT__size = 0U; + } else { + if ((1U & (~ ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__cache_miss_resrv__DOT__mrvq_push) + & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__cache_miss_resrv__DOT__increment_head))))) { + if (vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__cache_miss_resrv__DOT__mrvq_push) { + __Vdly__VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__cache_miss_resrv__DOT__size + = (0x1fU & ((IData)(1U) + (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__cache_miss_resrv__DOT__size))); + } + if (vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__cache_miss_resrv__DOT__increment_head) { + __Vdly__VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__cache_miss_resrv__DOT__size + = (0x1fU & ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__cache_miss_resrv__DOT__size) + - (IData)(1U))); + } + } + } + if (vlTOPp->reset) { + __Vdly__VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__cache_miss_resrv__DOT__size = 0U; + } else { + if ((1U & (~ ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__cache_miss_resrv__DOT__mrvq_push) + & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__cache_miss_resrv__DOT__increment_head))))) { + if (vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__cache_miss_resrv__DOT__mrvq_push) { + __Vdly__VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__cache_miss_resrv__DOT__size + = (0x1fU & ((IData)(1U) + (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__cache_miss_resrv__DOT__size))); + } + if (vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__cache_miss_resrv__DOT__increment_head) { + __Vdly__VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__cache_miss_resrv__DOT__size + = (0x1fU & ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__cache_miss_resrv__DOT__size) + - (IData)(1U))); + } + } + } + if (vlTOPp->reset) { + __Vdly__VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cache_miss_resrv__DOT__size = 0U; + } else { + if ((1U & (~ ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cache_miss_resrv__DOT__mrvq_push) + & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cache_miss_resrv__DOT__increment_head))))) { + if (vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cache_miss_resrv__DOT__mrvq_push) { + __Vdly__VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cache_miss_resrv__DOT__size + = (0x1fU & ((IData)(1U) + (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cache_miss_resrv__DOT__size))); + } + if (vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cache_miss_resrv__DOT__increment_head) { + __Vdly__VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cache_miss_resrv__DOT__size + = (0x1fU & ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cache_miss_resrv__DOT__size) + - (IData)(1U))); + } + } + } + if (vlTOPp->reset) { + __Vdly__VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr = 0U; + } else { + if ((1U & (~ (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cache_miss_resrv__DOT__mrvq_push)))) { + if ((1U & (~ (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cache_miss_resrv__DOT__increment_head)))) { + if (((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__miss_add) + & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__miss_add_is_mrvq))) { + __Vdly__VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr + = (0xfU & ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr) + - (IData)(1U))); + } + } + } + if (vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cache_miss_resrv__DOT__mrvq_pop) { + __Vdly__VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr + = (0xfU & ((IData)(1U) + (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr))); + } + } + if (vlTOPp->reset) { + __Vdly__VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr = 0U; + } else { + if ((1U & (~ (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__cache_miss_resrv__DOT__mrvq_push)))) { + if ((1U & (~ (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__cache_miss_resrv__DOT__increment_head)))) { + if (((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__miss_add) + & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__miss_add_is_mrvq))) { + __Vdly__VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr + = (0xfU & ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr) + - (IData)(1U))); + } + } + } + if (vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__cache_miss_resrv__DOT__mrvq_pop) { + __Vdly__VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr + = (0xfU & ((IData)(1U) + (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr))); + } + } + if (vlTOPp->reset) { + __Vdly__VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr = 0U; + } else { + if ((1U & (~ (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__cache_miss_resrv__DOT__mrvq_push)))) { + if ((1U & (~ (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__cache_miss_resrv__DOT__increment_head)))) { + if (((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__miss_add) + & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__miss_add_is_mrvq))) { + __Vdly__VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr + = (0xfU & ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr) + - (IData)(1U))); + } + } + } + if (vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__cache_miss_resrv__DOT__mrvq_pop) { + __Vdly__VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr + = (0xfU & ((IData)(1U) + (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr))); + } + } + if (vlTOPp->reset) { + __Vdly__VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr = 0U; + } else { + if ((1U & (~ (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cache_miss_resrv__DOT__mrvq_push)))) { + if ((1U & (~ (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cache_miss_resrv__DOT__increment_head)))) { + if (((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__miss_add) + & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__miss_add_is_mrvq))) { + __Vdly__VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr + = (0xfU & ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr) + - (IData)(1U))); + } + } + } + if (vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cache_miss_resrv__DOT__mrvq_pop) { + __Vdly__VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr + = (0xfU & ((IData)(1U) + (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr))); + } + } + if (vlTOPp->reset) { + __Vdly__VX_cache__DOT__cache_dram_req_arb__DOT__dram_fill_arb__DOT__dfqq_queue__DOT__size_r = 0U; + vlTOPp->VX_cache__DOT__cache_dram_req_arb__DOT__dram_fill_arb__DOT__dfqq_queue__DOT__genblk3__DOT__genblk2__DOT__head_r[0U] = 0U; + vlTOPp->VX_cache__DOT__cache_dram_req_arb__DOT__dram_fill_arb__DOT__dfqq_queue__DOT__genblk3__DOT__genblk2__DOT__head_r[1U] = 0U; + vlTOPp->VX_cache__DOT__cache_dram_req_arb__DOT__dram_fill_arb__DOT__dfqq_queue__DOT__genblk3__DOT__genblk2__DOT__head_r[2U] = 0U; + vlTOPp->VX_cache__DOT__cache_dram_req_arb__DOT__dram_fill_arb__DOT__dfqq_queue__DOT__genblk3__DOT__genblk2__DOT__head_r[3U] = 0U; + vlTOPp->VX_cache__DOT__cache_dram_req_arb__DOT__dram_fill_arb__DOT__dfqq_queue__DOT__genblk3__DOT__genblk2__DOT__curr_r[0U] = 0U; + vlTOPp->VX_cache__DOT__cache_dram_req_arb__DOT__dram_fill_arb__DOT__dfqq_queue__DOT__genblk3__DOT__genblk2__DOT__curr_r[1U] = 0U; + vlTOPp->VX_cache__DOT__cache_dram_req_arb__DOT__dram_fill_arb__DOT__dfqq_queue__DOT__genblk3__DOT__genblk2__DOT__curr_r[2U] = 0U; + vlTOPp->VX_cache__DOT__cache_dram_req_arb__DOT__dram_fill_arb__DOT__dfqq_queue__DOT__genblk3__DOT__genblk2__DOT__curr_r[3U] = 0U; + __Vdly__VX_cache__DOT__cache_dram_req_arb__DOT__dram_fill_arb__DOT__dfqq_queue__DOT__genblk3__DOT__genblk2__DOT__wr_ptr_r = 0U; + __Vdly__VX_cache__DOT__cache_dram_req_arb__DOT__dram_fill_arb__DOT__dfqq_queue__DOT__genblk3__DOT__genblk2__DOT__rd_ptr_r = 0U; + __Vdly__VX_cache__DOT__cache_dram_req_arb__DOT__dram_fill_arb__DOT__dfqq_queue__DOT__genblk3__DOT__genblk2__DOT__rd_ptr_next_r = 1U; + __Vdly__VX_cache__DOT__cache_dram_req_arb__DOT__dram_fill_arb__DOT__dfqq_queue__DOT__genblk3__DOT__genblk2__DOT__empty_r = 1U; + vlTOPp->VX_cache__DOT__cache_dram_req_arb__DOT__dram_fill_arb__DOT__dfqq_queue__DOT__genblk3__DOT__genblk2__DOT__full_r = 0U; + } else { + if (vlTOPp->VX_cache__DOT__cache_dram_req_arb__DOT__dram_fill_arb__DOT__dfqq_queue__DOT__writing) { + __Vdlyvval__VX_cache__DOT__cache_dram_req_arb__DOT__dram_fill_arb__DOT__dfqq_queue__DOT__genblk3__DOT__data__v0[0U] + = vlTOPp->VX_cache__DOT__cache_dram_req_arb__DOT__dram_fill_arb__DOT____Vcellinp__dfqq_queue__data_in[0U]; + __Vdlyvval__VX_cache__DOT__cache_dram_req_arb__DOT__dram_fill_arb__DOT__dfqq_queue__DOT__genblk3__DOT__data__v0[1U] + = vlTOPp->VX_cache__DOT__cache_dram_req_arb__DOT__dram_fill_arb__DOT____Vcellinp__dfqq_queue__data_in[1U]; + __Vdlyvval__VX_cache__DOT__cache_dram_req_arb__DOT__dram_fill_arb__DOT__dfqq_queue__DOT__genblk3__DOT__data__v0[2U] + = vlTOPp->VX_cache__DOT__cache_dram_req_arb__DOT__dram_fill_arb__DOT____Vcellinp__dfqq_queue__data_in[2U]; + __Vdlyvval__VX_cache__DOT__cache_dram_req_arb__DOT__dram_fill_arb__DOT__dfqq_queue__DOT__genblk3__DOT__data__v0[3U] + = vlTOPp->VX_cache__DOT__cache_dram_req_arb__DOT__dram_fill_arb__DOT____Vcellinp__dfqq_queue__data_in[3U]; + __Vdlyvset__VX_cache__DOT__cache_dram_req_arb__DOT__dram_fill_arb__DOT__dfqq_queue__DOT__genblk3__DOT__data__v0 = 1U; + __Vdlyvdim0__VX_cache__DOT__cache_dram_req_arb__DOT__dram_fill_arb__DOT__dfqq_queue__DOT__genblk3__DOT__data__v0 + = vlTOPp->VX_cache__DOT__cache_dram_req_arb__DOT__dram_fill_arb__DOT__dfqq_queue__DOT__genblk3__DOT__genblk2__DOT__wr_ptr_r; + if ((1U & (~ (IData)(vlTOPp->VX_cache__DOT__cache_dram_req_arb__DOT__dram_fill_arb__DOT__dfqq_queue__DOT__reading)))) { + __Vdly__VX_cache__DOT__cache_dram_req_arb__DOT__dram_fill_arb__DOT__dfqq_queue__DOT__genblk3__DOT__genblk2__DOT__empty_r = 0U; + if ((3U == (IData)(vlTOPp->VX_cache__DOT__cache_dram_req_arb__DOT__dram_fill_arb__DOT__dfqq_queue__DOT__size_r))) { + vlTOPp->VX_cache__DOT__cache_dram_req_arb__DOT__dram_fill_arb__DOT__dfqq_queue__DOT__genblk3__DOT__genblk2__DOT__full_r = 1U; + } + __Vdly__VX_cache__DOT__cache_dram_req_arb__DOT__dram_fill_arb__DOT__dfqq_queue__DOT__size_r + = (7U & ((IData)(1U) + (IData)(vlTOPp->VX_cache__DOT__cache_dram_req_arb__DOT__dram_fill_arb__DOT__dfqq_queue__DOT__size_r))); + } + __Vdly__VX_cache__DOT__cache_dram_req_arb__DOT__dram_fill_arb__DOT__dfqq_queue__DOT__genblk3__DOT__genblk2__DOT__wr_ptr_r + = (3U & ((IData)(1U) + (IData)(vlTOPp->VX_cache__DOT__cache_dram_req_arb__DOT__dram_fill_arb__DOT__dfqq_queue__DOT__genblk3__DOT__genblk2__DOT__wr_ptr_r))); + } + vlTOPp->VX_cache__DOT__cache_dram_req_arb__DOT__dram_fill_arb__DOT__dfqq_queue__DOT__genblk3__DOT__genblk2__DOT__curr_r[0U] + = vlTOPp->VX_cache__DOT__cache_dram_req_arb__DOT__dram_fill_arb__DOT____Vcellinp__dfqq_queue__data_in[0U]; + vlTOPp->VX_cache__DOT__cache_dram_req_arb__DOT__dram_fill_arb__DOT__dfqq_queue__DOT__genblk3__DOT__genblk2__DOT__curr_r[1U] + = vlTOPp->VX_cache__DOT__cache_dram_req_arb__DOT__dram_fill_arb__DOT____Vcellinp__dfqq_queue__data_in[1U]; + vlTOPp->VX_cache__DOT__cache_dram_req_arb__DOT__dram_fill_arb__DOT__dfqq_queue__DOT__genblk3__DOT__genblk2__DOT__curr_r[2U] + = vlTOPp->VX_cache__DOT__cache_dram_req_arb__DOT__dram_fill_arb__DOT____Vcellinp__dfqq_queue__data_in[2U]; + vlTOPp->VX_cache__DOT__cache_dram_req_arb__DOT__dram_fill_arb__DOT__dfqq_queue__DOT__genblk3__DOT__genblk2__DOT__curr_r[3U] + = vlTOPp->VX_cache__DOT__cache_dram_req_arb__DOT__dram_fill_arb__DOT____Vcellinp__dfqq_queue__data_in[3U]; + if (vlTOPp->VX_cache__DOT__cache_dram_req_arb__DOT__dram_fill_arb__DOT__dfqq_queue__DOT__reading) { + __Vdly__VX_cache__DOT__cache_dram_req_arb__DOT__dram_fill_arb__DOT__dfqq_queue__DOT__genblk3__DOT__genblk2__DOT__rd_ptr_r + = vlTOPp->VX_cache__DOT__cache_dram_req_arb__DOT__dram_fill_arb__DOT__dfqq_queue__DOT__genblk3__DOT__genblk2__DOT__rd_ptr_next_r; + if ((1U & (~ (IData)(vlTOPp->VX_cache__DOT__cache_dram_req_arb__DOT__dram_fill_arb__DOT__dfqq_queue__DOT__writing)))) { + if ((1U == (IData)(vlTOPp->VX_cache__DOT__cache_dram_req_arb__DOT__dram_fill_arb__DOT__dfqq_queue__DOT__size_r))) { + if (Verilated::assertOn()) { + if (VL_UNLIKELY(((IData)(vlTOPp->VX_cache__DOT__cache_dram_req_arb__DOT__dram_fill_arb__DOT__dfqq_queue__DOT__genblk3__DOT__genblk2__DOT__rd_ptr_next_r) + != (IData)(vlTOPp->VX_cache__DOT__cache_dram_req_arb__DOT__dram_fill_arb__DOT__dfqq_queue__DOT__genblk3__DOT__genblk2__DOT__wr_ptr_r)))) { + VL_WRITEF("[%0t] %%Error: VX_generic_queue.v:144: Assertion failed in %NVX_cache.cache_dram_req_arb.dram_fill_arb.dfqq_queue.genblk3.genblk2: 'assert' failed.\n", + 64,VL_TIME_Q(), + vlSymsp->name()); + VL_STOP_MT("../../rtl/libs/VX_generic_queue.v", 144, ""); + } + } + __Vdly__VX_cache__DOT__cache_dram_req_arb__DOT__dram_fill_arb__DOT__dfqq_queue__DOT__genblk3__DOT__genblk2__DOT__empty_r = 1U; + } + vlTOPp->VX_cache__DOT__cache_dram_req_arb__DOT__dram_fill_arb__DOT__dfqq_queue__DOT__genblk3__DOT__genblk2__DOT__full_r = 0U; + __Vdly__VX_cache__DOT__cache_dram_req_arb__DOT__dram_fill_arb__DOT__dfqq_queue__DOT__size_r + = (7U & ((IData)(vlTOPp->VX_cache__DOT__cache_dram_req_arb__DOT__dram_fill_arb__DOT__dfqq_queue__DOT__size_r) + - (IData)(1U))); + } + __Vdly__VX_cache__DOT__cache_dram_req_arb__DOT__dram_fill_arb__DOT__dfqq_queue__DOT__genblk3__DOT__genblk2__DOT__rd_ptr_next_r + = (3U & ((IData)(2U) + (IData)(vlTOPp->VX_cache__DOT__cache_dram_req_arb__DOT__dram_fill_arb__DOT__dfqq_queue__DOT__genblk3__DOT__genblk2__DOT__rd_ptr_r))); + } + vlTOPp->VX_cache__DOT__cache_dram_req_arb__DOT__dram_fill_arb__DOT__dfqq_queue__DOT__genblk3__DOT__genblk2__DOT__bypass_r + = ((IData)(vlTOPp->VX_cache__DOT__cache_dram_req_arb__DOT__dram_fill_arb__DOT__dfqq_queue__DOT__writing) + & ((IData)(vlTOPp->VX_cache__DOT__cache_dram_req_arb__DOT__dram_fill_arb__DOT__dfqq_queue__DOT__genblk3__DOT__genblk2__DOT__empty_r) + | ((1U == (IData)(vlTOPp->VX_cache__DOT__cache_dram_req_arb__DOT__dram_fill_arb__DOT__dfqq_queue__DOT__size_r)) + & (IData)(vlTOPp->VX_cache__DOT__cache_dram_req_arb__DOT__dram_fill_arb__DOT__dfqq_queue__DOT__reading)))); + vlTOPp->VX_cache__DOT__cache_dram_req_arb__DOT__dram_fill_arb__DOT__dfqq_queue__DOT__genblk3__DOT__genblk2__DOT__head_r[0U] + = vlTOPp->VX_cache__DOT__cache_dram_req_arb__DOT__dram_fill_arb__DOT__dfqq_queue__DOT__genblk3__DOT__data + [((IData)(vlTOPp->VX_cache__DOT__cache_dram_req_arb__DOT__dram_fill_arb__DOT__dfqq_queue__DOT__reading) + ? (IData)(vlTOPp->VX_cache__DOT__cache_dram_req_arb__DOT__dram_fill_arb__DOT__dfqq_queue__DOT__genblk3__DOT__genblk2__DOT__rd_ptr_next_r) + : (IData)(vlTOPp->VX_cache__DOT__cache_dram_req_arb__DOT__dram_fill_arb__DOT__dfqq_queue__DOT__genblk3__DOT__genblk2__DOT__rd_ptr_r))][0U]; + vlTOPp->VX_cache__DOT__cache_dram_req_arb__DOT__dram_fill_arb__DOT__dfqq_queue__DOT__genblk3__DOT__genblk2__DOT__head_r[1U] + = vlTOPp->VX_cache__DOT__cache_dram_req_arb__DOT__dram_fill_arb__DOT__dfqq_queue__DOT__genblk3__DOT__data + [((IData)(vlTOPp->VX_cache__DOT__cache_dram_req_arb__DOT__dram_fill_arb__DOT__dfqq_queue__DOT__reading) + ? (IData)(vlTOPp->VX_cache__DOT__cache_dram_req_arb__DOT__dram_fill_arb__DOT__dfqq_queue__DOT__genblk3__DOT__genblk2__DOT__rd_ptr_next_r) + : (IData)(vlTOPp->VX_cache__DOT__cache_dram_req_arb__DOT__dram_fill_arb__DOT__dfqq_queue__DOT__genblk3__DOT__genblk2__DOT__rd_ptr_r))][1U]; + vlTOPp->VX_cache__DOT__cache_dram_req_arb__DOT__dram_fill_arb__DOT__dfqq_queue__DOT__genblk3__DOT__genblk2__DOT__head_r[2U] + = vlTOPp->VX_cache__DOT__cache_dram_req_arb__DOT__dram_fill_arb__DOT__dfqq_queue__DOT__genblk3__DOT__data + [((IData)(vlTOPp->VX_cache__DOT__cache_dram_req_arb__DOT__dram_fill_arb__DOT__dfqq_queue__DOT__reading) + ? (IData)(vlTOPp->VX_cache__DOT__cache_dram_req_arb__DOT__dram_fill_arb__DOT__dfqq_queue__DOT__genblk3__DOT__genblk2__DOT__rd_ptr_next_r) + : (IData)(vlTOPp->VX_cache__DOT__cache_dram_req_arb__DOT__dram_fill_arb__DOT__dfqq_queue__DOT__genblk3__DOT__genblk2__DOT__rd_ptr_r))][2U]; + vlTOPp->VX_cache__DOT__cache_dram_req_arb__DOT__dram_fill_arb__DOT__dfqq_queue__DOT__genblk3__DOT__genblk2__DOT__head_r[3U] + = vlTOPp->VX_cache__DOT__cache_dram_req_arb__DOT__dram_fill_arb__DOT__dfqq_queue__DOT__genblk3__DOT__data + [((IData)(vlTOPp->VX_cache__DOT__cache_dram_req_arb__DOT__dram_fill_arb__DOT__dfqq_queue__DOT__reading) + ? (IData)(vlTOPp->VX_cache__DOT__cache_dram_req_arb__DOT__dram_fill_arb__DOT__dfqq_queue__DOT__genblk3__DOT__genblk2__DOT__rd_ptr_next_r) + : (IData)(vlTOPp->VX_cache__DOT__cache_dram_req_arb__DOT__dram_fill_arb__DOT__dfqq_queue__DOT__genblk3__DOT__genblk2__DOT__rd_ptr_r))][3U]; + } + if (vlTOPp->reset) { + __Vdly__VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cache_miss_resrv__DOT__ready_table = 0U; + } else { + if (vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cache_miss_resrv__DOT__mrvq_push) { + __Vdly__VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cache_miss_resrv__DOT__ready_table + = (((~ ((IData)(1U) << (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cache_miss_resrv__DOT__tail_ptr))) + & (IData)(__Vdly__VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cache_miss_resrv__DOT__ready_table)) + | ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__mrvq_init_ready_state_st2) + << (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cache_miss_resrv__DOT__tail_ptr))); + } + if ((0U != (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cache_miss_resrv__DOT__make_ready))) { + __Vdly__VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cache_miss_resrv__DOT__ready_table + = (0xffffU & (((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cache_miss_resrv__DOT__ready_table) + | (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cache_miss_resrv__DOT__make_ready)) + | (((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cache_miss_resrv__DOT__mrvq_push) + & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__mrvq_init_ready_state_st2)) + << (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cache_miss_resrv__DOT__tail_ptr)))); + } + if (vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cache_miss_resrv__DOT__mrvq_pop) { + __Vdly__VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cache_miss_resrv__DOT__ready_table + = ((~ ((IData)(1U) << (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr))) + & (IData)(__Vdly__VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cache_miss_resrv__DOT__ready_table)); + } + } + if (vlTOPp->reset) { + __Vdly__VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__cache_miss_resrv__DOT__ready_table = 0U; + } else { + if (vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__cache_miss_resrv__DOT__mrvq_push) { + __Vdly__VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__cache_miss_resrv__DOT__ready_table + = (((~ ((IData)(1U) << (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__cache_miss_resrv__DOT__tail_ptr))) + & (IData)(__Vdly__VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__cache_miss_resrv__DOT__ready_table)) + | ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__mrvq_init_ready_state_st2) + << (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__cache_miss_resrv__DOT__tail_ptr))); + } + if ((0U != (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__cache_miss_resrv__DOT__make_ready))) { + __Vdly__VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__cache_miss_resrv__DOT__ready_table + = (0xffffU & (((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__cache_miss_resrv__DOT__ready_table) + | (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__cache_miss_resrv__DOT__make_ready)) + | (((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__cache_miss_resrv__DOT__mrvq_push) + & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__mrvq_init_ready_state_st2)) + << (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__cache_miss_resrv__DOT__tail_ptr)))); + } + if (vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__cache_miss_resrv__DOT__mrvq_pop) { + __Vdly__VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__cache_miss_resrv__DOT__ready_table + = ((~ ((IData)(1U) << (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr))) + & (IData)(__Vdly__VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__cache_miss_resrv__DOT__ready_table)); + } + } + if (vlTOPp->reset) { + __Vdly__VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__cache_miss_resrv__DOT__ready_table = 0U; + } else { + if (vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__cache_miss_resrv__DOT__mrvq_push) { + __Vdly__VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__cache_miss_resrv__DOT__ready_table + = (((~ ((IData)(1U) << (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__cache_miss_resrv__DOT__tail_ptr))) + & (IData)(__Vdly__VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__cache_miss_resrv__DOT__ready_table)) + | ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__mrvq_init_ready_state_st2) + << (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__cache_miss_resrv__DOT__tail_ptr))); + } + if ((0U != (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__cache_miss_resrv__DOT__make_ready))) { + __Vdly__VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__cache_miss_resrv__DOT__ready_table + = (0xffffU & (((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__cache_miss_resrv__DOT__ready_table) + | (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__cache_miss_resrv__DOT__make_ready)) + | (((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__cache_miss_resrv__DOT__mrvq_push) + & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__mrvq_init_ready_state_st2)) + << (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__cache_miss_resrv__DOT__tail_ptr)))); + } + if (vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__cache_miss_resrv__DOT__mrvq_pop) { + __Vdly__VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__cache_miss_resrv__DOT__ready_table + = ((~ ((IData)(1U) << (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr))) + & (IData)(__Vdly__VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__cache_miss_resrv__DOT__ready_table)); + } + } + if (vlTOPp->reset) { + __Vdly__VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cache_miss_resrv__DOT__ready_table = 0U; + } else { + if (vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cache_miss_resrv__DOT__mrvq_push) { + __Vdly__VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cache_miss_resrv__DOT__ready_table + = (((~ ((IData)(1U) << (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cache_miss_resrv__DOT__tail_ptr))) + & (IData)(__Vdly__VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cache_miss_resrv__DOT__ready_table)) + | ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__mrvq_init_ready_state_st2) + << (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cache_miss_resrv__DOT__tail_ptr))); + } + if ((0U != (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cache_miss_resrv__DOT__make_ready))) { + __Vdly__VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cache_miss_resrv__DOT__ready_table + = (0xffffU & (((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cache_miss_resrv__DOT__ready_table) + | (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cache_miss_resrv__DOT__make_ready)) + | (((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cache_miss_resrv__DOT__mrvq_push) + & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__mrvq_init_ready_state_st2)) + << (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cache_miss_resrv__DOT__tail_ptr)))); + } + if (vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cache_miss_resrv__DOT__mrvq_pop) { + __Vdly__VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cache_miss_resrv__DOT__ready_table + = ((~ ((IData)(1U) << (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr))) + & (IData)(__Vdly__VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cache_miss_resrv__DOT__ready_table)); + } + } + if (vlTOPp->reset) { + vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__tag_data_access__DOT__s0_1_c0__DOT__value[0U] = 0U; + vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__tag_data_access__DOT__s0_1_c0__DOT__value[1U] = 0U; + vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__tag_data_access__DOT__s0_1_c0__DOT__value[2U] = 0U; + vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__tag_data_access__DOT__s0_1_c0__DOT__value[3U] = 0U; + vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__tag_data_access__DOT__s0_1_c0__DOT__value[4U] = 0U; + vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__tag_data_access__DOT__s0_1_c0__DOT__value[5U] = 0U; + } else { + if ((1U & (~ (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__stall_bank_pipe)))) { + vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__tag_data_access__DOT__s0_1_c0__DOT__value[0U] + = vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__tag_data_access__DOT____Vcellinp__s0_1_c0__in[0U]; + vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__tag_data_access__DOT__s0_1_c0__DOT__value[1U] + = vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__tag_data_access__DOT____Vcellinp__s0_1_c0__in[1U]; + vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__tag_data_access__DOT__s0_1_c0__DOT__value[2U] + = vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__tag_data_access__DOT____Vcellinp__s0_1_c0__in[2U]; + vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__tag_data_access__DOT__s0_1_c0__DOT__value[3U] + = vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__tag_data_access__DOT____Vcellinp__s0_1_c0__in[3U]; + vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__tag_data_access__DOT__s0_1_c0__DOT__value[4U] + = vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__tag_data_access__DOT____Vcellinp__s0_1_c0__in[4U]; + vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__tag_data_access__DOT__s0_1_c0__DOT__value[5U] + = vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__tag_data_access__DOT____Vcellinp__s0_1_c0__in[5U]; + } + } + if (vlTOPp->reset) { + vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__tag_data_access__DOT__s0_1_c0__DOT__value[0U] = 0U; + vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__tag_data_access__DOT__s0_1_c0__DOT__value[1U] = 0U; + vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__tag_data_access__DOT__s0_1_c0__DOT__value[2U] = 0U; + vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__tag_data_access__DOT__s0_1_c0__DOT__value[3U] = 0U; + vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__tag_data_access__DOT__s0_1_c0__DOT__value[4U] = 0U; + vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__tag_data_access__DOT__s0_1_c0__DOT__value[5U] = 0U; + } else { + if ((1U & (~ (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__stall_bank_pipe)))) { + vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__tag_data_access__DOT__s0_1_c0__DOT__value[0U] + = vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__tag_data_access__DOT____Vcellinp__s0_1_c0__in[0U]; + vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__tag_data_access__DOT__s0_1_c0__DOT__value[1U] + = vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__tag_data_access__DOT____Vcellinp__s0_1_c0__in[1U]; + vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__tag_data_access__DOT__s0_1_c0__DOT__value[2U] + = vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__tag_data_access__DOT____Vcellinp__s0_1_c0__in[2U]; + vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__tag_data_access__DOT__s0_1_c0__DOT__value[3U] + = vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__tag_data_access__DOT____Vcellinp__s0_1_c0__in[3U]; + vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__tag_data_access__DOT__s0_1_c0__DOT__value[4U] + = vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__tag_data_access__DOT____Vcellinp__s0_1_c0__in[4U]; + vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__tag_data_access__DOT__s0_1_c0__DOT__value[5U] + = vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__tag_data_access__DOT____Vcellinp__s0_1_c0__in[5U]; + } + } + if (vlTOPp->reset) { + vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__tag_data_access__DOT__s0_1_c0__DOT__value[0U] = 0U; + vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__tag_data_access__DOT__s0_1_c0__DOT__value[1U] = 0U; + vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__tag_data_access__DOT__s0_1_c0__DOT__value[2U] = 0U; + vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__tag_data_access__DOT__s0_1_c0__DOT__value[3U] = 0U; + vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__tag_data_access__DOT__s0_1_c0__DOT__value[4U] = 0U; + vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__tag_data_access__DOT__s0_1_c0__DOT__value[5U] = 0U; + } else { + if ((1U & (~ (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__stall_bank_pipe)))) { + vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__tag_data_access__DOT__s0_1_c0__DOT__value[0U] + = vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__tag_data_access__DOT____Vcellinp__s0_1_c0__in[0U]; + vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__tag_data_access__DOT__s0_1_c0__DOT__value[1U] + = vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__tag_data_access__DOT____Vcellinp__s0_1_c0__in[1U]; + vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__tag_data_access__DOT__s0_1_c0__DOT__value[2U] + = vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__tag_data_access__DOT____Vcellinp__s0_1_c0__in[2U]; + vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__tag_data_access__DOT__s0_1_c0__DOT__value[3U] + = vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__tag_data_access__DOT____Vcellinp__s0_1_c0__in[3U]; + vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__tag_data_access__DOT__s0_1_c0__DOT__value[4U] + = vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__tag_data_access__DOT____Vcellinp__s0_1_c0__in[4U]; + vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__tag_data_access__DOT__s0_1_c0__DOT__value[5U] + = vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__tag_data_access__DOT____Vcellinp__s0_1_c0__in[5U]; + } + } + if (vlTOPp->reset) { + vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__tag_data_access__DOT__s0_1_c0__DOT__value[0U] = 0U; + vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__tag_data_access__DOT__s0_1_c0__DOT__value[1U] = 0U; + vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__tag_data_access__DOT__s0_1_c0__DOT__value[2U] = 0U; + vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__tag_data_access__DOT__s0_1_c0__DOT__value[3U] = 0U; + vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__tag_data_access__DOT__s0_1_c0__DOT__value[4U] = 0U; + vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__tag_data_access__DOT__s0_1_c0__DOT__value[5U] = 0U; + } else { + if ((1U & (~ (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__stall_bank_pipe)))) { + vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__tag_data_access__DOT__s0_1_c0__DOT__value[0U] + = vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__tag_data_access__DOT____Vcellinp__s0_1_c0__in[0U]; + vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__tag_data_access__DOT__s0_1_c0__DOT__value[1U] + = vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__tag_data_access__DOT____Vcellinp__s0_1_c0__in[1U]; + vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__tag_data_access__DOT__s0_1_c0__DOT__value[2U] + = vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__tag_data_access__DOT____Vcellinp__s0_1_c0__in[2U]; + vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__tag_data_access__DOT__s0_1_c0__DOT__value[3U] + = vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__tag_data_access__DOT____Vcellinp__s0_1_c0__in[3U]; + vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__tag_data_access__DOT__s0_1_c0__DOT__value[4U] + = vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__tag_data_access__DOT____Vcellinp__s0_1_c0__in[4U]; + vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__tag_data_access__DOT__s0_1_c0__DOT__value[5U] + = vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__tag_data_access__DOT____Vcellinp__s0_1_c0__in[5U]; + } + } + if (vlTOPp->reset) { + __Vdly__VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__dwbq_dual_valid_sel = 0U; + } else { + if ((((vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT____Vcellout__dwb_queue__data_out[6U] + >> 7U) & (vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT____Vcellout__dwb_queue__data_out[6U] + >> 6U)) & ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__dram_wb_req_fire) + | (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__snp_rsp_fire)))) { + __Vdly__VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__dwbq_dual_valid_sel + = (1U & (~ (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__dwbq_dual_valid_sel))); + } + } + if (vlTOPp->reset) { + __Vdly__VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__dwbq_dual_valid_sel = 0U; + } else { + if ((((vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT____Vcellout__dwb_queue__data_out[6U] + >> 7U) & (vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT____Vcellout__dwb_queue__data_out[6U] + >> 6U)) & ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__dram_wb_req_fire) + | (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__snp_rsp_fire)))) { + __Vdly__VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__dwbq_dual_valid_sel + = (1U & (~ (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__dwbq_dual_valid_sel))); + } + } + if (vlTOPp->reset) { + __Vdly__VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__dwbq_dual_valid_sel = 0U; + } else { + if ((((vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT____Vcellout__dwb_queue__data_out[6U] + >> 7U) & (vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT____Vcellout__dwb_queue__data_out[6U] + >> 6U)) & ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__dram_wb_req_fire) + | (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__snp_rsp_fire)))) { + __Vdly__VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__dwbq_dual_valid_sel + = (1U & (~ (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__dwbq_dual_valid_sel))); + } + } + if (vlTOPp->reset) { + __Vdly__VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__dwbq_dual_valid_sel = 0U; + } else { + if ((((vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT____Vcellout__dwb_queue__data_out[6U] + >> 7U) & (vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT____Vcellout__dwb_queue__data_out[6U] + >> 6U)) & ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__dram_wb_req_fire) + | (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__snp_rsp_fire)))) { + __Vdly__VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__dwbq_dual_valid_sel + = (1U & (~ (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__dwbq_dual_valid_sel))); + } + } + if (vlTOPp->reset) { + __Vdly__VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__dwb_queue__DOT__size_r = 0U; + vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__genblk2__DOT__head_r[0U] = 0U; + vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__genblk2__DOT__head_r[1U] = 0U; + vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__genblk2__DOT__head_r[2U] = 0U; + vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__genblk2__DOT__head_r[3U] = 0U; + vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__genblk2__DOT__head_r[4U] = 0U; + vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__genblk2__DOT__head_r[5U] = 0U; + vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__genblk2__DOT__head_r[6U] = 0U; + vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__genblk2__DOT__curr_r[0U] = 0U; + vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__genblk2__DOT__curr_r[1U] = 0U; + vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__genblk2__DOT__curr_r[2U] = 0U; + vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__genblk2__DOT__curr_r[3U] = 0U; + vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__genblk2__DOT__curr_r[4U] = 0U; + vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__genblk2__DOT__curr_r[5U] = 0U; + vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__genblk2__DOT__curr_r[6U] = 0U; + __Vdly__VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__genblk2__DOT__wr_ptr_r = 0U; + __Vdly__VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__genblk2__DOT__rd_ptr_r = 0U; + __Vdly__VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__genblk2__DOT__rd_ptr_next_r = 1U; + __Vdly__VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__genblk2__DOT__empty_r = 1U; + vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__genblk2__DOT__full_r = 0U; + } else { + if (vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__dwb_queue__DOT__writing) { + __Vdlyvval__VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__data__v0[0U] + = vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT____Vcellinp__dwb_queue__data_in[0U]; + __Vdlyvval__VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__data__v0[1U] + = vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT____Vcellinp__dwb_queue__data_in[1U]; + __Vdlyvval__VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__data__v0[2U] + = vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT____Vcellinp__dwb_queue__data_in[2U]; + __Vdlyvval__VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__data__v0[3U] + = vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT____Vcellinp__dwb_queue__data_in[3U]; + __Vdlyvval__VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__data__v0[4U] + = vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT____Vcellinp__dwb_queue__data_in[4U]; + __Vdlyvval__VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__data__v0[5U] + = vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT____Vcellinp__dwb_queue__data_in[5U]; + __Vdlyvval__VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__data__v0[6U] + = vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT____Vcellinp__dwb_queue__data_in[6U]; + __Vdlyvset__VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__data__v0 = 1U; + __Vdlyvdim0__VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__data__v0 + = vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__genblk2__DOT__wr_ptr_r; + if ((1U & (~ (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__dwb_queue__DOT__reading)))) { + __Vdly__VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__genblk2__DOT__empty_r = 0U; + if ((3U == (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__dwb_queue__DOT__size_r))) { + vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__genblk2__DOT__full_r = 1U; + } + __Vdly__VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__dwb_queue__DOT__size_r + = (7U & ((IData)(1U) + (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__dwb_queue__DOT__size_r))); + } + __Vdly__VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__genblk2__DOT__wr_ptr_r + = (3U & ((IData)(1U) + (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__genblk2__DOT__wr_ptr_r))); + } + vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__genblk2__DOT__curr_r[0U] + = vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT____Vcellinp__dwb_queue__data_in[0U]; + vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__genblk2__DOT__curr_r[1U] + = vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT____Vcellinp__dwb_queue__data_in[1U]; + vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__genblk2__DOT__curr_r[2U] + = vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT____Vcellinp__dwb_queue__data_in[2U]; + vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__genblk2__DOT__curr_r[3U] + = vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT____Vcellinp__dwb_queue__data_in[3U]; + vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__genblk2__DOT__curr_r[4U] + = vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT____Vcellinp__dwb_queue__data_in[4U]; + vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__genblk2__DOT__curr_r[5U] + = vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT____Vcellinp__dwb_queue__data_in[5U]; + vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__genblk2__DOT__curr_r[6U] + = vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT____Vcellinp__dwb_queue__data_in[6U]; + if (vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__dwb_queue__DOT__reading) { + __Vdly__VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__genblk2__DOT__rd_ptr_r + = vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__genblk2__DOT__rd_ptr_next_r; + if ((1U & (~ (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__dwb_queue__DOT__writing)))) { + if ((1U == (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__dwb_queue__DOT__size_r))) { + if (Verilated::assertOn()) { + if (VL_UNLIKELY(((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__genblk2__DOT__rd_ptr_next_r) + != (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__genblk2__DOT__wr_ptr_r)))) { + VL_WRITEF("[%0t] %%Error: VX_generic_queue.v:144: Assertion failed in %NVX_cache.genblk5[3].bank.dwb_queue.genblk3.genblk2: 'assert' failed.\n", + 64,VL_TIME_Q(), + vlSymsp->name()); + VL_STOP_MT("../../rtl/libs/VX_generic_queue.v", 144, ""); + } + } + __Vdly__VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__genblk2__DOT__empty_r = 1U; + } + vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__genblk2__DOT__full_r = 0U; + __Vdly__VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__dwb_queue__DOT__size_r + = (7U & ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__dwb_queue__DOT__size_r) + - (IData)(1U))); + } + __Vdly__VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__genblk2__DOT__rd_ptr_next_r + = (3U & ((IData)(2U) + (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__genblk2__DOT__rd_ptr_r))); + } + vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__genblk2__DOT__bypass_r + = ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__dwb_queue__DOT__writing) + & ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__genblk2__DOT__empty_r) + | ((1U == (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__dwb_queue__DOT__size_r)) + & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__dwb_queue__DOT__reading)))); + vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__genblk2__DOT__head_r[0U] + = vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__data + [((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__dwb_queue__DOT__reading) + ? (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__genblk2__DOT__rd_ptr_next_r) + : (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__genblk2__DOT__rd_ptr_r))][0U]; + vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__genblk2__DOT__head_r[1U] + = vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__data + [((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__dwb_queue__DOT__reading) + ? (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__genblk2__DOT__rd_ptr_next_r) + : (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__genblk2__DOT__rd_ptr_r))][1U]; + vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__genblk2__DOT__head_r[2U] + = vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__data + [((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__dwb_queue__DOT__reading) + ? (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__genblk2__DOT__rd_ptr_next_r) + : (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__genblk2__DOT__rd_ptr_r))][2U]; + vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__genblk2__DOT__head_r[3U] + = vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__data + [((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__dwb_queue__DOT__reading) + ? (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__genblk2__DOT__rd_ptr_next_r) + : (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__genblk2__DOT__rd_ptr_r))][3U]; + vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__genblk2__DOT__head_r[4U] + = vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__data + [((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__dwb_queue__DOT__reading) + ? (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__genblk2__DOT__rd_ptr_next_r) + : (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__genblk2__DOT__rd_ptr_r))][4U]; + vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__genblk2__DOT__head_r[5U] + = vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__data + [((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__dwb_queue__DOT__reading) + ? (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__genblk2__DOT__rd_ptr_next_r) + : (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__genblk2__DOT__rd_ptr_r))][5U]; + vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__genblk2__DOT__head_r[6U] + = vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__data + [((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__dwb_queue__DOT__reading) + ? (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__genblk2__DOT__rd_ptr_next_r) + : (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__genblk2__DOT__rd_ptr_r))][6U]; + } + if (vlTOPp->reset) { + __Vdly__VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__dwb_queue__DOT__size_r = 0U; + vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__genblk2__DOT__head_r[0U] = 0U; + vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__genblk2__DOT__head_r[1U] = 0U; + vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__genblk2__DOT__head_r[2U] = 0U; + vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__genblk2__DOT__head_r[3U] = 0U; + vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__genblk2__DOT__head_r[4U] = 0U; + vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__genblk2__DOT__head_r[5U] = 0U; + vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__genblk2__DOT__head_r[6U] = 0U; + vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__genblk2__DOT__curr_r[0U] = 0U; + vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__genblk2__DOT__curr_r[1U] = 0U; + vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__genblk2__DOT__curr_r[2U] = 0U; + vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__genblk2__DOT__curr_r[3U] = 0U; + vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__genblk2__DOT__curr_r[4U] = 0U; + vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__genblk2__DOT__curr_r[5U] = 0U; + vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__genblk2__DOT__curr_r[6U] = 0U; + __Vdly__VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__genblk2__DOT__wr_ptr_r = 0U; + __Vdly__VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__genblk2__DOT__rd_ptr_r = 0U; + __Vdly__VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__genblk2__DOT__rd_ptr_next_r = 1U; + __Vdly__VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__genblk2__DOT__empty_r = 1U; + vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__genblk2__DOT__full_r = 0U; + } else { + if (vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__dwb_queue__DOT__writing) { + __Vdlyvval__VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__data__v0[0U] + = vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT____Vcellinp__dwb_queue__data_in[0U]; + __Vdlyvval__VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__data__v0[1U] + = vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT____Vcellinp__dwb_queue__data_in[1U]; + __Vdlyvval__VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__data__v0[2U] + = vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT____Vcellinp__dwb_queue__data_in[2U]; + __Vdlyvval__VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__data__v0[3U] + = vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT____Vcellinp__dwb_queue__data_in[3U]; + __Vdlyvval__VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__data__v0[4U] + = vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT____Vcellinp__dwb_queue__data_in[4U]; + __Vdlyvval__VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__data__v0[5U] + = vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT____Vcellinp__dwb_queue__data_in[5U]; + __Vdlyvval__VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__data__v0[6U] + = vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT____Vcellinp__dwb_queue__data_in[6U]; + __Vdlyvset__VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__data__v0 = 1U; + __Vdlyvdim0__VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__data__v0 + = vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__genblk2__DOT__wr_ptr_r; + if ((1U & (~ (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__dwb_queue__DOT__reading)))) { + __Vdly__VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__genblk2__DOT__empty_r = 0U; + if ((3U == (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__dwb_queue__DOT__size_r))) { + vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__genblk2__DOT__full_r = 1U; + } + __Vdly__VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__dwb_queue__DOT__size_r + = (7U & ((IData)(1U) + (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__dwb_queue__DOT__size_r))); + } + __Vdly__VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__genblk2__DOT__wr_ptr_r + = (3U & ((IData)(1U) + (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__genblk2__DOT__wr_ptr_r))); + } + vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__genblk2__DOT__curr_r[0U] + = vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT____Vcellinp__dwb_queue__data_in[0U]; + vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__genblk2__DOT__curr_r[1U] + = vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT____Vcellinp__dwb_queue__data_in[1U]; + vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__genblk2__DOT__curr_r[2U] + = vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT____Vcellinp__dwb_queue__data_in[2U]; + vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__genblk2__DOT__curr_r[3U] + = vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT____Vcellinp__dwb_queue__data_in[3U]; + vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__genblk2__DOT__curr_r[4U] + = vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT____Vcellinp__dwb_queue__data_in[4U]; + vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__genblk2__DOT__curr_r[5U] + = vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT____Vcellinp__dwb_queue__data_in[5U]; + vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__genblk2__DOT__curr_r[6U] + = vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT____Vcellinp__dwb_queue__data_in[6U]; + if (vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__dwb_queue__DOT__reading) { + __Vdly__VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__genblk2__DOT__rd_ptr_r + = vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__genblk2__DOT__rd_ptr_next_r; + if ((1U & (~ (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__dwb_queue__DOT__writing)))) { + if ((1U == (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__dwb_queue__DOT__size_r))) { + if (Verilated::assertOn()) { + if (VL_UNLIKELY(((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__genblk2__DOT__rd_ptr_next_r) + != (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__genblk2__DOT__wr_ptr_r)))) { + VL_WRITEF("[%0t] %%Error: VX_generic_queue.v:144: Assertion failed in %NVX_cache.genblk5[2].bank.dwb_queue.genblk3.genblk2: 'assert' failed.\n", + 64,VL_TIME_Q(), + vlSymsp->name()); + VL_STOP_MT("../../rtl/libs/VX_generic_queue.v", 144, ""); + } + } + __Vdly__VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__genblk2__DOT__empty_r = 1U; + } + vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__genblk2__DOT__full_r = 0U; + __Vdly__VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__dwb_queue__DOT__size_r + = (7U & ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__dwb_queue__DOT__size_r) + - (IData)(1U))); + } + __Vdly__VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__genblk2__DOT__rd_ptr_next_r + = (3U & ((IData)(2U) + (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__genblk2__DOT__rd_ptr_r))); + } + vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__genblk2__DOT__bypass_r + = ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__dwb_queue__DOT__writing) + & ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__genblk2__DOT__empty_r) + | ((1U == (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__dwb_queue__DOT__size_r)) + & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__dwb_queue__DOT__reading)))); + vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__genblk2__DOT__head_r[0U] + = vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__data + [((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__dwb_queue__DOT__reading) + ? (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__genblk2__DOT__rd_ptr_next_r) + : (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__genblk2__DOT__rd_ptr_r))][0U]; + vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__genblk2__DOT__head_r[1U] + = vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__data + [((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__dwb_queue__DOT__reading) + ? (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__genblk2__DOT__rd_ptr_next_r) + : (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__genblk2__DOT__rd_ptr_r))][1U]; + vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__genblk2__DOT__head_r[2U] + = vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__data + [((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__dwb_queue__DOT__reading) + ? (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__genblk2__DOT__rd_ptr_next_r) + : (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__genblk2__DOT__rd_ptr_r))][2U]; + vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__genblk2__DOT__head_r[3U] + = vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__data + [((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__dwb_queue__DOT__reading) + ? (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__genblk2__DOT__rd_ptr_next_r) + : (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__genblk2__DOT__rd_ptr_r))][3U]; + vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__genblk2__DOT__head_r[4U] + = vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__data + [((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__dwb_queue__DOT__reading) + ? (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__genblk2__DOT__rd_ptr_next_r) + : (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__genblk2__DOT__rd_ptr_r))][4U]; + vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__genblk2__DOT__head_r[5U] + = vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__data + [((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__dwb_queue__DOT__reading) + ? (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__genblk2__DOT__rd_ptr_next_r) + : (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__genblk2__DOT__rd_ptr_r))][5U]; + vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__genblk2__DOT__head_r[6U] + = vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__data + [((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__dwb_queue__DOT__reading) + ? (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__genblk2__DOT__rd_ptr_next_r) + : (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__genblk2__DOT__rd_ptr_r))][6U]; + } + if (vlTOPp->reset) { + __Vdly__VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__dwb_queue__DOT__size_r = 0U; + vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__genblk2__DOT__head_r[0U] = 0U; + vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__genblk2__DOT__head_r[1U] = 0U; + vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__genblk2__DOT__head_r[2U] = 0U; + vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__genblk2__DOT__head_r[3U] = 0U; + vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__genblk2__DOT__head_r[4U] = 0U; + vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__genblk2__DOT__head_r[5U] = 0U; + vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__genblk2__DOT__head_r[6U] = 0U; + vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__genblk2__DOT__curr_r[0U] = 0U; + vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__genblk2__DOT__curr_r[1U] = 0U; + vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__genblk2__DOT__curr_r[2U] = 0U; + vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__genblk2__DOT__curr_r[3U] = 0U; + vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__genblk2__DOT__curr_r[4U] = 0U; + vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__genblk2__DOT__curr_r[5U] = 0U; + vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__genblk2__DOT__curr_r[6U] = 0U; + __Vdly__VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__genblk2__DOT__wr_ptr_r = 0U; + __Vdly__VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__genblk2__DOT__rd_ptr_r = 0U; + __Vdly__VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__genblk2__DOT__rd_ptr_next_r = 1U; + __Vdly__VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__genblk2__DOT__empty_r = 1U; + vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__genblk2__DOT__full_r = 0U; + } else { + if (vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__dwb_queue__DOT__writing) { + __Vdlyvval__VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__data__v0[0U] + = vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT____Vcellinp__dwb_queue__data_in[0U]; + __Vdlyvval__VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__data__v0[1U] + = vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT____Vcellinp__dwb_queue__data_in[1U]; + __Vdlyvval__VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__data__v0[2U] + = vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT____Vcellinp__dwb_queue__data_in[2U]; + __Vdlyvval__VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__data__v0[3U] + = vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT____Vcellinp__dwb_queue__data_in[3U]; + __Vdlyvval__VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__data__v0[4U] + = vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT____Vcellinp__dwb_queue__data_in[4U]; + __Vdlyvval__VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__data__v0[5U] + = vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT____Vcellinp__dwb_queue__data_in[5U]; + __Vdlyvval__VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__data__v0[6U] + = vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT____Vcellinp__dwb_queue__data_in[6U]; + __Vdlyvset__VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__data__v0 = 1U; + __Vdlyvdim0__VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__data__v0 + = vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__genblk2__DOT__wr_ptr_r; + if ((1U & (~ (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__dwb_queue__DOT__reading)))) { + __Vdly__VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__genblk2__DOT__empty_r = 0U; + if ((3U == (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__dwb_queue__DOT__size_r))) { + vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__genblk2__DOT__full_r = 1U; + } + __Vdly__VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__dwb_queue__DOT__size_r + = (7U & ((IData)(1U) + (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__dwb_queue__DOT__size_r))); + } + __Vdly__VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__genblk2__DOT__wr_ptr_r + = (3U & ((IData)(1U) + (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__genblk2__DOT__wr_ptr_r))); + } + vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__genblk2__DOT__curr_r[0U] + = vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT____Vcellinp__dwb_queue__data_in[0U]; + vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__genblk2__DOT__curr_r[1U] + = vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT____Vcellinp__dwb_queue__data_in[1U]; + vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__genblk2__DOT__curr_r[2U] + = vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT____Vcellinp__dwb_queue__data_in[2U]; + vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__genblk2__DOT__curr_r[3U] + = vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT____Vcellinp__dwb_queue__data_in[3U]; + vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__genblk2__DOT__curr_r[4U] + = vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT____Vcellinp__dwb_queue__data_in[4U]; + vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__genblk2__DOT__curr_r[5U] + = vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT____Vcellinp__dwb_queue__data_in[5U]; + vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__genblk2__DOT__curr_r[6U] + = vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT____Vcellinp__dwb_queue__data_in[6U]; + if (vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__dwb_queue__DOT__reading) { + __Vdly__VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__genblk2__DOT__rd_ptr_r + = vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__genblk2__DOT__rd_ptr_next_r; + if ((1U & (~ (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__dwb_queue__DOT__writing)))) { + if ((1U == (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__dwb_queue__DOT__size_r))) { + if (Verilated::assertOn()) { + if (VL_UNLIKELY(((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__genblk2__DOT__rd_ptr_next_r) + != (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__genblk2__DOT__wr_ptr_r)))) { + VL_WRITEF("[%0t] %%Error: VX_generic_queue.v:144: Assertion failed in %NVX_cache.genblk5[1].bank.dwb_queue.genblk3.genblk2: 'assert' failed.\n", + 64,VL_TIME_Q(), + vlSymsp->name()); + VL_STOP_MT("../../rtl/libs/VX_generic_queue.v", 144, ""); + } + } + __Vdly__VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__genblk2__DOT__empty_r = 1U; + } + vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__genblk2__DOT__full_r = 0U; + __Vdly__VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__dwb_queue__DOT__size_r + = (7U & ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__dwb_queue__DOT__size_r) + - (IData)(1U))); + } + __Vdly__VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__genblk2__DOT__rd_ptr_next_r + = (3U & ((IData)(2U) + (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__genblk2__DOT__rd_ptr_r))); + } + vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__genblk2__DOT__bypass_r + = ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__dwb_queue__DOT__writing) + & ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__genblk2__DOT__empty_r) + | ((1U == (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__dwb_queue__DOT__size_r)) + & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__dwb_queue__DOT__reading)))); + vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__genblk2__DOT__head_r[0U] + = vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__data + [((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__dwb_queue__DOT__reading) + ? (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__genblk2__DOT__rd_ptr_next_r) + : (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__genblk2__DOT__rd_ptr_r))][0U]; + vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__genblk2__DOT__head_r[1U] + = vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__data + [((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__dwb_queue__DOT__reading) + ? (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__genblk2__DOT__rd_ptr_next_r) + : (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__genblk2__DOT__rd_ptr_r))][1U]; + vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__genblk2__DOT__head_r[2U] + = vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__data + [((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__dwb_queue__DOT__reading) + ? (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__genblk2__DOT__rd_ptr_next_r) + : (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__genblk2__DOT__rd_ptr_r))][2U]; + vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__genblk2__DOT__head_r[3U] + = vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__data + [((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__dwb_queue__DOT__reading) + ? (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__genblk2__DOT__rd_ptr_next_r) + : (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__genblk2__DOT__rd_ptr_r))][3U]; + vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__genblk2__DOT__head_r[4U] + = vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__data + [((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__dwb_queue__DOT__reading) + ? (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__genblk2__DOT__rd_ptr_next_r) + : (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__genblk2__DOT__rd_ptr_r))][4U]; + vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__genblk2__DOT__head_r[5U] + = vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__data + [((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__dwb_queue__DOT__reading) + ? (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__genblk2__DOT__rd_ptr_next_r) + : (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__genblk2__DOT__rd_ptr_r))][5U]; + vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__genblk2__DOT__head_r[6U] + = vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__data + [((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__dwb_queue__DOT__reading) + ? (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__genblk2__DOT__rd_ptr_next_r) + : (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__genblk2__DOT__rd_ptr_r))][6U]; + } + if (vlTOPp->reset) { + __Vdly__VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__dwb_queue__DOT__size_r = 0U; + vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__genblk2__DOT__head_r[0U] = 0U; + vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__genblk2__DOT__head_r[1U] = 0U; + vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__genblk2__DOT__head_r[2U] = 0U; + vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__genblk2__DOT__head_r[3U] = 0U; + vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__genblk2__DOT__head_r[4U] = 0U; + vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__genblk2__DOT__head_r[5U] = 0U; + vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__genblk2__DOT__head_r[6U] = 0U; + vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__genblk2__DOT__curr_r[0U] = 0U; + vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__genblk2__DOT__curr_r[1U] = 0U; + vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__genblk2__DOT__curr_r[2U] = 0U; + vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__genblk2__DOT__curr_r[3U] = 0U; + vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__genblk2__DOT__curr_r[4U] = 0U; + vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__genblk2__DOT__curr_r[5U] = 0U; + vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__genblk2__DOT__curr_r[6U] = 0U; + __Vdly__VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__genblk2__DOT__wr_ptr_r = 0U; + __Vdly__VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__genblk2__DOT__rd_ptr_r = 0U; + __Vdly__VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__genblk2__DOT__rd_ptr_next_r = 1U; + __Vdly__VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__genblk2__DOT__empty_r = 1U; + vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__genblk2__DOT__full_r = 0U; + } else { + if (vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__dwb_queue__DOT__writing) { + __Vdlyvval__VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__data__v0[0U] + = vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT____Vcellinp__dwb_queue__data_in[0U]; + __Vdlyvval__VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__data__v0[1U] + = vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT____Vcellinp__dwb_queue__data_in[1U]; + __Vdlyvval__VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__data__v0[2U] + = vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT____Vcellinp__dwb_queue__data_in[2U]; + __Vdlyvval__VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__data__v0[3U] + = vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT____Vcellinp__dwb_queue__data_in[3U]; + __Vdlyvval__VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__data__v0[4U] + = vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT____Vcellinp__dwb_queue__data_in[4U]; + __Vdlyvval__VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__data__v0[5U] + = vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT____Vcellinp__dwb_queue__data_in[5U]; + __Vdlyvval__VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__data__v0[6U] + = vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT____Vcellinp__dwb_queue__data_in[6U]; + __Vdlyvset__VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__data__v0 = 1U; + __Vdlyvdim0__VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__data__v0 + = vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__genblk2__DOT__wr_ptr_r; + if ((1U & (~ (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__dwb_queue__DOT__reading)))) { + __Vdly__VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__genblk2__DOT__empty_r = 0U; + if ((3U == (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__dwb_queue__DOT__size_r))) { + vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__genblk2__DOT__full_r = 1U; + } + __Vdly__VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__dwb_queue__DOT__size_r + = (7U & ((IData)(1U) + (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__dwb_queue__DOT__size_r))); + } + __Vdly__VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__genblk2__DOT__wr_ptr_r + = (3U & ((IData)(1U) + (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__genblk2__DOT__wr_ptr_r))); + } + vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__genblk2__DOT__curr_r[0U] + = vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT____Vcellinp__dwb_queue__data_in[0U]; + vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__genblk2__DOT__curr_r[1U] + = vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT____Vcellinp__dwb_queue__data_in[1U]; + vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__genblk2__DOT__curr_r[2U] + = vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT____Vcellinp__dwb_queue__data_in[2U]; + vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__genblk2__DOT__curr_r[3U] + = vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT____Vcellinp__dwb_queue__data_in[3U]; + vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__genblk2__DOT__curr_r[4U] + = vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT____Vcellinp__dwb_queue__data_in[4U]; + vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__genblk2__DOT__curr_r[5U] + = vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT____Vcellinp__dwb_queue__data_in[5U]; + vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__genblk2__DOT__curr_r[6U] + = vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT____Vcellinp__dwb_queue__data_in[6U]; + if (vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__dwb_queue__DOT__reading) { + __Vdly__VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__genblk2__DOT__rd_ptr_r + = vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__genblk2__DOT__rd_ptr_next_r; + if ((1U & (~ (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__dwb_queue__DOT__writing)))) { + if ((1U == (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__dwb_queue__DOT__size_r))) { + if (Verilated::assertOn()) { + if (VL_UNLIKELY(((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__genblk2__DOT__rd_ptr_next_r) + != (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__genblk2__DOT__wr_ptr_r)))) { + VL_WRITEF("[%0t] %%Error: VX_generic_queue.v:144: Assertion failed in %NVX_cache.genblk5[0].bank.dwb_queue.genblk3.genblk2: 'assert' failed.\n", + 64,VL_TIME_Q(), + vlSymsp->name()); + VL_STOP_MT("../../rtl/libs/VX_generic_queue.v", 144, ""); + } + } + __Vdly__VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__genblk2__DOT__empty_r = 1U; + } + vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__genblk2__DOT__full_r = 0U; + __Vdly__VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__dwb_queue__DOT__size_r + = (7U & ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__dwb_queue__DOT__size_r) + - (IData)(1U))); + } + __Vdly__VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__genblk2__DOT__rd_ptr_next_r + = (3U & ((IData)(2U) + (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__genblk2__DOT__rd_ptr_r))); + } + vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__genblk2__DOT__bypass_r + = ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__dwb_queue__DOT__writing) + & ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__genblk2__DOT__empty_r) + | ((1U == (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__dwb_queue__DOT__size_r)) + & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__dwb_queue__DOT__reading)))); + vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__genblk2__DOT__head_r[0U] + = vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__data + [((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__dwb_queue__DOT__reading) + ? (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__genblk2__DOT__rd_ptr_next_r) + : (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__genblk2__DOT__rd_ptr_r))][0U]; + vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__genblk2__DOT__head_r[1U] + = vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__data + [((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__dwb_queue__DOT__reading) + ? (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__genblk2__DOT__rd_ptr_next_r) + : (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__genblk2__DOT__rd_ptr_r))][1U]; + vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__genblk2__DOT__head_r[2U] + = vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__data + [((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__dwb_queue__DOT__reading) + ? (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__genblk2__DOT__rd_ptr_next_r) + : (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__genblk2__DOT__rd_ptr_r))][2U]; + vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__genblk2__DOT__head_r[3U] + = vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__data + [((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__dwb_queue__DOT__reading) + ? (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__genblk2__DOT__rd_ptr_next_r) + : (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__genblk2__DOT__rd_ptr_r))][3U]; + vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__genblk2__DOT__head_r[4U] + = vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__data + [((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__dwb_queue__DOT__reading) + ? (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__genblk2__DOT__rd_ptr_next_r) + : (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__genblk2__DOT__rd_ptr_r))][4U]; + vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__genblk2__DOT__head_r[5U] + = vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__data + [((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__dwb_queue__DOT__reading) + ? (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__genblk2__DOT__rd_ptr_next_r) + : (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__genblk2__DOT__rd_ptr_r))][5U]; + vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__genblk2__DOT__head_r[6U] + = vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__data + [((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__dwb_queue__DOT__reading) + ? (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__genblk2__DOT__rd_ptr_next_r) + : (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__genblk2__DOT__rd_ptr_r))][6U]; + } + if ((1U & (~ (IData)(vlTOPp->reset)))) { + if (vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cache_miss_resrv__DOT__mrvq_push) { + __Vtemp276[1U] = ((0xffe00000U & ((vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__st_1e_2__DOT__value[8U] + << 0x1eU) + | (0x3fe00000U + & (vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__st_1e_2__DOT__value[7U] + >> 2U)))) + | (IData)(((((QData)((IData)( + (3U + & vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__st_1e_2__DOT__value[0U]))) + << 0x33U) + | ((VL_ULL(0x7fffffffffe00) + & (((QData)((IData)( + vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__st_1e_2__DOT__value[1U])) + << 0x22U) + | (VL_ULL(0xfffffffffffffe00) + & ((QData)((IData)( + vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__st_1e_2__DOT__value[0U])) + << 2U)))) + | (QData)((IData)( + ((0x100U + & (vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__st_1e_2__DOT__value[0U] + << 2U)) + | ((0xf0U + & (vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__st_1e_2__DOT__value[0U] + << 2U)) + | ((0xcU + & ((vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__st_1e_2__DOT__value[9U] + << 0xbU) + | (0x7fcU + & (vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__st_1e_2__DOT__value[8U] + >> 0x15U)))) + | (3U + & (vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__st_1e_2__DOT__value[9U] + >> 0x16U))))))))) + >> 0x20U))); + __Vdlyvval__VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cache_miss_resrv__DOT__metadata_table__v0[0U] + = (IData)((((QData)((IData)((3U & vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__st_1e_2__DOT__value[0U]))) + << 0x33U) | ((VL_ULL(0x7fffffffffe00) + & (((QData)((IData)( + vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__st_1e_2__DOT__value[1U])) + << 0x22U) + | (VL_ULL(0xfffffffffffffe00) + & ((QData)((IData)( + vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__st_1e_2__DOT__value[0U])) + << 2U)))) + | (QData)((IData)( + ((0x100U + & (vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__st_1e_2__DOT__value[0U] + << 2U)) + | ((0xf0U + & (vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__st_1e_2__DOT__value[0U] + << 2U)) + | ((0xcU + & ((vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__st_1e_2__DOT__value[9U] + << 0xbU) + | (0x7fcU + & (vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__st_1e_2__DOT__value[8U] + >> 0x15U)))) + | (3U + & (vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__st_1e_2__DOT__value[9U] + >> 0x16U)))))))))); + __Vdlyvval__VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cache_miss_resrv__DOT__metadata_table__v0[1U] + = __Vtemp276[1U]; + __Vdlyvval__VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cache_miss_resrv__DOT__metadata_table__v0[2U] + = (0x1fffffU & (vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__st_1e_2__DOT__value[8U] + >> 2U)); + __Vdlyvset__VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cache_miss_resrv__DOT__metadata_table__v0 = 1U; + __Vdlyvdim0__VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cache_miss_resrv__DOT__metadata_table__v0 + = vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cache_miss_resrv__DOT__tail_ptr; + } + } + if ((1U & (~ (IData)(vlTOPp->reset)))) { + if (vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__cache_miss_resrv__DOT__mrvq_push) { + __Vtemp277[1U] = ((0xffe00000U & ((vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__st_1e_2__DOT__value[8U] + << 0x1eU) + | (0x3fe00000U + & (vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__st_1e_2__DOT__value[7U] + >> 2U)))) + | (IData)(((((QData)((IData)( + (3U + & vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__st_1e_2__DOT__value[0U]))) + << 0x33U) + | ((VL_ULL(0x7fffffffffe00) + & (((QData)((IData)( + vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__st_1e_2__DOT__value[1U])) + << 0x22U) + | (VL_ULL(0xfffffffffffffe00) + & ((QData)((IData)( + vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__st_1e_2__DOT__value[0U])) + << 2U)))) + | (QData)((IData)( + ((0x100U + & (vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__st_1e_2__DOT__value[0U] + << 2U)) + | ((0xf0U + & (vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__st_1e_2__DOT__value[0U] + << 2U)) + | ((0xcU + & ((vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__st_1e_2__DOT__value[9U] + << 0xbU) + | (0x7fcU + & (vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__st_1e_2__DOT__value[8U] + >> 0x15U)))) + | (3U + & (vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__st_1e_2__DOT__value[9U] + >> 0x16U))))))))) + >> 0x20U))); + __Vdlyvval__VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__cache_miss_resrv__DOT__metadata_table__v0[0U] + = (IData)((((QData)((IData)((3U & vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__st_1e_2__DOT__value[0U]))) + << 0x33U) | ((VL_ULL(0x7fffffffffe00) + & (((QData)((IData)( + vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__st_1e_2__DOT__value[1U])) + << 0x22U) + | (VL_ULL(0xfffffffffffffe00) + & ((QData)((IData)( + vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__st_1e_2__DOT__value[0U])) + << 2U)))) + | (QData)((IData)( + ((0x100U + & (vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__st_1e_2__DOT__value[0U] + << 2U)) + | ((0xf0U + & (vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__st_1e_2__DOT__value[0U] + << 2U)) + | ((0xcU + & ((vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__st_1e_2__DOT__value[9U] + << 0xbU) + | (0x7fcU + & (vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__st_1e_2__DOT__value[8U] + >> 0x15U)))) + | (3U + & (vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__st_1e_2__DOT__value[9U] + >> 0x16U)))))))))); + __Vdlyvval__VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__cache_miss_resrv__DOT__metadata_table__v0[1U] + = __Vtemp277[1U]; + __Vdlyvval__VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__cache_miss_resrv__DOT__metadata_table__v0[2U] + = (0x1fffffU & (vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__st_1e_2__DOT__value[8U] + >> 2U)); + __Vdlyvset__VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__cache_miss_resrv__DOT__metadata_table__v0 = 1U; + __Vdlyvdim0__VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__cache_miss_resrv__DOT__metadata_table__v0 + = vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__cache_miss_resrv__DOT__tail_ptr; + } + } + if ((1U & (~ (IData)(vlTOPp->reset)))) { + if (vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__cache_miss_resrv__DOT__mrvq_push) { + __Vtemp278[1U] = ((0xffe00000U & ((vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__st_1e_2__DOT__value[8U] + << 0x1eU) + | (0x3fe00000U + & (vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__st_1e_2__DOT__value[7U] + >> 2U)))) + | (IData)(((((QData)((IData)( + (3U + & vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__st_1e_2__DOT__value[0U]))) + << 0x33U) + | ((VL_ULL(0x7fffffffffe00) + & (((QData)((IData)( + vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__st_1e_2__DOT__value[1U])) + << 0x22U) + | (VL_ULL(0xfffffffffffffe00) + & ((QData)((IData)( + vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__st_1e_2__DOT__value[0U])) + << 2U)))) + | (QData)((IData)( + ((0x100U + & (vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__st_1e_2__DOT__value[0U] + << 2U)) + | ((0xf0U + & (vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__st_1e_2__DOT__value[0U] + << 2U)) + | ((0xcU + & ((vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__st_1e_2__DOT__value[9U] + << 0xbU) + | (0x7fcU + & (vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__st_1e_2__DOT__value[8U] + >> 0x15U)))) + | (3U + & (vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__st_1e_2__DOT__value[9U] + >> 0x16U))))))))) + >> 0x20U))); + __Vdlyvval__VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__cache_miss_resrv__DOT__metadata_table__v0[0U] + = (IData)((((QData)((IData)((3U & vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__st_1e_2__DOT__value[0U]))) + << 0x33U) | ((VL_ULL(0x7fffffffffe00) + & (((QData)((IData)( + vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__st_1e_2__DOT__value[1U])) + << 0x22U) + | (VL_ULL(0xfffffffffffffe00) + & ((QData)((IData)( + vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__st_1e_2__DOT__value[0U])) + << 2U)))) + | (QData)((IData)( + ((0x100U + & (vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__st_1e_2__DOT__value[0U] + << 2U)) + | ((0xf0U + & (vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__st_1e_2__DOT__value[0U] + << 2U)) + | ((0xcU + & ((vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__st_1e_2__DOT__value[9U] + << 0xbU) + | (0x7fcU + & (vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__st_1e_2__DOT__value[8U] + >> 0x15U)))) + | (3U + & (vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__st_1e_2__DOT__value[9U] + >> 0x16U)))))))))); + __Vdlyvval__VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__cache_miss_resrv__DOT__metadata_table__v0[1U] + = __Vtemp278[1U]; + __Vdlyvval__VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__cache_miss_resrv__DOT__metadata_table__v0[2U] + = (0x1fffffU & (vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__st_1e_2__DOT__value[8U] + >> 2U)); + __Vdlyvset__VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__cache_miss_resrv__DOT__metadata_table__v0 = 1U; + __Vdlyvdim0__VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__cache_miss_resrv__DOT__metadata_table__v0 + = vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__cache_miss_resrv__DOT__tail_ptr; + } + } + if ((1U & (~ (IData)(vlTOPp->reset)))) { + if (vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cache_miss_resrv__DOT__mrvq_push) { + __Vtemp279[1U] = ((0xffe00000U & ((vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__st_1e_2__DOT__value[8U] + << 0x1eU) + | (0x3fe00000U + & (vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__st_1e_2__DOT__value[7U] + >> 2U)))) + | (IData)(((((QData)((IData)( + (3U + & vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__st_1e_2__DOT__value[0U]))) + << 0x33U) + | ((VL_ULL(0x7fffffffffe00) + & (((QData)((IData)( + vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__st_1e_2__DOT__value[1U])) + << 0x22U) + | (VL_ULL(0xfffffffffffffe00) + & ((QData)((IData)( + vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__st_1e_2__DOT__value[0U])) + << 2U)))) + | (QData)((IData)( + ((0x100U + & (vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__st_1e_2__DOT__value[0U] + << 2U)) + | ((0xf0U + & (vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__st_1e_2__DOT__value[0U] + << 2U)) + | ((0xcU + & ((vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__st_1e_2__DOT__value[9U] + << 0xbU) + | (0x7fcU + & (vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__st_1e_2__DOT__value[8U] + >> 0x15U)))) + | (3U + & (vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__st_1e_2__DOT__value[9U] + >> 0x16U))))))))) + >> 0x20U))); + __Vdlyvval__VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cache_miss_resrv__DOT__metadata_table__v0[0U] + = (IData)((((QData)((IData)((3U & vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__st_1e_2__DOT__value[0U]))) + << 0x33U) | ((VL_ULL(0x7fffffffffe00) + & (((QData)((IData)( + vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__st_1e_2__DOT__value[1U])) + << 0x22U) + | (VL_ULL(0xfffffffffffffe00) + & ((QData)((IData)( + vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__st_1e_2__DOT__value[0U])) + << 2U)))) + | (QData)((IData)( + ((0x100U + & (vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__st_1e_2__DOT__value[0U] + << 2U)) + | ((0xf0U + & (vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__st_1e_2__DOT__value[0U] + << 2U)) + | ((0xcU + & ((vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__st_1e_2__DOT__value[9U] + << 0xbU) + | (0x7fcU + & (vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__st_1e_2__DOT__value[8U] + >> 0x15U)))) + | (3U + & (vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__st_1e_2__DOT__value[9U] + >> 0x16U)))))))))); + __Vdlyvval__VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cache_miss_resrv__DOT__metadata_table__v0[1U] + = __Vtemp279[1U]; + __Vdlyvval__VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cache_miss_resrv__DOT__metadata_table__v0[2U] + = (0x1fffffU & (vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__st_1e_2__DOT__value[8U] + >> 2U)); + __Vdlyvset__VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cache_miss_resrv__DOT__metadata_table__v0 = 1U; + __Vdlyvdim0__VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cache_miss_resrv__DOT__metadata_table__v0 + = vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cache_miss_resrv__DOT__tail_ptr; + } + } + if (vlTOPp->reset) { + vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cache_miss_resrv__DOT__valid_table = 0U; + __Vdly__VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cache_miss_resrv__DOT__head_ptr = 0U; + } else { + if (vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cache_miss_resrv__DOT__mrvq_push) { + vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cache_miss_resrv__DOT__valid_table + = ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cache_miss_resrv__DOT__valid_table) + | ((IData)(1U) << (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cache_miss_resrv__DOT__tail_ptr))); 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+ } else { + if (vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__cache_miss_resrv__DOT__increment_head) { + vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__cache_miss_resrv__DOT__valid_table + = ((~ ((IData)(1U) << (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__cache_miss_resrv__DOT__head_ptr))) + & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__cache_miss_resrv__DOT__valid_table)); + __Vdly__VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__cache_miss_resrv__DOT__head_ptr + = (0xfU & ((IData)(1U) + (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__cache_miss_resrv__DOT__head_ptr))); + } + } + } + if (vlTOPp->reset) { + vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__cache_miss_resrv__DOT__valid_table = 0U; + __Vdly__VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__cache_miss_resrv__DOT__head_ptr = 0U; + } else { + if (vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__cache_miss_resrv__DOT__mrvq_push) { + vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__cache_miss_resrv__DOT__valid_table + = ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__cache_miss_resrv__DOT__valid_table) + | ((IData)(1U) << (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__cache_miss_resrv__DOT__tail_ptr))); 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+ } + } + } + if ((1U & (~ (IData)(vlTOPp->reset)))) { + if ((1U & (~ (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__stall_bank_pipe)))) { + if ((0U != (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__tag_data_access__DOT__use_write_enable))) { + __Vdlyvval__VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__tag__v0 + = (0xfffffU & (vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__addr_st1 + [0U] >> 6U)); + __Vdlyvset__VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__tag__v0 = 1U; + __Vdlyvdim0__VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__tag__v0 + = (0x3fU & vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__addr_st1 + [0U]); + } + } + } + if ((1U & (~ (IData)(vlTOPp->reset)))) { + if ((1U & (~ (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__stall_bank_pipe)))) { + if ((0U != (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__tag_data_access__DOT__use_write_enable))) { + __Vdlyvval__VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__tag__v0 + = (0xfffffU & (vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__addr_st1 + [0U] >> 6U)); + __Vdlyvset__VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__tag__v0 = 1U; + __Vdlyvdim0__VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__tag__v0 + = (0x3fU & vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__addr_st1 + [0U]); + } + } + } + if ((1U & (~ (IData)(vlTOPp->reset)))) { + if (vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cache_miss_resrv__DOT__mrvq_push) { + vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cache_miss_resrv__DOT____Vlvbound1 + = (0x3ffffffU & ((vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__st_1e_2__DOT__value[9U] + << 7U) | (vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__st_1e_2__DOT__value[8U] + >> 0x19U))); + if ((0x19fU >= (0x1ffU & ((IData)(0x1aU) + * (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cache_miss_resrv__DOT__tail_ptr))))) { + VL_ASSIGNSEL_WIII(26,(0x1ffU & ((IData)(0x1aU) + * (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cache_miss_resrv__DOT__tail_ptr))), vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cache_miss_resrv__DOT__addr_table, vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cache_miss_resrv__DOT____Vlvbound1); + } + } + } + if ((1U & (~ (IData)(vlTOPp->reset)))) { + if (vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__cache_miss_resrv__DOT__mrvq_push) { + vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__cache_miss_resrv__DOT____Vlvbound1 + = (0x3ffffffU & ((vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__st_1e_2__DOT__value[9U] + << 7U) | (vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__st_1e_2__DOT__value[8U] + >> 0x19U))); + if ((0x19fU >= (0x1ffU & ((IData)(0x1aU) + * (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__cache_miss_resrv__DOT__tail_ptr))))) { + VL_ASSIGNSEL_WIII(26,(0x1ffU & ((IData)(0x1aU) + * (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__cache_miss_resrv__DOT__tail_ptr))), vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__cache_miss_resrv__DOT__addr_table, vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__cache_miss_resrv__DOT____Vlvbound1); + } + } + } + if ((1U & (~ (IData)(vlTOPp->reset)))) { + if (vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__cache_miss_resrv__DOT__mrvq_push) { + vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__cache_miss_resrv__DOT____Vlvbound1 + = (0x3ffffffU & ((vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__st_1e_2__DOT__value[9U] + << 7U) | (vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__st_1e_2__DOT__value[8U] + >> 0x19U))); + if ((0x19fU >= (0x1ffU & ((IData)(0x1aU) + * (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__cache_miss_resrv__DOT__tail_ptr))))) { + VL_ASSIGNSEL_WIII(26,(0x1ffU & ((IData)(0x1aU) + * (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__cache_miss_resrv__DOT__tail_ptr))), vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__cache_miss_resrv__DOT__addr_table, vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__cache_miss_resrv__DOT____Vlvbound1); + } + } + } + if ((1U & (~ (IData)(vlTOPp->reset)))) { + if (vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cache_miss_resrv__DOT__mrvq_push) { + vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cache_miss_resrv__DOT____Vlvbound1 + = (0x3ffffffU & ((vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__st_1e_2__DOT__value[9U] + << 7U) | (vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__st_1e_2__DOT__value[8U] + >> 0x19U))); + if ((0x19fU >= (0x1ffU & ((IData)(0x1aU) + * (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cache_miss_resrv__DOT__tail_ptr))))) { + VL_ASSIGNSEL_WIII(26,(0x1ffU & ((IData)(0x1aU) + * (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cache_miss_resrv__DOT__tail_ptr))), vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cache_miss_resrv__DOT__addr_table, vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cache_miss_resrv__DOT____Vlvbound1); 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+ vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__s0_1_c0__DOT__value[1U] + = vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT____Vcellinp__s0_1_c0__in[1U]; + vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__s0_1_c0__DOT__value[2U] + = vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT____Vcellinp__s0_1_c0__in[2U]; + vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__s0_1_c0__DOT__value[3U] + = vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT____Vcellinp__s0_1_c0__in[3U]; + vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__s0_1_c0__DOT__value[4U] + = vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT____Vcellinp__s0_1_c0__in[4U]; + vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__s0_1_c0__DOT__value[5U] + = vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT____Vcellinp__s0_1_c0__in[5U]; + vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__s0_1_c0__DOT__value[6U] + = vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT____Vcellinp__s0_1_c0__in[6U]; + vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__s0_1_c0__DOT__value[7U] + = vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT____Vcellinp__s0_1_c0__in[7U]; + } + } + if (vlTOPp->reset) { + vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__s0_1_c0__DOT__value[0U] = 0U; + vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__s0_1_c0__DOT__value[1U] = 0U; + vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__s0_1_c0__DOT__value[2U] = 0U; + vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__s0_1_c0__DOT__value[3U] = 0U; + vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__s0_1_c0__DOT__value[4U] = 0U; + vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__s0_1_c0__DOT__value[5U] = 0U; + vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__s0_1_c0__DOT__value[6U] = 0U; + vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__s0_1_c0__DOT__value[7U] = 0U; + } else { + if ((1U & (~ (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__stall_bank_pipe)))) { + vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__s0_1_c0__DOT__value[0U] + = vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT____Vcellinp__s0_1_c0__in[0U]; + vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__s0_1_c0__DOT__value[1U] + = vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT____Vcellinp__s0_1_c0__in[1U]; + vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__s0_1_c0__DOT__value[2U] + = vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT____Vcellinp__s0_1_c0__in[2U]; + vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__s0_1_c0__DOT__value[3U] + = vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT____Vcellinp__s0_1_c0__in[3U]; + vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__s0_1_c0__DOT__value[4U] + = vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT____Vcellinp__s0_1_c0__in[4U]; + vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__s0_1_c0__DOT__value[5U] + = vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT____Vcellinp__s0_1_c0__in[5U]; + vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__s0_1_c0__DOT__value[6U] + = vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT____Vcellinp__s0_1_c0__in[6U]; + vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__s0_1_c0__DOT__value[7U] + = vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT____Vcellinp__s0_1_c0__in[7U]; + } + } + if (vlTOPp->reset) { + vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__s0_1_c0__DOT__value[0U] = 0U; + vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__s0_1_c0__DOT__value[1U] = 0U; + vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__s0_1_c0__DOT__value[2U] = 0U; + vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__s0_1_c0__DOT__value[3U] = 0U; + vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__s0_1_c0__DOT__value[4U] = 0U; + vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__s0_1_c0__DOT__value[5U] = 0U; + vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__s0_1_c0__DOT__value[6U] = 0U; + vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__s0_1_c0__DOT__value[7U] = 0U; + } else { + if ((1U & (~ (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__stall_bank_pipe)))) { + vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__s0_1_c0__DOT__value[0U] + = vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT____Vcellinp__s0_1_c0__in[0U]; + vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__s0_1_c0__DOT__value[1U] + = vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT____Vcellinp__s0_1_c0__in[1U]; + vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__s0_1_c0__DOT__value[2U] + = vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT____Vcellinp__s0_1_c0__in[2U]; + vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__s0_1_c0__DOT__value[3U] + = vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT____Vcellinp__s0_1_c0__in[3U]; + vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__s0_1_c0__DOT__value[4U] + = vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT____Vcellinp__s0_1_c0__in[4U]; + vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__s0_1_c0__DOT__value[5U] + = vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT____Vcellinp__s0_1_c0__in[5U]; + vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__s0_1_c0__DOT__value[6U] + = vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT____Vcellinp__s0_1_c0__in[6U]; + vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__s0_1_c0__DOT__value[7U] + = vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT____Vcellinp__s0_1_c0__in[7U]; + } + } + if (vlTOPp->reset) { + vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__s0_1_c0__DOT__value[0U] = 0U; + vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__s0_1_c0__DOT__value[1U] = 0U; + vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__s0_1_c0__DOT__value[2U] = 0U; + vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__s0_1_c0__DOT__value[3U] = 0U; + vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__s0_1_c0__DOT__value[4U] = 0U; + vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__s0_1_c0__DOT__value[5U] = 0U; + vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__s0_1_c0__DOT__value[6U] = 0U; + vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__s0_1_c0__DOT__value[7U] = 0U; + } else { + if ((1U & (~ (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__stall_bank_pipe)))) { + vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__s0_1_c0__DOT__value[0U] + = vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT____Vcellinp__s0_1_c0__in[0U]; + vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__s0_1_c0__DOT__value[1U] + = vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT____Vcellinp__s0_1_c0__in[1U]; + vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__s0_1_c0__DOT__value[2U] + = vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT____Vcellinp__s0_1_c0__in[2U]; + vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__s0_1_c0__DOT__value[3U] + = vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT____Vcellinp__s0_1_c0__in[3U]; + vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__s0_1_c0__DOT__value[4U] + = vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT____Vcellinp__s0_1_c0__in[4U]; + vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__s0_1_c0__DOT__value[5U] + = vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT____Vcellinp__s0_1_c0__in[5U]; + vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__s0_1_c0__DOT__value[6U] + = vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT____Vcellinp__s0_1_c0__in[6U]; + vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__s0_1_c0__DOT__value[7U] + = vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT____Vcellinp__s0_1_c0__in[7U]; + } + } + if ((1U & (~ (IData)(vlTOPp->reset)))) { + if ((1U & (~ (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__stall_bank_pipe)))) { + if ((0U != (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__tag_data_access__DOT__use_write_enable))) { + __Vdlyvval__VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__dirtyb__v0 + = ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__tag_data_access__DOT__real_writefill) + ? 0U : (vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__dirtyb + [(0x3fU & vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__addr_st1 + [0U])] | (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__tag_data_access__DOT__use_write_enable))); + __Vdlyvset__VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__dirtyb__v0 = 1U; + __Vdlyvdim0__VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__dirtyb__v0 + = (0x3fU & vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__addr_st1 + [0U]); + } else { + if (vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__miss_st1e) { + __Vdlyvset__VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__dirtyb__v1 = 1U; + __Vdlyvdim0__VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__dirtyb__v1 + = (0x3fU & vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__addr_st1 + [0U]); + } + } + } + } + if ((1U & (~ (IData)(vlTOPp->reset)))) { + if ((1U & (~ (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__stall_bank_pipe)))) { + if ((0U != (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__tag_data_access__DOT__use_write_enable))) { + __Vdlyvval__VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__dirtyb__v0 + = ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__tag_data_access__DOT__real_writefill) + ? 0U : (vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__dirtyb + [(0x3fU & vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__addr_st1 + [0U])] | (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__tag_data_access__DOT__use_write_enable))); + __Vdlyvset__VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__dirtyb__v0 = 1U; + __Vdlyvdim0__VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__dirtyb__v0 + = (0x3fU & vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__addr_st1 + [0U]); + } else { + if (vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__miss_st1e) { + __Vdlyvset__VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__dirtyb__v1 = 1U; + __Vdlyvdim0__VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__dirtyb__v1 + = (0x3fU & vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__addr_st1 + [0U]); + } + } + } + } + if ((1U & (~ (IData)(vlTOPp->reset)))) { + if ((1U & (~ (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__stall_bank_pipe)))) { + if ((0U != (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__tag_data_access__DOT__use_write_enable))) { + __Vdlyvval__VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__dirtyb__v0 + = ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__tag_data_access__DOT__real_writefill) + ? 0U : (vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__dirtyb + [(0x3fU & vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__addr_st1 + [0U])] | (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__tag_data_access__DOT__use_write_enable))); + __Vdlyvset__VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__dirtyb__v0 = 1U; + __Vdlyvdim0__VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__dirtyb__v0 + = (0x3fU & vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__addr_st1 + [0U]); + } else { + if (vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__miss_st1e) { + __Vdlyvset__VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__dirtyb__v1 = 1U; + __Vdlyvdim0__VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__dirtyb__v1 + = (0x3fU & vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__addr_st1 + [0U]); + } + } + } + } + if ((1U & (~ (IData)(vlTOPp->reset)))) { + if ((1U & (~ (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__stall_bank_pipe)))) { + if ((0U != (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__tag_data_access__DOT__use_write_enable))) { + __Vdlyvval__VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__dirtyb__v0 + = ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__tag_data_access__DOT__real_writefill) + ? 0U : (vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__dirtyb + [(0x3fU & vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__addr_st1 + [0U])] | (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__tag_data_access__DOT__use_write_enable))); + __Vdlyvset__VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__dirtyb__v0 = 1U; + __Vdlyvdim0__VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__dirtyb__v0 + = (0x3fU & vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__addr_st1 + [0U]); + } else { + if (vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__miss_st1e) { + __Vdlyvset__VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__dirtyb__v1 = 1U; + __Vdlyvdim0__VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__dirtyb__v1 + = (0x3fU & vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__addr_st1 + [0U]); + } + } + } + } + if ((1U & (~ (IData)(vlTOPp->reset)))) { + if ((1U & (~ (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__stall_bank_pipe)))) { + if ((1U & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__tag_data_access__DOT__use_write_enable))) { + __Vdlyvval__VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__data__v0 + = (0xffU & vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__tag_data_access__DOT__data_write[0U]); + __Vdlyvset__VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__data__v0 = 1U; + __Vdlyvlsb__VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__data__v0 = 0U; + __Vdlyvdim0__VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__data__v0 + = (0x3fU & vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__addr_st1 + [0U]); + } + if ((2U & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__tag_data_access__DOT__use_write_enable))) { + __Vdlyvval__VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__data__v1 + = (0xffU & ((vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__tag_data_access__DOT__data_write[1U] + << 0x18U) | (vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__tag_data_access__DOT__data_write[0U] + >> 8U))); + __Vdlyvset__VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__data__v1 = 1U; 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+ } + if ((0x10U & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__tag_data_access__DOT__use_write_enable))) { + __Vdlyvval__VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__data__v4 + = (0xffU & vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__tag_data_access__DOT__data_write[1U]); + __Vdlyvset__VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__data__v4 = 1U; + __Vdlyvlsb__VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__data__v4 = 0x20U; + __Vdlyvdim0__VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__data__v4 + = (0x3fU & vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__addr_st1 + [0U]); + } + if ((0x20U & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__tag_data_access__DOT__use_write_enable))) { + __Vdlyvval__VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__data__v5 + = (0xffU & ((vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__tag_data_access__DOT__data_write[2U] + << 0x18U) | (vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__tag_data_access__DOT__data_write[1U] + >> 8U))); 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+ __Vdlyvdim0__VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__data__v7 + = (0x3fU & vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__addr_st1 + [0U]); + } + if ((0x100U & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__tag_data_access__DOT__use_write_enable))) { + __Vdlyvval__VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__data__v8 + = (0xffU & vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__tag_data_access__DOT__data_write[2U]); + __Vdlyvset__VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__data__v8 = 1U; + __Vdlyvlsb__VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__data__v8 = 0x40U; + __Vdlyvdim0__VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__data__v8 + = (0x3fU & vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__addr_st1 + [0U]); + } + if ((0x200U & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__tag_data_access__DOT__use_write_enable))) { + __Vdlyvval__VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__data__v9 + = (0xffU & ((vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__tag_data_access__DOT__data_write[3U] + << 0x18U) | (vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__tag_data_access__DOT__data_write[2U] + >> 8U))); + __Vdlyvset__VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__data__v9 = 1U; + __Vdlyvlsb__VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__data__v9 = 0x48U; + __Vdlyvdim0__VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__data__v9 + = (0x3fU & vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__addr_st1 + [0U]); + } + if ((0x400U & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__tag_data_access__DOT__use_write_enable))) { + __Vdlyvval__VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__data__v10 + = (0xffU & ((vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__tag_data_access__DOT__data_write[3U] + << 0x10U) | (vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__tag_data_access__DOT__data_write[2U] + >> 0x10U))); + __Vdlyvset__VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__data__v10 = 1U; + __Vdlyvlsb__VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__data__v10 = 0x50U; + __Vdlyvdim0__VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__data__v10 + = (0x3fU & vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__addr_st1 + [0U]); + } + if ((0x800U & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__tag_data_access__DOT__use_write_enable))) { + __Vdlyvval__VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__data__v11 + = (0xffU & ((vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__tag_data_access__DOT__data_write[3U] + << 8U) | (vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__tag_data_access__DOT__data_write[2U] + >> 0x18U))); + __Vdlyvset__VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__data__v11 = 1U; + __Vdlyvlsb__VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__data__v11 = 0x58U; + __Vdlyvdim0__VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__data__v11 + = (0x3fU & vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__addr_st1 + [0U]); + } + if ((0x1000U & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__tag_data_access__DOT__use_write_enable))) { + __Vdlyvval__VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__data__v12 + = (0xffU & vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__tag_data_access__DOT__data_write[3U]); + __Vdlyvset__VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__data__v12 = 1U; + __Vdlyvlsb__VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__data__v12 = 0x60U; + __Vdlyvdim0__VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__data__v12 + = (0x3fU & vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__addr_st1 + [0U]); + } + if ((0x2000U & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__tag_data_access__DOT__use_write_enable))) { + __Vdlyvval__VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__data__v13 + = (0xffU & (vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__tag_data_access__DOT__data_write[3U] + >> 8U)); + __Vdlyvset__VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__data__v13 = 1U; + __Vdlyvlsb__VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__data__v13 = 0x68U; + __Vdlyvdim0__VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__data__v13 + = (0x3fU & vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__addr_st1 + [0U]); + } + if ((0x4000U & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__tag_data_access__DOT__use_write_enable))) { + __Vdlyvval__VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__data__v14 + = (0xffU & (vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__tag_data_access__DOT__data_write[3U] + >> 0x10U)); + __Vdlyvset__VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__data__v14 = 1U; + __Vdlyvlsb__VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__data__v14 = 0x70U; + __Vdlyvdim0__VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__data__v14 + = (0x3fU & vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__addr_st1 + [0U]); + } + if ((0x8000U & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__tag_data_access__DOT__use_write_enable))) { + __Vdlyvval__VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__data__v15 + = (0xffU & (vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__tag_data_access__DOT__data_write[3U] + >> 0x18U)); + __Vdlyvset__VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__data__v15 = 1U; + __Vdlyvlsb__VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__data__v15 = 0x78U; + __Vdlyvdim0__VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__data__v15 + = (0x3fU & vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__addr_st1 + [0U]); + } + } + } + if ((1U & (~ (IData)(vlTOPp->reset)))) { + if ((1U & (~ (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__stall_bank_pipe)))) { + if ((1U & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__tag_data_access__DOT__use_write_enable))) { + __Vdlyvval__VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__data__v0 + = (0xffU & vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__tag_data_access__DOT__data_write[0U]); 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+ } + if ((0x10U & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__tag_data_access__DOT__use_write_enable))) { + __Vdlyvval__VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__data__v4 + = (0xffU & vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__tag_data_access__DOT__data_write[1U]); + __Vdlyvset__VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__data__v4 = 1U; + __Vdlyvlsb__VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__data__v4 = 0x20U; + __Vdlyvdim0__VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__data__v4 + = (0x3fU & vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__addr_st1 + [0U]); + } + if ((0x20U & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__tag_data_access__DOT__use_write_enable))) { + __Vdlyvval__VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__data__v5 + = (0xffU & ((vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__tag_data_access__DOT__data_write[2U] + << 0x18U) | (vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__tag_data_access__DOT__data_write[1U] + >> 8U))); + __Vdlyvset__VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__data__v5 = 1U; + __Vdlyvlsb__VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__data__v5 = 0x28U; + __Vdlyvdim0__VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__data__v5 + = (0x3fU & vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__addr_st1 + [0U]); + } + if ((0x40U & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__tag_data_access__DOT__use_write_enable))) { + __Vdlyvval__VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__data__v6 + = (0xffU & ((vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__tag_data_access__DOT__data_write[2U] + << 0x10U) | (vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__tag_data_access__DOT__data_write[1U] + >> 0x10U))); + __Vdlyvset__VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__data__v6 = 1U; + __Vdlyvlsb__VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__data__v6 = 0x30U; + __Vdlyvdim0__VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__data__v6 + = (0x3fU & vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__addr_st1 + [0U]); + } + if ((0x80U & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__tag_data_access__DOT__use_write_enable))) { + __Vdlyvval__VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__data__v7 + = (0xffU & ((vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__tag_data_access__DOT__data_write[2U] + << 8U) | (vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__tag_data_access__DOT__data_write[1U] + >> 0x18U))); + __Vdlyvset__VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__data__v7 = 1U; + __Vdlyvlsb__VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__data__v7 = 0x38U; + __Vdlyvdim0__VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__data__v7 + = (0x3fU & vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__addr_st1 + [0U]); + } + if ((0x100U & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__tag_data_access__DOT__use_write_enable))) { + __Vdlyvval__VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__data__v8 + = (0xffU & vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__tag_data_access__DOT__data_write[2U]); + __Vdlyvset__VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__data__v8 = 1U; + __Vdlyvlsb__VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__data__v8 = 0x40U; + __Vdlyvdim0__VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__data__v8 + = (0x3fU & vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__addr_st1 + [0U]); + } + if ((0x200U & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__tag_data_access__DOT__use_write_enable))) { + __Vdlyvval__VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__data__v9 + = (0xffU & ((vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__tag_data_access__DOT__data_write[3U] + << 0x18U) | (vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__tag_data_access__DOT__data_write[2U] + >> 8U))); + __Vdlyvset__VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__data__v9 = 1U; + __Vdlyvlsb__VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__data__v9 = 0x48U; + __Vdlyvdim0__VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__data__v9 + = (0x3fU & vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__addr_st1 + [0U]); + } + if ((0x400U & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__tag_data_access__DOT__use_write_enable))) { + __Vdlyvval__VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__data__v10 + = (0xffU & ((vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__tag_data_access__DOT__data_write[3U] + << 0x10U) | (vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__tag_data_access__DOT__data_write[2U] + >> 0x10U))); + __Vdlyvset__VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__data__v10 = 1U; + __Vdlyvlsb__VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__data__v10 = 0x50U; + __Vdlyvdim0__VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__data__v10 + = (0x3fU & vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__addr_st1 + [0U]); + } + if ((0x800U & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__tag_data_access__DOT__use_write_enable))) { + __Vdlyvval__VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__data__v11 + = (0xffU & ((vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__tag_data_access__DOT__data_write[3U] + << 8U) | (vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__tag_data_access__DOT__data_write[2U] + >> 0x18U))); + __Vdlyvset__VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__data__v11 = 1U; + __Vdlyvlsb__VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__data__v11 = 0x58U; + __Vdlyvdim0__VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__data__v11 + = (0x3fU & vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__addr_st1 + [0U]); + } + if ((0x1000U & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__tag_data_access__DOT__use_write_enable))) { + __Vdlyvval__VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__data__v12 + = (0xffU & vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__tag_data_access__DOT__data_write[3U]); + __Vdlyvset__VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__data__v12 = 1U; + __Vdlyvlsb__VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__data__v12 = 0x60U; + __Vdlyvdim0__VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__data__v12 + = (0x3fU & vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__addr_st1 + [0U]); + } + if ((0x2000U & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__tag_data_access__DOT__use_write_enable))) { + __Vdlyvval__VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__data__v13 + = (0xffU & (vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__tag_data_access__DOT__data_write[3U] + >> 8U)); + __Vdlyvset__VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__data__v13 = 1U; + __Vdlyvlsb__VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__data__v13 = 0x68U; + __Vdlyvdim0__VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__data__v13 + = (0x3fU & vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__addr_st1 + [0U]); + } + if ((0x4000U & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__tag_data_access__DOT__use_write_enable))) { + __Vdlyvval__VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__data__v14 + = (0xffU & (vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__tag_data_access__DOT__data_write[3U] + >> 0x10U)); + __Vdlyvset__VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__data__v14 = 1U; + __Vdlyvlsb__VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__data__v14 = 0x70U; + __Vdlyvdim0__VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__data__v14 + = (0x3fU & vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__addr_st1 + [0U]); + } + if ((0x8000U & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__tag_data_access__DOT__use_write_enable))) { + __Vdlyvval__VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__data__v15 + = (0xffU & (vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__tag_data_access__DOT__data_write[3U] + >> 0x18U)); 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+ } + if ((0x10U & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__tag_data_access__DOT__use_write_enable))) { + __Vdlyvval__VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__data__v4 + = (0xffU & vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__tag_data_access__DOT__data_write[1U]); + __Vdlyvset__VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__data__v4 = 1U; + __Vdlyvlsb__VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__data__v4 = 0x20U; + __Vdlyvdim0__VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__data__v4 + = (0x3fU & vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__addr_st1 + [0U]); + } + if ((0x20U & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__tag_data_access__DOT__use_write_enable))) { + __Vdlyvval__VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__data__v5 + = (0xffU & ((vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__tag_data_access__DOT__data_write[2U] + << 0x18U) | (vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__tag_data_access__DOT__data_write[1U] + >> 8U))); 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+ __Vdlyvdim0__VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__data__v7 + = (0x3fU & vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__addr_st1 + [0U]); + } + if ((0x100U & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__tag_data_access__DOT__use_write_enable))) { + __Vdlyvval__VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__data__v8 + = (0xffU & vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__tag_data_access__DOT__data_write[2U]); + __Vdlyvset__VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__data__v8 = 1U; + __Vdlyvlsb__VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__data__v8 = 0x40U; + __Vdlyvdim0__VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__data__v8 + = (0x3fU & vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__addr_st1 + [0U]); + } + if ((0x200U & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__tag_data_access__DOT__use_write_enable))) { + __Vdlyvval__VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__data__v9 + = (0xffU & ((vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__tag_data_access__DOT__data_write[3U] + << 0x18U) | (vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__tag_data_access__DOT__data_write[2U] + >> 8U))); + __Vdlyvset__VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__data__v9 = 1U; + __Vdlyvlsb__VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__data__v9 = 0x48U; + __Vdlyvdim0__VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__data__v9 + = (0x3fU & vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__addr_st1 + [0U]); + } + if ((0x400U & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__tag_data_access__DOT__use_write_enable))) { + __Vdlyvval__VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__data__v10 + = (0xffU & ((vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__tag_data_access__DOT__data_write[3U] + << 0x10U) | (vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__tag_data_access__DOT__data_write[2U] + >> 0x10U))); + __Vdlyvset__VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__data__v10 = 1U; + __Vdlyvlsb__VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__data__v10 = 0x50U; + __Vdlyvdim0__VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__data__v10 + = (0x3fU & vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__addr_st1 + [0U]); + } + if ((0x800U & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__tag_data_access__DOT__use_write_enable))) { + __Vdlyvval__VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__data__v11 + = (0xffU & ((vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__tag_data_access__DOT__data_write[3U] + << 8U) | (vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__tag_data_access__DOT__data_write[2U] + >> 0x18U))); + __Vdlyvset__VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__data__v11 = 1U; + __Vdlyvlsb__VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__data__v11 = 0x58U; + __Vdlyvdim0__VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__data__v11 + = (0x3fU & vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__addr_st1 + [0U]); + } + if ((0x1000U & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__tag_data_access__DOT__use_write_enable))) { + __Vdlyvval__VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__data__v12 + = (0xffU & vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__tag_data_access__DOT__data_write[3U]); + __Vdlyvset__VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__data__v12 = 1U; + __Vdlyvlsb__VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__data__v12 = 0x60U; + __Vdlyvdim0__VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__data__v12 + = (0x3fU & vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__addr_st1 + [0U]); + } + if ((0x2000U & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__tag_data_access__DOT__use_write_enable))) { + __Vdlyvval__VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__data__v13 + = (0xffU & (vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__tag_data_access__DOT__data_write[3U] + >> 8U)); + __Vdlyvset__VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__data__v13 = 1U; + __Vdlyvlsb__VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__data__v13 = 0x68U; + __Vdlyvdim0__VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__data__v13 + = (0x3fU & vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__addr_st1 + [0U]); + } + if ((0x4000U & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__tag_data_access__DOT__use_write_enable))) { + __Vdlyvval__VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__data__v14 + = (0xffU & (vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__tag_data_access__DOT__data_write[3U] + >> 0x10U)); + __Vdlyvset__VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__data__v14 = 1U; + __Vdlyvlsb__VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__data__v14 = 0x70U; + __Vdlyvdim0__VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__data__v14 + = (0x3fU & vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__addr_st1 + [0U]); + } + if ((0x8000U & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__tag_data_access__DOT__use_write_enable))) { + __Vdlyvval__VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__data__v15 + = (0xffU & (vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__tag_data_access__DOT__data_write[3U] + >> 0x18U)); + __Vdlyvset__VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__data__v15 = 1U; + __Vdlyvlsb__VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__data__v15 = 0x78U; + __Vdlyvdim0__VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__data__v15 + = (0x3fU & vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__addr_st1 + [0U]); + } + } + } + if ((1U & (~ (IData)(vlTOPp->reset)))) { + if ((1U & (~ (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__stall_bank_pipe)))) { + if ((1U & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__tag_data_access__DOT__use_write_enable))) { + __Vdlyvval__VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__data__v0 + = (0xffU & vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__tag_data_access__DOT__data_write[0U]); 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+ __Vdlyvdim0__VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__data__v2 + = (0x3fU & vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__addr_st1 + [0U]); + } + if ((8U & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__tag_data_access__DOT__use_write_enable))) { + __Vdlyvval__VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__data__v3 + = (0xffU & ((vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__tag_data_access__DOT__data_write[1U] + << 8U) | (vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__tag_data_access__DOT__data_write[0U] + >> 0x18U))); + __Vdlyvset__VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__data__v3 = 1U; + __Vdlyvlsb__VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__data__v3 = 0x18U; + __Vdlyvdim0__VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__data__v3 + = (0x3fU & vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__addr_st1 + [0U]); + } + if ((0x10U & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__tag_data_access__DOT__use_write_enable))) { + __Vdlyvval__VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__data__v4 + = (0xffU & vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__tag_data_access__DOT__data_write[1U]); + __Vdlyvset__VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__data__v4 = 1U; + __Vdlyvlsb__VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__data__v4 = 0x20U; + __Vdlyvdim0__VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__data__v4 + = (0x3fU & vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__addr_st1 + [0U]); + } + if ((0x20U & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__tag_data_access__DOT__use_write_enable))) { + __Vdlyvval__VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__data__v5 + = (0xffU & ((vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__tag_data_access__DOT__data_write[2U] + << 0x18U) | (vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__tag_data_access__DOT__data_write[1U] + >> 8U))); + __Vdlyvset__VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__data__v5 = 1U; + __Vdlyvlsb__VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__data__v5 = 0x28U; + __Vdlyvdim0__VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__data__v5 + = (0x3fU & vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__addr_st1 + [0U]); + } + if ((0x40U & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__tag_data_access__DOT__use_write_enable))) { + __Vdlyvval__VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__data__v6 + = (0xffU & ((vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__tag_data_access__DOT__data_write[2U] + << 0x10U) | (vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__tag_data_access__DOT__data_write[1U] + >> 0x10U))); + __Vdlyvset__VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__data__v6 = 1U; + __Vdlyvlsb__VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__data__v6 = 0x30U; + __Vdlyvdim0__VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__data__v6 + = (0x3fU & vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__addr_st1 + [0U]); + } + if ((0x80U & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__tag_data_access__DOT__use_write_enable))) { + __Vdlyvval__VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__data__v7 + = (0xffU & ((vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__tag_data_access__DOT__data_write[2U] + << 8U) | (vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__tag_data_access__DOT__data_write[1U] + >> 0x18U))); + __Vdlyvset__VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__data__v7 = 1U; + __Vdlyvlsb__VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__data__v7 = 0x38U; + __Vdlyvdim0__VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__data__v7 + = (0x3fU & vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__addr_st1 + [0U]); + } + if ((0x100U & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__tag_data_access__DOT__use_write_enable))) { + __Vdlyvval__VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__data__v8 + = (0xffU & vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__tag_data_access__DOT__data_write[2U]); + __Vdlyvset__VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__data__v8 = 1U; + __Vdlyvlsb__VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__data__v8 = 0x40U; + __Vdlyvdim0__VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__data__v8 + = (0x3fU & vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__addr_st1 + [0U]); + } + if ((0x200U & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__tag_data_access__DOT__use_write_enable))) { + __Vdlyvval__VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__data__v9 + = (0xffU & ((vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__tag_data_access__DOT__data_write[3U] + << 0x18U) | (vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__tag_data_access__DOT__data_write[2U] + >> 8U))); + __Vdlyvset__VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__data__v9 = 1U; + __Vdlyvlsb__VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__data__v9 = 0x48U; + __Vdlyvdim0__VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__data__v9 + = (0x3fU & vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__addr_st1 + [0U]); + } + if ((0x400U & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__tag_data_access__DOT__use_write_enable))) { + __Vdlyvval__VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__data__v10 + = (0xffU & ((vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__tag_data_access__DOT__data_write[3U] + << 0x10U) | (vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__tag_data_access__DOT__data_write[2U] + >> 0x10U))); + __Vdlyvset__VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__data__v10 = 1U; + __Vdlyvlsb__VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__data__v10 = 0x50U; + __Vdlyvdim0__VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__data__v10 + = (0x3fU & vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__addr_st1 + [0U]); + } + if ((0x800U & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__tag_data_access__DOT__use_write_enable))) { + __Vdlyvval__VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__data__v11 + = (0xffU & ((vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__tag_data_access__DOT__data_write[3U] + << 8U) | (vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__tag_data_access__DOT__data_write[2U] + >> 0x18U))); + __Vdlyvset__VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__data__v11 = 1U; + __Vdlyvlsb__VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__data__v11 = 0x58U; + __Vdlyvdim0__VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__data__v11 + = (0x3fU & vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__addr_st1 + [0U]); + } + if ((0x1000U & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__tag_data_access__DOT__use_write_enable))) { + __Vdlyvval__VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__data__v12 + = (0xffU & vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__tag_data_access__DOT__data_write[3U]); + __Vdlyvset__VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__data__v12 = 1U; + __Vdlyvlsb__VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__data__v12 = 0x60U; + __Vdlyvdim0__VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__data__v12 + = (0x3fU & vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__addr_st1 + [0U]); + } + if ((0x2000U & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__tag_data_access__DOT__use_write_enable))) { + __Vdlyvval__VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__data__v13 + = (0xffU & (vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__tag_data_access__DOT__data_write[3U] + >> 8U)); + __Vdlyvset__VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__data__v13 = 1U; + __Vdlyvlsb__VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__data__v13 = 0x68U; + __Vdlyvdim0__VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__data__v13 + = (0x3fU & vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__addr_st1 + [0U]); + } + if ((0x4000U & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__tag_data_access__DOT__use_write_enable))) { + __Vdlyvval__VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__data__v14 + = (0xffU & (vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__tag_data_access__DOT__data_write[3U] + >> 0x10U)); + __Vdlyvset__VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__data__v14 = 1U; + __Vdlyvlsb__VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__data__v14 = 0x70U; + __Vdlyvdim0__VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__data__v14 + = (0x3fU & vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__addr_st1 + [0U]); + } + if ((0x8000U & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__tag_data_access__DOT__use_write_enable))) { + __Vdlyvval__VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__data__v15 + = (0xffU & (vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__tag_data_access__DOT__data_write[3U] + >> 0x18U)); + __Vdlyvset__VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__data__v15 = 1U; + __Vdlyvlsb__VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__data__v15 = 0x78U; + __Vdlyvdim0__VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__data__v15 + = (0x3fU & vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__addr_st1 + [0U]); + } + } + } + vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__snp_req_queue__DOT__size_r + = __Vdly__VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__snp_req_queue__DOT__size_r; + vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__snp_req_queue__DOT__genblk3__DOT__genblk2__DOT__wr_ptr_r + = __Vdly__VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__snp_req_queue__DOT__genblk3__DOT__genblk2__DOT__wr_ptr_r; + vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__snp_req_queue__DOT__genblk3__DOT__genblk2__DOT__rd_ptr_r + = __Vdly__VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__snp_req_queue__DOT__genblk3__DOT__genblk2__DOT__rd_ptr_r; + vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__snp_req_queue__DOT__genblk3__DOT__genblk2__DOT__rd_ptr_next_r + = __Vdly__VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__snp_req_queue__DOT__genblk3__DOT__genblk2__DOT__rd_ptr_next_r; + if (__Vdlyvset__VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__snp_req_queue__DOT__genblk3__DOT__data__v0) { + vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__snp_req_queue__DOT__genblk3__DOT__data[__Vdlyvdim0__VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__snp_req_queue__DOT__genblk3__DOT__data__v0] + = __Vdlyvval__VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__snp_req_queue__DOT__genblk3__DOT__data__v0; + } + vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__snp_req_queue__DOT__genblk3__DOT__genblk2__DOT__empty_r + = __Vdly__VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__snp_req_queue__DOT__genblk3__DOT__genblk2__DOT__empty_r; + vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__snp_req_queue__DOT__size_r + = __Vdly__VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__snp_req_queue__DOT__size_r; + vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__snp_req_queue__DOT__genblk3__DOT__genblk2__DOT__wr_ptr_r + = __Vdly__VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__snp_req_queue__DOT__genblk3__DOT__genblk2__DOT__wr_ptr_r; + vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__snp_req_queue__DOT__genblk3__DOT__genblk2__DOT__rd_ptr_r + = __Vdly__VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__snp_req_queue__DOT__genblk3__DOT__genblk2__DOT__rd_ptr_r; + vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__snp_req_queue__DOT__genblk3__DOT__genblk2__DOT__rd_ptr_next_r + = __Vdly__VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__snp_req_queue__DOT__genblk3__DOT__genblk2__DOT__rd_ptr_next_r; + if (__Vdlyvset__VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__snp_req_queue__DOT__genblk3__DOT__data__v0) { + vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__snp_req_queue__DOT__genblk3__DOT__data[__Vdlyvdim0__VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__snp_req_queue__DOT__genblk3__DOT__data__v0] + = __Vdlyvval__VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__snp_req_queue__DOT__genblk3__DOT__data__v0; + } + vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__snp_req_queue__DOT__genblk3__DOT__genblk2__DOT__empty_r + = __Vdly__VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__snp_req_queue__DOT__genblk3__DOT__genblk2__DOT__empty_r; + vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__snp_req_queue__DOT__size_r + = __Vdly__VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__snp_req_queue__DOT__size_r; + vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__snp_req_queue__DOT__genblk3__DOT__genblk2__DOT__wr_ptr_r + = __Vdly__VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__snp_req_queue__DOT__genblk3__DOT__genblk2__DOT__wr_ptr_r; + vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__snp_req_queue__DOT__genblk3__DOT__genblk2__DOT__rd_ptr_r + = __Vdly__VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__snp_req_queue__DOT__genblk3__DOT__genblk2__DOT__rd_ptr_r; + vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__snp_req_queue__DOT__genblk3__DOT__genblk2__DOT__rd_ptr_next_r + = __Vdly__VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__snp_req_queue__DOT__genblk3__DOT__genblk2__DOT__rd_ptr_next_r; + if (__Vdlyvset__VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__snp_req_queue__DOT__genblk3__DOT__data__v0) { + vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__snp_req_queue__DOT__genblk3__DOT__data[__Vdlyvdim0__VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__snp_req_queue__DOT__genblk3__DOT__data__v0] + = __Vdlyvval__VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__snp_req_queue__DOT__genblk3__DOT__data__v0; + } + vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__snp_req_queue__DOT__genblk3__DOT__genblk2__DOT__empty_r + = __Vdly__VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__snp_req_queue__DOT__genblk3__DOT__genblk2__DOT__empty_r; + vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__snp_req_queue__DOT__size_r + = __Vdly__VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__snp_req_queue__DOT__size_r; + vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__snp_req_queue__DOT__genblk3__DOT__genblk2__DOT__wr_ptr_r + = __Vdly__VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__snp_req_queue__DOT__genblk3__DOT__genblk2__DOT__wr_ptr_r; + vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__snp_req_queue__DOT__genblk3__DOT__genblk2__DOT__rd_ptr_r + = __Vdly__VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__snp_req_queue__DOT__genblk3__DOT__genblk2__DOT__rd_ptr_r; + vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__snp_req_queue__DOT__genblk3__DOT__genblk2__DOT__rd_ptr_next_r + = __Vdly__VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__snp_req_queue__DOT__genblk3__DOT__genblk2__DOT__rd_ptr_next_r; + if (__Vdlyvset__VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__snp_req_queue__DOT__genblk3__DOT__data__v0) { + vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__snp_req_queue__DOT__genblk3__DOT__data[__Vdlyvdim0__VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__snp_req_queue__DOT__genblk3__DOT__data__v0] + = __Vdlyvval__VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__snp_req_queue__DOT__genblk3__DOT__data__v0; + } + vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__snp_req_queue__DOT__genblk3__DOT__genblk2__DOT__empty_r + = __Vdly__VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__snp_req_queue__DOT__genblk3__DOT__genblk2__DOT__empty_r; + vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__size_r + = __Vdly__VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__size_r; + vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__wr_ptr_r + = __Vdly__VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__wr_ptr_r; + vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__rd_ptr_r + = __Vdly__VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__rd_ptr_r; + vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__rd_ptr_next_r + = __Vdly__VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__rd_ptr_next_r; + if (__Vdlyvset__VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__data__v0) { + vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__data[__Vdlyvdim0__VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__data__v0][0U] + = __Vdlyvval__VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__data__v0[0U]; + vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__data[__Vdlyvdim0__VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__data__v0][1U] + = __Vdlyvval__VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__data__v0[1U]; + vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__data[__Vdlyvdim0__VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__data__v0][2U] + = __Vdlyvval__VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__data__v0[2U]; + vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__data[__Vdlyvdim0__VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__data__v0][3U] + = __Vdlyvval__VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__data__v0[3U]; + vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__data[__Vdlyvdim0__VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__data__v0][4U] + = __Vdlyvval__VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__data__v0[4U]; + vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__data[__Vdlyvdim0__VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__data__v0][5U] + = __Vdlyvval__VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__data__v0[5U]; + vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__data[__Vdlyvdim0__VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__data__v0][6U] + = __Vdlyvval__VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__data__v0[6U]; + vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__data[__Vdlyvdim0__VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__data__v0][7U] + = __Vdlyvval__VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__data__v0[7U]; + vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__data[__Vdlyvdim0__VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__data__v0][8U] + = __Vdlyvval__VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__data__v0[8U]; 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+ vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__data[__Vdlyvdim0__VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__data__v0][1U] + = __Vdlyvval__VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__data__v0[1U]; + vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__data[__Vdlyvdim0__VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__data__v0][2U] + = __Vdlyvval__VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__data__v0[2U]; + vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__data[__Vdlyvdim0__VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__data__v0][3U] + = __Vdlyvval__VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__data__v0[3U]; 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+ } + vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__empty_r + = __Vdly__VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__empty_r; + vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__size_r + = __Vdly__VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__size_r; + vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__wr_ptr_r + = __Vdly__VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__wr_ptr_r; + vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__rd_ptr_r + = __Vdly__VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__rd_ptr_r; + vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__rd_ptr_next_r + = __Vdly__VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__rd_ptr_next_r; + if (__Vdlyvset__VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__data__v0) { + vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__data[__Vdlyvdim0__VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__data__v0][0U] + = __Vdlyvval__VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__data__v0[0U]; + vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__data[__Vdlyvdim0__VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__data__v0][1U] + = __Vdlyvval__VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__data__v0[1U]; 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+ vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__data[__Vdlyvdim0__VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__data__v0][8U] + = __Vdlyvval__VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__data__v0[8U]; + vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__data[__Vdlyvdim0__VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__data__v0][9U] + = __Vdlyvval__VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__data__v0[9U]; + } + vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__empty_r + = __Vdly__VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__empty_r; + vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__size_r + = __Vdly__VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__size_r; + vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__wr_ptr_r + = __Vdly__VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__wr_ptr_r; + vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__rd_ptr_r + = __Vdly__VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__rd_ptr_r; + vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__rd_ptr_next_r + = __Vdly__VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__rd_ptr_next_r; + if (__Vdlyvset__VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__data__v0) { + vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__data[__Vdlyvdim0__VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__data__v0][0U] + = __Vdlyvval__VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__data__v0[0U]; + vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__data[__Vdlyvdim0__VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__data__v0][1U] + = __Vdlyvval__VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__data__v0[1U]; + vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__data[__Vdlyvdim0__VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__data__v0][2U] + = __Vdlyvval__VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__data__v0[2U]; + vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__data[__Vdlyvdim0__VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__data__v0][3U] + = __Vdlyvval__VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__data__v0[3U]; + vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__data[__Vdlyvdim0__VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__data__v0][4U] + = __Vdlyvval__VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__data__v0[4U]; + vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__data[__Vdlyvdim0__VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__data__v0][5U] + = __Vdlyvval__VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__data__v0[5U]; + vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__data[__Vdlyvdim0__VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__data__v0][6U] + = __Vdlyvval__VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__data__v0[6U]; + vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__data[__Vdlyvdim0__VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__data__v0][7U] + = __Vdlyvval__VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__data__v0[7U]; + vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__data[__Vdlyvdim0__VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__data__v0][8U] + = __Vdlyvval__VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__data__v0[8U]; + vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__data[__Vdlyvdim0__VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__data__v0][9U] + = __Vdlyvval__VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__data__v0[9U]; + } + vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__empty_r + = __Vdly__VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__empty_r; + vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cwb_queue__DOT__size_r + = __Vdly__VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cwb_queue__DOT__size_r; + vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cwb_queue__DOT__genblk3__DOT__genblk2__DOT__wr_ptr_r + = __Vdly__VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cwb_queue__DOT__genblk3__DOT__genblk2__DOT__wr_ptr_r; + vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cwb_queue__DOT__genblk3__DOT__genblk2__DOT__rd_ptr_r + = __Vdly__VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cwb_queue__DOT__genblk3__DOT__genblk2__DOT__rd_ptr_r; + vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cwb_queue__DOT__genblk3__DOT__genblk2__DOT__rd_ptr_next_r + = __Vdly__VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cwb_queue__DOT__genblk3__DOT__genblk2__DOT__rd_ptr_next_r; + if (__Vdlyvset__VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cwb_queue__DOT__genblk3__DOT__data__v0) { + vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cwb_queue__DOT__genblk3__DOT__data[__Vdlyvdim0__VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cwb_queue__DOT__genblk3__DOT__data__v0][0U] + = __Vdlyvval__VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cwb_queue__DOT__genblk3__DOT__data__v0[0U]; + vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cwb_queue__DOT__genblk3__DOT__data[__Vdlyvdim0__VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cwb_queue__DOT__genblk3__DOT__data__v0][1U] + = __Vdlyvval__VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cwb_queue__DOT__genblk3__DOT__data__v0[1U]; + vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cwb_queue__DOT__genblk3__DOT__data[__Vdlyvdim0__VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cwb_queue__DOT__genblk3__DOT__data__v0][2U] + = __Vdlyvval__VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cwb_queue__DOT__genblk3__DOT__data__v0[2U]; + } + vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cwb_queue__DOT__genblk3__DOT__genblk2__DOT__empty_r + = __Vdly__VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cwb_queue__DOT__genblk3__DOT__genblk2__DOT__empty_r; + vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__cwb_queue__DOT__size_r + = __Vdly__VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__cwb_queue__DOT__size_r; + vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__cwb_queue__DOT__genblk3__DOT__genblk2__DOT__wr_ptr_r + = __Vdly__VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__cwb_queue__DOT__genblk3__DOT__genblk2__DOT__wr_ptr_r; + vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__cwb_queue__DOT__genblk3__DOT__genblk2__DOT__rd_ptr_r + = __Vdly__VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__cwb_queue__DOT__genblk3__DOT__genblk2__DOT__rd_ptr_r; + vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__cwb_queue__DOT__genblk3__DOT__genblk2__DOT__rd_ptr_next_r + = __Vdly__VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__cwb_queue__DOT__genblk3__DOT__genblk2__DOT__rd_ptr_next_r; + if (__Vdlyvset__VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__cwb_queue__DOT__genblk3__DOT__data__v0) { + vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__cwb_queue__DOT__genblk3__DOT__data[__Vdlyvdim0__VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__cwb_queue__DOT__genblk3__DOT__data__v0][0U] + = __Vdlyvval__VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__cwb_queue__DOT__genblk3__DOT__data__v0[0U]; + vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__cwb_queue__DOT__genblk3__DOT__data[__Vdlyvdim0__VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__cwb_queue__DOT__genblk3__DOT__data__v0][1U] + = __Vdlyvval__VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__cwb_queue__DOT__genblk3__DOT__data__v0[1U]; + vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__cwb_queue__DOT__genblk3__DOT__data[__Vdlyvdim0__VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__cwb_queue__DOT__genblk3__DOT__data__v0][2U] + = __Vdlyvval__VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__cwb_queue__DOT__genblk3__DOT__data__v0[2U]; + } + vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__cwb_queue__DOT__genblk3__DOT__genblk2__DOT__empty_r + = __Vdly__VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__cwb_queue__DOT__genblk3__DOT__genblk2__DOT__empty_r; + vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__cwb_queue__DOT__size_r + = __Vdly__VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__cwb_queue__DOT__size_r; + vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__cwb_queue__DOT__genblk3__DOT__genblk2__DOT__wr_ptr_r + = __Vdly__VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__cwb_queue__DOT__genblk3__DOT__genblk2__DOT__wr_ptr_r; + vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__cwb_queue__DOT__genblk3__DOT__genblk2__DOT__rd_ptr_r + = __Vdly__VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__cwb_queue__DOT__genblk3__DOT__genblk2__DOT__rd_ptr_r; + vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__cwb_queue__DOT__genblk3__DOT__genblk2__DOT__rd_ptr_next_r + = __Vdly__VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__cwb_queue__DOT__genblk3__DOT__genblk2__DOT__rd_ptr_next_r; + if (__Vdlyvset__VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__cwb_queue__DOT__genblk3__DOT__data__v0) { + vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__cwb_queue__DOT__genblk3__DOT__data[__Vdlyvdim0__VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__cwb_queue__DOT__genblk3__DOT__data__v0][0U] + = __Vdlyvval__VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__cwb_queue__DOT__genblk3__DOT__data__v0[0U]; + vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__cwb_queue__DOT__genblk3__DOT__data[__Vdlyvdim0__VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__cwb_queue__DOT__genblk3__DOT__data__v0][1U] + = __Vdlyvval__VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__cwb_queue__DOT__genblk3__DOT__data__v0[1U]; + vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__cwb_queue__DOT__genblk3__DOT__data[__Vdlyvdim0__VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__cwb_queue__DOT__genblk3__DOT__data__v0][2U] + = __Vdlyvval__VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__cwb_queue__DOT__genblk3__DOT__data__v0[2U]; + } + vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__cwb_queue__DOT__genblk3__DOT__genblk2__DOT__empty_r + = __Vdly__VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__cwb_queue__DOT__genblk3__DOT__genblk2__DOT__empty_r; + vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cwb_queue__DOT__size_r + = __Vdly__VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cwb_queue__DOT__size_r; + vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cwb_queue__DOT__genblk3__DOT__genblk2__DOT__wr_ptr_r + = __Vdly__VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cwb_queue__DOT__genblk3__DOT__genblk2__DOT__wr_ptr_r; + vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cwb_queue__DOT__genblk3__DOT__genblk2__DOT__rd_ptr_r + = __Vdly__VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cwb_queue__DOT__genblk3__DOT__genblk2__DOT__rd_ptr_r; + vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cwb_queue__DOT__genblk3__DOT__genblk2__DOT__rd_ptr_next_r + = __Vdly__VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cwb_queue__DOT__genblk3__DOT__genblk2__DOT__rd_ptr_next_r; + if (__Vdlyvset__VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cwb_queue__DOT__genblk3__DOT__data__v0) { + vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cwb_queue__DOT__genblk3__DOT__data[__Vdlyvdim0__VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cwb_queue__DOT__genblk3__DOT__data__v0][0U] + = __Vdlyvval__VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cwb_queue__DOT__genblk3__DOT__data__v0[0U]; + vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cwb_queue__DOT__genblk3__DOT__data[__Vdlyvdim0__VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cwb_queue__DOT__genblk3__DOT__data__v0][1U] + = __Vdlyvval__VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cwb_queue__DOT__genblk3__DOT__data__v0[1U]; + vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cwb_queue__DOT__genblk3__DOT__data[__Vdlyvdim0__VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cwb_queue__DOT__genblk3__DOT__data__v0][2U] + = __Vdlyvval__VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cwb_queue__DOT__genblk3__DOT__data__v0[2U]; + } + vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cwb_queue__DOT__genblk3__DOT__genblk2__DOT__empty_r + = __Vdly__VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cwb_queue__DOT__genblk3__DOT__genblk2__DOT__empty_r; + vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__dfp_queue__DOT__size_r + = __Vdly__VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__dfp_queue__DOT__size_r; + vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__dfp_queue__DOT__genblk3__DOT__genblk2__DOT__wr_ptr_r + = __Vdly__VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__dfp_queue__DOT__genblk3__DOT__genblk2__DOT__wr_ptr_r; + vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__dfp_queue__DOT__genblk3__DOT__genblk2__DOT__rd_ptr_r + = __Vdly__VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__dfp_queue__DOT__genblk3__DOT__genblk2__DOT__rd_ptr_r; + vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__dfp_queue__DOT__genblk3__DOT__genblk2__DOT__rd_ptr_next_r + = __Vdly__VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__dfp_queue__DOT__genblk3__DOT__genblk2__DOT__rd_ptr_next_r; + if (__Vdlyvset__VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__dfp_queue__DOT__genblk3__DOT__data__v0) { + vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__dfp_queue__DOT__genblk3__DOT__data[__Vdlyvdim0__VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__dfp_queue__DOT__genblk3__DOT__data__v0][0U] + = __Vdlyvval__VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__dfp_queue__DOT__genblk3__DOT__data__v0[0U]; + vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__dfp_queue__DOT__genblk3__DOT__data[__Vdlyvdim0__VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__dfp_queue__DOT__genblk3__DOT__data__v0][1U] + = __Vdlyvval__VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__dfp_queue__DOT__genblk3__DOT__data__v0[1U]; + vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__dfp_queue__DOT__genblk3__DOT__data[__Vdlyvdim0__VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__dfp_queue__DOT__genblk3__DOT__data__v0][2U] + = __Vdlyvval__VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__dfp_queue__DOT__genblk3__DOT__data__v0[2U]; + vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__dfp_queue__DOT__genblk3__DOT__data[__Vdlyvdim0__VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__dfp_queue__DOT__genblk3__DOT__data__v0][3U] + = __Vdlyvval__VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__dfp_queue__DOT__genblk3__DOT__data__v0[3U]; + vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__dfp_queue__DOT__genblk3__DOT__data[__Vdlyvdim0__VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__dfp_queue__DOT__genblk3__DOT__data__v0][4U] + = __Vdlyvval__VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__dfp_queue__DOT__genblk3__DOT__data__v0[4U]; + } + vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__dfp_queue__DOT__genblk3__DOT__genblk2__DOT__empty_r + = __Vdly__VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__dfp_queue__DOT__genblk3__DOT__genblk2__DOT__empty_r; + vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__dfp_queue__DOT__size_r + = __Vdly__VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__dfp_queue__DOT__size_r; + vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__dfp_queue__DOT__genblk3__DOT__genblk2__DOT__wr_ptr_r + = __Vdly__VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__dfp_queue__DOT__genblk3__DOT__genblk2__DOT__wr_ptr_r; + vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__dfp_queue__DOT__genblk3__DOT__genblk2__DOT__rd_ptr_r + = __Vdly__VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__dfp_queue__DOT__genblk3__DOT__genblk2__DOT__rd_ptr_r; + vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__dfp_queue__DOT__genblk3__DOT__genblk2__DOT__rd_ptr_next_r + = __Vdly__VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__dfp_queue__DOT__genblk3__DOT__genblk2__DOT__rd_ptr_next_r; + if (__Vdlyvset__VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__dfp_queue__DOT__genblk3__DOT__data__v0) { + vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__dfp_queue__DOT__genblk3__DOT__data[__Vdlyvdim0__VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__dfp_queue__DOT__genblk3__DOT__data__v0][0U] + = __Vdlyvval__VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__dfp_queue__DOT__genblk3__DOT__data__v0[0U]; + vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__dfp_queue__DOT__genblk3__DOT__data[__Vdlyvdim0__VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__dfp_queue__DOT__genblk3__DOT__data__v0][1U] + = __Vdlyvval__VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__dfp_queue__DOT__genblk3__DOT__data__v0[1U]; + vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__dfp_queue__DOT__genblk3__DOT__data[__Vdlyvdim0__VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__dfp_queue__DOT__genblk3__DOT__data__v0][2U] + = __Vdlyvval__VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__dfp_queue__DOT__genblk3__DOT__data__v0[2U]; + vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__dfp_queue__DOT__genblk3__DOT__data[__Vdlyvdim0__VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__dfp_queue__DOT__genblk3__DOT__data__v0][3U] + = __Vdlyvval__VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__dfp_queue__DOT__genblk3__DOT__data__v0[3U]; + vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__dfp_queue__DOT__genblk3__DOT__data[__Vdlyvdim0__VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__dfp_queue__DOT__genblk3__DOT__data__v0][4U] + = __Vdlyvval__VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__dfp_queue__DOT__genblk3__DOT__data__v0[4U]; + } + vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__dfp_queue__DOT__genblk3__DOT__genblk2__DOT__empty_r + = __Vdly__VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__dfp_queue__DOT__genblk3__DOT__genblk2__DOT__empty_r; + vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__dfp_queue__DOT__size_r + = __Vdly__VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__dfp_queue__DOT__size_r; + vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__dfp_queue__DOT__genblk3__DOT__genblk2__DOT__wr_ptr_r + = __Vdly__VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__dfp_queue__DOT__genblk3__DOT__genblk2__DOT__wr_ptr_r; + vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__dfp_queue__DOT__genblk3__DOT__genblk2__DOT__rd_ptr_r + = __Vdly__VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__dfp_queue__DOT__genblk3__DOT__genblk2__DOT__rd_ptr_r; + vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__dfp_queue__DOT__genblk3__DOT__genblk2__DOT__rd_ptr_next_r + = __Vdly__VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__dfp_queue__DOT__genblk3__DOT__genblk2__DOT__rd_ptr_next_r; + if (__Vdlyvset__VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__dfp_queue__DOT__genblk3__DOT__data__v0) { + vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__dfp_queue__DOT__genblk3__DOT__data[__Vdlyvdim0__VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__dfp_queue__DOT__genblk3__DOT__data__v0][0U] + = __Vdlyvval__VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__dfp_queue__DOT__genblk3__DOT__data__v0[0U]; + vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__dfp_queue__DOT__genblk3__DOT__data[__Vdlyvdim0__VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__dfp_queue__DOT__genblk3__DOT__data__v0][1U] + = __Vdlyvval__VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__dfp_queue__DOT__genblk3__DOT__data__v0[1U]; + vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__dfp_queue__DOT__genblk3__DOT__data[__Vdlyvdim0__VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__dfp_queue__DOT__genblk3__DOT__data__v0][2U] + = __Vdlyvval__VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__dfp_queue__DOT__genblk3__DOT__data__v0[2U]; + vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__dfp_queue__DOT__genblk3__DOT__data[__Vdlyvdim0__VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__dfp_queue__DOT__genblk3__DOT__data__v0][3U] + = __Vdlyvval__VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__dfp_queue__DOT__genblk3__DOT__data__v0[3U]; + vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__dfp_queue__DOT__genblk3__DOT__data[__Vdlyvdim0__VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__dfp_queue__DOT__genblk3__DOT__data__v0][4U] + = __Vdlyvval__VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__dfp_queue__DOT__genblk3__DOT__data__v0[4U]; + } + vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__dfp_queue__DOT__genblk3__DOT__genblk2__DOT__empty_r + = __Vdly__VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__dfp_queue__DOT__genblk3__DOT__genblk2__DOT__empty_r; + vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__dfp_queue__DOT__size_r + = __Vdly__VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__dfp_queue__DOT__size_r; + vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__dfp_queue__DOT__genblk3__DOT__genblk2__DOT__wr_ptr_r + = __Vdly__VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__dfp_queue__DOT__genblk3__DOT__genblk2__DOT__wr_ptr_r; + vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__dfp_queue__DOT__genblk3__DOT__genblk2__DOT__rd_ptr_r + = __Vdly__VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__dfp_queue__DOT__genblk3__DOT__genblk2__DOT__rd_ptr_r; + vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__dfp_queue__DOT__genblk3__DOT__genblk2__DOT__rd_ptr_next_r + = __Vdly__VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__dfp_queue__DOT__genblk3__DOT__genblk2__DOT__rd_ptr_next_r; + if (__Vdlyvset__VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__dfp_queue__DOT__genblk3__DOT__data__v0) { + vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__dfp_queue__DOT__genblk3__DOT__data[__Vdlyvdim0__VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__dfp_queue__DOT__genblk3__DOT__data__v0][0U] + = __Vdlyvval__VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__dfp_queue__DOT__genblk3__DOT__data__v0[0U]; + vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__dfp_queue__DOT__genblk3__DOT__data[__Vdlyvdim0__VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__dfp_queue__DOT__genblk3__DOT__data__v0][1U] + = __Vdlyvval__VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__dfp_queue__DOT__genblk3__DOT__data__v0[1U]; + vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__dfp_queue__DOT__genblk3__DOT__data[__Vdlyvdim0__VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__dfp_queue__DOT__genblk3__DOT__data__v0][2U] + = __Vdlyvval__VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__dfp_queue__DOT__genblk3__DOT__data__v0[2U]; + vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__dfp_queue__DOT__genblk3__DOT__data[__Vdlyvdim0__VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__dfp_queue__DOT__genblk3__DOT__data__v0][3U] + = __Vdlyvval__VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__dfp_queue__DOT__genblk3__DOT__data__v0[3U]; + vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__dfp_queue__DOT__genblk3__DOT__data[__Vdlyvdim0__VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__dfp_queue__DOT__genblk3__DOT__data__v0][4U] + = __Vdlyvval__VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__dfp_queue__DOT__genblk3__DOT__data__v0[4U]; + } + vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__dfp_queue__DOT__genblk3__DOT__genblk2__DOT__empty_r + = __Vdly__VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__dfp_queue__DOT__genblk3__DOT__genblk2__DOT__empty_r; + vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cache_miss_resrv__DOT__size + = __Vdly__VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cache_miss_resrv__DOT__size; + vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__cache_miss_resrv__DOT__size + = __Vdly__VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__cache_miss_resrv__DOT__size; + vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__cache_miss_resrv__DOT__size + = __Vdly__VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__cache_miss_resrv__DOT__size; + vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cache_miss_resrv__DOT__size + = __Vdly__VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cache_miss_resrv__DOT__size; + vlTOPp->VX_cache__DOT__cache_dram_req_arb__DOT__dram_fill_arb__DOT__dfqq_queue__DOT__size_r + = __Vdly__VX_cache__DOT__cache_dram_req_arb__DOT__dram_fill_arb__DOT__dfqq_queue__DOT__size_r; + vlTOPp->VX_cache__DOT__cache_dram_req_arb__DOT__dram_fill_arb__DOT__dfqq_queue__DOT__genblk3__DOT__genblk2__DOT__wr_ptr_r + = __Vdly__VX_cache__DOT__cache_dram_req_arb__DOT__dram_fill_arb__DOT__dfqq_queue__DOT__genblk3__DOT__genblk2__DOT__wr_ptr_r; + vlTOPp->VX_cache__DOT__cache_dram_req_arb__DOT__dram_fill_arb__DOT__dfqq_queue__DOT__genblk3__DOT__genblk2__DOT__rd_ptr_r + = __Vdly__VX_cache__DOT__cache_dram_req_arb__DOT__dram_fill_arb__DOT__dfqq_queue__DOT__genblk3__DOT__genblk2__DOT__rd_ptr_r; + vlTOPp->VX_cache__DOT__cache_dram_req_arb__DOT__dram_fill_arb__DOT__dfqq_queue__DOT__genblk3__DOT__genblk2__DOT__rd_ptr_next_r + = __Vdly__VX_cache__DOT__cache_dram_req_arb__DOT__dram_fill_arb__DOT__dfqq_queue__DOT__genblk3__DOT__genblk2__DOT__rd_ptr_next_r; + if (__Vdlyvset__VX_cache__DOT__cache_dram_req_arb__DOT__dram_fill_arb__DOT__dfqq_queue__DOT__genblk3__DOT__data__v0) { + vlTOPp->VX_cache__DOT__cache_dram_req_arb__DOT__dram_fill_arb__DOT__dfqq_queue__DOT__genblk3__DOT__data[__Vdlyvdim0__VX_cache__DOT__cache_dram_req_arb__DOT__dram_fill_arb__DOT__dfqq_queue__DOT__genblk3__DOT__data__v0][0U] + = __Vdlyvval__VX_cache__DOT__cache_dram_req_arb__DOT__dram_fill_arb__DOT__dfqq_queue__DOT__genblk3__DOT__data__v0[0U]; + vlTOPp->VX_cache__DOT__cache_dram_req_arb__DOT__dram_fill_arb__DOT__dfqq_queue__DOT__genblk3__DOT__data[__Vdlyvdim0__VX_cache__DOT__cache_dram_req_arb__DOT__dram_fill_arb__DOT__dfqq_queue__DOT__genblk3__DOT__data__v0][1U] + = __Vdlyvval__VX_cache__DOT__cache_dram_req_arb__DOT__dram_fill_arb__DOT__dfqq_queue__DOT__genblk3__DOT__data__v0[1U]; + vlTOPp->VX_cache__DOT__cache_dram_req_arb__DOT__dram_fill_arb__DOT__dfqq_queue__DOT__genblk3__DOT__data[__Vdlyvdim0__VX_cache__DOT__cache_dram_req_arb__DOT__dram_fill_arb__DOT__dfqq_queue__DOT__genblk3__DOT__data__v0][2U] + = __Vdlyvval__VX_cache__DOT__cache_dram_req_arb__DOT__dram_fill_arb__DOT__dfqq_queue__DOT__genblk3__DOT__data__v0[2U]; + vlTOPp->VX_cache__DOT__cache_dram_req_arb__DOT__dram_fill_arb__DOT__dfqq_queue__DOT__genblk3__DOT__data[__Vdlyvdim0__VX_cache__DOT__cache_dram_req_arb__DOT__dram_fill_arb__DOT__dfqq_queue__DOT__genblk3__DOT__data__v0][3U] + = __Vdlyvval__VX_cache__DOT__cache_dram_req_arb__DOT__dram_fill_arb__DOT__dfqq_queue__DOT__genblk3__DOT__data__v0[3U]; + } + vlTOPp->VX_cache__DOT__cache_dram_req_arb__DOT__dram_fill_arb__DOT__dfqq_queue__DOT__genblk3__DOT__genblk2__DOT__empty_r + = __Vdly__VX_cache__DOT__cache_dram_req_arb__DOT__dram_fill_arb__DOT__dfqq_queue__DOT__genblk3__DOT__genblk2__DOT__empty_r; + vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cache_miss_resrv__DOT__ready_table + = __Vdly__VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cache_miss_resrv__DOT__ready_table; + vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr + = __Vdly__VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr; + vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__cache_miss_resrv__DOT__ready_table + = __Vdly__VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__cache_miss_resrv__DOT__ready_table; + vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr + = __Vdly__VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr; + vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__cache_miss_resrv__DOT__ready_table + = __Vdly__VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__cache_miss_resrv__DOT__ready_table; + vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr + = __Vdly__VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr; + vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cache_miss_resrv__DOT__ready_table + = __Vdly__VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cache_miss_resrv__DOT__ready_table; + vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr + = __Vdly__VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr; + vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__dwbq_dual_valid_sel + = __Vdly__VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__dwbq_dual_valid_sel; + vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__dwbq_dual_valid_sel + = __Vdly__VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__dwbq_dual_valid_sel; + vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__dwbq_dual_valid_sel + = __Vdly__VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__dwbq_dual_valid_sel; + vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__dwbq_dual_valid_sel + = __Vdly__VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__dwbq_dual_valid_sel; + vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__dwb_queue__DOT__size_r + = __Vdly__VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__dwb_queue__DOT__size_r; + vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__genblk2__DOT__wr_ptr_r + = __Vdly__VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__genblk2__DOT__wr_ptr_r; + vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__genblk2__DOT__rd_ptr_r + = __Vdly__VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__genblk2__DOT__rd_ptr_r; + vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__genblk2__DOT__rd_ptr_next_r + = __Vdly__VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__genblk2__DOT__rd_ptr_next_r; + if (__Vdlyvset__VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__data__v0) { + vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__data[__Vdlyvdim0__VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__data__v0][0U] + = __Vdlyvval__VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__data__v0[0U]; + vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__data[__Vdlyvdim0__VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__data__v0][1U] + = __Vdlyvval__VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__data__v0[1U]; + vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__data[__Vdlyvdim0__VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__data__v0][2U] + = __Vdlyvval__VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__data__v0[2U]; + vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__data[__Vdlyvdim0__VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__data__v0][3U] + = __Vdlyvval__VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__data__v0[3U]; + vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__data[__Vdlyvdim0__VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__data__v0][4U] + = __Vdlyvval__VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__data__v0[4U]; + vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__data[__Vdlyvdim0__VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__data__v0][5U] + = __Vdlyvval__VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__data__v0[5U]; + vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__data[__Vdlyvdim0__VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__data__v0][6U] + = __Vdlyvval__VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__data__v0[6U]; + } + vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__genblk2__DOT__empty_r + = __Vdly__VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__genblk2__DOT__empty_r; + vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__dwb_queue__DOT__size_r + = __Vdly__VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__dwb_queue__DOT__size_r; + vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__genblk2__DOT__wr_ptr_r + = __Vdly__VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__genblk2__DOT__wr_ptr_r; + vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__genblk2__DOT__rd_ptr_r + = __Vdly__VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__genblk2__DOT__rd_ptr_r; + vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__genblk2__DOT__rd_ptr_next_r + = __Vdly__VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__genblk2__DOT__rd_ptr_next_r; + if (__Vdlyvset__VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__data__v0) { + vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__data[__Vdlyvdim0__VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__data__v0][0U] + = __Vdlyvval__VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__data__v0[0U]; + vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__data[__Vdlyvdim0__VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__data__v0][1U] + = __Vdlyvval__VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__data__v0[1U]; + vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__data[__Vdlyvdim0__VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__data__v0][2U] + = __Vdlyvval__VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__data__v0[2U]; + vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__data[__Vdlyvdim0__VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__data__v0][3U] + = __Vdlyvval__VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__data__v0[3U]; + vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__data[__Vdlyvdim0__VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__data__v0][4U] + = __Vdlyvval__VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__data__v0[4U]; + vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__data[__Vdlyvdim0__VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__data__v0][5U] + = __Vdlyvval__VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__data__v0[5U]; + vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__data[__Vdlyvdim0__VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__data__v0][6U] + = __Vdlyvval__VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__data__v0[6U]; + } + vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__genblk2__DOT__empty_r + = __Vdly__VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__genblk2__DOT__empty_r; + vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__dwb_queue__DOT__size_r + = __Vdly__VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__dwb_queue__DOT__size_r; + vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__genblk2__DOT__wr_ptr_r + = __Vdly__VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__genblk2__DOT__wr_ptr_r; + vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__genblk2__DOT__rd_ptr_r + = __Vdly__VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__genblk2__DOT__rd_ptr_r; + vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__genblk2__DOT__rd_ptr_next_r + = __Vdly__VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__genblk2__DOT__rd_ptr_next_r; + if (__Vdlyvset__VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__data__v0) { + vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__data[__Vdlyvdim0__VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__data__v0][0U] + = __Vdlyvval__VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__data__v0[0U]; + vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__data[__Vdlyvdim0__VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__data__v0][1U] + = __Vdlyvval__VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__data__v0[1U]; + vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__data[__Vdlyvdim0__VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__data__v0][2U] + = __Vdlyvval__VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__data__v0[2U]; + vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__data[__Vdlyvdim0__VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__data__v0][3U] + = __Vdlyvval__VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__data__v0[3U]; + vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__data[__Vdlyvdim0__VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__data__v0][4U] + = __Vdlyvval__VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__data__v0[4U]; + vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__data[__Vdlyvdim0__VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__data__v0][5U] + = __Vdlyvval__VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__data__v0[5U]; + vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__data[__Vdlyvdim0__VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__data__v0][6U] + = __Vdlyvval__VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__data__v0[6U]; + } + vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__genblk2__DOT__empty_r + = __Vdly__VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__genblk2__DOT__empty_r; + vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__dwb_queue__DOT__size_r + = __Vdly__VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__dwb_queue__DOT__size_r; + vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__genblk2__DOT__wr_ptr_r + = __Vdly__VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__genblk2__DOT__wr_ptr_r; + vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__genblk2__DOT__rd_ptr_r + = __Vdly__VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__genblk2__DOT__rd_ptr_r; + vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__genblk2__DOT__rd_ptr_next_r + = __Vdly__VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__genblk2__DOT__rd_ptr_next_r; + if (__Vdlyvset__VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__data__v0) { + vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__data[__Vdlyvdim0__VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__data__v0][0U] + = __Vdlyvval__VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__data__v0[0U]; + vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__data[__Vdlyvdim0__VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__data__v0][1U] + = __Vdlyvval__VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__data__v0[1U]; + vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__data[__Vdlyvdim0__VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__data__v0][2U] + = __Vdlyvval__VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__data__v0[2U]; + vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__data[__Vdlyvdim0__VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__data__v0][3U] + = __Vdlyvval__VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__data__v0[3U]; + vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__data[__Vdlyvdim0__VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__data__v0][4U] + = __Vdlyvval__VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__data__v0[4U]; + vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__data[__Vdlyvdim0__VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__data__v0][5U] + = __Vdlyvval__VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__data__v0[5U]; + vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__data[__Vdlyvdim0__VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__data__v0][6U] + = __Vdlyvval__VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__data__v0[6U]; + } + vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__genblk2__DOT__empty_r + = __Vdly__VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__genblk2__DOT__empty_r; + if (__Vdlyvset__VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cache_miss_resrv__DOT__metadata_table__v0) { + vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cache_miss_resrv__DOT__metadata_table[__Vdlyvdim0__VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cache_miss_resrv__DOT__metadata_table__v0][0U] + = __Vdlyvval__VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cache_miss_resrv__DOT__metadata_table__v0[0U]; + vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cache_miss_resrv__DOT__metadata_table[__Vdlyvdim0__VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cache_miss_resrv__DOT__metadata_table__v0][1U] + = __Vdlyvval__VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cache_miss_resrv__DOT__metadata_table__v0[1U]; + vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cache_miss_resrv__DOT__metadata_table[__Vdlyvdim0__VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cache_miss_resrv__DOT__metadata_table__v0][2U] + = __Vdlyvval__VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cache_miss_resrv__DOT__metadata_table__v0[2U]; + } + if (__Vdlyvset__VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__cache_miss_resrv__DOT__metadata_table__v0) { + vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__cache_miss_resrv__DOT__metadata_table[__Vdlyvdim0__VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__cache_miss_resrv__DOT__metadata_table__v0][0U] + = __Vdlyvval__VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__cache_miss_resrv__DOT__metadata_table__v0[0U]; + vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__cache_miss_resrv__DOT__metadata_table[__Vdlyvdim0__VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__cache_miss_resrv__DOT__metadata_table__v0][1U] + = __Vdlyvval__VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__cache_miss_resrv__DOT__metadata_table__v0[1U]; + vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__cache_miss_resrv__DOT__metadata_table[__Vdlyvdim0__VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__cache_miss_resrv__DOT__metadata_table__v0][2U] + = __Vdlyvval__VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__cache_miss_resrv__DOT__metadata_table__v0[2U]; + } + if (__Vdlyvset__VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__cache_miss_resrv__DOT__metadata_table__v0) { + vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__cache_miss_resrv__DOT__metadata_table[__Vdlyvdim0__VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__cache_miss_resrv__DOT__metadata_table__v0][0U] + = __Vdlyvval__VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__cache_miss_resrv__DOT__metadata_table__v0[0U]; + vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__cache_miss_resrv__DOT__metadata_table[__Vdlyvdim0__VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__cache_miss_resrv__DOT__metadata_table__v0][1U] + = __Vdlyvval__VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__cache_miss_resrv__DOT__metadata_table__v0[1U]; + vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__cache_miss_resrv__DOT__metadata_table[__Vdlyvdim0__VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__cache_miss_resrv__DOT__metadata_table__v0][2U] + = __Vdlyvval__VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__cache_miss_resrv__DOT__metadata_table__v0[2U]; + } + if (__Vdlyvset__VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cache_miss_resrv__DOT__metadata_table__v0) { + vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cache_miss_resrv__DOT__metadata_table[__Vdlyvdim0__VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cache_miss_resrv__DOT__metadata_table__v0][0U] + = __Vdlyvval__VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cache_miss_resrv__DOT__metadata_table__v0[0U]; + vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cache_miss_resrv__DOT__metadata_table[__Vdlyvdim0__VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cache_miss_resrv__DOT__metadata_table__v0][1U] + = __Vdlyvval__VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cache_miss_resrv__DOT__metadata_table__v0[1U]; + vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cache_miss_resrv__DOT__metadata_table[__Vdlyvdim0__VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cache_miss_resrv__DOT__metadata_table__v0][2U] + = __Vdlyvval__VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cache_miss_resrv__DOT__metadata_table__v0[2U]; + } + vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cache_miss_resrv__DOT__head_ptr + = __Vdly__VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cache_miss_resrv__DOT__head_ptr; + vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__cache_miss_resrv__DOT__head_ptr + = __Vdly__VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__cache_miss_resrv__DOT__head_ptr; + vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__cache_miss_resrv__DOT__head_ptr + = __Vdly__VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__cache_miss_resrv__DOT__head_ptr; + vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cache_miss_resrv__DOT__head_ptr + = __Vdly__VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cache_miss_resrv__DOT__head_ptr; + if (__Vdlyvset__VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__tag__v0) { + vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__tag[__Vdlyvdim0__VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__tag__v0] + = __Vdlyvval__VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__tag__v0; + } + if (__Vdlyvset__VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__tag__v0) { + vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__tag[__Vdlyvdim0__VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__tag__v0] + = __Vdlyvval__VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__tag__v0; + } + if (__Vdlyvset__VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__tag__v0) { + vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__tag[__Vdlyvdim0__VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__tag__v0] + = __Vdlyvval__VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__tag__v0; + } + if (__Vdlyvset__VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__tag__v0) { + vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__tag[__Vdlyvdim0__VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__tag__v0] + = __Vdlyvval__VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__tag__v0; + } + vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cache_miss_resrv__DOT__tail_ptr + = __Vdly__VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cache_miss_resrv__DOT__tail_ptr; + vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__cache_miss_resrv__DOT__tail_ptr + = __Vdly__VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__cache_miss_resrv__DOT__tail_ptr; + vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__cache_miss_resrv__DOT__tail_ptr + = __Vdly__VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__cache_miss_resrv__DOT__tail_ptr; + vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cache_miss_resrv__DOT__tail_ptr + = __Vdly__VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cache_miss_resrv__DOT__tail_ptr; + if (__Vdlyvset__VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__dirtyb__v0) { + vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__dirtyb[__Vdlyvdim0__VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__dirtyb__v0] + = __Vdlyvval__VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__dirtyb__v0; + } + if (__Vdlyvset__VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__dirtyb__v1) { + vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__dirtyb[__Vdlyvdim0__VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__dirtyb__v1] = 0U; + } + if (__Vdlyvset__VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__dirtyb__v0) { + vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__dirtyb[__Vdlyvdim0__VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__dirtyb__v0] + = __Vdlyvval__VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__dirtyb__v0; + } + if (__Vdlyvset__VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__dirtyb__v1) { + vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__dirtyb[__Vdlyvdim0__VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__dirtyb__v1] = 0U; + } + if (__Vdlyvset__VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__dirtyb__v0) { + vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__dirtyb[__Vdlyvdim0__VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__dirtyb__v0] + = __Vdlyvval__VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__dirtyb__v0; + } + if (__Vdlyvset__VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__dirtyb__v1) { + vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__dirtyb[__Vdlyvdim0__VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__dirtyb__v1] = 0U; + } + if (__Vdlyvset__VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__dirtyb__v0) { + vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__dirtyb[__Vdlyvdim0__VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__dirtyb__v0] + = __Vdlyvval__VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__dirtyb__v0; + } + if (__Vdlyvset__VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__dirtyb__v1) { + vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__dirtyb[__Vdlyvdim0__VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__dirtyb__v1] = 0U; + } + if (__Vdlyvset__VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__data__v0) { + VL_ASSIGNSEL_WIII(8,(IData)(__Vdlyvlsb__VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__data__v0), + vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__data + [__Vdlyvdim0__VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__data__v0], __Vdlyvval__VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__data__v0); + } + if (__Vdlyvset__VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__data__v1) { + VL_ASSIGNSEL_WIII(8,(IData)(__Vdlyvlsb__VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__data__v1), + vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__data + [__Vdlyvdim0__VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__data__v1], __Vdlyvval__VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__data__v1); + } + if (__Vdlyvset__VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__data__v2) { + VL_ASSIGNSEL_WIII(8,(IData)(__Vdlyvlsb__VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__data__v2), + vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__data + [__Vdlyvdim0__VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__data__v2], __Vdlyvval__VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__data__v2); + } + if (__Vdlyvset__VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__data__v3) { + VL_ASSIGNSEL_WIII(8,(IData)(__Vdlyvlsb__VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__data__v3), + vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__data + [__Vdlyvdim0__VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__data__v3], __Vdlyvval__VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__data__v3); + } + if (__Vdlyvset__VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__data__v4) { + VL_ASSIGNSEL_WIII(8,(IData)(__Vdlyvlsb__VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__data__v4), + vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__data + [__Vdlyvdim0__VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__data__v4], __Vdlyvval__VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__data__v4); + } + if (__Vdlyvset__VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__data__v5) { + VL_ASSIGNSEL_WIII(8,(IData)(__Vdlyvlsb__VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__data__v5), + vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__data + [__Vdlyvdim0__VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__data__v5], __Vdlyvval__VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__data__v5); + } + if (__Vdlyvset__VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__data__v6) { + VL_ASSIGNSEL_WIII(8,(IData)(__Vdlyvlsb__VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__data__v6), + vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__data + [__Vdlyvdim0__VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__data__v6], __Vdlyvval__VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__data__v6); + } + if (__Vdlyvset__VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__data__v7) { + VL_ASSIGNSEL_WIII(8,(IData)(__Vdlyvlsb__VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__data__v7), + vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__data + [__Vdlyvdim0__VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__data__v7], __Vdlyvval__VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__data__v7); + } + if (__Vdlyvset__VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__data__v8) { + VL_ASSIGNSEL_WIII(8,(IData)(__Vdlyvlsb__VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__data__v8), + vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__data + [__Vdlyvdim0__VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__data__v8], __Vdlyvval__VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__data__v8); 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+ } + if (__Vdlyvset__VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__data__v11) { + VL_ASSIGNSEL_WIII(8,(IData)(__Vdlyvlsb__VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__data__v11), + vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__data + [__Vdlyvdim0__VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__data__v11], __Vdlyvval__VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__data__v11); + } + if (__Vdlyvset__VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__data__v12) { + VL_ASSIGNSEL_WIII(8,(IData)(__Vdlyvlsb__VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__data__v12), + vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__data + [__Vdlyvdim0__VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__data__v12], __Vdlyvval__VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__data__v12); + } + if (__Vdlyvset__VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__data__v13) { + VL_ASSIGNSEL_WIII(8,(IData)(__Vdlyvlsb__VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__data__v13), + vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__data + [__Vdlyvdim0__VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__data__v13], __Vdlyvval__VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__data__v13); + } + if (__Vdlyvset__VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__data__v14) { + VL_ASSIGNSEL_WIII(8,(IData)(__Vdlyvlsb__VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__data__v14), + vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__data + [__Vdlyvdim0__VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__data__v14], __Vdlyvval__VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__data__v14); + } + if (__Vdlyvset__VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__data__v15) { + VL_ASSIGNSEL_WIII(8,(IData)(__Vdlyvlsb__VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__data__v15), + vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__data + [__Vdlyvdim0__VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__data__v15], __Vdlyvval__VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__data__v15); + } + vlTOPp->VX_cache__DOT__cache_dram_req_arb__DOT__prfqq__DOT__update_use + = (((0U == (IData)(vlTOPp->VX_cache__DOT__cache_dram_req_arb__DOT__prfqq__DOT__use_valid)) + | (0U == ((IData)(vlTOPp->VX_cache__DOT__cache_dram_req_arb__DOT__prfqq__DOT__use_valid) + - (IData)(1U)))) & (IData)(vlTOPp->VX_cache__DOT__cache_dram_req_arb__DOT__prfqq__DOT__pfq_queue__DOT__size_r)); + if (vlTOPp->reset) { + vlTOPp->VX_cache__DOT__cache_dram_req_arb__DOT__prfqq__DOT__pfq_queue__DOT__genblk2__DOT__head_r = 0U; + } else { + if (vlTOPp->VX_cache__DOT__cache_dram_req_arb__DOT__prfqq__DOT__pfq_queue__DOT__writing) { + vlTOPp->VX_cache__DOT__cache_dram_req_arb__DOT__prfqq__DOT__pfq_queue__DOT__genblk2__DOT__head_r + = vlTOPp->dram_req_addr; + } + } + vlTOPp->VX_cache__DOT__per_bank_snp_req_ready = + ((7U & (IData)(vlTOPp->VX_cache__DOT__per_bank_snp_req_ready)) + | (8U & ((~ (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__snp_req_queue__DOT__genblk3__DOT__genblk2__DOT__full_r)) + << 3U))); + vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT____Vcellout__snp_req_queue__data_out + = ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__snp_req_queue__DOT__genblk3__DOT__genblk2__DOT__bypass_r) + ? vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__snp_req_queue__DOT__genblk3__DOT__genblk2__DOT__curr_r + : vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__snp_req_queue__DOT__genblk3__DOT__genblk2__DOT__head_r); + vlTOPp->VX_cache__DOT__per_bank_snp_req_ready = + ((0xbU & (IData)(vlTOPp->VX_cache__DOT__per_bank_snp_req_ready)) + | (4U & ((~ (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__snp_req_queue__DOT__genblk3__DOT__genblk2__DOT__full_r)) + << 2U))); + vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT____Vcellout__snp_req_queue__data_out + = ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__snp_req_queue__DOT__genblk3__DOT__genblk2__DOT__bypass_r) + ? vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__snp_req_queue__DOT__genblk3__DOT__genblk2__DOT__curr_r + : vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__snp_req_queue__DOT__genblk3__DOT__genblk2__DOT__head_r); + vlTOPp->VX_cache__DOT__per_bank_snp_req_ready = + ((0xdU & (IData)(vlTOPp->VX_cache__DOT__per_bank_snp_req_ready)) + | (2U & ((~ (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__snp_req_queue__DOT__genblk3__DOT__genblk2__DOT__full_r)) + << 1U))); + vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT____Vcellout__snp_req_queue__data_out + = ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__snp_req_queue__DOT__genblk3__DOT__genblk2__DOT__bypass_r) + ? vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__snp_req_queue__DOT__genblk3__DOT__genblk2__DOT__curr_r + : vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__snp_req_queue__DOT__genblk3__DOT__genblk2__DOT__head_r); + vlTOPp->VX_cache__DOT__per_bank_snp_req_ready = + ((0xeU & (IData)(vlTOPp->VX_cache__DOT__per_bank_snp_req_ready)) + | (1U & (~ (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__snp_req_queue__DOT__genblk3__DOT__genblk2__DOT__full_r)))); + vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT____Vcellout__snp_req_queue__data_out + = ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__snp_req_queue__DOT__genblk3__DOT__genblk2__DOT__bypass_r) + ? vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__snp_req_queue__DOT__genblk3__DOT__genblk2__DOT__curr_r + : vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__snp_req_queue__DOT__genblk3__DOT__genblk2__DOT__head_r); + vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__core_req_arb__DOT____Vcellout__reqq_queue__data_out[0U] + = ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__bypass_r) + ? vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__curr_r[0U] + : vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__head_r[0U]); + vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__core_req_arb__DOT____Vcellout__reqq_queue__data_out[1U] + = ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__bypass_r) + ? vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__curr_r[1U] + : vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__head_r[1U]); + vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__core_req_arb__DOT____Vcellout__reqq_queue__data_out[2U] + = ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__bypass_r) + ? vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__curr_r[2U] + : vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__head_r[2U]); + vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__core_req_arb__DOT____Vcellout__reqq_queue__data_out[3U] + = ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__bypass_r) + ? vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__curr_r[3U] + : vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__head_r[3U]); + vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__core_req_arb__DOT____Vcellout__reqq_queue__data_out[4U] + = ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__bypass_r) + ? vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__curr_r[4U] + : vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__head_r[4U]); + vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__core_req_arb__DOT____Vcellout__reqq_queue__data_out[5U] + = ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__bypass_r) + ? vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__curr_r[5U] + : vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__head_r[5U]); + vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__core_req_arb__DOT____Vcellout__reqq_queue__data_out[6U] + = ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__bypass_r) + ? vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__curr_r[6U] + : vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__head_r[6U]); + vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__core_req_arb__DOT____Vcellout__reqq_queue__data_out[7U] + = ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__bypass_r) + ? vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__curr_r[7U] + : vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__head_r[7U]); + vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__core_req_arb__DOT____Vcellout__reqq_queue__data_out[8U] + = ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__bypass_r) + ? vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__curr_r[8U] + : vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__head_r[8U]); + vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__core_req_arb__DOT____Vcellout__reqq_queue__data_out[9U] + = ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__bypass_r) + ? vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__curr_r[9U] + : vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__head_r[9U]); + vlTOPp->VX_cache__DOT__per_bank_core_req_ready + = ((7U & (IData)(vlTOPp->VX_cache__DOT__per_bank_core_req_ready)) + | (8U & ((~ (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__full_r)) + << 3U))); + vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__core_req_arb__DOT____Vcellout__reqq_queue__data_out[0U] + = ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__bypass_r) + ? vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__curr_r[0U] + : vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__head_r[0U]); + vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__core_req_arb__DOT____Vcellout__reqq_queue__data_out[1U] + = ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__bypass_r) + ? vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__curr_r[1U] + : vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__head_r[1U]); + vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__core_req_arb__DOT____Vcellout__reqq_queue__data_out[2U] + = ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__bypass_r) + ? vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__curr_r[2U] + : vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__head_r[2U]); + vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__core_req_arb__DOT____Vcellout__reqq_queue__data_out[3U] + = ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__bypass_r) + ? vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__curr_r[3U] + : vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__head_r[3U]); + vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__core_req_arb__DOT____Vcellout__reqq_queue__data_out[4U] + = ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__bypass_r) + ? vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__curr_r[4U] + : vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__head_r[4U]); + vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__core_req_arb__DOT____Vcellout__reqq_queue__data_out[5U] + = ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__bypass_r) + ? vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__curr_r[5U] + : vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__head_r[5U]); + vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__core_req_arb__DOT____Vcellout__reqq_queue__data_out[6U] + = ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__bypass_r) + ? vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__curr_r[6U] + : vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__head_r[6U]); + vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__core_req_arb__DOT____Vcellout__reqq_queue__data_out[7U] + = ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__bypass_r) + ? vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__curr_r[7U] + : vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__head_r[7U]); + vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__core_req_arb__DOT____Vcellout__reqq_queue__data_out[8U] + = ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__bypass_r) + ? vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__curr_r[8U] + : vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__head_r[8U]); + vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__core_req_arb__DOT____Vcellout__reqq_queue__data_out[9U] + = ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__bypass_r) + ? vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__curr_r[9U] + : vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__head_r[9U]); + vlTOPp->VX_cache__DOT__per_bank_core_req_ready + = ((0xbU & (IData)(vlTOPp->VX_cache__DOT__per_bank_core_req_ready)) + | (4U & ((~ (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__full_r)) + << 2U))); + vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__core_req_arb__DOT____Vcellout__reqq_queue__data_out[0U] + = ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__bypass_r) + ? vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__curr_r[0U] + : vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__head_r[0U]); + vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__core_req_arb__DOT____Vcellout__reqq_queue__data_out[1U] + = ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__bypass_r) + ? vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__curr_r[1U] + : vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__head_r[1U]); + vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__core_req_arb__DOT____Vcellout__reqq_queue__data_out[2U] + = ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__bypass_r) + ? vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__curr_r[2U] + : vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__head_r[2U]); + vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__core_req_arb__DOT____Vcellout__reqq_queue__data_out[3U] + = ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__bypass_r) + ? vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__curr_r[3U] + : vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__head_r[3U]); + vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__core_req_arb__DOT____Vcellout__reqq_queue__data_out[4U] + = ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__bypass_r) + ? vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__curr_r[4U] + : vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__head_r[4U]); + vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__core_req_arb__DOT____Vcellout__reqq_queue__data_out[5U] + = ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__bypass_r) + ? vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__curr_r[5U] + : vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__head_r[5U]); + vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__core_req_arb__DOT____Vcellout__reqq_queue__data_out[6U] + = ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__bypass_r) + ? vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__curr_r[6U] + : vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__head_r[6U]); + vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__core_req_arb__DOT____Vcellout__reqq_queue__data_out[7U] + = ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__bypass_r) + ? vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__curr_r[7U] + : vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__head_r[7U]); + vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__core_req_arb__DOT____Vcellout__reqq_queue__data_out[8U] + = ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__bypass_r) + ? vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__curr_r[8U] + : vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__head_r[8U]); + vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__core_req_arb__DOT____Vcellout__reqq_queue__data_out[9U] + = ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__bypass_r) + ? vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__curr_r[9U] + : vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__head_r[9U]); + vlTOPp->VX_cache__DOT__per_bank_core_req_ready + = ((0xdU & (IData)(vlTOPp->VX_cache__DOT__per_bank_core_req_ready)) + | (2U & ((~ (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__full_r)) + << 1U))); + vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__core_req_arb__DOT____Vcellout__reqq_queue__data_out[0U] + = ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__bypass_r) + ? vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__curr_r[0U] + : vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__head_r[0U]); + vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__core_req_arb__DOT____Vcellout__reqq_queue__data_out[1U] + = ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__bypass_r) + ? vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__curr_r[1U] + : vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__head_r[1U]); + vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__core_req_arb__DOT____Vcellout__reqq_queue__data_out[2U] + = ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__bypass_r) + ? vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__curr_r[2U] + : vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__head_r[2U]); + vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__core_req_arb__DOT____Vcellout__reqq_queue__data_out[3U] + = ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__bypass_r) + ? vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__curr_r[3U] + : vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__head_r[3U]); + vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__core_req_arb__DOT____Vcellout__reqq_queue__data_out[4U] + = ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__bypass_r) + ? vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__curr_r[4U] + : vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__head_r[4U]); + vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__core_req_arb__DOT____Vcellout__reqq_queue__data_out[5U] + = ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__bypass_r) + ? vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__curr_r[5U] + : vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__head_r[5U]); + vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__core_req_arb__DOT____Vcellout__reqq_queue__data_out[6U] + = ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__bypass_r) + ? vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__curr_r[6U] + : vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__head_r[6U]); + vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__core_req_arb__DOT____Vcellout__reqq_queue__data_out[7U] + = ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__bypass_r) + ? vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__curr_r[7U] + : vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__head_r[7U]); + vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__core_req_arb__DOT____Vcellout__reqq_queue__data_out[8U] + = ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__bypass_r) + ? vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__curr_r[8U] + : vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__head_r[8U]); + vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__core_req_arb__DOT____Vcellout__reqq_queue__data_out[9U] + = ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__bypass_r) + ? vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__curr_r[9U] + : vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__head_r[9U]); + vlTOPp->VX_cache__DOT__per_bank_core_req_ready + = ((0xeU & (IData)(vlTOPp->VX_cache__DOT__per_bank_core_req_ready)) + | (1U & (~ (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__full_r)))); + vlTOPp->VX_cache__DOT__cache_core_rsp_merge__DOT__sel_bank__DOT__genblk2__DOT__requests_use + = ((IData)(vlTOPp->reset) ? 0U : ((IData)(vlTOPp->VX_cache__DOT__cache_core_rsp_merge__DOT__sel_bank__DOT__genblk2__DOT__refill) + ? (IData)(vlTOPp->VX_cache__DOT__per_bank_core_rsp_valid) + : (IData)(vlTOPp->VX_cache__DOT__cache_core_rsp_merge__DOT__sel_bank__DOT__genblk2__DOT__update_value))); + vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT____Vcellout__cwb_queue__data_out[0U] + = ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cwb_queue__DOT__genblk3__DOT__genblk2__DOT__bypass_r) + ? vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cwb_queue__DOT__genblk3__DOT__genblk2__DOT__curr_r[0U] + : vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cwb_queue__DOT__genblk3__DOT__genblk2__DOT__head_r[0U]); + vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT____Vcellout__cwb_queue__data_out[1U] + = ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cwb_queue__DOT__genblk3__DOT__genblk2__DOT__bypass_r) + ? vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cwb_queue__DOT__genblk3__DOT__genblk2__DOT__curr_r[1U] + : vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cwb_queue__DOT__genblk3__DOT__genblk2__DOT__head_r[1U]); + vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT____Vcellout__cwb_queue__data_out[2U] + = ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cwb_queue__DOT__genblk3__DOT__genblk2__DOT__bypass_r) + ? vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cwb_queue__DOT__genblk3__DOT__genblk2__DOT__curr_r[2U] + : vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cwb_queue__DOT__genblk3__DOT__genblk2__DOT__head_r[2U]); + vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT____Vcellout__cwb_queue__data_out[0U] + = ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__cwb_queue__DOT__genblk3__DOT__genblk2__DOT__bypass_r) + ? vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__cwb_queue__DOT__genblk3__DOT__genblk2__DOT__curr_r[0U] + : vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__cwb_queue__DOT__genblk3__DOT__genblk2__DOT__head_r[0U]); + vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT____Vcellout__cwb_queue__data_out[1U] + = ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__cwb_queue__DOT__genblk3__DOT__genblk2__DOT__bypass_r) + ? vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__cwb_queue__DOT__genblk3__DOT__genblk2__DOT__curr_r[1U] + : vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__cwb_queue__DOT__genblk3__DOT__genblk2__DOT__head_r[1U]); + vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT____Vcellout__cwb_queue__data_out[2U] + = ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__cwb_queue__DOT__genblk3__DOT__genblk2__DOT__bypass_r) + ? vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__cwb_queue__DOT__genblk3__DOT__genblk2__DOT__curr_r[2U] + : vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__cwb_queue__DOT__genblk3__DOT__genblk2__DOT__head_r[2U]); + vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT____Vcellout__cwb_queue__data_out[0U] + = ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__cwb_queue__DOT__genblk3__DOT__genblk2__DOT__bypass_r) + ? vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__cwb_queue__DOT__genblk3__DOT__genblk2__DOT__curr_r[0U] + : vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__cwb_queue__DOT__genblk3__DOT__genblk2__DOT__head_r[0U]); + vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT____Vcellout__cwb_queue__data_out[1U] + = ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__cwb_queue__DOT__genblk3__DOT__genblk2__DOT__bypass_r) + ? vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__cwb_queue__DOT__genblk3__DOT__genblk2__DOT__curr_r[1U] + : vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__cwb_queue__DOT__genblk3__DOT__genblk2__DOT__head_r[1U]); + vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT____Vcellout__cwb_queue__data_out[2U] + = ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__cwb_queue__DOT__genblk3__DOT__genblk2__DOT__bypass_r) + ? vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__cwb_queue__DOT__genblk3__DOT__genblk2__DOT__curr_r[2U] + : vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__cwb_queue__DOT__genblk3__DOT__genblk2__DOT__head_r[2U]); + vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT____Vcellout__cwb_queue__data_out[0U] + = ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cwb_queue__DOT__genblk3__DOT__genblk2__DOT__bypass_r) + ? vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cwb_queue__DOT__genblk3__DOT__genblk2__DOT__curr_r[0U] + : vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cwb_queue__DOT__genblk3__DOT__genblk2__DOT__head_r[0U]); + vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT____Vcellout__cwb_queue__data_out[1U] + = ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cwb_queue__DOT__genblk3__DOT__genblk2__DOT__bypass_r) + ? vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cwb_queue__DOT__genblk3__DOT__genblk2__DOT__curr_r[1U] + : vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cwb_queue__DOT__genblk3__DOT__genblk2__DOT__head_r[1U]); + vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT____Vcellout__cwb_queue__data_out[2U] + = ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cwb_queue__DOT__genblk3__DOT__genblk2__DOT__bypass_r) + ? vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cwb_queue__DOT__genblk3__DOT__genblk2__DOT__curr_r[2U] + : vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cwb_queue__DOT__genblk3__DOT__genblk2__DOT__head_r[2U]); + vlTOPp->__Vtableidx8 = vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__core_req_arb__DOT__use_per_valids; + vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__core_req_arb__DOT__qual_request_index + = vlTOPp->__Vtable8_VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__core_req_arb__DOT__qual_request_index + [vlTOPp->__Vtableidx8]; + vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__core_req_arb__DOT__qual_has_request + = vlTOPp->__Vtable8_VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__core_req_arb__DOT__qual_has_request + [vlTOPp->__Vtableidx8]; + vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__core_req_arb__DOT__sel_bank__DOT__genblk2__DOT__priority_encoder__DOT__i + = vlTOPp->__Vtable8_VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__core_req_arb__DOT__sel_bank__DOT__genblk2__DOT__priority_encoder__DOT__i + [vlTOPp->__Vtableidx8]; + vlTOPp->__Vtableidx7 = vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__core_req_arb__DOT__use_per_valids; + vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__core_req_arb__DOT__qual_request_index + = vlTOPp->__Vtable7_VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__core_req_arb__DOT__qual_request_index + [vlTOPp->__Vtableidx7]; + vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__core_req_arb__DOT__qual_has_request + = vlTOPp->__Vtable7_VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__core_req_arb__DOT__qual_has_request + [vlTOPp->__Vtableidx7]; + vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__core_req_arb__DOT__sel_bank__DOT__genblk2__DOT__priority_encoder__DOT__i + = vlTOPp->__Vtable7_VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__core_req_arb__DOT__sel_bank__DOT__genblk2__DOT__priority_encoder__DOT__i + [vlTOPp->__Vtableidx7]; + vlTOPp->__Vtableidx6 = vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__core_req_arb__DOT__use_per_valids; + vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__core_req_arb__DOT__qual_request_index + = vlTOPp->__Vtable6_VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__core_req_arb__DOT__qual_request_index + [vlTOPp->__Vtableidx6]; + vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__core_req_arb__DOT__qual_has_request + = vlTOPp->__Vtable6_VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__core_req_arb__DOT__qual_has_request + [vlTOPp->__Vtableidx6]; + vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__core_req_arb__DOT__sel_bank__DOT__genblk2__DOT__priority_encoder__DOT__i + = vlTOPp->__Vtable6_VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__core_req_arb__DOT__sel_bank__DOT__genblk2__DOT__priority_encoder__DOT__i + [vlTOPp->__Vtableidx6]; + vlTOPp->__Vtableidx5 = vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__core_req_arb__DOT__use_per_valids; + vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__core_req_arb__DOT__qual_request_index + = vlTOPp->__Vtable5_VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__core_req_arb__DOT__qual_request_index + [vlTOPp->__Vtableidx5]; + vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__core_req_arb__DOT__qual_has_request + = vlTOPp->__Vtable5_VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__core_req_arb__DOT__qual_has_request + [vlTOPp->__Vtableidx5]; + vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__core_req_arb__DOT__sel_bank__DOT__genblk2__DOT__priority_encoder__DOT__i + = vlTOPp->__Vtable5_VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__core_req_arb__DOT__sel_bank__DOT__genblk2__DOT__priority_encoder__DOT__i + [vlTOPp->__Vtableidx5]; + vlTOPp->VX_cache__DOT__per_bank_dram_fill_rsp_ready + = ((7U & (IData)(vlTOPp->VX_cache__DOT__per_bank_dram_fill_rsp_ready)) + | (8U & ((~ (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__dfp_queue__DOT__genblk3__DOT__genblk2__DOT__full_r)) + << 3U))); + vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT____Vcellout__dfp_queue__data_out[0U] + = ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__dfp_queue__DOT__genblk3__DOT__genblk2__DOT__bypass_r) + ? vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__dfp_queue__DOT__genblk3__DOT__genblk2__DOT__curr_r[0U] + : vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__dfp_queue__DOT__genblk3__DOT__genblk2__DOT__head_r[0U]); + vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT____Vcellout__dfp_queue__data_out[1U] + = ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__dfp_queue__DOT__genblk3__DOT__genblk2__DOT__bypass_r) + ? vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__dfp_queue__DOT__genblk3__DOT__genblk2__DOT__curr_r[1U] + : vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__dfp_queue__DOT__genblk3__DOT__genblk2__DOT__head_r[1U]); + vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT____Vcellout__dfp_queue__data_out[2U] + = ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__dfp_queue__DOT__genblk3__DOT__genblk2__DOT__bypass_r) + ? vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__dfp_queue__DOT__genblk3__DOT__genblk2__DOT__curr_r[2U] + : vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__dfp_queue__DOT__genblk3__DOT__genblk2__DOT__head_r[2U]); + vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT____Vcellout__dfp_queue__data_out[3U] + = ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__dfp_queue__DOT__genblk3__DOT__genblk2__DOT__bypass_r) + ? vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__dfp_queue__DOT__genblk3__DOT__genblk2__DOT__curr_r[3U] + : vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__dfp_queue__DOT__genblk3__DOT__genblk2__DOT__head_r[3U]); + vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT____Vcellout__dfp_queue__data_out[4U] + = ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__dfp_queue__DOT__genblk3__DOT__genblk2__DOT__bypass_r) + ? vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__dfp_queue__DOT__genblk3__DOT__genblk2__DOT__curr_r[4U] + : vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__dfp_queue__DOT__genblk3__DOT__genblk2__DOT__head_r[4U]); + vlTOPp->VX_cache__DOT__per_bank_dram_fill_rsp_ready + = ((0xbU & (IData)(vlTOPp->VX_cache__DOT__per_bank_dram_fill_rsp_ready)) + | (4U & ((~ (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__dfp_queue__DOT__genblk3__DOT__genblk2__DOT__full_r)) + << 2U))); + vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT____Vcellout__dfp_queue__data_out[0U] + = ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__dfp_queue__DOT__genblk3__DOT__genblk2__DOT__bypass_r) + ? vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__dfp_queue__DOT__genblk3__DOT__genblk2__DOT__curr_r[0U] + : vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__dfp_queue__DOT__genblk3__DOT__genblk2__DOT__head_r[0U]); + vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT____Vcellout__dfp_queue__data_out[1U] + = ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__dfp_queue__DOT__genblk3__DOT__genblk2__DOT__bypass_r) + ? vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__dfp_queue__DOT__genblk3__DOT__genblk2__DOT__curr_r[1U] + : vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__dfp_queue__DOT__genblk3__DOT__genblk2__DOT__head_r[1U]); + vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT____Vcellout__dfp_queue__data_out[2U] + = ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__dfp_queue__DOT__genblk3__DOT__genblk2__DOT__bypass_r) + ? vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__dfp_queue__DOT__genblk3__DOT__genblk2__DOT__curr_r[2U] + : vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__dfp_queue__DOT__genblk3__DOT__genblk2__DOT__head_r[2U]); + vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT____Vcellout__dfp_queue__data_out[3U] + = ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__dfp_queue__DOT__genblk3__DOT__genblk2__DOT__bypass_r) + ? vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__dfp_queue__DOT__genblk3__DOT__genblk2__DOT__curr_r[3U] + : vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__dfp_queue__DOT__genblk3__DOT__genblk2__DOT__head_r[3U]); + vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT____Vcellout__dfp_queue__data_out[4U] + = ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__dfp_queue__DOT__genblk3__DOT__genblk2__DOT__bypass_r) + ? vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__dfp_queue__DOT__genblk3__DOT__genblk2__DOT__curr_r[4U] + : vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__dfp_queue__DOT__genblk3__DOT__genblk2__DOT__head_r[4U]); + vlTOPp->VX_cache__DOT__per_bank_dram_fill_rsp_ready + = ((0xdU & (IData)(vlTOPp->VX_cache__DOT__per_bank_dram_fill_rsp_ready)) + | (2U & ((~ (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__dfp_queue__DOT__genblk3__DOT__genblk2__DOT__full_r)) + << 1U))); + vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT____Vcellout__dfp_queue__data_out[0U] + = ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__dfp_queue__DOT__genblk3__DOT__genblk2__DOT__bypass_r) + ? vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__dfp_queue__DOT__genblk3__DOT__genblk2__DOT__curr_r[0U] + : vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__dfp_queue__DOT__genblk3__DOT__genblk2__DOT__head_r[0U]); + vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT____Vcellout__dfp_queue__data_out[1U] + = ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__dfp_queue__DOT__genblk3__DOT__genblk2__DOT__bypass_r) + ? vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__dfp_queue__DOT__genblk3__DOT__genblk2__DOT__curr_r[1U] + : vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__dfp_queue__DOT__genblk3__DOT__genblk2__DOT__head_r[1U]); + vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT____Vcellout__dfp_queue__data_out[2U] + = ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__dfp_queue__DOT__genblk3__DOT__genblk2__DOT__bypass_r) + ? vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__dfp_queue__DOT__genblk3__DOT__genblk2__DOT__curr_r[2U] + : vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__dfp_queue__DOT__genblk3__DOT__genblk2__DOT__head_r[2U]); + vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT____Vcellout__dfp_queue__data_out[3U] + = ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__dfp_queue__DOT__genblk3__DOT__genblk2__DOT__bypass_r) + ? vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__dfp_queue__DOT__genblk3__DOT__genblk2__DOT__curr_r[3U] + : vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__dfp_queue__DOT__genblk3__DOT__genblk2__DOT__head_r[3U]); + vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT____Vcellout__dfp_queue__data_out[4U] + = ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__dfp_queue__DOT__genblk3__DOT__genblk2__DOT__bypass_r) + ? vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__dfp_queue__DOT__genblk3__DOT__genblk2__DOT__curr_r[4U] + : vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__dfp_queue__DOT__genblk3__DOT__genblk2__DOT__head_r[4U]); + vlTOPp->VX_cache__DOT__per_bank_dram_fill_rsp_ready + = ((0xeU & (IData)(vlTOPp->VX_cache__DOT__per_bank_dram_fill_rsp_ready)) + | (1U & (~ (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__dfp_queue__DOT__genblk3__DOT__genblk2__DOT__full_r)))); + vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT____Vcellout__dfp_queue__data_out[0U] + = ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__dfp_queue__DOT__genblk3__DOT__genblk2__DOT__bypass_r) + ? vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__dfp_queue__DOT__genblk3__DOT__genblk2__DOT__curr_r[0U] + : vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__dfp_queue__DOT__genblk3__DOT__genblk2__DOT__head_r[0U]); + vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT____Vcellout__dfp_queue__data_out[1U] + = ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__dfp_queue__DOT__genblk3__DOT__genblk2__DOT__bypass_r) + ? vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__dfp_queue__DOT__genblk3__DOT__genblk2__DOT__curr_r[1U] + : vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__dfp_queue__DOT__genblk3__DOT__genblk2__DOT__head_r[1U]); + vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT____Vcellout__dfp_queue__data_out[2U] + = ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__dfp_queue__DOT__genblk3__DOT__genblk2__DOT__bypass_r) + ? vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__dfp_queue__DOT__genblk3__DOT__genblk2__DOT__curr_r[2U] + : vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__dfp_queue__DOT__genblk3__DOT__genblk2__DOT__head_r[2U]); + vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT____Vcellout__dfp_queue__data_out[3U] + = ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__dfp_queue__DOT__genblk3__DOT__genblk2__DOT__bypass_r) + ? vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__dfp_queue__DOT__genblk3__DOT__genblk2__DOT__curr_r[3U] + : vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__dfp_queue__DOT__genblk3__DOT__genblk2__DOT__head_r[3U]); + vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT____Vcellout__dfp_queue__data_out[4U] + = ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__dfp_queue__DOT__genblk3__DOT__genblk2__DOT__bypass_r) + ? vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__dfp_queue__DOT__genblk3__DOT__genblk2__DOT__curr_r[4U] + : vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__dfp_queue__DOT__genblk3__DOT__genblk2__DOT__head_r[4U]); + vlTOPp->VX_cache__DOT__cache_dram_req_arb__DOT__dram_fill_arb__DOT____Vcellout__dfqq_queue__data_out[0U] + = ((IData)(vlTOPp->VX_cache__DOT__cache_dram_req_arb__DOT__dram_fill_arb__DOT__dfqq_queue__DOT__genblk3__DOT__genblk2__DOT__bypass_r) + ? vlTOPp->VX_cache__DOT__cache_dram_req_arb__DOT__dram_fill_arb__DOT__dfqq_queue__DOT__genblk3__DOT__genblk2__DOT__curr_r[0U] + : vlTOPp->VX_cache__DOT__cache_dram_req_arb__DOT__dram_fill_arb__DOT__dfqq_queue__DOT__genblk3__DOT__genblk2__DOT__head_r[0U]); + vlTOPp->VX_cache__DOT__cache_dram_req_arb__DOT__dram_fill_arb__DOT____Vcellout__dfqq_queue__data_out[1U] + = ((IData)(vlTOPp->VX_cache__DOT__cache_dram_req_arb__DOT__dram_fill_arb__DOT__dfqq_queue__DOT__genblk3__DOT__genblk2__DOT__bypass_r) + ? vlTOPp->VX_cache__DOT__cache_dram_req_arb__DOT__dram_fill_arb__DOT__dfqq_queue__DOT__genblk3__DOT__genblk2__DOT__curr_r[1U] + : vlTOPp->VX_cache__DOT__cache_dram_req_arb__DOT__dram_fill_arb__DOT__dfqq_queue__DOT__genblk3__DOT__genblk2__DOT__head_r[1U]); + vlTOPp->VX_cache__DOT__cache_dram_req_arb__DOT__dram_fill_arb__DOT____Vcellout__dfqq_queue__data_out[2U] + = ((IData)(vlTOPp->VX_cache__DOT__cache_dram_req_arb__DOT__dram_fill_arb__DOT__dfqq_queue__DOT__genblk3__DOT__genblk2__DOT__bypass_r) + ? vlTOPp->VX_cache__DOT__cache_dram_req_arb__DOT__dram_fill_arb__DOT__dfqq_queue__DOT__genblk3__DOT__genblk2__DOT__curr_r[2U] + : vlTOPp->VX_cache__DOT__cache_dram_req_arb__DOT__dram_fill_arb__DOT__dfqq_queue__DOT__genblk3__DOT__genblk2__DOT__head_r[2U]); + vlTOPp->VX_cache__DOT__cache_dram_req_arb__DOT__dram_fill_arb__DOT____Vcellout__dfqq_queue__data_out[3U] + = ((IData)(vlTOPp->VX_cache__DOT__cache_dram_req_arb__DOT__dram_fill_arb__DOT__dfqq_queue__DOT__genblk3__DOT__genblk2__DOT__bypass_r) + ? vlTOPp->VX_cache__DOT__cache_dram_req_arb__DOT__dram_fill_arb__DOT__dfqq_queue__DOT__genblk3__DOT__genblk2__DOT__curr_r[3U] + : vlTOPp->VX_cache__DOT__cache_dram_req_arb__DOT__dram_fill_arb__DOT__dfqq_queue__DOT__genblk3__DOT__genblk2__DOT__head_r[3U]); + vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT____Vcellout__dwb_queue__data_out[0U] + = ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__genblk2__DOT__bypass_r) + ? vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__genblk2__DOT__curr_r[0U] + : vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__genblk2__DOT__head_r[0U]); + vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT____Vcellout__dwb_queue__data_out[1U] + = ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__genblk2__DOT__bypass_r) + ? vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__genblk2__DOT__curr_r[1U] + : vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__genblk2__DOT__head_r[1U]); + vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT____Vcellout__dwb_queue__data_out[2U] + = ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__genblk2__DOT__bypass_r) + ? vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__genblk2__DOT__curr_r[2U] + : vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__genblk2__DOT__head_r[2U]); + vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT____Vcellout__dwb_queue__data_out[3U] + = ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__genblk2__DOT__bypass_r) + ? vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__genblk2__DOT__curr_r[3U] + : vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__genblk2__DOT__head_r[3U]); + vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT____Vcellout__dwb_queue__data_out[4U] + = ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__genblk2__DOT__bypass_r) + ? vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__genblk2__DOT__curr_r[4U] + : vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__genblk2__DOT__head_r[4U]); + vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT____Vcellout__dwb_queue__data_out[5U] + = ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__genblk2__DOT__bypass_r) + ? vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__genblk2__DOT__curr_r[5U] + : vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__genblk2__DOT__head_r[5U]); + vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT____Vcellout__dwb_queue__data_out[6U] + = ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__genblk2__DOT__bypass_r) + ? vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__genblk2__DOT__curr_r[6U] + : vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__genblk2__DOT__head_r[6U]); + vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT____Vcellout__dwb_queue__data_out[0U] + = ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__genblk2__DOT__bypass_r) + ? vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__genblk2__DOT__curr_r[0U] + : vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__genblk2__DOT__head_r[0U]); + vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT____Vcellout__dwb_queue__data_out[1U] + = ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__genblk2__DOT__bypass_r) + ? vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__genblk2__DOT__curr_r[1U] + : vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__genblk2__DOT__head_r[1U]); + vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT____Vcellout__dwb_queue__data_out[2U] + = ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__genblk2__DOT__bypass_r) + ? vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__genblk2__DOT__curr_r[2U] + : vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__genblk2__DOT__head_r[2U]); + vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT____Vcellout__dwb_queue__data_out[3U] + = ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__genblk2__DOT__bypass_r) + ? vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__genblk2__DOT__curr_r[3U] + : vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__genblk2__DOT__head_r[3U]); + vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT____Vcellout__dwb_queue__data_out[4U] + = ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__genblk2__DOT__bypass_r) + ? vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__genblk2__DOT__curr_r[4U] + : vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__genblk2__DOT__head_r[4U]); + vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT____Vcellout__dwb_queue__data_out[5U] + = ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__genblk2__DOT__bypass_r) + ? vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__genblk2__DOT__curr_r[5U] + : vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__genblk2__DOT__head_r[5U]); + vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT____Vcellout__dwb_queue__data_out[6U] + = ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__genblk2__DOT__bypass_r) + ? vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__genblk2__DOT__curr_r[6U] + : vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__genblk2__DOT__head_r[6U]); + vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT____Vcellout__dwb_queue__data_out[0U] + = ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__genblk2__DOT__bypass_r) + ? vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__genblk2__DOT__curr_r[0U] + : vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__genblk2__DOT__head_r[0U]); + vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT____Vcellout__dwb_queue__data_out[1U] + = ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__genblk2__DOT__bypass_r) + ? vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__genblk2__DOT__curr_r[1U] + : vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__genblk2__DOT__head_r[1U]); + vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT____Vcellout__dwb_queue__data_out[2U] + = ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__genblk2__DOT__bypass_r) + ? vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__genblk2__DOT__curr_r[2U] + : vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__genblk2__DOT__head_r[2U]); + vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT____Vcellout__dwb_queue__data_out[3U] + = ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__genblk2__DOT__bypass_r) + ? vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__genblk2__DOT__curr_r[3U] + : vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__genblk2__DOT__head_r[3U]); + vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT____Vcellout__dwb_queue__data_out[4U] + = ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__genblk2__DOT__bypass_r) + ? vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__genblk2__DOT__curr_r[4U] + : vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__genblk2__DOT__head_r[4U]); + vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT____Vcellout__dwb_queue__data_out[5U] + = ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__genblk2__DOT__bypass_r) + ? vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__genblk2__DOT__curr_r[5U] + : vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__genblk2__DOT__head_r[5U]); + vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT____Vcellout__dwb_queue__data_out[6U] + = ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__genblk2__DOT__bypass_r) + ? vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__genblk2__DOT__curr_r[6U] + : vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__genblk2__DOT__head_r[6U]); + vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT____Vcellout__dwb_queue__data_out[0U] + = ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__genblk2__DOT__bypass_r) + ? vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__genblk2__DOT__curr_r[0U] + : vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__genblk2__DOT__head_r[0U]); + vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT____Vcellout__dwb_queue__data_out[1U] + = ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__genblk2__DOT__bypass_r) + ? vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__genblk2__DOT__curr_r[1U] + : vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__genblk2__DOT__head_r[1U]); + vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT____Vcellout__dwb_queue__data_out[2U] + = ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__genblk2__DOT__bypass_r) + ? vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__genblk2__DOT__curr_r[2U] + : vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__genblk2__DOT__head_r[2U]); + vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT____Vcellout__dwb_queue__data_out[3U] + = ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__genblk2__DOT__bypass_r) + ? vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__genblk2__DOT__curr_r[3U] + : vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__genblk2__DOT__head_r[3U]); + vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT____Vcellout__dwb_queue__data_out[4U] + = ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__genblk2__DOT__bypass_r) + ? vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__genblk2__DOT__curr_r[4U] + : vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__genblk2__DOT__head_r[4U]); + vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT____Vcellout__dwb_queue__data_out[5U] + = ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__genblk2__DOT__bypass_r) + ? vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__genblk2__DOT__curr_r[5U] + : vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__genblk2__DOT__head_r[5U]); + vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT____Vcellout__dwb_queue__data_out[6U] + = ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__genblk2__DOT__bypass_r) + ? vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__genblk2__DOT__curr_r[6U] + : vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__genblk2__DOT__head_r[6U]); + vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__mrvq_rw_st0 + = (1U & (vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cache_miss_resrv__DOT__metadata_table + [vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr][0U] + >> 8U)); + vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__mrvq_rw_st0 + = (1U & (vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__cache_miss_resrv__DOT__metadata_table + [vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr][0U] + >> 8U)); + vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__mrvq_rw_st0 + = (1U & (vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__cache_miss_resrv__DOT__metadata_table + [vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr][0U] + >> 8U)); + vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__mrvq_rw_st0 + = (1U & (vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cache_miss_resrv__DOT__metadata_table + [vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr][0U] + >> 8U)); + vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cache_miss_resrv__DOT__dequeue_possible + = (1U & (((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cache_miss_resrv__DOT__valid_table) + & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cache_miss_resrv__DOT__ready_table)) + >> (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr))); + vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__cache_miss_resrv__DOT__dequeue_possible + = (1U & (((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__cache_miss_resrv__DOT__valid_table) + & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__cache_miss_resrv__DOT__ready_table)) + >> (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr))); + vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__cache_miss_resrv__DOT__dequeue_possible + = (1U & (((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__cache_miss_resrv__DOT__valid_table) + & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__cache_miss_resrv__DOT__ready_table)) + >> (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr))); + vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cache_miss_resrv__DOT__dequeue_possible + = (1U & (((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cache_miss_resrv__DOT__valid_table) + & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cache_miss_resrv__DOT__ready_table)) + >> (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr))); + if (vlTOPp->reset) { + vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__st_1e_2__DOT__value[0U] = 0U; + vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__st_1e_2__DOT__value[1U] = 0U; + vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__st_1e_2__DOT__value[2U] = 0U; + vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__st_1e_2__DOT__value[3U] = 0U; + vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__st_1e_2__DOT__value[4U] = 0U; + vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__st_1e_2__DOT__value[5U] = 0U; + vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__st_1e_2__DOT__value[6U] = 0U; + vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__st_1e_2__DOT__value[7U] = 0U; + vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__st_1e_2__DOT__value[8U] = 0U; + vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__st_1e_2__DOT__value[9U] = 0U; + } else { + if ((1U & (~ (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__stall_bank_pipe)))) { + vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__st_1e_2__DOT__value[0U] + = vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT____Vcellinp__st_1e_2__in[0U]; + vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__st_1e_2__DOT__value[1U] + = vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT____Vcellinp__st_1e_2__in[1U]; + vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__st_1e_2__DOT__value[2U] + = vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT____Vcellinp__st_1e_2__in[2U]; + vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__st_1e_2__DOT__value[3U] + = vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT____Vcellinp__st_1e_2__in[3U]; + vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__st_1e_2__DOT__value[4U] + = vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT____Vcellinp__st_1e_2__in[4U]; + vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__st_1e_2__DOT__value[5U] + = vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT____Vcellinp__st_1e_2__in[5U]; + vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__st_1e_2__DOT__value[6U] + = vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT____Vcellinp__st_1e_2__in[6U]; + vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__st_1e_2__DOT__value[7U] + = vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT____Vcellinp__st_1e_2__in[7U]; + vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__st_1e_2__DOT__value[8U] + = vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT____Vcellinp__st_1e_2__in[8U]; + vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__st_1e_2__DOT__value[9U] + = vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT____Vcellinp__st_1e_2__in[9U]; + } + } + if (vlTOPp->reset) { + vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__st_1e_2__DOT__value[0U] = 0U; + vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__st_1e_2__DOT__value[1U] = 0U; + vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__st_1e_2__DOT__value[2U] = 0U; + vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__st_1e_2__DOT__value[3U] = 0U; + vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__st_1e_2__DOT__value[4U] = 0U; + vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__st_1e_2__DOT__value[5U] = 0U; + vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__st_1e_2__DOT__value[6U] = 0U; + vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__st_1e_2__DOT__value[7U] = 0U; + vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__st_1e_2__DOT__value[8U] = 0U; + vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__st_1e_2__DOT__value[9U] = 0U; + } else { + if ((1U & (~ (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__stall_bank_pipe)))) { + vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__st_1e_2__DOT__value[0U] + = vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT____Vcellinp__st_1e_2__in[0U]; + vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__st_1e_2__DOT__value[1U] + = vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT____Vcellinp__st_1e_2__in[1U]; + vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__st_1e_2__DOT__value[2U] + = vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT____Vcellinp__st_1e_2__in[2U]; + vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__st_1e_2__DOT__value[3U] + = vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT____Vcellinp__st_1e_2__in[3U]; + vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__st_1e_2__DOT__value[4U] + = vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT____Vcellinp__st_1e_2__in[4U]; + vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__st_1e_2__DOT__value[5U] + = vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT____Vcellinp__st_1e_2__in[5U]; + vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__st_1e_2__DOT__value[6U] + = vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT____Vcellinp__st_1e_2__in[6U]; + vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__st_1e_2__DOT__value[7U] + = vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT____Vcellinp__st_1e_2__in[7U]; + vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__st_1e_2__DOT__value[8U] + = vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT____Vcellinp__st_1e_2__in[8U]; + vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__st_1e_2__DOT__value[9U] + = vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT____Vcellinp__st_1e_2__in[9U]; + } + } + if (vlTOPp->reset) { + vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__st_1e_2__DOT__value[0U] = 0U; + vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__st_1e_2__DOT__value[1U] = 0U; + vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__st_1e_2__DOT__value[2U] = 0U; + vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__st_1e_2__DOT__value[3U] = 0U; + vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__st_1e_2__DOT__value[4U] = 0U; + vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__st_1e_2__DOT__value[5U] = 0U; + vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__st_1e_2__DOT__value[6U] = 0U; + vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__st_1e_2__DOT__value[7U] = 0U; + vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__st_1e_2__DOT__value[8U] = 0U; + vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__st_1e_2__DOT__value[9U] = 0U; + } else { + if ((1U & (~ (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__stall_bank_pipe)))) { + vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__st_1e_2__DOT__value[0U] + = vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT____Vcellinp__st_1e_2__in[0U]; + vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__st_1e_2__DOT__value[1U] + = vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT____Vcellinp__st_1e_2__in[1U]; + vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__st_1e_2__DOT__value[2U] + = vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT____Vcellinp__st_1e_2__in[2U]; + vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__st_1e_2__DOT__value[3U] + = vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT____Vcellinp__st_1e_2__in[3U]; + vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__st_1e_2__DOT__value[4U] + = vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT____Vcellinp__st_1e_2__in[4U]; + vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__st_1e_2__DOT__value[5U] + = vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT____Vcellinp__st_1e_2__in[5U]; + vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__st_1e_2__DOT__value[6U] + = vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT____Vcellinp__st_1e_2__in[6U]; + vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__st_1e_2__DOT__value[7U] + = vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT____Vcellinp__st_1e_2__in[7U]; + vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__st_1e_2__DOT__value[8U] + = vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT____Vcellinp__st_1e_2__in[8U]; + vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__st_1e_2__DOT__value[9U] + = vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT____Vcellinp__st_1e_2__in[9U]; + } + } + if (vlTOPp->reset) { + vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__st_1e_2__DOT__value[0U] = 0U; + vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__st_1e_2__DOT__value[1U] = 0U; + vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__st_1e_2__DOT__value[2U] = 0U; + vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__st_1e_2__DOT__value[3U] = 0U; + vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__st_1e_2__DOT__value[4U] = 0U; + vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__st_1e_2__DOT__value[5U] = 0U; + vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__st_1e_2__DOT__value[6U] = 0U; + vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__st_1e_2__DOT__value[7U] = 0U; + vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__st_1e_2__DOT__value[8U] = 0U; + vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__st_1e_2__DOT__value[9U] = 0U; + } else { + if ((1U & (~ (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__stall_bank_pipe)))) { + vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__st_1e_2__DOT__value[0U] + = vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT____Vcellinp__st_1e_2__in[0U]; + vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__st_1e_2__DOT__value[1U] + = vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT____Vcellinp__st_1e_2__in[1U]; + vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__st_1e_2__DOT__value[2U] + = vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT____Vcellinp__st_1e_2__in[2U]; + vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__st_1e_2__DOT__value[3U] + = vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT____Vcellinp__st_1e_2__in[3U]; + vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__st_1e_2__DOT__value[4U] + = vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT____Vcellinp__st_1e_2__in[4U]; + vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__st_1e_2__DOT__value[5U] + = vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT____Vcellinp__st_1e_2__in[5U]; + vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__st_1e_2__DOT__value[6U] + = vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT____Vcellinp__st_1e_2__in[6U]; + vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__st_1e_2__DOT__value[7U] + = vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT____Vcellinp__st_1e_2__in[7U]; + vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__st_1e_2__DOT__value[8U] + = vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT____Vcellinp__st_1e_2__in[8U]; + vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__st_1e_2__DOT__value[9U] + = vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT____Vcellinp__st_1e_2__in[9U]; + } + } + vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__going_to_write_st1[0U] + = (1U & (vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__s0_1_c0__DOT__value[7U] + >> 0xfU)); + vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__writedata_st1[0U][0U] + = vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__s0_1_c0__DOT__value[0U]; + vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__writedata_st1[0U][1U] + = vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__s0_1_c0__DOT__value[1U]; + vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__writedata_st1[0U][2U] + = vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__s0_1_c0__DOT__value[2U]; + vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__writedata_st1[0U][3U] + = vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__s0_1_c0__DOT__value[3U]; + vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__writeword_st1[0U] + = ((vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__s0_1_c0__DOT__value[6U] + << 0xeU) | (vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__s0_1_c0__DOT__value[5U] + >> 0x12U)); + vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__wsel_st1[0U] + = (3U & ((vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__s0_1_c0__DOT__value[7U] + << 0xeU) | (vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__s0_1_c0__DOT__value[6U] + >> 0x12U))); + vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__inst_meta_st1[0U] + = (VL_ULL(0x1ffffffffffff) & (((QData)((IData)( + vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__s0_1_c0__DOT__value[6U])) + << 0x3fU) | + (((QData)((IData)( + vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__s0_1_c0__DOT__value[5U])) + << 0x1fU) | + ((QData)((IData)( + vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__s0_1_c0__DOT__value[4U])) + >> 1U)))); + vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__snp_invalidate_st1[0U] + = (1U & (vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__s0_1_c0__DOT__value[7U] + >> 0x10U)); + vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__is_snp_st1[0U] + = (1U & (vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__s0_1_c0__DOT__value[7U] + >> 0x11U)); + vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__is_mrvq_st1[0U] + = (1U & (vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__s0_1_c0__DOT__value[7U] + >> 0x12U)); + vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__is_fill_st1[0U] + = (1U & vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__s0_1_c0__DOT__value[4U]); + vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__valid_st1[0U] + = (1U & (vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__s0_1_c0__DOT__value[7U] + >> 0xeU)); + vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__addr_st1[0U] + = (0x3ffffffU & ((vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__s0_1_c0__DOT__value[7U] + << 0xcU) | (vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__s0_1_c0__DOT__value[6U] + >> 0x14U))); + vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__going_to_write_st1[0U] + = (1U & (vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__s0_1_c0__DOT__value[7U] + >> 0xfU)); + vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__writedata_st1[0U][0U] + = vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__s0_1_c0__DOT__value[0U]; + vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__writedata_st1[0U][1U] + = vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__s0_1_c0__DOT__value[1U]; + vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__writedata_st1[0U][2U] + = vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__s0_1_c0__DOT__value[2U]; + vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__writedata_st1[0U][3U] + = vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__s0_1_c0__DOT__value[3U]; + vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__writeword_st1[0U] + = ((vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__s0_1_c0__DOT__value[6U] + << 0xeU) | (vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__s0_1_c0__DOT__value[5U] + >> 0x12U)); + vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__wsel_st1[0U] + = (3U & ((vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__s0_1_c0__DOT__value[7U] + << 0xeU) | (vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__s0_1_c0__DOT__value[6U] + >> 0x12U))); + vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__inst_meta_st1[0U] + = (VL_ULL(0x1ffffffffffff) & (((QData)((IData)( + vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__s0_1_c0__DOT__value[6U])) + << 0x3fU) | + (((QData)((IData)( + vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__s0_1_c0__DOT__value[5U])) + << 0x1fU) | + ((QData)((IData)( + vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__s0_1_c0__DOT__value[4U])) + >> 1U)))); + vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__snp_invalidate_st1[0U] + = (1U & (vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__s0_1_c0__DOT__value[7U] + >> 0x10U)); + vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__is_snp_st1[0U] + = (1U & (vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__s0_1_c0__DOT__value[7U] + >> 0x11U)); + vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__is_mrvq_st1[0U] + = (1U & (vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__s0_1_c0__DOT__value[7U] + >> 0x12U)); + vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__is_fill_st1[0U] + = (1U & vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__s0_1_c0__DOT__value[4U]); + vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__valid_st1[0U] + = (1U & (vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__s0_1_c0__DOT__value[7U] + >> 0xeU)); + vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__addr_st1[0U] + = (0x3ffffffU & ((vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__s0_1_c0__DOT__value[7U] + << 0xcU) | (vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__s0_1_c0__DOT__value[6U] + >> 0x14U))); + vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__going_to_write_st1[0U] + = (1U & (vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__s0_1_c0__DOT__value[7U] + >> 0xfU)); + vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__writedata_st1[0U][0U] + = vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__s0_1_c0__DOT__value[0U]; + vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__writedata_st1[0U][1U] + = vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__s0_1_c0__DOT__value[1U]; + vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__writedata_st1[0U][2U] + = vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__s0_1_c0__DOT__value[2U]; + vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__writedata_st1[0U][3U] + = vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__s0_1_c0__DOT__value[3U]; + vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__writeword_st1[0U] + = ((vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__s0_1_c0__DOT__value[6U] + << 0xeU) | (vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__s0_1_c0__DOT__value[5U] + >> 0x12U)); + vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__wsel_st1[0U] + = (3U & ((vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__s0_1_c0__DOT__value[7U] + << 0xeU) | (vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__s0_1_c0__DOT__value[6U] + >> 0x12U))); + vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__inst_meta_st1[0U] + = (VL_ULL(0x1ffffffffffff) & (((QData)((IData)( + vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__s0_1_c0__DOT__value[6U])) + << 0x3fU) | + (((QData)((IData)( + vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__s0_1_c0__DOT__value[5U])) + << 0x1fU) | + ((QData)((IData)( + vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__s0_1_c0__DOT__value[4U])) + >> 1U)))); + vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__snp_invalidate_st1[0U] + = (1U & (vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__s0_1_c0__DOT__value[7U] + >> 0x10U)); + vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__is_snp_st1[0U] + = (1U & (vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__s0_1_c0__DOT__value[7U] + >> 0x11U)); + vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__is_mrvq_st1[0U] + = (1U & (vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__s0_1_c0__DOT__value[7U] + >> 0x12U)); + vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__is_fill_st1[0U] + = (1U & vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__s0_1_c0__DOT__value[4U]); + vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__valid_st1[0U] + = (1U & (vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__s0_1_c0__DOT__value[7U] + >> 0xeU)); + vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__addr_st1[0U] + = (0x3ffffffU & ((vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__s0_1_c0__DOT__value[7U] + << 0xcU) | (vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__s0_1_c0__DOT__value[6U] + >> 0x14U))); + vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__going_to_write_st1[0U] + = (1U & (vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__s0_1_c0__DOT__value[7U] + >> 0xfU)); + vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__writedata_st1[0U][0U] + = vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__s0_1_c0__DOT__value[0U]; + vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__writedata_st1[0U][1U] + = vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__s0_1_c0__DOT__value[1U]; + vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__writedata_st1[0U][2U] + = vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__s0_1_c0__DOT__value[2U]; + vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__writedata_st1[0U][3U] + = vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__s0_1_c0__DOT__value[3U]; + vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__writeword_st1[0U] + = ((vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__s0_1_c0__DOT__value[6U] + << 0xeU) | (vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__s0_1_c0__DOT__value[5U] + >> 0x12U)); + vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__wsel_st1[0U] + = (3U & ((vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__s0_1_c0__DOT__value[7U] + << 0xeU) | (vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__s0_1_c0__DOT__value[6U] + >> 0x12U))); + vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__inst_meta_st1[0U] + = (VL_ULL(0x1ffffffffffff) & (((QData)((IData)( + vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__s0_1_c0__DOT__value[6U])) + << 0x3fU) | + (((QData)((IData)( + vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__s0_1_c0__DOT__value[5U])) + << 0x1fU) | + ((QData)((IData)( + vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__s0_1_c0__DOT__value[4U])) + >> 1U)))); + vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__snp_invalidate_st1[0U] + = (1U & (vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__s0_1_c0__DOT__value[7U] + >> 0x10U)); + vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__is_snp_st1[0U] + = (1U & (vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__s0_1_c0__DOT__value[7U] + >> 0x11U)); + vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__is_mrvq_st1[0U] + = (1U & (vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__s0_1_c0__DOT__value[7U] + >> 0x12U)); + vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__is_fill_st1[0U] + = (1U & vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__s0_1_c0__DOT__value[4U]); + vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__valid_st1[0U] + = (1U & (vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__s0_1_c0__DOT__value[7U] + >> 0xeU)); + vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__addr_st1[0U] + = (0x3ffffffU & ((vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__s0_1_c0__DOT__value[7U] + << 0xcU) | (vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__s0_1_c0__DOT__value[6U] + >> 0x14U))); + vlTOPp->VX_cache__DOT__cache_dram_req_arb__DOT__prfqq__DOT__pfq_queue__DOT__reading + = ((IData)(vlTOPp->VX_cache__DOT__cache_dram_req_arb__DOT__prfqq__DOT__update_use) + & (IData)(vlTOPp->VX_cache__DOT__cache_dram_req_arb__DOT__prfqq__DOT__pfq_queue__DOT__size_r)); + vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__core_req_arb__DOT__out_empty + = (1U & ((~ (IData)((0U != (0xfU & (vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__core_req_arb__DOT____Vcellout__reqq_queue__data_out[9U] + >> 0x16U))))) + | (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__empty_r))); + vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__core_req_arb__DOT__out_empty + = (1U & ((~ (IData)((0U != (0xfU & (vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__core_req_arb__DOT____Vcellout__reqq_queue__data_out[9U] + >> 0x16U))))) + | (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__empty_r))); + vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__core_req_arb__DOT__out_empty + = (1U & ((~ (IData)((0U != (0xfU & (vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__core_req_arb__DOT____Vcellout__reqq_queue__data_out[9U] + >> 0x16U))))) + | (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__empty_r))); + vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__core_req_arb__DOT__out_empty + = (1U & ((~ (IData)((0U != (0xfU & (vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__core_req_arb__DOT____Vcellout__reqq_queue__data_out[9U] + >> 0x16U))))) + | (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__empty_r))); + vlTOPp->VX_cache__DOT__per_bank_core_rsp_valid + = ((0xeU & (IData)(vlTOPp->VX_cache__DOT__per_bank_core_rsp_valid)) + | (1U & (~ (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cwb_queue__DOT__genblk3__DOT__genblk2__DOT__empty_r)))); + vlTOPp->VX_cache__DOT__per_bank_core_rsp_valid + = ((0xdU & (IData)(vlTOPp->VX_cache__DOT__per_bank_core_rsp_valid)) + | (2U & ((~ (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__cwb_queue__DOT__genblk3__DOT__genblk2__DOT__empty_r)) + << 1U))); + vlTOPp->VX_cache__DOT__per_bank_core_rsp_valid + = ((0xbU & (IData)(vlTOPp->VX_cache__DOT__per_bank_core_rsp_valid)) + | (4U & ((~ (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__cwb_queue__DOT__genblk3__DOT__genblk2__DOT__empty_r)) + << 2U))); + vlTOPp->VX_cache__DOT__per_bank_core_rsp_valid + = ((7U & (IData)(vlTOPp->VX_cache__DOT__per_bank_core_rsp_valid)) + | (8U & ((~ (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cwb_queue__DOT__genblk3__DOT__genblk2__DOT__empty_r)) + << 3U))); + vlTOPp->VX_cache__DOT__per_bank_core_rsp_data[3U] + = vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT____Vcellout__cwb_queue__data_out[0U]; + vlTOPp->VX_cache__DOT__per_bank_core_rsp_tid = + ((0x3fU & (IData)(vlTOPp->VX_cache__DOT__per_bank_core_rsp_tid)) + | (0xc0U & (vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT____Vcellout__cwb_queue__data_out[2U] + >> 4U))); + vlTOPp->VX_cache__DOT__per_bank_core_rsp_tag[3U] + = ((0x3fffffffU & vlTOPp->VX_cache__DOT__per_bank_core_rsp_tag[3U]) + | (0xc0000000U & ((IData)((VL_ULL(0x3ffffffffff) + & (((QData)((IData)( + vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT____Vcellout__cwb_queue__data_out[2U])) + << 0x20U) + | (QData)((IData)( + vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT____Vcellout__cwb_queue__data_out[1U]))))) + << 0x1eU))); + vlTOPp->VX_cache__DOT__per_bank_core_rsp_tag[4U] + = ((0x3fffffffU & ((IData)((VL_ULL(0x3ffffffffff) + & (((QData)((IData)( + vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT____Vcellout__cwb_queue__data_out[2U])) + << 0x20U) | (QData)((IData)( + vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT____Vcellout__cwb_queue__data_out[1U]))))) + >> 2U)) | (0xc0000000U & + ((IData)(((VL_ULL(0x3ffffffffff) + & (((QData)((IData)( + vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT____Vcellout__cwb_queue__data_out[2U])) + << 0x20U) + | (QData)((IData)( + vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT____Vcellout__cwb_queue__data_out[1U])))) + >> 0x20U)) + << 0x1eU))); + vlTOPp->VX_cache__DOT__per_bank_core_rsp_tag[5U] + = (0x3fffffffU & ((IData)(((VL_ULL(0x3ffffffffff) + & (((QData)((IData)( + vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT____Vcellout__cwb_queue__data_out[2U])) + << 0x20U) | (QData)((IData)( + vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT____Vcellout__cwb_queue__data_out[1U])))) + >> 0x20U)) >> 2U)); + vlTOPp->VX_cache__DOT__per_bank_core_rsp_data[2U] + = vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT____Vcellout__cwb_queue__data_out[0U]; + vlTOPp->VX_cache__DOT__per_bank_core_rsp_tid = + ((0xcfU & (IData)(vlTOPp->VX_cache__DOT__per_bank_core_rsp_tid)) + | (0x30U & (vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT____Vcellout__cwb_queue__data_out[2U] + >> 6U))); + vlTOPp->VX_cache__DOT__per_bank_core_rsp_tag[2U] + = ((0xfffffU & vlTOPp->VX_cache__DOT__per_bank_core_rsp_tag[2U]) + | (0xfff00000U & ((IData)((VL_ULL(0x3ffffffffff) + & (((QData)((IData)( + vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT____Vcellout__cwb_queue__data_out[2U])) + << 0x20U) + | (QData)((IData)( + vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT____Vcellout__cwb_queue__data_out[1U]))))) + << 0x14U))); + vlTOPp->VX_cache__DOT__per_bank_core_rsp_tag[3U] + = ((0xc0000000U & vlTOPp->VX_cache__DOT__per_bank_core_rsp_tag[3U]) + | ((0xfffffU & ((IData)((VL_ULL(0x3ffffffffff) + & (((QData)((IData)( + vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT____Vcellout__cwb_queue__data_out[2U])) + << 0x20U) | (QData)((IData)( + vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT____Vcellout__cwb_queue__data_out[1U]))))) + >> 0xcU)) | (0xfff00000U + & ((IData)( + ((VL_ULL(0x3ffffffffff) + & (((QData)((IData)( + vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT____Vcellout__cwb_queue__data_out[2U])) + << 0x20U) + | (QData)((IData)( + vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT____Vcellout__cwb_queue__data_out[1U])))) + >> 0x20U)) + << 0x14U)))); + vlTOPp->VX_cache__DOT__per_bank_core_rsp_data[1U] + = vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT____Vcellout__cwb_queue__data_out[0U]; + vlTOPp->VX_cache__DOT__per_bank_core_rsp_tid = + ((0xf3U & (IData)(vlTOPp->VX_cache__DOT__per_bank_core_rsp_tid)) + | (0xcU & (vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT____Vcellout__cwb_queue__data_out[2U] + >> 8U))); + vlTOPp->VX_cache__DOT__per_bank_core_rsp_tag[1U] + = ((0x3ffU & vlTOPp->VX_cache__DOT__per_bank_core_rsp_tag[1U]) + | (0xfffffc00U & ((IData)((VL_ULL(0x3ffffffffff) + & (((QData)((IData)( + vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT____Vcellout__cwb_queue__data_out[2U])) + << 0x20U) + | (QData)((IData)( + vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT____Vcellout__cwb_queue__data_out[1U]))))) + << 0xaU))); + vlTOPp->VX_cache__DOT__per_bank_core_rsp_tag[2U] + = ((0xfff00000U & vlTOPp->VX_cache__DOT__per_bank_core_rsp_tag[2U]) + | ((0x3ffU & ((IData)((VL_ULL(0x3ffffffffff) + & (((QData)((IData)( + vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT____Vcellout__cwb_queue__data_out[2U])) + << 0x20U) | (QData)((IData)( + vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT____Vcellout__cwb_queue__data_out[1U]))))) + >> 0x16U)) | (0xfffffc00U + & ((IData)(( + (VL_ULL(0x3ffffffffff) + & (((QData)((IData)( + vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT____Vcellout__cwb_queue__data_out[2U])) + << 0x20U) + | (QData)((IData)( + vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT____Vcellout__cwb_queue__data_out[1U])))) + >> 0x20U)) + << 0xaU)))); + vlTOPp->VX_cache__DOT__per_bank_core_rsp_data[0U] + = vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT____Vcellout__cwb_queue__data_out[0U]; + vlTOPp->VX_cache__DOT__per_bank_core_rsp_tid = + ((0xfcU & (IData)(vlTOPp->VX_cache__DOT__per_bank_core_rsp_tid)) + | (3U & (vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT____Vcellout__cwb_queue__data_out[2U] + >> 0xaU))); + vlTOPp->VX_cache__DOT__per_bank_core_rsp_tag[0U] + = (IData)((VL_ULL(0x3ffffffffff) & (((QData)((IData)( + vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT____Vcellout__cwb_queue__data_out[2U])) + << 0x20U) + | (QData)((IData)( + vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT____Vcellout__cwb_queue__data_out[1U]))))); + vlTOPp->VX_cache__DOT__per_bank_core_rsp_tag[1U] + = ((0xfffffc00U & vlTOPp->VX_cache__DOT__per_bank_core_rsp_tag[1U]) + | (IData)(((VL_ULL(0x3ffffffffff) & (((QData)((IData)( + vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT____Vcellout__cwb_queue__data_out[2U])) + << 0x20U) + | (QData)((IData)( + vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT____Vcellout__cwb_queue__data_out[1U])))) + >> 0x20U))); + vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__core_req_arb__DOT__sel_bank__DOT__genblk2__DOT__grant_onehot_r = 0U; + vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__core_req_arb__DOT__sel_bank__DOT__genblk2__DOT__grant_onehot_r + = ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__core_req_arb__DOT__sel_bank__DOT__genblk2__DOT__grant_onehot_r) + | ((IData)(1U) << (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__core_req_arb__DOT__qual_request_index))); + vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__reqq_req_rw_st0 + = (1U & ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__core_req_arb__DOT__use_per_rw) + >> (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__core_req_arb__DOT__qual_request_index))); + vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__reqq_req_addr_st0 + = ((0x77U >= (0x7fU & ((IData)(0x1eU) * (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__core_req_arb__DOT__qual_request_index)))) + ? (0x3fffffffU & (((0U == (0x1fU & ((IData)(0x1eU) + * (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__core_req_arb__DOT__qual_request_index)))) + ? 0U : (vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__core_req_arb__DOT__use_per_addr[ + ((IData)(1U) + + (3U & (((IData)(0x1eU) + * (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__core_req_arb__DOT__qual_request_index)) + >> 5U)))] + << ((IData)(0x20U) + - (0x1fU + & ((IData)(0x1eU) + * (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__core_req_arb__DOT__qual_request_index)))))) + | (vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__core_req_arb__DOT__use_per_addr[ + (3U & (((IData)(0x1eU) + * (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__core_req_arb__DOT__qual_request_index)) + >> 5U))] >> + (0x1fU & ((IData)(0x1eU) + * (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__core_req_arb__DOT__qual_request_index)))))) + : 0U); + vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__core_req_arb__DOT__sel_bank__DOT__genblk2__DOT__grant_onehot_r = 0U; + vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__core_req_arb__DOT__sel_bank__DOT__genblk2__DOT__grant_onehot_r + = ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__core_req_arb__DOT__sel_bank__DOT__genblk2__DOT__grant_onehot_r) + | ((IData)(1U) << (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__core_req_arb__DOT__qual_request_index))); + vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__reqq_req_rw_st0 + = (1U & ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__core_req_arb__DOT__use_per_rw) + >> (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__core_req_arb__DOT__qual_request_index))); + vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__reqq_req_addr_st0 + = ((0x77U >= (0x7fU & ((IData)(0x1eU) * (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__core_req_arb__DOT__qual_request_index)))) + ? (0x3fffffffU & (((0U == (0x1fU & ((IData)(0x1eU) + * (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__core_req_arb__DOT__qual_request_index)))) + ? 0U : (vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__core_req_arb__DOT__use_per_addr[ + ((IData)(1U) + + (3U & (((IData)(0x1eU) + * (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__core_req_arb__DOT__qual_request_index)) + >> 5U)))] + << ((IData)(0x20U) + - (0x1fU + & ((IData)(0x1eU) + * (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__core_req_arb__DOT__qual_request_index)))))) + | (vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__core_req_arb__DOT__use_per_addr[ + (3U & (((IData)(0x1eU) + * (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__core_req_arb__DOT__qual_request_index)) + >> 5U))] >> + (0x1fU & ((IData)(0x1eU) + * (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__core_req_arb__DOT__qual_request_index)))))) + : 0U); + vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__core_req_arb__DOT__sel_bank__DOT__genblk2__DOT__grant_onehot_r = 0U; + vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__core_req_arb__DOT__sel_bank__DOT__genblk2__DOT__grant_onehot_r + = ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__core_req_arb__DOT__sel_bank__DOT__genblk2__DOT__grant_onehot_r) + | ((IData)(1U) << (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__core_req_arb__DOT__qual_request_index))); + vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__reqq_req_rw_st0 + = (1U & ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__core_req_arb__DOT__use_per_rw) + >> (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__core_req_arb__DOT__qual_request_index))); + vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__reqq_req_addr_st0 + = ((0x77U >= (0x7fU & ((IData)(0x1eU) * (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__core_req_arb__DOT__qual_request_index)))) + ? (0x3fffffffU & (((0U == (0x1fU & ((IData)(0x1eU) + * (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__core_req_arb__DOT__qual_request_index)))) + ? 0U : (vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__core_req_arb__DOT__use_per_addr[ + ((IData)(1U) + + (3U & (((IData)(0x1eU) + * (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__core_req_arb__DOT__qual_request_index)) + >> 5U)))] + << ((IData)(0x20U) + - (0x1fU + & ((IData)(0x1eU) + * (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__core_req_arb__DOT__qual_request_index)))))) + | (vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__core_req_arb__DOT__use_per_addr[ + (3U & (((IData)(0x1eU) + * (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__core_req_arb__DOT__qual_request_index)) + >> 5U))] >> + (0x1fU & ((IData)(0x1eU) + * (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__core_req_arb__DOT__qual_request_index)))))) + : 0U); + vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__core_req_arb__DOT__sel_bank__DOT__genblk2__DOT__grant_onehot_r = 0U; + vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__core_req_arb__DOT__sel_bank__DOT__genblk2__DOT__grant_onehot_r + = ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__core_req_arb__DOT__sel_bank__DOT__genblk2__DOT__grant_onehot_r) + | ((IData)(1U) << (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__core_req_arb__DOT__qual_request_index))); + vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__reqq_req_rw_st0 + = (1U & ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__core_req_arb__DOT__use_per_rw) + >> (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__core_req_arb__DOT__qual_request_index))); + vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__reqq_req_addr_st0 + = ((0x77U >= (0x7fU & ((IData)(0x1eU) * (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__core_req_arb__DOT__qual_request_index)))) + ? (0x3fffffffU & (((0U == (0x1fU & ((IData)(0x1eU) + * (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__core_req_arb__DOT__qual_request_index)))) + ? 0U : (vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__core_req_arb__DOT__use_per_addr[ + ((IData)(1U) + + (3U & (((IData)(0x1eU) + * (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__core_req_arb__DOT__qual_request_index)) + >> 5U)))] + << ((IData)(0x20U) + - (0x1fU + & ((IData)(0x1eU) + * (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__core_req_arb__DOT__qual_request_index)))))) + | (vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__core_req_arb__DOT__use_per_addr[ + (3U & (((IData)(0x1eU) + * (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__core_req_arb__DOT__qual_request_index)) + >> 5U))] >> + (0x1fU & ((IData)(0x1eU) + * (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__core_req_arb__DOT__qual_request_index)))))) + : 0U); + vlTOPp->dram_rsp_ready = (0U != (IData)(vlTOPp->VX_cache__DOT__per_bank_dram_fill_rsp_ready)); + vlTOPp->VX_cache__DOT__cache_dram_req_arb__DOT__dram_fill_arb__DOT__qual_bank_dram_fill_req_addr[0U] + = ((0U != (IData)(vlTOPp->VX_cache__DOT__cache_dram_req_arb__DOT__dram_fill_arb__DOT__use_per_bank_dram_fill_req_valid)) + ? vlTOPp->VX_cache__DOT__cache_dram_req_arb__DOT__dram_fill_arb__DOT__use_per_bank_dram_fill_req_addr[0U] + : vlTOPp->VX_cache__DOT__cache_dram_req_arb__DOT__dram_fill_arb__DOT____Vcellout__dfqq_queue__data_out[0U]); + vlTOPp->VX_cache__DOT__cache_dram_req_arb__DOT__dram_fill_arb__DOT__qual_bank_dram_fill_req_addr[1U] + = ((0U != (IData)(vlTOPp->VX_cache__DOT__cache_dram_req_arb__DOT__dram_fill_arb__DOT__use_per_bank_dram_fill_req_valid)) + ? vlTOPp->VX_cache__DOT__cache_dram_req_arb__DOT__dram_fill_arb__DOT__use_per_bank_dram_fill_req_addr[1U] + : vlTOPp->VX_cache__DOT__cache_dram_req_arb__DOT__dram_fill_arb__DOT____Vcellout__dfqq_queue__data_out[1U]); + vlTOPp->VX_cache__DOT__cache_dram_req_arb__DOT__dram_fill_arb__DOT__qual_bank_dram_fill_req_addr[2U] + = ((0U != (IData)(vlTOPp->VX_cache__DOT__cache_dram_req_arb__DOT__dram_fill_arb__DOT__use_per_bank_dram_fill_req_valid)) + ? vlTOPp->VX_cache__DOT__cache_dram_req_arb__DOT__dram_fill_arb__DOT__use_per_bank_dram_fill_req_addr[2U] + : vlTOPp->VX_cache__DOT__cache_dram_req_arb__DOT__dram_fill_arb__DOT____Vcellout__dfqq_queue__data_out[2U]); + vlTOPp->VX_cache__DOT__cache_dram_req_arb__DOT__dram_fill_arb__DOT__qual_bank_dram_fill_req_addr[3U] + = (0xffffU & ((0U != (IData)(vlTOPp->VX_cache__DOT__cache_dram_req_arb__DOT__dram_fill_arb__DOT__use_per_bank_dram_fill_req_valid)) + ? vlTOPp->VX_cache__DOT__cache_dram_req_arb__DOT__dram_fill_arb__DOT__use_per_bank_dram_fill_req_addr[3U] + : vlTOPp->VX_cache__DOT__cache_dram_req_arb__DOT__dram_fill_arb__DOT____Vcellout__dfqq_queue__data_out[3U])); + vlTOPp->VX_cache__DOT__cache_dram_req_arb__DOT__dram_fill_arb__DOT__use_per_bqual_bank_dram_fill_req_valid + = (0xfU & ((0U != (IData)(vlTOPp->VX_cache__DOT__cache_dram_req_arb__DOT__dram_fill_arb__DOT__use_per_bank_dram_fill_req_valid)) + ? ((IData)(vlTOPp->VX_cache__DOT__cache_dram_req_arb__DOT__dram_fill_arb__DOT__use_per_bank_dram_fill_req_valid) + & VL_NEGATE_I((IData)((0U != (IData)(vlTOPp->VX_cache__DOT__cache_dram_req_arb__DOT__dram_fill_arb__DOT__use_per_bank_dram_fill_req_valid))))) + : ((vlTOPp->VX_cache__DOT__cache_dram_req_arb__DOT__dram_fill_arb__DOT____Vcellout__dfqq_queue__data_out[3U] + >> 0x10U) & VL_NEGATE_I((IData)( + (1U + & (~ (IData)(vlTOPp->VX_cache__DOT__cache_dram_req_arb__DOT__dram_fill_arb__DOT__dfqq_queue__DOT__genblk3__DOT__genblk2__DOT__empty_r)))))))); + vlTOPp->VX_cache__DOT__per_bank_snp_rsp_tag[2U] + = ((0xfffffU & vlTOPp->VX_cache__DOT__per_bank_snp_rsp_tag[2U]) + | (0xfff00000U & (vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT____Vcellout__dwb_queue__data_out[0U] + << 0x14U))); + vlTOPp->VX_cache__DOT__per_bank_snp_rsp_tag[3U] + = (0xffffU & (vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT____Vcellout__dwb_queue__data_out[0U] + >> 0xcU)); + vlTOPp->VX_cache__DOT__per_bank_dram_wb_req_byteen + = ((VL_ULL(0xffffffffffff) & vlTOPp->VX_cache__DOT__per_bank_dram_wb_req_byteen) + | ((QData)((IData)((0xffffU & ((vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT____Vcellout__dwb_queue__data_out[6U] + << 0xaU) + | (vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT____Vcellout__dwb_queue__data_out[5U] + >> 0x16U))))) + << 0x30U)); + vlTOPp->VX_cache__DOT__per_bank_dram_wb_req_data[0xcU] + = ((vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT____Vcellout__dwb_queue__data_out[1U] + << 4U) | (vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT____Vcellout__dwb_queue__data_out[0U] + >> 0x1cU)); + vlTOPp->VX_cache__DOT__per_bank_dram_wb_req_data[0xdU] + = ((vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT____Vcellout__dwb_queue__data_out[2U] + << 4U) | (vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT____Vcellout__dwb_queue__data_out[1U] + >> 0x1cU)); + vlTOPp->VX_cache__DOT__per_bank_dram_wb_req_data[0xeU] + = ((vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT____Vcellout__dwb_queue__data_out[3U] + << 4U) | (vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT____Vcellout__dwb_queue__data_out[2U] + >> 0x1cU)); + vlTOPp->VX_cache__DOT__per_bank_dram_wb_req_data[0xfU] + = ((vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT____Vcellout__dwb_queue__data_out[4U] + << 4U) | (vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT____Vcellout__dwb_queue__data_out[3U] + >> 0x1cU)); + vlTOPp->VX_cache__DOT__per_bank_dram_wb_req_addr[2U] + = ((0xfffffU & vlTOPp->VX_cache__DOT__per_bank_dram_wb_req_addr[2U]) + | (0xfff00000U & (0x300000U | (0xffc00000U + & ((vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT____Vcellout__dwb_queue__data_out[5U] + << 0x1aU) + | (0x3c00000U + & (vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT____Vcellout__dwb_queue__data_out[4U] + >> 6U))))))); + vlTOPp->VX_cache__DOT__per_bank_dram_wb_req_addr[3U] + = (0xffffU & (vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT____Vcellout__dwb_queue__data_out[5U] + >> 6U)); + vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__curr_bank_snp_rsp_valid + = (1U & (((~ (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__genblk2__DOT__empty_r)) + & (vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT____Vcellout__dwb_queue__data_out[6U] + >> 6U)) & ((~ (vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT____Vcellout__dwb_queue__data_out[6U] + >> 7U)) | (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__dwbq_dual_valid_sel)))); + vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__curr_bank_dram_wb_req_valid + = (1U & (((~ (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__genblk2__DOT__empty_r)) + & (vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT____Vcellout__dwb_queue__data_out[6U] + >> 7U)) & ((~ (vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT____Vcellout__dwb_queue__data_out[6U] + >> 6U)) | (~ (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__dwbq_dual_valid_sel))))); + vlTOPp->VX_cache__DOT__per_bank_snp_rsp_tag[1U] + = ((0xffffffU & vlTOPp->VX_cache__DOT__per_bank_snp_rsp_tag[1U]) + | (0xff000000U & (vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT____Vcellout__dwb_queue__data_out[0U] + << 0x18U))); + vlTOPp->VX_cache__DOT__per_bank_snp_rsp_tag[2U] + = ((0xfff00000U & vlTOPp->VX_cache__DOT__per_bank_snp_rsp_tag[2U]) + | (0xfffffU & (vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT____Vcellout__dwb_queue__data_out[0U] + >> 8U))); + vlTOPp->VX_cache__DOT__per_bank_dram_wb_req_byteen + = ((VL_ULL(0xffff0000ffffffff) & vlTOPp->VX_cache__DOT__per_bank_dram_wb_req_byteen) + | ((QData)((IData)((0xffffU & ((vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT____Vcellout__dwb_queue__data_out[6U] + << 0xaU) + | (vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT____Vcellout__dwb_queue__data_out[5U] + >> 0x16U))))) + << 0x20U)); + vlTOPp->VX_cache__DOT__per_bank_dram_wb_req_data[8U] + = ((vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT____Vcellout__dwb_queue__data_out[1U] + << 4U) | (vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT____Vcellout__dwb_queue__data_out[0U] + >> 0x1cU)); + vlTOPp->VX_cache__DOT__per_bank_dram_wb_req_data[9U] + = ((vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT____Vcellout__dwb_queue__data_out[2U] + << 4U) | (vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT____Vcellout__dwb_queue__data_out[1U] + >> 0x1cU)); + vlTOPp->VX_cache__DOT__per_bank_dram_wb_req_data[0xaU] + = ((vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT____Vcellout__dwb_queue__data_out[3U] + << 4U) | (vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT____Vcellout__dwb_queue__data_out[2U] + >> 0x1cU)); + vlTOPp->VX_cache__DOT__per_bank_dram_wb_req_data[0xbU] + = ((vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT____Vcellout__dwb_queue__data_out[4U] + << 4U) | (vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT____Vcellout__dwb_queue__data_out[3U] + >> 0x1cU)); + vlTOPp->VX_cache__DOT__per_bank_dram_wb_req_addr[1U] + = ((0xffffffU & vlTOPp->VX_cache__DOT__per_bank_dram_wb_req_addr[1U]) + | (0xff000000U & (0x2000000U | (0xfc000000U + & ((vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT____Vcellout__dwb_queue__data_out[5U] + << 0x1eU) + | (0x3c000000U + & (vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT____Vcellout__dwb_queue__data_out[4U] + >> 2U))))))); + vlTOPp->VX_cache__DOT__per_bank_dram_wb_req_addr[2U] + = ((0xfff00000U & vlTOPp->VX_cache__DOT__per_bank_dram_wb_req_addr[2U]) + | (0xfffffU & (vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT____Vcellout__dwb_queue__data_out[5U] + >> 2U))); + vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__curr_bank_snp_rsp_valid + = (1U & (((~ (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__genblk2__DOT__empty_r)) + & (vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT____Vcellout__dwb_queue__data_out[6U] + >> 6U)) & ((~ (vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT____Vcellout__dwb_queue__data_out[6U] + >> 7U)) | (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__dwbq_dual_valid_sel)))); + vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__curr_bank_dram_wb_req_valid + = (1U & (((~ (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__genblk2__DOT__empty_r)) + & (vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT____Vcellout__dwb_queue__data_out[6U] + >> 7U)) & ((~ (vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT____Vcellout__dwb_queue__data_out[6U] + >> 6U)) | (~ (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__dwbq_dual_valid_sel))))); + vlTOPp->VX_cache__DOT__per_bank_snp_rsp_tag[0U] + = ((0xfffffffU & vlTOPp->VX_cache__DOT__per_bank_snp_rsp_tag[0U]) + | (0xf0000000U & (vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT____Vcellout__dwb_queue__data_out[0U] + << 0x1cU))); + vlTOPp->VX_cache__DOT__per_bank_snp_rsp_tag[1U] + = ((0xff000000U & vlTOPp->VX_cache__DOT__per_bank_snp_rsp_tag[1U]) + | (0xffffffU & (vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT____Vcellout__dwb_queue__data_out[0U] + >> 4U))); + vlTOPp->VX_cache__DOT__per_bank_dram_wb_req_byteen + = ((VL_ULL(0xffffffff0000ffff) & vlTOPp->VX_cache__DOT__per_bank_dram_wb_req_byteen) + | ((QData)((IData)((0xffffU & ((vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT____Vcellout__dwb_queue__data_out[6U] + << 0xaU) + | (vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT____Vcellout__dwb_queue__data_out[5U] + >> 0x16U))))) + << 0x10U)); + vlTOPp->VX_cache__DOT__per_bank_dram_wb_req_data[4U] + = ((vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT____Vcellout__dwb_queue__data_out[1U] + << 4U) | (vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT____Vcellout__dwb_queue__data_out[0U] + >> 0x1cU)); + vlTOPp->VX_cache__DOT__per_bank_dram_wb_req_data[5U] + = ((vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT____Vcellout__dwb_queue__data_out[2U] + << 4U) | (vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT____Vcellout__dwb_queue__data_out[1U] + >> 0x1cU)); + vlTOPp->VX_cache__DOT__per_bank_dram_wb_req_data[6U] + = ((vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT____Vcellout__dwb_queue__data_out[3U] + << 4U) | (vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT____Vcellout__dwb_queue__data_out[2U] + >> 0x1cU)); + vlTOPp->VX_cache__DOT__per_bank_dram_wb_req_data[7U] + = ((vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT____Vcellout__dwb_queue__data_out[4U] + << 4U) | (vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT____Vcellout__dwb_queue__data_out[3U] + >> 0x1cU)); + vlTOPp->VX_cache__DOT__per_bank_dram_wb_req_addr[0U] + = ((0xfffffffU & vlTOPp->VX_cache__DOT__per_bank_dram_wb_req_addr[0U]) + | (0xf0000000U & (0x10000000U | (0xc0000000U + & (vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT____Vcellout__dwb_queue__data_out[4U] + << 2U))))); + vlTOPp->VX_cache__DOT__per_bank_dram_wb_req_addr[1U] + = ((0xff000000U & vlTOPp->VX_cache__DOT__per_bank_dram_wb_req_addr[1U]) + | (0xffffffU & ((0xffffffcU & (vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT____Vcellout__dwb_queue__data_out[5U] + << 2U)) | + (3U & (vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT____Vcellout__dwb_queue__data_out[4U] + >> 0x1eU))))); + vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__curr_bank_snp_rsp_valid + = (1U & (((~ (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__genblk2__DOT__empty_r)) + & (vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT____Vcellout__dwb_queue__data_out[6U] + >> 6U)) & ((~ (vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT____Vcellout__dwb_queue__data_out[6U] + >> 7U)) | (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__dwbq_dual_valid_sel)))); + vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__curr_bank_dram_wb_req_valid + = (1U & (((~ (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__genblk2__DOT__empty_r)) + & (vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT____Vcellout__dwb_queue__data_out[6U] + >> 7U)) & ((~ (vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT____Vcellout__dwb_queue__data_out[6U] + >> 6U)) | (~ (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__dwbq_dual_valid_sel))))); + vlTOPp->VX_cache__DOT__per_bank_snp_rsp_tag[0U] + = ((0xf0000000U & vlTOPp->VX_cache__DOT__per_bank_snp_rsp_tag[0U]) + | (0xfffffffU & vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT____Vcellout__dwb_queue__data_out[0U])); + vlTOPp->VX_cache__DOT__per_bank_dram_wb_req_byteen + = ((VL_ULL(0xffffffffffff0000) & vlTOPp->VX_cache__DOT__per_bank_dram_wb_req_byteen) + | (IData)((IData)((0xffffU & ((vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT____Vcellout__dwb_queue__data_out[6U] + << 0xaU) + | (vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT____Vcellout__dwb_queue__data_out[5U] + >> 0x16U)))))); + vlTOPp->VX_cache__DOT__per_bank_dram_wb_req_data[0U] + = ((vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT____Vcellout__dwb_queue__data_out[1U] + << 4U) | (vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT____Vcellout__dwb_queue__data_out[0U] + >> 0x1cU)); + vlTOPp->VX_cache__DOT__per_bank_dram_wb_req_data[1U] + = ((vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT____Vcellout__dwb_queue__data_out[2U] + << 4U) | (vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT____Vcellout__dwb_queue__data_out[1U] + >> 0x1cU)); + vlTOPp->VX_cache__DOT__per_bank_dram_wb_req_data[2U] + = ((vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT____Vcellout__dwb_queue__data_out[3U] + << 4U) | (vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT____Vcellout__dwb_queue__data_out[2U] + >> 0x1cU)); + vlTOPp->VX_cache__DOT__per_bank_dram_wb_req_data[3U] + = ((vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT____Vcellout__dwb_queue__data_out[4U] + << 4U) | (vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT____Vcellout__dwb_queue__data_out[3U] + >> 0x1cU)); + vlTOPp->VX_cache__DOT__per_bank_dram_wb_req_addr[0U] + = ((0xf0000000U & vlTOPp->VX_cache__DOT__per_bank_dram_wb_req_addr[0U]) + | (0xffffffcU & ((vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT____Vcellout__dwb_queue__data_out[5U] + << 6U) | (0x3cU & (vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT____Vcellout__dwb_queue__data_out[4U] + >> 0x1aU))))); + vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__curr_bank_snp_rsp_valid + = (1U & (((~ (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__genblk2__DOT__empty_r)) + & (vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT____Vcellout__dwb_queue__data_out[6U] + >> 6U)) & ((~ (vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT____Vcellout__dwb_queue__data_out[6U] + >> 7U)) | (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__dwbq_dual_valid_sel)))); + vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__curr_bank_dram_wb_req_valid + = (1U & (((~ (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__genblk2__DOT__empty_r)) + & (vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT____Vcellout__dwb_queue__data_out[6U] + >> 7U)) & ((~ (vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT____Vcellout__dwb_queue__data_out[6U] + >> 6U)) | (~ (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__dwbq_dual_valid_sel))))); + vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__dfpq_pop_unqual + = (1U & ((~ (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cache_miss_resrv__DOT__dequeue_possible)) + & (~ (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__dfp_queue__DOT__genblk3__DOT__genblk2__DOT__empty_r)))); + vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__dfpq_pop_unqual + = (1U & ((~ (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__cache_miss_resrv__DOT__dequeue_possible)) + & (~ (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__dfp_queue__DOT__genblk3__DOT__genblk2__DOT__empty_r)))); + vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__dfpq_pop_unqual + = (1U & ((~ (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__cache_miss_resrv__DOT__dequeue_possible)) + & (~ (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__dfp_queue__DOT__genblk3__DOT__genblk2__DOT__empty_r)))); + vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__dfpq_pop_unqual + = (1U & ((~ (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cache_miss_resrv__DOT__dequeue_possible)) + & (~ (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__dfp_queue__DOT__genblk3__DOT__genblk2__DOT__empty_r)))); + vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__is_fill_in_pipe = 0U; + if (vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__is_fill_st1 + [0U]) { + vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__is_fill_in_pipe = 1U; + } + vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cache_miss_resrv__DOT__valid_address_match + = ((0xfffeU & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cache_miss_resrv__DOT__valid_address_match)) + | ((1U & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cache_miss_resrv__DOT__valid_table)) + ? (1U & ((0x3ffffffU & vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cache_miss_resrv__DOT__addr_table[0U]) + == vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__addr_st1 + [0U])) : 0U)); + vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cache_miss_resrv__DOT__valid_address_match + = ((0xfffdU & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cache_miss_resrv__DOT__valid_address_match)) + | (((2U & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cache_miss_resrv__DOT__valid_table)) + ? (1U & ((0x3ffffffU & ((vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cache_miss_resrv__DOT__addr_table[1U] + << 6U) | ( + vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cache_miss_resrv__DOT__addr_table[0U] + >> 0x1aU))) + == vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__addr_st1 + [0U])) : 0U) << 1U)); + vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cache_miss_resrv__DOT__valid_address_match + = ((0xfffbU & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cache_miss_resrv__DOT__valid_address_match)) + | (((4U & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cache_miss_resrv__DOT__valid_table)) + ? (1U & ((0x3ffffffU & ((vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cache_miss_resrv__DOT__addr_table[2U] + << 0xcU) | + (vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cache_miss_resrv__DOT__addr_table[1U] + >> 0x14U))) + == vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__addr_st1 + [0U])) : 0U) << 2U)); + vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cache_miss_resrv__DOT__valid_address_match + = ((0xfff7U & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cache_miss_resrv__DOT__valid_address_match)) + | (((8U & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cache_miss_resrv__DOT__valid_table)) + ? (1U & ((0x3ffffffU & ((vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cache_miss_resrv__DOT__addr_table[3U] + << 0x12U) + | (vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cache_miss_resrv__DOT__addr_table[2U] + >> 0xeU))) + == vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__addr_st1 + [0U])) : 0U) << 3U)); + vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cache_miss_resrv__DOT__valid_address_match + = ((0xffefU & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cache_miss_resrv__DOT__valid_address_match)) + | (((0x10U & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cache_miss_resrv__DOT__valid_table)) + ? (1U & ((0x3ffffffU & ((vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cache_miss_resrv__DOT__addr_table[4U] + << 0x18U) + | (vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cache_miss_resrv__DOT__addr_table[3U] + >> 8U))) + == vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__addr_st1 + [0U])) : 0U) << 4U)); + vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cache_miss_resrv__DOT__valid_address_match + = ((0xffdfU & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cache_miss_resrv__DOT__valid_address_match)) + | (((0x20U & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cache_miss_resrv__DOT__valid_table)) + ? (1U & ((0x3ffffffU & ((vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cache_miss_resrv__DOT__addr_table[5U] + << 0x1eU) + | (vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cache_miss_resrv__DOT__addr_table[4U] + >> 2U))) + == vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__addr_st1 + [0U])) : 0U) << 5U)); + vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cache_miss_resrv__DOT__valid_address_match + = ((0xffbfU & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cache_miss_resrv__DOT__valid_address_match)) + | (((0x40U & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cache_miss_resrv__DOT__valid_table)) + ? (1U & ((0x3ffffffU & ((vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cache_miss_resrv__DOT__addr_table[5U] + << 4U) | ( + vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cache_miss_resrv__DOT__addr_table[4U] + >> 0x1cU))) + == vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__addr_st1 + [0U])) : 0U) << 6U)); + vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cache_miss_resrv__DOT__valid_address_match + = ((0xff7fU & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cache_miss_resrv__DOT__valid_address_match)) + | (((0x80U & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cache_miss_resrv__DOT__valid_table)) + ? (1U & ((0x3ffffffU & ((vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cache_miss_resrv__DOT__addr_table[6U] + << 0xaU) | + (vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cache_miss_resrv__DOT__addr_table[5U] + >> 0x16U))) + == vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__addr_st1 + [0U])) : 0U) << 7U)); + vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cache_miss_resrv__DOT__valid_address_match + = ((0xfeffU & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cache_miss_resrv__DOT__valid_address_match)) + | (((0x100U & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cache_miss_resrv__DOT__valid_table)) + ? (1U & ((0x3ffffffU & ((vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cache_miss_resrv__DOT__addr_table[7U] + << 0x10U) + | (vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cache_miss_resrv__DOT__addr_table[6U] + >> 0x10U))) + == vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__addr_st1 + [0U])) : 0U) << 8U)); + vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cache_miss_resrv__DOT__valid_address_match + = ((0xfdffU & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cache_miss_resrv__DOT__valid_address_match)) + | (((0x200U & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cache_miss_resrv__DOT__valid_table)) + ? (1U & ((0x3ffffffU & ((vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cache_miss_resrv__DOT__addr_table[8U] + << 0x16U) + | (vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cache_miss_resrv__DOT__addr_table[7U] + >> 0xaU))) + == vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__addr_st1 + [0U])) : 0U) << 9U)); + vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cache_miss_resrv__DOT__valid_address_match + = ((0xfbffU & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cache_miss_resrv__DOT__valid_address_match)) + | (((0x400U & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cache_miss_resrv__DOT__valid_table)) + ? (1U & ((0x3ffffffU & ((vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cache_miss_resrv__DOT__addr_table[9U] + << 0x1cU) + | (vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cache_miss_resrv__DOT__addr_table[8U] + >> 4U))) + == vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__addr_st1 + [0U])) : 0U) << 0xaU)); + vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cache_miss_resrv__DOT__valid_address_match + = ((0xf7ffU & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cache_miss_resrv__DOT__valid_address_match)) + | (((0x800U & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cache_miss_resrv__DOT__valid_table)) + ? (1U & ((0x3ffffffU & ((vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cache_miss_resrv__DOT__addr_table[9U] + << 2U) | ( + vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cache_miss_resrv__DOT__addr_table[8U] + >> 0x1eU))) + == vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__addr_st1 + [0U])) : 0U) << 0xbU)); + vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cache_miss_resrv__DOT__valid_address_match + = ((0xefffU & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cache_miss_resrv__DOT__valid_address_match)) + | (((0x1000U & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cache_miss_resrv__DOT__valid_table)) + ? (1U & ((0x3ffffffU & ((vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cache_miss_resrv__DOT__addr_table[0xaU] + << 8U) | ( + vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cache_miss_resrv__DOT__addr_table[9U] + >> 0x18U))) + == vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__addr_st1 + [0U])) : 0U) << 0xcU)); + vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cache_miss_resrv__DOT__valid_address_match + = ((0xdfffU & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cache_miss_resrv__DOT__valid_address_match)) + | (((0x2000U & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cache_miss_resrv__DOT__valid_table)) + ? (1U & ((0x3ffffffU & ((vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cache_miss_resrv__DOT__addr_table[0xbU] + << 0xeU) | + (vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cache_miss_resrv__DOT__addr_table[0xaU] + >> 0x12U))) + == vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__addr_st1 + [0U])) : 0U) << 0xdU)); + vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cache_miss_resrv__DOT__valid_address_match + = ((0xbfffU & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cache_miss_resrv__DOT__valid_address_match)) + | (((0x4000U & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cache_miss_resrv__DOT__valid_table)) + ? (1U & ((0x3ffffffU & ((vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cache_miss_resrv__DOT__addr_table[0xcU] + << 0x14U) + | (vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cache_miss_resrv__DOT__addr_table[0xbU] + >> 0xcU))) + == vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__addr_st1 + [0U])) : 0U) << 0xeU)); + vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cache_miss_resrv__DOT__valid_address_match + = ((0x7fffU & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cache_miss_resrv__DOT__valid_address_match)) + | (((0x8000U & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cache_miss_resrv__DOT__valid_table)) + ? (1U & ((0x3ffffffU & (vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cache_miss_resrv__DOT__addr_table[0xcU] + >> 6U)) == + vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__addr_st1 + [0U])) : 0U) << 0xfU)); + vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__tag_data_access__DOT____Vcellinp__s0_1_c0__in[0U] + = vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__data + [(0x3fU & vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__addr_st1 + [0U])][0U]; + vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__tag_data_access__DOT____Vcellinp__s0_1_c0__in[1U] + = vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__data + [(0x3fU & vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__addr_st1 + [0U])][1U]; + vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__tag_data_access__DOT____Vcellinp__s0_1_c0__in[2U] + = vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__data + [(0x3fU & vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__addr_st1 + [0U])][2U]; + vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__tag_data_access__DOT____Vcellinp__s0_1_c0__in[3U] + = vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__data + [(0x3fU & vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__addr_st1 + [0U])][3U]; + vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__tag_data_access__DOT____Vcellinp__s0_1_c0__in[4U] + = ((0xfff00000U & (vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__dirtyb + [(0x3fU & vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__addr_st1 + [0U])] << 0x14U)) | vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__tag + [(0x3fU & vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__addr_st1 + [0U])]); + vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__tag_data_access__DOT____Vcellinp__s0_1_c0__in[5U] + = ((0x20U & ((IData)((vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__valid + >> (0x3fU & vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__addr_st1 + [0U]))) << 5U)) | + ((0x10U & ((IData)((vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__dirty + >> (0x3fU & vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__addr_st1 + [0U]))) << 4U)) + | (0xfffffU & (vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__dirtyb + [(0x3fU & vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__addr_st1 + [0U])] >> 0xcU)))); + vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__is_fill_in_pipe = 0U; + if (vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__is_fill_st1 + [0U]) { + vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__is_fill_in_pipe = 1U; + } + vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__cache_miss_resrv__DOT__valid_address_match + = ((0xfffeU & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__cache_miss_resrv__DOT__valid_address_match)) + | ((1U & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__cache_miss_resrv__DOT__valid_table)) + ? (1U & ((0x3ffffffU & vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__cache_miss_resrv__DOT__addr_table[0U]) + == vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__addr_st1 + [0U])) : 0U)); + vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__cache_miss_resrv__DOT__valid_address_match + = ((0xfffdU & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__cache_miss_resrv__DOT__valid_address_match)) + | (((2U & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__cache_miss_resrv__DOT__valid_table)) + ? (1U & ((0x3ffffffU & ((vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__cache_miss_resrv__DOT__addr_table[1U] + << 6U) | ( + vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__cache_miss_resrv__DOT__addr_table[0U] + >> 0x1aU))) + == vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__addr_st1 + [0U])) : 0U) << 1U)); + vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__cache_miss_resrv__DOT__valid_address_match + = ((0xfffbU & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__cache_miss_resrv__DOT__valid_address_match)) + | (((4U & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__cache_miss_resrv__DOT__valid_table)) + ? (1U & ((0x3ffffffU & ((vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__cache_miss_resrv__DOT__addr_table[2U] + << 0xcU) | + (vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__cache_miss_resrv__DOT__addr_table[1U] + >> 0x14U))) + == vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__addr_st1 + [0U])) : 0U) << 2U)); + vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__cache_miss_resrv__DOT__valid_address_match + = ((0xfff7U & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__cache_miss_resrv__DOT__valid_address_match)) + | (((8U & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__cache_miss_resrv__DOT__valid_table)) + ? (1U & ((0x3ffffffU & ((vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__cache_miss_resrv__DOT__addr_table[3U] + << 0x12U) + | (vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__cache_miss_resrv__DOT__addr_table[2U] + >> 0xeU))) + == vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__addr_st1 + [0U])) : 0U) << 3U)); + vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__cache_miss_resrv__DOT__valid_address_match + = ((0xffefU & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__cache_miss_resrv__DOT__valid_address_match)) + | (((0x10U & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__cache_miss_resrv__DOT__valid_table)) + ? (1U & ((0x3ffffffU & ((vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__cache_miss_resrv__DOT__addr_table[4U] + << 0x18U) + | (vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__cache_miss_resrv__DOT__addr_table[3U] + >> 8U))) + == vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__addr_st1 + [0U])) : 0U) << 4U)); + vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__cache_miss_resrv__DOT__valid_address_match + = ((0xffdfU & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__cache_miss_resrv__DOT__valid_address_match)) + | (((0x20U & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__cache_miss_resrv__DOT__valid_table)) + ? (1U & ((0x3ffffffU & ((vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__cache_miss_resrv__DOT__addr_table[5U] + << 0x1eU) + | (vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__cache_miss_resrv__DOT__addr_table[4U] + >> 2U))) + == vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__addr_st1 + [0U])) : 0U) << 5U)); + vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__cache_miss_resrv__DOT__valid_address_match + = ((0xffbfU & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__cache_miss_resrv__DOT__valid_address_match)) + | (((0x40U & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__cache_miss_resrv__DOT__valid_table)) + ? (1U & ((0x3ffffffU & ((vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__cache_miss_resrv__DOT__addr_table[5U] + << 4U) | ( + vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__cache_miss_resrv__DOT__addr_table[4U] + >> 0x1cU))) + == vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__addr_st1 + [0U])) : 0U) << 6U)); + vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__cache_miss_resrv__DOT__valid_address_match + = ((0xff7fU & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__cache_miss_resrv__DOT__valid_address_match)) + | (((0x80U & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__cache_miss_resrv__DOT__valid_table)) + ? (1U & ((0x3ffffffU & ((vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__cache_miss_resrv__DOT__addr_table[6U] + << 0xaU) | + (vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__cache_miss_resrv__DOT__addr_table[5U] + >> 0x16U))) + == vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__addr_st1 + [0U])) : 0U) << 7U)); + vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__cache_miss_resrv__DOT__valid_address_match + = ((0xfeffU & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__cache_miss_resrv__DOT__valid_address_match)) + | (((0x100U & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__cache_miss_resrv__DOT__valid_table)) + ? (1U & ((0x3ffffffU & ((vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__cache_miss_resrv__DOT__addr_table[7U] + << 0x10U) + | (vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__cache_miss_resrv__DOT__addr_table[6U] + >> 0x10U))) + == vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__addr_st1 + [0U])) : 0U) << 8U)); + vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__cache_miss_resrv__DOT__valid_address_match + = ((0xfdffU & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__cache_miss_resrv__DOT__valid_address_match)) + | (((0x200U & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__cache_miss_resrv__DOT__valid_table)) + ? (1U & ((0x3ffffffU & ((vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__cache_miss_resrv__DOT__addr_table[8U] + << 0x16U) + | (vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__cache_miss_resrv__DOT__addr_table[7U] + >> 0xaU))) + == vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__addr_st1 + [0U])) : 0U) << 9U)); + vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__cache_miss_resrv__DOT__valid_address_match + = ((0xfbffU & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__cache_miss_resrv__DOT__valid_address_match)) + | (((0x400U & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__cache_miss_resrv__DOT__valid_table)) + ? (1U & ((0x3ffffffU & ((vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__cache_miss_resrv__DOT__addr_table[9U] + << 0x1cU) + | (vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__cache_miss_resrv__DOT__addr_table[8U] + >> 4U))) + == vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__addr_st1 + [0U])) : 0U) << 0xaU)); + vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__cache_miss_resrv__DOT__valid_address_match + = ((0xf7ffU & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__cache_miss_resrv__DOT__valid_address_match)) + | (((0x800U & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__cache_miss_resrv__DOT__valid_table)) + ? (1U & ((0x3ffffffU & ((vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__cache_miss_resrv__DOT__addr_table[9U] + << 2U) | ( + vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__cache_miss_resrv__DOT__addr_table[8U] + >> 0x1eU))) + == vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__addr_st1 + [0U])) : 0U) << 0xbU)); + vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__cache_miss_resrv__DOT__valid_address_match + = ((0xefffU & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__cache_miss_resrv__DOT__valid_address_match)) + | (((0x1000U & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__cache_miss_resrv__DOT__valid_table)) + ? (1U & ((0x3ffffffU & ((vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__cache_miss_resrv__DOT__addr_table[0xaU] + << 8U) | ( + vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__cache_miss_resrv__DOT__addr_table[9U] + >> 0x18U))) + == vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__addr_st1 + [0U])) : 0U) << 0xcU)); + vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__cache_miss_resrv__DOT__valid_address_match + = ((0xdfffU & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__cache_miss_resrv__DOT__valid_address_match)) + | (((0x2000U & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__cache_miss_resrv__DOT__valid_table)) + ? (1U & ((0x3ffffffU & ((vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__cache_miss_resrv__DOT__addr_table[0xbU] + << 0xeU) | + (vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__cache_miss_resrv__DOT__addr_table[0xaU] + >> 0x12U))) + == vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__addr_st1 + [0U])) : 0U) << 0xdU)); + vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__cache_miss_resrv__DOT__valid_address_match + = ((0xbfffU & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__cache_miss_resrv__DOT__valid_address_match)) + | (((0x4000U & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__cache_miss_resrv__DOT__valid_table)) + ? (1U & ((0x3ffffffU & ((vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__cache_miss_resrv__DOT__addr_table[0xcU] + << 0x14U) + | (vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__cache_miss_resrv__DOT__addr_table[0xbU] + >> 0xcU))) + == vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__addr_st1 + [0U])) : 0U) << 0xeU)); + vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__cache_miss_resrv__DOT__valid_address_match + = ((0x7fffU & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__cache_miss_resrv__DOT__valid_address_match)) + | (((0x8000U & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__cache_miss_resrv__DOT__valid_table)) + ? (1U & ((0x3ffffffU & (vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__cache_miss_resrv__DOT__addr_table[0xcU] + >> 6U)) == + vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__addr_st1 + [0U])) : 0U) << 0xfU)); + vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__tag_data_access__DOT____Vcellinp__s0_1_c0__in[0U] + = vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__data + [(0x3fU & vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__addr_st1 + [0U])][0U]; + vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__tag_data_access__DOT____Vcellinp__s0_1_c0__in[1U] + = vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__data + [(0x3fU & vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__addr_st1 + [0U])][1U]; + vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__tag_data_access__DOT____Vcellinp__s0_1_c0__in[2U] + = vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__data + [(0x3fU & vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__addr_st1 + [0U])][2U]; + vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__tag_data_access__DOT____Vcellinp__s0_1_c0__in[3U] + = vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__data + [(0x3fU & vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__addr_st1 + [0U])][3U]; + vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__tag_data_access__DOT____Vcellinp__s0_1_c0__in[4U] + = ((0xfff00000U & (vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__dirtyb + [(0x3fU & vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__addr_st1 + [0U])] << 0x14U)) | vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__tag + [(0x3fU & vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__addr_st1 + [0U])]); + vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__tag_data_access__DOT____Vcellinp__s0_1_c0__in[5U] + = ((0x20U & ((IData)((vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__valid + >> (0x3fU & vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__addr_st1 + [0U]))) << 5U)) | + ((0x10U & ((IData)((vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__dirty + >> (0x3fU & vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__addr_st1 + [0U]))) << 4U)) + | (0xfffffU & (vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__dirtyb + [(0x3fU & vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__addr_st1 + [0U])] >> 0xcU)))); + vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__is_fill_in_pipe = 0U; + if (vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__is_fill_st1 + [0U]) { + vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__is_fill_in_pipe = 1U; + } + vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__cache_miss_resrv__DOT__valid_address_match + = ((0xfffeU & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__cache_miss_resrv__DOT__valid_address_match)) + | ((1U & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__cache_miss_resrv__DOT__valid_table)) + ? (1U & ((0x3ffffffU & vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__cache_miss_resrv__DOT__addr_table[0U]) + == vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__addr_st1 + [0U])) : 0U)); + vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__cache_miss_resrv__DOT__valid_address_match + = ((0xfffdU & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__cache_miss_resrv__DOT__valid_address_match)) + | (((2U & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__cache_miss_resrv__DOT__valid_table)) + ? (1U & ((0x3ffffffU & ((vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__cache_miss_resrv__DOT__addr_table[1U] + << 6U) | ( + vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__cache_miss_resrv__DOT__addr_table[0U] + >> 0x1aU))) + == vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__addr_st1 + [0U])) : 0U) << 1U)); + vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__cache_miss_resrv__DOT__valid_address_match + = ((0xfffbU & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__cache_miss_resrv__DOT__valid_address_match)) + | (((4U & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__cache_miss_resrv__DOT__valid_table)) + ? (1U & ((0x3ffffffU & ((vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__cache_miss_resrv__DOT__addr_table[2U] + << 0xcU) | + (vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__cache_miss_resrv__DOT__addr_table[1U] + >> 0x14U))) + == vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__addr_st1 + [0U])) : 0U) << 2U)); + vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__cache_miss_resrv__DOT__valid_address_match + = ((0xfff7U & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__cache_miss_resrv__DOT__valid_address_match)) + | (((8U & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__cache_miss_resrv__DOT__valid_table)) + ? (1U & ((0x3ffffffU & ((vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__cache_miss_resrv__DOT__addr_table[3U] + << 0x12U) + | (vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__cache_miss_resrv__DOT__addr_table[2U] + >> 0xeU))) + == vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__addr_st1 + [0U])) : 0U) << 3U)); + vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__cache_miss_resrv__DOT__valid_address_match + = ((0xffefU & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__cache_miss_resrv__DOT__valid_address_match)) + | (((0x10U & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__cache_miss_resrv__DOT__valid_table)) + ? (1U & ((0x3ffffffU & ((vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__cache_miss_resrv__DOT__addr_table[4U] + << 0x18U) + | (vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__cache_miss_resrv__DOT__addr_table[3U] + >> 8U))) + == vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__addr_st1 + [0U])) : 0U) << 4U)); + vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__cache_miss_resrv__DOT__valid_address_match + = ((0xffdfU & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__cache_miss_resrv__DOT__valid_address_match)) + | (((0x20U & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__cache_miss_resrv__DOT__valid_table)) + ? (1U & ((0x3ffffffU & ((vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__cache_miss_resrv__DOT__addr_table[5U] + << 0x1eU) + | (vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__cache_miss_resrv__DOT__addr_table[4U] + >> 2U))) + == vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__addr_st1 + [0U])) : 0U) << 5U)); + vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__cache_miss_resrv__DOT__valid_address_match + = ((0xffbfU & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__cache_miss_resrv__DOT__valid_address_match)) + | (((0x40U & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__cache_miss_resrv__DOT__valid_table)) + ? (1U & ((0x3ffffffU & ((vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__cache_miss_resrv__DOT__addr_table[5U] + << 4U) | ( + vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__cache_miss_resrv__DOT__addr_table[4U] + >> 0x1cU))) + == vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__addr_st1 + [0U])) : 0U) << 6U)); + vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__cache_miss_resrv__DOT__valid_address_match + = ((0xff7fU & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__cache_miss_resrv__DOT__valid_address_match)) + | (((0x80U & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__cache_miss_resrv__DOT__valid_table)) + ? (1U & ((0x3ffffffU & ((vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__cache_miss_resrv__DOT__addr_table[6U] + << 0xaU) | + (vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__cache_miss_resrv__DOT__addr_table[5U] + >> 0x16U))) + == vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__addr_st1 + [0U])) : 0U) << 7U)); + vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__cache_miss_resrv__DOT__valid_address_match + = ((0xfeffU & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__cache_miss_resrv__DOT__valid_address_match)) + | (((0x100U & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__cache_miss_resrv__DOT__valid_table)) + ? (1U & ((0x3ffffffU & ((vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__cache_miss_resrv__DOT__addr_table[7U] + << 0x10U) + | (vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__cache_miss_resrv__DOT__addr_table[6U] + >> 0x10U))) + == vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__addr_st1 + [0U])) : 0U) << 8U)); + vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__cache_miss_resrv__DOT__valid_address_match + = ((0xfdffU & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__cache_miss_resrv__DOT__valid_address_match)) + | (((0x200U & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__cache_miss_resrv__DOT__valid_table)) + ? (1U & ((0x3ffffffU & ((vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__cache_miss_resrv__DOT__addr_table[8U] + << 0x16U) + | (vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__cache_miss_resrv__DOT__addr_table[7U] + >> 0xaU))) + == vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__addr_st1 + [0U])) : 0U) << 9U)); + vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__cache_miss_resrv__DOT__valid_address_match + = ((0xfbffU & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__cache_miss_resrv__DOT__valid_address_match)) + | (((0x400U & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__cache_miss_resrv__DOT__valid_table)) + ? (1U & ((0x3ffffffU & ((vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__cache_miss_resrv__DOT__addr_table[9U] + << 0x1cU) + | (vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__cache_miss_resrv__DOT__addr_table[8U] + >> 4U))) + == vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__addr_st1 + [0U])) : 0U) << 0xaU)); + vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__cache_miss_resrv__DOT__valid_address_match + = ((0xf7ffU & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__cache_miss_resrv__DOT__valid_address_match)) + | (((0x800U & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__cache_miss_resrv__DOT__valid_table)) + ? (1U & ((0x3ffffffU & ((vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__cache_miss_resrv__DOT__addr_table[9U] + << 2U) | ( + vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__cache_miss_resrv__DOT__addr_table[8U] + >> 0x1eU))) + == vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__addr_st1 + [0U])) : 0U) << 0xbU)); + vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__cache_miss_resrv__DOT__valid_address_match + = ((0xefffU & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__cache_miss_resrv__DOT__valid_address_match)) + | (((0x1000U & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__cache_miss_resrv__DOT__valid_table)) + ? (1U & ((0x3ffffffU & ((vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__cache_miss_resrv__DOT__addr_table[0xaU] + << 8U) | ( + vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__cache_miss_resrv__DOT__addr_table[9U] + >> 0x18U))) + == vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__addr_st1 + [0U])) : 0U) << 0xcU)); + vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__cache_miss_resrv__DOT__valid_address_match + = ((0xdfffU & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__cache_miss_resrv__DOT__valid_address_match)) + | (((0x2000U & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__cache_miss_resrv__DOT__valid_table)) + ? (1U & ((0x3ffffffU & ((vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__cache_miss_resrv__DOT__addr_table[0xbU] + << 0xeU) | + (vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__cache_miss_resrv__DOT__addr_table[0xaU] + >> 0x12U))) + == vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__addr_st1 + [0U])) : 0U) << 0xdU)); + vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__cache_miss_resrv__DOT__valid_address_match + = ((0xbfffU & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__cache_miss_resrv__DOT__valid_address_match)) + | (((0x4000U & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__cache_miss_resrv__DOT__valid_table)) + ? (1U & ((0x3ffffffU & ((vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__cache_miss_resrv__DOT__addr_table[0xcU] + << 0x14U) + | (vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__cache_miss_resrv__DOT__addr_table[0xbU] + >> 0xcU))) + == vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__addr_st1 + [0U])) : 0U) << 0xeU)); + vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__cache_miss_resrv__DOT__valid_address_match + = ((0x7fffU & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__cache_miss_resrv__DOT__valid_address_match)) + | (((0x8000U & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__cache_miss_resrv__DOT__valid_table)) + ? (1U & ((0x3ffffffU & (vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__cache_miss_resrv__DOT__addr_table[0xcU] + >> 6U)) == + vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__addr_st1 + [0U])) : 0U) << 0xfU)); + vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__tag_data_access__DOT____Vcellinp__s0_1_c0__in[0U] + = vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__data + [(0x3fU & vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__addr_st1 + [0U])][0U]; + vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__tag_data_access__DOT____Vcellinp__s0_1_c0__in[1U] + = vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__data + [(0x3fU & vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__addr_st1 + [0U])][1U]; + vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__tag_data_access__DOT____Vcellinp__s0_1_c0__in[2U] + = vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__data + [(0x3fU & vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__addr_st1 + [0U])][2U]; + vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__tag_data_access__DOT____Vcellinp__s0_1_c0__in[3U] + = vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__data + [(0x3fU & vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__addr_st1 + [0U])][3U]; + vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__tag_data_access__DOT____Vcellinp__s0_1_c0__in[4U] + = ((0xfff00000U & (vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__dirtyb + [(0x3fU & vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__addr_st1 + [0U])] << 0x14U)) | vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__tag + [(0x3fU & vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__addr_st1 + [0U])]); + vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__tag_data_access__DOT____Vcellinp__s0_1_c0__in[5U] + = ((0x20U & ((IData)((vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__valid + >> (0x3fU & vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__addr_st1 + [0U]))) << 5U)) | + ((0x10U & ((IData)((vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__dirty + >> (0x3fU & vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__addr_st1 + [0U]))) << 4U)) + | (0xfffffU & (vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__dirtyb + [(0x3fU & vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__addr_st1 + [0U])] >> 0xcU)))); + vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__is_fill_in_pipe = 0U; + if (vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__is_fill_st1 + [0U]) { + vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__is_fill_in_pipe = 1U; + } + vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cache_miss_resrv__DOT__valid_address_match + = ((0xfffeU & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cache_miss_resrv__DOT__valid_address_match)) + | ((1U & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cache_miss_resrv__DOT__valid_table)) + ? (1U & ((0x3ffffffU & vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cache_miss_resrv__DOT__addr_table[0U]) + == vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__addr_st1 + [0U])) : 0U)); + vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cache_miss_resrv__DOT__valid_address_match + = ((0xfffdU & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cache_miss_resrv__DOT__valid_address_match)) + | (((2U & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cache_miss_resrv__DOT__valid_table)) + ? (1U & ((0x3ffffffU & ((vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cache_miss_resrv__DOT__addr_table[1U] + << 6U) | ( + vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cache_miss_resrv__DOT__addr_table[0U] + >> 0x1aU))) + == vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__addr_st1 + [0U])) : 0U) << 1U)); + vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cache_miss_resrv__DOT__valid_address_match + = ((0xfffbU & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cache_miss_resrv__DOT__valid_address_match)) + | (((4U & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cache_miss_resrv__DOT__valid_table)) + ? (1U & ((0x3ffffffU & ((vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cache_miss_resrv__DOT__addr_table[2U] + << 0xcU) | + (vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cache_miss_resrv__DOT__addr_table[1U] + >> 0x14U))) + == vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__addr_st1 + [0U])) : 0U) << 2U)); + vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cache_miss_resrv__DOT__valid_address_match + = ((0xfff7U & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cache_miss_resrv__DOT__valid_address_match)) + | (((8U & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cache_miss_resrv__DOT__valid_table)) + ? (1U & ((0x3ffffffU & ((vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cache_miss_resrv__DOT__addr_table[3U] + << 0x12U) + | (vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cache_miss_resrv__DOT__addr_table[2U] + >> 0xeU))) + == vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__addr_st1 + [0U])) : 0U) << 3U)); + vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cache_miss_resrv__DOT__valid_address_match + = ((0xffefU & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cache_miss_resrv__DOT__valid_address_match)) + | (((0x10U & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cache_miss_resrv__DOT__valid_table)) + ? (1U & ((0x3ffffffU & ((vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cache_miss_resrv__DOT__addr_table[4U] + << 0x18U) + | (vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cache_miss_resrv__DOT__addr_table[3U] + >> 8U))) + == vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__addr_st1 + [0U])) : 0U) << 4U)); + vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cache_miss_resrv__DOT__valid_address_match + = ((0xffdfU & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cache_miss_resrv__DOT__valid_address_match)) + | (((0x20U & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cache_miss_resrv__DOT__valid_table)) + ? (1U & ((0x3ffffffU & ((vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cache_miss_resrv__DOT__addr_table[5U] + << 0x1eU) + | (vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cache_miss_resrv__DOT__addr_table[4U] + >> 2U))) + == vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__addr_st1 + [0U])) : 0U) << 5U)); + vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cache_miss_resrv__DOT__valid_address_match + = ((0xffbfU & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cache_miss_resrv__DOT__valid_address_match)) + | (((0x40U & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cache_miss_resrv__DOT__valid_table)) + ? (1U & ((0x3ffffffU & ((vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cache_miss_resrv__DOT__addr_table[5U] + << 4U) | ( + vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cache_miss_resrv__DOT__addr_table[4U] + >> 0x1cU))) + == vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__addr_st1 + [0U])) : 0U) << 6U)); + vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cache_miss_resrv__DOT__valid_address_match + = ((0xff7fU & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cache_miss_resrv__DOT__valid_address_match)) + | (((0x80U & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cache_miss_resrv__DOT__valid_table)) + ? (1U & ((0x3ffffffU & ((vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cache_miss_resrv__DOT__addr_table[6U] + << 0xaU) | + (vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cache_miss_resrv__DOT__addr_table[5U] + >> 0x16U))) + == vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__addr_st1 + [0U])) : 0U) << 7U)); + vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cache_miss_resrv__DOT__valid_address_match + = ((0xfeffU & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cache_miss_resrv__DOT__valid_address_match)) + | (((0x100U & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cache_miss_resrv__DOT__valid_table)) + ? (1U & ((0x3ffffffU & ((vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cache_miss_resrv__DOT__addr_table[7U] + << 0x10U) + | (vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cache_miss_resrv__DOT__addr_table[6U] + >> 0x10U))) + == vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__addr_st1 + [0U])) : 0U) << 8U)); + vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cache_miss_resrv__DOT__valid_address_match + = ((0xfdffU & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cache_miss_resrv__DOT__valid_address_match)) + | (((0x200U & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cache_miss_resrv__DOT__valid_table)) + ? (1U & ((0x3ffffffU & ((vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cache_miss_resrv__DOT__addr_table[8U] + << 0x16U) + | (vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cache_miss_resrv__DOT__addr_table[7U] + >> 0xaU))) + == vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__addr_st1 + [0U])) : 0U) << 9U)); + vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cache_miss_resrv__DOT__valid_address_match + = ((0xfbffU & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cache_miss_resrv__DOT__valid_address_match)) + | (((0x400U & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cache_miss_resrv__DOT__valid_table)) + ? (1U & ((0x3ffffffU & ((vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cache_miss_resrv__DOT__addr_table[9U] + << 0x1cU) + | (vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cache_miss_resrv__DOT__addr_table[8U] + >> 4U))) + == vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__addr_st1 + [0U])) : 0U) << 0xaU)); + vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cache_miss_resrv__DOT__valid_address_match + = ((0xf7ffU & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cache_miss_resrv__DOT__valid_address_match)) + | (((0x800U & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cache_miss_resrv__DOT__valid_table)) + ? (1U & ((0x3ffffffU & ((vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cache_miss_resrv__DOT__addr_table[9U] + << 2U) | ( + vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cache_miss_resrv__DOT__addr_table[8U] + >> 0x1eU))) + == vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__addr_st1 + [0U])) : 0U) << 0xbU)); + vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cache_miss_resrv__DOT__valid_address_match + = ((0xefffU & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cache_miss_resrv__DOT__valid_address_match)) + | (((0x1000U & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cache_miss_resrv__DOT__valid_table)) + ? (1U & ((0x3ffffffU & ((vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cache_miss_resrv__DOT__addr_table[0xaU] + << 8U) | ( + vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cache_miss_resrv__DOT__addr_table[9U] + >> 0x18U))) + == vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__addr_st1 + [0U])) : 0U) << 0xcU)); + vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cache_miss_resrv__DOT__valid_address_match + = ((0xdfffU & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cache_miss_resrv__DOT__valid_address_match)) + | (((0x2000U & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cache_miss_resrv__DOT__valid_table)) + ? (1U & ((0x3ffffffU & ((vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cache_miss_resrv__DOT__addr_table[0xbU] + << 0xeU) | + (vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cache_miss_resrv__DOT__addr_table[0xaU] + >> 0x12U))) + == vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__addr_st1 + [0U])) : 0U) << 0xdU)); + vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cache_miss_resrv__DOT__valid_address_match + = ((0xbfffU & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cache_miss_resrv__DOT__valid_address_match)) + | (((0x4000U & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cache_miss_resrv__DOT__valid_table)) + ? (1U & ((0x3ffffffU & ((vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cache_miss_resrv__DOT__addr_table[0xcU] + << 0x14U) + | (vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cache_miss_resrv__DOT__addr_table[0xbU] + >> 0xcU))) + == vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__addr_st1 + [0U])) : 0U) << 0xeU)); + vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cache_miss_resrv__DOT__valid_address_match + = ((0x7fffU & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cache_miss_resrv__DOT__valid_address_match)) + | (((0x8000U & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cache_miss_resrv__DOT__valid_table)) + ? (1U & ((0x3ffffffU & (vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cache_miss_resrv__DOT__addr_table[0xcU] + >> 6U)) == + vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__addr_st1 + [0U])) : 0U) << 0xfU)); + vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__tag_data_access__DOT____Vcellinp__s0_1_c0__in[0U] + = vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__data + [(0x3fU & vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__addr_st1 + [0U])][0U]; + vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__tag_data_access__DOT____Vcellinp__s0_1_c0__in[1U] + = vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__data + [(0x3fU & vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__addr_st1 + [0U])][1U]; + vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__tag_data_access__DOT____Vcellinp__s0_1_c0__in[2U] + = vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__data + [(0x3fU & vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__addr_st1 + [0U])][2U]; + vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__tag_data_access__DOT____Vcellinp__s0_1_c0__in[3U] + = vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__data + [(0x3fU & vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__addr_st1 + [0U])][3U]; + vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__tag_data_access__DOT____Vcellinp__s0_1_c0__in[4U] + = ((0xfff00000U & (vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__dirtyb + [(0x3fU & vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__addr_st1 + [0U])] << 0x14U)) | vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__tag + [(0x3fU & vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__addr_st1 + [0U])]); + vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__tag_data_access__DOT____Vcellinp__s0_1_c0__in[5U] + = ((0x20U & ((IData)((vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__valid + >> (0x3fU & vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__addr_st1 + [0U]))) << 5U)) | + ((0x10U & ((IData)((vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__dirty + >> (0x3fU & vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__addr_st1 + [0U]))) << 4U)) + | (0xfffffU & (vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__dirtyb + [(0x3fU & vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__addr_st1 + [0U])] >> 0xcU)))); + vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__core_req_arb__DOT__pop_qual + = (1U & ((~ (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__core_req_arb__DOT__out_empty)) + & (~ (IData)((0U != (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__core_req_arb__DOT__use_per_valids)))))); + vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__core_req_arb__DOT__pop_qual + = (1U & ((~ (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__core_req_arb__DOT__out_empty)) + & (~ (IData)((0U != (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__core_req_arb__DOT__use_per_valids)))))); + vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__core_req_arb__DOT__pop_qual + = (1U & ((~ (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__core_req_arb__DOT__out_empty)) + & (~ (IData)((0U != (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__core_req_arb__DOT__use_per_valids)))))); + vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__core_req_arb__DOT__pop_qual + = (1U & ((~ (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__core_req_arb__DOT__out_empty)) + & (~ (IData)((0U != (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__core_req_arb__DOT__use_per_valids)))))); + vlTOPp->VX_cache__DOT__cache_core_rsp_merge__DOT__sel_bank__DOT__genblk2__DOT__refill + = (0U == (IData)(vlTOPp->VX_cache__DOT__cache_core_rsp_merge__DOT__sel_bank__DOT__genblk2__DOT__requests_use)); + vlTOPp->__Vtableidx3 = vlTOPp->VX_cache__DOT__cache_core_rsp_merge__DOT__sel_bank__DOT__genblk2__DOT__requests_use; + vlTOPp->VX_cache__DOT__cache_core_rsp_merge__DOT__main_bank_index + = vlTOPp->__Vtable3_VX_cache__DOT__cache_core_rsp_merge__DOT__main_bank_index + [vlTOPp->__Vtableidx3]; + vlTOPp->VX_cache__DOT__cache_core_rsp_merge__DOT__sel_bank__DOT__grant_valid + = vlTOPp->__Vtable3_VX_cache__DOT__cache_core_rsp_merge__DOT__sel_bank__DOT__grant_valid + [vlTOPp->__Vtableidx3]; + vlTOPp->VX_cache__DOT__cache_core_rsp_merge__DOT__sel_bank__DOT__genblk2__DOT__priority_encoder__DOT__i + = vlTOPp->__Vtable3_VX_cache__DOT__cache_core_rsp_merge__DOT__sel_bank__DOT__genblk2__DOT__priority_encoder__DOT__i + [vlTOPp->__Vtableidx3]; + vlTOPp->__Vtableidx1 = vlTOPp->VX_cache__DOT__cache_dram_req_arb__DOT__dram_fill_arb__DOT__use_per_bqual_bank_dram_fill_req_valid; + vlTOPp->VX_cache__DOT__cache_dram_req_arb__DOT__dram_fill_arb__DOT__qual_request_index + = vlTOPp->__Vtable1_VX_cache__DOT__cache_dram_req_arb__DOT__dram_fill_arb__DOT__qual_request_index + [vlTOPp->__Vtableidx1]; + vlTOPp->VX_cache__DOT__cache_dram_req_arb__DOT__dram_fill_arb__DOT__qual_has_request + = vlTOPp->__Vtable1_VX_cache__DOT__cache_dram_req_arb__DOT__dram_fill_arb__DOT__qual_has_request + [vlTOPp->__Vtableidx1]; + vlTOPp->VX_cache__DOT__cache_dram_req_arb__DOT__dram_fill_arb__DOT__sel_bank__DOT__genblk2__DOT__priority_encoder__DOT__i + = vlTOPp->__Vtable1_VX_cache__DOT__cache_dram_req_arb__DOT__dram_fill_arb__DOT__sel_bank__DOT__genblk2__DOT__priority_encoder__DOT__i + [vlTOPp->__Vtableidx1]; + vlTOPp->VX_cache__DOT__per_bank_snp_rsp_valid = + ((7U & (IData)(vlTOPp->VX_cache__DOT__per_bank_snp_rsp_valid)) + | ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__curr_bank_snp_rsp_valid) + << 3U)); + vlTOPp->VX_cache__DOT__per_bank_dram_wb_req_valid + = ((7U & (IData)(vlTOPp->VX_cache__DOT__per_bank_dram_wb_req_valid)) + | ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__curr_bank_dram_wb_req_valid) + << 3U)); + vlTOPp->VX_cache__DOT__per_bank_snp_rsp_valid = + ((0xbU & (IData)(vlTOPp->VX_cache__DOT__per_bank_snp_rsp_valid)) + | ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__curr_bank_snp_rsp_valid) + << 2U)); + vlTOPp->VX_cache__DOT__per_bank_dram_wb_req_valid + = ((0xbU & (IData)(vlTOPp->VX_cache__DOT__per_bank_dram_wb_req_valid)) + | ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__curr_bank_dram_wb_req_valid) + << 2U)); + vlTOPp->VX_cache__DOT__per_bank_snp_rsp_valid = + ((0xdU & (IData)(vlTOPp->VX_cache__DOT__per_bank_snp_rsp_valid)) + | ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__curr_bank_snp_rsp_valid) + << 1U)); + vlTOPp->VX_cache__DOT__per_bank_dram_wb_req_valid + = ((0xdU & (IData)(vlTOPp->VX_cache__DOT__per_bank_dram_wb_req_valid)) + | ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__curr_bank_dram_wb_req_valid) + << 1U)); + vlTOPp->VX_cache__DOT__per_bank_snp_rsp_valid = + ((0xeU & (IData)(vlTOPp->VX_cache__DOT__per_bank_snp_rsp_valid)) + | (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__curr_bank_snp_rsp_valid)); + vlTOPp->VX_cache__DOT__per_bank_dram_wb_req_valid + = ((0xeU & (IData)(vlTOPp->VX_cache__DOT__per_bank_dram_wb_req_valid)) + | (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__curr_bank_dram_wb_req_valid)); + vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT____Vcellinp__cwb_queue__data_in[0U] + = ((vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__st_1e_2__DOT__value[7U] + << 9U) | (vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__st_1e_2__DOT__value[6U] + >> 0x17U)); + vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT____Vcellinp__cwb_queue__data_in[1U] + = (IData)((VL_ULL(0x3ffffffffff) & (((QData)((IData)( + vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__st_1e_2__DOT__value[2U])) + << 0x39U) + | (((QData)((IData)( + vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__st_1e_2__DOT__value[1U])) + << 0x19U) + | ((QData)((IData)( + vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__st_1e_2__DOT__value[0U])) + >> 7U))))); + vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT____Vcellinp__cwb_queue__data_in[2U] + = ((0xc00U & (vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__st_1e_2__DOT__value[0U] + << 0xaU)) | (IData)(((VL_ULL(0x3ffffffffff) + & (((QData)((IData)( + vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__st_1e_2__DOT__value[2U])) + << 0x39U) + | (((QData)((IData)( + vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__st_1e_2__DOT__value[1U])) + << 0x19U) + | ((QData)((IData)( + vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__st_1e_2__DOT__value[0U])) + >> 7U)))) + >> 0x20U))); + vlTOPp->VX_cache__DOT__per_bank_dram_fill_req_addr[2U] + = ((0xfffffU & vlTOPp->VX_cache__DOT__per_bank_dram_fill_req_addr[2U]) + | (0xfff00000U & (0x300000U | (0xffc00000U + & ((vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__st_1e_2__DOT__value[9U] + << 0x1dU) + | (0x1fc00000U + & (vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__st_1e_2__DOT__value[8U] + >> 3U))))))); + vlTOPp->VX_cache__DOT__per_bank_dram_fill_req_addr[3U] + = (0xffffU & (vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__st_1e_2__DOT__value[9U] + >> 3U)); + vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cwbq_push_unqual + = (1U & ((((vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__st_1e_2__DOT__value[9U] + >> 0x13U) & (~ (vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__st_1e_2__DOT__value[2U] + >> 2U))) & (~ ( + vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__st_1e_2__DOT__value[9U] + >> 0x14U))) + & (~ (vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__st_1e_2__DOT__value[9U] + >> 0x17U)))); + vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__dwbq_is_snp_in + = (1U & (((vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__st_1e_2__DOT__value[9U] + >> 0x17U) & (vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__st_1e_2__DOT__value[9U] + >> 0x13U)) & (~ (vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__st_1e_2__DOT__value[9U] + >> 0x18U)))); + vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__dwbq_is_dwb_in + = (1U & ((((vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__st_1e_2__DOT__value[9U] + >> 0x13U) & (vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__st_1e_2__DOT__value[2U] + >> 2U)) & (vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__st_1e_2__DOT__value[2U] + >> 1U)) + | (vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__st_1e_2__DOT__value[9U] + >> 0x15U))); + vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__miss_add_because_miss + = (1U & (((vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__st_1e_2__DOT__value[9U] + >> 0x13U) & (~ (vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__st_1e_2__DOT__value[9U] + >> 0x17U))) & (vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__st_1e_2__DOT__value[2U] + >> 2U))); + vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT____Vcellinp__cwb_queue__data_in[0U] + = ((vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__st_1e_2__DOT__value[7U] + << 9U) | (vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__st_1e_2__DOT__value[6U] + >> 0x17U)); + vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT____Vcellinp__cwb_queue__data_in[1U] + = (IData)((VL_ULL(0x3ffffffffff) & (((QData)((IData)( + vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__st_1e_2__DOT__value[2U])) + << 0x39U) + | (((QData)((IData)( + vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__st_1e_2__DOT__value[1U])) + << 0x19U) + | ((QData)((IData)( + vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__st_1e_2__DOT__value[0U])) + >> 7U))))); + vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT____Vcellinp__cwb_queue__data_in[2U] + = ((0xc00U & (vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__st_1e_2__DOT__value[0U] + << 0xaU)) | (IData)(((VL_ULL(0x3ffffffffff) + & (((QData)((IData)( + vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__st_1e_2__DOT__value[2U])) + << 0x39U) + | (((QData)((IData)( + vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__st_1e_2__DOT__value[1U])) + << 0x19U) + | ((QData)((IData)( + vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__st_1e_2__DOT__value[0U])) + >> 7U)))) + >> 0x20U))); + vlTOPp->VX_cache__DOT__per_bank_dram_fill_req_addr[1U] + = ((0xffffffU & vlTOPp->VX_cache__DOT__per_bank_dram_fill_req_addr[1U]) + | (0xff000000U & (0x2000000U | (0xfc000000U + & (vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__st_1e_2__DOT__value[8U] + << 1U))))); + vlTOPp->VX_cache__DOT__per_bank_dram_fill_req_addr[2U] + = ((0xfff00000U & vlTOPp->VX_cache__DOT__per_bank_dram_fill_req_addr[2U]) + | (0xfffffU & ((0xfffffeU & (vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__st_1e_2__DOT__value[9U] + << 1U)) | (1U + & (vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__st_1e_2__DOT__value[8U] + >> 0x1fU))))); + vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__cwbq_push_unqual + = (1U & ((((vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__st_1e_2__DOT__value[9U] + >> 0x13U) & (~ (vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__st_1e_2__DOT__value[2U] + >> 2U))) & (~ ( + vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__st_1e_2__DOT__value[9U] + >> 0x14U))) + & (~ (vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__st_1e_2__DOT__value[9U] + >> 0x17U)))); + vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__dwbq_is_snp_in + = (1U & (((vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__st_1e_2__DOT__value[9U] + >> 0x17U) & (vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__st_1e_2__DOT__value[9U] + >> 0x13U)) & (~ (vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__st_1e_2__DOT__value[9U] + >> 0x18U)))); + vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__dwbq_is_dwb_in + = (1U & ((((vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__st_1e_2__DOT__value[9U] + >> 0x13U) & (vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__st_1e_2__DOT__value[2U] + >> 2U)) & (vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__st_1e_2__DOT__value[2U] + >> 1U)) + | (vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__st_1e_2__DOT__value[9U] + >> 0x15U))); + vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__miss_add_because_miss + = (1U & (((vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__st_1e_2__DOT__value[9U] + >> 0x13U) & (~ (vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__st_1e_2__DOT__value[9U] + >> 0x17U))) & (vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__st_1e_2__DOT__value[2U] + >> 2U))); + vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT____Vcellinp__cwb_queue__data_in[0U] + = ((vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__st_1e_2__DOT__value[7U] + << 9U) | (vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__st_1e_2__DOT__value[6U] + >> 0x17U)); + vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT____Vcellinp__cwb_queue__data_in[1U] + = (IData)((VL_ULL(0x3ffffffffff) & (((QData)((IData)( + vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__st_1e_2__DOT__value[2U])) + << 0x39U) + | (((QData)((IData)( + vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__st_1e_2__DOT__value[1U])) + << 0x19U) + | ((QData)((IData)( + vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__st_1e_2__DOT__value[0U])) + >> 7U))))); + vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT____Vcellinp__cwb_queue__data_in[2U] + = ((0xc00U & (vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__st_1e_2__DOT__value[0U] + << 0xaU)) | (IData)(((VL_ULL(0x3ffffffffff) + & (((QData)((IData)( + vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__st_1e_2__DOT__value[2U])) + << 0x39U) + | (((QData)((IData)( + vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__st_1e_2__DOT__value[1U])) + << 0x19U) + | ((QData)((IData)( + vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__st_1e_2__DOT__value[0U])) + >> 7U)))) + >> 0x20U))); + vlTOPp->VX_cache__DOT__per_bank_dram_fill_req_addr[0U] + = ((0xfffffffU & vlTOPp->VX_cache__DOT__per_bank_dram_fill_req_addr[0U]) + | (0xf0000000U & (0x10000000U | (0xc0000000U + & (vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__st_1e_2__DOT__value[8U] + << 5U))))); + vlTOPp->VX_cache__DOT__per_bank_dram_fill_req_addr[1U] + = ((0xff000000U & vlTOPp->VX_cache__DOT__per_bank_dram_fill_req_addr[1U]) + | (0xffffffU & ((0xfffffe0U & (vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__st_1e_2__DOT__value[9U] + << 5U)) | + (0x1fU & (vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__st_1e_2__DOT__value[8U] + >> 0x1bU))))); + vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__cwbq_push_unqual + = (1U & ((((vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__st_1e_2__DOT__value[9U] + >> 0x13U) & (~ (vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__st_1e_2__DOT__value[2U] + >> 2U))) & (~ ( + vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__st_1e_2__DOT__value[9U] + >> 0x14U))) + & (~ (vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__st_1e_2__DOT__value[9U] + >> 0x17U)))); + vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__dwbq_is_snp_in + = (1U & (((vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__st_1e_2__DOT__value[9U] + >> 0x17U) & (vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__st_1e_2__DOT__value[9U] + >> 0x13U)) & (~ (vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__st_1e_2__DOT__value[9U] + >> 0x18U)))); + vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__dwbq_is_dwb_in + = (1U & ((((vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__st_1e_2__DOT__value[9U] + >> 0x13U) & (vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__st_1e_2__DOT__value[2U] + >> 2U)) & (vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__st_1e_2__DOT__value[2U] + >> 1U)) + | (vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__st_1e_2__DOT__value[9U] + >> 0x15U))); + vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__miss_add_because_miss + = (1U & (((vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__st_1e_2__DOT__value[9U] + >> 0x13U) & (~ (vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__st_1e_2__DOT__value[9U] + >> 0x17U))) & (vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__st_1e_2__DOT__value[2U] + >> 2U))); + vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT____Vcellinp__cwb_queue__data_in[0U] + = ((vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__st_1e_2__DOT__value[7U] + << 9U) | (vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__st_1e_2__DOT__value[6U] + >> 0x17U)); + vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT____Vcellinp__cwb_queue__data_in[1U] + = (IData)((VL_ULL(0x3ffffffffff) & (((QData)((IData)( + vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__st_1e_2__DOT__value[2U])) + << 0x39U) + | (((QData)((IData)( + vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__st_1e_2__DOT__value[1U])) + << 0x19U) + | ((QData)((IData)( + vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__st_1e_2__DOT__value[0U])) + >> 7U))))); + vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT____Vcellinp__cwb_queue__data_in[2U] + = ((0xc00U & (vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__st_1e_2__DOT__value[0U] + << 0xaU)) | (IData)(((VL_ULL(0x3ffffffffff) + & (((QData)((IData)( + vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__st_1e_2__DOT__value[2U])) + << 0x39U) + | (((QData)((IData)( + vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__st_1e_2__DOT__value[1U])) + << 0x19U) + | ((QData)((IData)( + vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__st_1e_2__DOT__value[0U])) + >> 7U)))) + >> 0x20U))); + vlTOPp->VX_cache__DOT__per_bank_dram_fill_req_addr[0U] + = ((0xf0000000U & vlTOPp->VX_cache__DOT__per_bank_dram_fill_req_addr[0U]) + | (0xffffffcU & ((vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__st_1e_2__DOT__value[9U] + << 9U) | (0x1fcU & (vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__st_1e_2__DOT__value[8U] + >> 0x17U))))); + vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cwbq_push_unqual + = (1U & ((((vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__st_1e_2__DOT__value[9U] + >> 0x13U) & (~ (vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__st_1e_2__DOT__value[2U] + >> 2U))) & (~ ( + vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__st_1e_2__DOT__value[9U] + >> 0x14U))) + & (~ (vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__st_1e_2__DOT__value[9U] + >> 0x17U)))); + vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__dwbq_is_snp_in + = (1U & (((vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__st_1e_2__DOT__value[9U] + >> 0x17U) & (vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__st_1e_2__DOT__value[9U] + >> 0x13U)) & (~ (vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__st_1e_2__DOT__value[9U] + >> 0x18U)))); + vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__dwbq_is_dwb_in + = (1U & ((((vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__st_1e_2__DOT__value[9U] + >> 0x13U) & (vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__st_1e_2__DOT__value[2U] + >> 2U)) & (vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__st_1e_2__DOT__value[2U] + >> 1U)) + | (vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__st_1e_2__DOT__value[9U] + >> 0x15U))); + vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__miss_add_because_miss + = (1U & (((vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__st_1e_2__DOT__value[9U] + >> 0x13U) & (~ (vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__st_1e_2__DOT__value[9U] + >> 0x17U))) & (vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__st_1e_2__DOT__value[2U] + >> 2U))); + vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__reqq_pop_unqual + = (((((((0xbU >= (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cache_miss_resrv__DOT__size)) + & (~ (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cache_miss_resrv__DOT__dequeue_possible))) + & (~ (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__dfpq_pop_unqual))) + & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__core_req_arb__DOT__qual_has_request)) + & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__core_req_arb__DOT__qual_has_request)) + & (~ vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__is_fill_st1 + [0U])) & (~ (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__is_fill_in_pipe))); + vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cache_miss_resrv__DOT__make_ready + = ((0xfffeU & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cache_miss_resrv__DOT__make_ready)) + | (vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__is_fill_st1 + [0U] & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cache_miss_resrv__DOT__valid_address_match))); + vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cache_miss_resrv__DOT__make_ready + = ((0xfffdU & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cache_miss_resrv__DOT__make_ready)) + | (0xfffffffeU & ((vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__is_fill_st1 + [0U] << 1U) & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cache_miss_resrv__DOT__valid_address_match)))); + vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cache_miss_resrv__DOT__make_ready + = ((0xfffbU & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cache_miss_resrv__DOT__make_ready)) + | (0xfffffffcU & ((vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__is_fill_st1 + [0U] << 2U) & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cache_miss_resrv__DOT__valid_address_match)))); + vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cache_miss_resrv__DOT__make_ready + = ((0xfff7U & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cache_miss_resrv__DOT__make_ready)) + | (0xfffffff8U & ((vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__is_fill_st1 + [0U] << 3U) & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cache_miss_resrv__DOT__valid_address_match)))); + vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cache_miss_resrv__DOT__make_ready + = ((0xffefU & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cache_miss_resrv__DOT__make_ready)) + | (0xfffffff0U & ((vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__is_fill_st1 + [0U] << 4U) & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cache_miss_resrv__DOT__valid_address_match)))); + vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cache_miss_resrv__DOT__make_ready + = ((0xffdfU & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cache_miss_resrv__DOT__make_ready)) + | (0xffffffe0U & ((vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__is_fill_st1 + [0U] << 5U) & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cache_miss_resrv__DOT__valid_address_match)))); + vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cache_miss_resrv__DOT__make_ready + = ((0xffbfU & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cache_miss_resrv__DOT__make_ready)) + | (0xffffffc0U & ((vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__is_fill_st1 + [0U] << 6U) & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cache_miss_resrv__DOT__valid_address_match)))); + vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cache_miss_resrv__DOT__make_ready + = ((0xff7fU & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cache_miss_resrv__DOT__make_ready)) + | (0xffffff80U & ((vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__is_fill_st1 + [0U] << 7U) & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cache_miss_resrv__DOT__valid_address_match)))); + vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cache_miss_resrv__DOT__make_ready + = ((0xfeffU & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cache_miss_resrv__DOT__make_ready)) + | (0xffffff00U & ((vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__is_fill_st1 + [0U] << 8U) & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cache_miss_resrv__DOT__valid_address_match)))); + vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cache_miss_resrv__DOT__make_ready + = ((0xfdffU & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cache_miss_resrv__DOT__make_ready)) + | (0xfffffe00U & ((vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__is_fill_st1 + [0U] << 9U) & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cache_miss_resrv__DOT__valid_address_match)))); + vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cache_miss_resrv__DOT__make_ready + = ((0xfbffU & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cache_miss_resrv__DOT__make_ready)) + | (0xfffffc00U & ((vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__is_fill_st1 + [0U] << 0xaU) & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cache_miss_resrv__DOT__valid_address_match)))); + vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cache_miss_resrv__DOT__make_ready + = ((0xf7ffU & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cache_miss_resrv__DOT__make_ready)) + | (0xfffff800U & ((vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__is_fill_st1 + [0U] << 0xbU) & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cache_miss_resrv__DOT__valid_address_match)))); + vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cache_miss_resrv__DOT__make_ready + = ((0xefffU & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cache_miss_resrv__DOT__make_ready)) + | (0xfffff000U & ((vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__is_fill_st1 + [0U] << 0xcU) & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cache_miss_resrv__DOT__valid_address_match)))); + vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cache_miss_resrv__DOT__make_ready + = ((0xdfffU & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cache_miss_resrv__DOT__make_ready)) + | (0xffffe000U & ((vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__is_fill_st1 + [0U] << 0xdU) & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cache_miss_resrv__DOT__valid_address_match)))); + vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cache_miss_resrv__DOT__make_ready + = ((0xbfffU & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cache_miss_resrv__DOT__make_ready)) + | (0xffffc000U & ((vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__is_fill_st1 + [0U] << 0xeU) & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cache_miss_resrv__DOT__valid_address_match)))); + vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cache_miss_resrv__DOT__make_ready + = ((0x7fffU & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cache_miss_resrv__DOT__make_ready)) + | (0xffff8000U & ((vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__is_fill_st1 + [0U] << 0xfU) & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cache_miss_resrv__DOT__valid_address_match)))); + vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__tag_data_access__DOT__read_dirtyb_st1c[0U] + = (0xffffU & ((vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__tag_data_access__DOT____Vcellinp__s0_1_c0__in[5U] + << 0xcU) | (vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__tag_data_access__DOT____Vcellinp__s0_1_c0__in[4U] + >> 0x14U))); + vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__tag_data_access__DOT__read_data_st1c[0U][0U] + = vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__tag_data_access__DOT____Vcellinp__s0_1_c0__in[0U]; + vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__tag_data_access__DOT__read_data_st1c[0U][1U] + = vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__tag_data_access__DOT____Vcellinp__s0_1_c0__in[1U]; + vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__tag_data_access__DOT__read_data_st1c[0U][2U] + = vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__tag_data_access__DOT____Vcellinp__s0_1_c0__in[2U]; + vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__tag_data_access__DOT__read_data_st1c[0U][3U] + = vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__tag_data_access__DOT____Vcellinp__s0_1_c0__in[3U]; + vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__tag_data_access__DOT__read_dirty_st1c[0U] + = (1U & (vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__tag_data_access__DOT____Vcellinp__s0_1_c0__in[5U] + >> 4U)); + vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__tag_data_access__DOT__read_valid_st1c[0U] + = (1U & (vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__tag_data_access__DOT____Vcellinp__s0_1_c0__in[5U] + >> 5U)); + vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__tag_data_access__DOT__read_tag_st1c[0U] + = (0xfffffU & vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__tag_data_access__DOT____Vcellinp__s0_1_c0__in[4U]); + vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__reqq_pop_unqual + = (((((((0xbU >= (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__cache_miss_resrv__DOT__size)) + & (~ (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__cache_miss_resrv__DOT__dequeue_possible))) + & (~ (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__dfpq_pop_unqual))) + & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__core_req_arb__DOT__qual_has_request)) + & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__core_req_arb__DOT__qual_has_request)) + & (~ vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__is_fill_st1 + [0U])) & (~ (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__is_fill_in_pipe))); + vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__cache_miss_resrv__DOT__make_ready + = ((0xfffeU & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__cache_miss_resrv__DOT__make_ready)) + | (vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__is_fill_st1 + [0U] & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__cache_miss_resrv__DOT__valid_address_match))); + vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__cache_miss_resrv__DOT__make_ready + = ((0xfffdU & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__cache_miss_resrv__DOT__make_ready)) + | (0xfffffffeU & ((vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__is_fill_st1 + [0U] << 1U) & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__cache_miss_resrv__DOT__valid_address_match)))); + vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__cache_miss_resrv__DOT__make_ready + = ((0xfffbU & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__cache_miss_resrv__DOT__make_ready)) + | (0xfffffffcU & ((vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__is_fill_st1 + [0U] << 2U) & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__cache_miss_resrv__DOT__valid_address_match)))); + vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__cache_miss_resrv__DOT__make_ready + = ((0xfff7U & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__cache_miss_resrv__DOT__make_ready)) + | (0xfffffff8U & ((vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__is_fill_st1 + [0U] << 3U) & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__cache_miss_resrv__DOT__valid_address_match)))); + vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__cache_miss_resrv__DOT__make_ready + = ((0xffefU & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__cache_miss_resrv__DOT__make_ready)) + | (0xfffffff0U & ((vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__is_fill_st1 + [0U] << 4U) & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__cache_miss_resrv__DOT__valid_address_match)))); + vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__cache_miss_resrv__DOT__make_ready + = ((0xffdfU & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__cache_miss_resrv__DOT__make_ready)) + | (0xffffffe0U & ((vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__is_fill_st1 + [0U] << 5U) & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__cache_miss_resrv__DOT__valid_address_match)))); + vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__cache_miss_resrv__DOT__make_ready + = ((0xffbfU & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__cache_miss_resrv__DOT__make_ready)) + | (0xffffffc0U & ((vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__is_fill_st1 + [0U] << 6U) & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__cache_miss_resrv__DOT__valid_address_match)))); + vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__cache_miss_resrv__DOT__make_ready + = ((0xff7fU & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__cache_miss_resrv__DOT__make_ready)) + | (0xffffff80U & ((vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__is_fill_st1 + [0U] << 7U) & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__cache_miss_resrv__DOT__valid_address_match)))); + vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__cache_miss_resrv__DOT__make_ready + = ((0xfeffU & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__cache_miss_resrv__DOT__make_ready)) + | (0xffffff00U & ((vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__is_fill_st1 + [0U] << 8U) & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__cache_miss_resrv__DOT__valid_address_match)))); + vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__cache_miss_resrv__DOT__make_ready + = ((0xfdffU & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__cache_miss_resrv__DOT__make_ready)) + | (0xfffffe00U & ((vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__is_fill_st1 + [0U] << 9U) & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__cache_miss_resrv__DOT__valid_address_match)))); + vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__cache_miss_resrv__DOT__make_ready + = ((0xfbffU & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__cache_miss_resrv__DOT__make_ready)) + | (0xfffffc00U & ((vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__is_fill_st1 + [0U] << 0xaU) & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__cache_miss_resrv__DOT__valid_address_match)))); + vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__cache_miss_resrv__DOT__make_ready + = ((0xf7ffU & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__cache_miss_resrv__DOT__make_ready)) + | (0xfffff800U & ((vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__is_fill_st1 + [0U] << 0xbU) & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__cache_miss_resrv__DOT__valid_address_match)))); + vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__cache_miss_resrv__DOT__make_ready + = ((0xefffU & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__cache_miss_resrv__DOT__make_ready)) + | (0xfffff000U & ((vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__is_fill_st1 + [0U] << 0xcU) & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__cache_miss_resrv__DOT__valid_address_match)))); + vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__cache_miss_resrv__DOT__make_ready + = ((0xdfffU & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__cache_miss_resrv__DOT__make_ready)) + | (0xffffe000U & ((vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__is_fill_st1 + [0U] << 0xdU) & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__cache_miss_resrv__DOT__valid_address_match)))); + vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__cache_miss_resrv__DOT__make_ready + = ((0xbfffU & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__cache_miss_resrv__DOT__make_ready)) + | (0xffffc000U & ((vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__is_fill_st1 + [0U] << 0xeU) & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__cache_miss_resrv__DOT__valid_address_match)))); + vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__cache_miss_resrv__DOT__make_ready + = ((0x7fffU & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__cache_miss_resrv__DOT__make_ready)) + | (0xffff8000U & ((vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__is_fill_st1 + [0U] << 0xfU) & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__cache_miss_resrv__DOT__valid_address_match)))); + vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__tag_data_access__DOT__read_dirtyb_st1c[0U] + = (0xffffU & ((vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__tag_data_access__DOT____Vcellinp__s0_1_c0__in[5U] + << 0xcU) | (vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__tag_data_access__DOT____Vcellinp__s0_1_c0__in[4U] + >> 0x14U))); + vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__tag_data_access__DOT__read_data_st1c[0U][0U] + = vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__tag_data_access__DOT____Vcellinp__s0_1_c0__in[0U]; + vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__tag_data_access__DOT__read_data_st1c[0U][1U] + = vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__tag_data_access__DOT____Vcellinp__s0_1_c0__in[1U]; + vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__tag_data_access__DOT__read_data_st1c[0U][2U] + = vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__tag_data_access__DOT____Vcellinp__s0_1_c0__in[2U]; + vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__tag_data_access__DOT__read_data_st1c[0U][3U] + = vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__tag_data_access__DOT____Vcellinp__s0_1_c0__in[3U]; + vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__tag_data_access__DOT__read_dirty_st1c[0U] + = (1U & (vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__tag_data_access__DOT____Vcellinp__s0_1_c0__in[5U] + >> 4U)); + vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__tag_data_access__DOT__read_valid_st1c[0U] + = (1U & (vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__tag_data_access__DOT____Vcellinp__s0_1_c0__in[5U] + >> 5U)); + vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__tag_data_access__DOT__read_tag_st1c[0U] + = (0xfffffU & vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__tag_data_access__DOT____Vcellinp__s0_1_c0__in[4U]); + vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__reqq_pop_unqual + = (((((((0xbU >= (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__cache_miss_resrv__DOT__size)) + & (~ (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__cache_miss_resrv__DOT__dequeue_possible))) + & (~ (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__dfpq_pop_unqual))) + & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__core_req_arb__DOT__qual_has_request)) + & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__core_req_arb__DOT__qual_has_request)) + & (~ vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__is_fill_st1 + [0U])) & (~ (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__is_fill_in_pipe))); + vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__cache_miss_resrv__DOT__make_ready + = ((0xfffeU & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__cache_miss_resrv__DOT__make_ready)) + | (vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__is_fill_st1 + [0U] & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__cache_miss_resrv__DOT__valid_address_match))); + vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__cache_miss_resrv__DOT__make_ready + = ((0xfffdU & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__cache_miss_resrv__DOT__make_ready)) + | (0xfffffffeU & ((vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__is_fill_st1 + [0U] << 1U) & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__cache_miss_resrv__DOT__valid_address_match)))); + vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__cache_miss_resrv__DOT__make_ready + = ((0xfffbU & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__cache_miss_resrv__DOT__make_ready)) + | (0xfffffffcU & ((vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__is_fill_st1 + [0U] << 2U) & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__cache_miss_resrv__DOT__valid_address_match)))); + vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__cache_miss_resrv__DOT__make_ready + = ((0xfff7U & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__cache_miss_resrv__DOT__make_ready)) + | (0xfffffff8U & ((vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__is_fill_st1 + [0U] << 3U) & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__cache_miss_resrv__DOT__valid_address_match)))); + vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__cache_miss_resrv__DOT__make_ready + = ((0xffefU & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__cache_miss_resrv__DOT__make_ready)) + | (0xfffffff0U & ((vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__is_fill_st1 + [0U] << 4U) & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__cache_miss_resrv__DOT__valid_address_match)))); + vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__cache_miss_resrv__DOT__make_ready + = ((0xffdfU & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__cache_miss_resrv__DOT__make_ready)) + | (0xffffffe0U & ((vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__is_fill_st1 + [0U] << 5U) & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__cache_miss_resrv__DOT__valid_address_match)))); + vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__cache_miss_resrv__DOT__make_ready + = ((0xffbfU & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__cache_miss_resrv__DOT__make_ready)) + | (0xffffffc0U & ((vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__is_fill_st1 + [0U] << 6U) & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__cache_miss_resrv__DOT__valid_address_match)))); + vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__cache_miss_resrv__DOT__make_ready + = ((0xff7fU & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__cache_miss_resrv__DOT__make_ready)) + | (0xffffff80U & ((vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__is_fill_st1 + [0U] << 7U) & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__cache_miss_resrv__DOT__valid_address_match)))); + vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__cache_miss_resrv__DOT__make_ready + = ((0xfeffU & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__cache_miss_resrv__DOT__make_ready)) + | (0xffffff00U & ((vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__is_fill_st1 + [0U] << 8U) & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__cache_miss_resrv__DOT__valid_address_match)))); + vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__cache_miss_resrv__DOT__make_ready + = ((0xfdffU & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__cache_miss_resrv__DOT__make_ready)) + | (0xfffffe00U & ((vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__is_fill_st1 + [0U] << 9U) & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__cache_miss_resrv__DOT__valid_address_match)))); + vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__cache_miss_resrv__DOT__make_ready + = ((0xfbffU & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__cache_miss_resrv__DOT__make_ready)) + | (0xfffffc00U & ((vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__is_fill_st1 + [0U] << 0xaU) & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__cache_miss_resrv__DOT__valid_address_match)))); + vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__cache_miss_resrv__DOT__make_ready + = ((0xf7ffU & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__cache_miss_resrv__DOT__make_ready)) + | (0xfffff800U & ((vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__is_fill_st1 + [0U] << 0xbU) & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__cache_miss_resrv__DOT__valid_address_match)))); + vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__cache_miss_resrv__DOT__make_ready + = ((0xefffU & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__cache_miss_resrv__DOT__make_ready)) + | (0xfffff000U & ((vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__is_fill_st1 + [0U] << 0xcU) & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__cache_miss_resrv__DOT__valid_address_match)))); + vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__cache_miss_resrv__DOT__make_ready + = ((0xdfffU & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__cache_miss_resrv__DOT__make_ready)) + | (0xffffe000U & ((vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__is_fill_st1 + [0U] << 0xdU) & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__cache_miss_resrv__DOT__valid_address_match)))); + vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__cache_miss_resrv__DOT__make_ready + = ((0xbfffU & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__cache_miss_resrv__DOT__make_ready)) + | (0xffffc000U & ((vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__is_fill_st1 + [0U] << 0xeU) & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__cache_miss_resrv__DOT__valid_address_match)))); + vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__cache_miss_resrv__DOT__make_ready + = ((0x7fffU & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__cache_miss_resrv__DOT__make_ready)) + | (0xffff8000U & ((vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__is_fill_st1 + [0U] << 0xfU) & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__cache_miss_resrv__DOT__valid_address_match)))); + vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__tag_data_access__DOT__read_dirtyb_st1c[0U] + = (0xffffU & ((vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__tag_data_access__DOT____Vcellinp__s0_1_c0__in[5U] + << 0xcU) | (vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__tag_data_access__DOT____Vcellinp__s0_1_c0__in[4U] + >> 0x14U))); + vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__tag_data_access__DOT__read_data_st1c[0U][0U] + = vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__tag_data_access__DOT____Vcellinp__s0_1_c0__in[0U]; + vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__tag_data_access__DOT__read_data_st1c[0U][1U] + = vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__tag_data_access__DOT____Vcellinp__s0_1_c0__in[1U]; + vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__tag_data_access__DOT__read_data_st1c[0U][2U] + = vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__tag_data_access__DOT____Vcellinp__s0_1_c0__in[2U]; + vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__tag_data_access__DOT__read_data_st1c[0U][3U] + = vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__tag_data_access__DOT____Vcellinp__s0_1_c0__in[3U]; + vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__tag_data_access__DOT__read_dirty_st1c[0U] + = (1U & (vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__tag_data_access__DOT____Vcellinp__s0_1_c0__in[5U] + >> 4U)); + vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__tag_data_access__DOT__read_valid_st1c[0U] + = (1U & (vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__tag_data_access__DOT____Vcellinp__s0_1_c0__in[5U] + >> 5U)); + vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__tag_data_access__DOT__read_tag_st1c[0U] + = (0xfffffU & vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__tag_data_access__DOT____Vcellinp__s0_1_c0__in[4U]); + vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__reqq_pop_unqual + = (((((((0xbU >= (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cache_miss_resrv__DOT__size)) + & (~ (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cache_miss_resrv__DOT__dequeue_possible))) + & (~ (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__dfpq_pop_unqual))) + & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__core_req_arb__DOT__qual_has_request)) + & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__core_req_arb__DOT__qual_has_request)) + & (~ vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__is_fill_st1 + [0U])) & (~ (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__is_fill_in_pipe))); + vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cache_miss_resrv__DOT__make_ready + = ((0xfffeU & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cache_miss_resrv__DOT__make_ready)) + | (vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__is_fill_st1 + [0U] & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cache_miss_resrv__DOT__valid_address_match))); + vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cache_miss_resrv__DOT__make_ready + = ((0xfffdU & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cache_miss_resrv__DOT__make_ready)) + | (0xfffffffeU & ((vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__is_fill_st1 + [0U] << 1U) & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cache_miss_resrv__DOT__valid_address_match)))); + vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cache_miss_resrv__DOT__make_ready + = ((0xfffbU & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cache_miss_resrv__DOT__make_ready)) + | (0xfffffffcU & ((vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__is_fill_st1 + [0U] << 2U) & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cache_miss_resrv__DOT__valid_address_match)))); + vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cache_miss_resrv__DOT__make_ready + = ((0xfff7U & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cache_miss_resrv__DOT__make_ready)) + | (0xfffffff8U & ((vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__is_fill_st1 + [0U] << 3U) & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cache_miss_resrv__DOT__valid_address_match)))); + vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cache_miss_resrv__DOT__make_ready + = ((0xffefU & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cache_miss_resrv__DOT__make_ready)) + | (0xfffffff0U & ((vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__is_fill_st1 + [0U] << 4U) & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cache_miss_resrv__DOT__valid_address_match)))); + vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cache_miss_resrv__DOT__make_ready + = ((0xffdfU & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cache_miss_resrv__DOT__make_ready)) + | (0xffffffe0U & ((vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__is_fill_st1 + [0U] << 5U) & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cache_miss_resrv__DOT__valid_address_match)))); + vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cache_miss_resrv__DOT__make_ready + = ((0xffbfU & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cache_miss_resrv__DOT__make_ready)) + | (0xffffffc0U & ((vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__is_fill_st1 + [0U] << 6U) & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cache_miss_resrv__DOT__valid_address_match)))); + vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cache_miss_resrv__DOT__make_ready + = ((0xff7fU & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cache_miss_resrv__DOT__make_ready)) + | (0xffffff80U & ((vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__is_fill_st1 + [0U] << 7U) & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cache_miss_resrv__DOT__valid_address_match)))); + vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cache_miss_resrv__DOT__make_ready + = ((0xfeffU & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cache_miss_resrv__DOT__make_ready)) + | (0xffffff00U & ((vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__is_fill_st1 + [0U] << 8U) & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cache_miss_resrv__DOT__valid_address_match)))); + vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cache_miss_resrv__DOT__make_ready + = ((0xfdffU & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cache_miss_resrv__DOT__make_ready)) + | (0xfffffe00U & ((vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__is_fill_st1 + [0U] << 9U) & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cache_miss_resrv__DOT__valid_address_match)))); + vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cache_miss_resrv__DOT__make_ready + = ((0xfbffU & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cache_miss_resrv__DOT__make_ready)) + | (0xfffffc00U & ((vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__is_fill_st1 + [0U] << 0xaU) & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cache_miss_resrv__DOT__valid_address_match)))); + vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cache_miss_resrv__DOT__make_ready + = ((0xf7ffU & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cache_miss_resrv__DOT__make_ready)) + | (0xfffff800U & ((vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__is_fill_st1 + [0U] << 0xbU) & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cache_miss_resrv__DOT__valid_address_match)))); + vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cache_miss_resrv__DOT__make_ready + = ((0xefffU & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cache_miss_resrv__DOT__make_ready)) + | (0xfffff000U & ((vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__is_fill_st1 + [0U] << 0xcU) & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cache_miss_resrv__DOT__valid_address_match)))); + vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cache_miss_resrv__DOT__make_ready + = ((0xdfffU & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cache_miss_resrv__DOT__make_ready)) + | (0xffffe000U & ((vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__is_fill_st1 + [0U] << 0xdU) & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cache_miss_resrv__DOT__valid_address_match)))); + vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cache_miss_resrv__DOT__make_ready + = ((0xbfffU & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cache_miss_resrv__DOT__make_ready)) + | (0xffffc000U & ((vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__is_fill_st1 + [0U] << 0xeU) & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cache_miss_resrv__DOT__valid_address_match)))); + vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cache_miss_resrv__DOT__make_ready + = ((0x7fffU & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cache_miss_resrv__DOT__make_ready)) + | (0xffff8000U & ((vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__is_fill_st1 + [0U] << 0xfU) & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cache_miss_resrv__DOT__valid_address_match)))); + vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__tag_data_access__DOT__read_dirtyb_st1c[0U] + = (0xffffU & ((vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__tag_data_access__DOT____Vcellinp__s0_1_c0__in[5U] + << 0xcU) | (vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__tag_data_access__DOT____Vcellinp__s0_1_c0__in[4U] + >> 0x14U))); + vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__tag_data_access__DOT__read_data_st1c[0U][0U] + = vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__tag_data_access__DOT____Vcellinp__s0_1_c0__in[0U]; + vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__tag_data_access__DOT__read_data_st1c[0U][1U] + = vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__tag_data_access__DOT____Vcellinp__s0_1_c0__in[1U]; + vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__tag_data_access__DOT__read_data_st1c[0U][2U] + = vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__tag_data_access__DOT____Vcellinp__s0_1_c0__in[2U]; + vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__tag_data_access__DOT__read_data_st1c[0U][3U] + = vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__tag_data_access__DOT____Vcellinp__s0_1_c0__in[3U]; + vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__tag_data_access__DOT__read_dirty_st1c[0U] + = (1U & (vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__tag_data_access__DOT____Vcellinp__s0_1_c0__in[5U] + >> 4U)); + vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__tag_data_access__DOT__read_valid_st1c[0U] + = (1U & (vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__tag_data_access__DOT____Vcellinp__s0_1_c0__in[5U] + >> 5U)); + vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__tag_data_access__DOT__read_tag_st1c[0U] + = (0xfffffU & vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__tag_data_access__DOT____Vcellinp__s0_1_c0__in[4U]); + vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__reading + = ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__core_req_arb__DOT__pop_qual) + & (~ (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__empty_r))); + vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__reading + = ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__core_req_arb__DOT__pop_qual) + & (~ (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__empty_r))); + vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__reading + = ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__core_req_arb__DOT__pop_qual) + & (~ (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__empty_r))); + vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__reading + = ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__core_req_arb__DOT__pop_qual) + & (~ (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__empty_r))); + vlTOPp->core_rsp_tag = ((0xa7U >= (0xffU & ((IData)(0x2aU) + * (IData)(vlTOPp->VX_cache__DOT__cache_core_rsp_merge__DOT__main_bank_index)))) + ? (VL_ULL(0x3ffffffffff) + & (((0U == (0x1fU & + ((IData)(0x2aU) + * (IData)(vlTOPp->VX_cache__DOT__cache_core_rsp_merge__DOT__main_bank_index)))) + ? VL_ULL(0) : + ((QData)((IData)( + vlTOPp->VX_cache__DOT__per_bank_core_rsp_tag[ + ((IData)(2U) + + + (7U + & (((IData)(0x2aU) + * (IData)(vlTOPp->VX_cache__DOT__cache_core_rsp_merge__DOT__main_bank_index)) + >> 5U)))])) + << ((IData)(0x40U) + - (0x1fU & + ((IData)(0x2aU) + * (IData)(vlTOPp->VX_cache__DOT__cache_core_rsp_merge__DOT__main_bank_index)))))) + | (((QData)((IData)( + vlTOPp->VX_cache__DOT__per_bank_core_rsp_tag[ + ((IData)(1U) + + + (7U + & (((IData)(0x2aU) + * (IData)(vlTOPp->VX_cache__DOT__cache_core_rsp_merge__DOT__main_bank_index)) + >> 5U)))])) + << ((0U == (0x1fU + & ((IData)(0x2aU) + * (IData)(vlTOPp->VX_cache__DOT__cache_core_rsp_merge__DOT__main_bank_index)))) + ? 0x20U + : ((IData)(0x20U) + - (0x1fU + & ((IData)(0x2aU) + * (IData)(vlTOPp->VX_cache__DOT__cache_core_rsp_merge__DOT__main_bank_index)))))) + | ((QData)((IData)( + vlTOPp->VX_cache__DOT__per_bank_core_rsp_tag[ + (7U + & (((IData)(0x2aU) + * (IData)(vlTOPp->VX_cache__DOT__cache_core_rsp_merge__DOT__main_bank_index)) + >> 5U))])) + >> (0x1fU + & ((IData)(0x2aU) + * (IData)(vlTOPp->VX_cache__DOT__cache_core_rsp_merge__DOT__main_bank_index))))))) + : VL_ULL(0)); + vlTOPp->core_rsp_valid = 0U; + if (((IData)(vlTOPp->VX_cache__DOT__per_bank_core_rsp_valid) + & ((0xffU & vlTOPp->VX_cache__DOT__per_bank_core_rsp_tag[0U]) + == ((0xa7U >= (0xffU & ((IData)(0x2aU) + * (IData)(vlTOPp->VX_cache__DOT__cache_core_rsp_merge__DOT__main_bank_index)))) + ? (0xffU & (((0U == (0x1fU & ((IData)(0x2aU) + * (IData)(vlTOPp->VX_cache__DOT__cache_core_rsp_merge__DOT__main_bank_index)))) + ? 0U : (vlTOPp->VX_cache__DOT__per_bank_core_rsp_tag[ + ((IData)(1U) + + (7U & (((IData)(0x2aU) + * (IData)(vlTOPp->VX_cache__DOT__cache_core_rsp_merge__DOT__main_bank_index)) + >> 5U)))] + << ((IData)(0x20U) + - (0x1fU + & ((IData)(0x2aU) + * (IData)(vlTOPp->VX_cache__DOT__cache_core_rsp_merge__DOT__main_bank_index)))))) + | (vlTOPp->VX_cache__DOT__per_bank_core_rsp_tag[ + (7U & (((IData)(0x2aU) + * (IData)(vlTOPp->VX_cache__DOT__cache_core_rsp_merge__DOT__main_bank_index)) + >> 5U))] >> + (0x1fU & ((IData)(0x2aU) + * (IData)(vlTOPp->VX_cache__DOT__cache_core_rsp_merge__DOT__main_bank_index)))))) + : 0U)))) { + vlTOPp->core_rsp_valid = ((IData)(vlTOPp->core_rsp_valid) + | ((IData)(1U) << + (3U & (IData)(vlTOPp->VX_cache__DOT__per_bank_core_rsp_tid)))); + } + if ((((IData)(vlTOPp->VX_cache__DOT__per_bank_core_rsp_valid) + >> 1U) & ((0xffU & ((vlTOPp->VX_cache__DOT__per_bank_core_rsp_tag[2U] + << 0x16U) | (vlTOPp->VX_cache__DOT__per_bank_core_rsp_tag[1U] + >> 0xaU))) + == ((0xa7U >= (0xffU & ((IData)(0x2aU) + * (IData)(vlTOPp->VX_cache__DOT__cache_core_rsp_merge__DOT__main_bank_index)))) + ? (0xffU & (((0U == (0x1fU + & ((IData)(0x2aU) + * (IData)(vlTOPp->VX_cache__DOT__cache_core_rsp_merge__DOT__main_bank_index)))) + ? 0U : (vlTOPp->VX_cache__DOT__per_bank_core_rsp_tag[ + ((IData)(1U) + + (7U + & (((IData)(0x2aU) + * (IData)(vlTOPp->VX_cache__DOT__cache_core_rsp_merge__DOT__main_bank_index)) + >> 5U)))] + << ((IData)(0x20U) + - + (0x1fU + & ((IData)(0x2aU) + * (IData)(vlTOPp->VX_cache__DOT__cache_core_rsp_merge__DOT__main_bank_index)))))) + | (vlTOPp->VX_cache__DOT__per_bank_core_rsp_tag[ + (7U & (((IData)(0x2aU) + * (IData)(vlTOPp->VX_cache__DOT__cache_core_rsp_merge__DOT__main_bank_index)) + >> 5U))] + >> (0x1fU & + ((IData)(0x2aU) + * (IData)(vlTOPp->VX_cache__DOT__cache_core_rsp_merge__DOT__main_bank_index)))))) + : 0U)))) { + vlTOPp->core_rsp_valid = ((IData)(vlTOPp->core_rsp_valid) + | ((IData)(1U) << + (3U & ((IData)(vlTOPp->VX_cache__DOT__per_bank_core_rsp_tid) + >> 2U)))); + } + if ((((IData)(vlTOPp->VX_cache__DOT__per_bank_core_rsp_valid) + >> 2U) & ((0xffU & ((vlTOPp->VX_cache__DOT__per_bank_core_rsp_tag[3U] + << 0xcU) | (vlTOPp->VX_cache__DOT__per_bank_core_rsp_tag[2U] + >> 0x14U))) + == ((0xa7U >= (0xffU & ((IData)(0x2aU) + * (IData)(vlTOPp->VX_cache__DOT__cache_core_rsp_merge__DOT__main_bank_index)))) + ? (0xffU & (((0U == (0x1fU + & ((IData)(0x2aU) + * (IData)(vlTOPp->VX_cache__DOT__cache_core_rsp_merge__DOT__main_bank_index)))) + ? 0U : (vlTOPp->VX_cache__DOT__per_bank_core_rsp_tag[ + ((IData)(1U) + + (7U + & (((IData)(0x2aU) + * (IData)(vlTOPp->VX_cache__DOT__cache_core_rsp_merge__DOT__main_bank_index)) + >> 5U)))] + << ((IData)(0x20U) + - + (0x1fU + & ((IData)(0x2aU) + * (IData)(vlTOPp->VX_cache__DOT__cache_core_rsp_merge__DOT__main_bank_index)))))) + | (vlTOPp->VX_cache__DOT__per_bank_core_rsp_tag[ + (7U & (((IData)(0x2aU) + * (IData)(vlTOPp->VX_cache__DOT__cache_core_rsp_merge__DOT__main_bank_index)) + >> 5U))] + >> (0x1fU & + ((IData)(0x2aU) + * (IData)(vlTOPp->VX_cache__DOT__cache_core_rsp_merge__DOT__main_bank_index)))))) + : 0U)))) { + vlTOPp->core_rsp_valid = ((IData)(vlTOPp->core_rsp_valid) + | ((IData)(1U) << + (3U & ((IData)(vlTOPp->VX_cache__DOT__per_bank_core_rsp_tid) + >> 4U)))); + } + if ((((IData)(vlTOPp->VX_cache__DOT__per_bank_core_rsp_valid) + >> 3U) & ((0xffU & ((vlTOPp->VX_cache__DOT__per_bank_core_rsp_tag[4U] + << 2U) | (vlTOPp->VX_cache__DOT__per_bank_core_rsp_tag[3U] + >> 0x1eU))) + == ((0xa7U >= (0xffU & ((IData)(0x2aU) + * (IData)(vlTOPp->VX_cache__DOT__cache_core_rsp_merge__DOT__main_bank_index)))) + ? (0xffU & (((0U == (0x1fU + & ((IData)(0x2aU) + * (IData)(vlTOPp->VX_cache__DOT__cache_core_rsp_merge__DOT__main_bank_index)))) + ? 0U : (vlTOPp->VX_cache__DOT__per_bank_core_rsp_tag[ + ((IData)(1U) + + (7U + & (((IData)(0x2aU) + * (IData)(vlTOPp->VX_cache__DOT__cache_core_rsp_merge__DOT__main_bank_index)) + >> 5U)))] + << ((IData)(0x20U) + - + (0x1fU + & ((IData)(0x2aU) + * (IData)(vlTOPp->VX_cache__DOT__cache_core_rsp_merge__DOT__main_bank_index)))))) + | (vlTOPp->VX_cache__DOT__per_bank_core_rsp_tag[ + (7U & (((IData)(0x2aU) + * (IData)(vlTOPp->VX_cache__DOT__cache_core_rsp_merge__DOT__main_bank_index)) + >> 5U))] + >> (0x1fU & + ((IData)(0x2aU) + * (IData)(vlTOPp->VX_cache__DOT__cache_core_rsp_merge__DOT__main_bank_index)))))) + : 0U)))) { + vlTOPp->core_rsp_valid = ((IData)(vlTOPp->core_rsp_valid) + | ((IData)(1U) << + (3U & ((IData)(vlTOPp->VX_cache__DOT__per_bank_core_rsp_tid) + >> 6U)))); + } + vlTOPp->VX_cache__DOT____Vcellout__cache_core_rsp_merge__core_rsp_data[0U] = 0U; + vlTOPp->VX_cache__DOT____Vcellout__cache_core_rsp_merge__core_rsp_data[1U] = 0U; + vlTOPp->VX_cache__DOT____Vcellout__cache_core_rsp_merge__core_rsp_data[2U] = 0U; + vlTOPp->VX_cache__DOT____Vcellout__cache_core_rsp_merge__core_rsp_data[3U] = 0U; + if (((IData)(vlTOPp->VX_cache__DOT__per_bank_core_rsp_valid) + & ((0xffU & vlTOPp->VX_cache__DOT__per_bank_core_rsp_tag[0U]) + == ((0xa7U >= (0xffU & ((IData)(0x2aU) + * (IData)(vlTOPp->VX_cache__DOT__cache_core_rsp_merge__DOT__main_bank_index)))) + ? (0xffU & (((0U == (0x1fU & ((IData)(0x2aU) + * (IData)(vlTOPp->VX_cache__DOT__cache_core_rsp_merge__DOT__main_bank_index)))) + ? 0U : (vlTOPp->VX_cache__DOT__per_bank_core_rsp_tag[ + ((IData)(1U) + + (7U & (((IData)(0x2aU) + * (IData)(vlTOPp->VX_cache__DOT__cache_core_rsp_merge__DOT__main_bank_index)) + >> 5U)))] + << ((IData)(0x20U) + - (0x1fU + & ((IData)(0x2aU) + * (IData)(vlTOPp->VX_cache__DOT__cache_core_rsp_merge__DOT__main_bank_index)))))) + | (vlTOPp->VX_cache__DOT__per_bank_core_rsp_tag[ + (7U & (((IData)(0x2aU) + * (IData)(vlTOPp->VX_cache__DOT__cache_core_rsp_merge__DOT__main_bank_index)) + >> 5U))] >> + (0x1fU & ((IData)(0x2aU) + * (IData)(vlTOPp->VX_cache__DOT__cache_core_rsp_merge__DOT__main_bank_index)))))) + : 0U)))) { + VL_ASSIGNSEL_WIII(32,(0x60U & ((IData)(vlTOPp->VX_cache__DOT__per_bank_core_rsp_tid) + << 5U)), vlTOPp->VX_cache__DOT____Vcellout__cache_core_rsp_merge__core_rsp_data, + vlTOPp->VX_cache__DOT__per_bank_core_rsp_data[0U]); + } + if ((((IData)(vlTOPp->VX_cache__DOT__per_bank_core_rsp_valid) + >> 1U) & ((0xffU & ((vlTOPp->VX_cache__DOT__per_bank_core_rsp_tag[2U] + << 0x16U) | (vlTOPp->VX_cache__DOT__per_bank_core_rsp_tag[1U] + >> 0xaU))) + == ((0xa7U >= (0xffU & ((IData)(0x2aU) + * (IData)(vlTOPp->VX_cache__DOT__cache_core_rsp_merge__DOT__main_bank_index)))) + ? (0xffU & (((0U == (0x1fU + & ((IData)(0x2aU) + * (IData)(vlTOPp->VX_cache__DOT__cache_core_rsp_merge__DOT__main_bank_index)))) + ? 0U : (vlTOPp->VX_cache__DOT__per_bank_core_rsp_tag[ + ((IData)(1U) + + (7U + & (((IData)(0x2aU) + * (IData)(vlTOPp->VX_cache__DOT__cache_core_rsp_merge__DOT__main_bank_index)) + >> 5U)))] + << ((IData)(0x20U) + - + (0x1fU + & ((IData)(0x2aU) + * (IData)(vlTOPp->VX_cache__DOT__cache_core_rsp_merge__DOT__main_bank_index)))))) + | (vlTOPp->VX_cache__DOT__per_bank_core_rsp_tag[ + (7U & (((IData)(0x2aU) + * (IData)(vlTOPp->VX_cache__DOT__cache_core_rsp_merge__DOT__main_bank_index)) + >> 5U))] + >> (0x1fU & + ((IData)(0x2aU) + * (IData)(vlTOPp->VX_cache__DOT__cache_core_rsp_merge__DOT__main_bank_index)))))) + : 0U)))) { + VL_ASSIGNSEL_WIII(32,(0x60U & ((IData)(vlTOPp->VX_cache__DOT__per_bank_core_rsp_tid) + << 3U)), vlTOPp->VX_cache__DOT____Vcellout__cache_core_rsp_merge__core_rsp_data, + vlTOPp->VX_cache__DOT__per_bank_core_rsp_data[1U]); + } + if ((((IData)(vlTOPp->VX_cache__DOT__per_bank_core_rsp_valid) + >> 2U) & ((0xffU & ((vlTOPp->VX_cache__DOT__per_bank_core_rsp_tag[3U] + << 0xcU) | (vlTOPp->VX_cache__DOT__per_bank_core_rsp_tag[2U] + >> 0x14U))) + == ((0xa7U >= (0xffU & ((IData)(0x2aU) + * (IData)(vlTOPp->VX_cache__DOT__cache_core_rsp_merge__DOT__main_bank_index)))) + ? (0xffU & (((0U == (0x1fU + & ((IData)(0x2aU) + * (IData)(vlTOPp->VX_cache__DOT__cache_core_rsp_merge__DOT__main_bank_index)))) + ? 0U : (vlTOPp->VX_cache__DOT__per_bank_core_rsp_tag[ + ((IData)(1U) + + (7U + & (((IData)(0x2aU) + * (IData)(vlTOPp->VX_cache__DOT__cache_core_rsp_merge__DOT__main_bank_index)) + >> 5U)))] + << ((IData)(0x20U) + - + (0x1fU + & ((IData)(0x2aU) + * (IData)(vlTOPp->VX_cache__DOT__cache_core_rsp_merge__DOT__main_bank_index)))))) + | (vlTOPp->VX_cache__DOT__per_bank_core_rsp_tag[ + (7U & (((IData)(0x2aU) + * (IData)(vlTOPp->VX_cache__DOT__cache_core_rsp_merge__DOT__main_bank_index)) + >> 5U))] + >> (0x1fU & + ((IData)(0x2aU) + * (IData)(vlTOPp->VX_cache__DOT__cache_core_rsp_merge__DOT__main_bank_index)))))) + : 0U)))) { + VL_ASSIGNSEL_WIII(32,(0x60U & ((IData)(vlTOPp->VX_cache__DOT__per_bank_core_rsp_tid) + << 1U)), vlTOPp->VX_cache__DOT____Vcellout__cache_core_rsp_merge__core_rsp_data, + vlTOPp->VX_cache__DOT__per_bank_core_rsp_data[2U]); + } + if ((((IData)(vlTOPp->VX_cache__DOT__per_bank_core_rsp_valid) + >> 3U) & ((0xffU & ((vlTOPp->VX_cache__DOT__per_bank_core_rsp_tag[4U] + << 2U) | (vlTOPp->VX_cache__DOT__per_bank_core_rsp_tag[3U] + >> 0x1eU))) + == ((0xa7U >= (0xffU & ((IData)(0x2aU) + * (IData)(vlTOPp->VX_cache__DOT__cache_core_rsp_merge__DOT__main_bank_index)))) + ? (0xffU & (((0U == (0x1fU + & ((IData)(0x2aU) + * (IData)(vlTOPp->VX_cache__DOT__cache_core_rsp_merge__DOT__main_bank_index)))) + ? 0U : (vlTOPp->VX_cache__DOT__per_bank_core_rsp_tag[ + ((IData)(1U) + + (7U + & (((IData)(0x2aU) + * (IData)(vlTOPp->VX_cache__DOT__cache_core_rsp_merge__DOT__main_bank_index)) + >> 5U)))] + << ((IData)(0x20U) + - + (0x1fU + & ((IData)(0x2aU) + * (IData)(vlTOPp->VX_cache__DOT__cache_core_rsp_merge__DOT__main_bank_index)))))) + | (vlTOPp->VX_cache__DOT__per_bank_core_rsp_tag[ + (7U & (((IData)(0x2aU) + * (IData)(vlTOPp->VX_cache__DOT__cache_core_rsp_merge__DOT__main_bank_index)) + >> 5U))] + >> (0x1fU & + ((IData)(0x2aU) + * (IData)(vlTOPp->VX_cache__DOT__cache_core_rsp_merge__DOT__main_bank_index)))))) + : 0U)))) { + VL_ASSIGNSEL_WIII(32,(0x60U & ((IData)(vlTOPp->VX_cache__DOT__per_bank_core_rsp_tid) + >> 1U)), vlTOPp->VX_cache__DOT____Vcellout__cache_core_rsp_merge__core_rsp_data, + vlTOPp->VX_cache__DOT__per_bank_core_rsp_data[3U]); + } + vlTOPp->VX_cache__DOT__cache_core_rsp_merge__DOT__sel_bank__DOT__genblk2__DOT__grant_onehot_r = 0U; + vlTOPp->VX_cache__DOT__cache_core_rsp_merge__DOT__sel_bank__DOT__genblk2__DOT__grant_onehot_r + = ((IData)(vlTOPp->VX_cache__DOT__cache_core_rsp_merge__DOT__sel_bank__DOT__genblk2__DOT__grant_onehot_r) + | ((IData)(1U) << (IData)(vlTOPp->VX_cache__DOT__cache_core_rsp_merge__DOT__main_bank_index))); + vlTOPp->VX_cache__DOT__cache_core_rsp_merge__DOT__per_bank_core_rsp_pop_unqual + = ((0xeU & (IData)(vlTOPp->VX_cache__DOT__cache_core_rsp_merge__DOT__per_bank_core_rsp_pop_unqual)) + | ((IData)(vlTOPp->VX_cache__DOT__per_bank_core_rsp_valid) + & ((0xffU & vlTOPp->VX_cache__DOT__per_bank_core_rsp_tag[0U]) + == ((0xa7U >= (0xffU & ((IData)(0x2aU) + * (IData)(vlTOPp->VX_cache__DOT__cache_core_rsp_merge__DOT__main_bank_index)))) + ? (0xffU & (((0U == (0x1fU & + ((IData)(0x2aU) + * (IData)(vlTOPp->VX_cache__DOT__cache_core_rsp_merge__DOT__main_bank_index)))) + ? 0U : (vlTOPp->VX_cache__DOT__per_bank_core_rsp_tag[ + ((IData)(1U) + + (7U + & (((IData)(0x2aU) + * (IData)(vlTOPp->VX_cache__DOT__cache_core_rsp_merge__DOT__main_bank_index)) + >> 5U)))] + << ((IData)(0x20U) + - (0x1fU + & ((IData)(0x2aU) + * (IData)(vlTOPp->VX_cache__DOT__cache_core_rsp_merge__DOT__main_bank_index)))))) + | (vlTOPp->VX_cache__DOT__per_bank_core_rsp_tag[ + (7U & (((IData)(0x2aU) + * (IData)(vlTOPp->VX_cache__DOT__cache_core_rsp_merge__DOT__main_bank_index)) + >> 5U))] + >> (0x1fU & ((IData)(0x2aU) + * (IData)(vlTOPp->VX_cache__DOT__cache_core_rsp_merge__DOT__main_bank_index)))))) + : 0U)))); + vlTOPp->VX_cache__DOT__cache_core_rsp_merge__DOT__per_bank_core_rsp_pop_unqual + = ((0xdU & (IData)(vlTOPp->VX_cache__DOT__cache_core_rsp_merge__DOT__per_bank_core_rsp_pop_unqual)) + | (0xfffffffeU & ((IData)(vlTOPp->VX_cache__DOT__per_bank_core_rsp_valid) + & (((0xffU & ((vlTOPp->VX_cache__DOT__per_bank_core_rsp_tag[2U] + << 0x16U) + | (vlTOPp->VX_cache__DOT__per_bank_core_rsp_tag[1U] + >> 0xaU))) + == ((0xa7U >= (0xffU + & ((IData)(0x2aU) + * (IData)(vlTOPp->VX_cache__DOT__cache_core_rsp_merge__DOT__main_bank_index)))) + ? (0xffU & (( + (0U + == + (0x1fU + & ((IData)(0x2aU) + * (IData)(vlTOPp->VX_cache__DOT__cache_core_rsp_merge__DOT__main_bank_index)))) + ? 0U + : + (vlTOPp->VX_cache__DOT__per_bank_core_rsp_tag[ + ((IData)(1U) + + + (7U + & (((IData)(0x2aU) + * (IData)(vlTOPp->VX_cache__DOT__cache_core_rsp_merge__DOT__main_bank_index)) + >> 5U)))] + << + ((IData)(0x20U) + - + (0x1fU + & ((IData)(0x2aU) + * (IData)(vlTOPp->VX_cache__DOT__cache_core_rsp_merge__DOT__main_bank_index)))))) + | (vlTOPp->VX_cache__DOT__per_bank_core_rsp_tag[ + (7U + & (((IData)(0x2aU) + * (IData)(vlTOPp->VX_cache__DOT__cache_core_rsp_merge__DOT__main_bank_index)) + >> 5U))] + >> + (0x1fU + & ((IData)(0x2aU) + * (IData)(vlTOPp->VX_cache__DOT__cache_core_rsp_merge__DOT__main_bank_index)))))) + : 0U)) << 1U)))); + vlTOPp->VX_cache__DOT__cache_core_rsp_merge__DOT__per_bank_core_rsp_pop_unqual + = ((0xbU & (IData)(vlTOPp->VX_cache__DOT__cache_core_rsp_merge__DOT__per_bank_core_rsp_pop_unqual)) + | (0xfffffffcU & ((IData)(vlTOPp->VX_cache__DOT__per_bank_core_rsp_valid) + & (((0xffU & ((vlTOPp->VX_cache__DOT__per_bank_core_rsp_tag[3U] + << 0xcU) + | (vlTOPp->VX_cache__DOT__per_bank_core_rsp_tag[2U] + >> 0x14U))) + == ((0xa7U >= (0xffU + & ((IData)(0x2aU) + * (IData)(vlTOPp->VX_cache__DOT__cache_core_rsp_merge__DOT__main_bank_index)))) + ? (0xffU & (( + (0U + == + (0x1fU + & ((IData)(0x2aU) + * (IData)(vlTOPp->VX_cache__DOT__cache_core_rsp_merge__DOT__main_bank_index)))) + ? 0U + : + (vlTOPp->VX_cache__DOT__per_bank_core_rsp_tag[ + ((IData)(1U) + + + (7U + & (((IData)(0x2aU) + * (IData)(vlTOPp->VX_cache__DOT__cache_core_rsp_merge__DOT__main_bank_index)) + >> 5U)))] + << + ((IData)(0x20U) + - + (0x1fU + & ((IData)(0x2aU) + * (IData)(vlTOPp->VX_cache__DOT__cache_core_rsp_merge__DOT__main_bank_index)))))) + | (vlTOPp->VX_cache__DOT__per_bank_core_rsp_tag[ + (7U + & (((IData)(0x2aU) + * (IData)(vlTOPp->VX_cache__DOT__cache_core_rsp_merge__DOT__main_bank_index)) + >> 5U))] + >> + (0x1fU + & ((IData)(0x2aU) + * (IData)(vlTOPp->VX_cache__DOT__cache_core_rsp_merge__DOT__main_bank_index)))))) + : 0U)) << 2U)))); + vlTOPp->VX_cache__DOT__cache_core_rsp_merge__DOT__per_bank_core_rsp_pop_unqual + = ((7U & (IData)(vlTOPp->VX_cache__DOT__cache_core_rsp_merge__DOT__per_bank_core_rsp_pop_unqual)) + | (0xfffffff8U & ((IData)(vlTOPp->VX_cache__DOT__per_bank_core_rsp_valid) + & (((0xffU & ((vlTOPp->VX_cache__DOT__per_bank_core_rsp_tag[4U] + << 2U) + | (vlTOPp->VX_cache__DOT__per_bank_core_rsp_tag[3U] + >> 0x1eU))) + == ((0xa7U >= (0xffU + & ((IData)(0x2aU) + * (IData)(vlTOPp->VX_cache__DOT__cache_core_rsp_merge__DOT__main_bank_index)))) + ? (0xffU & (( + (0U + == + (0x1fU + & ((IData)(0x2aU) + * (IData)(vlTOPp->VX_cache__DOT__cache_core_rsp_merge__DOT__main_bank_index)))) + ? 0U + : + (vlTOPp->VX_cache__DOT__per_bank_core_rsp_tag[ + ((IData)(1U) + + + (7U + & (((IData)(0x2aU) + * (IData)(vlTOPp->VX_cache__DOT__cache_core_rsp_merge__DOT__main_bank_index)) + >> 5U)))] + << + ((IData)(0x20U) + - + (0x1fU + & ((IData)(0x2aU) + * (IData)(vlTOPp->VX_cache__DOT__cache_core_rsp_merge__DOT__main_bank_index)))))) + | (vlTOPp->VX_cache__DOT__per_bank_core_rsp_tag[ + (7U + & (((IData)(0x2aU) + * (IData)(vlTOPp->VX_cache__DOT__cache_core_rsp_merge__DOT__main_bank_index)) + >> 5U))] + >> + (0x1fU + & ((IData)(0x2aU) + * (IData)(vlTOPp->VX_cache__DOT__cache_core_rsp_merge__DOT__main_bank_index)))))) + : 0U)) << 3U)))); + vlTOPp->VX_cache__DOT__cache_dram_req_arb__DOT__dram_fill_arb__DOT__sel_bank__DOT__genblk2__DOT__grant_onehot_r = 0U; + vlTOPp->VX_cache__DOT__cache_dram_req_arb__DOT__dram_fill_arb__DOT__sel_bank__DOT__genblk2__DOT__grant_onehot_r + = ((IData)(vlTOPp->VX_cache__DOT__cache_dram_req_arb__DOT__dram_fill_arb__DOT__sel_bank__DOT__genblk2__DOT__grant_onehot_r) + | ((IData)(1U) << (IData)(vlTOPp->VX_cache__DOT__cache_dram_req_arb__DOT__dram_fill_arb__DOT__qual_request_index))); + vlTOPp->VX_cache__DOT__cache_dram_req_arb__DOT__dfqq_req + = (1U & ((IData)(vlTOPp->VX_cache__DOT__cache_dram_req_arb__DOT__dram_fill_arb__DOT__use_per_bqual_bank_dram_fill_req_valid) + >> (IData)(vlTOPp->VX_cache__DOT__cache_dram_req_arb__DOT__dram_fill_arb__DOT__qual_request_index))); + vlTOPp->__Vtableidx4 = vlTOPp->VX_cache__DOT__per_bank_snp_rsp_valid; + vlTOPp->VX_cache__DOT__snp_rsp_arb__DOT__fsq_bank + = vlTOPp->__Vtable4_VX_cache__DOT__snp_rsp_arb__DOT__fsq_bank + [vlTOPp->__Vtableidx4]; + vlTOPp->VX_cache__DOT__snp_rsp_arb__DOT__fsq_valid + = vlTOPp->__Vtable4_VX_cache__DOT__snp_rsp_arb__DOT__fsq_valid + [vlTOPp->__Vtableidx4]; + vlTOPp->VX_cache__DOT__snp_rsp_arb__DOT__sel_ffsq__DOT__genblk2__DOT__priority_encoder__DOT__i + = vlTOPp->__Vtable4_VX_cache__DOT__snp_rsp_arb__DOT__sel_ffsq__DOT__genblk2__DOT__priority_encoder__DOT__i + [vlTOPp->__Vtableidx4]; + vlTOPp->__Vtableidx2 = vlTOPp->VX_cache__DOT__per_bank_dram_wb_req_valid; + vlTOPp->VX_cache__DOT__cache_dram_req_arb__DOT__dwb_bank + = vlTOPp->__Vtable2_VX_cache__DOT__cache_dram_req_arb__DOT__dwb_bank + [vlTOPp->__Vtableidx2]; + vlTOPp->VX_cache__DOT__cache_dram_req_arb__DOT__dwb_valid + = vlTOPp->__Vtable2_VX_cache__DOT__cache_dram_req_arb__DOT__dwb_valid + [vlTOPp->__Vtableidx2]; + vlTOPp->VX_cache__DOT__cache_dram_req_arb__DOT__sel_dwb__DOT__genblk2__DOT__priority_encoder__DOT__i + = vlTOPp->__Vtable2_VX_cache__DOT__cache_dram_req_arb__DOT__sel_dwb__DOT__genblk2__DOT__priority_encoder__DOT__i + [vlTOPp->__Vtableidx2]; + vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cwbq_push_stall + = ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cwbq_push_unqual) + & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cwb_queue__DOT__genblk3__DOT__genblk2__DOT__full_r)); + vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT____Vcellinp__dwb_queue__data_in[0U] + = ((0xf0000000U & (vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__st_1e_2__DOT__value[2U] + << 5U)) | (0xfffffffU & + ((vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__st_1e_2__DOT__value[1U] + << 0x19U) | + (vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__st_1e_2__DOT__value[0U] + >> 7U)))); + vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT____Vcellinp__dwb_queue__data_in[1U] + = ((0xfffffffU & ((0xfffffe0U & (vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__st_1e_2__DOT__value[3U] + << 5U)) | + (vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__st_1e_2__DOT__value[2U] + >> 0x1bU))) | (0xf0000000U + & (vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__st_1e_2__DOT__value[3U] + << 5U))); + vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT____Vcellinp__dwb_queue__data_in[2U] + = ((0xfffffffU & ((0xfffffe0U & (vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__st_1e_2__DOT__value[4U] + << 5U)) | + (vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__st_1e_2__DOT__value[3U] + >> 0x1bU))) | (0xf0000000U + & (vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__st_1e_2__DOT__value[4U] + << 5U))); + vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT____Vcellinp__dwb_queue__data_in[3U] + = ((0xfffffffU & ((0xfffffe0U & (vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__st_1e_2__DOT__value[5U] + << 5U)) | + (vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__st_1e_2__DOT__value[4U] + >> 0x1bU))) | (0xf0000000U + & (vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__st_1e_2__DOT__value[5U] + << 5U))); + vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT____Vcellinp__dwb_queue__data_in[4U] + = ((0xf0000000U & (vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__st_1e_2__DOT__value[8U] + << 3U)) | (0xfffffffU & + ((0xfffffe0U + & (vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__st_1e_2__DOT__value[6U] + << 5U)) + | (vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__st_1e_2__DOT__value[5U] + >> 0x1bU)))); + vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT____Vcellinp__dwb_queue__data_in[5U] + = ((0xffc00000U & (vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__st_1e_2__DOT__value[1U] + << 5U)) | (0xfffffffU & + ((0x3ffffcU & + (vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__st_1e_2__DOT__value[2U] + >> 1U)) | + (3U & ((0xffffff8U + & (vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__st_1e_2__DOT__value[9U] + << 3U)) + | (vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__st_1e_2__DOT__value[8U] + >> 0x1dU)))))); + vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT____Vcellinp__dwb_queue__data_in[6U] + = ((0xffffff80U & ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__dwbq_is_dwb_in) + << 7U)) | ((0xffffffc0U + & ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__dwbq_is_snp_in) + << 6U)) | + (0x3fU & ((0x3fffe0U + & (vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__st_1e_2__DOT__value[2U] + << 5U)) + | (vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__st_1e_2__DOT__value[1U] + >> 0x1bU))))); + vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__dwbq_push_unqual + = ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__dwbq_is_dwb_in) + | (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__dwbq_is_snp_in)); + vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__miss_add_unqual + = (1U & ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__miss_add_because_miss) + | (vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__st_1e_2__DOT__value[9U] + >> 0x18U))); + vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__cwbq_push_stall + = ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__cwbq_push_unqual) + & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__cwb_queue__DOT__genblk3__DOT__genblk2__DOT__full_r)); + vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT____Vcellinp__dwb_queue__data_in[0U] + = ((0xf0000000U & (vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__st_1e_2__DOT__value[2U] + << 5U)) | (0xfffffffU & + ((vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__st_1e_2__DOT__value[1U] + << 0x19U) | + (vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__st_1e_2__DOT__value[0U] + >> 7U)))); + vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT____Vcellinp__dwb_queue__data_in[1U] + = ((0xfffffffU & ((0xfffffe0U & (vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__st_1e_2__DOT__value[3U] + << 5U)) | + (vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__st_1e_2__DOT__value[2U] + >> 0x1bU))) | (0xf0000000U + & (vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__st_1e_2__DOT__value[3U] + << 5U))); + vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT____Vcellinp__dwb_queue__data_in[2U] + = ((0xfffffffU & ((0xfffffe0U & (vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__st_1e_2__DOT__value[4U] + << 5U)) | + (vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__st_1e_2__DOT__value[3U] + >> 0x1bU))) | (0xf0000000U + & (vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__st_1e_2__DOT__value[4U] + << 5U))); + vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT____Vcellinp__dwb_queue__data_in[3U] + = ((0xfffffffU & ((0xfffffe0U & (vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__st_1e_2__DOT__value[5U] + << 5U)) | + (vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__st_1e_2__DOT__value[4U] + >> 0x1bU))) | (0xf0000000U + & (vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__st_1e_2__DOT__value[5U] + << 5U))); + vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT____Vcellinp__dwb_queue__data_in[4U] + = ((0xf0000000U & (vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__st_1e_2__DOT__value[8U] + << 3U)) | (0xfffffffU & + ((0xfffffe0U + & (vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__st_1e_2__DOT__value[6U] + << 5U)) + | (vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__st_1e_2__DOT__value[5U] + >> 0x1bU)))); + vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT____Vcellinp__dwb_queue__data_in[5U] + = ((0xffc00000U & (vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__st_1e_2__DOT__value[1U] + << 5U)) | (0xfffffffU & + ((0x3ffffcU & + (vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__st_1e_2__DOT__value[2U] + >> 1U)) | + (3U & ((0xffffff8U + & (vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__st_1e_2__DOT__value[9U] + << 3U)) + | (vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__st_1e_2__DOT__value[8U] + >> 0x1dU)))))); + vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT____Vcellinp__dwb_queue__data_in[6U] + = ((0xffffff80U & ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__dwbq_is_dwb_in) + << 7U)) | ((0xffffffc0U + & ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__dwbq_is_snp_in) + << 6U)) | + (0x3fU & ((0x3fffe0U + & (vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__st_1e_2__DOT__value[2U] + << 5U)) + | (vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__st_1e_2__DOT__value[1U] + >> 0x1bU))))); + vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__dwbq_push_unqual + = ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__dwbq_is_dwb_in) + | (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__dwbq_is_snp_in)); + vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__miss_add_unqual + = (1U & ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__miss_add_because_miss) + | (vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__st_1e_2__DOT__value[9U] + >> 0x18U))); + vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__cwbq_push_stall + = ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__cwbq_push_unqual) + & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__cwb_queue__DOT__genblk3__DOT__genblk2__DOT__full_r)); + vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT____Vcellinp__dwb_queue__data_in[0U] + = ((0xf0000000U & (vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__st_1e_2__DOT__value[2U] + << 5U)) | (0xfffffffU & + ((vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__st_1e_2__DOT__value[1U] + << 0x19U) | + (vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__st_1e_2__DOT__value[0U] + >> 7U)))); + vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT____Vcellinp__dwb_queue__data_in[1U] + = ((0xfffffffU & ((0xfffffe0U & (vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__st_1e_2__DOT__value[3U] + << 5U)) | + (vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__st_1e_2__DOT__value[2U] + >> 0x1bU))) | (0xf0000000U + & (vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__st_1e_2__DOT__value[3U] + << 5U))); + vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT____Vcellinp__dwb_queue__data_in[2U] + = ((0xfffffffU & ((0xfffffe0U & (vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__st_1e_2__DOT__value[4U] + << 5U)) | + (vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__st_1e_2__DOT__value[3U] + >> 0x1bU))) | (0xf0000000U + & (vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__st_1e_2__DOT__value[4U] + << 5U))); + vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT____Vcellinp__dwb_queue__data_in[3U] + = ((0xfffffffU & ((0xfffffe0U & (vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__st_1e_2__DOT__value[5U] + << 5U)) | + (vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__st_1e_2__DOT__value[4U] + >> 0x1bU))) | (0xf0000000U + & (vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__st_1e_2__DOT__value[5U] + << 5U))); + vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT____Vcellinp__dwb_queue__data_in[4U] + = ((0xf0000000U & (vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__st_1e_2__DOT__value[8U] + << 3U)) | (0xfffffffU & + ((0xfffffe0U + & (vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__st_1e_2__DOT__value[6U] + << 5U)) + | (vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__st_1e_2__DOT__value[5U] + >> 0x1bU)))); + vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT____Vcellinp__dwb_queue__data_in[5U] + = ((0xffc00000U & (vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__st_1e_2__DOT__value[1U] + << 5U)) | (0xfffffffU & + ((0x3ffffcU & + (vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__st_1e_2__DOT__value[2U] + >> 1U)) | + (3U & ((0xffffff8U + & (vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__st_1e_2__DOT__value[9U] + << 3U)) + | (vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__st_1e_2__DOT__value[8U] + >> 0x1dU)))))); + vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT____Vcellinp__dwb_queue__data_in[6U] + = ((0xffffff80U & ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__dwbq_is_dwb_in) + << 7U)) | ((0xffffffc0U + & ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__dwbq_is_snp_in) + << 6U)) | + (0x3fU & ((0x3fffe0U + & (vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__st_1e_2__DOT__value[2U] + << 5U)) + | (vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__st_1e_2__DOT__value[1U] + >> 0x1bU))))); + vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__dwbq_push_unqual + = ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__dwbq_is_dwb_in) + | (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__dwbq_is_snp_in)); + vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__miss_add_unqual + = (1U & ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__miss_add_because_miss) + | (vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__st_1e_2__DOT__value[9U] + >> 0x18U))); + vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cwbq_push_stall + = ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cwbq_push_unqual) + & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cwb_queue__DOT__genblk3__DOT__genblk2__DOT__full_r)); + vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT____Vcellinp__dwb_queue__data_in[0U] + = ((0xf0000000U & (vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__st_1e_2__DOT__value[2U] + << 5U)) | (0xfffffffU & + ((vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__st_1e_2__DOT__value[1U] + << 0x19U) | + (vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__st_1e_2__DOT__value[0U] + >> 7U)))); + vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT____Vcellinp__dwb_queue__data_in[1U] + = ((0xfffffffU & ((0xfffffe0U & (vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__st_1e_2__DOT__value[3U] + << 5U)) | + (vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__st_1e_2__DOT__value[2U] + >> 0x1bU))) | (0xf0000000U + & (vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__st_1e_2__DOT__value[3U] + << 5U))); + vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT____Vcellinp__dwb_queue__data_in[2U] + = ((0xfffffffU & ((0xfffffe0U & (vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__st_1e_2__DOT__value[4U] + << 5U)) | + (vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__st_1e_2__DOT__value[3U] + >> 0x1bU))) | (0xf0000000U + & (vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__st_1e_2__DOT__value[4U] + << 5U))); + vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT____Vcellinp__dwb_queue__data_in[3U] + = ((0xfffffffU & ((0xfffffe0U & (vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__st_1e_2__DOT__value[5U] + << 5U)) | + (vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__st_1e_2__DOT__value[4U] + >> 0x1bU))) | (0xf0000000U + & (vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__st_1e_2__DOT__value[5U] + << 5U))); + vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT____Vcellinp__dwb_queue__data_in[4U] + = ((0xf0000000U & (vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__st_1e_2__DOT__value[8U] + << 3U)) | (0xfffffffU & + ((0xfffffe0U + & (vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__st_1e_2__DOT__value[6U] + << 5U)) + | (vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__st_1e_2__DOT__value[5U] + >> 0x1bU)))); + vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT____Vcellinp__dwb_queue__data_in[5U] + = ((0xffc00000U & (vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__st_1e_2__DOT__value[1U] + << 5U)) | (0xfffffffU & + ((0x3ffffcU & + (vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__st_1e_2__DOT__value[2U] + >> 1U)) | + (3U & ((0xffffff8U + & (vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__st_1e_2__DOT__value[9U] + << 3U)) + | (vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__st_1e_2__DOT__value[8U] + >> 0x1dU)))))); + vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT____Vcellinp__dwb_queue__data_in[6U] + = ((0xffffff80U & ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__dwbq_is_dwb_in) + << 7U)) | ((0xffffffc0U + & ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__dwbq_is_snp_in) + << 6U)) | + (0x3fU & ((0x3fffe0U + & (vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__st_1e_2__DOT__value[2U] + << 5U)) + | (vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__st_1e_2__DOT__value[1U] + >> 0x1bU))))); + vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__dwbq_push_unqual + = ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__dwbq_is_dwb_in) + | (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__dwbq_is_snp_in)); + vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__miss_add_unqual + = (1U & ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__miss_add_because_miss) + | (vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__st_1e_2__DOT__value[9U] + >> 0x18U))); + vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__snrq_pop_unqual + = (((((((0xbU >= (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cache_miss_resrv__DOT__size)) + & (~ (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__reqq_pop_unqual))) + & (~ (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__reqq_pop_unqual))) + & (~ (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cache_miss_resrv__DOT__dequeue_possible))) + & (~ (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__dfpq_pop_unqual))) + & (~ (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__snp_req_queue__DOT__genblk3__DOT__genblk2__DOT__empty_r))) + & (~ (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__core_req_arb__DOT__qual_has_request))); + vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__dirty_st1e + = ((vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__valid_st1 + [0U] & vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__tag_data_access__DOT__read_valid_st1c + [0U]) & vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__tag_data_access__DOT__read_dirty_st1c + [0U]); + vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__tag_data_access__DOT__tags_match + = ((0xfffffU & (vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__addr_st1 + [0U] >> 6U)) == vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__tag_data_access__DOT__read_tag_st1c + [0U]); + vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__snrq_pop_unqual + = (((((((0xbU >= (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__cache_miss_resrv__DOT__size)) + & (~ (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__reqq_pop_unqual))) + & (~ (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__reqq_pop_unqual))) + & (~ (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__cache_miss_resrv__DOT__dequeue_possible))) + & (~ (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__dfpq_pop_unqual))) + & (~ (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__snp_req_queue__DOT__genblk3__DOT__genblk2__DOT__empty_r))) + & (~ (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__core_req_arb__DOT__qual_has_request))); + vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__dirty_st1e + = ((vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__valid_st1 + [0U] & vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__tag_data_access__DOT__read_valid_st1c + [0U]) & vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__tag_data_access__DOT__read_dirty_st1c + [0U]); + vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__tag_data_access__DOT__tags_match + = ((0xfffffU & (vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__addr_st1 + [0U] >> 6U)) == vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__tag_data_access__DOT__read_tag_st1c + [0U]); + vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__snrq_pop_unqual + = (((((((0xbU >= (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__cache_miss_resrv__DOT__size)) + & (~ (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__reqq_pop_unqual))) + & (~ (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__reqq_pop_unqual))) + & (~ (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__cache_miss_resrv__DOT__dequeue_possible))) + & (~ (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__dfpq_pop_unqual))) + & (~ (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__snp_req_queue__DOT__genblk3__DOT__genblk2__DOT__empty_r))) + & (~ (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__core_req_arb__DOT__qual_has_request))); + vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__dirty_st1e + = ((vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__valid_st1 + [0U] & vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__tag_data_access__DOT__read_valid_st1c + [0U]) & vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__tag_data_access__DOT__read_dirty_st1c + [0U]); + vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__tag_data_access__DOT__tags_match + = ((0xfffffU & (vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__addr_st1 + [0U] >> 6U)) == vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__tag_data_access__DOT__read_tag_st1c + [0U]); + vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__snrq_pop_unqual + = (((((((0xbU >= (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cache_miss_resrv__DOT__size)) + & (~ (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__reqq_pop_unqual))) + & (~ (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__reqq_pop_unqual))) + & (~ (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cache_miss_resrv__DOT__dequeue_possible))) + & (~ (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__dfpq_pop_unqual))) + & (~ (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__snp_req_queue__DOT__genblk3__DOT__genblk2__DOT__empty_r))) + & (~ (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__core_req_arb__DOT__qual_has_request))); + vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__dirty_st1e + = ((vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__valid_st1 + [0U] & vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__tag_data_access__DOT__read_valid_st1c + [0U]) & vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__tag_data_access__DOT__read_dirty_st1c + [0U]); + vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__tag_data_access__DOT__tags_match + = ((0xfffffU & (vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__addr_st1 + [0U] >> 6U)) == vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__tag_data_access__DOT__read_tag_st1c + [0U]); + vlTOPp->core_rsp_data[0U] = vlTOPp->VX_cache__DOT____Vcellout__cache_core_rsp_merge__core_rsp_data[0U]; + vlTOPp->core_rsp_data[1U] = vlTOPp->VX_cache__DOT____Vcellout__cache_core_rsp_merge__core_rsp_data[1U]; + vlTOPp->core_rsp_data[2U] = vlTOPp->VX_cache__DOT____Vcellout__cache_core_rsp_merge__core_rsp_data[2U]; + vlTOPp->core_rsp_data[3U] = vlTOPp->VX_cache__DOT____Vcellout__cache_core_rsp_merge__core_rsp_data[3U]; + vlTOPp->VX_cache__DOT__cache_core_rsp_merge__DOT__sel_bank__DOT__genblk2__DOT__update_value + = (((IData)(vlTOPp->VX_cache__DOT__cache_core_rsp_merge__DOT__sel_bank__DOT__genblk2__DOT__requests_use) + & (~ (IData)(vlTOPp->VX_cache__DOT__cache_core_rsp_merge__DOT__sel_bank__DOT__genblk2__DOT__grant_onehot_r))) + | (((IData)(vlTOPp->VX_cache__DOT__cache_core_rsp_merge__DOT__sel_bank__DOT__genblk2__DOT__refill_original) + ^ (IData)(vlTOPp->VX_cache__DOT__per_bank_core_rsp_valid)) + & (~ (IData)(vlTOPp->VX_cache__DOT__cache_core_rsp_merge__DOT__sel_bank__DOT__genblk2__DOT__refill_original)))); + vlTOPp->snp_rsp_valid = vlTOPp->VX_cache__DOT__snp_rsp_arb__DOT__fsq_valid; + vlTOPp->VX_cache__DOT__snp_rsp_arb__DOT__sel_ffsq__DOT__genblk2__DOT__grant_onehot_r = 0U; + vlTOPp->VX_cache__DOT__snp_rsp_arb__DOT__sel_ffsq__DOT__genblk2__DOT__grant_onehot_r + = ((IData)(vlTOPp->VX_cache__DOT__snp_rsp_arb__DOT__sel_ffsq__DOT__genblk2__DOT__grant_onehot_r) + | ((IData)(1U) << (IData)(vlTOPp->VX_cache__DOT__snp_rsp_arb__DOT__fsq_bank))); + vlTOPp->snp_rsp_tag = ((0x6fU >= (0x7fU & ((IData)(0x1cU) + * (IData)(vlTOPp->VX_cache__DOT__snp_rsp_arb__DOT__fsq_bank)))) + ? (0xfffffffU & (((0U == + (0x1fU + & ((IData)(0x1cU) + * (IData)(vlTOPp->VX_cache__DOT__snp_rsp_arb__DOT__fsq_bank)))) + ? 0U + : (vlTOPp->VX_cache__DOT__per_bank_snp_rsp_tag[ + ((IData)(1U) + + + (3U + & (((IData)(0x1cU) + * (IData)(vlTOPp->VX_cache__DOT__snp_rsp_arb__DOT__fsq_bank)) + >> 5U)))] + << + ((IData)(0x20U) + - + (0x1fU + & ((IData)(0x1cU) + * (IData)(vlTOPp->VX_cache__DOT__snp_rsp_arb__DOT__fsq_bank)))))) + | (vlTOPp->VX_cache__DOT__per_bank_snp_rsp_tag[ + (3U + & (((IData)(0x1cU) + * (IData)(vlTOPp->VX_cache__DOT__snp_rsp_arb__DOT__fsq_bank)) + >> 5U))] + >> + (0x1fU + & ((IData)(0x1cU) + * (IData)(vlTOPp->VX_cache__DOT__snp_rsp_arb__DOT__fsq_bank)))))) + : 0U); + vlTOPp->dram_req_rw = vlTOPp->VX_cache__DOT__cache_dram_req_arb__DOT__dwb_valid; + vlTOPp->dram_req_valid = ((IData)(vlTOPp->VX_cache__DOT__cache_dram_req_arb__DOT__dwb_valid) + | (IData)(vlTOPp->VX_cache__DOT__cache_dram_req_arb__DOT__dfqq_req)); + vlTOPp->VX_cache__DOT__cache_dram_req_arb__DOT__sel_dwb__DOT__genblk2__DOT__grant_onehot_r = 0U; + vlTOPp->VX_cache__DOT__cache_dram_req_arb__DOT__sel_dwb__DOT__genblk2__DOT__grant_onehot_r + = ((IData)(vlTOPp->VX_cache__DOT__cache_dram_req_arb__DOT__sel_dwb__DOT__genblk2__DOT__grant_onehot_r) + | ((IData)(1U) << (IData)(vlTOPp->VX_cache__DOT__cache_dram_req_arb__DOT__dwb_bank))); + vlTOPp->dram_req_byteen = ((IData)(vlTOPp->VX_cache__DOT__cache_dram_req_arb__DOT__dwb_valid) + ? (0xffffU & (IData)( + (vlTOPp->VX_cache__DOT__per_bank_dram_wb_req_byteen + >> + (0x3fU + & ((IData)(vlTOPp->VX_cache__DOT__cache_dram_req_arb__DOT__dwb_bank) + << 4U))))) + : 0xffffU); + vlTOPp->dram_req_data[0U] = ((IData)(vlTOPp->VX_cache__DOT__cache_dram_req_arb__DOT__dwb_valid) + ? (((0U == (0x1fU + & ((IData)(vlTOPp->VX_cache__DOT__cache_dram_req_arb__DOT__dwb_bank) + << 7U))) + ? 0U : (vlTOPp->VX_cache__DOT__per_bank_dram_wb_req_data[ + ((IData)(1U) + + (0xcU + & ((IData)(vlTOPp->VX_cache__DOT__cache_dram_req_arb__DOT__dwb_bank) + << 2U)))] + << ((IData)(0x20U) + - + (0x1fU + & ((IData)(vlTOPp->VX_cache__DOT__cache_dram_req_arb__DOT__dwb_bank) + << 7U))))) + | (vlTOPp->VX_cache__DOT__per_bank_dram_wb_req_data[ + (0xcU & ((IData)(vlTOPp->VX_cache__DOT__cache_dram_req_arb__DOT__dwb_bank) + << 2U))] + >> (0x1fU & + ((IData)(vlTOPp->VX_cache__DOT__cache_dram_req_arb__DOT__dwb_bank) + << 7U)))) + : 0U); + vlTOPp->dram_req_data[1U] = ((IData)(vlTOPp->VX_cache__DOT__cache_dram_req_arb__DOT__dwb_valid) + ? (((0U == (0x1fU + & ((IData)(vlTOPp->VX_cache__DOT__cache_dram_req_arb__DOT__dwb_bank) + << 7U))) + ? 0U : (vlTOPp->VX_cache__DOT__per_bank_dram_wb_req_data[ + ((IData)(2U) + + (0xcU + & ((IData)(vlTOPp->VX_cache__DOT__cache_dram_req_arb__DOT__dwb_bank) + << 2U)))] + << ((IData)(0x20U) + - + (0x1fU + & ((IData)(vlTOPp->VX_cache__DOT__cache_dram_req_arb__DOT__dwb_bank) + << 7U))))) + | (vlTOPp->VX_cache__DOT__per_bank_dram_wb_req_data[ + ((IData)(1U) + + (0xcU & + ((IData)(vlTOPp->VX_cache__DOT__cache_dram_req_arb__DOT__dwb_bank) + << 2U)))] + >> (0x1fU & + ((IData)(vlTOPp->VX_cache__DOT__cache_dram_req_arb__DOT__dwb_bank) + << 7U)))) + : 0U); + vlTOPp->dram_req_data[2U] = ((IData)(vlTOPp->VX_cache__DOT__cache_dram_req_arb__DOT__dwb_valid) + ? (((0U == (0x1fU + & ((IData)(vlTOPp->VX_cache__DOT__cache_dram_req_arb__DOT__dwb_bank) + << 7U))) + ? 0U : (vlTOPp->VX_cache__DOT__per_bank_dram_wb_req_data[ + ((IData)(3U) + + (0xcU + & ((IData)(vlTOPp->VX_cache__DOT__cache_dram_req_arb__DOT__dwb_bank) + << 2U)))] + << ((IData)(0x20U) + - + (0x1fU + & ((IData)(vlTOPp->VX_cache__DOT__cache_dram_req_arb__DOT__dwb_bank) + << 7U))))) + | (vlTOPp->VX_cache__DOT__per_bank_dram_wb_req_data[ + ((IData)(2U) + + (0xcU & + ((IData)(vlTOPp->VX_cache__DOT__cache_dram_req_arb__DOT__dwb_bank) + << 2U)))] + >> (0x1fU & + ((IData)(vlTOPp->VX_cache__DOT__cache_dram_req_arb__DOT__dwb_bank) + << 7U)))) + : 0U); + vlTOPp->dram_req_data[3U] = ((IData)(vlTOPp->VX_cache__DOT__cache_dram_req_arb__DOT__dwb_valid) + ? (((0U == (0x1fU + & ((IData)(vlTOPp->VX_cache__DOT__cache_dram_req_arb__DOT__dwb_bank) + << 7U))) + ? 0U : (vlTOPp->VX_cache__DOT__per_bank_dram_wb_req_data[ + ((IData)(4U) + + (0xcU + & ((IData)(vlTOPp->VX_cache__DOT__cache_dram_req_arb__DOT__dwb_bank) + << 2U)))] + << ((IData)(0x20U) + - + (0x1fU + & ((IData)(vlTOPp->VX_cache__DOT__cache_dram_req_arb__DOT__dwb_bank) + << 7U))))) + | (vlTOPp->VX_cache__DOT__per_bank_dram_wb_req_data[ + ((IData)(3U) + + (0xcU & + ((IData)(vlTOPp->VX_cache__DOT__cache_dram_req_arb__DOT__dwb_bank) + << 2U)))] + >> (0x1fU & + ((IData)(vlTOPp->VX_cache__DOT__cache_dram_req_arb__DOT__dwb_bank) + << 7U)))) + : 0U); + vlTOPp->dram_req_addr = (0xfffffffU & ((IData)(vlTOPp->VX_cache__DOT__cache_dram_req_arb__DOT__dwb_valid) + ? ((0x6fU + >= + (0x7fU + & ((IData)(0x1cU) + * (IData)(vlTOPp->VX_cache__DOT__cache_dram_req_arb__DOT__dwb_bank)))) + ? ( + ((0U + == + (0x1fU + & ((IData)(0x1cU) + * (IData)(vlTOPp->VX_cache__DOT__cache_dram_req_arb__DOT__dwb_bank)))) + ? 0U + : + (vlTOPp->VX_cache__DOT__per_bank_dram_wb_req_addr[ + ((IData)(1U) + + + (3U + & (((IData)(0x1cU) + * (IData)(vlTOPp->VX_cache__DOT__cache_dram_req_arb__DOT__dwb_bank)) + >> 5U)))] + << + ((IData)(0x20U) + - + (0x1fU + & ((IData)(0x1cU) + * (IData)(vlTOPp->VX_cache__DOT__cache_dram_req_arb__DOT__dwb_bank)))))) + | (vlTOPp->VX_cache__DOT__per_bank_dram_wb_req_addr[ + (3U + & (((IData)(0x1cU) + * (IData)(vlTOPp->VX_cache__DOT__cache_dram_req_arb__DOT__dwb_bank)) + >> 5U))] + >> + (0x1fU + & ((IData)(0x1cU) + * (IData)(vlTOPp->VX_cache__DOT__cache_dram_req_arb__DOT__dwb_bank))))) + : 0U) + : ((IData)(vlTOPp->VX_cache__DOT__cache_dram_req_arb__DOT__dfqq_req) + ? ( + (0x6fU + >= + (0x7fU + & ((IData)(0x1cU) + * (IData)(vlTOPp->VX_cache__DOT__cache_dram_req_arb__DOT__dram_fill_arb__DOT__qual_request_index)))) + ? + (((0U + == + (0x1fU + & ((IData)(0x1cU) + * (IData)(vlTOPp->VX_cache__DOT__cache_dram_req_arb__DOT__dram_fill_arb__DOT__qual_request_index)))) + ? 0U + : + (vlTOPp->VX_cache__DOT__cache_dram_req_arb__DOT__dram_fill_arb__DOT__qual_bank_dram_fill_req_addr[ + ((IData)(1U) + + + (3U + & (((IData)(0x1cU) + * (IData)(vlTOPp->VX_cache__DOT__cache_dram_req_arb__DOT__dram_fill_arb__DOT__qual_request_index)) + >> 5U)))] + << + ((IData)(0x20U) + - + (0x1fU + & ((IData)(0x1cU) + * (IData)(vlTOPp->VX_cache__DOT__cache_dram_req_arb__DOT__dram_fill_arb__DOT__qual_request_index)))))) + | (vlTOPp->VX_cache__DOT__cache_dram_req_arb__DOT__dram_fill_arb__DOT__qual_bank_dram_fill_req_addr[ + (3U + & (((IData)(0x1cU) + * (IData)(vlTOPp->VX_cache__DOT__cache_dram_req_arb__DOT__dram_fill_arb__DOT__qual_request_index)) + >> 5U))] + >> + (0x1fU + & ((IData)(0x1cU) + * (IData)(vlTOPp->VX_cache__DOT__cache_dram_req_arb__DOT__dram_fill_arb__DOT__qual_request_index))))) + : 0U) + : vlTOPp->VX_cache__DOT__cache_dram_req_arb__DOT__prfqq__DOT__use_addr))); + vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__dwbq_push_stall + = ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__dwbq_push_unqual) + & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__genblk2__DOT__full_r)); + vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__mrvq_init_ready_state_st2 + = (1U & (((vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__st_1e_2__DOT__value[9U] + >> 0x19U) | (((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__miss_add_unqual) + & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__dfpq_pop_unqual)) + & ((0x3ffffffU & (( + vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__st_1e_2__DOT__value[9U] + << 7U) + | (vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__st_1e_2__DOT__value[8U] + >> 0x19U))) + == (0x3ffffffU & + vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT____Vcellout__dfp_queue__data_out[4U])))) + | (((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__miss_add_unqual) + & vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__is_fill_st1 + [0U]) & ((0x3ffffffU & ((vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__st_1e_2__DOT__value[9U] + << 7U) + | (vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__st_1e_2__DOT__value[8U] + >> 0x19U))) + == vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__addr_st1 + [0U])))); + vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__dram_fill_req_stall + = ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__miss_add_unqual) + & (IData)(vlTOPp->VX_cache__DOT__cache_dram_req_arb__DOT__dram_fill_arb__DOT__dfqq_queue__DOT__genblk3__DOT__genblk2__DOT__full_r)); + vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__mrvq_push_stall + = ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__miss_add_unqual) + & (0x10U == (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cache_miss_resrv__DOT__size))); + vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__recover_mrvq_state_st2 + = ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__miss_add_unqual) + & (vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__st_1e_2__DOT__value[9U] + >> 0x1aU)); + vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__dwbq_push_stall + = ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__dwbq_push_unqual) + & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__genblk2__DOT__full_r)); + vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__mrvq_init_ready_state_st2 + = (1U & (((vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__st_1e_2__DOT__value[9U] + >> 0x19U) | (((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__miss_add_unqual) + & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__dfpq_pop_unqual)) + & ((0x3ffffffU & (( + vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__st_1e_2__DOT__value[9U] + << 7U) + | (vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__st_1e_2__DOT__value[8U] + >> 0x19U))) + == (0x3ffffffU & + vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT____Vcellout__dfp_queue__data_out[4U])))) + | (((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__miss_add_unqual) + & vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__is_fill_st1 + [0U]) & ((0x3ffffffU & ((vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__st_1e_2__DOT__value[9U] + << 7U) + | (vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__st_1e_2__DOT__value[8U] + >> 0x19U))) + == vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__addr_st1 + [0U])))); + vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__dram_fill_req_stall + = ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__miss_add_unqual) + & (IData)(vlTOPp->VX_cache__DOT__cache_dram_req_arb__DOT__dram_fill_arb__DOT__dfqq_queue__DOT__genblk3__DOT__genblk2__DOT__full_r)); + vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__mrvq_push_stall + = ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__miss_add_unqual) + & (0x10U == (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__cache_miss_resrv__DOT__size))); + vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__recover_mrvq_state_st2 + = ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__miss_add_unqual) + & (vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__st_1e_2__DOT__value[9U] + >> 0x1aU)); + vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__dwbq_push_stall + = ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__dwbq_push_unqual) + & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__genblk2__DOT__full_r)); + vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__mrvq_init_ready_state_st2 + = (1U & (((vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__st_1e_2__DOT__value[9U] + >> 0x19U) | (((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__miss_add_unqual) + & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__dfpq_pop_unqual)) + & ((0x3ffffffU & (( + vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__st_1e_2__DOT__value[9U] + << 7U) + | (vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__st_1e_2__DOT__value[8U] + >> 0x19U))) + == (0x3ffffffU & + vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT____Vcellout__dfp_queue__data_out[4U])))) + | (((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__miss_add_unqual) + & vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__is_fill_st1 + [0U]) & ((0x3ffffffU & ((vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__st_1e_2__DOT__value[9U] + << 7U) + | (vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__st_1e_2__DOT__value[8U] + >> 0x19U))) + == vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__addr_st1 + [0U])))); + vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__dram_fill_req_stall + = ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__miss_add_unqual) + & (IData)(vlTOPp->VX_cache__DOT__cache_dram_req_arb__DOT__dram_fill_arb__DOT__dfqq_queue__DOT__genblk3__DOT__genblk2__DOT__full_r)); + vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__mrvq_push_stall + = ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__miss_add_unqual) + & (0x10U == (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__cache_miss_resrv__DOT__size))); + vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__recover_mrvq_state_st2 + = ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__miss_add_unqual) + & (vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__st_1e_2__DOT__value[9U] + >> 0x1aU)); + vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__dwbq_push_stall + = ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__dwbq_push_unqual) + & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__genblk2__DOT__full_r)); + vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__mrvq_init_ready_state_st2 + = (1U & (((vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__st_1e_2__DOT__value[9U] + >> 0x19U) | (((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__miss_add_unqual) + & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__dfpq_pop_unqual)) + & ((0x3ffffffU & (( + vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__st_1e_2__DOT__value[9U] + << 7U) + | (vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__st_1e_2__DOT__value[8U] + >> 0x19U))) + == (0x3ffffffU & + vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT____Vcellout__dfp_queue__data_out[4U])))) + | (((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__miss_add_unqual) + & vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__is_fill_st1 + [0U]) & ((0x3ffffffU & ((vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__st_1e_2__DOT__value[9U] + << 7U) + | (vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__st_1e_2__DOT__value[8U] + >> 0x19U))) + == vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__addr_st1 + [0U])))); + vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__dram_fill_req_stall + = ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__miss_add_unqual) + & (IData)(vlTOPp->VX_cache__DOT__cache_dram_req_arb__DOT__dram_fill_arb__DOT__dfqq_queue__DOT__genblk3__DOT__genblk2__DOT__full_r)); + vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__mrvq_push_stall + = ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__miss_add_unqual) + & (0x10U == (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cache_miss_resrv__DOT__size))); + vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__recover_mrvq_state_st2 + = ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__miss_add_unqual) + & (vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__st_1e_2__DOT__value[9U] + >> 0x1aU)); + vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__tag_data_access__DOT__real_writefill + = ((vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__valid_st1 + [0U] & vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__is_fill_st1 + [0U]) & ((~ vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__tag_data_access__DOT__read_valid_st1c + [0U]) | (vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__tag_data_access__DOT__read_valid_st1c + [0U] & (~ (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__tag_data_access__DOT__tags_match))))); + vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__tag_data_access__DOT__real_miss + = ((((vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__valid_st1 + [0U] & (~ vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__is_snp_st1 + [0U])) & (~ vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__tag_data_access__DOT__read_valid_st1c + [0U])) & (~ vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__is_fill_st1 + [0U])) | + ((((vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__valid_st1 + [0U] & (~ vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__is_snp_st1 + [0U])) & vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__tag_data_access__DOT__read_valid_st1c + [0U]) & (~ vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__is_fill_st1 + [0U])) & (~ (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__tag_data_access__DOT__tags_match)))); + vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__tag_data_access__DOT__real_writefill + = ((vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__valid_st1 + [0U] & vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__is_fill_st1 + [0U]) & ((~ vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__tag_data_access__DOT__read_valid_st1c + [0U]) | (vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__tag_data_access__DOT__read_valid_st1c + [0U] & (~ (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__tag_data_access__DOT__tags_match))))); + vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__tag_data_access__DOT__real_miss + = ((((vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__valid_st1 + [0U] & (~ vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__is_snp_st1 + [0U])) & (~ vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__tag_data_access__DOT__read_valid_st1c + [0U])) & (~ vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__is_fill_st1 + [0U])) | + ((((vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__valid_st1 + [0U] & (~ vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__is_snp_st1 + [0U])) & vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__tag_data_access__DOT__read_valid_st1c + [0U]) & (~ vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__is_fill_st1 + [0U])) & (~ (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__tag_data_access__DOT__tags_match)))); + vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__tag_data_access__DOT__real_writefill + = ((vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__valid_st1 + [0U] & vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__is_fill_st1 + [0U]) & ((~ vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__tag_data_access__DOT__read_valid_st1c + [0U]) | (vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__tag_data_access__DOT__read_valid_st1c + [0U] & (~ (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__tag_data_access__DOT__tags_match))))); + vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__tag_data_access__DOT__real_miss + = ((((vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__valid_st1 + [0U] & (~ vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__is_snp_st1 + [0U])) & (~ vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__tag_data_access__DOT__read_valid_st1c + [0U])) & (~ vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__is_fill_st1 + [0U])) | + ((((vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__valid_st1 + [0U] & (~ vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__is_snp_st1 + [0U])) & vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__tag_data_access__DOT__read_valid_st1c + [0U]) & (~ vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__is_fill_st1 + [0U])) & (~ (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__tag_data_access__DOT__tags_match)))); + vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__tag_data_access__DOT__real_writefill + = ((vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__valid_st1 + [0U] & vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__is_fill_st1 + [0U]) & ((~ vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__tag_data_access__DOT__read_valid_st1c + [0U]) | (vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__tag_data_access__DOT__read_valid_st1c + [0U] & (~ (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__tag_data_access__DOT__tags_match))))); + vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__tag_data_access__DOT__real_miss + = ((((vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__valid_st1 + [0U] & (~ vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__is_snp_st1 + [0U])) & (~ vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__tag_data_access__DOT__read_valid_st1c + [0U])) & (~ vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__is_fill_st1 + [0U])) | + ((((vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__valid_st1 + [0U] & (~ vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__is_snp_st1 + [0U])) & vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__tag_data_access__DOT__read_valid_st1c + [0U]) & (~ vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__is_fill_st1 + [0U])) & (~ (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__tag_data_access__DOT__tags_match)))); + vlTOPp->VX_cache__DOT__cache_dram_req_arb__DOT__prfqq__DOT__pfq_queue__DOT__writing + = ((((IData)(vlTOPp->dram_req_valid) & (~ (IData)(vlTOPp->dram_req_rw))) + & (~ (IData)(vlTOPp->VX_cache__DOT__cache_dram_req_arb__DOT__prfqq__DOT__pfq_queue__DOT__size_r))) + & (~ (IData)(vlTOPp->VX_cache__DOT__cache_dram_req_arb__DOT__prfqq__DOT__pfq_queue__DOT__size_r))); + vlTOPp->dram_req_tag = vlTOPp->dram_req_addr; + vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__miss_add + = (((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__miss_add_unqual) + & (0x10U != (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cache_miss_resrv__DOT__size))) + & (~ (((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cwbq_push_stall) + | (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__dwbq_push_stall)) + | (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__dram_fill_req_stall)))); + vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__dwb_queue__DOT__writing + = ((((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__dwbq_push_unqual) + & (~ (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__genblk2__DOT__full_r))) + & (~ (((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cwbq_push_stall) + | (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__mrvq_push_stall)) + | (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__dram_fill_req_stall)))) + & (~ (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__genblk2__DOT__full_r))); + vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cwb_queue__DOT__writing + = (((((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cwbq_push_unqual) + & (~ (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cwb_queue__DOT__genblk3__DOT__genblk2__DOT__full_r))) + & (~ (vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__st_1e_2__DOT__value[0U] + >> 6U))) & (~ (((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__dwbq_push_stall) + | (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__mrvq_push_stall)) + | (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__dram_fill_req_stall)))) + & (~ (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cwb_queue__DOT__genblk3__DOT__genblk2__DOT__full_r))); + vlTOPp->VX_cache__DOT__per_bank_dram_fill_req_valid + = ((7U & (IData)(vlTOPp->VX_cache__DOT__per_bank_dram_fill_req_valid)) + | ((((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__miss_add_unqual) + << 3U) & (((~ (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__mrvq_init_ready_state_st2)) + << 3U) | (0x1f8U & ((vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__st_1e_2__DOT__value[9U] + >> 0x17U) + & ((~ + (vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__st_1e_2__DOT__value[9U] + >> 0x1bU)) + << 3U))))) + & ((~ (((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__dwbq_push_stall) + | (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__mrvq_push_stall)) + | (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cwbq_push_stall))) + << 3U))); + vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__stall_bank_pipe + = ((((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cwbq_push_stall) + | (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__dwbq_push_stall)) + | (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__mrvq_push_stall)) + | (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__dram_fill_req_stall)); + vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__force_request_miss_st1e + = (((vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__valid_st1 + [0U] & (~ vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__is_mrvq_st1 + [0U])) & ((0U != (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cache_miss_resrv__DOT__valid_address_match)) + | ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__miss_add_because_miss) + & (((0x3ffffffU & + ((vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__st_1e_2__DOT__value[9U] + << 7U) | ( + vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__st_1e_2__DOT__value[8U] + >> 0x19U))) + == vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__addr_st1 + [0U]) & (~ (vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__st_1e_2__DOT__value[9U] + >> 0x14U)))))) + | ((vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__valid_st1 + [0U] & vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__is_mrvq_st1 + [0U]) & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__recover_mrvq_state_st2))); + vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__miss_add + = (((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__miss_add_unqual) + & (0x10U != (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__cache_miss_resrv__DOT__size))) + & (~ (((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__cwbq_push_stall) + | (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__dwbq_push_stall)) + | (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__dram_fill_req_stall)))); + vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__dwb_queue__DOT__writing + = ((((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__dwbq_push_unqual) + & (~ (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__genblk2__DOT__full_r))) + & (~ (((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__cwbq_push_stall) + | (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__mrvq_push_stall)) + | (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__dram_fill_req_stall)))) + & (~ (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__genblk2__DOT__full_r))); + vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__cwb_queue__DOT__writing + = (((((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__cwbq_push_unqual) + & (~ (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__cwb_queue__DOT__genblk3__DOT__genblk2__DOT__full_r))) + & (~ (vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__st_1e_2__DOT__value[0U] + >> 6U))) & (~ (((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__dwbq_push_stall) + | (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__mrvq_push_stall)) + | (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__dram_fill_req_stall)))) + & (~ (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__cwb_queue__DOT__genblk3__DOT__genblk2__DOT__full_r))); + vlTOPp->VX_cache__DOT__per_bank_dram_fill_req_valid + = ((0xbU & (IData)(vlTOPp->VX_cache__DOT__per_bank_dram_fill_req_valid)) + | ((((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__miss_add_unqual) + << 2U) & (((~ (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__mrvq_init_ready_state_st2)) + << 2U) | (0xfcU & ((vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__st_1e_2__DOT__value[9U] + >> 0x18U) + & ((~ + (vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__st_1e_2__DOT__value[9U] + >> 0x1bU)) + << 2U))))) + & ((~ (((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__dwbq_push_stall) + | (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__mrvq_push_stall)) + | (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__cwbq_push_stall))) + << 2U))); + vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__stall_bank_pipe + = ((((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__cwbq_push_stall) + | (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__dwbq_push_stall)) + | (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__mrvq_push_stall)) + | (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__dram_fill_req_stall)); + vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__force_request_miss_st1e + = (((vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__valid_st1 + [0U] & (~ vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__is_mrvq_st1 + [0U])) & ((0U != (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__cache_miss_resrv__DOT__valid_address_match)) + | ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__miss_add_because_miss) + & (((0x3ffffffU & + ((vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__st_1e_2__DOT__value[9U] + << 7U) | ( + vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__st_1e_2__DOT__value[8U] + >> 0x19U))) + == vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__addr_st1 + [0U]) & (~ (vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__st_1e_2__DOT__value[9U] + >> 0x14U)))))) + | ((vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__valid_st1 + [0U] & vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__is_mrvq_st1 + [0U]) & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__recover_mrvq_state_st2))); + vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__miss_add + = (((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__miss_add_unqual) + & (0x10U != (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__cache_miss_resrv__DOT__size))) + & (~ (((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__cwbq_push_stall) + | (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__dwbq_push_stall)) + | (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__dram_fill_req_stall)))); + vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__dwb_queue__DOT__writing + = ((((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__dwbq_push_unqual) + & (~ (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__genblk2__DOT__full_r))) + & (~ (((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__cwbq_push_stall) + | (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__mrvq_push_stall)) + | (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__dram_fill_req_stall)))) + & (~ (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__genblk2__DOT__full_r))); + vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__cwb_queue__DOT__writing + = (((((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__cwbq_push_unqual) + & (~ (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__cwb_queue__DOT__genblk3__DOT__genblk2__DOT__full_r))) + & (~ (vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__st_1e_2__DOT__value[0U] + >> 6U))) & (~ (((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__dwbq_push_stall) + | (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__mrvq_push_stall)) + | (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__dram_fill_req_stall)))) + & (~ (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__cwb_queue__DOT__genblk3__DOT__genblk2__DOT__full_r))); + vlTOPp->VX_cache__DOT__per_bank_dram_fill_req_valid + = ((0xdU & (IData)(vlTOPp->VX_cache__DOT__per_bank_dram_fill_req_valid)) + | ((((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__miss_add_unqual) + << 1U) & (((~ (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__mrvq_init_ready_state_st2)) + << 1U) | (0x7eU & ((vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__st_1e_2__DOT__value[9U] + >> 0x19U) + & ((~ + (vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__st_1e_2__DOT__value[9U] + >> 0x1bU)) + << 1U))))) + & ((~ (((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__dwbq_push_stall) + | (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__mrvq_push_stall)) + | (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__cwbq_push_stall))) + << 1U))); + vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__stall_bank_pipe + = ((((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__cwbq_push_stall) + | (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__dwbq_push_stall)) + | (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__mrvq_push_stall)) + | (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__dram_fill_req_stall)); + vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__force_request_miss_st1e + = (((vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__valid_st1 + [0U] & (~ vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__is_mrvq_st1 + [0U])) & ((0U != (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__cache_miss_resrv__DOT__valid_address_match)) + | ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__miss_add_because_miss) + & (((0x3ffffffU & + ((vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__st_1e_2__DOT__value[9U] + << 7U) | ( + vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__st_1e_2__DOT__value[8U] + >> 0x19U))) + == vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__addr_st1 + [0U]) & (~ (vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__st_1e_2__DOT__value[9U] + >> 0x14U)))))) + | ((vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__valid_st1 + [0U] & vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__is_mrvq_st1 + [0U]) & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__recover_mrvq_state_st2))); + vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__miss_add + = (((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__miss_add_unqual) + & (0x10U != (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cache_miss_resrv__DOT__size))) + & (~ (((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cwbq_push_stall) + | (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__dwbq_push_stall)) + | (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__dram_fill_req_stall)))); + vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__dwb_queue__DOT__writing + = ((((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__dwbq_push_unqual) + & (~ (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__genblk2__DOT__full_r))) + & (~ (((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cwbq_push_stall) + | (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__mrvq_push_stall)) + | (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__dram_fill_req_stall)))) + & (~ (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__genblk2__DOT__full_r))); + vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cwb_queue__DOT__writing + = (((((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cwbq_push_unqual) + & (~ (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cwb_queue__DOT__genblk3__DOT__genblk2__DOT__full_r))) + & (~ (vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__st_1e_2__DOT__value[0U] + >> 6U))) & (~ (((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__dwbq_push_stall) + | (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__mrvq_push_stall)) + | (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__dram_fill_req_stall)))) + & (~ (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cwb_queue__DOT__genblk3__DOT__genblk2__DOT__full_r))); + vlTOPp->VX_cache__DOT__per_bank_dram_fill_req_valid + = ((0xeU & (IData)(vlTOPp->VX_cache__DOT__per_bank_dram_fill_req_valid)) + | (((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__miss_add_unqual) + & ((~ (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__mrvq_init_ready_state_st2)) + | ((vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__st_1e_2__DOT__value[9U] + >> 0x1aU) & (~ (vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__st_1e_2__DOT__value[9U] + >> 0x1bU))))) + & (~ (((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__dwbq_push_stall) + | (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__mrvq_push_stall)) + | (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cwbq_push_stall))))); + vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__stall_bank_pipe + = ((((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cwbq_push_stall) + | (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__dwbq_push_stall)) + | (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__mrvq_push_stall)) + | (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__dram_fill_req_stall)); + vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__force_request_miss_st1e + = (((vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__valid_st1 + [0U] & (~ vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__is_mrvq_st1 + [0U])) & ((0U != (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cache_miss_resrv__DOT__valid_address_match)) + | ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__miss_add_because_miss) + & (((0x3ffffffU & + ((vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__st_1e_2__DOT__value[9U] + << 7U) | ( + vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__st_1e_2__DOT__value[8U] + >> 0x19U))) + == vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__addr_st1 + [0U]) & (~ (vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__st_1e_2__DOT__value[9U] + >> 0x14U)))))) + | ((vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__valid_st1 + [0U] & vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__is_mrvq_st1 + [0U]) & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__recover_mrvq_state_st2))); + vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__tag_data_access__DOT__data_write[0U] + = ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__tag_data_access__DOT__real_writefill) + ? vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__writedata_st1 + [0U][0U] : vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__writeword_st1 + [0U]); + vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__tag_data_access__DOT__data_write[1U] + = ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__tag_data_access__DOT__real_writefill) + ? vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__writedata_st1 + [0U][1U] : vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__writeword_st1 + [0U]); + vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__tag_data_access__DOT__data_write[2U] + = ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__tag_data_access__DOT__real_writefill) + ? vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__writedata_st1 + [0U][2U] : vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__writeword_st1 + [0U]); + vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__tag_data_access__DOT__data_write[3U] + = ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__tag_data_access__DOT__real_writefill) + ? vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__writedata_st1 + [0U][3U] : vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__writeword_st1 + [0U]); + vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__tag_data_access__DOT__data_write[0U] + = ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__tag_data_access__DOT__real_writefill) + ? vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__writedata_st1 + [0U][0U] : vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__writeword_st1 + [0U]); + vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__tag_data_access__DOT__data_write[1U] + = ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__tag_data_access__DOT__real_writefill) + ? vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__writedata_st1 + [0U][1U] : vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__writeword_st1 + [0U]); + vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__tag_data_access__DOT__data_write[2U] + = ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__tag_data_access__DOT__real_writefill) + ? vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__writedata_st1 + [0U][2U] : vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__writeword_st1 + [0U]); + vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__tag_data_access__DOT__data_write[3U] + = ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__tag_data_access__DOT__real_writefill) + ? vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__writedata_st1 + [0U][3U] : vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__writeword_st1 + [0U]); + vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__tag_data_access__DOT__data_write[0U] + = ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__tag_data_access__DOT__real_writefill) + ? vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__writedata_st1 + [0U][0U] : vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__writeword_st1 + [0U]); + vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__tag_data_access__DOT__data_write[1U] + = ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__tag_data_access__DOT__real_writefill) + ? vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__writedata_st1 + [0U][1U] : vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__writeword_st1 + [0U]); + vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__tag_data_access__DOT__data_write[2U] + = ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__tag_data_access__DOT__real_writefill) + ? vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__writedata_st1 + [0U][2U] : vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__writeword_st1 + [0U]); + vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__tag_data_access__DOT__data_write[3U] + = ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__tag_data_access__DOT__real_writefill) + ? vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__writedata_st1 + [0U][3U] : vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__writeword_st1 + [0U]); + vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__tag_data_access__DOT__data_write[0U] + = ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__tag_data_access__DOT__real_writefill) + ? vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__writedata_st1 + [0U][0U] : vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__writeword_st1 + [0U]); + vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__tag_data_access__DOT__data_write[1U] + = ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__tag_data_access__DOT__real_writefill) + ? vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__writedata_st1 + [0U][1U] : vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__writeword_st1 + [0U]); + vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__tag_data_access__DOT__data_write[2U] + = ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__tag_data_access__DOT__real_writefill) + ? vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__writedata_st1 + [0U][2U] : vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__writeword_st1 + [0U]); + vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__tag_data_access__DOT__data_write[3U] + = ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__tag_data_access__DOT__real_writefill) + ? vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__writedata_st1 + [0U][3U] : vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__writeword_st1 + [0U]); + vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__miss_add_is_mrvq + = (1U & (((vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__st_1e_2__DOT__value[9U] + >> 0x13U) & (vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__st_1e_2__DOT__value[9U] + >> 0x1aU)) & (~ (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__stall_bank_pipe)))); + vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__reqq_pop + = ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__reqq_pop_unqual) + & (~ (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__stall_bank_pipe))); + vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__dfpq_pop + = ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__dfpq_pop_unqual) + & (~ (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__stall_bank_pipe))); + vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__snrq_pop + = ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__snrq_pop_unqual) + & (~ (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__stall_bank_pipe))); + vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__mrvq_pop + = (((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cache_miss_resrv__DOT__dequeue_possible) + & (~ (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__stall_bank_pipe))) + & (~ (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__recover_mrvq_state_st2))); + vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__snp_to_mrvq_st1e + = ((vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__valid_st1 + [0U] & vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__is_snp_st1 + [0U]) & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__force_request_miss_st1e)); + vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__tag_data_access__DOT__snoop_hit_no_pending + = (((((vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__valid_st1 + [0U] & vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__is_snp_st1 + [0U]) & vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__tag_data_access__DOT__read_valid_st1c + [0U]) & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__tag_data_access__DOT__tags_match)) + & (vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__tag_data_access__DOT__read_dirty_st1c + [0U] | vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__snp_invalidate_st1 + [0U])) & (~ (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__force_request_miss_st1e))); + vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__miss_add_is_mrvq + = (1U & (((vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__st_1e_2__DOT__value[9U] + >> 0x13U) & (vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__st_1e_2__DOT__value[9U] + >> 0x1aU)) & (~ (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__stall_bank_pipe)))); + vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__reqq_pop + = ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__reqq_pop_unqual) + & (~ (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__stall_bank_pipe))); + vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__dfpq_pop + = ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__dfpq_pop_unqual) + & (~ (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__stall_bank_pipe))); + vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__snrq_pop + = ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__snrq_pop_unqual) + & (~ (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__stall_bank_pipe))); + vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__mrvq_pop + = (((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__cache_miss_resrv__DOT__dequeue_possible) + & (~ (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__stall_bank_pipe))) + & (~ (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__recover_mrvq_state_st2))); + vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__snp_to_mrvq_st1e + = ((vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__valid_st1 + [0U] & vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__is_snp_st1 + [0U]) & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__force_request_miss_st1e)); + vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__tag_data_access__DOT__snoop_hit_no_pending + = (((((vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__valid_st1 + [0U] & vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__is_snp_st1 + [0U]) & vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__tag_data_access__DOT__read_valid_st1c + [0U]) & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__tag_data_access__DOT__tags_match)) + & (vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__tag_data_access__DOT__read_dirty_st1c + [0U] | vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__snp_invalidate_st1 + [0U])) & (~ (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__force_request_miss_st1e))); + vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__miss_add_is_mrvq + = (1U & (((vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__st_1e_2__DOT__value[9U] + >> 0x13U) & (vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__st_1e_2__DOT__value[9U] + >> 0x1aU)) & (~ (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__stall_bank_pipe)))); + vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__reqq_pop + = ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__reqq_pop_unqual) + & (~ (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__stall_bank_pipe))); + vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__dfpq_pop + = ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__dfpq_pop_unqual) + & (~ (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__stall_bank_pipe))); + vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__snrq_pop + = ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__snrq_pop_unqual) + & (~ (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__stall_bank_pipe))); + vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__mrvq_pop + = (((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__cache_miss_resrv__DOT__dequeue_possible) + & (~ (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__stall_bank_pipe))) + & (~ (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__recover_mrvq_state_st2))); + vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__snp_to_mrvq_st1e + = ((vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__valid_st1 + [0U] & vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__is_snp_st1 + [0U]) & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__force_request_miss_st1e)); + vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__tag_data_access__DOT__snoop_hit_no_pending + = (((((vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__valid_st1 + [0U] & vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__is_snp_st1 + [0U]) & vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__tag_data_access__DOT__read_valid_st1c + [0U]) & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__tag_data_access__DOT__tags_match)) + & (vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__tag_data_access__DOT__read_dirty_st1c + [0U] | vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__snp_invalidate_st1 + [0U])) & (~ (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__force_request_miss_st1e))); + vlTOPp->VX_cache__DOT__cache_dram_req_arb__DOT__dram_fill_arb__DOT____Vcellinp__dfqq_queue__data_in[0U] + = vlTOPp->VX_cache__DOT__per_bank_dram_fill_req_addr[0U]; + vlTOPp->VX_cache__DOT__cache_dram_req_arb__DOT__dram_fill_arb__DOT____Vcellinp__dfqq_queue__data_in[1U] + = vlTOPp->VX_cache__DOT__per_bank_dram_fill_req_addr[1U]; + vlTOPp->VX_cache__DOT__cache_dram_req_arb__DOT__dram_fill_arb__DOT____Vcellinp__dfqq_queue__data_in[2U] + = vlTOPp->VX_cache__DOT__per_bank_dram_fill_req_addr[2U]; + vlTOPp->VX_cache__DOT__cache_dram_req_arb__DOT__dram_fill_arb__DOT____Vcellinp__dfqq_queue__data_in[3U] + = ((0xffff0000U & ((IData)(vlTOPp->VX_cache__DOT__per_bank_dram_fill_req_valid) + << 0x10U)) | vlTOPp->VX_cache__DOT__per_bank_dram_fill_req_addr[3U]); + vlTOPp->VX_cache__DOT__cache_dram_req_arb__DOT__dram_fill_arb__DOT__dfqq_queue__DOT__writing + = (((0U != (IData)(vlTOPp->VX_cache__DOT__per_bank_dram_fill_req_valid)) + & (~ (IData)(vlTOPp->VX_cache__DOT__cache_dram_req_arb__DOT__dram_fill_arb__DOT__dfqq_queue__DOT__genblk3__DOT__genblk2__DOT__full_r))) + & (~ (IData)(vlTOPp->VX_cache__DOT__cache_dram_req_arb__DOT__dram_fill_arb__DOT__dfqq_queue__DOT__genblk3__DOT__genblk2__DOT__full_r))); + vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__miss_add_is_mrvq + = (1U & (((vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__st_1e_2__DOT__value[9U] + >> 0x13U) & (vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__st_1e_2__DOT__value[9U] + >> 0x1aU)) & (~ (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__stall_bank_pipe)))); + vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__reqq_pop + = ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__reqq_pop_unqual) + & (~ (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__stall_bank_pipe))); + vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__dfpq_pop + = ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__dfpq_pop_unqual) + & (~ (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__stall_bank_pipe))); + vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__snrq_pop + = ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__snrq_pop_unqual) + & (~ (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__stall_bank_pipe))); + vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__mrvq_pop + = (((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cache_miss_resrv__DOT__dequeue_possible) + & (~ (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__stall_bank_pipe))) + & (~ (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__recover_mrvq_state_st2))); + vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__snp_to_mrvq_st1e + = ((vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__valid_st1 + [0U] & vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__is_snp_st1 + [0U]) & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__force_request_miss_st1e)); + vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__tag_data_access__DOT__snoop_hit_no_pending + = (((((vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__valid_st1 + [0U] & vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__is_snp_st1 + [0U]) & vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__tag_data_access__DOT__read_valid_st1c + [0U]) & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__tag_data_access__DOT__tags_match)) + & (vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__tag_data_access__DOT__read_dirty_st1c + [0U] | vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__snp_invalidate_st1 + [0U])) & (~ (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__force_request_miss_st1e))); + vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cache_miss_resrv__DOT__increment_head + = ((~ (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__miss_add)) + & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__miss_add_is_mrvq)); + vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cache_miss_resrv__DOT__mrvq_push + = (((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__miss_add) + & (0x10U != (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cache_miss_resrv__DOT__size))) + & (~ (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__miss_add_is_mrvq))); + vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__dfp_queue__DOT__reading + = ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__dfpq_pop) + & (~ (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__dfp_queue__DOT__genblk3__DOT__genblk2__DOT__empty_r))); + vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__snp_req_queue__DOT__reading + = ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__snrq_pop) + & (~ (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__snp_req_queue__DOT__genblk3__DOT__genblk2__DOT__empty_r))); + vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cache_miss_resrv__DOT__mrvq_pop + = ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__mrvq_pop) + & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cache_miss_resrv__DOT__dequeue_possible)); + __Vtemp401[4U] = ((0xfffffffeU & ((IData)(((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cache_miss_resrv__DOT__dequeue_possible) + ? ( + (VL_ULL(0x1ffffffffff80) + & (((QData)((IData)( + vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cache_miss_resrv__DOT__metadata_table + [vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr][2U])) + << 0x3eU) + | (((QData)((IData)( + vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cache_miss_resrv__DOT__metadata_table + [vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr][1U])) + << 0x1eU) + | (VL_ULL(0x3fffffffffffff80) + & ((QData)((IData)( + vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cache_miss_resrv__DOT__metadata_table + [vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr][0U])) + >> 2U))))) + | (QData)((IData)( + (((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__mrvq_rw_st0) + << 6U) + | ((0x3cU + & ((vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cache_miss_resrv__DOT__metadata_table + [vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr][1U] + << 0x1eU) + | (0x3ffffffcU + & (vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cache_miss_resrv__DOT__metadata_table + [vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr][0U] + >> 2U)))) + | (3U + & ((vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cache_miss_resrv__DOT__metadata_table + [vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr][2U] + << 0xdU) + | (vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cache_miss_resrv__DOT__metadata_table + [vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr][1U] + >> 0x13U)))))))) + : ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__reqq_pop_unqual) + ? + ((vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__core_req_arb__DOT__use_per_tag + << 7U) + | (QData)((IData)( + (((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__reqq_req_rw_st0) + << 6U) + | ((0x3cU + & (((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__core_req_arb__DOT__use_per_byteen) + >> + (0xfU + & ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__core_req_arb__DOT__qual_request_index) + << 2U))) + << 2U)) + | (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__core_req_arb__DOT__qual_request_index)))))) + : + ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__snrq_pop_unqual) + ? + ((QData)((IData)( + (0xfffffffU + & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT____Vcellout__snp_req_queue__data_out)))) + << 7U) + : VL_ULL(0))))) + << 1U)) | (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__dfpq_pop_unqual)); + __Vtemp401[5U] = ((1U & ((IData)(((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cache_miss_resrv__DOT__dequeue_possible) + ? ((VL_ULL(0x1ffffffffff80) + & (((QData)((IData)( + vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cache_miss_resrv__DOT__metadata_table + [vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr][2U])) + << 0x3eU) + | (((QData)((IData)( + vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cache_miss_resrv__DOT__metadata_table + [vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr][1U])) + << 0x1eU) + | (VL_ULL(0x3fffffffffffff80) + & ((QData)((IData)( + vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cache_miss_resrv__DOT__metadata_table + [vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr][0U])) + >> 2U))))) + | (QData)((IData)( + (((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__mrvq_rw_st0) + << 6U) + | ((0x3cU + & ((vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cache_miss_resrv__DOT__metadata_table + [vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr][1U] + << 0x1eU) + | (0x3ffffffcU + & (vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cache_miss_resrv__DOT__metadata_table + [vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr][0U] + >> 2U)))) + | (3U + & ((vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cache_miss_resrv__DOT__metadata_table + [vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr][2U] + << 0xdU) + | (vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cache_miss_resrv__DOT__metadata_table + [vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr][1U] + >> 0x13U)))))))) + : ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__reqq_pop_unqual) + ? ((vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__core_req_arb__DOT__use_per_tag + << 7U) + | (QData)((IData)( + (((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__reqq_req_rw_st0) + << 6U) + | ((0x3cU + & (((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__core_req_arb__DOT__use_per_byteen) + >> + (0xfU + & ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__core_req_arb__DOT__qual_request_index) + << 2U))) + << 2U)) + | (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__core_req_arb__DOT__qual_request_index)))))) + : ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__snrq_pop_unqual) + ? ((QData)((IData)( + (0xfffffffU + & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT____Vcellout__snp_req_queue__data_out)))) + << 7U) + : VL_ULL(0))))) + >> 0x1fU)) | (0xfffffffeU + & ((IData)( + (((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cache_miss_resrv__DOT__dequeue_possible) + ? + ((VL_ULL(0x1ffffffffff80) + & (((QData)((IData)( + vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cache_miss_resrv__DOT__metadata_table + [vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr][2U])) + << 0x3eU) + | (((QData)((IData)( + vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cache_miss_resrv__DOT__metadata_table + [vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr][1U])) + << 0x1eU) + | (VL_ULL(0x3fffffffffffff80) + & ((QData)((IData)( + vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cache_miss_resrv__DOT__metadata_table + [vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr][0U])) + >> 2U))))) + | (QData)((IData)( + (((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__mrvq_rw_st0) + << 6U) + | ((0x3cU + & ((vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cache_miss_resrv__DOT__metadata_table + [vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr][1U] + << 0x1eU) + | (0x3ffffffcU + & (vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cache_miss_resrv__DOT__metadata_table + [vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr][0U] + >> 2U)))) + | (3U + & ((vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cache_miss_resrv__DOT__metadata_table + [vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr][2U] + << 0xdU) + | (vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cache_miss_resrv__DOT__metadata_table + [vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr][1U] + >> 0x13U)))))))) + : + ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__reqq_pop_unqual) + ? + ((vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__core_req_arb__DOT__use_per_tag + << 7U) + | (QData)((IData)( + (((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__reqq_req_rw_st0) + << 6U) + | ((0x3cU + & (((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__core_req_arb__DOT__use_per_byteen) + >> + (0xfU + & ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__core_req_arb__DOT__qual_request_index) + << 2U))) + << 2U)) + | (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__core_req_arb__DOT__qual_request_index)))))) + : + ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__snrq_pop_unqual) + ? + ((QData)((IData)( + (0xfffffffU + & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT____Vcellout__snp_req_queue__data_out)))) + << 7U) + : VL_ULL(0)))) + >> 0x20U)) + << 1U))); + __Vtemp402[5U] = ((0xfffc0000U & ((IData)((((QData)((IData)( + ((0x80000000U + & (((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cache_miss_resrv__DOT__dequeue_possible) + ? + (1U + & (vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cache_miss_resrv__DOT__metadata_table + [vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr][0U] + >> 1U)) + : + ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__snrq_pop_unqual) + ? 1U + : 0U)) + << 0x1fU)) + | ((0x40000000U + & (((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cache_miss_resrv__DOT__dequeue_possible) + ? + (1U + & vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cache_miss_resrv__DOT__metadata_table + [vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr][0U]) + : + ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__snrq_pop_unqual) + ? + (1U + & (IData)( + (vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT____Vcellout__snp_req_queue__data_out + >> 0x1cU))) + : 0U)) + << 0x1eU)) + | ((((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__dfpq_pop_unqual) + ? 1U + : + (((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cache_miss_resrv__DOT__dequeue_possible) + & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__mrvq_rw_st0)) + ? 1U + : + (((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__reqq_pop_unqual) + & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__reqq_req_rw_st0)) + ? 1U + : 0U))) + << 0x1dU) + | ((((((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__dfpq_pop) + | (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__mrvq_pop)) + | (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__reqq_pop)) + | (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__snrq_pop)) + << 0x1cU) + | ((0xffffffcU + & (((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__dfpq_pop_unqual) + ? + (0x3ffffffU + & vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT____Vcellout__dfp_queue__data_out[4U]) + : + ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cache_miss_resrv__DOT__dequeue_possible) + ? + ((0x19fU + >= + (0x1ffU + & ((IData)(0x1aU) + * (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr)))) + ? + (0x3ffffffU + & (((0U + == + (0x1fU + & ((IData)(0x1aU) + * (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr)))) + ? 0U + : + (vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cache_miss_resrv__DOT__addr_table[ + ((IData)(1U) + + + (0xfU + & (((IData)(0x1aU) + * (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr)) + >> 5U)))] + << + ((IData)(0x20U) + - + (0x1fU + & ((IData)(0x1aU) + * (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr)))))) + | (vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cache_miss_resrv__DOT__addr_table[ + (0xfU + & (((IData)(0x1aU) + * (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr)) + >> 5U))] + >> + (0x1fU + & ((IData)(0x1aU) + * (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr)))))) + : 0U) + : + ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__reqq_pop_unqual) + ? + (0x3ffffffU + & (vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__reqq_req_addr_st0 + >> 4U)) + : + ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__snrq_pop_unqual) + ? + (0x3ffffffU + & (IData)( + (vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT____Vcellout__snp_req_queue__data_out + >> 0x1dU))) + : 0U)))) + << 2U)) + | (3U + & ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__reqq_pop_unqual) + ? + (3U + & vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__reqq_req_addr_st0) + : + ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cache_miss_resrv__DOT__dequeue_possible) + ? + (3U + & ((vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cache_miss_resrv__DOT__metadata_table + [vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr][1U] + << 0x1eU) + | (vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cache_miss_resrv__DOT__metadata_table + [vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr][0U] + >> 2U))) + : 0U)))))))))) + << 0x20U) + | (QData)((IData)( + ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cache_miss_resrv__DOT__dequeue_possible) + ? + ((vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cache_miss_resrv__DOT__metadata_table + [vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr][2U] + << 0xbU) + | (vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cache_miss_resrv__DOT__metadata_table + [vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr][1U] + >> 0x15U)) + : + ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__reqq_pop_unqual) + ? + (((0U + == + (0x1fU + & ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__core_req_arb__DOT__qual_request_index) + << 5U))) + ? 0U + : + (vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__core_req_arb__DOT__use_per_writedata[ + ((IData)(1U) + + + (3U + & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__core_req_arb__DOT__qual_request_index)))] + << + ((IData)(0x20U) + - + (0x1fU + & ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__core_req_arb__DOT__qual_request_index) + << 5U))))) + | (vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__core_req_arb__DOT__use_per_writedata[ + (3U + & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__core_req_arb__DOT__qual_request_index))] + >> + (0x1fU + & ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__core_req_arb__DOT__qual_request_index) + << 5U)))) + : 0U)))))) + << 0x12U)) | + __Vtemp401[5U]); + __Vtemp402[6U] = ((0x3ffffU & ((IData)((((QData)((IData)( + ((0x80000000U + & (((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cache_miss_resrv__DOT__dequeue_possible) + ? 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1U + : + (((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cache_miss_resrv__DOT__dequeue_possible) + & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__mrvq_rw_st0)) + ? 1U + : + (((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__reqq_pop_unqual) + & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__reqq_req_rw_st0)) + ? 1U + : 0U))) + << 0x1dU) + | ((((((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__dfpq_pop) + | (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__mrvq_pop)) + | (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__reqq_pop)) + | (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__snrq_pop)) + << 0x1cU) + | ((0xffffffcU + & (((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__dfpq_pop_unqual) + ? + (0x3ffffffU + & vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT____Vcellout__dfp_queue__data_out[4U]) + : + ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cache_miss_resrv__DOT__dequeue_possible) + ? + ((0x19fU + >= + (0x1ffU + & ((IData)(0x1aU) + * (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr)))) + ? + (0x3ffffffU + & (((0U + == + (0x1fU + & ((IData)(0x1aU) + * (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr)))) + ? 0U + : + (vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cache_miss_resrv__DOT__addr_table[ + ((IData)(1U) + + + (0xfU + & (((IData)(0x1aU) + * (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr)) + >> 5U)))] + << + ((IData)(0x20U) + - + (0x1fU + & ((IData)(0x1aU) + * (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr)))))) + | (vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cache_miss_resrv__DOT__addr_table[ + (0xfU + & (((IData)(0x1aU) + * (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr)) + >> 5U))] + >> + (0x1fU + & ((IData)(0x1aU) + * (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr)))))) + : 0U) + : + ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__reqq_pop_unqual) + ? + (0x3ffffffU + & (vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__reqq_req_addr_st0 + >> 4U)) + : + ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__snrq_pop_unqual) + ? + (0x3ffffffU + & (IData)( + (vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT____Vcellout__snp_req_queue__data_out + >> 0x1dU))) + : 0U)))) + << 2U)) + | (3U + & ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__reqq_pop_unqual) + ? + (3U + & vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__reqq_req_addr_st0) + : + ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cache_miss_resrv__DOT__dequeue_possible) + ? + (3U + & ((vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cache_miss_resrv__DOT__metadata_table + [vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr][1U] + << 0x1eU) + | (vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cache_miss_resrv__DOT__metadata_table + [vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr][0U] + >> 2U))) + : 0U)))))))))) + << 0x20U) + | (QData)((IData)( + ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cache_miss_resrv__DOT__dequeue_possible) + ? + ((vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cache_miss_resrv__DOT__metadata_table + [vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr][2U] + << 0xbU) + | (vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cache_miss_resrv__DOT__metadata_table + [vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr][1U] + >> 0x15U)) + : + ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__reqq_pop_unqual) + ? + (((0U + == + (0x1fU + & ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__core_req_arb__DOT__qual_request_index) + << 5U))) + ? 0U + : + (vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__core_req_arb__DOT__use_per_writedata[ + ((IData)(1U) + + + (3U + & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__core_req_arb__DOT__qual_request_index)))] + << + ((IData)(0x20U) + - + (0x1fU + & ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__core_req_arb__DOT__qual_request_index) + << 5U))))) + | (vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__core_req_arb__DOT__use_per_writedata[ + (3U + & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__core_req_arb__DOT__qual_request_index))] + >> + (0x1fU + & ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__core_req_arb__DOT__qual_request_index) + << 5U)))) + : 0U)))))) + >> 0xeU)) | (0xfffc0000U + & ((IData)( + ((((QData)((IData)( + ((0x80000000U + & (((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cache_miss_resrv__DOT__dequeue_possible) + ? + (1U + & (vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cache_miss_resrv__DOT__metadata_table + [vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr][0U] + >> 1U)) + : + ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__snrq_pop_unqual) + ? 1U + : 0U)) + << 0x1fU)) + | ((0x40000000U + & (((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cache_miss_resrv__DOT__dequeue_possible) + ? + (1U + & vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cache_miss_resrv__DOT__metadata_table + [vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr][0U]) + : + ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__snrq_pop_unqual) + ? + (1U + & (IData)( + (vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT____Vcellout__snp_req_queue__data_out + >> 0x1cU))) + : 0U)) + << 0x1eU)) + | ((((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__dfpq_pop_unqual) + ? 1U + : + (((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cache_miss_resrv__DOT__dequeue_possible) + & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__mrvq_rw_st0)) + ? 1U + : + (((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__reqq_pop_unqual) + & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__reqq_req_rw_st0)) + ? 1U + : 0U))) + << 0x1dU) + | ((((((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__dfpq_pop) + | (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__mrvq_pop)) + | (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__reqq_pop)) + | (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__snrq_pop)) + << 0x1cU) + | ((0xffffffcU + & (((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__dfpq_pop_unqual) + ? + (0x3ffffffU + & vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT____Vcellout__dfp_queue__data_out[4U]) + : + ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cache_miss_resrv__DOT__dequeue_possible) + ? + ((0x19fU + >= + (0x1ffU + & ((IData)(0x1aU) + * (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr)))) + ? + (0x3ffffffU + & (((0U + == + (0x1fU + & ((IData)(0x1aU) + * (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr)))) + ? 0U + : + (vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cache_miss_resrv__DOT__addr_table[ + ((IData)(1U) + + + (0xfU + & (((IData)(0x1aU) + * (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr)) + >> 5U)))] + << + ((IData)(0x20U) + - + (0x1fU + & ((IData)(0x1aU) + * (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr)))))) + | (vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cache_miss_resrv__DOT__addr_table[ + (0xfU + & (((IData)(0x1aU) + * (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr)) + >> 5U))] + >> + (0x1fU + & ((IData)(0x1aU) + * (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr)))))) + : 0U) + : + ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__reqq_pop_unqual) + ? + (0x3ffffffU + & (vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__reqq_req_addr_st0 + >> 4U)) + : + ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__snrq_pop_unqual) + ? + (0x3ffffffU + & (IData)( + (vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT____Vcellout__snp_req_queue__data_out + >> 0x1dU))) + : 0U)))) + << 2U)) + | (3U + & ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__reqq_pop_unqual) + ? + (3U + & vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__reqq_req_addr_st0) + : + ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cache_miss_resrv__DOT__dequeue_possible) + ? + (3U + & ((vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cache_miss_resrv__DOT__metadata_table + [vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr][1U] + << 0x1eU) + | (vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cache_miss_resrv__DOT__metadata_table + [vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr][0U] + >> 2U))) + : 0U)))))))))) + << 0x20U) + | (QData)((IData)( + ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cache_miss_resrv__DOT__dequeue_possible) + ? + ((vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cache_miss_resrv__DOT__metadata_table + [vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr][2U] + << 0xbU) + | (vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cache_miss_resrv__DOT__metadata_table + [vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr][1U] + >> 0x15U)) + : + ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__reqq_pop_unqual) + ? + (((0U + == + (0x1fU + & ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__core_req_arb__DOT__qual_request_index) + << 5U))) + ? 0U + : + (vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__core_req_arb__DOT__use_per_writedata[ + ((IData)(1U) + + + (3U + & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__core_req_arb__DOT__qual_request_index)))] + << + ((IData)(0x20U) + - + (0x1fU + & ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__core_req_arb__DOT__qual_request_index) + << 5U))))) + | (vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__core_req_arb__DOT__use_per_writedata[ + (3U + & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__core_req_arb__DOT__qual_request_index))] + >> + (0x1fU + & ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__core_req_arb__DOT__qual_request_index) + << 5U)))) + : 0U))))) + >> 0x20U)) + << 0x12U))); + __Vtemp402[7U] = (0x3ffffU & ((IData)(((((QData)((IData)( + ((0x80000000U + & (((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cache_miss_resrv__DOT__dequeue_possible) + ? + (1U + & (vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cache_miss_resrv__DOT__metadata_table + [vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr][0U] + >> 1U)) + : + ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__snrq_pop_unqual) + ? 1U + : 0U)) + << 0x1fU)) + | ((0x40000000U + & (((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cache_miss_resrv__DOT__dequeue_possible) + ? + (1U + & vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cache_miss_resrv__DOT__metadata_table + [vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr][0U]) + : + ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__snrq_pop_unqual) + ? + (1U + & (IData)( + (vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT____Vcellout__snp_req_queue__data_out + >> 0x1cU))) + : 0U)) + << 0x1eU)) + | ((((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__dfpq_pop_unqual) + ? 1U + : + (((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cache_miss_resrv__DOT__dequeue_possible) + & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__mrvq_rw_st0)) + ? 1U + : + (((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__reqq_pop_unqual) + & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__reqq_req_rw_st0)) + ? 1U + : 0U))) + << 0x1dU) + | ((((((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__dfpq_pop) + | (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__mrvq_pop)) + | (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__reqq_pop)) + | (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__snrq_pop)) + << 0x1cU) + | ((0xffffffcU + & (((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__dfpq_pop_unqual) + ? + (0x3ffffffU + & vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT____Vcellout__dfp_queue__data_out[4U]) + : + ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cache_miss_resrv__DOT__dequeue_possible) + ? + ((0x19fU + >= + (0x1ffU + & ((IData)(0x1aU) + * (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr)))) + ? + (0x3ffffffU + & (((0U + == + (0x1fU + & ((IData)(0x1aU) + * (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr)))) + ? 0U + : + (vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cache_miss_resrv__DOT__addr_table[ + ((IData)(1U) + + + (0xfU + & (((IData)(0x1aU) + * (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr)) + >> 5U)))] + << + ((IData)(0x20U) + - + (0x1fU + & ((IData)(0x1aU) + * (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr)))))) + | (vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cache_miss_resrv__DOT__addr_table[ + (0xfU + & (((IData)(0x1aU) + * (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr)) + >> 5U))] + >> + (0x1fU + & ((IData)(0x1aU) + * (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr)))))) + : 0U) + : + ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__reqq_pop_unqual) + ? + (0x3ffffffU + & (vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__reqq_req_addr_st0 + >> 4U)) + : + ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__snrq_pop_unqual) + ? + (0x3ffffffU + & (IData)( + (vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT____Vcellout__snp_req_queue__data_out + >> 0x1dU))) + : 0U)))) + << 2U)) + | (3U + & ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__reqq_pop_unqual) + ? + (3U + & vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__reqq_req_addr_st0) + : + ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cache_miss_resrv__DOT__dequeue_possible) + ? + (3U + & ((vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cache_miss_resrv__DOT__metadata_table + [vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr][1U] + << 0x1eU) + | (vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cache_miss_resrv__DOT__metadata_table + [vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr][0U] + >> 2U))) + : 0U)))))))))) + << 0x20U) + | (QData)((IData)( + ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cache_miss_resrv__DOT__dequeue_possible) + ? + ((vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cache_miss_resrv__DOT__metadata_table + [vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr][2U] + << 0xbU) + | (vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cache_miss_resrv__DOT__metadata_table + [vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr][1U] + >> 0x15U)) + : + ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__reqq_pop_unqual) + ? + (((0U + == + (0x1fU + & ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__core_req_arb__DOT__qual_request_index) + << 5U))) + ? 0U + : + (vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__core_req_arb__DOT__use_per_writedata[ + ((IData)(1U) + + + (3U + & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__core_req_arb__DOT__qual_request_index)))] + << + ((IData)(0x20U) + - + (0x1fU + & ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__core_req_arb__DOT__qual_request_index) + << 5U))))) + | (vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__core_req_arb__DOT__use_per_writedata[ + (3U + & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__core_req_arb__DOT__qual_request_index))] + >> + (0x1fU + & ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__core_req_arb__DOT__qual_request_index) + << 5U)))) + : 0U))))) + >> 0x20U)) + >> 0xeU)); + vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT____Vcellinp__s0_1_c0__in[0U] + = ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__dfpq_pop_unqual) + ? vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT____Vcellout__dfp_queue__data_out[0U] + : 0x39U); + vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT____Vcellinp__s0_1_c0__in[1U] + = ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__dfpq_pop_unqual) + ? vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT____Vcellout__dfp_queue__data_out[1U] + : 0U); + vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT____Vcellinp__s0_1_c0__in[2U] + = ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__dfpq_pop_unqual) + ? vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT____Vcellout__dfp_queue__data_out[2U] + : 0U); + vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT____Vcellinp__s0_1_c0__in[3U] + = ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__dfpq_pop_unqual) + ? vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT____Vcellout__dfp_queue__data_out[3U] + : 0U); + vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT____Vcellinp__s0_1_c0__in[4U] + = __Vtemp401[4U]; + vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT____Vcellinp__s0_1_c0__in[5U] + = __Vtemp402[5U]; + vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT____Vcellinp__s0_1_c0__in[6U] + = __Vtemp402[6U]; + vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT____Vcellinp__s0_1_c0__in[7U] + = ((0xfffc0000U & ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cache_miss_resrv__DOT__dequeue_possible) + << 0x12U)) | __Vtemp402[7U]); + vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__miss_st1e + = (((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__tag_data_access__DOT__real_miss) + | (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__tag_data_access__DOT__snoop_hit_no_pending)) + | (((((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__force_request_miss_st1e) + & (~ vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__is_snp_st1 + [0U])) & (~ vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__is_fill_st1 + [0U])) & vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__valid_st1 + [0U]) & (~ (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__tag_data_access__DOT__real_miss)))); + vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__cache_miss_resrv__DOT__increment_head + = ((~ (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__miss_add)) + & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__miss_add_is_mrvq)); + vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__cache_miss_resrv__DOT__mrvq_push + = (((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__miss_add) + & (0x10U != (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__cache_miss_resrv__DOT__size))) + & (~ (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__miss_add_is_mrvq))); + vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__dfp_queue__DOT__reading + = ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__dfpq_pop) + & (~ (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__dfp_queue__DOT__genblk3__DOT__genblk2__DOT__empty_r))); + vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__snp_req_queue__DOT__reading + = ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__snrq_pop) + & (~ (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__snp_req_queue__DOT__genblk3__DOT__genblk2__DOT__empty_r))); + vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__cache_miss_resrv__DOT__mrvq_pop + = ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__mrvq_pop) + & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__cache_miss_resrv__DOT__dequeue_possible)); + __Vtemp415[4U] = ((0xfffffffeU & ((IData)(((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__cache_miss_resrv__DOT__dequeue_possible) + ? ( + (VL_ULL(0x1ffffffffff80) + & (((QData)((IData)( + vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__cache_miss_resrv__DOT__metadata_table + [vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr][2U])) + << 0x3eU) + | (((QData)((IData)( + vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__cache_miss_resrv__DOT__metadata_table + [vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr][1U])) + << 0x1eU) + | (VL_ULL(0x3fffffffffffff80) + & ((QData)((IData)( + vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__cache_miss_resrv__DOT__metadata_table + [vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr][0U])) + >> 2U))))) + | (QData)((IData)( + (((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__mrvq_rw_st0) + << 6U) + | ((0x3cU + & ((vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__cache_miss_resrv__DOT__metadata_table + [vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr][1U] + << 0x1eU) + | (0x3ffffffcU + & (vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__cache_miss_resrv__DOT__metadata_table + [vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr][0U] + >> 2U)))) + | (3U + & ((vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__cache_miss_resrv__DOT__metadata_table + [vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr][2U] + << 0xdU) + | (vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__cache_miss_resrv__DOT__metadata_table + [vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr][1U] + >> 0x13U)))))))) + : ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__reqq_pop_unqual) + ? + ((vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__core_req_arb__DOT__use_per_tag + << 7U) + | (QData)((IData)( + (((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__reqq_req_rw_st0) + << 6U) + | ((0x3cU + & (((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__core_req_arb__DOT__use_per_byteen) + >> + (0xfU + & ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__core_req_arb__DOT__qual_request_index) + << 2U))) + << 2U)) + | (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__core_req_arb__DOT__qual_request_index)))))) + : + ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__snrq_pop_unqual) + ? + ((QData)((IData)( + (0xfffffffU + & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT____Vcellout__snp_req_queue__data_out)))) + << 7U) + : VL_ULL(0))))) + << 1U)) | (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__dfpq_pop_unqual)); + __Vtemp415[5U] = ((1U & ((IData)(((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__cache_miss_resrv__DOT__dequeue_possible) + ? ((VL_ULL(0x1ffffffffff80) + & (((QData)((IData)( + vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__cache_miss_resrv__DOT__metadata_table + [vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr][2U])) + << 0x3eU) + | (((QData)((IData)( + vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__cache_miss_resrv__DOT__metadata_table + [vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr][1U])) + << 0x1eU) + | (VL_ULL(0x3fffffffffffff80) + & ((QData)((IData)( + vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__cache_miss_resrv__DOT__metadata_table + [vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr][0U])) + >> 2U))))) + | (QData)((IData)( + (((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__mrvq_rw_st0) + << 6U) + | ((0x3cU + & ((vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__cache_miss_resrv__DOT__metadata_table + [vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr][1U] + << 0x1eU) + | (0x3ffffffcU + & (vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__cache_miss_resrv__DOT__metadata_table + [vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr][0U] + >> 2U)))) + | (3U + & ((vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__cache_miss_resrv__DOT__metadata_table + [vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr][2U] + << 0xdU) + | (vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__cache_miss_resrv__DOT__metadata_table + [vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr][1U] + >> 0x13U)))))))) + : ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__reqq_pop_unqual) + ? ((vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__core_req_arb__DOT__use_per_tag + << 7U) + | (QData)((IData)( + (((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__reqq_req_rw_st0) + << 6U) + | ((0x3cU + & (((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__core_req_arb__DOT__use_per_byteen) + >> + (0xfU + & ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__core_req_arb__DOT__qual_request_index) + << 2U))) + << 2U)) + | (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__core_req_arb__DOT__qual_request_index)))))) + : ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__snrq_pop_unqual) + ? ((QData)((IData)( + (0xfffffffU + & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT____Vcellout__snp_req_queue__data_out)))) + << 7U) + : VL_ULL(0))))) + >> 0x1fU)) | (0xfffffffeU + & ((IData)( + (((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__cache_miss_resrv__DOT__dequeue_possible) + ? + ((VL_ULL(0x1ffffffffff80) + & (((QData)((IData)( + vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__cache_miss_resrv__DOT__metadata_table + [vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr][2U])) + << 0x3eU) + | (((QData)((IData)( + vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__cache_miss_resrv__DOT__metadata_table + [vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr][1U])) + << 0x1eU) + | (VL_ULL(0x3fffffffffffff80) + & ((QData)((IData)( + vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__cache_miss_resrv__DOT__metadata_table + [vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr][0U])) + >> 2U))))) + | (QData)((IData)( + (((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__mrvq_rw_st0) + << 6U) + | ((0x3cU + & ((vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__cache_miss_resrv__DOT__metadata_table + [vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr][1U] + << 0x1eU) + | (0x3ffffffcU + & (vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__cache_miss_resrv__DOT__metadata_table + [vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr][0U] + >> 2U)))) + | (3U + & ((vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__cache_miss_resrv__DOT__metadata_table + [vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr][2U] + << 0xdU) + | (vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__cache_miss_resrv__DOT__metadata_table + [vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr][1U] + >> 0x13U)))))))) + : + ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__reqq_pop_unqual) + ? + ((vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__core_req_arb__DOT__use_per_tag + << 7U) + | (QData)((IData)( + (((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__reqq_req_rw_st0) + << 6U) + | ((0x3cU + & (((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__core_req_arb__DOT__use_per_byteen) + >> + (0xfU + & ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__core_req_arb__DOT__qual_request_index) + << 2U))) + << 2U)) + | (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__core_req_arb__DOT__qual_request_index)))))) + : + ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__snrq_pop_unqual) + ? + ((QData)((IData)( + (0xfffffffU + & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT____Vcellout__snp_req_queue__data_out)))) + << 7U) + : VL_ULL(0)))) + >> 0x20U)) + << 1U))); + __Vtemp416[5U] = ((0xfffc0000U & ((IData)((((QData)((IData)( + ((0x80000000U + & (((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__cache_miss_resrv__DOT__dequeue_possible) + ? + (1U + & (vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__cache_miss_resrv__DOT__metadata_table + [vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr][0U] + >> 1U)) + : + ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__snrq_pop_unqual) + ? 1U + : 0U)) + << 0x1fU)) + | ((0x40000000U + & (((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__cache_miss_resrv__DOT__dequeue_possible) + ? + (1U + & vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__cache_miss_resrv__DOT__metadata_table + [vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr][0U]) + : + ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__snrq_pop_unqual) + ? + (1U + & (IData)( + (vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT____Vcellout__snp_req_queue__data_out + >> 0x1cU))) + : 0U)) + << 0x1eU)) + | ((((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__dfpq_pop_unqual) + ? 1U + : + (((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__cache_miss_resrv__DOT__dequeue_possible) + & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__mrvq_rw_st0)) + ? 1U + : + (((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__reqq_pop_unqual) + & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__reqq_req_rw_st0)) + ? 1U + : 0U))) + << 0x1dU) + | ((((((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__dfpq_pop) + | (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__mrvq_pop)) + | (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__reqq_pop)) + | (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__snrq_pop)) + << 0x1cU) + | ((0xffffffcU + & (((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__dfpq_pop_unqual) + ? + (0x3ffffffU + & vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT____Vcellout__dfp_queue__data_out[4U]) + : + ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__cache_miss_resrv__DOT__dequeue_possible) + ? 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+ ((vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__cache_miss_resrv__DOT__metadata_table + [vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr][2U] + << 0xbU) + | (vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__cache_miss_resrv__DOT__metadata_table + [vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr][1U] + >> 0x15U)) + : + ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__reqq_pop_unqual) + ? + (((0U + == + (0x1fU + & ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__core_req_arb__DOT__qual_request_index) + << 5U))) + ? 0U + : + (vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__core_req_arb__DOT__use_per_writedata[ + ((IData)(1U) + + + (3U + & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__core_req_arb__DOT__qual_request_index)))] + << + ((IData)(0x20U) + - + (0x1fU + & ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__core_req_arb__DOT__qual_request_index) + << 5U))))) + | (vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__core_req_arb__DOT__use_per_writedata[ + (3U + & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__core_req_arb__DOT__qual_request_index))] + >> + (0x1fU + & ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__core_req_arb__DOT__qual_request_index) + << 5U)))) + : 0U)))))) + << 0x12U)) | + __Vtemp415[5U]); + __Vtemp416[6U] = ((0x3ffffU & ((IData)((((QData)((IData)( + ((0x80000000U + & (((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__cache_miss_resrv__DOT__dequeue_possible) + ? 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1U + : + (((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__cache_miss_resrv__DOT__dequeue_possible) + & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__mrvq_rw_st0)) + ? 1U + : + (((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__reqq_pop_unqual) + & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__reqq_req_rw_st0)) + ? 1U + : 0U))) + << 0x1dU) + | ((((((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__dfpq_pop) + | (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__mrvq_pop)) + | (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__reqq_pop)) + | (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__snrq_pop)) + << 0x1cU) + | ((0xffffffcU + & (((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__dfpq_pop_unqual) + ? + (0x3ffffffU + & vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT____Vcellout__dfp_queue__data_out[4U]) + : + ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__cache_miss_resrv__DOT__dequeue_possible) + ? + ((0x19fU + >= + (0x1ffU + & ((IData)(0x1aU) + * (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr)))) + ? + (0x3ffffffU + & (((0U + == + (0x1fU + & ((IData)(0x1aU) + * (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr)))) + ? 0U + : + (vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__cache_miss_resrv__DOT__addr_table[ + ((IData)(1U) + + + (0xfU + & (((IData)(0x1aU) + * (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr)) + >> 5U)))] + << + ((IData)(0x20U) + - + (0x1fU + & ((IData)(0x1aU) + * (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr)))))) + | (vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__cache_miss_resrv__DOT__addr_table[ + (0xfU + & (((IData)(0x1aU) + * (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr)) + >> 5U))] + >> + (0x1fU + & ((IData)(0x1aU) + * (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr)))))) + : 0U) + : + ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__reqq_pop_unqual) + ? + (0x3ffffffU + & (vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__reqq_req_addr_st0 + >> 4U)) + : + ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__snrq_pop_unqual) + ? + (0x3ffffffU + & (IData)( + (vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT____Vcellout__snp_req_queue__data_out + >> 0x1dU))) + : 0U)))) + << 2U)) + | (3U + & ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__reqq_pop_unqual) + ? + (3U + & vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__reqq_req_addr_st0) + : + ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__cache_miss_resrv__DOT__dequeue_possible) + ? + (3U + & ((vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__cache_miss_resrv__DOT__metadata_table + [vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr][1U] + << 0x1eU) + | (vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__cache_miss_resrv__DOT__metadata_table + [vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr][0U] + >> 2U))) + : 0U)))))))))) + << 0x20U) + | (QData)((IData)( + ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__cache_miss_resrv__DOT__dequeue_possible) + ? + ((vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__cache_miss_resrv__DOT__metadata_table + [vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr][2U] + << 0xbU) + | (vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__cache_miss_resrv__DOT__metadata_table + [vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr][1U] + >> 0x15U)) + : + ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__reqq_pop_unqual) + ? + (((0U + == + (0x1fU + & ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__core_req_arb__DOT__qual_request_index) + << 5U))) + ? 0U + : + (vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__core_req_arb__DOT__use_per_writedata[ + ((IData)(1U) + + + (3U + & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__core_req_arb__DOT__qual_request_index)))] + << + ((IData)(0x20U) + - + (0x1fU + & ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__core_req_arb__DOT__qual_request_index) + << 5U))))) + | (vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__core_req_arb__DOT__use_per_writedata[ + (3U + & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__core_req_arb__DOT__qual_request_index))] + >> + (0x1fU + & ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__core_req_arb__DOT__qual_request_index) + << 5U)))) + : 0U)))))) + >> 0xeU)) | (0xfffc0000U + & ((IData)( + ((((QData)((IData)( + ((0x80000000U + & (((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__cache_miss_resrv__DOT__dequeue_possible) + ? + (1U + & (vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__cache_miss_resrv__DOT__metadata_table + [vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr][0U] + >> 1U)) + : + ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__snrq_pop_unqual) + ? 1U + : 0U)) + << 0x1fU)) + | ((0x40000000U + & (((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__cache_miss_resrv__DOT__dequeue_possible) + ? + (1U + & vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__cache_miss_resrv__DOT__metadata_table + [vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr][0U]) + : + ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__snrq_pop_unqual) + ? + (1U + & (IData)( + (vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT____Vcellout__snp_req_queue__data_out + >> 0x1cU))) + : 0U)) + << 0x1eU)) + | ((((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__dfpq_pop_unqual) + ? 1U + : + (((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__cache_miss_resrv__DOT__dequeue_possible) + & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__mrvq_rw_st0)) + ? 1U + : + (((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__reqq_pop_unqual) + & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__reqq_req_rw_st0)) + ? 1U + : 0U))) + << 0x1dU) + | ((((((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__dfpq_pop) + | (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__mrvq_pop)) + | (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__reqq_pop)) + | (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__snrq_pop)) + << 0x1cU) + | ((0xffffffcU + & (((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__dfpq_pop_unqual) + ? + (0x3ffffffU + & vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT____Vcellout__dfp_queue__data_out[4U]) + : + ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__cache_miss_resrv__DOT__dequeue_possible) + ? + ((0x19fU + >= + (0x1ffU + & ((IData)(0x1aU) + * (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr)))) + ? + (0x3ffffffU + & (((0U + == + (0x1fU + & ((IData)(0x1aU) + * (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr)))) + ? 0U + : + (vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__cache_miss_resrv__DOT__addr_table[ + ((IData)(1U) + + + (0xfU + & (((IData)(0x1aU) + * (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr)) + >> 5U)))] + << + ((IData)(0x20U) + - + (0x1fU + & ((IData)(0x1aU) + * (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr)))))) + | (vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__cache_miss_resrv__DOT__addr_table[ + (0xfU + & (((IData)(0x1aU) + * (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr)) + >> 5U))] + >> + (0x1fU + & ((IData)(0x1aU) + * (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr)))))) + : 0U) + : + ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__reqq_pop_unqual) + ? + (0x3ffffffU + & (vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__reqq_req_addr_st0 + >> 4U)) + : + ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__snrq_pop_unqual) + ? + (0x3ffffffU + & (IData)( + (vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT____Vcellout__snp_req_queue__data_out + >> 0x1dU))) + : 0U)))) + << 2U)) + | (3U + & ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__reqq_pop_unqual) + ? + (3U + & vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__reqq_req_addr_st0) + : + ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__cache_miss_resrv__DOT__dequeue_possible) + ? + (3U + & ((vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__cache_miss_resrv__DOT__metadata_table + [vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr][1U] + << 0x1eU) + | (vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__cache_miss_resrv__DOT__metadata_table + [vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr][0U] + >> 2U))) + : 0U)))))))))) + << 0x20U) + | (QData)((IData)( + ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__cache_miss_resrv__DOT__dequeue_possible) + ? + ((vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__cache_miss_resrv__DOT__metadata_table + [vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr][2U] + << 0xbU) + | (vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__cache_miss_resrv__DOT__metadata_table + [vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr][1U] + >> 0x15U)) + : + ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__reqq_pop_unqual) + ? + (((0U + == + (0x1fU + & ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__core_req_arb__DOT__qual_request_index) + << 5U))) + ? 0U + : + (vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__core_req_arb__DOT__use_per_writedata[ + ((IData)(1U) + + + (3U + & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__core_req_arb__DOT__qual_request_index)))] + << + ((IData)(0x20U) + - + (0x1fU + & ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__core_req_arb__DOT__qual_request_index) + << 5U))))) + | (vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__core_req_arb__DOT__use_per_writedata[ + (3U + & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__core_req_arb__DOT__qual_request_index))] + >> + (0x1fU + & ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__core_req_arb__DOT__qual_request_index) + << 5U)))) + : 0U))))) + >> 0x20U)) + << 0x12U))); + __Vtemp416[7U] = (0x3ffffU & ((IData)(((((QData)((IData)( + ((0x80000000U + & (((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__cache_miss_resrv__DOT__dequeue_possible) + ? + (1U + & (vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__cache_miss_resrv__DOT__metadata_table + [vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr][0U] + >> 1U)) + : + ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__snrq_pop_unqual) + ? 1U + : 0U)) + << 0x1fU)) + | ((0x40000000U + & (((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__cache_miss_resrv__DOT__dequeue_possible) + ? + (1U + & vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__cache_miss_resrv__DOT__metadata_table + [vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr][0U]) + : + ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__snrq_pop_unqual) + ? + (1U + & (IData)( + (vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT____Vcellout__snp_req_queue__data_out + >> 0x1cU))) + : 0U)) + << 0x1eU)) + | ((((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__dfpq_pop_unqual) + ? 1U + : + (((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__cache_miss_resrv__DOT__dequeue_possible) + & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__mrvq_rw_st0)) + ? 1U + : + (((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__reqq_pop_unqual) + & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__reqq_req_rw_st0)) + ? 1U + : 0U))) + << 0x1dU) + | ((((((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__dfpq_pop) + | (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__mrvq_pop)) + | (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__reqq_pop)) + | (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__snrq_pop)) + << 0x1cU) + | ((0xffffffcU + & (((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__dfpq_pop_unqual) + ? + (0x3ffffffU + & vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT____Vcellout__dfp_queue__data_out[4U]) + : + ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__cache_miss_resrv__DOT__dequeue_possible) + ? + ((0x19fU + >= + (0x1ffU + & ((IData)(0x1aU) + * (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr)))) + ? + (0x3ffffffU + & (((0U + == + (0x1fU + & ((IData)(0x1aU) + * (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr)))) + ? 0U + : + (vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__cache_miss_resrv__DOT__addr_table[ + ((IData)(1U) + + + (0xfU + & (((IData)(0x1aU) + * (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr)) + >> 5U)))] + << + ((IData)(0x20U) + - + (0x1fU + & ((IData)(0x1aU) + * (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr)))))) + | (vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__cache_miss_resrv__DOT__addr_table[ + (0xfU + & (((IData)(0x1aU) + * (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr)) + >> 5U))] + >> + (0x1fU + & ((IData)(0x1aU) + * (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr)))))) + : 0U) + : + ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__reqq_pop_unqual) + ? + (0x3ffffffU + & (vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__reqq_req_addr_st0 + >> 4U)) + : + ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__snrq_pop_unqual) + ? + (0x3ffffffU + & (IData)( + (vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT____Vcellout__snp_req_queue__data_out + >> 0x1dU))) + : 0U)))) + << 2U)) + | (3U + & ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__reqq_pop_unqual) + ? + (3U + & vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__reqq_req_addr_st0) + : + ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__cache_miss_resrv__DOT__dequeue_possible) + ? + (3U + & ((vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__cache_miss_resrv__DOT__metadata_table + [vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr][1U] + << 0x1eU) + | (vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__cache_miss_resrv__DOT__metadata_table + [vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr][0U] + >> 2U))) + : 0U)))))))))) + << 0x20U) + | (QData)((IData)( + ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__cache_miss_resrv__DOT__dequeue_possible) + ? + ((vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__cache_miss_resrv__DOT__metadata_table + [vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr][2U] + << 0xbU) + | (vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__cache_miss_resrv__DOT__metadata_table + [vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr][1U] + >> 0x15U)) + : + ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__reqq_pop_unqual) + ? + (((0U + == + (0x1fU + & ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__core_req_arb__DOT__qual_request_index) + << 5U))) + ? 0U + : + (vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__core_req_arb__DOT__use_per_writedata[ + ((IData)(1U) + + + (3U + & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__core_req_arb__DOT__qual_request_index)))] + << + ((IData)(0x20U) + - + (0x1fU + & ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__core_req_arb__DOT__qual_request_index) + << 5U))))) + | (vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__core_req_arb__DOT__use_per_writedata[ + (3U + & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__core_req_arb__DOT__qual_request_index))] + >> + (0x1fU + & ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__core_req_arb__DOT__qual_request_index) + << 5U)))) + : 0U))))) + >> 0x20U)) + >> 0xeU)); + vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT____Vcellinp__s0_1_c0__in[0U] + = ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__dfpq_pop_unqual) + ? vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT____Vcellout__dfp_queue__data_out[0U] + : 0x39U); + vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT____Vcellinp__s0_1_c0__in[1U] + = ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__dfpq_pop_unqual) + ? vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT____Vcellout__dfp_queue__data_out[1U] + : 0U); + vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT____Vcellinp__s0_1_c0__in[2U] + = ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__dfpq_pop_unqual) + ? vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT____Vcellout__dfp_queue__data_out[2U] + : 0U); + vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT____Vcellinp__s0_1_c0__in[3U] + = ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__dfpq_pop_unqual) + ? vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT____Vcellout__dfp_queue__data_out[3U] + : 0U); + vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT____Vcellinp__s0_1_c0__in[4U] + = __Vtemp415[4U]; + vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT____Vcellinp__s0_1_c0__in[5U] + = __Vtemp416[5U]; + vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT____Vcellinp__s0_1_c0__in[6U] + = __Vtemp416[6U]; + vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT____Vcellinp__s0_1_c0__in[7U] + = ((0xfffc0000U & ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__cache_miss_resrv__DOT__dequeue_possible) + << 0x12U)) | __Vtemp416[7U]); + vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__miss_st1e + = (((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__tag_data_access__DOT__real_miss) + | (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__tag_data_access__DOT__snoop_hit_no_pending)) + | (((((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__force_request_miss_st1e) + & (~ vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__is_snp_st1 + [0U])) & (~ vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__is_fill_st1 + [0U])) & vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__valid_st1 + [0U]) & (~ (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__tag_data_access__DOT__real_miss)))); + vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__cache_miss_resrv__DOT__increment_head + = ((~ (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__miss_add)) + & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__miss_add_is_mrvq)); + vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__cache_miss_resrv__DOT__mrvq_push + = (((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__miss_add) + & (0x10U != (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__cache_miss_resrv__DOT__size))) + & (~ (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__miss_add_is_mrvq))); + vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__dfp_queue__DOT__reading + = ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__dfpq_pop) + & (~ (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__dfp_queue__DOT__genblk3__DOT__genblk2__DOT__empty_r))); + vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__snp_req_queue__DOT__reading + = ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__snrq_pop) + & (~ (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__snp_req_queue__DOT__genblk3__DOT__genblk2__DOT__empty_r))); + vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__cache_miss_resrv__DOT__mrvq_pop + = ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__mrvq_pop) + & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__cache_miss_resrv__DOT__dequeue_possible)); + __Vtemp429[4U] = ((0xfffffffeU & ((IData)(((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__cache_miss_resrv__DOT__dequeue_possible) + ? ( + (VL_ULL(0x1ffffffffff80) + & (((QData)((IData)( + vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__cache_miss_resrv__DOT__metadata_table + [vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr][2U])) + << 0x3eU) + | (((QData)((IData)( + vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__cache_miss_resrv__DOT__metadata_table + [vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr][1U])) + << 0x1eU) + | (VL_ULL(0x3fffffffffffff80) + & ((QData)((IData)( + vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__cache_miss_resrv__DOT__metadata_table + [vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr][0U])) + >> 2U))))) + | (QData)((IData)( + (((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__mrvq_rw_st0) + << 6U) + | ((0x3cU + & ((vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__cache_miss_resrv__DOT__metadata_table + [vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr][1U] + << 0x1eU) + | (0x3ffffffcU + & (vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__cache_miss_resrv__DOT__metadata_table + [vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr][0U] + >> 2U)))) + | (3U + & ((vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__cache_miss_resrv__DOT__metadata_table + [vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr][2U] + << 0xdU) + | (vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__cache_miss_resrv__DOT__metadata_table + [vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr][1U] + >> 0x13U)))))))) + : ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__reqq_pop_unqual) + ? + ((vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__core_req_arb__DOT__use_per_tag + << 7U) + | (QData)((IData)( + (((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__reqq_req_rw_st0) + << 6U) + | ((0x3cU + & (((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__core_req_arb__DOT__use_per_byteen) + >> + (0xfU + & ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__core_req_arb__DOT__qual_request_index) + << 2U))) + << 2U)) + | (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__core_req_arb__DOT__qual_request_index)))))) + : + ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__snrq_pop_unqual) + ? + ((QData)((IData)( + (0xfffffffU + & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT____Vcellout__snp_req_queue__data_out)))) + << 7U) + : VL_ULL(0))))) + << 1U)) | (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__dfpq_pop_unqual)); + __Vtemp429[5U] = ((1U & ((IData)(((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__cache_miss_resrv__DOT__dequeue_possible) + ? ((VL_ULL(0x1ffffffffff80) + & (((QData)((IData)( + vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__cache_miss_resrv__DOT__metadata_table + [vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr][2U])) + << 0x3eU) + | (((QData)((IData)( + vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__cache_miss_resrv__DOT__metadata_table + [vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr][1U])) + << 0x1eU) + | (VL_ULL(0x3fffffffffffff80) + & ((QData)((IData)( + vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__cache_miss_resrv__DOT__metadata_table + [vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr][0U])) + >> 2U))))) + | (QData)((IData)( + (((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__mrvq_rw_st0) + << 6U) + | ((0x3cU + & ((vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__cache_miss_resrv__DOT__metadata_table + [vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr][1U] + << 0x1eU) + | (0x3ffffffcU + & (vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__cache_miss_resrv__DOT__metadata_table + [vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr][0U] + >> 2U)))) + | (3U + & ((vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__cache_miss_resrv__DOT__metadata_table + [vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr][2U] + << 0xdU) + | (vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__cache_miss_resrv__DOT__metadata_table + [vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr][1U] + >> 0x13U)))))))) + : ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__reqq_pop_unqual) + ? ((vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__core_req_arb__DOT__use_per_tag + << 7U) + | (QData)((IData)( + (((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__reqq_req_rw_st0) + << 6U) + | ((0x3cU + & (((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__core_req_arb__DOT__use_per_byteen) + >> + (0xfU + & ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__core_req_arb__DOT__qual_request_index) + << 2U))) + << 2U)) + | (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__core_req_arb__DOT__qual_request_index)))))) + : ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__snrq_pop_unqual) + ? ((QData)((IData)( + (0xfffffffU + & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT____Vcellout__snp_req_queue__data_out)))) + << 7U) + : VL_ULL(0))))) + >> 0x1fU)) | (0xfffffffeU + & ((IData)( + (((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__cache_miss_resrv__DOT__dequeue_possible) + ? + ((VL_ULL(0x1ffffffffff80) + & (((QData)((IData)( + vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__cache_miss_resrv__DOT__metadata_table + [vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr][2U])) + << 0x3eU) + | (((QData)((IData)( + vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__cache_miss_resrv__DOT__metadata_table + [vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr][1U])) + << 0x1eU) + | (VL_ULL(0x3fffffffffffff80) + & ((QData)((IData)( + vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__cache_miss_resrv__DOT__metadata_table + [vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr][0U])) + >> 2U))))) + | (QData)((IData)( + (((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__mrvq_rw_st0) + << 6U) + | ((0x3cU + & ((vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__cache_miss_resrv__DOT__metadata_table + [vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr][1U] + << 0x1eU) + | (0x3ffffffcU + & (vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__cache_miss_resrv__DOT__metadata_table + [vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr][0U] + >> 2U)))) + | (3U + & ((vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__cache_miss_resrv__DOT__metadata_table + [vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr][2U] + << 0xdU) + | (vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__cache_miss_resrv__DOT__metadata_table + [vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr][1U] + >> 0x13U)))))))) + : + ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__reqq_pop_unqual) + ? + ((vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__core_req_arb__DOT__use_per_tag + << 7U) + | (QData)((IData)( + (((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__reqq_req_rw_st0) + << 6U) + | ((0x3cU + & (((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__core_req_arb__DOT__use_per_byteen) + >> + (0xfU + & ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__core_req_arb__DOT__qual_request_index) + << 2U))) + << 2U)) + | (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__core_req_arb__DOT__qual_request_index)))))) + : + ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__snrq_pop_unqual) + ? + ((QData)((IData)( + (0xfffffffU + & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT____Vcellout__snp_req_queue__data_out)))) + << 7U) + : VL_ULL(0)))) + >> 0x20U)) + << 1U))); + __Vtemp430[5U] = ((0xfffc0000U & ((IData)((((QData)((IData)( + ((0x80000000U + & (((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__cache_miss_resrv__DOT__dequeue_possible) + ? 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1U + : + (((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__cache_miss_resrv__DOT__dequeue_possible) + & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__mrvq_rw_st0)) + ? 1U + : + (((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__reqq_pop_unqual) + & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__reqq_req_rw_st0)) + ? 1U + : 0U))) + << 0x1dU) + | ((((((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__dfpq_pop) + | (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__mrvq_pop)) + | (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__reqq_pop)) + | (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__snrq_pop)) + << 0x1cU) + | ((0xffffffcU + & (((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__dfpq_pop_unqual) + ? + (0x3ffffffU + & vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT____Vcellout__dfp_queue__data_out[4U]) + : + ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__cache_miss_resrv__DOT__dequeue_possible) + ? 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+ ((vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__cache_miss_resrv__DOT__metadata_table + [vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr][2U] + << 0xbU) + | (vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__cache_miss_resrv__DOT__metadata_table + [vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr][1U] + >> 0x15U)) + : + ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__reqq_pop_unqual) + ? + (((0U + == + (0x1fU + & ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__core_req_arb__DOT__qual_request_index) + << 5U))) + ? 0U + : + (vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__core_req_arb__DOT__use_per_writedata[ + ((IData)(1U) + + + (3U + & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__core_req_arb__DOT__qual_request_index)))] + << + ((IData)(0x20U) + - + (0x1fU + & ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__core_req_arb__DOT__qual_request_index) + << 5U))))) + | (vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__core_req_arb__DOT__use_per_writedata[ + (3U + & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__core_req_arb__DOT__qual_request_index))] + >> + (0x1fU + & ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__core_req_arb__DOT__qual_request_index) + << 5U)))) + : 0U)))))) + << 0x12U)) | + __Vtemp429[5U]); + __Vtemp430[6U] = ((0x3ffffU & ((IData)((((QData)((IData)( + ((0x80000000U + & (((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__cache_miss_resrv__DOT__dequeue_possible) + ? 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1U + : + (((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__cache_miss_resrv__DOT__dequeue_possible) + & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__mrvq_rw_st0)) + ? 1U + : + (((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__reqq_pop_unqual) + & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__reqq_req_rw_st0)) + ? 1U + : 0U))) + << 0x1dU) + | ((((((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__dfpq_pop) + | (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__mrvq_pop)) + | (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__reqq_pop)) + | (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__snrq_pop)) + << 0x1cU) + | ((0xffffffcU + & (((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__dfpq_pop_unqual) + ? + (0x3ffffffU + & vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT____Vcellout__dfp_queue__data_out[4U]) + : + ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__cache_miss_resrv__DOT__dequeue_possible) + ? + ((0x19fU + >= + (0x1ffU + & ((IData)(0x1aU) + * (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr)))) + ? + (0x3ffffffU + & (((0U + == + (0x1fU + & ((IData)(0x1aU) + * (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr)))) + ? 0U + : + (vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__cache_miss_resrv__DOT__addr_table[ + ((IData)(1U) + + + (0xfU + & (((IData)(0x1aU) + * (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr)) + >> 5U)))] + << + ((IData)(0x20U) + - + (0x1fU + & ((IData)(0x1aU) + * (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr)))))) + | (vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__cache_miss_resrv__DOT__addr_table[ + (0xfU + & (((IData)(0x1aU) + * (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr)) + >> 5U))] + >> + (0x1fU + & ((IData)(0x1aU) + * (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr)))))) + : 0U) + : + ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__reqq_pop_unqual) + ? + (0x3ffffffU + & (vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__reqq_req_addr_st0 + >> 4U)) + : + ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__snrq_pop_unqual) + ? + (0x3ffffffU + & (IData)( + (vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT____Vcellout__snp_req_queue__data_out + >> 0x1dU))) + : 0U)))) + << 2U)) + | (3U + & ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__reqq_pop_unqual) + ? + (3U + & vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__reqq_req_addr_st0) + : + ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__cache_miss_resrv__DOT__dequeue_possible) + ? + (3U + & ((vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__cache_miss_resrv__DOT__metadata_table + [vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr][1U] + << 0x1eU) + | (vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__cache_miss_resrv__DOT__metadata_table + [vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr][0U] + >> 2U))) + : 0U)))))))))) + << 0x20U) + | (QData)((IData)( + ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__cache_miss_resrv__DOT__dequeue_possible) + ? + ((vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__cache_miss_resrv__DOT__metadata_table + [vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr][2U] + << 0xbU) + | (vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__cache_miss_resrv__DOT__metadata_table + [vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr][1U] + >> 0x15U)) + : + ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__reqq_pop_unqual) + ? + (((0U + == + (0x1fU + & ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__core_req_arb__DOT__qual_request_index) + << 5U))) + ? 0U + : + (vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__core_req_arb__DOT__use_per_writedata[ + ((IData)(1U) + + + (3U + & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__core_req_arb__DOT__qual_request_index)))] + << + ((IData)(0x20U) + - + (0x1fU + & ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__core_req_arb__DOT__qual_request_index) + << 5U))))) + | (vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__core_req_arb__DOT__use_per_writedata[ + (3U + & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__core_req_arb__DOT__qual_request_index))] + >> + (0x1fU + & ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__core_req_arb__DOT__qual_request_index) + << 5U)))) + : 0U)))))) + >> 0xeU)) | (0xfffc0000U + & ((IData)( + ((((QData)((IData)( + ((0x80000000U + & (((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__cache_miss_resrv__DOT__dequeue_possible) + ? + (1U + & (vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__cache_miss_resrv__DOT__metadata_table + [vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr][0U] + >> 1U)) + : + ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__snrq_pop_unqual) + ? 1U + : 0U)) + << 0x1fU)) + | ((0x40000000U + & (((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__cache_miss_resrv__DOT__dequeue_possible) + ? + (1U + & vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__cache_miss_resrv__DOT__metadata_table + [vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr][0U]) + : + ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__snrq_pop_unqual) + ? + (1U + & (IData)( + (vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT____Vcellout__snp_req_queue__data_out + >> 0x1cU))) + : 0U)) + << 0x1eU)) + | ((((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__dfpq_pop_unqual) + ? 1U + : + (((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__cache_miss_resrv__DOT__dequeue_possible) + & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__mrvq_rw_st0)) + ? 1U + : + (((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__reqq_pop_unqual) + & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__reqq_req_rw_st0)) + ? 1U + : 0U))) + << 0x1dU) + | ((((((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__dfpq_pop) + | (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__mrvq_pop)) + | (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__reqq_pop)) + | (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__snrq_pop)) + << 0x1cU) + | ((0xffffffcU + & (((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__dfpq_pop_unqual) + ? + (0x3ffffffU + & vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT____Vcellout__dfp_queue__data_out[4U]) + : + ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__cache_miss_resrv__DOT__dequeue_possible) + ? + ((0x19fU + >= + (0x1ffU + & ((IData)(0x1aU) + * (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr)))) + ? + (0x3ffffffU + & (((0U + == + (0x1fU + & ((IData)(0x1aU) + * (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr)))) + ? 0U + : + (vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__cache_miss_resrv__DOT__addr_table[ + ((IData)(1U) + + + (0xfU + & (((IData)(0x1aU) + * (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr)) + >> 5U)))] + << + ((IData)(0x20U) + - + (0x1fU + & ((IData)(0x1aU) + * (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr)))))) + | (vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__cache_miss_resrv__DOT__addr_table[ + (0xfU + & (((IData)(0x1aU) + * (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr)) + >> 5U))] + >> + (0x1fU + & ((IData)(0x1aU) + * (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr)))))) + : 0U) + : + ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__reqq_pop_unqual) + ? + (0x3ffffffU + & (vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__reqq_req_addr_st0 + >> 4U)) + : + ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__snrq_pop_unqual) + ? + (0x3ffffffU + & (IData)( + (vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT____Vcellout__snp_req_queue__data_out + >> 0x1dU))) + : 0U)))) + << 2U)) + | (3U + & ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__reqq_pop_unqual) + ? + (3U + & vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__reqq_req_addr_st0) + : + ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__cache_miss_resrv__DOT__dequeue_possible) + ? + (3U + & ((vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__cache_miss_resrv__DOT__metadata_table + [vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr][1U] + << 0x1eU) + | (vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__cache_miss_resrv__DOT__metadata_table + [vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr][0U] + >> 2U))) + : 0U)))))))))) + << 0x20U) + | (QData)((IData)( + ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__cache_miss_resrv__DOT__dequeue_possible) + ? + ((vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__cache_miss_resrv__DOT__metadata_table + [vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr][2U] + << 0xbU) + | (vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__cache_miss_resrv__DOT__metadata_table + [vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr][1U] + >> 0x15U)) + : + ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__reqq_pop_unqual) + ? + (((0U + == + (0x1fU + & ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__core_req_arb__DOT__qual_request_index) + << 5U))) + ? 0U + : + (vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__core_req_arb__DOT__use_per_writedata[ + ((IData)(1U) + + + (3U + & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__core_req_arb__DOT__qual_request_index)))] + << + ((IData)(0x20U) + - + (0x1fU + & ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__core_req_arb__DOT__qual_request_index) + << 5U))))) + | (vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__core_req_arb__DOT__use_per_writedata[ + (3U + & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__core_req_arb__DOT__qual_request_index))] + >> + (0x1fU + & ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__core_req_arb__DOT__qual_request_index) + << 5U)))) + : 0U))))) + >> 0x20U)) + << 0x12U))); + __Vtemp430[7U] = (0x3ffffU & ((IData)(((((QData)((IData)( + ((0x80000000U + & (((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__cache_miss_resrv__DOT__dequeue_possible) + ? + (1U + & (vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__cache_miss_resrv__DOT__metadata_table + [vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr][0U] + >> 1U)) + : + ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__snrq_pop_unqual) + ? 1U + : 0U)) + << 0x1fU)) + | ((0x40000000U + & (((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__cache_miss_resrv__DOT__dequeue_possible) + ? + (1U + & vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__cache_miss_resrv__DOT__metadata_table + [vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr][0U]) + : + ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__snrq_pop_unqual) + ? + (1U + & (IData)( + (vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT____Vcellout__snp_req_queue__data_out + >> 0x1cU))) + : 0U)) + << 0x1eU)) + | ((((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__dfpq_pop_unqual) + ? 1U + : + (((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__cache_miss_resrv__DOT__dequeue_possible) + & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__mrvq_rw_st0)) + ? 1U + : + (((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__reqq_pop_unqual) + & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__reqq_req_rw_st0)) + ? 1U + : 0U))) + << 0x1dU) + | ((((((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__dfpq_pop) + | (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__mrvq_pop)) + | (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__reqq_pop)) + | (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__snrq_pop)) + << 0x1cU) + | ((0xffffffcU + & (((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__dfpq_pop_unqual) + ? + (0x3ffffffU + & vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT____Vcellout__dfp_queue__data_out[4U]) + : + ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__cache_miss_resrv__DOT__dequeue_possible) + ? + ((0x19fU + >= + (0x1ffU + & ((IData)(0x1aU) + * (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr)))) + ? + (0x3ffffffU + & (((0U + == + (0x1fU + & ((IData)(0x1aU) + * (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr)))) + ? 0U + : + (vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__cache_miss_resrv__DOT__addr_table[ + ((IData)(1U) + + + (0xfU + & (((IData)(0x1aU) + * (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr)) + >> 5U)))] + << + ((IData)(0x20U) + - + (0x1fU + & ((IData)(0x1aU) + * (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr)))))) + | (vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__cache_miss_resrv__DOT__addr_table[ + (0xfU + & (((IData)(0x1aU) + * (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr)) + >> 5U))] + >> + (0x1fU + & ((IData)(0x1aU) + * (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr)))))) + : 0U) + : + ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__reqq_pop_unqual) + ? + (0x3ffffffU + & (vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__reqq_req_addr_st0 + >> 4U)) + : + ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__snrq_pop_unqual) + ? + (0x3ffffffU + & (IData)( + (vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT____Vcellout__snp_req_queue__data_out + >> 0x1dU))) + : 0U)))) + << 2U)) + | (3U + & ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__reqq_pop_unqual) + ? + (3U + & vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__reqq_req_addr_st0) + : + ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__cache_miss_resrv__DOT__dequeue_possible) + ? + (3U + & ((vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__cache_miss_resrv__DOT__metadata_table + [vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr][1U] + << 0x1eU) + | (vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__cache_miss_resrv__DOT__metadata_table + [vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr][0U] + >> 2U))) + : 0U)))))))))) + << 0x20U) + | (QData)((IData)( + ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__cache_miss_resrv__DOT__dequeue_possible) + ? + ((vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__cache_miss_resrv__DOT__metadata_table + [vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr][2U] + << 0xbU) + | (vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__cache_miss_resrv__DOT__metadata_table + [vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr][1U] + >> 0x15U)) + : + ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__reqq_pop_unqual) + ? + (((0U + == + (0x1fU + & ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__core_req_arb__DOT__qual_request_index) + << 5U))) + ? 0U + : + (vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__core_req_arb__DOT__use_per_writedata[ + ((IData)(1U) + + + (3U + & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__core_req_arb__DOT__qual_request_index)))] + << + ((IData)(0x20U) + - + (0x1fU + & ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__core_req_arb__DOT__qual_request_index) + << 5U))))) + | (vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__core_req_arb__DOT__use_per_writedata[ + (3U + & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__core_req_arb__DOT__qual_request_index))] + >> + (0x1fU + & ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__core_req_arb__DOT__qual_request_index) + << 5U)))) + : 0U))))) + >> 0x20U)) + >> 0xeU)); + vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT____Vcellinp__s0_1_c0__in[0U] + = ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__dfpq_pop_unqual) + ? vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT____Vcellout__dfp_queue__data_out[0U] + : 0x39U); + vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT____Vcellinp__s0_1_c0__in[1U] + = ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__dfpq_pop_unqual) + ? vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT____Vcellout__dfp_queue__data_out[1U] + : 0U); + vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT____Vcellinp__s0_1_c0__in[2U] + = ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__dfpq_pop_unqual) + ? vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT____Vcellout__dfp_queue__data_out[2U] + : 0U); + vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT____Vcellinp__s0_1_c0__in[3U] + = ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__dfpq_pop_unqual) + ? vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT____Vcellout__dfp_queue__data_out[3U] + : 0U); + vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT____Vcellinp__s0_1_c0__in[4U] + = __Vtemp429[4U]; + vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT____Vcellinp__s0_1_c0__in[5U] + = __Vtemp430[5U]; + vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT____Vcellinp__s0_1_c0__in[6U] + = __Vtemp430[6U]; + vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT____Vcellinp__s0_1_c0__in[7U] + = ((0xfffc0000U & ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__cache_miss_resrv__DOT__dequeue_possible) + << 0x12U)) | __Vtemp430[7U]); + vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__miss_st1e + = (((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__tag_data_access__DOT__real_miss) + | (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__tag_data_access__DOT__snoop_hit_no_pending)) + | (((((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__force_request_miss_st1e) + & (~ vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__is_snp_st1 + [0U])) & (~ vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__is_fill_st1 + [0U])) & vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__valid_st1 + [0U]) & (~ (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__tag_data_access__DOT__real_miss)))); + vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cache_miss_resrv__DOT__increment_head + = ((~ (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__miss_add)) + & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__miss_add_is_mrvq)); + vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cache_miss_resrv__DOT__mrvq_push + = (((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__miss_add) + & (0x10U != (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cache_miss_resrv__DOT__size))) + & (~ (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__miss_add_is_mrvq))); + vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__dfp_queue__DOT__reading + = ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__dfpq_pop) + & (~ (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__dfp_queue__DOT__genblk3__DOT__genblk2__DOT__empty_r))); + vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__snp_req_queue__DOT__reading + = ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__snrq_pop) + & (~ (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__snp_req_queue__DOT__genblk3__DOT__genblk2__DOT__empty_r))); + vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cache_miss_resrv__DOT__mrvq_pop + = ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__mrvq_pop) + & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cache_miss_resrv__DOT__dequeue_possible)); + __Vtemp443[4U] = ((0xfffffffeU & ((IData)(((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cache_miss_resrv__DOT__dequeue_possible) + ? ( + (VL_ULL(0x1ffffffffff80) + & (((QData)((IData)( + vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cache_miss_resrv__DOT__metadata_table + [vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr][2U])) + << 0x3eU) + | (((QData)((IData)( + vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cache_miss_resrv__DOT__metadata_table + [vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr][1U])) + << 0x1eU) + | (VL_ULL(0x3fffffffffffff80) + & ((QData)((IData)( + vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cache_miss_resrv__DOT__metadata_table + [vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr][0U])) + >> 2U))))) + | (QData)((IData)( + (((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__mrvq_rw_st0) + << 6U) + | ((0x3cU + & ((vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cache_miss_resrv__DOT__metadata_table + [vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr][1U] + << 0x1eU) + | (0x3ffffffcU + & (vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cache_miss_resrv__DOT__metadata_table + [vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr][0U] + >> 2U)))) + | (3U + & ((vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cache_miss_resrv__DOT__metadata_table + [vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr][2U] + << 0xdU) + | (vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cache_miss_resrv__DOT__metadata_table + [vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr][1U] + >> 0x13U)))))))) + : ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__reqq_pop_unqual) + ? + ((vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__core_req_arb__DOT__use_per_tag + << 7U) + | (QData)((IData)( + (((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__reqq_req_rw_st0) + << 6U) + | ((0x3cU + & (((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__core_req_arb__DOT__use_per_byteen) + >> + (0xfU + & ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__core_req_arb__DOT__qual_request_index) + << 2U))) + << 2U)) + | (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__core_req_arb__DOT__qual_request_index)))))) + : + ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__snrq_pop_unqual) + ? + ((QData)((IData)( + (0xfffffffU + & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT____Vcellout__snp_req_queue__data_out)))) + << 7U) + : VL_ULL(0))))) + << 1U)) | (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__dfpq_pop_unqual)); + __Vtemp443[5U] = ((1U & ((IData)(((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cache_miss_resrv__DOT__dequeue_possible) + ? ((VL_ULL(0x1ffffffffff80) + & (((QData)((IData)( + vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cache_miss_resrv__DOT__metadata_table + [vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr][2U])) + << 0x3eU) + | (((QData)((IData)( + vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cache_miss_resrv__DOT__metadata_table + [vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr][1U])) + << 0x1eU) + | (VL_ULL(0x3fffffffffffff80) + & ((QData)((IData)( + vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cache_miss_resrv__DOT__metadata_table + [vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr][0U])) + >> 2U))))) + | (QData)((IData)( + (((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__mrvq_rw_st0) + << 6U) + | ((0x3cU + & ((vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cache_miss_resrv__DOT__metadata_table + [vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr][1U] + << 0x1eU) + | (0x3ffffffcU + & (vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cache_miss_resrv__DOT__metadata_table + [vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr][0U] + >> 2U)))) + | (3U + & ((vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cache_miss_resrv__DOT__metadata_table + [vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr][2U] + << 0xdU) + | (vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cache_miss_resrv__DOT__metadata_table + [vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr][1U] + >> 0x13U)))))))) + : ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__reqq_pop_unqual) + ? ((vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__core_req_arb__DOT__use_per_tag + << 7U) + | (QData)((IData)( + (((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__reqq_req_rw_st0) + << 6U) + | ((0x3cU + & (((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__core_req_arb__DOT__use_per_byteen) + >> + (0xfU + & ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__core_req_arb__DOT__qual_request_index) + << 2U))) + << 2U)) + | (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__core_req_arb__DOT__qual_request_index)))))) + : ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__snrq_pop_unqual) + ? ((QData)((IData)( + (0xfffffffU + & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT____Vcellout__snp_req_queue__data_out)))) + << 7U) + : VL_ULL(0))))) + >> 0x1fU)) | (0xfffffffeU + & ((IData)( + (((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cache_miss_resrv__DOT__dequeue_possible) + ? + ((VL_ULL(0x1ffffffffff80) + & (((QData)((IData)( + vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cache_miss_resrv__DOT__metadata_table + [vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr][2U])) + << 0x3eU) + | (((QData)((IData)( + vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cache_miss_resrv__DOT__metadata_table + [vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr][1U])) + << 0x1eU) + | (VL_ULL(0x3fffffffffffff80) + & ((QData)((IData)( + vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cache_miss_resrv__DOT__metadata_table + [vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr][0U])) + >> 2U))))) + | (QData)((IData)( + (((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__mrvq_rw_st0) + << 6U) + | ((0x3cU + & ((vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cache_miss_resrv__DOT__metadata_table + [vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr][1U] + << 0x1eU) + | (0x3ffffffcU + & (vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cache_miss_resrv__DOT__metadata_table + [vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr][0U] + >> 2U)))) + | (3U + & ((vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cache_miss_resrv__DOT__metadata_table + [vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr][2U] + << 0xdU) + | (vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cache_miss_resrv__DOT__metadata_table + [vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr][1U] + >> 0x13U)))))))) + : + ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__reqq_pop_unqual) + ? + ((vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__core_req_arb__DOT__use_per_tag + << 7U) + | (QData)((IData)( + (((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__reqq_req_rw_st0) + << 6U) + | ((0x3cU + & (((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__core_req_arb__DOT__use_per_byteen) + >> + (0xfU + & ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__core_req_arb__DOT__qual_request_index) + << 2U))) + << 2U)) + | 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(((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cache_miss_resrv__DOT__dequeue_possible) + ? + (1U + & vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cache_miss_resrv__DOT__metadata_table + [vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr][0U]) + : + ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__snrq_pop_unqual) + ? + (1U + & (IData)( + (vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT____Vcellout__snp_req_queue__data_out + >> 0x1cU))) + : 0U)) + << 0x1eU)) + | ((((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__dfpq_pop_unqual) + ? 1U + : + (((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cache_miss_resrv__DOT__dequeue_possible) + & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__mrvq_rw_st0)) + ? 1U + : + (((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__reqq_pop_unqual) + & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__reqq_req_rw_st0)) + ? 1U + : 0U))) + << 0x1dU) + | ((((((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__dfpq_pop) + | (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__mrvq_pop)) + | (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__reqq_pop)) + | (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__snrq_pop)) + << 0x1cU) + | ((0xffffffcU + & (((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__dfpq_pop_unqual) + ? + (0x3ffffffU + & vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT____Vcellout__dfp_queue__data_out[4U]) + : + ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cache_miss_resrv__DOT__dequeue_possible) + ? + ((0x19fU + >= + (0x1ffU + & ((IData)(0x1aU) + * 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((vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cache_miss_resrv__DOT__metadata_table + [vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr][1U] + << 0x1eU) + | (vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cache_miss_resrv__DOT__metadata_table + [vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr][0U] + >> 2U))) + : 0U)))))))))) + << 0x20U) + | (QData)((IData)( + ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cache_miss_resrv__DOT__dequeue_possible) + ? + ((vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cache_miss_resrv__DOT__metadata_table + [vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr][2U] + << 0xbU) + | (vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cache_miss_resrv__DOT__metadata_table + [vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr][1U] + >> 0x15U)) + : + ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__reqq_pop_unqual) + ? + (((0U + == + (0x1fU + & ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__core_req_arb__DOT__qual_request_index) + << 5U))) + ? 0U + : + (vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__core_req_arb__DOT__use_per_writedata[ + ((IData)(1U) + + + (3U + & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__core_req_arb__DOT__qual_request_index)))] + << + ((IData)(0x20U) + - + (0x1fU + & ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__core_req_arb__DOT__qual_request_index) + << 5U))))) + | (vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__core_req_arb__DOT__use_per_writedata[ + (3U + & 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vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cache_miss_resrv__DOT__metadata_table + [vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr][0U]) + : + ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__snrq_pop_unqual) + ? + (1U + & (IData)( + (vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT____Vcellout__snp_req_queue__data_out + >> 0x1cU))) + : 0U)) + << 0x1eU)) + | ((((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__dfpq_pop_unqual) + ? 1U + : + (((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cache_miss_resrv__DOT__dequeue_possible) + & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__mrvq_rw_st0)) + ? 1U + : + (((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__reqq_pop_unqual) + & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__reqq_req_rw_st0)) + ? 1U + : 0U))) + << 0x1dU) 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((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__reqq_pop_unqual) + ? + (0x3ffffffU + & (vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__reqq_req_addr_st0 + >> 4U)) + : + ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__snrq_pop_unqual) + ? + (0x3ffffffU + & (IData)( + (vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT____Vcellout__snp_req_queue__data_out + >> 0x1dU))) + : 0U)))) + << 2U)) + | (3U + & ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__reqq_pop_unqual) + ? + (3U + & vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__reqq_req_addr_st0) + : + ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cache_miss_resrv__DOT__dequeue_possible) + ? + (3U + & ((vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cache_miss_resrv__DOT__metadata_table + [vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr][1U] + << 0x1eU) + | (vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cache_miss_resrv__DOT__metadata_table + [vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr][0U] + >> 2U))) + : 0U)))))))))) + << 0x20U) + | (QData)((IData)( + ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cache_miss_resrv__DOT__dequeue_possible) + ? + ((vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cache_miss_resrv__DOT__metadata_table + [vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr][2U] + << 0xbU) + | (vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cache_miss_resrv__DOT__metadata_table + [vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr][1U] + >> 0x15U)) + : + ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__reqq_pop_unqual) + ? + (((0U + == + (0x1fU + & ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__core_req_arb__DOT__qual_request_index) + << 5U))) + ? 0U + : + (vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__core_req_arb__DOT__use_per_writedata[ + ((IData)(1U) + + + (3U + & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__core_req_arb__DOT__qual_request_index)))] + << + ((IData)(0x20U) + - + (0x1fU + & ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__core_req_arb__DOT__qual_request_index) + << 5U))))) + | (vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__core_req_arb__DOT__use_per_writedata[ + (3U + & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__core_req_arb__DOT__qual_request_index))] + >> + (0x1fU + & ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__core_req_arb__DOT__qual_request_index) + << 5U)))) + : 0U)))))) + >> 0xeU)) | (0xfffc0000U + & ((IData)( + ((((QData)((IData)( + ((0x80000000U + & (((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cache_miss_resrv__DOT__dequeue_possible) + ? + (1U + & (vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cache_miss_resrv__DOT__metadata_table + [vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr][0U] + >> 1U)) + : + ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__snrq_pop_unqual) + ? 1U + : 0U)) + << 0x1fU)) + | ((0x40000000U + & (((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cache_miss_resrv__DOT__dequeue_possible) + ? + (1U + & vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cache_miss_resrv__DOT__metadata_table + [vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr][0U]) + : + ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__snrq_pop_unqual) + ? + (1U + & (IData)( + (vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT____Vcellout__snp_req_queue__data_out + >> 0x1cU))) + : 0U)) + << 0x1eU)) + | ((((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__dfpq_pop_unqual) + ? 1U + : + (((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cache_miss_resrv__DOT__dequeue_possible) + & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__mrvq_rw_st0)) + ? 1U + : + (((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__reqq_pop_unqual) + & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__reqq_req_rw_st0)) + ? 1U + : 0U))) + << 0x1dU) + | ((((((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__dfpq_pop) + | (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__mrvq_pop)) + | (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__reqq_pop)) + | (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__snrq_pop)) + << 0x1cU) + | ((0xffffffcU + & (((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__dfpq_pop_unqual) + ? + (0x3ffffffU + & vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT____Vcellout__dfp_queue__data_out[4U]) + : + ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cache_miss_resrv__DOT__dequeue_possible) + ? + ((0x19fU + >= + (0x1ffU + & ((IData)(0x1aU) + * (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr)))) + ? + (0x3ffffffU + & (((0U + == + (0x1fU + & ((IData)(0x1aU) + * (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr)))) + ? 0U + : + (vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cache_miss_resrv__DOT__addr_table[ + ((IData)(1U) + + + (0xfU + & (((IData)(0x1aU) + * (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr)) + >> 5U)))] + << + ((IData)(0x20U) + - + (0x1fU + & ((IData)(0x1aU) + * (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr)))))) + | (vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cache_miss_resrv__DOT__addr_table[ + (0xfU + & (((IData)(0x1aU) + * (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr)) + >> 5U))] + >> + (0x1fU + & ((IData)(0x1aU) + * (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr)))))) + : 0U) + : + ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__reqq_pop_unqual) + ? + (0x3ffffffU + & (vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__reqq_req_addr_st0 + >> 4U)) + : + ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__snrq_pop_unqual) + ? + (0x3ffffffU + & (IData)( + (vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT____Vcellout__snp_req_queue__data_out + >> 0x1dU))) + : 0U)))) + << 2U)) + | (3U + & ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__reqq_pop_unqual) + ? + (3U + & vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__reqq_req_addr_st0) + : + ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cache_miss_resrv__DOT__dequeue_possible) + ? + (3U + & ((vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cache_miss_resrv__DOT__metadata_table + [vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr][1U] + << 0x1eU) + | (vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cache_miss_resrv__DOT__metadata_table + [vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr][0U] + >> 2U))) + : 0U)))))))))) + << 0x20U) + | (QData)((IData)( + ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cache_miss_resrv__DOT__dequeue_possible) + ? + ((vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cache_miss_resrv__DOT__metadata_table + [vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr][2U] + << 0xbU) + | (vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cache_miss_resrv__DOT__metadata_table + [vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr][1U] + >> 0x15U)) + : + ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__reqq_pop_unqual) + ? + (((0U + == + (0x1fU + & ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__core_req_arb__DOT__qual_request_index) + << 5U))) + ? 0U + : + (vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__core_req_arb__DOT__use_per_writedata[ + ((IData)(1U) + + + (3U + & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__core_req_arb__DOT__qual_request_index)))] + << + ((IData)(0x20U) + - + (0x1fU + & ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__core_req_arb__DOT__qual_request_index) + << 5U))))) + | (vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__core_req_arb__DOT__use_per_writedata[ + (3U + & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__core_req_arb__DOT__qual_request_index))] + >> + (0x1fU + & ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__core_req_arb__DOT__qual_request_index) + << 5U)))) + : 0U))))) + >> 0x20U)) + << 0x12U))); + __Vtemp444[7U] = (0x3ffffU & ((IData)(((((QData)((IData)( + ((0x80000000U + & (((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cache_miss_resrv__DOT__dequeue_possible) + ? + (1U + & (vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cache_miss_resrv__DOT__metadata_table + [vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr][0U] + >> 1U)) + : + ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__snrq_pop_unqual) + ? 1U + : 0U)) + << 0x1fU)) + | ((0x40000000U + & (((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cache_miss_resrv__DOT__dequeue_possible) + ? + (1U + & vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cache_miss_resrv__DOT__metadata_table + [vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr][0U]) + : + ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__snrq_pop_unqual) + ? + (1U + & (IData)( + (vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT____Vcellout__snp_req_queue__data_out + >> 0x1cU))) + : 0U)) + << 0x1eU)) + | ((((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__dfpq_pop_unqual) + ? 1U + : + (((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cache_miss_resrv__DOT__dequeue_possible) + & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__mrvq_rw_st0)) + ? 1U + : + (((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__reqq_pop_unqual) + & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__reqq_req_rw_st0)) + ? 1U + : 0U))) + << 0x1dU) + | ((((((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__dfpq_pop) + | (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__mrvq_pop)) + | (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__reqq_pop)) + | (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__snrq_pop)) + << 0x1cU) + | ((0xffffffcU + & (((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__dfpq_pop_unqual) + ? + (0x3ffffffU + & vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT____Vcellout__dfp_queue__data_out[4U]) + : + ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cache_miss_resrv__DOT__dequeue_possible) + ? + ((0x19fU + >= + (0x1ffU + & ((IData)(0x1aU) + * (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr)))) + ? + (0x3ffffffU + & (((0U + == + (0x1fU + & ((IData)(0x1aU) + * (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr)))) + ? 0U + : + (vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cache_miss_resrv__DOT__addr_table[ + ((IData)(1U) + + + (0xfU + & (((IData)(0x1aU) + * (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr)) + >> 5U)))] + << + ((IData)(0x20U) + - + (0x1fU + & ((IData)(0x1aU) + * (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr)))))) + | (vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cache_miss_resrv__DOT__addr_table[ + (0xfU + & (((IData)(0x1aU) + * (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr)) + >> 5U))] + >> + (0x1fU + & ((IData)(0x1aU) + * (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr)))))) + : 0U) + : + ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__reqq_pop_unqual) + ? + (0x3ffffffU + & (vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__reqq_req_addr_st0 + >> 4U)) + : + ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__snrq_pop_unqual) + ? + (0x3ffffffU + & (IData)( + (vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT____Vcellout__snp_req_queue__data_out + >> 0x1dU))) + : 0U)))) + << 2U)) + | (3U + & ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__reqq_pop_unqual) + ? + (3U + & vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__reqq_req_addr_st0) + : + ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cache_miss_resrv__DOT__dequeue_possible) + ? + (3U + & ((vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cache_miss_resrv__DOT__metadata_table + [vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr][1U] + << 0x1eU) + | (vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cache_miss_resrv__DOT__metadata_table + [vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr][0U] + >> 2U))) + : 0U)))))))))) + << 0x20U) + | (QData)((IData)( + ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cache_miss_resrv__DOT__dequeue_possible) + ? + ((vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cache_miss_resrv__DOT__metadata_table + [vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr][2U] + << 0xbU) + | (vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cache_miss_resrv__DOT__metadata_table + [vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr][1U] + >> 0x15U)) + : + ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__reqq_pop_unqual) + ? + (((0U + == + (0x1fU + & ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__core_req_arb__DOT__qual_request_index) + << 5U))) + ? 0U + : + (vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__core_req_arb__DOT__use_per_writedata[ + ((IData)(1U) + + + (3U + & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__core_req_arb__DOT__qual_request_index)))] + << + ((IData)(0x20U) + - + (0x1fU + & ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__core_req_arb__DOT__qual_request_index) + << 5U))))) + | (vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__core_req_arb__DOT__use_per_writedata[ + (3U + & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__core_req_arb__DOT__qual_request_index))] + >> + (0x1fU + & ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__core_req_arb__DOT__qual_request_index) + << 5U)))) + : 0U))))) + >> 0x20U)) + >> 0xeU)); + vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT____Vcellinp__s0_1_c0__in[0U] + = ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__dfpq_pop_unqual) + ? vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT____Vcellout__dfp_queue__data_out[0U] + : 0x39U); + vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT____Vcellinp__s0_1_c0__in[1U] + = ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__dfpq_pop_unqual) + ? vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT____Vcellout__dfp_queue__data_out[1U] + : 0U); + vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT____Vcellinp__s0_1_c0__in[2U] + = ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__dfpq_pop_unqual) + ? vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT____Vcellout__dfp_queue__data_out[2U] + : 0U); + vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT____Vcellinp__s0_1_c0__in[3U] + = ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__dfpq_pop_unqual) + ? vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT____Vcellout__dfp_queue__data_out[3U] + : 0U); + vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT____Vcellinp__s0_1_c0__in[4U] + = __Vtemp443[4U]; + vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT____Vcellinp__s0_1_c0__in[5U] + = __Vtemp444[5U]; + vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT____Vcellinp__s0_1_c0__in[6U] + = __Vtemp444[6U]; + vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT____Vcellinp__s0_1_c0__in[7U] + = ((0xfffc0000U & ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cache_miss_resrv__DOT__dequeue_possible) + << 0x12U)) | __Vtemp444[7U]); + vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__miss_st1e + = (((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__tag_data_access__DOT__real_miss) + | (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__tag_data_access__DOT__snoop_hit_no_pending)) + | (((((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__force_request_miss_st1e) + & (~ vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__is_snp_st1 + [0U])) & (~ vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__is_fill_st1 + [0U])) & vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__valid_st1 + [0U]) & (~ (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__tag_data_access__DOT__real_miss)))); + __Vtemp446[0U] = vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__tag_data_access__DOT__read_data_st1c + [0U][0U]; + __Vtemp446[1U] = vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__tag_data_access__DOT__read_data_st1c + [0U][1U]; + __Vtemp446[2U] = vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__tag_data_access__DOT__read_data_st1c + [0U][2U]; + __Vtemp446[3U] = vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__tag_data_access__DOT__read_data_st1c + [0U][3U]; + __Vtemp453[6U] = ((0x7fffffU & (vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__tag_data_access__DOT__read_data_st1c + [0U][3U] >> 9U)) + | (0xff800000U & ((IData)((((QData)((IData)( + vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__writeword_st1 + [0U])) + << 0x20U) + | (QData)((IData)( + (((0U + == + (0x1fU + & (vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__wsel_st1 + [0U] + << 5U))) + ? 0U + : + (__Vtemp446[ + ((IData)(1U) + + + (3U + & vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__wsel_st1 + [0U]))] + << + ((IData)(0x20U) + - + (0x1fU + & (vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__wsel_st1 + [0U] + << 5U))))) + | (__Vtemp446[ + (3U + & vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__wsel_st1 + [0U])] + >> + (0x1fU + & (vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__wsel_st1 + [0U] + << 5U)))))))) + << 0x17U))); + __Vtemp453[7U] = ((0x7fffffU & ((IData)((((QData)((IData)( + vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__writeword_st1 + [0U])) + << 0x20U) + | (QData)((IData)( + (((0U + == + (0x1fU + & (vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__wsel_st1 + [0U] + << 5U))) + ? 0U + : + (__Vtemp446[ + ((IData)(1U) + + + (3U + & vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__wsel_st1 + [0U]))] + << + ((IData)(0x20U) + - + (0x1fU + & (vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__wsel_st1 + [0U] + << 5U))))) + | (__Vtemp446[ + (3U + & vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__wsel_st1 + [0U])] + >> + (0x1fU + & (vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__wsel_st1 + [0U] + << 5U)))))))) + >> 9U)) | (0xff800000U + & ((IData)( + ((((QData)((IData)( + vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__writeword_st1 + [0U])) + << 0x20U) + | (QData)((IData)( + (((0U + == + (0x1fU + & (vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__wsel_st1 + [0U] + << 5U))) + ? 0U + : + (__Vtemp446[ + ((IData)(1U) + + + (3U + & vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__wsel_st1 + [0U]))] + << + ((IData)(0x20U) + - + (0x1fU + & (vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__wsel_st1 + [0U] + << 5U))))) + | (__Vtemp446[ + (3U + & vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__wsel_st1 + [0U])] + >> + (0x1fU + & (vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__wsel_st1 + [0U] + << 5U))))))) + >> 0x20U)) + << 0x17U))); + __Vtemp454[8U] = ((0xff800000U & (vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__wsel_st1 + [0U] << 0x17U)) + | (0x7fffffU & ((IData)(((((QData)((IData)( + vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__writeword_st1 + [0U])) + << 0x20U) + | (QData)((IData)( + (((0U + == + (0x1fU + & (vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__wsel_st1 + [0U] + << 5U))) + ? 0U + : + (__Vtemp446[ + ((IData)(1U) + + + (3U + & vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__wsel_st1 + [0U]))] + << + ((IData)(0x20U) + - + (0x1fU + & (vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__wsel_st1 + [0U] + << 5U))))) + | (__Vtemp446[ + (3U + & vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__wsel_st1 + [0U])] + >> + (0x1fU + & (vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__wsel_st1 + [0U] + << 5U))))))) + >> 0x20U)) + >> 9U))); + __Vtemp456[9U] = ((0xfe000000U & (((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__snp_to_mrvq_st1e) + | ((((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__force_request_miss_st1e) + & (~ vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__is_snp_st1 + [0U])) + & (~ vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__is_fill_st1 + [0U])) + & vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__valid_st1 + [0U])) << 0x19U)) + | (0x1ffffffU & ((0x1000000U + & ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__snp_to_mrvq_st1e) + << 0x18U)) + | ((0x1800000U + & (vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__is_snp_st1 + [0U] + << 0x17U)) + | ((0x1c00000U + & (vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__snp_invalidate_st1 + [0U] + << 0x16U)) + | ((0x1e00000U + & (((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__tag_data_access__DOT__real_writefill) + & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__dirty_st1e)) + << 0x15U)) + | ((0x1f00000U + & (vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__is_fill_st1 + [0U] + << 0x14U)) + | ((0x1f80000U + & ((vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__valid_st1 + [0U] + & (~ + vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__is_fill_st1 + [0U])) + << 0x13U)) + | (vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__addr_st1 + [0U] + >> 7U))))))))); + vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT____Vcellinp__st_1e_2__in[0U] + = (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__inst_meta_st1 + [0U]); + vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT____Vcellinp__st_1e_2__in[1U] + = ((0xfffe0000U & (vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__tag_data_access__DOT__read_dirtyb_st1c + [0U] << 0x11U)) | (IData)( + (vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__inst_meta_st1 + [0U] + >> 0x20U))); + vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT____Vcellinp__st_1e_2__in[2U] + = ((0xff800000U & (vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__tag_data_access__DOT__read_data_st1c + [0U][0U] << 0x17U)) | ((0xfffffff8U + & (vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__tag_data_access__DOT__read_tag_st1c + [0U] + << 3U)) + | ((0xfffffffcU + & ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__miss_st1e) + << 2U)) + | ((0xfffffffeU + & ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__dirty_st1e) + << 1U)) + | (0x1ffffU + & (vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__tag_data_access__DOT__read_dirtyb_st1c + [0U] + >> 0xfU)))))); + vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT____Vcellinp__st_1e_2__in[3U] + = ((0x7fffffU & (vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__tag_data_access__DOT__read_data_st1c + [0U][0U] >> 9U)) | (0xff800000U + & (vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__tag_data_access__DOT__read_data_st1c + [0U][1U] + << 0x17U))); + vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT____Vcellinp__st_1e_2__in[4U] + = ((0x7fffffU & (vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__tag_data_access__DOT__read_data_st1c + [0U][1U] >> 9U)) | (0xff800000U + & (vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__tag_data_access__DOT__read_data_st1c + [0U][2U] + << 0x17U))); + vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT____Vcellinp__st_1e_2__in[5U] + = ((0x7fffffU & (vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__tag_data_access__DOT__read_data_st1c + [0U][2U] >> 9U)) | (0xff800000U + & (vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__tag_data_access__DOT__read_data_st1c + [0U][3U] + << 0x17U))); + vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT____Vcellinp__st_1e_2__in[6U] + = __Vtemp453[6U]; + vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT____Vcellinp__st_1e_2__in[7U] + = __Vtemp453[7U]; + vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT____Vcellinp__st_1e_2__in[8U] + = ((0xfe000000U & (vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__addr_st1 + [0U] << 0x19U)) | __Vtemp454[8U]); + vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT____Vcellinp__st_1e_2__in[9U] + = ((0xf8000000U & ((((vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__valid_st1 + [0U] & vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__is_mrvq_st1 + [0U]) & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__recover_mrvq_state_st2)) + & ((0x3ffffffU & ((vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__st_1e_2__DOT__value[9U] + << 7U) + | (vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__st_1e_2__DOT__value[8U] + >> 0x19U))) + == vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__addr_st1 + [0U])) << 0x1bU)) | + ((0xfc000000U & (vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__is_mrvq_st1 + [0U] << 0x1aU)) | __Vtemp456[9U])); + vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__tag_data_access__DOT__should_write + = ((((((IData)((vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__inst_meta_st1 + [0U] >> 6U)) & vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__valid_st1 + [0U]) & vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__tag_data_access__DOT__read_valid_st1c + [0U]) & (~ (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__miss_st1e))) + & (~ vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__is_snp_st1 + [0U])) & (~ (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__tag_data_access__DOT__real_writefill))); + __Vtemp459[0U] = vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__tag_data_access__DOT__read_data_st1c + [0U][0U]; + __Vtemp459[1U] = vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__tag_data_access__DOT__read_data_st1c + [0U][1U]; + __Vtemp459[2U] = vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__tag_data_access__DOT__read_data_st1c + [0U][2U]; + __Vtemp459[3U] = vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__tag_data_access__DOT__read_data_st1c + [0U][3U]; + __Vtemp466[6U] = ((0x7fffffU & (vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__tag_data_access__DOT__read_data_st1c + [0U][3U] >> 9U)) + | (0xff800000U & ((IData)((((QData)((IData)( + vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__writeword_st1 + [0U])) + << 0x20U) + | (QData)((IData)( + (((0U + == + (0x1fU + & (vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__wsel_st1 + [0U] + << 5U))) + ? 0U + : + (__Vtemp459[ + ((IData)(1U) + + + (3U + & vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__wsel_st1 + [0U]))] + << + ((IData)(0x20U) + - + (0x1fU + & (vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__wsel_st1 + [0U] + << 5U))))) + | (__Vtemp459[ + (3U + & vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__wsel_st1 + [0U])] + >> + (0x1fU + & (vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__wsel_st1 + [0U] + << 5U)))))))) + << 0x17U))); + __Vtemp466[7U] = ((0x7fffffU & ((IData)((((QData)((IData)( + vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__writeword_st1 + [0U])) + << 0x20U) + | (QData)((IData)( + (((0U + == + (0x1fU + & (vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__wsel_st1 + [0U] + << 5U))) + ? 0U + : + (__Vtemp459[ + ((IData)(1U) + + + (3U + & vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__wsel_st1 + [0U]))] + << + ((IData)(0x20U) + - + (0x1fU + & (vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__wsel_st1 + [0U] + << 5U))))) + | (__Vtemp459[ + (3U + & vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__wsel_st1 + [0U])] + >> + (0x1fU + & (vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__wsel_st1 + [0U] + << 5U)))))))) + >> 9U)) | (0xff800000U + & ((IData)( + ((((QData)((IData)( + vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__writeword_st1 + [0U])) + << 0x20U) + | (QData)((IData)( + (((0U + == + (0x1fU + & (vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__wsel_st1 + [0U] + << 5U))) + ? 0U + : + (__Vtemp459[ + ((IData)(1U) + + + (3U + & vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__wsel_st1 + [0U]))] + << + ((IData)(0x20U) + - + (0x1fU + & (vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__wsel_st1 + [0U] + << 5U))))) + | (__Vtemp459[ + (3U + & vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__wsel_st1 + [0U])] + >> + (0x1fU + & (vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__wsel_st1 + [0U] + << 5U))))))) + >> 0x20U)) + << 0x17U))); + __Vtemp467[8U] = ((0xff800000U & (vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__wsel_st1 + [0U] << 0x17U)) + | (0x7fffffU & ((IData)(((((QData)((IData)( + vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__writeword_st1 + [0U])) + << 0x20U) + | (QData)((IData)( + (((0U + == + (0x1fU + & (vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__wsel_st1 + [0U] + << 5U))) + ? 0U + : + (__Vtemp459[ + ((IData)(1U) + + + (3U + & vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__wsel_st1 + [0U]))] + << + ((IData)(0x20U) + - + (0x1fU + & (vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__wsel_st1 + [0U] + << 5U))))) + | (__Vtemp459[ + (3U + & vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__wsel_st1 + [0U])] + >> + (0x1fU + & (vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__wsel_st1 + [0U] + << 5U))))))) + >> 0x20U)) + >> 9U))); + __Vtemp469[9U] = ((0xfe000000U & (((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__snp_to_mrvq_st1e) + | ((((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__force_request_miss_st1e) + & (~ vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__is_snp_st1 + [0U])) + & (~ vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__is_fill_st1 + [0U])) + & vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__valid_st1 + [0U])) << 0x19U)) + | (0x1ffffffU & ((0x1000000U + & ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__snp_to_mrvq_st1e) + << 0x18U)) + | ((0x1800000U + & (vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__is_snp_st1 + [0U] + << 0x17U)) + | ((0x1c00000U + & (vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__snp_invalidate_st1 + [0U] + << 0x16U)) + | ((0x1e00000U + & (((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__tag_data_access__DOT__real_writefill) + & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__dirty_st1e)) + << 0x15U)) + | ((0x1f00000U + & (vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__is_fill_st1 + [0U] + << 0x14U)) + | ((0x1f80000U + & ((vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__valid_st1 + [0U] + & (~ + vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__is_fill_st1 + [0U])) + << 0x13U)) + | (vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__addr_st1 + [0U] + >> 7U))))))))); + vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT____Vcellinp__st_1e_2__in[0U] + = (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__inst_meta_st1 + [0U]); + vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT____Vcellinp__st_1e_2__in[1U] + = ((0xfffe0000U & (vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__tag_data_access__DOT__read_dirtyb_st1c + [0U] << 0x11U)) | (IData)( + (vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__inst_meta_st1 + [0U] + >> 0x20U))); + vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT____Vcellinp__st_1e_2__in[2U] + = ((0xff800000U & (vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__tag_data_access__DOT__read_data_st1c + [0U][0U] << 0x17U)) | ((0xfffffff8U + & (vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__tag_data_access__DOT__read_tag_st1c + [0U] + << 3U)) + | ((0xfffffffcU + & ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__miss_st1e) + << 2U)) + | ((0xfffffffeU + & ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__dirty_st1e) + << 1U)) + | (0x1ffffU + & (vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__tag_data_access__DOT__read_dirtyb_st1c + [0U] + >> 0xfU)))))); + vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT____Vcellinp__st_1e_2__in[3U] + = ((0x7fffffU & (vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__tag_data_access__DOT__read_data_st1c + [0U][0U] >> 9U)) | (0xff800000U + & (vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__tag_data_access__DOT__read_data_st1c + [0U][1U] + << 0x17U))); + vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT____Vcellinp__st_1e_2__in[4U] + = ((0x7fffffU & (vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__tag_data_access__DOT__read_data_st1c + [0U][1U] >> 9U)) | (0xff800000U + & (vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__tag_data_access__DOT__read_data_st1c + [0U][2U] + << 0x17U))); + vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT____Vcellinp__st_1e_2__in[5U] + = ((0x7fffffU & (vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__tag_data_access__DOT__read_data_st1c + [0U][2U] >> 9U)) | (0xff800000U + & (vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__tag_data_access__DOT__read_data_st1c + [0U][3U] + << 0x17U))); + vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT____Vcellinp__st_1e_2__in[6U] + = __Vtemp466[6U]; + vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT____Vcellinp__st_1e_2__in[7U] + = __Vtemp466[7U]; + vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT____Vcellinp__st_1e_2__in[8U] + = ((0xfe000000U & (vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__addr_st1 + [0U] << 0x19U)) | __Vtemp467[8U]); + vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT____Vcellinp__st_1e_2__in[9U] + = ((0xf8000000U & ((((vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__valid_st1 + [0U] & vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__is_mrvq_st1 + [0U]) & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__recover_mrvq_state_st2)) + & ((0x3ffffffU & ((vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__st_1e_2__DOT__value[9U] + << 7U) + | (vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__st_1e_2__DOT__value[8U] + >> 0x19U))) + == vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__addr_st1 + [0U])) << 0x1bU)) | + ((0xfc000000U & (vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__is_mrvq_st1 + [0U] << 0x1aU)) | __Vtemp469[9U])); + vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__tag_data_access__DOT__should_write + = ((((((IData)((vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__inst_meta_st1 + [0U] >> 6U)) & vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__valid_st1 + [0U]) & vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__tag_data_access__DOT__read_valid_st1c + [0U]) & (~ (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__miss_st1e))) + & (~ vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__is_snp_st1 + [0U])) & (~ (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__tag_data_access__DOT__real_writefill))); + __Vtemp472[0U] = vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__tag_data_access__DOT__read_data_st1c + [0U][0U]; + __Vtemp472[1U] = vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__tag_data_access__DOT__read_data_st1c + [0U][1U]; + __Vtemp472[2U] = vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__tag_data_access__DOT__read_data_st1c + [0U][2U]; + __Vtemp472[3U] = vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__tag_data_access__DOT__read_data_st1c + [0U][3U]; + __Vtemp479[6U] = ((0x7fffffU & (vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__tag_data_access__DOT__read_data_st1c + [0U][3U] >> 9U)) + | (0xff800000U & ((IData)((((QData)((IData)( + vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__writeword_st1 + [0U])) + << 0x20U) + | (QData)((IData)( + (((0U + == + (0x1fU + & (vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__wsel_st1 + [0U] + << 5U))) + ? 0U + : + (__Vtemp472[ + ((IData)(1U) + + + (3U + & vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__wsel_st1 + [0U]))] + << + ((IData)(0x20U) + - + (0x1fU + & (vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__wsel_st1 + [0U] + << 5U))))) + | (__Vtemp472[ + (3U + & vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__wsel_st1 + [0U])] + >> + (0x1fU + & (vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__wsel_st1 + [0U] + << 5U)))))))) + << 0x17U))); + __Vtemp479[7U] = ((0x7fffffU & ((IData)((((QData)((IData)( + vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__writeword_st1 + [0U])) + << 0x20U) + | (QData)((IData)( + (((0U + == + (0x1fU + & (vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__wsel_st1 + [0U] + << 5U))) + ? 0U + : + (__Vtemp472[ + ((IData)(1U) + + + (3U + & vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__wsel_st1 + [0U]))] + << + ((IData)(0x20U) + - + (0x1fU + & (vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__wsel_st1 + [0U] + << 5U))))) + | (__Vtemp472[ + (3U + & vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__wsel_st1 + [0U])] + >> + (0x1fU + & (vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__wsel_st1 + [0U] + << 5U)))))))) + >> 9U)) | (0xff800000U + & ((IData)( + ((((QData)((IData)( + vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__writeword_st1 + [0U])) + << 0x20U) + | (QData)((IData)( + (((0U + == + (0x1fU + & (vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__wsel_st1 + [0U] + << 5U))) + ? 0U + : + (__Vtemp472[ + ((IData)(1U) + + + (3U + & vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__wsel_st1 + [0U]))] + << + ((IData)(0x20U) + - + (0x1fU + & (vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__wsel_st1 + [0U] + << 5U))))) + | (__Vtemp472[ + (3U + & vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__wsel_st1 + [0U])] + >> + (0x1fU + & (vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__wsel_st1 + [0U] + << 5U))))))) + >> 0x20U)) + << 0x17U))); + __Vtemp480[8U] = ((0xff800000U & (vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__wsel_st1 + [0U] << 0x17U)) + | (0x7fffffU & ((IData)(((((QData)((IData)( + vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__writeword_st1 + [0U])) + << 0x20U) + | (QData)((IData)( + (((0U + == + (0x1fU + & (vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__wsel_st1 + [0U] + << 5U))) + ? 0U + : + (__Vtemp472[ + ((IData)(1U) + + + (3U + & vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__wsel_st1 + [0U]))] + << + ((IData)(0x20U) + - + (0x1fU + & (vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__wsel_st1 + [0U] + << 5U))))) + | (__Vtemp472[ + (3U + & vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__wsel_st1 + [0U])] + >> + (0x1fU + & (vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__wsel_st1 + [0U] + << 5U))))))) + >> 0x20U)) + >> 9U))); + __Vtemp482[9U] = ((0xfe000000U & (((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__snp_to_mrvq_st1e) + | ((((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__force_request_miss_st1e) + & (~ vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__is_snp_st1 + [0U])) + & (~ vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__is_fill_st1 + [0U])) + & vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__valid_st1 + [0U])) << 0x19U)) + | (0x1ffffffU & ((0x1000000U + & ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__snp_to_mrvq_st1e) + << 0x18U)) + | ((0x1800000U + & (vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__is_snp_st1 + [0U] + << 0x17U)) + | ((0x1c00000U + & (vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__snp_invalidate_st1 + [0U] + << 0x16U)) + | ((0x1e00000U + & (((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__tag_data_access__DOT__real_writefill) + & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__dirty_st1e)) + << 0x15U)) + | ((0x1f00000U + & (vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__is_fill_st1 + [0U] + << 0x14U)) + | ((0x1f80000U + & ((vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__valid_st1 + [0U] + & (~ + vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__is_fill_st1 + [0U])) + << 0x13U)) + | (vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__addr_st1 + [0U] + >> 7U))))))))); + vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT____Vcellinp__st_1e_2__in[0U] + = (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__inst_meta_st1 + [0U]); + vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT____Vcellinp__st_1e_2__in[1U] + = ((0xfffe0000U & (vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__tag_data_access__DOT__read_dirtyb_st1c + [0U] << 0x11U)) | (IData)( + (vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__inst_meta_st1 + [0U] + >> 0x20U))); + vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT____Vcellinp__st_1e_2__in[2U] + = ((0xff800000U & (vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__tag_data_access__DOT__read_data_st1c + [0U][0U] << 0x17U)) | ((0xfffffff8U + & (vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__tag_data_access__DOT__read_tag_st1c + [0U] + << 3U)) + | ((0xfffffffcU + & ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__miss_st1e) + << 2U)) + | ((0xfffffffeU + & ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__dirty_st1e) + << 1U)) + | (0x1ffffU + & (vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__tag_data_access__DOT__read_dirtyb_st1c + [0U] + >> 0xfU)))))); + vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT____Vcellinp__st_1e_2__in[3U] + = ((0x7fffffU & (vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__tag_data_access__DOT__read_data_st1c + [0U][0U] >> 9U)) | (0xff800000U + & (vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__tag_data_access__DOT__read_data_st1c + [0U][1U] + << 0x17U))); + vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT____Vcellinp__st_1e_2__in[4U] + = ((0x7fffffU & (vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__tag_data_access__DOT__read_data_st1c + [0U][1U] >> 9U)) | (0xff800000U + & (vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__tag_data_access__DOT__read_data_st1c + [0U][2U] + << 0x17U))); + vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT____Vcellinp__st_1e_2__in[5U] + = ((0x7fffffU & (vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__tag_data_access__DOT__read_data_st1c + [0U][2U] >> 9U)) | (0xff800000U + & (vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__tag_data_access__DOT__read_data_st1c + [0U][3U] + << 0x17U))); + vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT____Vcellinp__st_1e_2__in[6U] + = __Vtemp479[6U]; + vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT____Vcellinp__st_1e_2__in[7U] + = __Vtemp479[7U]; + vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT____Vcellinp__st_1e_2__in[8U] + = ((0xfe000000U & (vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__addr_st1 + [0U] << 0x19U)) | __Vtemp480[8U]); + vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT____Vcellinp__st_1e_2__in[9U] + = ((0xf8000000U & ((((vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__valid_st1 + [0U] & vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__is_mrvq_st1 + [0U]) & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__recover_mrvq_state_st2)) + & ((0x3ffffffU & ((vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__st_1e_2__DOT__value[9U] + << 7U) + | (vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__st_1e_2__DOT__value[8U] + >> 0x19U))) + == vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__addr_st1 + [0U])) << 0x1bU)) | + ((0xfc000000U & (vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__is_mrvq_st1 + [0U] << 0x1aU)) | __Vtemp482[9U])); + vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__tag_data_access__DOT__should_write + = ((((((IData)((vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__inst_meta_st1 + [0U] >> 6U)) & vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__valid_st1 + [0U]) & vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__tag_data_access__DOT__read_valid_st1c + [0U]) & (~ (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__miss_st1e))) + & (~ vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__is_snp_st1 + [0U])) & (~ (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__tag_data_access__DOT__real_writefill))); + __Vtemp485[0U] = vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__tag_data_access__DOT__read_data_st1c + [0U][0U]; + __Vtemp485[1U] = vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__tag_data_access__DOT__read_data_st1c + [0U][1U]; + __Vtemp485[2U] = vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__tag_data_access__DOT__read_data_st1c + [0U][2U]; + __Vtemp485[3U] = vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__tag_data_access__DOT__read_data_st1c + [0U][3U]; + __Vtemp492[6U] = ((0x7fffffU & (vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__tag_data_access__DOT__read_data_st1c + [0U][3U] >> 9U)) + | (0xff800000U & ((IData)((((QData)((IData)( + vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__writeword_st1 + [0U])) + << 0x20U) + | (QData)((IData)( + (((0U + == + (0x1fU + & (vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__wsel_st1 + [0U] + << 5U))) + ? 0U + : + (__Vtemp485[ + ((IData)(1U) + + + (3U + & vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__wsel_st1 + [0U]))] + << + ((IData)(0x20U) + - + (0x1fU + & (vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__wsel_st1 + [0U] + << 5U))))) + | (__Vtemp485[ + (3U + & vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__wsel_st1 + [0U])] + >> + (0x1fU + & (vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__wsel_st1 + [0U] + << 5U)))))))) + << 0x17U))); + __Vtemp492[7U] = ((0x7fffffU & ((IData)((((QData)((IData)( + vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__writeword_st1 + [0U])) + << 0x20U) + | (QData)((IData)( + (((0U + == + (0x1fU + & (vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__wsel_st1 + [0U] + << 5U))) + ? 0U + : + (__Vtemp485[ + ((IData)(1U) + + + (3U + & vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__wsel_st1 + [0U]))] + << + ((IData)(0x20U) + - + (0x1fU + & (vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__wsel_st1 + [0U] + << 5U))))) + | (__Vtemp485[ + (3U + & vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__wsel_st1 + [0U])] + >> + (0x1fU + & (vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__wsel_st1 + [0U] + << 5U)))))))) + >> 9U)) | (0xff800000U + & ((IData)( + ((((QData)((IData)( + vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__writeword_st1 + [0U])) + << 0x20U) + | (QData)((IData)( + (((0U + == + (0x1fU + & (vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__wsel_st1 + [0U] + << 5U))) + ? 0U + : + (__Vtemp485[ + ((IData)(1U) + + + (3U + & vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__wsel_st1 + [0U]))] + << + ((IData)(0x20U) + - + (0x1fU + & (vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__wsel_st1 + [0U] + << 5U))))) + | (__Vtemp485[ + (3U + & vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__wsel_st1 + [0U])] + >> + (0x1fU + & (vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__wsel_st1 + [0U] + << 5U))))))) + >> 0x20U)) + << 0x17U))); + __Vtemp493[8U] = ((0xff800000U & (vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__wsel_st1 + [0U] << 0x17U)) + | (0x7fffffU & ((IData)(((((QData)((IData)( + vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__writeword_st1 + [0U])) + << 0x20U) + | (QData)((IData)( + (((0U + == + (0x1fU + & (vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__wsel_st1 + [0U] + << 5U))) + ? 0U + : + (__Vtemp485[ + ((IData)(1U) + + + (3U + & vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__wsel_st1 + [0U]))] + << + ((IData)(0x20U) + - + (0x1fU + & (vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__wsel_st1 + [0U] + << 5U))))) + | (__Vtemp485[ + (3U + & vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__wsel_st1 + [0U])] + >> + (0x1fU + & (vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__wsel_st1 + [0U] + << 5U))))))) + >> 0x20U)) + >> 9U))); + __Vtemp495[9U] = ((0xfe000000U & (((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__snp_to_mrvq_st1e) + | ((((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__force_request_miss_st1e) + & (~ vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__is_snp_st1 + [0U])) + & (~ vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__is_fill_st1 + [0U])) + & vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__valid_st1 + [0U])) << 0x19U)) + | (0x1ffffffU & ((0x1000000U + & ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__snp_to_mrvq_st1e) + << 0x18U)) + | ((0x1800000U + & (vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__is_snp_st1 + [0U] + << 0x17U)) + | ((0x1c00000U + & (vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__snp_invalidate_st1 + [0U] + << 0x16U)) + | ((0x1e00000U + & (((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__tag_data_access__DOT__real_writefill) + & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__dirty_st1e)) + << 0x15U)) + | ((0x1f00000U + & (vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__is_fill_st1 + [0U] + << 0x14U)) + | ((0x1f80000U + & ((vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__valid_st1 + [0U] + & (~ + vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__is_fill_st1 + [0U])) + << 0x13U)) + | (vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__addr_st1 + [0U] + >> 7U))))))))); + vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT____Vcellinp__st_1e_2__in[0U] + = (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__inst_meta_st1 + [0U]); + vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT____Vcellinp__st_1e_2__in[1U] + = ((0xfffe0000U & (vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__tag_data_access__DOT__read_dirtyb_st1c + [0U] << 0x11U)) | (IData)( + (vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__inst_meta_st1 + [0U] + >> 0x20U))); + vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT____Vcellinp__st_1e_2__in[2U] + = ((0xff800000U & (vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__tag_data_access__DOT__read_data_st1c + [0U][0U] << 0x17U)) | ((0xfffffff8U + & (vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__tag_data_access__DOT__read_tag_st1c + [0U] + << 3U)) + | ((0xfffffffcU + & ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__miss_st1e) + << 2U)) + | ((0xfffffffeU + & ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__dirty_st1e) + << 1U)) + | (0x1ffffU + & (vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__tag_data_access__DOT__read_dirtyb_st1c + [0U] + >> 0xfU)))))); + vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT____Vcellinp__st_1e_2__in[3U] + = ((0x7fffffU & (vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__tag_data_access__DOT__read_data_st1c + [0U][0U] >> 9U)) | (0xff800000U + & (vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__tag_data_access__DOT__read_data_st1c + [0U][1U] + << 0x17U))); + vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT____Vcellinp__st_1e_2__in[4U] + = ((0x7fffffU & (vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__tag_data_access__DOT__read_data_st1c + [0U][1U] >> 9U)) | (0xff800000U + & (vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__tag_data_access__DOT__read_data_st1c + [0U][2U] + << 0x17U))); + vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT____Vcellinp__st_1e_2__in[5U] + = ((0x7fffffU & (vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__tag_data_access__DOT__read_data_st1c + [0U][2U] >> 9U)) | (0xff800000U + & (vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__tag_data_access__DOT__read_data_st1c + [0U][3U] + << 0x17U))); + vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT____Vcellinp__st_1e_2__in[6U] + = __Vtemp492[6U]; + vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT____Vcellinp__st_1e_2__in[7U] + = __Vtemp492[7U]; + vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT____Vcellinp__st_1e_2__in[8U] + = ((0xfe000000U & (vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__addr_st1 + [0U] << 0x19U)) | __Vtemp493[8U]); + vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT____Vcellinp__st_1e_2__in[9U] + = ((0xf8000000U & ((((vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__valid_st1 + [0U] & vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__is_mrvq_st1 + [0U]) & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__recover_mrvq_state_st2)) + & ((0x3ffffffU & ((vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__st_1e_2__DOT__value[9U] + << 7U) + | (vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__st_1e_2__DOT__value[8U] + >> 0x19U))) + == vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__addr_st1 + [0U])) << 0x1bU)) | + ((0xfc000000U & (vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__is_mrvq_st1 + [0U] << 0x1aU)) | __Vtemp495[9U])); + vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__tag_data_access__DOT__should_write + = ((((((IData)((vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__inst_meta_st1 + [0U] >> 6U)) & vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__valid_st1 + [0U]) & vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__tag_data_access__DOT__read_valid_st1c + [0U]) & (~ (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__miss_st1e))) + & (~ vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__is_snp_st1 + [0U])) & (~ (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__tag_data_access__DOT__real_writefill))); + vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__tag_data_access__DOT__we + = ((0xfff0U & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__tag_data_access__DOT__we)) + | ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__tag_data_access__DOT__real_writefill) + ? 0xfU : (((0U == vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__wsel_st1 + [0U]) & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__tag_data_access__DOT__should_write)) + ? (0xfU & (IData)((vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__inst_meta_st1 + [0U] >> 2U))) + : 0U))); + vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__tag_data_access__DOT__we + = ((0xff0fU & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__tag_data_access__DOT__we)) + | (((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__tag_data_access__DOT__real_writefill) + ? 0xfU : (((1U == vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__wsel_st1 + [0U]) & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__tag_data_access__DOT__should_write)) + ? (0xfU & (IData)((vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__inst_meta_st1 + [0U] + >> 2U))) + : 0U)) << 4U)); + vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__tag_data_access__DOT__we + = ((0xf0ffU & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__tag_data_access__DOT__we)) + | (((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__tag_data_access__DOT__real_writefill) + ? 0xfU : (((2U == vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__wsel_st1 + [0U]) & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__tag_data_access__DOT__should_write)) + ? (0xfU & (IData)((vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__inst_meta_st1 + [0U] + >> 2U))) + : 0U)) << 8U)); + vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__tag_data_access__DOT__we + = ((0xfffU & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__tag_data_access__DOT__we)) + | (((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__tag_data_access__DOT__real_writefill) + ? 0xfU : (((3U == vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__wsel_st1 + [0U]) & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__tag_data_access__DOT__should_write)) + ? (0xfU & (IData)((vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__inst_meta_st1 + [0U] + >> 2U))) + : 0U)) << 0xcU)); + vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__tag_data_access__DOT__we + = ((0xfff0U & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__tag_data_access__DOT__we)) + | ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__tag_data_access__DOT__real_writefill) + ? 0xfU : (((0U == vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__wsel_st1 + [0U]) & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__tag_data_access__DOT__should_write)) + ? (0xfU & (IData)((vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__inst_meta_st1 + [0U] >> 2U))) + : 0U))); + vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__tag_data_access__DOT__we + = ((0xff0fU & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__tag_data_access__DOT__we)) + | (((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__tag_data_access__DOT__real_writefill) + ? 0xfU : (((1U == vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__wsel_st1 + [0U]) & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__tag_data_access__DOT__should_write)) + ? (0xfU & (IData)((vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__inst_meta_st1 + [0U] + >> 2U))) + : 0U)) << 4U)); + vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__tag_data_access__DOT__we + = ((0xf0ffU & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__tag_data_access__DOT__we)) + | (((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__tag_data_access__DOT__real_writefill) + ? 0xfU : (((2U == vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__wsel_st1 + [0U]) & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__tag_data_access__DOT__should_write)) + ? (0xfU & (IData)((vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__inst_meta_st1 + [0U] + >> 2U))) + : 0U)) << 8U)); + vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__tag_data_access__DOT__we + = ((0xfffU & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__tag_data_access__DOT__we)) + | (((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__tag_data_access__DOT__real_writefill) + ? 0xfU : (((3U == vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__wsel_st1 + [0U]) & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__tag_data_access__DOT__should_write)) + ? (0xfU & (IData)((vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__inst_meta_st1 + [0U] + >> 2U))) + : 0U)) << 0xcU)); + vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__tag_data_access__DOT__we + = ((0xfff0U & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__tag_data_access__DOT__we)) + | ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__tag_data_access__DOT__real_writefill) + ? 0xfU : (((0U == vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__wsel_st1 + [0U]) & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__tag_data_access__DOT__should_write)) + ? (0xfU & (IData)((vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__inst_meta_st1 + [0U] >> 2U))) + : 0U))); + vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__tag_data_access__DOT__we + = ((0xff0fU & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__tag_data_access__DOT__we)) + | (((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__tag_data_access__DOT__real_writefill) + ? 0xfU : (((1U == vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__wsel_st1 + [0U]) & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__tag_data_access__DOT__should_write)) + ? (0xfU & (IData)((vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__inst_meta_st1 + [0U] + >> 2U))) + : 0U)) << 4U)); + vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__tag_data_access__DOT__we + = ((0xf0ffU & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__tag_data_access__DOT__we)) + | (((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__tag_data_access__DOT__real_writefill) + ? 0xfU : (((2U == vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__wsel_st1 + [0U]) & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__tag_data_access__DOT__should_write)) + ? (0xfU & (IData)((vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__inst_meta_st1 + [0U] + >> 2U))) + : 0U)) << 8U)); + vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__tag_data_access__DOT__we + = ((0xfffU & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__tag_data_access__DOT__we)) + | (((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__tag_data_access__DOT__real_writefill) + ? 0xfU : (((3U == vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__wsel_st1 + [0U]) & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__tag_data_access__DOT__should_write)) + ? (0xfU & (IData)((vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__inst_meta_st1 + [0U] + >> 2U))) + : 0U)) << 0xcU)); + vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__tag_data_access__DOT__we + = ((0xfff0U & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__tag_data_access__DOT__we)) + | ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__tag_data_access__DOT__real_writefill) + ? 0xfU : (((0U == vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__wsel_st1 + [0U]) & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__tag_data_access__DOT__should_write)) + ? (0xfU & (IData)((vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__inst_meta_st1 + [0U] >> 2U))) + : 0U))); + vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__tag_data_access__DOT__we + = ((0xff0fU & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__tag_data_access__DOT__we)) + | (((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__tag_data_access__DOT__real_writefill) + ? 0xfU : (((1U == vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__wsel_st1 + [0U]) & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__tag_data_access__DOT__should_write)) + ? (0xfU & (IData)((vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__inst_meta_st1 + [0U] + >> 2U))) + : 0U)) << 4U)); + vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__tag_data_access__DOT__we + = ((0xf0ffU & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__tag_data_access__DOT__we)) + | (((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__tag_data_access__DOT__real_writefill) + ? 0xfU : (((2U == vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__wsel_st1 + [0U]) & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__tag_data_access__DOT__should_write)) + ? (0xfU & (IData)((vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__inst_meta_st1 + [0U] + >> 2U))) + : 0U)) << 8U)); + vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__tag_data_access__DOT__we + = ((0xfffU & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__tag_data_access__DOT__we)) + | (((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__tag_data_access__DOT__real_writefill) + ? 0xfU : (((3U == vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__wsel_st1 + [0U]) & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__tag_data_access__DOT__should_write)) + ? (0xfU & (IData)((vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__inst_meta_st1 + [0U] + >> 2U))) + : 0U)) << 0xcU)); + vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__tag_data_access__DOT__use_write_enable + = ((vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__is_fill_st1 + [0U] & (~ (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__tag_data_access__DOT__real_writefill))) + ? 0U : (0xffffU & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__tag_data_access__DOT__we))); + vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__tag_data_access__DOT__use_write_enable + = ((vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__is_fill_st1 + [0U] & (~ (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__tag_data_access__DOT__real_writefill))) + ? 0U : (0xffffU & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__tag_data_access__DOT__we))); + vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__tag_data_access__DOT__use_write_enable + = ((vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__is_fill_st1 + [0U] & (~ (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__tag_data_access__DOT__real_writefill))) + ? 0U : (0xffffU & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__tag_data_access__DOT__we))); + vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__tag_data_access__DOT__use_write_enable + = ((vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__is_fill_st1 + [0U] & (~ (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__tag_data_access__DOT__real_writefill))) + ? 0U : (0xffffU & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__tag_data_access__DOT__we))); +} + +VL_INLINE_OPT void VVX_cache::_combo__TOP__5(VVX_cache__Syms* __restrict vlSymsp) { + VL_DEBUG_IF(VL_DBG_MSGF("+ VVX_cache::_combo__TOP__5\n"); ); + VVX_cache* __restrict vlTOPp VL_ATTR_UNUSED = vlSymsp->TOPp; + // Body + vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT____Vcellinp__snp_req_queue__data_in + = (((QData)((IData)((0x3ffffffU & (vlTOPp->snp_req_addr + >> 2U)))) + << 0x1dU) | (QData)((IData)((((IData)(vlTOPp->snp_req_invalidate) + << 0x1cU) + | vlTOPp->snp_req_tag)))); + vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT____Vcellinp__snp_req_queue__data_in + = (((QData)((IData)((0x3ffffffU & (vlTOPp->snp_req_addr + >> 2U)))) + << 0x1dU) | (QData)((IData)((((IData)(vlTOPp->snp_req_invalidate) + << 0x1cU) + | vlTOPp->snp_req_tag)))); + vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT____Vcellinp__snp_req_queue__data_in + = (((QData)((IData)((0x3ffffffU & (vlTOPp->snp_req_addr + >> 2U)))) + << 0x1dU) | (QData)((IData)((((IData)(vlTOPp->snp_req_invalidate) + << 0x1cU) + | vlTOPp->snp_req_tag)))); + vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT____Vcellinp__snp_req_queue__data_in + = (((QData)((IData)((0x3ffffffU & (vlTOPp->snp_req_addr + >> 2U)))) + << 0x1dU) | (QData)((IData)((((IData)(vlTOPp->snp_req_invalidate) + << 0x1cU) + | vlTOPp->snp_req_tag)))); + vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT____Vcellinp__dfp_queue__data_in[0U] + = vlTOPp->dram_rsp_data[0U]; + vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT____Vcellinp__dfp_queue__data_in[1U] + = vlTOPp->dram_rsp_data[1U]; + vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT____Vcellinp__dfp_queue__data_in[2U] + = vlTOPp->dram_rsp_data[2U]; + vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT____Vcellinp__dfp_queue__data_in[3U] + = vlTOPp->dram_rsp_data[3U]; + vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT____Vcellinp__dfp_queue__data_in[4U] + = (0x3ffffffU & (vlTOPp->dram_rsp_tag >> 2U)); + vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT____Vcellinp__dfp_queue__data_in[0U] + = vlTOPp->dram_rsp_data[0U]; + vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT____Vcellinp__dfp_queue__data_in[1U] + = vlTOPp->dram_rsp_data[1U]; + vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT____Vcellinp__dfp_queue__data_in[2U] + = vlTOPp->dram_rsp_data[2U]; + vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT____Vcellinp__dfp_queue__data_in[3U] + = vlTOPp->dram_rsp_data[3U]; + vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT____Vcellinp__dfp_queue__data_in[4U] + = (0x3ffffffU & (vlTOPp->dram_rsp_tag >> 2U)); + vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT____Vcellinp__dfp_queue__data_in[0U] + = vlTOPp->dram_rsp_data[0U]; + vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT____Vcellinp__dfp_queue__data_in[1U] + = vlTOPp->dram_rsp_data[1U]; + vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT____Vcellinp__dfp_queue__data_in[2U] + = vlTOPp->dram_rsp_data[2U]; + vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT____Vcellinp__dfp_queue__data_in[3U] + = vlTOPp->dram_rsp_data[3U]; + vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT____Vcellinp__dfp_queue__data_in[4U] + = (0x3ffffffU & (vlTOPp->dram_rsp_tag >> 2U)); + vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT____Vcellinp__dfp_queue__data_in[0U] + = vlTOPp->dram_rsp_data[0U]; + vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT____Vcellinp__dfp_queue__data_in[1U] + = vlTOPp->dram_rsp_data[1U]; + vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT____Vcellinp__dfp_queue__data_in[2U] + = vlTOPp->dram_rsp_data[2U]; + vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT____Vcellinp__dfp_queue__data_in[3U] + = vlTOPp->dram_rsp_data[3U]; + vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT____Vcellinp__dfp_queue__data_in[4U] + = (0x3ffffffU & (vlTOPp->dram_rsp_tag >> 2U)); + vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__snp_req_queue__DOT__writing + = (((IData)(vlTOPp->snp_req_valid) & (3U == + (3U & vlTOPp->snp_req_addr))) + & (~ (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__snp_req_queue__DOT__genblk3__DOT__genblk2__DOT__full_r))); + vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__snp_req_queue__DOT__writing + = (((IData)(vlTOPp->snp_req_valid) & (2U == + (3U & vlTOPp->snp_req_addr))) + & (~ (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__snp_req_queue__DOT__genblk3__DOT__genblk2__DOT__full_r))); + vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__snp_req_queue__DOT__writing + = (((IData)(vlTOPp->snp_req_valid) & (1U == + (3U & vlTOPp->snp_req_addr))) + & (~ (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__snp_req_queue__DOT__genblk3__DOT__genblk2__DOT__full_r))); + vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__snp_req_queue__DOT__writing + = (((IData)(vlTOPp->snp_req_valid) & (0U == + (3U & vlTOPp->snp_req_addr))) + & (~ (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__snp_req_queue__DOT__genblk3__DOT__genblk2__DOT__full_r))); + vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__dfp_queue__DOT__writing + = (((IData)(vlTOPp->dram_rsp_valid) & (3U == + (3U + & vlTOPp->dram_rsp_tag))) + & (~ (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__dfp_queue__DOT__genblk3__DOT__genblk2__DOT__full_r))); + vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__dfp_queue__DOT__writing + = (((IData)(vlTOPp->dram_rsp_valid) & (2U == + (3U + & vlTOPp->dram_rsp_tag))) + & (~ (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__dfp_queue__DOT__genblk3__DOT__genblk2__DOT__full_r))); + vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__dfp_queue__DOT__writing + = (((IData)(vlTOPp->dram_rsp_valid) & (1U == + (3U + & vlTOPp->dram_rsp_tag))) + & (~ (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__dfp_queue__DOT__genblk3__DOT__genblk2__DOT__full_r))); + vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__dfp_queue__DOT__writing + = (((IData)(vlTOPp->dram_rsp_valid) & (0U == + (3U + & vlTOPp->dram_rsp_tag))) + & (~ (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__dfp_queue__DOT__genblk3__DOT__genblk2__DOT__full_r))); + vlTOPp->snp_req_ready = (1U & ((IData)(vlTOPp->VX_cache__DOT__per_bank_snp_req_ready) + >> (3U & vlTOPp->snp_req_addr))); + vlTOPp->core_req_ready = (0xfU == ((IData)(vlTOPp->VX_cache__DOT__per_bank_core_req_ready) + | (IData)(vlTOPp->VX_cache__DOT__cache_core_req_bank_sel__DOT__genblk2__DOT__per_bank_ready_sel))); + vlTOPp->VX_cache__DOT__per_bank_core_rsp_ready + = ((IData)(vlTOPp->VX_cache__DOT__cache_core_rsp_merge__DOT__per_bank_core_rsp_pop_unqual) + & VL_NEGATE_I((IData)((IData)(vlTOPp->core_rsp_ready)))); + vlTOPp->VX_cache__DOT__per_bank_snp_rsp_ready = + ((0xeU & (IData)(vlTOPp->VX_cache__DOT__per_bank_snp_rsp_ready)) + | ((IData)(vlTOPp->snp_rsp_ready) & (0U == (IData)(vlTOPp->VX_cache__DOT__snp_rsp_arb__DOT__fsq_bank)))); + vlTOPp->VX_cache__DOT__per_bank_snp_rsp_ready = + ((0xdU & (IData)(vlTOPp->VX_cache__DOT__per_bank_snp_rsp_ready)) + | (((IData)(vlTOPp->snp_rsp_ready) & (1U == (IData)(vlTOPp->VX_cache__DOT__snp_rsp_arb__DOT__fsq_bank))) + << 1U)); + vlTOPp->VX_cache__DOT__per_bank_snp_rsp_ready = + ((0xbU & (IData)(vlTOPp->VX_cache__DOT__per_bank_snp_rsp_ready)) + | (((IData)(vlTOPp->snp_rsp_ready) & (2U == (IData)(vlTOPp->VX_cache__DOT__snp_rsp_arb__DOT__fsq_bank))) + << 2U)); + vlTOPp->VX_cache__DOT__per_bank_snp_rsp_ready = + ((7U & (IData)(vlTOPp->VX_cache__DOT__per_bank_snp_rsp_ready)) + | (((IData)(vlTOPp->snp_rsp_ready) & (3U == (IData)(vlTOPp->VX_cache__DOT__snp_rsp_arb__DOT__fsq_bank))) + << 3U)); + vlTOPp->VX_cache__DOT__cache_dram_req_arb__DOT__dfqq_pop + = (((~ (IData)(vlTOPp->VX_cache__DOT__cache_dram_req_arb__DOT__dwb_valid)) + & (IData)(vlTOPp->VX_cache__DOT__cache_dram_req_arb__DOT__dfqq_req)) + & (IData)(vlTOPp->dram_req_ready)); + vlTOPp->VX_cache__DOT__per_bank_dram_wb_req_ready + = ((0xeU & (IData)(vlTOPp->VX_cache__DOT__per_bank_dram_wb_req_ready)) + | ((IData)(vlTOPp->dram_req_ready) & (0U + == (IData)(vlTOPp->VX_cache__DOT__cache_dram_req_arb__DOT__dwb_bank)))); + vlTOPp->VX_cache__DOT__per_bank_dram_wb_req_ready + = ((0xdU & (IData)(vlTOPp->VX_cache__DOT__per_bank_dram_wb_req_ready)) + | (((IData)(vlTOPp->dram_req_ready) & (1U + == (IData)(vlTOPp->VX_cache__DOT__cache_dram_req_arb__DOT__dwb_bank))) + << 1U)); + vlTOPp->VX_cache__DOT__per_bank_dram_wb_req_ready + = ((0xbU & (IData)(vlTOPp->VX_cache__DOT__per_bank_dram_wb_req_ready)) + | (((IData)(vlTOPp->dram_req_ready) & (2U + == (IData)(vlTOPp->VX_cache__DOT__cache_dram_req_arb__DOT__dwb_bank))) + << 2U)); + vlTOPp->VX_cache__DOT__per_bank_dram_wb_req_ready + = ((7U & (IData)(vlTOPp->VX_cache__DOT__per_bank_dram_wb_req_ready)) + | (((IData)(vlTOPp->dram_req_ready) & (3U + == (IData)(vlTOPp->VX_cache__DOT__cache_dram_req_arb__DOT__dwb_bank))) + << 3U)); + vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__curr_bank_core_req_valid + = (0xfU & ((IData)(vlTOPp->VX_cache__DOT____Vcellout__cache_core_req_bank_sel__per_bank_valid) + & VL_NEGATE_I((IData)((IData)(vlTOPp->core_req_ready))))); + vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__curr_bank_core_req_valid + = (0xfU & (((IData)(vlTOPp->VX_cache__DOT____Vcellout__cache_core_req_bank_sel__per_bank_valid) + >> 4U) & VL_NEGATE_I((IData)((IData)(vlTOPp->core_req_ready))))); + vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__curr_bank_core_req_valid + = (0xfU & (((IData)(vlTOPp->VX_cache__DOT____Vcellout__cache_core_req_bank_sel__per_bank_valid) + >> 8U) & VL_NEGATE_I((IData)((IData)(vlTOPp->core_req_ready))))); + vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__curr_bank_core_req_valid + = (0xfU & (((IData)(vlTOPp->VX_cache__DOT____Vcellout__cache_core_req_bank_sel__per_bank_valid) + >> 0xcU) & VL_NEGATE_I((IData)((IData)(vlTOPp->core_req_ready))))); + vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cwb_queue__DOT__reading + = (1U & (((~ (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cwb_queue__DOT__genblk3__DOT__genblk2__DOT__empty_r)) + & (IData)(vlTOPp->VX_cache__DOT__per_bank_core_rsp_ready)) + & (~ (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cwb_queue__DOT__genblk3__DOT__genblk2__DOT__empty_r)))); + vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__cwb_queue__DOT__reading + = (1U & (((~ (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__cwb_queue__DOT__genblk3__DOT__genblk2__DOT__empty_r)) + & ((IData)(vlTOPp->VX_cache__DOT__per_bank_core_rsp_ready) + >> 1U)) & (~ (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__cwb_queue__DOT__genblk3__DOT__genblk2__DOT__empty_r)))); + vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__cwb_queue__DOT__reading + = (1U & (((~ (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__cwb_queue__DOT__genblk3__DOT__genblk2__DOT__empty_r)) + & ((IData)(vlTOPp->VX_cache__DOT__per_bank_core_rsp_ready) + >> 2U)) & (~ (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__cwb_queue__DOT__genblk3__DOT__genblk2__DOT__empty_r)))); + vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cwb_queue__DOT__reading + = (1U & (((~ (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cwb_queue__DOT__genblk3__DOT__genblk2__DOT__empty_r)) + & ((IData)(vlTOPp->VX_cache__DOT__per_bank_core_rsp_ready) + >> 3U)) & (~ (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cwb_queue__DOT__genblk3__DOT__genblk2__DOT__empty_r)))); + vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__snp_rsp_fire + = ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__curr_bank_snp_rsp_valid) + & (IData)(vlTOPp->VX_cache__DOT__per_bank_snp_rsp_ready)); + vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__snp_rsp_fire + = ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__curr_bank_snp_rsp_valid) + & ((IData)(vlTOPp->VX_cache__DOT__per_bank_snp_rsp_ready) + >> 1U)); + vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__snp_rsp_fire + = ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__curr_bank_snp_rsp_valid) + & ((IData)(vlTOPp->VX_cache__DOT__per_bank_snp_rsp_ready) + >> 2U)); + vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__snp_rsp_fire + = ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__curr_bank_snp_rsp_valid) + & ((IData)(vlTOPp->VX_cache__DOT__per_bank_snp_rsp_ready) + >> 3U)); + vlTOPp->VX_cache__DOT__cache_dram_req_arb__DOT__dram_fill_arb__DOT__dfqq_queue__DOT__reading + = ((((IData)(vlTOPp->VX_cache__DOT__cache_dram_req_arb__DOT__dfqq_pop) + & (~ (IData)((0U != (IData)(vlTOPp->VX_cache__DOT__cache_dram_req_arb__DOT__dram_fill_arb__DOT__use_per_bank_dram_fill_req_valid))))) + & (~ ((~ (IData)((0U != (0xfU & (vlTOPp->VX_cache__DOT__cache_dram_req_arb__DOT__dram_fill_arb__DOT____Vcellout__dfqq_queue__data_out[3U] + >> 0x10U))))) + | (IData)(vlTOPp->VX_cache__DOT__cache_dram_req_arb__DOT__dram_fill_arb__DOT__dfqq_queue__DOT__genblk3__DOT__genblk2__DOT__empty_r)))) + & (~ (IData)(vlTOPp->VX_cache__DOT__cache_dram_req_arb__DOT__dram_fill_arb__DOT__dfqq_queue__DOT__genblk3__DOT__genblk2__DOT__empty_r))); + vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__dram_wb_req_fire + = ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__curr_bank_dram_wb_req_valid) + & (IData)(vlTOPp->VX_cache__DOT__per_bank_dram_wb_req_ready)); + vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__dram_wb_req_fire + = ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__curr_bank_dram_wb_req_valid) + & ((IData)(vlTOPp->VX_cache__DOT__per_bank_dram_wb_req_ready) + >> 1U)); + vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__dram_wb_req_fire + = ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__curr_bank_dram_wb_req_valid) + & ((IData)(vlTOPp->VX_cache__DOT__per_bank_dram_wb_req_ready) + >> 2U)); + vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__dram_wb_req_fire + = ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__curr_bank_dram_wb_req_valid) + & ((IData)(vlTOPp->VX_cache__DOT__per_bank_dram_wb_req_ready) + >> 3U)); + vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__writing + = ((((0U != (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__curr_bank_core_req_valid)) + & (~ (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__full_r))) + & (~ (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__full_r))) + & (~ (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__full_r))); + vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__core_req_arb__DOT____Vcellinp__reqq_queue__data_in[0U] + = (IData)(vlTOPp->core_req_tag); + vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__core_req_arb__DOT____Vcellinp__reqq_queue__data_in[1U] + = ((0xfffffc00U & (vlTOPp->core_req_data[0U] + << 0xaU)) | (IData)((vlTOPp->core_req_tag + >> 0x20U))); + vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__core_req_arb__DOT____Vcellinp__reqq_queue__data_in[2U] + = ((0x3ffU & (vlTOPp->core_req_data[0U] >> 0x16U)) + | (0xfffffc00U & (vlTOPp->core_req_data[1U] + << 0xaU))); + vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__core_req_arb__DOT____Vcellinp__reqq_queue__data_in[3U] + = ((0x3ffU & (vlTOPp->core_req_data[1U] >> 0x16U)) + | (0xfffffc00U & (vlTOPp->core_req_data[2U] + << 0xaU))); + vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__core_req_arb__DOT____Vcellinp__reqq_queue__data_in[4U] + = ((0x3ffU & (vlTOPp->core_req_data[2U] >> 0x16U)) + | (0xfffffc00U & (vlTOPp->core_req_data[3U] + << 0xaU))); + vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__core_req_arb__DOT____Vcellinp__reqq_queue__data_in[5U] + = ((0xfffffc00U & (vlTOPp->core_req_addr[0U] + << 0xaU)) | (0x3ffU & (vlTOPp->core_req_data[3U] + >> 0x16U))); + vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__core_req_arb__DOT____Vcellinp__reqq_queue__data_in[6U] + = ((0x3ffU & (vlTOPp->core_req_addr[0U] >> 0x16U)) + | (0xfffffc00U & (vlTOPp->core_req_addr[1U] + << 0xaU))); + vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__core_req_arb__DOT____Vcellinp__reqq_queue__data_in[7U] + = ((0x3ffU & (vlTOPp->core_req_addr[1U] >> 0x16U)) + | (0xfffffc00U & (vlTOPp->core_req_addr[2U] + << 0xaU))); + vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__core_req_arb__DOT____Vcellinp__reqq_queue__data_in[8U] + = ((0x3ffU & (vlTOPp->core_req_addr[2U] >> 0x16U)) + | (0xfffffc00U & (vlTOPp->core_req_addr[3U] + << 0xaU))); + vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__core_req_arb__DOT____Vcellinp__reqq_queue__data_in[9U] + = ((0xffc00000U & ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__curr_bank_core_req_valid) + << 0x16U)) | ((0xfffc0000U + & ((IData)(vlTOPp->core_req_rw) + << 0x12U)) + | ((0xfffffffcU + & ((IData)(vlTOPp->core_req_byteen) + << 2U)) + | (0x3ffU + & (vlTOPp->core_req_addr[3U] + >> 0x16U))))); + vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__writing + = ((((0U != (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__curr_bank_core_req_valid)) + & (~ (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__full_r))) + & (~ (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__full_r))) + & (~ (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__full_r))); + vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__core_req_arb__DOT____Vcellinp__reqq_queue__data_in[0U] + = (IData)(vlTOPp->core_req_tag); + vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__core_req_arb__DOT____Vcellinp__reqq_queue__data_in[1U] + = ((0xfffffc00U & (vlTOPp->core_req_data[0U] + << 0xaU)) | (IData)((vlTOPp->core_req_tag + >> 0x20U))); + vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__core_req_arb__DOT____Vcellinp__reqq_queue__data_in[2U] + = ((0x3ffU & (vlTOPp->core_req_data[0U] >> 0x16U)) + | (0xfffffc00U & (vlTOPp->core_req_data[1U] + << 0xaU))); + vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__core_req_arb__DOT____Vcellinp__reqq_queue__data_in[3U] + = ((0x3ffU & (vlTOPp->core_req_data[1U] >> 0x16U)) + | (0xfffffc00U & (vlTOPp->core_req_data[2U] + << 0xaU))); + vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__core_req_arb__DOT____Vcellinp__reqq_queue__data_in[4U] + = ((0x3ffU & (vlTOPp->core_req_data[2U] >> 0x16U)) + | (0xfffffc00U & (vlTOPp->core_req_data[3U] + << 0xaU))); + vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__core_req_arb__DOT____Vcellinp__reqq_queue__data_in[5U] + = ((0xfffffc00U & (vlTOPp->core_req_addr[0U] + << 0xaU)) | (0x3ffU & (vlTOPp->core_req_data[3U] + >> 0x16U))); + vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__core_req_arb__DOT____Vcellinp__reqq_queue__data_in[6U] + = ((0x3ffU & (vlTOPp->core_req_addr[0U] >> 0x16U)) + | (0xfffffc00U & (vlTOPp->core_req_addr[1U] + << 0xaU))); + vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__core_req_arb__DOT____Vcellinp__reqq_queue__data_in[7U] + = ((0x3ffU & (vlTOPp->core_req_addr[1U] >> 0x16U)) + | (0xfffffc00U & (vlTOPp->core_req_addr[2U] + << 0xaU))); + vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__core_req_arb__DOT____Vcellinp__reqq_queue__data_in[8U] + = ((0x3ffU & (vlTOPp->core_req_addr[2U] >> 0x16U)) + | (0xfffffc00U & (vlTOPp->core_req_addr[3U] + << 0xaU))); + vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__core_req_arb__DOT____Vcellinp__reqq_queue__data_in[9U] + = ((0xffc00000U & ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__curr_bank_core_req_valid) + << 0x16U)) | ((0xfffc0000U + & ((IData)(vlTOPp->core_req_rw) + << 0x12U)) + | ((0xfffffffcU + & ((IData)(vlTOPp->core_req_byteen) + << 2U)) + | (0x3ffU + & (vlTOPp->core_req_addr[3U] + >> 0x16U))))); + vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__writing + = ((((0U != (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__curr_bank_core_req_valid)) + & (~ (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__full_r))) + & (~ (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__full_r))) + & (~ (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__full_r))); + vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__core_req_arb__DOT____Vcellinp__reqq_queue__data_in[0U] + = (IData)(vlTOPp->core_req_tag); + vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__core_req_arb__DOT____Vcellinp__reqq_queue__data_in[1U] + = ((0xfffffc00U & (vlTOPp->core_req_data[0U] + << 0xaU)) | (IData)((vlTOPp->core_req_tag + >> 0x20U))); + vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__core_req_arb__DOT____Vcellinp__reqq_queue__data_in[2U] + = ((0x3ffU & (vlTOPp->core_req_data[0U] >> 0x16U)) + | (0xfffffc00U & (vlTOPp->core_req_data[1U] + << 0xaU))); + vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__core_req_arb__DOT____Vcellinp__reqq_queue__data_in[3U] + = ((0x3ffU & (vlTOPp->core_req_data[1U] >> 0x16U)) + | (0xfffffc00U & (vlTOPp->core_req_data[2U] + << 0xaU))); + vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__core_req_arb__DOT____Vcellinp__reqq_queue__data_in[4U] + = ((0x3ffU & (vlTOPp->core_req_data[2U] >> 0x16U)) + | (0xfffffc00U & (vlTOPp->core_req_data[3U] + << 0xaU))); + vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__core_req_arb__DOT____Vcellinp__reqq_queue__data_in[5U] + = ((0xfffffc00U & (vlTOPp->core_req_addr[0U] + << 0xaU)) | (0x3ffU & (vlTOPp->core_req_data[3U] + >> 0x16U))); + vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__core_req_arb__DOT____Vcellinp__reqq_queue__data_in[6U] + = ((0x3ffU & (vlTOPp->core_req_addr[0U] >> 0x16U)) + | (0xfffffc00U & (vlTOPp->core_req_addr[1U] + << 0xaU))); + vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__core_req_arb__DOT____Vcellinp__reqq_queue__data_in[7U] + = ((0x3ffU & (vlTOPp->core_req_addr[1U] >> 0x16U)) + | (0xfffffc00U & (vlTOPp->core_req_addr[2U] + << 0xaU))); + vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__core_req_arb__DOT____Vcellinp__reqq_queue__data_in[8U] + = ((0x3ffU & (vlTOPp->core_req_addr[2U] >> 0x16U)) + | (0xfffffc00U & (vlTOPp->core_req_addr[3U] + << 0xaU))); + vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__core_req_arb__DOT____Vcellinp__reqq_queue__data_in[9U] + = ((0xffc00000U & ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__curr_bank_core_req_valid) + << 0x16U)) | ((0xfffc0000U + & ((IData)(vlTOPp->core_req_rw) + << 0x12U)) + | ((0xfffffffcU + & ((IData)(vlTOPp->core_req_byteen) + << 2U)) + | (0x3ffU + & (vlTOPp->core_req_addr[3U] + >> 0x16U))))); + vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__writing + = ((((0U != (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__curr_bank_core_req_valid)) + & (~ (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__full_r))) + & (~ (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__full_r))) + & (~ (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__full_r))); + vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__core_req_arb__DOT____Vcellinp__reqq_queue__data_in[0U] + = (IData)(vlTOPp->core_req_tag); + vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__core_req_arb__DOT____Vcellinp__reqq_queue__data_in[1U] + = ((0xfffffc00U & (vlTOPp->core_req_data[0U] + << 0xaU)) | (IData)((vlTOPp->core_req_tag + >> 0x20U))); + vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__core_req_arb__DOT____Vcellinp__reqq_queue__data_in[2U] + = ((0x3ffU & (vlTOPp->core_req_data[0U] >> 0x16U)) + | (0xfffffc00U & (vlTOPp->core_req_data[1U] + << 0xaU))); + vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__core_req_arb__DOT____Vcellinp__reqq_queue__data_in[3U] + = ((0x3ffU & (vlTOPp->core_req_data[1U] >> 0x16U)) + | (0xfffffc00U & (vlTOPp->core_req_data[2U] + << 0xaU))); + vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__core_req_arb__DOT____Vcellinp__reqq_queue__data_in[4U] + = ((0x3ffU & (vlTOPp->core_req_data[2U] >> 0x16U)) + | (0xfffffc00U & (vlTOPp->core_req_data[3U] + << 0xaU))); + vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__core_req_arb__DOT____Vcellinp__reqq_queue__data_in[5U] + = ((0xfffffc00U & (vlTOPp->core_req_addr[0U] + << 0xaU)) | (0x3ffU & (vlTOPp->core_req_data[3U] + >> 0x16U))); + vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__core_req_arb__DOT____Vcellinp__reqq_queue__data_in[6U] + = ((0x3ffU & (vlTOPp->core_req_addr[0U] >> 0x16U)) + | (0xfffffc00U & (vlTOPp->core_req_addr[1U] + << 0xaU))); + vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__core_req_arb__DOT____Vcellinp__reqq_queue__data_in[7U] + = ((0x3ffU & (vlTOPp->core_req_addr[1U] >> 0x16U)) + | (0xfffffc00U & (vlTOPp->core_req_addr[2U] + << 0xaU))); + vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__core_req_arb__DOT____Vcellinp__reqq_queue__data_in[8U] + = ((0x3ffU & (vlTOPp->core_req_addr[2U] >> 0x16U)) + | (0xfffffc00U & (vlTOPp->core_req_addr[3U] + << 0xaU))); + vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__core_req_arb__DOT____Vcellinp__reqq_queue__data_in[9U] + = ((0xffc00000U & ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__curr_bank_core_req_valid) + << 0x16U)) | ((0xfffc0000U + & ((IData)(vlTOPp->core_req_rw) + << 0x12U)) + | ((0xfffffffcU + & ((IData)(vlTOPp->core_req_byteen) + << 2U)) + | (0x3ffU + & (vlTOPp->core_req_addr[3U] + >> 0x16U))))); + vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__dwb_queue__DOT__reading + = ((((((vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT____Vcellout__dwb_queue__data_out[6U] + >> 7U) & (~ (vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT____Vcellout__dwb_queue__data_out[6U] + >> 6U))) & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__dram_wb_req_fire)) + | (((vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT____Vcellout__dwb_queue__data_out[6U] + >> 6U) & (~ (vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT____Vcellout__dwb_queue__data_out[6U] + >> 7U))) & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__snp_rsp_fire))) + | (((vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT____Vcellout__dwb_queue__data_out[6U] + >> 7U) & (vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT____Vcellout__dwb_queue__data_out[6U] + >> 6U)) & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__snp_rsp_fire))) + & (~ (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__genblk2__DOT__empty_r))); + vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__dwb_queue__DOT__reading + = ((((((vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT____Vcellout__dwb_queue__data_out[6U] + >> 7U) & (~ (vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT____Vcellout__dwb_queue__data_out[6U] + >> 6U))) & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__dram_wb_req_fire)) + | (((vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT____Vcellout__dwb_queue__data_out[6U] + >> 6U) & (~ (vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT____Vcellout__dwb_queue__data_out[6U] + >> 7U))) & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__snp_rsp_fire))) + | (((vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT____Vcellout__dwb_queue__data_out[6U] + >> 7U) & (vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT____Vcellout__dwb_queue__data_out[6U] + >> 6U)) & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__snp_rsp_fire))) + & (~ (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__genblk2__DOT__empty_r))); + vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__dwb_queue__DOT__reading + = ((((((vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT____Vcellout__dwb_queue__data_out[6U] + >> 7U) & (~ (vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT____Vcellout__dwb_queue__data_out[6U] + >> 6U))) & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__dram_wb_req_fire)) + | (((vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT____Vcellout__dwb_queue__data_out[6U] + >> 6U) & (~ (vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT____Vcellout__dwb_queue__data_out[6U] + >> 7U))) & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__snp_rsp_fire))) + | (((vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT____Vcellout__dwb_queue__data_out[6U] + >> 7U) & (vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT____Vcellout__dwb_queue__data_out[6U] + >> 6U)) & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__snp_rsp_fire))) + & (~ (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__genblk2__DOT__empty_r))); + vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__dwb_queue__DOT__reading + = ((((((vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT____Vcellout__dwb_queue__data_out[6U] + >> 7U) & (~ (vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT____Vcellout__dwb_queue__data_out[6U] + >> 6U))) & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__dram_wb_req_fire)) + | (((vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT____Vcellout__dwb_queue__data_out[6U] + >> 6U) & (~ (vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT____Vcellout__dwb_queue__data_out[6U] + >> 7U))) & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__snp_rsp_fire))) + | (((vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT____Vcellout__dwb_queue__data_out[6U] + >> 7U) & (vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT____Vcellout__dwb_queue__data_out[6U] + >> 6U)) & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__snp_rsp_fire))) + & (~ (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__genblk2__DOT__empty_r))); +} + +void VVX_cache::_eval(VVX_cache__Syms* __restrict vlSymsp) { + VL_DEBUG_IF(VL_DBG_MSGF("+ VVX_cache::_eval\n"); ); + VVX_cache* __restrict vlTOPp VL_ATTR_UNUSED = vlSymsp->TOPp; + // Body + vlTOPp->_combo__TOP__2(vlSymsp); + vlTOPp->__Vm_traceActivity = (2U | vlTOPp->__Vm_traceActivity); + if (((IData)(vlTOPp->clk) & (~ (IData)(vlTOPp->__Vclklast__TOP__clk)))) { + vlTOPp->_sequent__TOP__4(vlSymsp); + vlTOPp->__Vm_traceActivity = (4U | vlTOPp->__Vm_traceActivity); + } + vlTOPp->_combo__TOP__5(vlSymsp); + // Final + vlTOPp->__Vclklast__TOP__clk = vlTOPp->clk; +} + +void VVX_cache::_eval_initial(VVX_cache__Syms* __restrict vlSymsp) { + VL_DEBUG_IF(VL_DBG_MSGF("+ VVX_cache::_eval_initial\n"); ); + VVX_cache* __restrict vlTOPp VL_ATTR_UNUSED = vlSymsp->TOPp; + // Body + vlTOPp->_initial__TOP__1(vlSymsp); + vlTOPp->__Vclklast__TOP__clk = vlTOPp->clk; +} + +void VVX_cache::final() { + VL_DEBUG_IF(VL_DBG_MSGF("+ VVX_cache::final\n"); ); + // Variables + VVX_cache__Syms* __restrict vlSymsp = this->__VlSymsp; + VVX_cache* __restrict vlTOPp VL_ATTR_UNUSED = vlSymsp->TOPp; +} + +void VVX_cache::_eval_settle(VVX_cache__Syms* __restrict vlSymsp) { + VL_DEBUG_IF(VL_DBG_MSGF("+ VVX_cache::_eval_settle\n"); ); + VVX_cache* __restrict vlTOPp VL_ATTR_UNUSED = vlSymsp->TOPp; + // Body + vlTOPp->_settle__TOP__3(vlSymsp); + vlTOPp->__Vm_traceActivity = (1U | vlTOPp->__Vm_traceActivity); +} + +VL_INLINE_OPT QData VVX_cache::_change_request(VVX_cache__Syms* __restrict vlSymsp) { + VL_DEBUG_IF(VL_DBG_MSGF("+ VVX_cache::_change_request\n"); ); + VVX_cache* __restrict vlTOPp VL_ATTR_UNUSED = vlSymsp->TOPp; + // Body + // Change detection + QData __req = false; // Logically a bool + return __req; +} + +#ifdef VL_DEBUG +void VVX_cache::_eval_debug_assertions() { + VL_DEBUG_IF(VL_DBG_MSGF("+ VVX_cache::_eval_debug_assertions\n"); ); + // Body + if (VL_UNLIKELY((clk & 0xfeU))) { + Verilated::overWidthError("clk");} + if (VL_UNLIKELY((reset & 0xfeU))) { + Verilated::overWidthError("reset");} + if (VL_UNLIKELY((core_req_valid & 0xf0U))) { + Verilated::overWidthError("core_req_valid");} + if (VL_UNLIKELY((core_req_rw & 0xf0U))) { + Verilated::overWidthError("core_req_rw");} + if (VL_UNLIKELY((core_rsp_ready & 0xfeU))) { + Verilated::overWidthError("core_rsp_ready");} + if (VL_UNLIKELY((dram_req_ready & 0xfeU))) { + Verilated::overWidthError("dram_req_ready");} + if (VL_UNLIKELY((dram_rsp_valid & 0xfeU))) { + Verilated::overWidthError("dram_rsp_valid");} + if (VL_UNLIKELY((dram_rsp_tag & 0xf0000000U))) { + Verilated::overWidthError("dram_rsp_tag");} + if (VL_UNLIKELY((snp_req_valid & 0xfeU))) { + Verilated::overWidthError("snp_req_valid");} + if (VL_UNLIKELY((snp_req_addr & 0xf0000000U))) { + Verilated::overWidthError("snp_req_addr");} + if (VL_UNLIKELY((snp_req_invalidate & 0xfeU))) { + Verilated::overWidthError("snp_req_invalidate");} + if (VL_UNLIKELY((snp_req_tag & 0xf0000000U))) { + Verilated::overWidthError("snp_req_tag");} + if (VL_UNLIKELY((snp_rsp_ready & 0xfeU))) { + Verilated::overWidthError("snp_rsp_ready");} + if (VL_UNLIKELY((snp_fwdout_ready & 0xfcU))) { + Verilated::overWidthError("snp_fwdout_ready");} + if (VL_UNLIKELY((snp_fwdin_valid & 0xfcU))) { + Verilated::overWidthError("snp_fwdin_valid");} +} +#endif // VL_DEBUG + +void VVX_cache::_ctor_var_reset() { + VL_DEBUG_IF(VL_DBG_MSGF("+ VVX_cache::_ctor_var_reset\n"); ); + // Body + clk = VL_RAND_RESET_I(1); + reset = VL_RAND_RESET_I(1); + core_req_valid = VL_RAND_RESET_I(4); + core_req_rw = VL_RAND_RESET_I(4); + core_req_byteen = VL_RAND_RESET_I(16); + VL_RAND_RESET_W(120, core_req_addr); + VL_RAND_RESET_W(128, core_req_data); + core_req_tag = VL_RAND_RESET_Q(42); + core_req_ready = VL_RAND_RESET_I(1); + core_rsp_valid = VL_RAND_RESET_I(4); + VL_RAND_RESET_W(128, core_rsp_data); + core_rsp_tag = VL_RAND_RESET_Q(42); + core_rsp_ready = VL_RAND_RESET_I(1); + dram_req_valid = VL_RAND_RESET_I(1); + dram_req_rw = VL_RAND_RESET_I(1); + dram_req_byteen = VL_RAND_RESET_I(16); + dram_req_addr = VL_RAND_RESET_I(28); + VL_RAND_RESET_W(128, dram_req_data); + dram_req_tag = VL_RAND_RESET_I(28); + dram_req_ready = VL_RAND_RESET_I(1); + dram_rsp_valid = VL_RAND_RESET_I(1); + VL_RAND_RESET_W(128, dram_rsp_data); + dram_rsp_tag = VL_RAND_RESET_I(28); + dram_rsp_ready = VL_RAND_RESET_I(1); + snp_req_valid = VL_RAND_RESET_I(1); + snp_req_addr = VL_RAND_RESET_I(28); + snp_req_invalidate = VL_RAND_RESET_I(1); + snp_req_tag = VL_RAND_RESET_I(28); + snp_req_ready = VL_RAND_RESET_I(1); + snp_rsp_valid = VL_RAND_RESET_I(1); + snp_rsp_tag = VL_RAND_RESET_I(28); + snp_rsp_ready = VL_RAND_RESET_I(1); + snp_fwdout_valid = VL_RAND_RESET_I(2); + snp_fwdout_addr = VL_RAND_RESET_Q(56); + snp_fwdout_invalidate = VL_RAND_RESET_I(2); + snp_fwdout_tag = VL_RAND_RESET_I(2); + snp_fwdout_ready = VL_RAND_RESET_I(2); + snp_fwdin_valid = VL_RAND_RESET_I(2); + snp_fwdin_tag = VL_RAND_RESET_I(2); + snp_fwdin_ready = VL_RAND_RESET_I(2); + VX_cache__DOT__per_bank_core_req_ready = VL_RAND_RESET_I(4); + VX_cache__DOT__per_bank_core_rsp_valid = VL_RAND_RESET_I(4); + VX_cache__DOT__per_bank_core_rsp_tid = VL_RAND_RESET_I(8); + VL_RAND_RESET_W(128, VX_cache__DOT__per_bank_core_rsp_data); + VL_RAND_RESET_W(168, VX_cache__DOT__per_bank_core_rsp_tag); + VX_cache__DOT__per_bank_core_rsp_ready = VL_RAND_RESET_I(4); + VX_cache__DOT__per_bank_dram_fill_req_valid = VL_RAND_RESET_I(4); + VL_RAND_RESET_W(112, VX_cache__DOT__per_bank_dram_fill_req_addr); + VX_cache__DOT__per_bank_dram_fill_rsp_ready = VL_RAND_RESET_I(4); + VX_cache__DOT__per_bank_dram_wb_req_ready = VL_RAND_RESET_I(4); + VX_cache__DOT__per_bank_dram_wb_req_valid = VL_RAND_RESET_I(4); + VX_cache__DOT__per_bank_dram_wb_req_byteen = VL_RAND_RESET_Q(64); + VL_RAND_RESET_W(112, VX_cache__DOT__per_bank_dram_wb_req_addr); + VL_RAND_RESET_W(512, VX_cache__DOT__per_bank_dram_wb_req_data); + VX_cache__DOT__per_bank_snp_req_ready = VL_RAND_RESET_I(4); + VX_cache__DOT__per_bank_snp_rsp_valid = VL_RAND_RESET_I(4); + VL_RAND_RESET_W(112, VX_cache__DOT__per_bank_snp_rsp_tag); + VX_cache__DOT__per_bank_snp_rsp_ready = VL_RAND_RESET_I(4); + VX_cache__DOT____Vcellout__cache_core_req_bank_sel__per_bank_valid = VL_RAND_RESET_I(16); + VL_RAND_RESET_W(128, VX_cache__DOT____Vcellout__cache_core_rsp_merge__core_rsp_data); + VX_cache__DOT__genblk5__BRA__0__KET____DOT__curr_bank_core_req_valid = VL_RAND_RESET_I(4); + VX_cache__DOT__genblk5__BRA__0__KET____DOT__curr_bank_dram_wb_req_valid = VL_RAND_RESET_I(1); + VX_cache__DOT__genblk5__BRA__0__KET____DOT__curr_bank_snp_rsp_valid = VL_RAND_RESET_I(1); + VX_cache__DOT__genblk5__BRA__1__KET____DOT__curr_bank_core_req_valid = VL_RAND_RESET_I(4); + VX_cache__DOT__genblk5__BRA__1__KET____DOT__curr_bank_dram_wb_req_valid = VL_RAND_RESET_I(1); + VX_cache__DOT__genblk5__BRA__1__KET____DOT__curr_bank_snp_rsp_valid = VL_RAND_RESET_I(1); + VX_cache__DOT__genblk5__BRA__2__KET____DOT__curr_bank_core_req_valid = VL_RAND_RESET_I(4); + VX_cache__DOT__genblk5__BRA__2__KET____DOT__curr_bank_dram_wb_req_valid = VL_RAND_RESET_I(1); + VX_cache__DOT__genblk5__BRA__2__KET____DOT__curr_bank_snp_rsp_valid = VL_RAND_RESET_I(1); + VX_cache__DOT__genblk5__BRA__3__KET____DOT__curr_bank_core_req_valid = VL_RAND_RESET_I(4); + VX_cache__DOT__genblk5__BRA__3__KET____DOT__curr_bank_dram_wb_req_valid = VL_RAND_RESET_I(1); + VX_cache__DOT__genblk5__BRA__3__KET____DOT__curr_bank_snp_rsp_valid = VL_RAND_RESET_I(1); + VX_cache__DOT__cache_core_req_bank_sel__DOT__genblk2__DOT__per_bank_ready_sel = VL_RAND_RESET_I(4); + VX_cache__DOT__cache_dram_req_arb__DOT__dwb_valid = VL_RAND_RESET_I(1); + VX_cache__DOT__cache_dram_req_arb__DOT__dfqq_req = VL_RAND_RESET_I(1); + VX_cache__DOT__cache_dram_req_arb__DOT__dfqq_pop = VL_RAND_RESET_I(1); + VX_cache__DOT__cache_dram_req_arb__DOT__dwb_bank = VL_RAND_RESET_I(2); + VX_cache__DOT__cache_dram_req_arb__DOT__prfqq__DOT__use_valid = VL_RAND_RESET_I(2); + VX_cache__DOT__cache_dram_req_arb__DOT__prfqq__DOT__use_addr = VL_RAND_RESET_I(28); + VX_cache__DOT__cache_dram_req_arb__DOT__prfqq__DOT__update_use = VL_RAND_RESET_I(1); + VX_cache__DOT__cache_dram_req_arb__DOT__prfqq__DOT__pfq_queue__DOT__size_r = VL_RAND_RESET_I(1); + VX_cache__DOT__cache_dram_req_arb__DOT__prfqq__DOT__pfq_queue__DOT__reading = VL_RAND_RESET_I(1); + VX_cache__DOT__cache_dram_req_arb__DOT__prfqq__DOT__pfq_queue__DOT__writing = VL_RAND_RESET_I(1); + VX_cache__DOT__cache_dram_req_arb__DOT__prfqq__DOT__pfq_queue__DOT__genblk2__DOT__head_r = VL_RAND_RESET_I(28); + VX_cache__DOT__cache_dram_req_arb__DOT__dram_fill_arb__DOT__use_per_bank_dram_fill_req_valid = VL_RAND_RESET_I(4); + VL_RAND_RESET_W(112, VX_cache__DOT__cache_dram_req_arb__DOT__dram_fill_arb__DOT__use_per_bank_dram_fill_req_addr); + VX_cache__DOT__cache_dram_req_arb__DOT__dram_fill_arb__DOT__use_per_bqual_bank_dram_fill_req_valid = VL_RAND_RESET_I(4); + VL_RAND_RESET_W(112, VX_cache__DOT__cache_dram_req_arb__DOT__dram_fill_arb__DOT__qual_bank_dram_fill_req_addr); + VL_RAND_RESET_W(116, VX_cache__DOT__cache_dram_req_arb__DOT__dram_fill_arb__DOT____Vcellout__dfqq_queue__data_out); + VL_RAND_RESET_W(116, VX_cache__DOT__cache_dram_req_arb__DOT__dram_fill_arb__DOT____Vcellinp__dfqq_queue__data_in); + VX_cache__DOT__cache_dram_req_arb__DOT__dram_fill_arb__DOT__qual_request_index = VL_RAND_RESET_I(2); + VX_cache__DOT__cache_dram_req_arb__DOT__dram_fill_arb__DOT__qual_has_request = VL_RAND_RESET_I(1); + VX_cache__DOT__cache_dram_req_arb__DOT__dram_fill_arb__DOT__dfqq_queue__DOT__size_r = VL_RAND_RESET_I(3); + VX_cache__DOT__cache_dram_req_arb__DOT__dram_fill_arb__DOT__dfqq_queue__DOT__reading = VL_RAND_RESET_I(1); + VX_cache__DOT__cache_dram_req_arb__DOT__dram_fill_arb__DOT__dfqq_queue__DOT__writing = VL_RAND_RESET_I(1); + { int __Vi0=0; for (; __Vi0<4; ++__Vi0) { + VL_RAND_RESET_W(116, VX_cache__DOT__cache_dram_req_arb__DOT__dram_fill_arb__DOT__dfqq_queue__DOT__genblk3__DOT__data[__Vi0]); + }} + VL_RAND_RESET_W(116, VX_cache__DOT__cache_dram_req_arb__DOT__dram_fill_arb__DOT__dfqq_queue__DOT__genblk3__DOT__genblk2__DOT__head_r); + VL_RAND_RESET_W(116, VX_cache__DOT__cache_dram_req_arb__DOT__dram_fill_arb__DOT__dfqq_queue__DOT__genblk3__DOT__genblk2__DOT__curr_r); + VX_cache__DOT__cache_dram_req_arb__DOT__dram_fill_arb__DOT__dfqq_queue__DOT__genblk3__DOT__genblk2__DOT__wr_ptr_r = VL_RAND_RESET_I(2); + VX_cache__DOT__cache_dram_req_arb__DOT__dram_fill_arb__DOT__dfqq_queue__DOT__genblk3__DOT__genblk2__DOT__rd_ptr_r = VL_RAND_RESET_I(2); + VX_cache__DOT__cache_dram_req_arb__DOT__dram_fill_arb__DOT__dfqq_queue__DOT__genblk3__DOT__genblk2__DOT__rd_ptr_next_r = VL_RAND_RESET_I(2); + VX_cache__DOT__cache_dram_req_arb__DOT__dram_fill_arb__DOT__dfqq_queue__DOT__genblk3__DOT__genblk2__DOT__empty_r = VL_RAND_RESET_I(1); + VX_cache__DOT__cache_dram_req_arb__DOT__dram_fill_arb__DOT__dfqq_queue__DOT__genblk3__DOT__genblk2__DOT__full_r = VL_RAND_RESET_I(1); + VX_cache__DOT__cache_dram_req_arb__DOT__dram_fill_arb__DOT__dfqq_queue__DOT__genblk3__DOT__genblk2__DOT__bypass_r = VL_RAND_RESET_I(1); + VX_cache__DOT__cache_dram_req_arb__DOT__dram_fill_arb__DOT__sel_bank__DOT__genblk2__DOT__grant_onehot_r = VL_RAND_RESET_I(4); + VX_cache__DOT__cache_dram_req_arb__DOT__dram_fill_arb__DOT__sel_bank__DOT__genblk2__DOT__priority_encoder__DOT__i = VL_RAND_RESET_I(32); + VX_cache__DOT__cache_dram_req_arb__DOT__sel_dwb__DOT__genblk2__DOT__grant_onehot_r = VL_RAND_RESET_I(4); + VX_cache__DOT__cache_dram_req_arb__DOT__sel_dwb__DOT__genblk2__DOT__priority_encoder__DOT__i = VL_RAND_RESET_I(32); + VX_cache__DOT__cache_core_rsp_merge__DOT__main_bank_index = VL_RAND_RESET_I(2); + VX_cache__DOT__cache_core_rsp_merge__DOT__per_bank_core_rsp_pop_unqual = VL_RAND_RESET_I(4); + VX_cache__DOT__cache_core_rsp_merge__DOT__sel_bank__DOT__grant_valid = VL_RAND_RESET_I(1); + VX_cache__DOT__cache_core_rsp_merge__DOT__sel_bank__DOT__genblk2__DOT__requests_use = VL_RAND_RESET_I(4); + VX_cache__DOT__cache_core_rsp_merge__DOT__sel_bank__DOT__genblk2__DOT__update_value = VL_RAND_RESET_I(4); + VX_cache__DOT__cache_core_rsp_merge__DOT__sel_bank__DOT__genblk2__DOT__refill = VL_RAND_RESET_I(1); + VX_cache__DOT__cache_core_rsp_merge__DOT__sel_bank__DOT__genblk2__DOT__refill_original = VL_RAND_RESET_I(4); + VX_cache__DOT__cache_core_rsp_merge__DOT__sel_bank__DOT__genblk2__DOT__grant_onehot_r = VL_RAND_RESET_I(4); + VX_cache__DOT__cache_core_rsp_merge__DOT__sel_bank__DOT__genblk2__DOT__priority_encoder__DOT__i = VL_RAND_RESET_I(32); + VX_cache__DOT__snp_rsp_arb__DOT__fsq_bank = VL_RAND_RESET_I(2); + VX_cache__DOT__snp_rsp_arb__DOT__fsq_valid = VL_RAND_RESET_I(1); + VX_cache__DOT__snp_rsp_arb__DOT__sel_ffsq__DOT__genblk2__DOT__grant_onehot_r = VL_RAND_RESET_I(4); + VX_cache__DOT__snp_rsp_arb__DOT__sel_ffsq__DOT__genblk2__DOT__priority_encoder__DOT__i = VL_RAND_RESET_I(32); + VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__snrq_pop = VL_RAND_RESET_I(1); + VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT____Vcellout__snp_req_queue__data_out = VL_RAND_RESET_Q(55); + VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT____Vcellinp__snp_req_queue__data_in = VL_RAND_RESET_Q(55); + VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__dfpq_pop = VL_RAND_RESET_I(1); + VL_RAND_RESET_W(154, VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT____Vcellout__dfp_queue__data_out); + VL_RAND_RESET_W(154, VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT____Vcellinp__dfp_queue__data_in); + VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__reqq_pop = VL_RAND_RESET_I(1); + VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__reqq_req_rw_st0 = VL_RAND_RESET_I(1); + VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__reqq_req_addr_st0 = VL_RAND_RESET_I(30); + VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__mrvq_pop = VL_RAND_RESET_I(1); + VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__mrvq_rw_st0 = VL_RAND_RESET_I(1); + VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__force_request_miss_st1e = VL_RAND_RESET_I(1); + VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__recover_mrvq_state_st2 = VL_RAND_RESET_I(1); + VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__mrvq_push_stall = VL_RAND_RESET_I(1); + VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cwbq_push_stall = VL_RAND_RESET_I(1); + VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__dwbq_push_stall = VL_RAND_RESET_I(1); + VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__dram_fill_req_stall = VL_RAND_RESET_I(1); + VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__stall_bank_pipe = VL_RAND_RESET_I(1); + VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__is_fill_in_pipe = VL_RAND_RESET_I(1); + { int __Vi0=0; for (; __Vi0<1; ++__Vi0) { + VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__is_fill_st1[__Vi0] = VL_RAND_RESET_I(1); + }} + { int __Vi0=0; for (; __Vi0<1; ++__Vi0) { + VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__going_to_write_st1[__Vi0] = VL_RAND_RESET_I(1); + }} + VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__dfpq_pop_unqual = VL_RAND_RESET_I(1); + VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__reqq_pop_unqual = VL_RAND_RESET_I(1); + VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__snrq_pop_unqual = VL_RAND_RESET_I(1); + { int __Vi0=0; for (; __Vi0<1; ++__Vi0) { + VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__valid_st1[__Vi0] = VL_RAND_RESET_I(1); + }} + { int __Vi0=0; for (; __Vi0<1; ++__Vi0) { + VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__addr_st1[__Vi0] = VL_RAND_RESET_I(26); + }} + { int __Vi0=0; for (; __Vi0<1; ++__Vi0) { + VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__wsel_st1[__Vi0] = VL_RAND_RESET_I(2); + }} + { int __Vi0=0; for (; __Vi0<1; ++__Vi0) { + VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__writeword_st1[__Vi0] = VL_RAND_RESET_I(32); + }} + { int __Vi0=0; for (; __Vi0<1; ++__Vi0) { + VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__inst_meta_st1[__Vi0] = VL_RAND_RESET_Q(49); + }} + { int __Vi0=0; for (; __Vi0<1; ++__Vi0) { + VL_RAND_RESET_W(128, VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__writedata_st1[__Vi0]); + }} + { int __Vi0=0; for (; __Vi0<1; ++__Vi0) { + VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__is_snp_st1[__Vi0] = VL_RAND_RESET_I(1); + }} + { int __Vi0=0; for (; __Vi0<1; ++__Vi0) { + VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__snp_invalidate_st1[__Vi0] = VL_RAND_RESET_I(1); + }} + { int __Vi0=0; for (; __Vi0<1; ++__Vi0) { + VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__is_mrvq_st1[__Vi0] = VL_RAND_RESET_I(1); + }} + VL_RAND_RESET_W(243, VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT____Vcellinp__s0_1_c0__in); + VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__miss_st1e = VL_RAND_RESET_I(1); + VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__dirty_st1e = VL_RAND_RESET_I(1); + VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__snp_to_mrvq_st1e = VL_RAND_RESET_I(1); + VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__miss_add_because_miss = VL_RAND_RESET_I(1); + VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__mrvq_init_ready_state_st2 = VL_RAND_RESET_I(1); + VL_RAND_RESET_W(316, VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT____Vcellinp__st_1e_2__in); + VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__miss_add_unqual = VL_RAND_RESET_I(1); + VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__miss_add = VL_RAND_RESET_I(1); + VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__miss_add_is_mrvq = VL_RAND_RESET_I(1); + VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cwbq_push_unqual = VL_RAND_RESET_I(1); + VL_RAND_RESET_W(76, VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT____Vcellout__cwb_queue__data_out); + VL_RAND_RESET_W(76, VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT____Vcellinp__cwb_queue__data_in); + VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__dwbq_is_dwb_in = VL_RAND_RESET_I(1); + VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__dwbq_is_snp_in = VL_RAND_RESET_I(1); + VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__dwbq_push_unqual = VL_RAND_RESET_I(1); + VL_RAND_RESET_W(200, VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT____Vcellout__dwb_queue__data_out); + VL_RAND_RESET_W(200, VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT____Vcellinp__dwb_queue__data_in); + VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__dram_wb_req_fire = VL_RAND_RESET_I(1); + VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__snp_rsp_fire = VL_RAND_RESET_I(1); + VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__dwbq_dual_valid_sel = VL_RAND_RESET_I(1); + VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__snp_req_queue__DOT__size_r = VL_RAND_RESET_I(5); + VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__snp_req_queue__DOT__reading = VL_RAND_RESET_I(1); + VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__snp_req_queue__DOT__writing = VL_RAND_RESET_I(1); + { int __Vi0=0; for (; __Vi0<16; ++__Vi0) { + VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__snp_req_queue__DOT__genblk3__DOT__data[__Vi0] = VL_RAND_RESET_Q(55); + }} + VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__snp_req_queue__DOT__genblk3__DOT__genblk2__DOT__head_r = VL_RAND_RESET_Q(55); + VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__snp_req_queue__DOT__genblk3__DOT__genblk2__DOT__curr_r = VL_RAND_RESET_Q(55); + VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__snp_req_queue__DOT__genblk3__DOT__genblk2__DOT__wr_ptr_r = VL_RAND_RESET_I(4); + VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__snp_req_queue__DOT__genblk3__DOT__genblk2__DOT__rd_ptr_r = VL_RAND_RESET_I(4); + VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__snp_req_queue__DOT__genblk3__DOT__genblk2__DOT__rd_ptr_next_r = VL_RAND_RESET_I(4); + VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__snp_req_queue__DOT__genblk3__DOT__genblk2__DOT__empty_r = VL_RAND_RESET_I(1); + VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__snp_req_queue__DOT__genblk3__DOT__genblk2__DOT__full_r = VL_RAND_RESET_I(1); + VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__snp_req_queue__DOT__genblk3__DOT__genblk2__DOT__bypass_r = VL_RAND_RESET_I(1); + VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__dfp_queue__DOT__size_r = VL_RAND_RESET_I(5); + VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__dfp_queue__DOT__reading = VL_RAND_RESET_I(1); + VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__dfp_queue__DOT__writing = VL_RAND_RESET_I(1); + { int __Vi0=0; for (; __Vi0<16; ++__Vi0) { + VL_RAND_RESET_W(154, VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__dfp_queue__DOT__genblk3__DOT__data[__Vi0]); + }} + VL_RAND_RESET_W(154, VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__dfp_queue__DOT__genblk3__DOT__genblk2__DOT__head_r); + VL_RAND_RESET_W(154, VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__dfp_queue__DOT__genblk3__DOT__genblk2__DOT__curr_r); + VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__dfp_queue__DOT__genblk3__DOT__genblk2__DOT__wr_ptr_r = VL_RAND_RESET_I(4); + VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__dfp_queue__DOT__genblk3__DOT__genblk2__DOT__rd_ptr_r = VL_RAND_RESET_I(4); + VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__dfp_queue__DOT__genblk3__DOT__genblk2__DOT__rd_ptr_next_r = VL_RAND_RESET_I(4); + VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__dfp_queue__DOT__genblk3__DOT__genblk2__DOT__empty_r = VL_RAND_RESET_I(1); + VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__dfp_queue__DOT__genblk3__DOT__genblk2__DOT__full_r = VL_RAND_RESET_I(1); + VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__dfp_queue__DOT__genblk3__DOT__genblk2__DOT__bypass_r = VL_RAND_RESET_I(1); + VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__core_req_arb__DOT__use_per_valids = VL_RAND_RESET_I(4); + VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__core_req_arb__DOT__use_per_rw = VL_RAND_RESET_I(4); + VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__core_req_arb__DOT__use_per_byteen = VL_RAND_RESET_I(16); + VL_RAND_RESET_W(120, VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__core_req_arb__DOT__use_per_addr); + VL_RAND_RESET_W(128, VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__core_req_arb__DOT__use_per_writedata); + VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__core_req_arb__DOT__use_per_tag = VL_RAND_RESET_Q(42); + VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__core_req_arb__DOT__out_empty = VL_RAND_RESET_I(1); + VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__core_req_arb__DOT__pop_qual = VL_RAND_RESET_I(1); + VL_RAND_RESET_W(314, VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__core_req_arb__DOT____Vcellout__reqq_queue__data_out); + VL_RAND_RESET_W(314, VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__core_req_arb__DOT____Vcellinp__reqq_queue__data_in); + VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__core_req_arb__DOT__qual_request_index = VL_RAND_RESET_I(2); + VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__core_req_arb__DOT__qual_has_request = VL_RAND_RESET_I(1); + VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__size_r = VL_RAND_RESET_I(3); + VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__reading = VL_RAND_RESET_I(1); + VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__writing = VL_RAND_RESET_I(1); + { int __Vi0=0; for (; __Vi0<4; ++__Vi0) { + VL_RAND_RESET_W(314, VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__data[__Vi0]); + }} + VL_RAND_RESET_W(314, VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__head_r); + VL_RAND_RESET_W(314, VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__curr_r); + VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__wr_ptr_r = VL_RAND_RESET_I(2); + VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__rd_ptr_r = VL_RAND_RESET_I(2); + VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__rd_ptr_next_r = VL_RAND_RESET_I(2); + VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__empty_r = VL_RAND_RESET_I(1); + VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__full_r = VL_RAND_RESET_I(1); + VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__bypass_r = VL_RAND_RESET_I(1); + VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__core_req_arb__DOT__sel_bank__DOT__genblk2__DOT__grant_onehot_r = VL_RAND_RESET_I(4); + VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__core_req_arb__DOT__sel_bank__DOT__genblk2__DOT__priority_encoder__DOT__i = VL_RAND_RESET_I(32); + VL_RAND_RESET_W(243, VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__s0_1_c0__DOT__value); + { int __Vi0=0; for (; __Vi0<1; ++__Vi0) { + VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__tag_data_access__DOT__read_valid_st1c[__Vi0] = VL_RAND_RESET_I(1); + }} + { int __Vi0=0; for (; __Vi0<1; ++__Vi0) { + VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__tag_data_access__DOT__read_dirty_st1c[__Vi0] = VL_RAND_RESET_I(1); + }} + { int __Vi0=0; for (; __Vi0<1; ++__Vi0) { + VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__tag_data_access__DOT__read_dirtyb_st1c[__Vi0] = VL_RAND_RESET_I(16); + }} + { int __Vi0=0; for (; __Vi0<1; ++__Vi0) { + VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__tag_data_access__DOT__read_tag_st1c[__Vi0] = VL_RAND_RESET_I(20); + }} + { int __Vi0=0; for (; __Vi0<1; ++__Vi0) { + VL_RAND_RESET_W(128, VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__tag_data_access__DOT__read_data_st1c[__Vi0]); + }} + VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__tag_data_access__DOT__use_write_enable = VL_RAND_RESET_I(16); + VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__tag_data_access__DOT__tags_match = VL_RAND_RESET_I(1); + VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__tag_data_access__DOT__real_writefill = VL_RAND_RESET_I(1); + VL_RAND_RESET_W(166, VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__tag_data_access__DOT____Vcellinp__s0_1_c0__in); + VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__tag_data_access__DOT__we = VL_RAND_RESET_I(16); + VL_RAND_RESET_W(128, VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__tag_data_access__DOT__data_write); + VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__tag_data_access__DOT__should_write = VL_RAND_RESET_I(1); + VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__tag_data_access__DOT__snoop_hit_no_pending = VL_RAND_RESET_I(1); + VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__tag_data_access__DOT__real_miss = VL_RAND_RESET_I(1); + { int __Vi0=0; for (; __Vi0<64; ++__Vi0) { + VL_RAND_RESET_W(128, VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__data[__Vi0]); + }} + { int __Vi0=0; for (; __Vi0<64; ++__Vi0) { + VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__tag[__Vi0] = VL_RAND_RESET_I(20); + }} + { int __Vi0=0; for (; __Vi0<64; ++__Vi0) { + VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__dirtyb[__Vi0] = VL_RAND_RESET_I(16); + }} + VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__dirty = VL_RAND_RESET_Q(64); + VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__valid = VL_RAND_RESET_Q(64); + VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__i = VL_RAND_RESET_I(32); + VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__j = VL_RAND_RESET_I(32); + VL_RAND_RESET_W(166, VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__tag_data_access__DOT__s0_1_c0__DOT__value); + VL_RAND_RESET_W(316, VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__st_1e_2__DOT__value); + { int __Vi0=0; for (; __Vi0<16; ++__Vi0) { + VL_RAND_RESET_W(85, VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cache_miss_resrv__DOT__metadata_table[__Vi0]); + }} + VL_RAND_RESET_W(416, VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cache_miss_resrv__DOT__addr_table); + VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cache_miss_resrv__DOT__valid_table = VL_RAND_RESET_I(16); + VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cache_miss_resrv__DOT__ready_table = VL_RAND_RESET_I(16); + VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr = VL_RAND_RESET_I(4); + VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cache_miss_resrv__DOT__head_ptr = VL_RAND_RESET_I(4); + VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cache_miss_resrv__DOT__tail_ptr = VL_RAND_RESET_I(4); + VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cache_miss_resrv__DOT__size = VL_RAND_RESET_I(5); + VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cache_miss_resrv__DOT__make_ready = VL_RAND_RESET_I(16); + VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cache_miss_resrv__DOT__valid_address_match = VL_RAND_RESET_I(16); + VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cache_miss_resrv__DOT__dequeue_possible = VL_RAND_RESET_I(1); + VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cache_miss_resrv__DOT__mrvq_push = VL_RAND_RESET_I(1); + VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cache_miss_resrv__DOT__mrvq_pop = VL_RAND_RESET_I(1); + VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cache_miss_resrv__DOT__increment_head = VL_RAND_RESET_I(1); + VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cache_miss_resrv__DOT____Vlvbound1 = VL_RAND_RESET_I(26); + VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cwb_queue__DOT__size_r = VL_RAND_RESET_I(3); + VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cwb_queue__DOT__reading = VL_RAND_RESET_I(1); + VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cwb_queue__DOT__writing = VL_RAND_RESET_I(1); + { int __Vi0=0; for (; __Vi0<4; ++__Vi0) { + VL_RAND_RESET_W(76, VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cwb_queue__DOT__genblk3__DOT__data[__Vi0]); + }} + VL_RAND_RESET_W(76, VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cwb_queue__DOT__genblk3__DOT__genblk2__DOT__head_r); + VL_RAND_RESET_W(76, VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cwb_queue__DOT__genblk3__DOT__genblk2__DOT__curr_r); + VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cwb_queue__DOT__genblk3__DOT__genblk2__DOT__wr_ptr_r = VL_RAND_RESET_I(2); + VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cwb_queue__DOT__genblk3__DOT__genblk2__DOT__rd_ptr_r = VL_RAND_RESET_I(2); + VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cwb_queue__DOT__genblk3__DOT__genblk2__DOT__rd_ptr_next_r = VL_RAND_RESET_I(2); + VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cwb_queue__DOT__genblk3__DOT__genblk2__DOT__empty_r = VL_RAND_RESET_I(1); + VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cwb_queue__DOT__genblk3__DOT__genblk2__DOT__full_r = VL_RAND_RESET_I(1); + VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cwb_queue__DOT__genblk3__DOT__genblk2__DOT__bypass_r = VL_RAND_RESET_I(1); + VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__dwb_queue__DOT__size_r = VL_RAND_RESET_I(3); + VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__dwb_queue__DOT__reading = VL_RAND_RESET_I(1); + VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__dwb_queue__DOT__writing = VL_RAND_RESET_I(1); + { int __Vi0=0; for (; __Vi0<4; ++__Vi0) { + VL_RAND_RESET_W(200, VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__data[__Vi0]); + }} + VL_RAND_RESET_W(200, VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__genblk2__DOT__head_r); + VL_RAND_RESET_W(200, VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__genblk2__DOT__curr_r); + VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__genblk2__DOT__wr_ptr_r = VL_RAND_RESET_I(2); + VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__genblk2__DOT__rd_ptr_r = VL_RAND_RESET_I(2); + VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__genblk2__DOT__rd_ptr_next_r = VL_RAND_RESET_I(2); + VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__genblk2__DOT__empty_r = VL_RAND_RESET_I(1); + VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__genblk2__DOT__full_r = VL_RAND_RESET_I(1); + VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__genblk2__DOT__bypass_r = VL_RAND_RESET_I(1); + VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__snrq_pop = VL_RAND_RESET_I(1); + VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT____Vcellout__snp_req_queue__data_out = VL_RAND_RESET_Q(55); + VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT____Vcellinp__snp_req_queue__data_in = VL_RAND_RESET_Q(55); + VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__dfpq_pop = VL_RAND_RESET_I(1); + VL_RAND_RESET_W(154, VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT____Vcellout__dfp_queue__data_out); + VL_RAND_RESET_W(154, VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT____Vcellinp__dfp_queue__data_in); + VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__reqq_pop = VL_RAND_RESET_I(1); + VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__reqq_req_rw_st0 = VL_RAND_RESET_I(1); + VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__reqq_req_addr_st0 = VL_RAND_RESET_I(30); + VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__mrvq_pop = VL_RAND_RESET_I(1); + VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__mrvq_rw_st0 = VL_RAND_RESET_I(1); + VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__force_request_miss_st1e = VL_RAND_RESET_I(1); + VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__recover_mrvq_state_st2 = VL_RAND_RESET_I(1); + VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__mrvq_push_stall = VL_RAND_RESET_I(1); + VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__cwbq_push_stall = VL_RAND_RESET_I(1); + VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__dwbq_push_stall = VL_RAND_RESET_I(1); + VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__dram_fill_req_stall = VL_RAND_RESET_I(1); + VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__stall_bank_pipe = VL_RAND_RESET_I(1); + VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__is_fill_in_pipe = VL_RAND_RESET_I(1); + { int __Vi0=0; for (; __Vi0<1; ++__Vi0) { + VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__is_fill_st1[__Vi0] = VL_RAND_RESET_I(1); + }} + { int __Vi0=0; for (; __Vi0<1; ++__Vi0) { + VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__going_to_write_st1[__Vi0] = VL_RAND_RESET_I(1); + }} + VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__dfpq_pop_unqual = VL_RAND_RESET_I(1); + VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__reqq_pop_unqual = VL_RAND_RESET_I(1); + VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__snrq_pop_unqual = VL_RAND_RESET_I(1); + { int __Vi0=0; for (; __Vi0<1; ++__Vi0) { + VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__valid_st1[__Vi0] = VL_RAND_RESET_I(1); + }} + { int __Vi0=0; for (; __Vi0<1; ++__Vi0) { + VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__addr_st1[__Vi0] = VL_RAND_RESET_I(26); + }} + { int __Vi0=0; for (; __Vi0<1; ++__Vi0) { + VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__wsel_st1[__Vi0] = VL_RAND_RESET_I(2); + }} + { int __Vi0=0; for (; __Vi0<1; ++__Vi0) { + VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__writeword_st1[__Vi0] = VL_RAND_RESET_I(32); + }} + { int __Vi0=0; for (; __Vi0<1; ++__Vi0) { + VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__inst_meta_st1[__Vi0] = VL_RAND_RESET_Q(49); + }} + { int __Vi0=0; for (; __Vi0<1; ++__Vi0) { + VL_RAND_RESET_W(128, VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__writedata_st1[__Vi0]); + }} + { int __Vi0=0; for (; __Vi0<1; ++__Vi0) { + VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__is_snp_st1[__Vi0] = VL_RAND_RESET_I(1); + }} + { int __Vi0=0; for (; __Vi0<1; ++__Vi0) { + VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__snp_invalidate_st1[__Vi0] = VL_RAND_RESET_I(1); + }} + { int __Vi0=0; for (; __Vi0<1; ++__Vi0) { + VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__is_mrvq_st1[__Vi0] = VL_RAND_RESET_I(1); + }} + VL_RAND_RESET_W(243, VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT____Vcellinp__s0_1_c0__in); + VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__miss_st1e = VL_RAND_RESET_I(1); + VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__dirty_st1e = VL_RAND_RESET_I(1); + VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__snp_to_mrvq_st1e = VL_RAND_RESET_I(1); + VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__miss_add_because_miss = VL_RAND_RESET_I(1); + VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__mrvq_init_ready_state_st2 = VL_RAND_RESET_I(1); + VL_RAND_RESET_W(316, VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT____Vcellinp__st_1e_2__in); + VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__miss_add_unqual = VL_RAND_RESET_I(1); + VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__miss_add = VL_RAND_RESET_I(1); + VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__miss_add_is_mrvq = VL_RAND_RESET_I(1); + VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__cwbq_push_unqual = VL_RAND_RESET_I(1); + VL_RAND_RESET_W(76, VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT____Vcellout__cwb_queue__data_out); + VL_RAND_RESET_W(76, VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT____Vcellinp__cwb_queue__data_in); + VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__dwbq_is_dwb_in = VL_RAND_RESET_I(1); + VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__dwbq_is_snp_in = VL_RAND_RESET_I(1); + VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__dwbq_push_unqual = VL_RAND_RESET_I(1); + VL_RAND_RESET_W(200, VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT____Vcellout__dwb_queue__data_out); + VL_RAND_RESET_W(200, VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT____Vcellinp__dwb_queue__data_in); + VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__dram_wb_req_fire = VL_RAND_RESET_I(1); + VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__snp_rsp_fire = VL_RAND_RESET_I(1); + VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__dwbq_dual_valid_sel = VL_RAND_RESET_I(1); + VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__snp_req_queue__DOT__size_r = VL_RAND_RESET_I(5); + VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__snp_req_queue__DOT__reading = VL_RAND_RESET_I(1); + VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__snp_req_queue__DOT__writing = VL_RAND_RESET_I(1); + { int __Vi0=0; for (; __Vi0<16; ++__Vi0) { + VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__snp_req_queue__DOT__genblk3__DOT__data[__Vi0] = VL_RAND_RESET_Q(55); + }} + VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__snp_req_queue__DOT__genblk3__DOT__genblk2__DOT__head_r = VL_RAND_RESET_Q(55); + VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__snp_req_queue__DOT__genblk3__DOT__genblk2__DOT__curr_r = VL_RAND_RESET_Q(55); + VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__snp_req_queue__DOT__genblk3__DOT__genblk2__DOT__wr_ptr_r = VL_RAND_RESET_I(4); + VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__snp_req_queue__DOT__genblk3__DOT__genblk2__DOT__rd_ptr_r = VL_RAND_RESET_I(4); + VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__snp_req_queue__DOT__genblk3__DOT__genblk2__DOT__rd_ptr_next_r = VL_RAND_RESET_I(4); + VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__snp_req_queue__DOT__genblk3__DOT__genblk2__DOT__empty_r = VL_RAND_RESET_I(1); + VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__snp_req_queue__DOT__genblk3__DOT__genblk2__DOT__full_r = VL_RAND_RESET_I(1); + VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__snp_req_queue__DOT__genblk3__DOT__genblk2__DOT__bypass_r = VL_RAND_RESET_I(1); + VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__dfp_queue__DOT__size_r = VL_RAND_RESET_I(5); + VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__dfp_queue__DOT__reading = VL_RAND_RESET_I(1); + VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__dfp_queue__DOT__writing = VL_RAND_RESET_I(1); + { int __Vi0=0; for (; __Vi0<16; ++__Vi0) { + VL_RAND_RESET_W(154, VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__dfp_queue__DOT__genblk3__DOT__data[__Vi0]); + }} + VL_RAND_RESET_W(154, VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__dfp_queue__DOT__genblk3__DOT__genblk2__DOT__head_r); + VL_RAND_RESET_W(154, VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__dfp_queue__DOT__genblk3__DOT__genblk2__DOT__curr_r); + VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__dfp_queue__DOT__genblk3__DOT__genblk2__DOT__wr_ptr_r = VL_RAND_RESET_I(4); + VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__dfp_queue__DOT__genblk3__DOT__genblk2__DOT__rd_ptr_r = VL_RAND_RESET_I(4); + VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__dfp_queue__DOT__genblk3__DOT__genblk2__DOT__rd_ptr_next_r = VL_RAND_RESET_I(4); + VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__dfp_queue__DOT__genblk3__DOT__genblk2__DOT__empty_r = VL_RAND_RESET_I(1); + VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__dfp_queue__DOT__genblk3__DOT__genblk2__DOT__full_r = VL_RAND_RESET_I(1); + VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__dfp_queue__DOT__genblk3__DOT__genblk2__DOT__bypass_r = VL_RAND_RESET_I(1); + VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__core_req_arb__DOT__use_per_valids = VL_RAND_RESET_I(4); + VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__core_req_arb__DOT__use_per_rw = VL_RAND_RESET_I(4); + VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__core_req_arb__DOT__use_per_byteen = VL_RAND_RESET_I(16); + VL_RAND_RESET_W(120, VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__core_req_arb__DOT__use_per_addr); + VL_RAND_RESET_W(128, VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__core_req_arb__DOT__use_per_writedata); + VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__core_req_arb__DOT__use_per_tag = VL_RAND_RESET_Q(42); + VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__core_req_arb__DOT__out_empty = VL_RAND_RESET_I(1); + VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__core_req_arb__DOT__pop_qual = VL_RAND_RESET_I(1); + VL_RAND_RESET_W(314, VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__core_req_arb__DOT____Vcellout__reqq_queue__data_out); + VL_RAND_RESET_W(314, VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__core_req_arb__DOT____Vcellinp__reqq_queue__data_in); + VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__core_req_arb__DOT__qual_request_index = VL_RAND_RESET_I(2); + VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__core_req_arb__DOT__qual_has_request = VL_RAND_RESET_I(1); + VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__size_r = VL_RAND_RESET_I(3); + VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__reading = VL_RAND_RESET_I(1); + VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__writing = VL_RAND_RESET_I(1); + { int __Vi0=0; for (; __Vi0<4; ++__Vi0) { + VL_RAND_RESET_W(314, VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__data[__Vi0]); + }} + VL_RAND_RESET_W(314, VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__head_r); + VL_RAND_RESET_W(314, VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__curr_r); + VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__wr_ptr_r = VL_RAND_RESET_I(2); + VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__rd_ptr_r = VL_RAND_RESET_I(2); + VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__rd_ptr_next_r = VL_RAND_RESET_I(2); + VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__empty_r = VL_RAND_RESET_I(1); + VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__full_r = VL_RAND_RESET_I(1); + VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__bypass_r = VL_RAND_RESET_I(1); + VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__core_req_arb__DOT__sel_bank__DOT__genblk2__DOT__grant_onehot_r = VL_RAND_RESET_I(4); + VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__core_req_arb__DOT__sel_bank__DOT__genblk2__DOT__priority_encoder__DOT__i = VL_RAND_RESET_I(32); + VL_RAND_RESET_W(243, VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__s0_1_c0__DOT__value); + { int __Vi0=0; for (; __Vi0<1; ++__Vi0) { + VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__tag_data_access__DOT__read_valid_st1c[__Vi0] = VL_RAND_RESET_I(1); + }} + { int __Vi0=0; for (; __Vi0<1; ++__Vi0) { + VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__tag_data_access__DOT__read_dirty_st1c[__Vi0] = VL_RAND_RESET_I(1); + }} + { int __Vi0=0; for (; __Vi0<1; ++__Vi0) { + VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__tag_data_access__DOT__read_dirtyb_st1c[__Vi0] = VL_RAND_RESET_I(16); + }} + { int __Vi0=0; for (; __Vi0<1; ++__Vi0) { + VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__tag_data_access__DOT__read_tag_st1c[__Vi0] = VL_RAND_RESET_I(20); + }} + { int __Vi0=0; for (; __Vi0<1; ++__Vi0) { + VL_RAND_RESET_W(128, VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__tag_data_access__DOT__read_data_st1c[__Vi0]); + }} + VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__tag_data_access__DOT__use_write_enable = VL_RAND_RESET_I(16); + VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__tag_data_access__DOT__tags_match = VL_RAND_RESET_I(1); + VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__tag_data_access__DOT__real_writefill = VL_RAND_RESET_I(1); + VL_RAND_RESET_W(166, VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__tag_data_access__DOT____Vcellinp__s0_1_c0__in); + VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__tag_data_access__DOT__we = VL_RAND_RESET_I(16); + VL_RAND_RESET_W(128, VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__tag_data_access__DOT__data_write); + VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__tag_data_access__DOT__should_write = VL_RAND_RESET_I(1); + VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__tag_data_access__DOT__snoop_hit_no_pending = VL_RAND_RESET_I(1); + VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__tag_data_access__DOT__real_miss = VL_RAND_RESET_I(1); + { int __Vi0=0; for (; __Vi0<64; ++__Vi0) { + VL_RAND_RESET_W(128, VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__data[__Vi0]); + }} + { int __Vi0=0; for (; __Vi0<64; ++__Vi0) { + VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__tag[__Vi0] = VL_RAND_RESET_I(20); + }} + { int __Vi0=0; for (; __Vi0<64; ++__Vi0) { + VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__dirtyb[__Vi0] = VL_RAND_RESET_I(16); + }} + VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__dirty = VL_RAND_RESET_Q(64); + VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__valid = VL_RAND_RESET_Q(64); + VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__i = VL_RAND_RESET_I(32); + VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__j = VL_RAND_RESET_I(32); + VL_RAND_RESET_W(166, VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__tag_data_access__DOT__s0_1_c0__DOT__value); + VL_RAND_RESET_W(316, VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__st_1e_2__DOT__value); + { int __Vi0=0; for (; __Vi0<16; ++__Vi0) { + VL_RAND_RESET_W(85, VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__cache_miss_resrv__DOT__metadata_table[__Vi0]); + }} + VL_RAND_RESET_W(416, VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__cache_miss_resrv__DOT__addr_table); + VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__cache_miss_resrv__DOT__valid_table = VL_RAND_RESET_I(16); + VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__cache_miss_resrv__DOT__ready_table = VL_RAND_RESET_I(16); + VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr = VL_RAND_RESET_I(4); + VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__cache_miss_resrv__DOT__head_ptr = VL_RAND_RESET_I(4); + VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__cache_miss_resrv__DOT__tail_ptr = VL_RAND_RESET_I(4); + VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__cache_miss_resrv__DOT__size = VL_RAND_RESET_I(5); + VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__cache_miss_resrv__DOT__make_ready = VL_RAND_RESET_I(16); + VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__cache_miss_resrv__DOT__valid_address_match = VL_RAND_RESET_I(16); + VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__cache_miss_resrv__DOT__dequeue_possible = VL_RAND_RESET_I(1); + VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__cache_miss_resrv__DOT__mrvq_push = VL_RAND_RESET_I(1); + VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__cache_miss_resrv__DOT__mrvq_pop = VL_RAND_RESET_I(1); + VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__cache_miss_resrv__DOT__increment_head = VL_RAND_RESET_I(1); + VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__cache_miss_resrv__DOT____Vlvbound1 = VL_RAND_RESET_I(26); + VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__cwb_queue__DOT__size_r = VL_RAND_RESET_I(3); + VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__cwb_queue__DOT__reading = VL_RAND_RESET_I(1); + VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__cwb_queue__DOT__writing = VL_RAND_RESET_I(1); + { int __Vi0=0; for (; __Vi0<4; ++__Vi0) { + VL_RAND_RESET_W(76, VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__cwb_queue__DOT__genblk3__DOT__data[__Vi0]); + }} + VL_RAND_RESET_W(76, VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__cwb_queue__DOT__genblk3__DOT__genblk2__DOT__head_r); + VL_RAND_RESET_W(76, VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__cwb_queue__DOT__genblk3__DOT__genblk2__DOT__curr_r); + VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__cwb_queue__DOT__genblk3__DOT__genblk2__DOT__wr_ptr_r = VL_RAND_RESET_I(2); + VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__cwb_queue__DOT__genblk3__DOT__genblk2__DOT__rd_ptr_r = VL_RAND_RESET_I(2); + VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__cwb_queue__DOT__genblk3__DOT__genblk2__DOT__rd_ptr_next_r = VL_RAND_RESET_I(2); + VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__cwb_queue__DOT__genblk3__DOT__genblk2__DOT__empty_r = VL_RAND_RESET_I(1); + VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__cwb_queue__DOT__genblk3__DOT__genblk2__DOT__full_r = VL_RAND_RESET_I(1); + VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__cwb_queue__DOT__genblk3__DOT__genblk2__DOT__bypass_r = VL_RAND_RESET_I(1); + VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__dwb_queue__DOT__size_r = VL_RAND_RESET_I(3); + VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__dwb_queue__DOT__reading = VL_RAND_RESET_I(1); + VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__dwb_queue__DOT__writing = VL_RAND_RESET_I(1); + { int __Vi0=0; for (; __Vi0<4; ++__Vi0) { + VL_RAND_RESET_W(200, VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__data[__Vi0]); + }} + VL_RAND_RESET_W(200, VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__genblk2__DOT__head_r); + VL_RAND_RESET_W(200, VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__genblk2__DOT__curr_r); + VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__genblk2__DOT__wr_ptr_r = VL_RAND_RESET_I(2); + VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__genblk2__DOT__rd_ptr_r = VL_RAND_RESET_I(2); + VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__genblk2__DOT__rd_ptr_next_r = VL_RAND_RESET_I(2); + VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__genblk2__DOT__empty_r = VL_RAND_RESET_I(1); + VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__genblk2__DOT__full_r = VL_RAND_RESET_I(1); + VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__genblk2__DOT__bypass_r = VL_RAND_RESET_I(1); + VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__snrq_pop = VL_RAND_RESET_I(1); + VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT____Vcellout__snp_req_queue__data_out = VL_RAND_RESET_Q(55); + VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT____Vcellinp__snp_req_queue__data_in = VL_RAND_RESET_Q(55); + VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__dfpq_pop = VL_RAND_RESET_I(1); + VL_RAND_RESET_W(154, VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT____Vcellout__dfp_queue__data_out); + VL_RAND_RESET_W(154, VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT____Vcellinp__dfp_queue__data_in); + VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__reqq_pop = VL_RAND_RESET_I(1); + VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__reqq_req_rw_st0 = VL_RAND_RESET_I(1); + VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__reqq_req_addr_st0 = VL_RAND_RESET_I(30); + VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__mrvq_pop = VL_RAND_RESET_I(1); + VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__mrvq_rw_st0 = VL_RAND_RESET_I(1); + VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__force_request_miss_st1e = VL_RAND_RESET_I(1); + VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__recover_mrvq_state_st2 = VL_RAND_RESET_I(1); + VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__mrvq_push_stall = VL_RAND_RESET_I(1); + VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__cwbq_push_stall = VL_RAND_RESET_I(1); + VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__dwbq_push_stall = VL_RAND_RESET_I(1); + VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__dram_fill_req_stall = VL_RAND_RESET_I(1); + VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__stall_bank_pipe = VL_RAND_RESET_I(1); + VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__is_fill_in_pipe = VL_RAND_RESET_I(1); + { int __Vi0=0; for (; __Vi0<1; ++__Vi0) { + VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__is_fill_st1[__Vi0] = VL_RAND_RESET_I(1); + }} + { int __Vi0=0; for (; __Vi0<1; ++__Vi0) { + VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__going_to_write_st1[__Vi0] = VL_RAND_RESET_I(1); + }} + VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__dfpq_pop_unqual = VL_RAND_RESET_I(1); + VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__reqq_pop_unqual = VL_RAND_RESET_I(1); + VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__snrq_pop_unqual = VL_RAND_RESET_I(1); + { int __Vi0=0; for (; __Vi0<1; ++__Vi0) { + VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__valid_st1[__Vi0] = VL_RAND_RESET_I(1); + }} + { int __Vi0=0; for (; __Vi0<1; ++__Vi0) { + VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__addr_st1[__Vi0] = VL_RAND_RESET_I(26); + }} + { int __Vi0=0; for (; __Vi0<1; ++__Vi0) { + VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__wsel_st1[__Vi0] = VL_RAND_RESET_I(2); + }} + { int __Vi0=0; for (; __Vi0<1; ++__Vi0) { + VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__writeword_st1[__Vi0] = VL_RAND_RESET_I(32); + }} + { int __Vi0=0; for (; __Vi0<1; ++__Vi0) { + VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__inst_meta_st1[__Vi0] = VL_RAND_RESET_Q(49); + }} + { int __Vi0=0; for (; __Vi0<1; ++__Vi0) { + VL_RAND_RESET_W(128, VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__writedata_st1[__Vi0]); + }} + { int __Vi0=0; for (; __Vi0<1; ++__Vi0) { + VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__is_snp_st1[__Vi0] = VL_RAND_RESET_I(1); + }} + { int __Vi0=0; for (; __Vi0<1; ++__Vi0) { + VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__snp_invalidate_st1[__Vi0] = VL_RAND_RESET_I(1); + }} + { int __Vi0=0; for (; __Vi0<1; ++__Vi0) { + VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__is_mrvq_st1[__Vi0] = VL_RAND_RESET_I(1); + }} + VL_RAND_RESET_W(243, VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT____Vcellinp__s0_1_c0__in); + VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__miss_st1e = VL_RAND_RESET_I(1); + VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__dirty_st1e = VL_RAND_RESET_I(1); + VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__snp_to_mrvq_st1e = VL_RAND_RESET_I(1); + VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__miss_add_because_miss = VL_RAND_RESET_I(1); + VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__mrvq_init_ready_state_st2 = VL_RAND_RESET_I(1); + VL_RAND_RESET_W(316, VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT____Vcellinp__st_1e_2__in); + VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__miss_add_unqual = VL_RAND_RESET_I(1); + VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__miss_add = VL_RAND_RESET_I(1); + VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__miss_add_is_mrvq = VL_RAND_RESET_I(1); + VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__cwbq_push_unqual = VL_RAND_RESET_I(1); + VL_RAND_RESET_W(76, VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT____Vcellout__cwb_queue__data_out); + VL_RAND_RESET_W(76, VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT____Vcellinp__cwb_queue__data_in); + VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__dwbq_is_dwb_in = VL_RAND_RESET_I(1); + VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__dwbq_is_snp_in = VL_RAND_RESET_I(1); + VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__dwbq_push_unqual = VL_RAND_RESET_I(1); + VL_RAND_RESET_W(200, VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT____Vcellout__dwb_queue__data_out); + VL_RAND_RESET_W(200, VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT____Vcellinp__dwb_queue__data_in); + VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__dram_wb_req_fire = VL_RAND_RESET_I(1); + VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__snp_rsp_fire = VL_RAND_RESET_I(1); + VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__dwbq_dual_valid_sel = VL_RAND_RESET_I(1); + VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__snp_req_queue__DOT__size_r = VL_RAND_RESET_I(5); + VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__snp_req_queue__DOT__reading = VL_RAND_RESET_I(1); + VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__snp_req_queue__DOT__writing = VL_RAND_RESET_I(1); + { int __Vi0=0; for (; __Vi0<16; ++__Vi0) { + VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__snp_req_queue__DOT__genblk3__DOT__data[__Vi0] = VL_RAND_RESET_Q(55); + }} + VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__snp_req_queue__DOT__genblk3__DOT__genblk2__DOT__head_r = VL_RAND_RESET_Q(55); + VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__snp_req_queue__DOT__genblk3__DOT__genblk2__DOT__curr_r = VL_RAND_RESET_Q(55); + VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__snp_req_queue__DOT__genblk3__DOT__genblk2__DOT__wr_ptr_r = VL_RAND_RESET_I(4); + VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__snp_req_queue__DOT__genblk3__DOT__genblk2__DOT__rd_ptr_r = VL_RAND_RESET_I(4); + VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__snp_req_queue__DOT__genblk3__DOT__genblk2__DOT__rd_ptr_next_r = VL_RAND_RESET_I(4); + VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__snp_req_queue__DOT__genblk3__DOT__genblk2__DOT__empty_r = VL_RAND_RESET_I(1); + VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__snp_req_queue__DOT__genblk3__DOT__genblk2__DOT__full_r = VL_RAND_RESET_I(1); + VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__snp_req_queue__DOT__genblk3__DOT__genblk2__DOT__bypass_r = VL_RAND_RESET_I(1); + VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__dfp_queue__DOT__size_r = VL_RAND_RESET_I(5); + VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__dfp_queue__DOT__reading = VL_RAND_RESET_I(1); + VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__dfp_queue__DOT__writing = VL_RAND_RESET_I(1); + { int __Vi0=0; for (; __Vi0<16; ++__Vi0) { + VL_RAND_RESET_W(154, VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__dfp_queue__DOT__genblk3__DOT__data[__Vi0]); + }} + VL_RAND_RESET_W(154, VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__dfp_queue__DOT__genblk3__DOT__genblk2__DOT__head_r); + VL_RAND_RESET_W(154, VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__dfp_queue__DOT__genblk3__DOT__genblk2__DOT__curr_r); + VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__dfp_queue__DOT__genblk3__DOT__genblk2__DOT__wr_ptr_r = VL_RAND_RESET_I(4); + VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__dfp_queue__DOT__genblk3__DOT__genblk2__DOT__rd_ptr_r = VL_RAND_RESET_I(4); + VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__dfp_queue__DOT__genblk3__DOT__genblk2__DOT__rd_ptr_next_r = VL_RAND_RESET_I(4); + VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__dfp_queue__DOT__genblk3__DOT__genblk2__DOT__empty_r = VL_RAND_RESET_I(1); + VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__dfp_queue__DOT__genblk3__DOT__genblk2__DOT__full_r = VL_RAND_RESET_I(1); + VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__dfp_queue__DOT__genblk3__DOT__genblk2__DOT__bypass_r = VL_RAND_RESET_I(1); + VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__core_req_arb__DOT__use_per_valids = VL_RAND_RESET_I(4); + VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__core_req_arb__DOT__use_per_rw = VL_RAND_RESET_I(4); + VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__core_req_arb__DOT__use_per_byteen = VL_RAND_RESET_I(16); + VL_RAND_RESET_W(120, VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__core_req_arb__DOT__use_per_addr); + VL_RAND_RESET_W(128, VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__core_req_arb__DOT__use_per_writedata); + VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__core_req_arb__DOT__use_per_tag = VL_RAND_RESET_Q(42); + VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__core_req_arb__DOT__out_empty = VL_RAND_RESET_I(1); + VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__core_req_arb__DOT__pop_qual = VL_RAND_RESET_I(1); + VL_RAND_RESET_W(314, VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__core_req_arb__DOT____Vcellout__reqq_queue__data_out); + VL_RAND_RESET_W(314, VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__core_req_arb__DOT____Vcellinp__reqq_queue__data_in); + VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__core_req_arb__DOT__qual_request_index = VL_RAND_RESET_I(2); + VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__core_req_arb__DOT__qual_has_request = VL_RAND_RESET_I(1); + VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__size_r = VL_RAND_RESET_I(3); + VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__reading = VL_RAND_RESET_I(1); + VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__writing = VL_RAND_RESET_I(1); + { int __Vi0=0; for (; __Vi0<4; ++__Vi0) { + VL_RAND_RESET_W(314, VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__data[__Vi0]); + }} + VL_RAND_RESET_W(314, VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__head_r); + VL_RAND_RESET_W(314, VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__curr_r); + VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__wr_ptr_r = VL_RAND_RESET_I(2); + VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__rd_ptr_r = VL_RAND_RESET_I(2); + VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__rd_ptr_next_r = VL_RAND_RESET_I(2); + VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__empty_r = VL_RAND_RESET_I(1); + VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__full_r = VL_RAND_RESET_I(1); + VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__bypass_r = VL_RAND_RESET_I(1); + VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__core_req_arb__DOT__sel_bank__DOT__genblk2__DOT__grant_onehot_r = VL_RAND_RESET_I(4); + VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__core_req_arb__DOT__sel_bank__DOT__genblk2__DOT__priority_encoder__DOT__i = VL_RAND_RESET_I(32); + VL_RAND_RESET_W(243, VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__s0_1_c0__DOT__value); + { int __Vi0=0; for (; __Vi0<1; ++__Vi0) { + VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__tag_data_access__DOT__read_valid_st1c[__Vi0] = VL_RAND_RESET_I(1); + }} + { int __Vi0=0; for (; __Vi0<1; ++__Vi0) { + VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__tag_data_access__DOT__read_dirty_st1c[__Vi0] = VL_RAND_RESET_I(1); + }} + { int __Vi0=0; for (; __Vi0<1; ++__Vi0) { + VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__tag_data_access__DOT__read_dirtyb_st1c[__Vi0] = VL_RAND_RESET_I(16); + }} + { int __Vi0=0; for (; __Vi0<1; ++__Vi0) { + VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__tag_data_access__DOT__read_tag_st1c[__Vi0] = VL_RAND_RESET_I(20); + }} + { int __Vi0=0; for (; __Vi0<1; ++__Vi0) { + VL_RAND_RESET_W(128, VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__tag_data_access__DOT__read_data_st1c[__Vi0]); + }} + VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__tag_data_access__DOT__use_write_enable = VL_RAND_RESET_I(16); + VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__tag_data_access__DOT__tags_match = VL_RAND_RESET_I(1); + VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__tag_data_access__DOT__real_writefill = VL_RAND_RESET_I(1); + VL_RAND_RESET_W(166, VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__tag_data_access__DOT____Vcellinp__s0_1_c0__in); + VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__tag_data_access__DOT__we = VL_RAND_RESET_I(16); + VL_RAND_RESET_W(128, VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__tag_data_access__DOT__data_write); + VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__tag_data_access__DOT__should_write = VL_RAND_RESET_I(1); + VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__tag_data_access__DOT__snoop_hit_no_pending = VL_RAND_RESET_I(1); + VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__tag_data_access__DOT__real_miss = VL_RAND_RESET_I(1); + { int __Vi0=0; for (; __Vi0<64; ++__Vi0) { + VL_RAND_RESET_W(128, VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__data[__Vi0]); + }} + { int __Vi0=0; for (; __Vi0<64; ++__Vi0) { + VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__tag[__Vi0] = VL_RAND_RESET_I(20); + }} + { int __Vi0=0; for (; __Vi0<64; ++__Vi0) { + VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__dirtyb[__Vi0] = VL_RAND_RESET_I(16); + }} + VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__dirty = VL_RAND_RESET_Q(64); + VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__valid = VL_RAND_RESET_Q(64); + VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__i = VL_RAND_RESET_I(32); + VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__j = VL_RAND_RESET_I(32); + VL_RAND_RESET_W(166, VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__tag_data_access__DOT__s0_1_c0__DOT__value); + VL_RAND_RESET_W(316, VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__st_1e_2__DOT__value); + { int __Vi0=0; for (; __Vi0<16; ++__Vi0) { + VL_RAND_RESET_W(85, VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__cache_miss_resrv__DOT__metadata_table[__Vi0]); + }} + VL_RAND_RESET_W(416, VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__cache_miss_resrv__DOT__addr_table); + VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__cache_miss_resrv__DOT__valid_table = VL_RAND_RESET_I(16); + VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__cache_miss_resrv__DOT__ready_table = VL_RAND_RESET_I(16); + VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr = VL_RAND_RESET_I(4); + VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__cache_miss_resrv__DOT__head_ptr = VL_RAND_RESET_I(4); + VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__cache_miss_resrv__DOT__tail_ptr = VL_RAND_RESET_I(4); + VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__cache_miss_resrv__DOT__size = VL_RAND_RESET_I(5); + VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__cache_miss_resrv__DOT__make_ready = VL_RAND_RESET_I(16); + VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__cache_miss_resrv__DOT__valid_address_match = VL_RAND_RESET_I(16); + VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__cache_miss_resrv__DOT__dequeue_possible = VL_RAND_RESET_I(1); + VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__cache_miss_resrv__DOT__mrvq_push = VL_RAND_RESET_I(1); + VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__cache_miss_resrv__DOT__mrvq_pop = VL_RAND_RESET_I(1); + VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__cache_miss_resrv__DOT__increment_head = VL_RAND_RESET_I(1); + VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__cache_miss_resrv__DOT____Vlvbound1 = VL_RAND_RESET_I(26); + VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__cwb_queue__DOT__size_r = VL_RAND_RESET_I(3); + VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__cwb_queue__DOT__reading = VL_RAND_RESET_I(1); + VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__cwb_queue__DOT__writing = VL_RAND_RESET_I(1); + { int __Vi0=0; for (; __Vi0<4; ++__Vi0) { + VL_RAND_RESET_W(76, VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__cwb_queue__DOT__genblk3__DOT__data[__Vi0]); + }} + VL_RAND_RESET_W(76, VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__cwb_queue__DOT__genblk3__DOT__genblk2__DOT__head_r); + VL_RAND_RESET_W(76, VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__cwb_queue__DOT__genblk3__DOT__genblk2__DOT__curr_r); + VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__cwb_queue__DOT__genblk3__DOT__genblk2__DOT__wr_ptr_r = VL_RAND_RESET_I(2); + VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__cwb_queue__DOT__genblk3__DOT__genblk2__DOT__rd_ptr_r = VL_RAND_RESET_I(2); + VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__cwb_queue__DOT__genblk3__DOT__genblk2__DOT__rd_ptr_next_r = VL_RAND_RESET_I(2); + VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__cwb_queue__DOT__genblk3__DOT__genblk2__DOT__empty_r = VL_RAND_RESET_I(1); + VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__cwb_queue__DOT__genblk3__DOT__genblk2__DOT__full_r = VL_RAND_RESET_I(1); + VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__cwb_queue__DOT__genblk3__DOT__genblk2__DOT__bypass_r = VL_RAND_RESET_I(1); + VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__dwb_queue__DOT__size_r = VL_RAND_RESET_I(3); + VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__dwb_queue__DOT__reading = VL_RAND_RESET_I(1); + VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__dwb_queue__DOT__writing = VL_RAND_RESET_I(1); + { int __Vi0=0; for (; __Vi0<4; ++__Vi0) { + VL_RAND_RESET_W(200, VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__data[__Vi0]); + }} + VL_RAND_RESET_W(200, VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__genblk2__DOT__head_r); + VL_RAND_RESET_W(200, VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__genblk2__DOT__curr_r); + VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__genblk2__DOT__wr_ptr_r = VL_RAND_RESET_I(2); + VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__genblk2__DOT__rd_ptr_r = VL_RAND_RESET_I(2); + VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__genblk2__DOT__rd_ptr_next_r = VL_RAND_RESET_I(2); + VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__genblk2__DOT__empty_r = VL_RAND_RESET_I(1); + VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__genblk2__DOT__full_r = VL_RAND_RESET_I(1); + VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__genblk2__DOT__bypass_r = VL_RAND_RESET_I(1); + VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__snrq_pop = VL_RAND_RESET_I(1); + VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT____Vcellout__snp_req_queue__data_out = VL_RAND_RESET_Q(55); + VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT____Vcellinp__snp_req_queue__data_in = VL_RAND_RESET_Q(55); + VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__dfpq_pop = VL_RAND_RESET_I(1); + VL_RAND_RESET_W(154, VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT____Vcellout__dfp_queue__data_out); + VL_RAND_RESET_W(154, VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT____Vcellinp__dfp_queue__data_in); + VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__reqq_pop = VL_RAND_RESET_I(1); + VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__reqq_req_rw_st0 = VL_RAND_RESET_I(1); + VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__reqq_req_addr_st0 = VL_RAND_RESET_I(30); + VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__mrvq_pop = VL_RAND_RESET_I(1); + VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__mrvq_rw_st0 = VL_RAND_RESET_I(1); + VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__force_request_miss_st1e = VL_RAND_RESET_I(1); + VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__recover_mrvq_state_st2 = VL_RAND_RESET_I(1); + VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__mrvq_push_stall = VL_RAND_RESET_I(1); + VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cwbq_push_stall = VL_RAND_RESET_I(1); + VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__dwbq_push_stall = VL_RAND_RESET_I(1); + VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__dram_fill_req_stall = VL_RAND_RESET_I(1); + VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__stall_bank_pipe = VL_RAND_RESET_I(1); + VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__is_fill_in_pipe = VL_RAND_RESET_I(1); + { int __Vi0=0; for (; __Vi0<1; ++__Vi0) { + VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__is_fill_st1[__Vi0] = VL_RAND_RESET_I(1); + }} + { int __Vi0=0; for (; __Vi0<1; ++__Vi0) { + VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__going_to_write_st1[__Vi0] = VL_RAND_RESET_I(1); + }} + VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__dfpq_pop_unqual = VL_RAND_RESET_I(1); + VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__reqq_pop_unqual = VL_RAND_RESET_I(1); + VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__snrq_pop_unqual = VL_RAND_RESET_I(1); + { int __Vi0=0; for (; __Vi0<1; ++__Vi0) { + VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__valid_st1[__Vi0] = VL_RAND_RESET_I(1); + }} + { int __Vi0=0; for (; __Vi0<1; ++__Vi0) { + VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__addr_st1[__Vi0] = VL_RAND_RESET_I(26); + }} + { int __Vi0=0; for (; __Vi0<1; ++__Vi0) { + VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__wsel_st1[__Vi0] = VL_RAND_RESET_I(2); + }} + { int __Vi0=0; for (; __Vi0<1; ++__Vi0) { + VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__writeword_st1[__Vi0] = VL_RAND_RESET_I(32); + }} + { int __Vi0=0; for (; __Vi0<1; ++__Vi0) { + VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__inst_meta_st1[__Vi0] = VL_RAND_RESET_Q(49); + }} + { int __Vi0=0; for (; __Vi0<1; ++__Vi0) { + VL_RAND_RESET_W(128, VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__writedata_st1[__Vi0]); + }} + { int __Vi0=0; for (; __Vi0<1; ++__Vi0) { + VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__is_snp_st1[__Vi0] = VL_RAND_RESET_I(1); + }} + { int __Vi0=0; for (; __Vi0<1; ++__Vi0) { + VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__snp_invalidate_st1[__Vi0] = VL_RAND_RESET_I(1); + }} + { int __Vi0=0; for (; __Vi0<1; ++__Vi0) { + VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__is_mrvq_st1[__Vi0] = VL_RAND_RESET_I(1); + }} + VL_RAND_RESET_W(243, VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT____Vcellinp__s0_1_c0__in); + VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__miss_st1e = VL_RAND_RESET_I(1); + VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__dirty_st1e = VL_RAND_RESET_I(1); + VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__snp_to_mrvq_st1e = VL_RAND_RESET_I(1); + VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__miss_add_because_miss = VL_RAND_RESET_I(1); + VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__mrvq_init_ready_state_st2 = VL_RAND_RESET_I(1); + VL_RAND_RESET_W(316, VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT____Vcellinp__st_1e_2__in); + VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__miss_add_unqual = VL_RAND_RESET_I(1); + VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__miss_add = VL_RAND_RESET_I(1); + VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__miss_add_is_mrvq = VL_RAND_RESET_I(1); + VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cwbq_push_unqual = VL_RAND_RESET_I(1); + VL_RAND_RESET_W(76, VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT____Vcellout__cwb_queue__data_out); + VL_RAND_RESET_W(76, VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT____Vcellinp__cwb_queue__data_in); + VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__dwbq_is_dwb_in = VL_RAND_RESET_I(1); + VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__dwbq_is_snp_in = VL_RAND_RESET_I(1); + VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__dwbq_push_unqual = VL_RAND_RESET_I(1); + VL_RAND_RESET_W(200, VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT____Vcellout__dwb_queue__data_out); + VL_RAND_RESET_W(200, VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT____Vcellinp__dwb_queue__data_in); + VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__dram_wb_req_fire = VL_RAND_RESET_I(1); + VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__snp_rsp_fire = VL_RAND_RESET_I(1); + VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__dwbq_dual_valid_sel = VL_RAND_RESET_I(1); + VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__snp_req_queue__DOT__size_r = VL_RAND_RESET_I(5); + VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__snp_req_queue__DOT__reading = VL_RAND_RESET_I(1); + VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__snp_req_queue__DOT__writing = VL_RAND_RESET_I(1); + { int __Vi0=0; for (; __Vi0<16; ++__Vi0) { + VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__snp_req_queue__DOT__genblk3__DOT__data[__Vi0] = VL_RAND_RESET_Q(55); + }} + VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__snp_req_queue__DOT__genblk3__DOT__genblk2__DOT__head_r = VL_RAND_RESET_Q(55); + VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__snp_req_queue__DOT__genblk3__DOT__genblk2__DOT__curr_r = VL_RAND_RESET_Q(55); + VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__snp_req_queue__DOT__genblk3__DOT__genblk2__DOT__wr_ptr_r = VL_RAND_RESET_I(4); + VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__snp_req_queue__DOT__genblk3__DOT__genblk2__DOT__rd_ptr_r = VL_RAND_RESET_I(4); + VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__snp_req_queue__DOT__genblk3__DOT__genblk2__DOT__rd_ptr_next_r = VL_RAND_RESET_I(4); + VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__snp_req_queue__DOT__genblk3__DOT__genblk2__DOT__empty_r = VL_RAND_RESET_I(1); + VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__snp_req_queue__DOT__genblk3__DOT__genblk2__DOT__full_r = VL_RAND_RESET_I(1); + VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__snp_req_queue__DOT__genblk3__DOT__genblk2__DOT__bypass_r = VL_RAND_RESET_I(1); + VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__dfp_queue__DOT__size_r = VL_RAND_RESET_I(5); + VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__dfp_queue__DOT__reading = VL_RAND_RESET_I(1); + VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__dfp_queue__DOT__writing = VL_RAND_RESET_I(1); + { int __Vi0=0; for (; __Vi0<16; ++__Vi0) { + VL_RAND_RESET_W(154, VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__dfp_queue__DOT__genblk3__DOT__data[__Vi0]); + }} + VL_RAND_RESET_W(154, VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__dfp_queue__DOT__genblk3__DOT__genblk2__DOT__head_r); + VL_RAND_RESET_W(154, VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__dfp_queue__DOT__genblk3__DOT__genblk2__DOT__curr_r); + VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__dfp_queue__DOT__genblk3__DOT__genblk2__DOT__wr_ptr_r = VL_RAND_RESET_I(4); + VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__dfp_queue__DOT__genblk3__DOT__genblk2__DOT__rd_ptr_r = VL_RAND_RESET_I(4); + VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__dfp_queue__DOT__genblk3__DOT__genblk2__DOT__rd_ptr_next_r = VL_RAND_RESET_I(4); + VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__dfp_queue__DOT__genblk3__DOT__genblk2__DOT__empty_r = VL_RAND_RESET_I(1); + VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__dfp_queue__DOT__genblk3__DOT__genblk2__DOT__full_r = VL_RAND_RESET_I(1); + VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__dfp_queue__DOT__genblk3__DOT__genblk2__DOT__bypass_r = VL_RAND_RESET_I(1); + VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__core_req_arb__DOT__use_per_valids = VL_RAND_RESET_I(4); + VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__core_req_arb__DOT__use_per_rw = VL_RAND_RESET_I(4); + VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__core_req_arb__DOT__use_per_byteen = VL_RAND_RESET_I(16); + VL_RAND_RESET_W(120, VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__core_req_arb__DOT__use_per_addr); + VL_RAND_RESET_W(128, VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__core_req_arb__DOT__use_per_writedata); + VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__core_req_arb__DOT__use_per_tag = VL_RAND_RESET_Q(42); + VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__core_req_arb__DOT__out_empty = VL_RAND_RESET_I(1); + VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__core_req_arb__DOT__pop_qual = VL_RAND_RESET_I(1); + VL_RAND_RESET_W(314, VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__core_req_arb__DOT____Vcellout__reqq_queue__data_out); + VL_RAND_RESET_W(314, VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__core_req_arb__DOT____Vcellinp__reqq_queue__data_in); + VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__core_req_arb__DOT__qual_request_index = VL_RAND_RESET_I(2); + VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__core_req_arb__DOT__qual_has_request = VL_RAND_RESET_I(1); + VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__size_r = VL_RAND_RESET_I(3); + VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__reading = VL_RAND_RESET_I(1); + VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__writing = VL_RAND_RESET_I(1); + { int __Vi0=0; for (; __Vi0<4; ++__Vi0) { + VL_RAND_RESET_W(314, VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__data[__Vi0]); + }} + VL_RAND_RESET_W(314, VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__head_r); + VL_RAND_RESET_W(314, VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__curr_r); + VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__wr_ptr_r = VL_RAND_RESET_I(2); + VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__rd_ptr_r = VL_RAND_RESET_I(2); + VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__rd_ptr_next_r = VL_RAND_RESET_I(2); + VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__empty_r = VL_RAND_RESET_I(1); + VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__full_r = VL_RAND_RESET_I(1); + VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__bypass_r = VL_RAND_RESET_I(1); + VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__core_req_arb__DOT__sel_bank__DOT__genblk2__DOT__grant_onehot_r = VL_RAND_RESET_I(4); + VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__core_req_arb__DOT__sel_bank__DOT__genblk2__DOT__priority_encoder__DOT__i = VL_RAND_RESET_I(32); + VL_RAND_RESET_W(243, VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__s0_1_c0__DOT__value); + { int __Vi0=0; for (; __Vi0<1; ++__Vi0) { + VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__tag_data_access__DOT__read_valid_st1c[__Vi0] = VL_RAND_RESET_I(1); + }} + { int __Vi0=0; for (; __Vi0<1; ++__Vi0) { + VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__tag_data_access__DOT__read_dirty_st1c[__Vi0] = VL_RAND_RESET_I(1); + }} + { int __Vi0=0; for (; __Vi0<1; ++__Vi0) { + VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__tag_data_access__DOT__read_dirtyb_st1c[__Vi0] = VL_RAND_RESET_I(16); + }} + { int __Vi0=0; for (; __Vi0<1; ++__Vi0) { + VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__tag_data_access__DOT__read_tag_st1c[__Vi0] = VL_RAND_RESET_I(20); + }} + { int __Vi0=0; for (; __Vi0<1; ++__Vi0) { + VL_RAND_RESET_W(128, VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__tag_data_access__DOT__read_data_st1c[__Vi0]); + }} + VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__tag_data_access__DOT__use_write_enable = VL_RAND_RESET_I(16); + VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__tag_data_access__DOT__tags_match = VL_RAND_RESET_I(1); + VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__tag_data_access__DOT__real_writefill = VL_RAND_RESET_I(1); + VL_RAND_RESET_W(166, VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__tag_data_access__DOT____Vcellinp__s0_1_c0__in); + VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__tag_data_access__DOT__we = VL_RAND_RESET_I(16); + VL_RAND_RESET_W(128, VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__tag_data_access__DOT__data_write); + VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__tag_data_access__DOT__should_write = VL_RAND_RESET_I(1); + VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__tag_data_access__DOT__snoop_hit_no_pending = VL_RAND_RESET_I(1); + VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__tag_data_access__DOT__real_miss = VL_RAND_RESET_I(1); + { int __Vi0=0; for (; __Vi0<64; ++__Vi0) { + VL_RAND_RESET_W(128, VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__data[__Vi0]); + }} + { int __Vi0=0; for (; __Vi0<64; ++__Vi0) { + VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__tag[__Vi0] = VL_RAND_RESET_I(20); + }} + { int __Vi0=0; for (; __Vi0<64; ++__Vi0) { + VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__dirtyb[__Vi0] = VL_RAND_RESET_I(16); + }} + VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__dirty = VL_RAND_RESET_Q(64); + VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__valid = VL_RAND_RESET_Q(64); + VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__i = VL_RAND_RESET_I(32); + VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__j = VL_RAND_RESET_I(32); + VL_RAND_RESET_W(166, VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__tag_data_access__DOT__s0_1_c0__DOT__value); + VL_RAND_RESET_W(316, VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__st_1e_2__DOT__value); + { int __Vi0=0; for (; __Vi0<16; ++__Vi0) { + VL_RAND_RESET_W(85, VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cache_miss_resrv__DOT__metadata_table[__Vi0]); + }} + VL_RAND_RESET_W(416, VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cache_miss_resrv__DOT__addr_table); + VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cache_miss_resrv__DOT__valid_table = VL_RAND_RESET_I(16); + VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cache_miss_resrv__DOT__ready_table = VL_RAND_RESET_I(16); + VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr = VL_RAND_RESET_I(4); + VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cache_miss_resrv__DOT__head_ptr = VL_RAND_RESET_I(4); + VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cache_miss_resrv__DOT__tail_ptr = VL_RAND_RESET_I(4); + VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cache_miss_resrv__DOT__size = VL_RAND_RESET_I(5); + VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cache_miss_resrv__DOT__make_ready = VL_RAND_RESET_I(16); + VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cache_miss_resrv__DOT__valid_address_match = VL_RAND_RESET_I(16); + VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cache_miss_resrv__DOT__dequeue_possible = VL_RAND_RESET_I(1); + VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cache_miss_resrv__DOT__mrvq_push = VL_RAND_RESET_I(1); + VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cache_miss_resrv__DOT__mrvq_pop = VL_RAND_RESET_I(1); + VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cache_miss_resrv__DOT__increment_head = VL_RAND_RESET_I(1); + VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cache_miss_resrv__DOT____Vlvbound1 = VL_RAND_RESET_I(26); + VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cwb_queue__DOT__size_r = VL_RAND_RESET_I(3); + VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cwb_queue__DOT__reading = VL_RAND_RESET_I(1); + VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cwb_queue__DOT__writing = VL_RAND_RESET_I(1); + { int __Vi0=0; for (; __Vi0<4; ++__Vi0) { + VL_RAND_RESET_W(76, VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cwb_queue__DOT__genblk3__DOT__data[__Vi0]); + }} + VL_RAND_RESET_W(76, VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cwb_queue__DOT__genblk3__DOT__genblk2__DOT__head_r); + VL_RAND_RESET_W(76, VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cwb_queue__DOT__genblk3__DOT__genblk2__DOT__curr_r); + VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cwb_queue__DOT__genblk3__DOT__genblk2__DOT__wr_ptr_r = VL_RAND_RESET_I(2); + VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cwb_queue__DOT__genblk3__DOT__genblk2__DOT__rd_ptr_r = VL_RAND_RESET_I(2); + VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cwb_queue__DOT__genblk3__DOT__genblk2__DOT__rd_ptr_next_r = VL_RAND_RESET_I(2); + VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cwb_queue__DOT__genblk3__DOT__genblk2__DOT__empty_r = VL_RAND_RESET_I(1); + VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cwb_queue__DOT__genblk3__DOT__genblk2__DOT__full_r = VL_RAND_RESET_I(1); + VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cwb_queue__DOT__genblk3__DOT__genblk2__DOT__bypass_r = VL_RAND_RESET_I(1); + VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__dwb_queue__DOT__size_r = VL_RAND_RESET_I(3); + VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__dwb_queue__DOT__reading = VL_RAND_RESET_I(1); + VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__dwb_queue__DOT__writing = VL_RAND_RESET_I(1); + { int __Vi0=0; for (; __Vi0<4; ++__Vi0) { + VL_RAND_RESET_W(200, VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__data[__Vi0]); + }} + VL_RAND_RESET_W(200, VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__genblk2__DOT__head_r); + VL_RAND_RESET_W(200, VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__genblk2__DOT__curr_r); + VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__genblk2__DOT__wr_ptr_r = VL_RAND_RESET_I(2); + VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__genblk2__DOT__rd_ptr_r = VL_RAND_RESET_I(2); + VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__genblk2__DOT__rd_ptr_next_r = VL_RAND_RESET_I(2); + VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__genblk2__DOT__empty_r = VL_RAND_RESET_I(1); + VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__genblk2__DOT__full_r = VL_RAND_RESET_I(1); + VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__genblk2__DOT__bypass_r = VL_RAND_RESET_I(1); + __Vtableidx1 = 0; + __Vtable1_VX_cache__DOT__cache_dram_req_arb__DOT__dram_fill_arb__DOT__qual_request_index[0] = 0U; + __Vtable1_VX_cache__DOT__cache_dram_req_arb__DOT__dram_fill_arb__DOT__qual_request_index[1] = 0U; + __Vtable1_VX_cache__DOT__cache_dram_req_arb__DOT__dram_fill_arb__DOT__qual_request_index[2] = 1U; + __Vtable1_VX_cache__DOT__cache_dram_req_arb__DOT__dram_fill_arb__DOT__qual_request_index[3] = 0U; + __Vtable1_VX_cache__DOT__cache_dram_req_arb__DOT__dram_fill_arb__DOT__qual_request_index[4] = 2U; + __Vtable1_VX_cache__DOT__cache_dram_req_arb__DOT__dram_fill_arb__DOT__qual_request_index[5] = 0U; + __Vtable1_VX_cache__DOT__cache_dram_req_arb__DOT__dram_fill_arb__DOT__qual_request_index[6] = 1U; + __Vtable1_VX_cache__DOT__cache_dram_req_arb__DOT__dram_fill_arb__DOT__qual_request_index[7] = 0U; + __Vtable1_VX_cache__DOT__cache_dram_req_arb__DOT__dram_fill_arb__DOT__qual_request_index[8] = 3U; + __Vtable1_VX_cache__DOT__cache_dram_req_arb__DOT__dram_fill_arb__DOT__qual_request_index[9] = 0U; + __Vtable1_VX_cache__DOT__cache_dram_req_arb__DOT__dram_fill_arb__DOT__qual_request_index[10] = 1U; + __Vtable1_VX_cache__DOT__cache_dram_req_arb__DOT__dram_fill_arb__DOT__qual_request_index[11] = 0U; + __Vtable1_VX_cache__DOT__cache_dram_req_arb__DOT__dram_fill_arb__DOT__qual_request_index[12] = 2U; + __Vtable1_VX_cache__DOT__cache_dram_req_arb__DOT__dram_fill_arb__DOT__qual_request_index[13] = 0U; + __Vtable1_VX_cache__DOT__cache_dram_req_arb__DOT__dram_fill_arb__DOT__qual_request_index[14] = 1U; + __Vtable1_VX_cache__DOT__cache_dram_req_arb__DOT__dram_fill_arb__DOT__qual_request_index[15] = 0U; + __Vtable1_VX_cache__DOT__cache_dram_req_arb__DOT__dram_fill_arb__DOT__qual_has_request[0] = 0U; + __Vtable1_VX_cache__DOT__cache_dram_req_arb__DOT__dram_fill_arb__DOT__qual_has_request[1] = 1U; + __Vtable1_VX_cache__DOT__cache_dram_req_arb__DOT__dram_fill_arb__DOT__qual_has_request[2] = 1U; + __Vtable1_VX_cache__DOT__cache_dram_req_arb__DOT__dram_fill_arb__DOT__qual_has_request[3] = 1U; + __Vtable1_VX_cache__DOT__cache_dram_req_arb__DOT__dram_fill_arb__DOT__qual_has_request[4] = 1U; + __Vtable1_VX_cache__DOT__cache_dram_req_arb__DOT__dram_fill_arb__DOT__qual_has_request[5] = 1U; + __Vtable1_VX_cache__DOT__cache_dram_req_arb__DOT__dram_fill_arb__DOT__qual_has_request[6] = 1U; + __Vtable1_VX_cache__DOT__cache_dram_req_arb__DOT__dram_fill_arb__DOT__qual_has_request[7] = 1U; + __Vtable1_VX_cache__DOT__cache_dram_req_arb__DOT__dram_fill_arb__DOT__qual_has_request[8] = 1U; + __Vtable1_VX_cache__DOT__cache_dram_req_arb__DOT__dram_fill_arb__DOT__qual_has_request[9] = 1U; + __Vtable1_VX_cache__DOT__cache_dram_req_arb__DOT__dram_fill_arb__DOT__qual_has_request[10] = 1U; + __Vtable1_VX_cache__DOT__cache_dram_req_arb__DOT__dram_fill_arb__DOT__qual_has_request[11] = 1U; + __Vtable1_VX_cache__DOT__cache_dram_req_arb__DOT__dram_fill_arb__DOT__qual_has_request[12] = 1U; + __Vtable1_VX_cache__DOT__cache_dram_req_arb__DOT__dram_fill_arb__DOT__qual_has_request[13] = 1U; + __Vtable1_VX_cache__DOT__cache_dram_req_arb__DOT__dram_fill_arb__DOT__qual_has_request[14] = 1U; + __Vtable1_VX_cache__DOT__cache_dram_req_arb__DOT__dram_fill_arb__DOT__qual_has_request[15] = 1U; + __Vtable1_VX_cache__DOT__cache_dram_req_arb__DOT__dram_fill_arb__DOT__sel_bank__DOT__genblk2__DOT__priority_encoder__DOT__i[0] = 0xffffffffU; + __Vtable1_VX_cache__DOT__cache_dram_req_arb__DOT__dram_fill_arb__DOT__sel_bank__DOT__genblk2__DOT__priority_encoder__DOT__i[1] = 0xffffffffU; + __Vtable1_VX_cache__DOT__cache_dram_req_arb__DOT__dram_fill_arb__DOT__sel_bank__DOT__genblk2__DOT__priority_encoder__DOT__i[2] = 0xffffffffU; + __Vtable1_VX_cache__DOT__cache_dram_req_arb__DOT__dram_fill_arb__DOT__sel_bank__DOT__genblk2__DOT__priority_encoder__DOT__i[3] = 0xffffffffU; + __Vtable1_VX_cache__DOT__cache_dram_req_arb__DOT__dram_fill_arb__DOT__sel_bank__DOT__genblk2__DOT__priority_encoder__DOT__i[4] = 0xffffffffU; + __Vtable1_VX_cache__DOT__cache_dram_req_arb__DOT__dram_fill_arb__DOT__sel_bank__DOT__genblk2__DOT__priority_encoder__DOT__i[5] = 0xffffffffU; + __Vtable1_VX_cache__DOT__cache_dram_req_arb__DOT__dram_fill_arb__DOT__sel_bank__DOT__genblk2__DOT__priority_encoder__DOT__i[6] = 0xffffffffU; + __Vtable1_VX_cache__DOT__cache_dram_req_arb__DOT__dram_fill_arb__DOT__sel_bank__DOT__genblk2__DOT__priority_encoder__DOT__i[7] = 0xffffffffU; + __Vtable1_VX_cache__DOT__cache_dram_req_arb__DOT__dram_fill_arb__DOT__sel_bank__DOT__genblk2__DOT__priority_encoder__DOT__i[8] = 0xffffffffU; + __Vtable1_VX_cache__DOT__cache_dram_req_arb__DOT__dram_fill_arb__DOT__sel_bank__DOT__genblk2__DOT__priority_encoder__DOT__i[9] = 0xffffffffU; + __Vtable1_VX_cache__DOT__cache_dram_req_arb__DOT__dram_fill_arb__DOT__sel_bank__DOT__genblk2__DOT__priority_encoder__DOT__i[10] = 0xffffffffU; + __Vtable1_VX_cache__DOT__cache_dram_req_arb__DOT__dram_fill_arb__DOT__sel_bank__DOT__genblk2__DOT__priority_encoder__DOT__i[11] = 0xffffffffU; + __Vtable1_VX_cache__DOT__cache_dram_req_arb__DOT__dram_fill_arb__DOT__sel_bank__DOT__genblk2__DOT__priority_encoder__DOT__i[12] = 0xffffffffU; + __Vtable1_VX_cache__DOT__cache_dram_req_arb__DOT__dram_fill_arb__DOT__sel_bank__DOT__genblk2__DOT__priority_encoder__DOT__i[13] = 0xffffffffU; + __Vtable1_VX_cache__DOT__cache_dram_req_arb__DOT__dram_fill_arb__DOT__sel_bank__DOT__genblk2__DOT__priority_encoder__DOT__i[14] = 0xffffffffU; + __Vtable1_VX_cache__DOT__cache_dram_req_arb__DOT__dram_fill_arb__DOT__sel_bank__DOT__genblk2__DOT__priority_encoder__DOT__i[15] = 0xffffffffU; + __Vtableidx2 = 0; + __Vtable2_VX_cache__DOT__cache_dram_req_arb__DOT__dwb_bank[0] = 0U; + __Vtable2_VX_cache__DOT__cache_dram_req_arb__DOT__dwb_bank[1] = 0U; + __Vtable2_VX_cache__DOT__cache_dram_req_arb__DOT__dwb_bank[2] = 1U; + __Vtable2_VX_cache__DOT__cache_dram_req_arb__DOT__dwb_bank[3] = 0U; + __Vtable2_VX_cache__DOT__cache_dram_req_arb__DOT__dwb_bank[4] = 2U; + __Vtable2_VX_cache__DOT__cache_dram_req_arb__DOT__dwb_bank[5] = 0U; + __Vtable2_VX_cache__DOT__cache_dram_req_arb__DOT__dwb_bank[6] = 1U; + __Vtable2_VX_cache__DOT__cache_dram_req_arb__DOT__dwb_bank[7] = 0U; + __Vtable2_VX_cache__DOT__cache_dram_req_arb__DOT__dwb_bank[8] = 3U; + __Vtable2_VX_cache__DOT__cache_dram_req_arb__DOT__dwb_bank[9] = 0U; + __Vtable2_VX_cache__DOT__cache_dram_req_arb__DOT__dwb_bank[10] = 1U; + __Vtable2_VX_cache__DOT__cache_dram_req_arb__DOT__dwb_bank[11] = 0U; + __Vtable2_VX_cache__DOT__cache_dram_req_arb__DOT__dwb_bank[12] = 2U; + __Vtable2_VX_cache__DOT__cache_dram_req_arb__DOT__dwb_bank[13] = 0U; + __Vtable2_VX_cache__DOT__cache_dram_req_arb__DOT__dwb_bank[14] = 1U; + __Vtable2_VX_cache__DOT__cache_dram_req_arb__DOT__dwb_bank[15] = 0U; + __Vtable2_VX_cache__DOT__cache_dram_req_arb__DOT__dwb_valid[0] = 0U; + __Vtable2_VX_cache__DOT__cache_dram_req_arb__DOT__dwb_valid[1] = 1U; + __Vtable2_VX_cache__DOT__cache_dram_req_arb__DOT__dwb_valid[2] = 1U; + __Vtable2_VX_cache__DOT__cache_dram_req_arb__DOT__dwb_valid[3] = 1U; + __Vtable2_VX_cache__DOT__cache_dram_req_arb__DOT__dwb_valid[4] = 1U; + __Vtable2_VX_cache__DOT__cache_dram_req_arb__DOT__dwb_valid[5] = 1U; + __Vtable2_VX_cache__DOT__cache_dram_req_arb__DOT__dwb_valid[6] = 1U; + __Vtable2_VX_cache__DOT__cache_dram_req_arb__DOT__dwb_valid[7] = 1U; + __Vtable2_VX_cache__DOT__cache_dram_req_arb__DOT__dwb_valid[8] = 1U; + __Vtable2_VX_cache__DOT__cache_dram_req_arb__DOT__dwb_valid[9] = 1U; + __Vtable2_VX_cache__DOT__cache_dram_req_arb__DOT__dwb_valid[10] = 1U; + __Vtable2_VX_cache__DOT__cache_dram_req_arb__DOT__dwb_valid[11] = 1U; + __Vtable2_VX_cache__DOT__cache_dram_req_arb__DOT__dwb_valid[12] = 1U; + __Vtable2_VX_cache__DOT__cache_dram_req_arb__DOT__dwb_valid[13] = 1U; + __Vtable2_VX_cache__DOT__cache_dram_req_arb__DOT__dwb_valid[14] = 1U; + __Vtable2_VX_cache__DOT__cache_dram_req_arb__DOT__dwb_valid[15] = 1U; + __Vtable2_VX_cache__DOT__cache_dram_req_arb__DOT__sel_dwb__DOT__genblk2__DOT__priority_encoder__DOT__i[0] = 0xffffffffU; + __Vtable2_VX_cache__DOT__cache_dram_req_arb__DOT__sel_dwb__DOT__genblk2__DOT__priority_encoder__DOT__i[1] = 0xffffffffU; + __Vtable2_VX_cache__DOT__cache_dram_req_arb__DOT__sel_dwb__DOT__genblk2__DOT__priority_encoder__DOT__i[2] = 0xffffffffU; + __Vtable2_VX_cache__DOT__cache_dram_req_arb__DOT__sel_dwb__DOT__genblk2__DOT__priority_encoder__DOT__i[3] = 0xffffffffU; + __Vtable2_VX_cache__DOT__cache_dram_req_arb__DOT__sel_dwb__DOT__genblk2__DOT__priority_encoder__DOT__i[4] = 0xffffffffU; + __Vtable2_VX_cache__DOT__cache_dram_req_arb__DOT__sel_dwb__DOT__genblk2__DOT__priority_encoder__DOT__i[5] = 0xffffffffU; + __Vtable2_VX_cache__DOT__cache_dram_req_arb__DOT__sel_dwb__DOT__genblk2__DOT__priority_encoder__DOT__i[6] = 0xffffffffU; + __Vtable2_VX_cache__DOT__cache_dram_req_arb__DOT__sel_dwb__DOT__genblk2__DOT__priority_encoder__DOT__i[7] = 0xffffffffU; + __Vtable2_VX_cache__DOT__cache_dram_req_arb__DOT__sel_dwb__DOT__genblk2__DOT__priority_encoder__DOT__i[8] = 0xffffffffU; + __Vtable2_VX_cache__DOT__cache_dram_req_arb__DOT__sel_dwb__DOT__genblk2__DOT__priority_encoder__DOT__i[9] = 0xffffffffU; + __Vtable2_VX_cache__DOT__cache_dram_req_arb__DOT__sel_dwb__DOT__genblk2__DOT__priority_encoder__DOT__i[10] = 0xffffffffU; + __Vtable2_VX_cache__DOT__cache_dram_req_arb__DOT__sel_dwb__DOT__genblk2__DOT__priority_encoder__DOT__i[11] = 0xffffffffU; + __Vtable2_VX_cache__DOT__cache_dram_req_arb__DOT__sel_dwb__DOT__genblk2__DOT__priority_encoder__DOT__i[12] = 0xffffffffU; + __Vtable2_VX_cache__DOT__cache_dram_req_arb__DOT__sel_dwb__DOT__genblk2__DOT__priority_encoder__DOT__i[13] = 0xffffffffU; + __Vtable2_VX_cache__DOT__cache_dram_req_arb__DOT__sel_dwb__DOT__genblk2__DOT__priority_encoder__DOT__i[14] = 0xffffffffU; + __Vtable2_VX_cache__DOT__cache_dram_req_arb__DOT__sel_dwb__DOT__genblk2__DOT__priority_encoder__DOT__i[15] = 0xffffffffU; + __Vtableidx3 = 0; + __Vtable3_VX_cache__DOT__cache_core_rsp_merge__DOT__main_bank_index[0] = 0U; + __Vtable3_VX_cache__DOT__cache_core_rsp_merge__DOT__main_bank_index[1] = 0U; + __Vtable3_VX_cache__DOT__cache_core_rsp_merge__DOT__main_bank_index[2] = 1U; + __Vtable3_VX_cache__DOT__cache_core_rsp_merge__DOT__main_bank_index[3] = 0U; + __Vtable3_VX_cache__DOT__cache_core_rsp_merge__DOT__main_bank_index[4] = 2U; + __Vtable3_VX_cache__DOT__cache_core_rsp_merge__DOT__main_bank_index[5] = 0U; + __Vtable3_VX_cache__DOT__cache_core_rsp_merge__DOT__main_bank_index[6] = 1U; + __Vtable3_VX_cache__DOT__cache_core_rsp_merge__DOT__main_bank_index[7] = 0U; + __Vtable3_VX_cache__DOT__cache_core_rsp_merge__DOT__main_bank_index[8] = 3U; + __Vtable3_VX_cache__DOT__cache_core_rsp_merge__DOT__main_bank_index[9] = 0U; + __Vtable3_VX_cache__DOT__cache_core_rsp_merge__DOT__main_bank_index[10] = 1U; + __Vtable3_VX_cache__DOT__cache_core_rsp_merge__DOT__main_bank_index[11] = 0U; + __Vtable3_VX_cache__DOT__cache_core_rsp_merge__DOT__main_bank_index[12] = 2U; + __Vtable3_VX_cache__DOT__cache_core_rsp_merge__DOT__main_bank_index[13] = 0U; + __Vtable3_VX_cache__DOT__cache_core_rsp_merge__DOT__main_bank_index[14] = 1U; + __Vtable3_VX_cache__DOT__cache_core_rsp_merge__DOT__main_bank_index[15] = 0U; + __Vtable3_VX_cache__DOT__cache_core_rsp_merge__DOT__sel_bank__DOT__grant_valid[0] = 0U; + __Vtable3_VX_cache__DOT__cache_core_rsp_merge__DOT__sel_bank__DOT__grant_valid[1] = 1U; + __Vtable3_VX_cache__DOT__cache_core_rsp_merge__DOT__sel_bank__DOT__grant_valid[2] = 1U; + __Vtable3_VX_cache__DOT__cache_core_rsp_merge__DOT__sel_bank__DOT__grant_valid[3] = 1U; + __Vtable3_VX_cache__DOT__cache_core_rsp_merge__DOT__sel_bank__DOT__grant_valid[4] = 1U; + __Vtable3_VX_cache__DOT__cache_core_rsp_merge__DOT__sel_bank__DOT__grant_valid[5] = 1U; + __Vtable3_VX_cache__DOT__cache_core_rsp_merge__DOT__sel_bank__DOT__grant_valid[6] = 1U; + __Vtable3_VX_cache__DOT__cache_core_rsp_merge__DOT__sel_bank__DOT__grant_valid[7] = 1U; + __Vtable3_VX_cache__DOT__cache_core_rsp_merge__DOT__sel_bank__DOT__grant_valid[8] = 1U; + __Vtable3_VX_cache__DOT__cache_core_rsp_merge__DOT__sel_bank__DOT__grant_valid[9] = 1U; + __Vtable3_VX_cache__DOT__cache_core_rsp_merge__DOT__sel_bank__DOT__grant_valid[10] = 1U; + __Vtable3_VX_cache__DOT__cache_core_rsp_merge__DOT__sel_bank__DOT__grant_valid[11] = 1U; + __Vtable3_VX_cache__DOT__cache_core_rsp_merge__DOT__sel_bank__DOT__grant_valid[12] = 1U; + __Vtable3_VX_cache__DOT__cache_core_rsp_merge__DOT__sel_bank__DOT__grant_valid[13] = 1U; + __Vtable3_VX_cache__DOT__cache_core_rsp_merge__DOT__sel_bank__DOT__grant_valid[14] = 1U; + __Vtable3_VX_cache__DOT__cache_core_rsp_merge__DOT__sel_bank__DOT__grant_valid[15] = 1U; + __Vtable3_VX_cache__DOT__cache_core_rsp_merge__DOT__sel_bank__DOT__genblk2__DOT__priority_encoder__DOT__i[0] = 0xffffffffU; + __Vtable3_VX_cache__DOT__cache_core_rsp_merge__DOT__sel_bank__DOT__genblk2__DOT__priority_encoder__DOT__i[1] = 0xffffffffU; + __Vtable3_VX_cache__DOT__cache_core_rsp_merge__DOT__sel_bank__DOT__genblk2__DOT__priority_encoder__DOT__i[2] = 0xffffffffU; + __Vtable3_VX_cache__DOT__cache_core_rsp_merge__DOT__sel_bank__DOT__genblk2__DOT__priority_encoder__DOT__i[3] = 0xffffffffU; + __Vtable3_VX_cache__DOT__cache_core_rsp_merge__DOT__sel_bank__DOT__genblk2__DOT__priority_encoder__DOT__i[4] = 0xffffffffU; + __Vtable3_VX_cache__DOT__cache_core_rsp_merge__DOT__sel_bank__DOT__genblk2__DOT__priority_encoder__DOT__i[5] = 0xffffffffU; + __Vtable3_VX_cache__DOT__cache_core_rsp_merge__DOT__sel_bank__DOT__genblk2__DOT__priority_encoder__DOT__i[6] = 0xffffffffU; + __Vtable3_VX_cache__DOT__cache_core_rsp_merge__DOT__sel_bank__DOT__genblk2__DOT__priority_encoder__DOT__i[7] = 0xffffffffU; + __Vtable3_VX_cache__DOT__cache_core_rsp_merge__DOT__sel_bank__DOT__genblk2__DOT__priority_encoder__DOT__i[8] = 0xffffffffU; + __Vtable3_VX_cache__DOT__cache_core_rsp_merge__DOT__sel_bank__DOT__genblk2__DOT__priority_encoder__DOT__i[9] = 0xffffffffU; + __Vtable3_VX_cache__DOT__cache_core_rsp_merge__DOT__sel_bank__DOT__genblk2__DOT__priority_encoder__DOT__i[10] = 0xffffffffU; + __Vtable3_VX_cache__DOT__cache_core_rsp_merge__DOT__sel_bank__DOT__genblk2__DOT__priority_encoder__DOT__i[11] = 0xffffffffU; + __Vtable3_VX_cache__DOT__cache_core_rsp_merge__DOT__sel_bank__DOT__genblk2__DOT__priority_encoder__DOT__i[12] = 0xffffffffU; + __Vtable3_VX_cache__DOT__cache_core_rsp_merge__DOT__sel_bank__DOT__genblk2__DOT__priority_encoder__DOT__i[13] = 0xffffffffU; + __Vtable3_VX_cache__DOT__cache_core_rsp_merge__DOT__sel_bank__DOT__genblk2__DOT__priority_encoder__DOT__i[14] = 0xffffffffU; + __Vtable3_VX_cache__DOT__cache_core_rsp_merge__DOT__sel_bank__DOT__genblk2__DOT__priority_encoder__DOT__i[15] = 0xffffffffU; + __Vtableidx4 = 0; + __Vtable4_VX_cache__DOT__snp_rsp_arb__DOT__fsq_bank[0] = 0U; + __Vtable4_VX_cache__DOT__snp_rsp_arb__DOT__fsq_bank[1] = 0U; + __Vtable4_VX_cache__DOT__snp_rsp_arb__DOT__fsq_bank[2] = 1U; + __Vtable4_VX_cache__DOT__snp_rsp_arb__DOT__fsq_bank[3] = 0U; + __Vtable4_VX_cache__DOT__snp_rsp_arb__DOT__fsq_bank[4] = 2U; + __Vtable4_VX_cache__DOT__snp_rsp_arb__DOT__fsq_bank[5] = 0U; + __Vtable4_VX_cache__DOT__snp_rsp_arb__DOT__fsq_bank[6] = 1U; + __Vtable4_VX_cache__DOT__snp_rsp_arb__DOT__fsq_bank[7] = 0U; + __Vtable4_VX_cache__DOT__snp_rsp_arb__DOT__fsq_bank[8] = 3U; + __Vtable4_VX_cache__DOT__snp_rsp_arb__DOT__fsq_bank[9] = 0U; + __Vtable4_VX_cache__DOT__snp_rsp_arb__DOT__fsq_bank[10] = 1U; + __Vtable4_VX_cache__DOT__snp_rsp_arb__DOT__fsq_bank[11] = 0U; + __Vtable4_VX_cache__DOT__snp_rsp_arb__DOT__fsq_bank[12] = 2U; + __Vtable4_VX_cache__DOT__snp_rsp_arb__DOT__fsq_bank[13] = 0U; + __Vtable4_VX_cache__DOT__snp_rsp_arb__DOT__fsq_bank[14] = 1U; + __Vtable4_VX_cache__DOT__snp_rsp_arb__DOT__fsq_bank[15] = 0U; + __Vtable4_VX_cache__DOT__snp_rsp_arb__DOT__fsq_valid[0] = 0U; + __Vtable4_VX_cache__DOT__snp_rsp_arb__DOT__fsq_valid[1] = 1U; + __Vtable4_VX_cache__DOT__snp_rsp_arb__DOT__fsq_valid[2] = 1U; + __Vtable4_VX_cache__DOT__snp_rsp_arb__DOT__fsq_valid[3] = 1U; + __Vtable4_VX_cache__DOT__snp_rsp_arb__DOT__fsq_valid[4] = 1U; + __Vtable4_VX_cache__DOT__snp_rsp_arb__DOT__fsq_valid[5] = 1U; + __Vtable4_VX_cache__DOT__snp_rsp_arb__DOT__fsq_valid[6] = 1U; + __Vtable4_VX_cache__DOT__snp_rsp_arb__DOT__fsq_valid[7] = 1U; + __Vtable4_VX_cache__DOT__snp_rsp_arb__DOT__fsq_valid[8] = 1U; + __Vtable4_VX_cache__DOT__snp_rsp_arb__DOT__fsq_valid[9] = 1U; + __Vtable4_VX_cache__DOT__snp_rsp_arb__DOT__fsq_valid[10] = 1U; + __Vtable4_VX_cache__DOT__snp_rsp_arb__DOT__fsq_valid[11] = 1U; + __Vtable4_VX_cache__DOT__snp_rsp_arb__DOT__fsq_valid[12] = 1U; + __Vtable4_VX_cache__DOT__snp_rsp_arb__DOT__fsq_valid[13] = 1U; + __Vtable4_VX_cache__DOT__snp_rsp_arb__DOT__fsq_valid[14] = 1U; + __Vtable4_VX_cache__DOT__snp_rsp_arb__DOT__fsq_valid[15] = 1U; + __Vtable4_VX_cache__DOT__snp_rsp_arb__DOT__sel_ffsq__DOT__genblk2__DOT__priority_encoder__DOT__i[0] = 0xffffffffU; + __Vtable4_VX_cache__DOT__snp_rsp_arb__DOT__sel_ffsq__DOT__genblk2__DOT__priority_encoder__DOT__i[1] = 0xffffffffU; + __Vtable4_VX_cache__DOT__snp_rsp_arb__DOT__sel_ffsq__DOT__genblk2__DOT__priority_encoder__DOT__i[2] = 0xffffffffU; + __Vtable4_VX_cache__DOT__snp_rsp_arb__DOT__sel_ffsq__DOT__genblk2__DOT__priority_encoder__DOT__i[3] = 0xffffffffU; + __Vtable4_VX_cache__DOT__snp_rsp_arb__DOT__sel_ffsq__DOT__genblk2__DOT__priority_encoder__DOT__i[4] = 0xffffffffU; + __Vtable4_VX_cache__DOT__snp_rsp_arb__DOT__sel_ffsq__DOT__genblk2__DOT__priority_encoder__DOT__i[5] = 0xffffffffU; + __Vtable4_VX_cache__DOT__snp_rsp_arb__DOT__sel_ffsq__DOT__genblk2__DOT__priority_encoder__DOT__i[6] = 0xffffffffU; + __Vtable4_VX_cache__DOT__snp_rsp_arb__DOT__sel_ffsq__DOT__genblk2__DOT__priority_encoder__DOT__i[7] = 0xffffffffU; + __Vtable4_VX_cache__DOT__snp_rsp_arb__DOT__sel_ffsq__DOT__genblk2__DOT__priority_encoder__DOT__i[8] = 0xffffffffU; + __Vtable4_VX_cache__DOT__snp_rsp_arb__DOT__sel_ffsq__DOT__genblk2__DOT__priority_encoder__DOT__i[9] = 0xffffffffU; + __Vtable4_VX_cache__DOT__snp_rsp_arb__DOT__sel_ffsq__DOT__genblk2__DOT__priority_encoder__DOT__i[10] = 0xffffffffU; + __Vtable4_VX_cache__DOT__snp_rsp_arb__DOT__sel_ffsq__DOT__genblk2__DOT__priority_encoder__DOT__i[11] = 0xffffffffU; + __Vtable4_VX_cache__DOT__snp_rsp_arb__DOT__sel_ffsq__DOT__genblk2__DOT__priority_encoder__DOT__i[12] = 0xffffffffU; + __Vtable4_VX_cache__DOT__snp_rsp_arb__DOT__sel_ffsq__DOT__genblk2__DOT__priority_encoder__DOT__i[13] = 0xffffffffU; + __Vtable4_VX_cache__DOT__snp_rsp_arb__DOT__sel_ffsq__DOT__genblk2__DOT__priority_encoder__DOT__i[14] = 0xffffffffU; + __Vtable4_VX_cache__DOT__snp_rsp_arb__DOT__sel_ffsq__DOT__genblk2__DOT__priority_encoder__DOT__i[15] = 0xffffffffU; + __Vtableidx5 = 0; + __Vtable5_VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__core_req_arb__DOT__qual_request_index[0] = 0U; + __Vtable5_VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__core_req_arb__DOT__qual_request_index[1] = 0U; + __Vtable5_VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__core_req_arb__DOT__qual_request_index[2] = 1U; + __Vtable5_VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__core_req_arb__DOT__qual_request_index[3] = 0U; + __Vtable5_VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__core_req_arb__DOT__qual_request_index[4] = 2U; + __Vtable5_VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__core_req_arb__DOT__qual_request_index[5] = 0U; + __Vtable5_VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__core_req_arb__DOT__qual_request_index[6] = 1U; + __Vtable5_VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__core_req_arb__DOT__qual_request_index[7] = 0U; + __Vtable5_VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__core_req_arb__DOT__qual_request_index[8] = 3U; + __Vtable5_VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__core_req_arb__DOT__qual_request_index[9] = 0U; + __Vtable5_VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__core_req_arb__DOT__qual_request_index[10] = 1U; + __Vtable5_VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__core_req_arb__DOT__qual_request_index[11] = 0U; + __Vtable5_VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__core_req_arb__DOT__qual_request_index[12] = 2U; + __Vtable5_VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__core_req_arb__DOT__qual_request_index[13] = 0U; + __Vtable5_VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__core_req_arb__DOT__qual_request_index[14] = 1U; + __Vtable5_VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__core_req_arb__DOT__qual_request_index[15] = 0U; + __Vtable5_VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__core_req_arb__DOT__qual_has_request[0] = 0U; + __Vtable5_VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__core_req_arb__DOT__qual_has_request[1] = 1U; + __Vtable5_VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__core_req_arb__DOT__qual_has_request[2] = 1U; + __Vtable5_VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__core_req_arb__DOT__qual_has_request[3] = 1U; + __Vtable5_VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__core_req_arb__DOT__qual_has_request[4] = 1U; + __Vtable5_VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__core_req_arb__DOT__qual_has_request[5] = 1U; + __Vtable5_VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__core_req_arb__DOT__qual_has_request[6] = 1U; + __Vtable5_VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__core_req_arb__DOT__qual_has_request[7] = 1U; + __Vtable5_VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__core_req_arb__DOT__qual_has_request[8] = 1U; + __Vtable5_VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__core_req_arb__DOT__qual_has_request[9] = 1U; + __Vtable5_VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__core_req_arb__DOT__qual_has_request[10] = 1U; + __Vtable5_VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__core_req_arb__DOT__qual_has_request[11] = 1U; + __Vtable5_VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__core_req_arb__DOT__qual_has_request[12] = 1U; + __Vtable5_VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__core_req_arb__DOT__qual_has_request[13] = 1U; + __Vtable5_VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__core_req_arb__DOT__qual_has_request[14] = 1U; + __Vtable5_VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__core_req_arb__DOT__qual_has_request[15] = 1U; + __Vtable5_VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__core_req_arb__DOT__sel_bank__DOT__genblk2__DOT__priority_encoder__DOT__i[0] = 0xffffffffU; + __Vtable5_VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__core_req_arb__DOT__sel_bank__DOT__genblk2__DOT__priority_encoder__DOT__i[1] = 0xffffffffU; + __Vtable5_VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__core_req_arb__DOT__sel_bank__DOT__genblk2__DOT__priority_encoder__DOT__i[2] = 0xffffffffU; + __Vtable5_VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__core_req_arb__DOT__sel_bank__DOT__genblk2__DOT__priority_encoder__DOT__i[3] = 0xffffffffU; + __Vtable5_VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__core_req_arb__DOT__sel_bank__DOT__genblk2__DOT__priority_encoder__DOT__i[4] = 0xffffffffU; + __Vtable5_VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__core_req_arb__DOT__sel_bank__DOT__genblk2__DOT__priority_encoder__DOT__i[5] = 0xffffffffU; + __Vtable5_VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__core_req_arb__DOT__sel_bank__DOT__genblk2__DOT__priority_encoder__DOT__i[6] = 0xffffffffU; + __Vtable5_VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__core_req_arb__DOT__sel_bank__DOT__genblk2__DOT__priority_encoder__DOT__i[7] = 0xffffffffU; + __Vtable5_VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__core_req_arb__DOT__sel_bank__DOT__genblk2__DOT__priority_encoder__DOT__i[8] = 0xffffffffU; + __Vtable5_VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__core_req_arb__DOT__sel_bank__DOT__genblk2__DOT__priority_encoder__DOT__i[9] = 0xffffffffU; + __Vtable5_VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__core_req_arb__DOT__sel_bank__DOT__genblk2__DOT__priority_encoder__DOT__i[10] = 0xffffffffU; + __Vtable5_VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__core_req_arb__DOT__sel_bank__DOT__genblk2__DOT__priority_encoder__DOT__i[11] = 0xffffffffU; + __Vtable5_VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__core_req_arb__DOT__sel_bank__DOT__genblk2__DOT__priority_encoder__DOT__i[12] = 0xffffffffU; + __Vtable5_VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__core_req_arb__DOT__sel_bank__DOT__genblk2__DOT__priority_encoder__DOT__i[13] = 0xffffffffU; + __Vtable5_VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__core_req_arb__DOT__sel_bank__DOT__genblk2__DOT__priority_encoder__DOT__i[14] = 0xffffffffU; + __Vtable5_VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__core_req_arb__DOT__sel_bank__DOT__genblk2__DOT__priority_encoder__DOT__i[15] = 0xffffffffU; + __Vtableidx6 = 0; + __Vtable6_VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__core_req_arb__DOT__qual_request_index[0] = 0U; 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+ __Vtable6_VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__core_req_arb__DOT__qual_has_request[12] = 1U; + __Vtable6_VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__core_req_arb__DOT__qual_has_request[13] = 1U; + __Vtable6_VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__core_req_arb__DOT__qual_has_request[14] = 1U; + __Vtable6_VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__core_req_arb__DOT__qual_has_request[15] = 1U; + __Vtable6_VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__core_req_arb__DOT__sel_bank__DOT__genblk2__DOT__priority_encoder__DOT__i[0] = 0xffffffffU; + __Vtable6_VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__core_req_arb__DOT__sel_bank__DOT__genblk2__DOT__priority_encoder__DOT__i[1] = 0xffffffffU; + __Vtable6_VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__core_req_arb__DOT__sel_bank__DOT__genblk2__DOT__priority_encoder__DOT__i[2] = 0xffffffffU; + __Vtable6_VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__core_req_arb__DOT__sel_bank__DOT__genblk2__DOT__priority_encoder__DOT__i[3] = 0xffffffffU; + __Vtable6_VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__core_req_arb__DOT__sel_bank__DOT__genblk2__DOT__priority_encoder__DOT__i[4] = 0xffffffffU; + __Vtable6_VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__core_req_arb__DOT__sel_bank__DOT__genblk2__DOT__priority_encoder__DOT__i[5] = 0xffffffffU; + __Vtable6_VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__core_req_arb__DOT__sel_bank__DOT__genblk2__DOT__priority_encoder__DOT__i[6] = 0xffffffffU; + __Vtable6_VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__core_req_arb__DOT__sel_bank__DOT__genblk2__DOT__priority_encoder__DOT__i[7] = 0xffffffffU; + __Vtable6_VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__core_req_arb__DOT__sel_bank__DOT__genblk2__DOT__priority_encoder__DOT__i[8] = 0xffffffffU; + __Vtable6_VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__core_req_arb__DOT__sel_bank__DOT__genblk2__DOT__priority_encoder__DOT__i[9] = 0xffffffffU; + __Vtable6_VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__core_req_arb__DOT__sel_bank__DOT__genblk2__DOT__priority_encoder__DOT__i[10] = 0xffffffffU; + __Vtable6_VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__core_req_arb__DOT__sel_bank__DOT__genblk2__DOT__priority_encoder__DOT__i[11] = 0xffffffffU; + __Vtable6_VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__core_req_arb__DOT__sel_bank__DOT__genblk2__DOT__priority_encoder__DOT__i[12] = 0xffffffffU; + __Vtable6_VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__core_req_arb__DOT__sel_bank__DOT__genblk2__DOT__priority_encoder__DOT__i[13] = 0xffffffffU; + __Vtable6_VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__core_req_arb__DOT__sel_bank__DOT__genblk2__DOT__priority_encoder__DOT__i[14] = 0xffffffffU; + __Vtable6_VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__core_req_arb__DOT__sel_bank__DOT__genblk2__DOT__priority_encoder__DOT__i[15] = 0xffffffffU; + __Vtableidx7 = 0; + __Vtable7_VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__core_req_arb__DOT__qual_request_index[0] = 0U; + __Vtable7_VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__core_req_arb__DOT__qual_request_index[1] = 0U; + __Vtable7_VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__core_req_arb__DOT__qual_request_index[2] = 1U; + __Vtable7_VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__core_req_arb__DOT__qual_request_index[3] = 0U; + __Vtable7_VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__core_req_arb__DOT__qual_request_index[4] = 2U; + __Vtable7_VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__core_req_arb__DOT__qual_request_index[5] = 0U; + __Vtable7_VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__core_req_arb__DOT__qual_request_index[6] = 1U; + __Vtable7_VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__core_req_arb__DOT__qual_request_index[7] = 0U; + __Vtable7_VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__core_req_arb__DOT__qual_request_index[8] = 3U; + __Vtable7_VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__core_req_arb__DOT__qual_request_index[9] = 0U; + __Vtable7_VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__core_req_arb__DOT__qual_request_index[10] = 1U; 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+ __Vtable7_VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__core_req_arb__DOT__qual_has_request[4] = 1U; + __Vtable7_VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__core_req_arb__DOT__qual_has_request[5] = 1U; + __Vtable7_VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__core_req_arb__DOT__qual_has_request[6] = 1U; + __Vtable7_VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__core_req_arb__DOT__qual_has_request[7] = 1U; + __Vtable7_VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__core_req_arb__DOT__qual_has_request[8] = 1U; + __Vtable7_VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__core_req_arb__DOT__qual_has_request[9] = 1U; + __Vtable7_VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__core_req_arb__DOT__qual_has_request[10] = 1U; + __Vtable7_VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__core_req_arb__DOT__qual_has_request[11] = 1U; + __Vtable7_VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__core_req_arb__DOT__qual_has_request[12] = 1U; + __Vtable7_VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__core_req_arb__DOT__qual_has_request[13] = 1U; + __Vtable7_VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__core_req_arb__DOT__qual_has_request[14] = 1U; + __Vtable7_VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__core_req_arb__DOT__qual_has_request[15] = 1U; + __Vtable7_VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__core_req_arb__DOT__sel_bank__DOT__genblk2__DOT__priority_encoder__DOT__i[0] = 0xffffffffU; + __Vtable7_VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__core_req_arb__DOT__sel_bank__DOT__genblk2__DOT__priority_encoder__DOT__i[1] = 0xffffffffU; + __Vtable7_VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__core_req_arb__DOT__sel_bank__DOT__genblk2__DOT__priority_encoder__DOT__i[2] = 0xffffffffU; + __Vtable7_VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__core_req_arb__DOT__sel_bank__DOT__genblk2__DOT__priority_encoder__DOT__i[3] = 0xffffffffU; + __Vtable7_VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__core_req_arb__DOT__sel_bank__DOT__genblk2__DOT__priority_encoder__DOT__i[4] = 0xffffffffU; + __Vtable7_VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__core_req_arb__DOT__sel_bank__DOT__genblk2__DOT__priority_encoder__DOT__i[5] = 0xffffffffU; + __Vtable7_VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__core_req_arb__DOT__sel_bank__DOT__genblk2__DOT__priority_encoder__DOT__i[6] = 0xffffffffU; + __Vtable7_VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__core_req_arb__DOT__sel_bank__DOT__genblk2__DOT__priority_encoder__DOT__i[7] = 0xffffffffU; + __Vtable7_VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__core_req_arb__DOT__sel_bank__DOT__genblk2__DOT__priority_encoder__DOT__i[8] = 0xffffffffU; + __Vtable7_VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__core_req_arb__DOT__sel_bank__DOT__genblk2__DOT__priority_encoder__DOT__i[9] = 0xffffffffU; + __Vtable7_VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__core_req_arb__DOT__sel_bank__DOT__genblk2__DOT__priority_encoder__DOT__i[10] = 0xffffffffU; + __Vtable7_VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__core_req_arb__DOT__sel_bank__DOT__genblk2__DOT__priority_encoder__DOT__i[11] = 0xffffffffU; + __Vtable7_VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__core_req_arb__DOT__sel_bank__DOT__genblk2__DOT__priority_encoder__DOT__i[12] = 0xffffffffU; + __Vtable7_VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__core_req_arb__DOT__sel_bank__DOT__genblk2__DOT__priority_encoder__DOT__i[13] = 0xffffffffU; + __Vtable7_VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__core_req_arb__DOT__sel_bank__DOT__genblk2__DOT__priority_encoder__DOT__i[14] = 0xffffffffU; + __Vtable7_VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__core_req_arb__DOT__sel_bank__DOT__genblk2__DOT__priority_encoder__DOT__i[15] = 0xffffffffU; + __Vtableidx8 = 0; + __Vtable8_VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__core_req_arb__DOT__qual_request_index[0] = 0U; + __Vtable8_VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__core_req_arb__DOT__qual_request_index[1] = 0U; + __Vtable8_VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__core_req_arb__DOT__qual_request_index[2] = 1U; + __Vtable8_VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__core_req_arb__DOT__qual_request_index[3] = 0U; + __Vtable8_VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__core_req_arb__DOT__qual_request_index[4] = 2U; + __Vtable8_VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__core_req_arb__DOT__qual_request_index[5] = 0U; + __Vtable8_VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__core_req_arb__DOT__qual_request_index[6] = 1U; + __Vtable8_VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__core_req_arb__DOT__qual_request_index[7] = 0U; + __Vtable8_VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__core_req_arb__DOT__qual_request_index[8] = 3U; + __Vtable8_VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__core_req_arb__DOT__qual_request_index[9] = 0U; + __Vtable8_VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__core_req_arb__DOT__qual_request_index[10] = 1U; + __Vtable8_VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__core_req_arb__DOT__qual_request_index[11] = 0U; + __Vtable8_VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__core_req_arb__DOT__qual_request_index[12] = 2U; + __Vtable8_VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__core_req_arb__DOT__qual_request_index[13] = 0U; + __Vtable8_VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__core_req_arb__DOT__qual_request_index[14] = 1U; + __Vtable8_VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__core_req_arb__DOT__qual_request_index[15] = 0U; + __Vtable8_VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__core_req_arb__DOT__qual_has_request[0] = 0U; + __Vtable8_VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__core_req_arb__DOT__qual_has_request[1] = 1U; + __Vtable8_VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__core_req_arb__DOT__qual_has_request[2] = 1U; + __Vtable8_VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__core_req_arb__DOT__qual_has_request[3] = 1U; + __Vtable8_VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__core_req_arb__DOT__qual_has_request[4] = 1U; + __Vtable8_VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__core_req_arb__DOT__qual_has_request[5] = 1U; + __Vtable8_VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__core_req_arb__DOT__qual_has_request[6] = 1U; + __Vtable8_VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__core_req_arb__DOT__qual_has_request[7] = 1U; + __Vtable8_VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__core_req_arb__DOT__qual_has_request[8] = 1U; + __Vtable8_VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__core_req_arb__DOT__qual_has_request[9] = 1U; + __Vtable8_VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__core_req_arb__DOT__qual_has_request[10] = 1U; + __Vtable8_VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__core_req_arb__DOT__qual_has_request[11] = 1U; + __Vtable8_VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__core_req_arb__DOT__qual_has_request[12] = 1U; + __Vtable8_VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__core_req_arb__DOT__qual_has_request[13] = 1U; + __Vtable8_VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__core_req_arb__DOT__qual_has_request[14] = 1U; + __Vtable8_VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__core_req_arb__DOT__qual_has_request[15] = 1U; + __Vtable8_VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__core_req_arb__DOT__sel_bank__DOT__genblk2__DOT__priority_encoder__DOT__i[0] = 0xffffffffU; + __Vtable8_VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__core_req_arb__DOT__sel_bank__DOT__genblk2__DOT__priority_encoder__DOT__i[1] = 0xffffffffU; + __Vtable8_VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__core_req_arb__DOT__sel_bank__DOT__genblk2__DOT__priority_encoder__DOT__i[2] = 0xffffffffU; + __Vtable8_VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__core_req_arb__DOT__sel_bank__DOT__genblk2__DOT__priority_encoder__DOT__i[3] = 0xffffffffU; + __Vtable8_VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__core_req_arb__DOT__sel_bank__DOT__genblk2__DOT__priority_encoder__DOT__i[4] = 0xffffffffU; + __Vtable8_VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__core_req_arb__DOT__sel_bank__DOT__genblk2__DOT__priority_encoder__DOT__i[5] = 0xffffffffU; + __Vtable8_VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__core_req_arb__DOT__sel_bank__DOT__genblk2__DOT__priority_encoder__DOT__i[6] = 0xffffffffU; + __Vtable8_VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__core_req_arb__DOT__sel_bank__DOT__genblk2__DOT__priority_encoder__DOT__i[7] = 0xffffffffU; + __Vtable8_VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__core_req_arb__DOT__sel_bank__DOT__genblk2__DOT__priority_encoder__DOT__i[8] = 0xffffffffU; + __Vtable8_VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__core_req_arb__DOT__sel_bank__DOT__genblk2__DOT__priority_encoder__DOT__i[9] = 0xffffffffU; + __Vtable8_VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__core_req_arb__DOT__sel_bank__DOT__genblk2__DOT__priority_encoder__DOT__i[10] = 0xffffffffU; + __Vtable8_VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__core_req_arb__DOT__sel_bank__DOT__genblk2__DOT__priority_encoder__DOT__i[11] = 0xffffffffU; + __Vtable8_VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__core_req_arb__DOT__sel_bank__DOT__genblk2__DOT__priority_encoder__DOT__i[12] = 0xffffffffU; + __Vtable8_VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__core_req_arb__DOT__sel_bank__DOT__genblk2__DOT__priority_encoder__DOT__i[13] = 0xffffffffU; + __Vtable8_VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__core_req_arb__DOT__sel_bank__DOT__genblk2__DOT__priority_encoder__DOT__i[14] = 0xffffffffU; + __Vtable8_VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__core_req_arb__DOT__sel_bank__DOT__genblk2__DOT__priority_encoder__DOT__i[15] = 0xffffffffU; + __Vm_traceActivity = 0; +} diff --git a/hw/unit_tests/cache/obj_dir/VVX_cache.h b/hw/unit_tests/cache/obj_dir/VVX_cache.h new file mode 100644 index 00000000..78b800c1 --- /dev/null +++ b/hw/unit_tests/cache/obj_dir/VVX_cache.h @@ -0,0 +1,955 @@ +// Verilated -*- C++ -*- +// DESCRIPTION: Verilator output: Primary design header +// +// This header should be included by all source files instantiating the design. +// The class here is then constructed to instantiate the design. +// See the Verilator manual for examples. + +#ifndef _VVX_CACHE_H_ +#define _VVX_CACHE_H_ // guard + +#include "verilated_heavy.h" + +//========== + +class VVX_cache__Syms; +class VVX_cache_VerilatedVcd; + + +//---------- + +VL_MODULE(VVX_cache) { + public: + + // PORTS + // The application code writes and reads these signals to + // propagate new values into/out from the Verilated model. + VL_IN8(clk,0,0); + VL_IN8(reset,0,0); + VL_IN8(core_req_valid,3,0); + VL_IN8(core_req_rw,3,0); + VL_IN16(core_req_byteen,15,0); + VL_OUT8(core_req_ready,0,0); + VL_OUT8(core_rsp_valid,3,0); + VL_IN8(core_rsp_ready,0,0); + VL_OUT8(dram_req_valid,0,0); + VL_OUT8(dram_req_rw,0,0); + VL_IN8(dram_req_ready,0,0); + VL_IN8(dram_rsp_valid,0,0); + VL_OUT8(dram_rsp_ready,0,0); + VL_IN8(snp_req_valid,0,0); + VL_IN8(snp_req_invalidate,0,0); + VL_OUT8(snp_req_ready,0,0); + VL_OUT8(snp_rsp_valid,0,0); + VL_IN8(snp_rsp_ready,0,0); + VL_OUT8(snp_fwdout_valid,1,0); + VL_OUT8(snp_fwdout_invalidate,1,0); + VL_OUT8(snp_fwdout_tag,1,0); + VL_IN8(snp_fwdout_ready,1,0); + VL_IN8(snp_fwdin_valid,1,0); + VL_IN8(snp_fwdin_tag,1,0); + VL_OUT8(snp_fwdin_ready,1,0); + VL_OUT16(dram_req_byteen,15,0); + VL_INW(core_req_addr,119,0,4); + VL_INW(core_req_data,127,0,4); + VL_OUTW(core_rsp_data,127,0,4); + VL_OUT(dram_req_addr,27,0); + VL_OUTW(dram_req_data,127,0,4); + VL_OUT(dram_req_tag,27,0); + VL_INW(dram_rsp_data,127,0,4); + VL_IN(dram_rsp_tag,27,0); + VL_IN(snp_req_addr,27,0); + VL_IN(snp_req_tag,27,0); + VL_OUT(snp_rsp_tag,27,0); + VL_OUT64(snp_fwdout_addr,55,0); + VL_IN64(core_req_tag,41,0); + VL_OUT64(core_rsp_tag,41,0); + + // LOCAL SIGNALS + // Internals; generally not touched by application code + // Anonymous structures to workaround compiler member-count bugs + struct { + CData/*3:0*/ VX_cache__DOT__per_bank_core_req_ready; + CData/*3:0*/ VX_cache__DOT__per_bank_core_rsp_valid; + CData/*7:0*/ VX_cache__DOT__per_bank_core_rsp_tid; + CData/*3:0*/ VX_cache__DOT__per_bank_core_rsp_ready; + CData/*3:0*/ VX_cache__DOT__per_bank_dram_fill_req_valid; + CData/*3:0*/ VX_cache__DOT__per_bank_dram_fill_rsp_ready; + CData/*3:0*/ VX_cache__DOT__per_bank_dram_wb_req_ready; + CData/*3:0*/ VX_cache__DOT__per_bank_dram_wb_req_valid; + CData/*3:0*/ VX_cache__DOT__per_bank_snp_req_ready; + CData/*3:0*/ VX_cache__DOT__per_bank_snp_rsp_valid; + CData/*3:0*/ VX_cache__DOT__per_bank_snp_rsp_ready; + CData/*3:0*/ VX_cache__DOT__genblk5__BRA__0__KET____DOT__curr_bank_core_req_valid; + CData/*0:0*/ VX_cache__DOT__genblk5__BRA__0__KET____DOT__curr_bank_dram_wb_req_valid; + CData/*0:0*/ VX_cache__DOT__genblk5__BRA__0__KET____DOT__curr_bank_snp_rsp_valid; + CData/*3:0*/ VX_cache__DOT__genblk5__BRA__1__KET____DOT__curr_bank_core_req_valid; + CData/*0:0*/ VX_cache__DOT__genblk5__BRA__1__KET____DOT__curr_bank_dram_wb_req_valid; + CData/*0:0*/ VX_cache__DOT__genblk5__BRA__1__KET____DOT__curr_bank_snp_rsp_valid; + CData/*3:0*/ VX_cache__DOT__genblk5__BRA__2__KET____DOT__curr_bank_core_req_valid; + CData/*0:0*/ VX_cache__DOT__genblk5__BRA__2__KET____DOT__curr_bank_dram_wb_req_valid; + CData/*0:0*/ VX_cache__DOT__genblk5__BRA__2__KET____DOT__curr_bank_snp_rsp_valid; + CData/*3:0*/ VX_cache__DOT__genblk5__BRA__3__KET____DOT__curr_bank_core_req_valid; + CData/*0:0*/ VX_cache__DOT__genblk5__BRA__3__KET____DOT__curr_bank_dram_wb_req_valid; + CData/*0:0*/ VX_cache__DOT__genblk5__BRA__3__KET____DOT__curr_bank_snp_rsp_valid; + CData/*3:0*/ VX_cache__DOT__cache_core_req_bank_sel__DOT__genblk2__DOT__per_bank_ready_sel; + CData/*0:0*/ VX_cache__DOT__cache_dram_req_arb__DOT__dwb_valid; + CData/*0:0*/ VX_cache__DOT__cache_dram_req_arb__DOT__dfqq_req; + CData/*0:0*/ VX_cache__DOT__cache_dram_req_arb__DOT__dfqq_pop; + CData/*1:0*/ VX_cache__DOT__cache_dram_req_arb__DOT__dwb_bank; + CData/*1:0*/ VX_cache__DOT__cache_dram_req_arb__DOT__prfqq__DOT__use_valid; + CData/*0:0*/ VX_cache__DOT__cache_dram_req_arb__DOT__prfqq__DOT__update_use; + CData/*0:0*/ VX_cache__DOT__cache_dram_req_arb__DOT__prfqq__DOT__pfq_queue__DOT__size_r; + CData/*0:0*/ VX_cache__DOT__cache_dram_req_arb__DOT__prfqq__DOT__pfq_queue__DOT__reading; + CData/*0:0*/ VX_cache__DOT__cache_dram_req_arb__DOT__prfqq__DOT__pfq_queue__DOT__writing; + CData/*3:0*/ VX_cache__DOT__cache_dram_req_arb__DOT__dram_fill_arb__DOT__use_per_bank_dram_fill_req_valid; + CData/*3:0*/ VX_cache__DOT__cache_dram_req_arb__DOT__dram_fill_arb__DOT__use_per_bqual_bank_dram_fill_req_valid; + CData/*1:0*/ VX_cache__DOT__cache_dram_req_arb__DOT__dram_fill_arb__DOT__qual_request_index; + CData/*0:0*/ VX_cache__DOT__cache_dram_req_arb__DOT__dram_fill_arb__DOT__qual_has_request; + CData/*2:0*/ VX_cache__DOT__cache_dram_req_arb__DOT__dram_fill_arb__DOT__dfqq_queue__DOT__size_r; + CData/*0:0*/ VX_cache__DOT__cache_dram_req_arb__DOT__dram_fill_arb__DOT__dfqq_queue__DOT__reading; + CData/*0:0*/ VX_cache__DOT__cache_dram_req_arb__DOT__dram_fill_arb__DOT__dfqq_queue__DOT__writing; + CData/*1:0*/ VX_cache__DOT__cache_dram_req_arb__DOT__dram_fill_arb__DOT__dfqq_queue__DOT__genblk3__DOT__genblk2__DOT__wr_ptr_r; + CData/*1:0*/ VX_cache__DOT__cache_dram_req_arb__DOT__dram_fill_arb__DOT__dfqq_queue__DOT__genblk3__DOT__genblk2__DOT__rd_ptr_r; + CData/*1:0*/ VX_cache__DOT__cache_dram_req_arb__DOT__dram_fill_arb__DOT__dfqq_queue__DOT__genblk3__DOT__genblk2__DOT__rd_ptr_next_r; + CData/*0:0*/ VX_cache__DOT__cache_dram_req_arb__DOT__dram_fill_arb__DOT__dfqq_queue__DOT__genblk3__DOT__genblk2__DOT__empty_r; + CData/*0:0*/ VX_cache__DOT__cache_dram_req_arb__DOT__dram_fill_arb__DOT__dfqq_queue__DOT__genblk3__DOT__genblk2__DOT__full_r; + CData/*0:0*/ VX_cache__DOT__cache_dram_req_arb__DOT__dram_fill_arb__DOT__dfqq_queue__DOT__genblk3__DOT__genblk2__DOT__bypass_r; + CData/*3:0*/ VX_cache__DOT__cache_dram_req_arb__DOT__dram_fill_arb__DOT__sel_bank__DOT__genblk2__DOT__grant_onehot_r; + CData/*3:0*/ VX_cache__DOT__cache_dram_req_arb__DOT__sel_dwb__DOT__genblk2__DOT__grant_onehot_r; + CData/*1:0*/ VX_cache__DOT__cache_core_rsp_merge__DOT__main_bank_index; + CData/*3:0*/ VX_cache__DOT__cache_core_rsp_merge__DOT__per_bank_core_rsp_pop_unqual; + CData/*0:0*/ VX_cache__DOT__cache_core_rsp_merge__DOT__sel_bank__DOT__grant_valid; + CData/*3:0*/ VX_cache__DOT__cache_core_rsp_merge__DOT__sel_bank__DOT__genblk2__DOT__requests_use; + CData/*3:0*/ VX_cache__DOT__cache_core_rsp_merge__DOT__sel_bank__DOT__genblk2__DOT__update_value; + CData/*0:0*/ VX_cache__DOT__cache_core_rsp_merge__DOT__sel_bank__DOT__genblk2__DOT__refill; + CData/*3:0*/ VX_cache__DOT__cache_core_rsp_merge__DOT__sel_bank__DOT__genblk2__DOT__refill_original; + CData/*3:0*/ VX_cache__DOT__cache_core_rsp_merge__DOT__sel_bank__DOT__genblk2__DOT__grant_onehot_r; + CData/*1:0*/ VX_cache__DOT__snp_rsp_arb__DOT__fsq_bank; + CData/*0:0*/ VX_cache__DOT__snp_rsp_arb__DOT__fsq_valid; + CData/*3:0*/ VX_cache__DOT__snp_rsp_arb__DOT__sel_ffsq__DOT__genblk2__DOT__grant_onehot_r; + CData/*0:0*/ VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__snrq_pop; + CData/*0:0*/ VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__dfpq_pop; + CData/*0:0*/ VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__reqq_pop; + CData/*0:0*/ VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__reqq_req_rw_st0; + CData/*0:0*/ VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__mrvq_pop; + }; + struct { + CData/*0:0*/ VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__mrvq_rw_st0; + CData/*0:0*/ VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__force_request_miss_st1e; + CData/*0:0*/ VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__recover_mrvq_state_st2; + CData/*0:0*/ VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__mrvq_push_stall; + CData/*0:0*/ VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cwbq_push_stall; + CData/*0:0*/ VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__dwbq_push_stall; + CData/*0:0*/ VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__dram_fill_req_stall; + CData/*0:0*/ VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__stall_bank_pipe; + CData/*0:0*/ VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__is_fill_in_pipe; + CData/*0:0*/ VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__dfpq_pop_unqual; + CData/*0:0*/ VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__reqq_pop_unqual; + CData/*0:0*/ VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__snrq_pop_unqual; + CData/*0:0*/ VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__miss_st1e; + CData/*0:0*/ VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__dirty_st1e; + CData/*0:0*/ VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__snp_to_mrvq_st1e; + CData/*0:0*/ VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__miss_add_because_miss; + CData/*0:0*/ VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__mrvq_init_ready_state_st2; + CData/*0:0*/ VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__miss_add_unqual; + CData/*0:0*/ VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__miss_add; + CData/*0:0*/ VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__miss_add_is_mrvq; + CData/*0:0*/ VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cwbq_push_unqual; + CData/*0:0*/ VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__dwbq_is_dwb_in; + CData/*0:0*/ VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__dwbq_is_snp_in; + CData/*0:0*/ VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__dwbq_push_unqual; + CData/*0:0*/ VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__dram_wb_req_fire; + CData/*0:0*/ VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__snp_rsp_fire; + CData/*0:0*/ VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__dwbq_dual_valid_sel; + CData/*4:0*/ VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__snp_req_queue__DOT__size_r; + CData/*0:0*/ VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__snp_req_queue__DOT__reading; + CData/*0:0*/ VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__snp_req_queue__DOT__writing; + CData/*3:0*/ VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__snp_req_queue__DOT__genblk3__DOT__genblk2__DOT__wr_ptr_r; + CData/*3:0*/ VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__snp_req_queue__DOT__genblk3__DOT__genblk2__DOT__rd_ptr_r; + CData/*3:0*/ VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__snp_req_queue__DOT__genblk3__DOT__genblk2__DOT__rd_ptr_next_r; + CData/*0:0*/ VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__snp_req_queue__DOT__genblk3__DOT__genblk2__DOT__empty_r; + CData/*0:0*/ VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__snp_req_queue__DOT__genblk3__DOT__genblk2__DOT__full_r; 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+ CData/*0:0*/ VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__tag_data_access__DOT__read_dirty_st1c[1]; + SData/*15:0*/ VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__tag_data_access__DOT__read_dirtyb_st1c[1]; + IData/*19:0*/ VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__tag_data_access__DOT__read_tag_st1c[1]; + WData/*127:0*/ VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__tag_data_access__DOT__read_data_st1c[1][4]; + WData/*127:0*/ VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__data[64][4]; + IData/*19:0*/ VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__tag[64]; + SData/*15:0*/ VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__dirtyb[64]; + WData/*84:0*/ VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cache_miss_resrv__DOT__metadata_table[16][3]; + WData/*75:0*/ VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cwb_queue__DOT__genblk3__DOT__data[4][3]; + WData/*199:0*/ VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__data[4][7]; + CData/*0:0*/ VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__is_fill_st1[1]; + CData/*0:0*/ VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__going_to_write_st1[1]; + CData/*0:0*/ VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__valid_st1[1]; + IData/*25:0*/ VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__addr_st1[1]; + CData/*1:0*/ VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__wsel_st1[1]; + IData/*31:0*/ VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__writeword_st1[1]; + QData/*48:0*/ VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__inst_meta_st1[1]; + WData/*127:0*/ VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__writedata_st1[1][4]; + CData/*0:0*/ VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__is_snp_st1[1]; + CData/*0:0*/ VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__snp_invalidate_st1[1]; + CData/*0:0*/ VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__is_mrvq_st1[1]; + QData/*54:0*/ VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__snp_req_queue__DOT__genblk3__DOT__data[16]; + WData/*153:0*/ VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__dfp_queue__DOT__genblk3__DOT__data[16][5]; + WData/*313:0*/ VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__data[4][10]; + CData/*0:0*/ VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__tag_data_access__DOT__read_valid_st1c[1]; + CData/*0:0*/ VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__tag_data_access__DOT__read_dirty_st1c[1]; + SData/*15:0*/ VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__tag_data_access__DOT__read_dirtyb_st1c[1]; + IData/*19:0*/ VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__tag_data_access__DOT__read_tag_st1c[1]; + WData/*127:0*/ VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__tag_data_access__DOT__read_data_st1c[1][4]; + WData/*127:0*/ VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__data[64][4]; + IData/*19:0*/ VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__tag[64]; + SData/*15:0*/ VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__dirtyb[64]; + WData/*84:0*/ VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__cache_miss_resrv__DOT__metadata_table[16][3]; + WData/*75:0*/ VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__cwb_queue__DOT__genblk3__DOT__data[4][3]; + WData/*199:0*/ VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__data[4][7]; + CData/*0:0*/ VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__is_fill_st1[1]; + }; + struct { + CData/*0:0*/ VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__going_to_write_st1[1]; + CData/*0:0*/ VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__valid_st1[1]; + IData/*25:0*/ VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__addr_st1[1]; + CData/*1:0*/ VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__wsel_st1[1]; + IData/*31:0*/ VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__writeword_st1[1]; + QData/*48:0*/ VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__inst_meta_st1[1]; + WData/*127:0*/ VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__writedata_st1[1][4]; + CData/*0:0*/ VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__is_snp_st1[1]; + CData/*0:0*/ VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__snp_invalidate_st1[1]; + CData/*0:0*/ VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__is_mrvq_st1[1]; + QData/*54:0*/ VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__snp_req_queue__DOT__genblk3__DOT__data[16]; + WData/*153:0*/ VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__dfp_queue__DOT__genblk3__DOT__data[16][5]; + WData/*313:0*/ VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__data[4][10]; + CData/*0:0*/ VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__tag_data_access__DOT__read_valid_st1c[1]; + CData/*0:0*/ VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__tag_data_access__DOT__read_dirty_st1c[1]; + SData/*15:0*/ VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__tag_data_access__DOT__read_dirtyb_st1c[1]; + IData/*19:0*/ VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__tag_data_access__DOT__read_tag_st1c[1]; + WData/*127:0*/ VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__tag_data_access__DOT__read_data_st1c[1][4]; + WData/*127:0*/ VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__data[64][4]; + IData/*19:0*/ VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__tag[64]; + SData/*15:0*/ VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__dirtyb[64]; + WData/*84:0*/ VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__cache_miss_resrv__DOT__metadata_table[16][3]; + WData/*75:0*/ VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__cwb_queue__DOT__genblk3__DOT__data[4][3]; + WData/*199:0*/ VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__data[4][7]; + CData/*0:0*/ VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__is_fill_st1[1]; + CData/*0:0*/ VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__going_to_write_st1[1]; + CData/*0:0*/ VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__valid_st1[1]; + IData/*25:0*/ VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__addr_st1[1]; + CData/*1:0*/ VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__wsel_st1[1]; + IData/*31:0*/ VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__writeword_st1[1]; + QData/*48:0*/ VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__inst_meta_st1[1]; + WData/*127:0*/ VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__writedata_st1[1][4]; + CData/*0:0*/ VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__is_snp_st1[1]; + CData/*0:0*/ VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__snp_invalidate_st1[1]; + CData/*0:0*/ VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__is_mrvq_st1[1]; + QData/*54:0*/ VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__snp_req_queue__DOT__genblk3__DOT__data[16]; + WData/*153:0*/ VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__dfp_queue__DOT__genblk3__DOT__data[16][5]; + WData/*313:0*/ VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__data[4][10]; + CData/*0:0*/ VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__tag_data_access__DOT__read_valid_st1c[1]; + CData/*0:0*/ VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__tag_data_access__DOT__read_dirty_st1c[1]; + SData/*15:0*/ VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__tag_data_access__DOT__read_dirtyb_st1c[1]; + IData/*19:0*/ VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__tag_data_access__DOT__read_tag_st1c[1]; + WData/*127:0*/ VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__tag_data_access__DOT__read_data_st1c[1][4]; + WData/*127:0*/ VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__data[64][4]; + IData/*19:0*/ VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__tag[64]; + SData/*15:0*/ VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__dirtyb[64]; + WData/*84:0*/ VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cache_miss_resrv__DOT__metadata_table[16][3]; + WData/*75:0*/ VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cwb_queue__DOT__genblk3__DOT__data[4][3]; + WData/*199:0*/ VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__data[4][7]; + }; + + // LOCAL VARIABLES + // Internals; generally not touched by application code + // Anonymous structures to workaround compiler member-count bugs + struct { + SData/*15:0*/ VX_cache__DOT____Vcellout__cache_core_req_bank_sel__per_bank_valid; + CData/*3:0*/ __Vtableidx1; + CData/*3:0*/ __Vtableidx2; + CData/*3:0*/ __Vtableidx3; + CData/*3:0*/ __Vtableidx4; + CData/*3:0*/ __Vtableidx5; + CData/*3:0*/ __Vtableidx6; + CData/*3:0*/ __Vtableidx7; + CData/*3:0*/ __Vtableidx8; + CData/*0:0*/ __Vclklast__TOP__clk; + WData/*127:0*/ VX_cache__DOT____Vcellout__cache_core_rsp_merge__core_rsp_data[4]; + WData/*115:0*/ VX_cache__DOT__cache_dram_req_arb__DOT__dram_fill_arb__DOT____Vcellout__dfqq_queue__data_out[4]; + WData/*115:0*/ VX_cache__DOT__cache_dram_req_arb__DOT__dram_fill_arb__DOT____Vcellinp__dfqq_queue__data_in[4]; + WData/*153:0*/ VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT____Vcellout__dfp_queue__data_out[5]; + WData/*153:0*/ VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT____Vcellinp__dfp_queue__data_in[5]; + WData/*242:0*/ VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT____Vcellinp__s0_1_c0__in[8]; + WData/*315:0*/ VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT____Vcellinp__st_1e_2__in[10]; + WData/*75:0*/ VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT____Vcellout__cwb_queue__data_out[3]; + WData/*75:0*/ VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT____Vcellinp__cwb_queue__data_in[3]; + WData/*199:0*/ VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT____Vcellout__dwb_queue__data_out[7]; + WData/*199:0*/ VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT____Vcellinp__dwb_queue__data_in[7]; + WData/*313:0*/ VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__core_req_arb__DOT____Vcellout__reqq_queue__data_out[10]; + WData/*313:0*/ VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__core_req_arb__DOT____Vcellinp__reqq_queue__data_in[10]; + WData/*165:0*/ VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__tag_data_access__DOT____Vcellinp__s0_1_c0__in[6]; + IData/*25:0*/ VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cache_miss_resrv__DOT____Vlvbound1; + WData/*153:0*/ VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT____Vcellout__dfp_queue__data_out[5]; + WData/*153:0*/ VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT____Vcellinp__dfp_queue__data_in[5]; + WData/*242:0*/ VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT____Vcellinp__s0_1_c0__in[8]; + WData/*315:0*/ VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT____Vcellinp__st_1e_2__in[10]; + WData/*75:0*/ VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT____Vcellout__cwb_queue__data_out[3]; + WData/*75:0*/ VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT____Vcellinp__cwb_queue__data_in[3]; + WData/*199:0*/ VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT____Vcellout__dwb_queue__data_out[7]; + WData/*199:0*/ VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT____Vcellinp__dwb_queue__data_in[7]; + WData/*313:0*/ VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__core_req_arb__DOT____Vcellout__reqq_queue__data_out[10]; + WData/*313:0*/ VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__core_req_arb__DOT____Vcellinp__reqq_queue__data_in[10]; + WData/*165:0*/ VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__tag_data_access__DOT____Vcellinp__s0_1_c0__in[6]; + IData/*25:0*/ VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__cache_miss_resrv__DOT____Vlvbound1; + WData/*153:0*/ VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT____Vcellout__dfp_queue__data_out[5]; + WData/*153:0*/ VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT____Vcellinp__dfp_queue__data_in[5]; + WData/*242:0*/ VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT____Vcellinp__s0_1_c0__in[8]; + WData/*315:0*/ VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT____Vcellinp__st_1e_2__in[10]; + WData/*75:0*/ VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT____Vcellout__cwb_queue__data_out[3]; + WData/*75:0*/ VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT____Vcellinp__cwb_queue__data_in[3]; + WData/*199:0*/ VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT____Vcellout__dwb_queue__data_out[7]; + WData/*199:0*/ VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT____Vcellinp__dwb_queue__data_in[7]; + WData/*313:0*/ VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__core_req_arb__DOT____Vcellout__reqq_queue__data_out[10]; + WData/*313:0*/ VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__core_req_arb__DOT____Vcellinp__reqq_queue__data_in[10]; + WData/*165:0*/ VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__tag_data_access__DOT____Vcellinp__s0_1_c0__in[6]; + IData/*25:0*/ VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__cache_miss_resrv__DOT____Vlvbound1; + WData/*153:0*/ VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT____Vcellout__dfp_queue__data_out[5]; + WData/*153:0*/ VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT____Vcellinp__dfp_queue__data_in[5]; + WData/*242:0*/ VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT____Vcellinp__s0_1_c0__in[8]; + WData/*315:0*/ VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT____Vcellinp__st_1e_2__in[10]; + WData/*75:0*/ VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT____Vcellout__cwb_queue__data_out[3]; + WData/*75:0*/ VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT____Vcellinp__cwb_queue__data_in[3]; + WData/*199:0*/ VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT____Vcellout__dwb_queue__data_out[7]; + WData/*199:0*/ VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT____Vcellinp__dwb_queue__data_in[7]; + WData/*313:0*/ VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__core_req_arb__DOT____Vcellout__reqq_queue__data_out[10]; + WData/*313:0*/ VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__core_req_arb__DOT____Vcellinp__reqq_queue__data_in[10]; + WData/*165:0*/ VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__tag_data_access__DOT____Vcellinp__s0_1_c0__in[6]; + IData/*25:0*/ VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cache_miss_resrv__DOT____Vlvbound1; + IData/*31:0*/ __Vm_traceActivity; + QData/*54:0*/ VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT____Vcellout__snp_req_queue__data_out; + QData/*54:0*/ VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT____Vcellinp__snp_req_queue__data_in; + }; + struct { + QData/*54:0*/ VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT____Vcellout__snp_req_queue__data_out; + QData/*54:0*/ VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT____Vcellinp__snp_req_queue__data_in; + QData/*54:0*/ VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT____Vcellout__snp_req_queue__data_out; + QData/*54:0*/ VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT____Vcellinp__snp_req_queue__data_in; + QData/*54:0*/ VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT____Vcellout__snp_req_queue__data_out; + QData/*54:0*/ VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT____Vcellinp__snp_req_queue__data_in; + }; + static CData/*1:0*/ __Vtable1_VX_cache__DOT__cache_dram_req_arb__DOT__dram_fill_arb__DOT__qual_request_index[16]; + static CData/*0:0*/ __Vtable1_VX_cache__DOT__cache_dram_req_arb__DOT__dram_fill_arb__DOT__qual_has_request[16]; + static IData/*31:0*/ __Vtable1_VX_cache__DOT__cache_dram_req_arb__DOT__dram_fill_arb__DOT__sel_bank__DOT__genblk2__DOT__priority_encoder__DOT__i[16]; + static CData/*1:0*/ __Vtable2_VX_cache__DOT__cache_dram_req_arb__DOT__dwb_bank[16]; + static CData/*0:0*/ __Vtable2_VX_cache__DOT__cache_dram_req_arb__DOT__dwb_valid[16]; + static IData/*31:0*/ __Vtable2_VX_cache__DOT__cache_dram_req_arb__DOT__sel_dwb__DOT__genblk2__DOT__priority_encoder__DOT__i[16]; + static CData/*1:0*/ __Vtable3_VX_cache__DOT__cache_core_rsp_merge__DOT__main_bank_index[16]; + static CData/*0:0*/ __Vtable3_VX_cache__DOT__cache_core_rsp_merge__DOT__sel_bank__DOT__grant_valid[16]; + static IData/*31:0*/ __Vtable3_VX_cache__DOT__cache_core_rsp_merge__DOT__sel_bank__DOT__genblk2__DOT__priority_encoder__DOT__i[16]; + static CData/*1:0*/ __Vtable4_VX_cache__DOT__snp_rsp_arb__DOT__fsq_bank[16]; + static CData/*0:0*/ __Vtable4_VX_cache__DOT__snp_rsp_arb__DOT__fsq_valid[16]; + static IData/*31:0*/ __Vtable4_VX_cache__DOT__snp_rsp_arb__DOT__sel_ffsq__DOT__genblk2__DOT__priority_encoder__DOT__i[16]; + static CData/*1:0*/ __Vtable5_VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__core_req_arb__DOT__qual_request_index[16]; + static CData/*0:0*/ __Vtable5_VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__core_req_arb__DOT__qual_has_request[16]; + static IData/*31:0*/ __Vtable5_VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__core_req_arb__DOT__sel_bank__DOT__genblk2__DOT__priority_encoder__DOT__i[16]; + static CData/*1:0*/ __Vtable6_VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__core_req_arb__DOT__qual_request_index[16]; + static CData/*0:0*/ __Vtable6_VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__core_req_arb__DOT__qual_has_request[16]; + static IData/*31:0*/ __Vtable6_VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__core_req_arb__DOT__sel_bank__DOT__genblk2__DOT__priority_encoder__DOT__i[16]; + static CData/*1:0*/ __Vtable7_VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__core_req_arb__DOT__qual_request_index[16]; + static CData/*0:0*/ __Vtable7_VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__core_req_arb__DOT__qual_has_request[16]; + static IData/*31:0*/ __Vtable7_VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__core_req_arb__DOT__sel_bank__DOT__genblk2__DOT__priority_encoder__DOT__i[16]; + static CData/*1:0*/ __Vtable8_VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__core_req_arb__DOT__qual_request_index[16]; + static CData/*0:0*/ __Vtable8_VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__core_req_arb__DOT__qual_has_request[16]; + static IData/*31:0*/ __Vtable8_VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__core_req_arb__DOT__sel_bank__DOT__genblk2__DOT__priority_encoder__DOT__i[16]; + + // INTERNAL VARIABLES + // Internals; generally not touched by application code + VVX_cache__Syms* __VlSymsp; // Symbol table + + // CONSTRUCTORS + private: + VL_UNCOPYABLE(VVX_cache); ///< Copying not allowed + public: + /// Construct the model; called by application code + /// The special name may be used to make a wrapper with a + /// single model invisible with respect to DPI scope names. + VVX_cache(const char* name = "TOP"); + /// Destroy the model; called (often implicitly) by application code + ~VVX_cache(); + /// Trace signals in the model; called by application code + void trace(VerilatedVcdC* tfp, int levels, int options = 0); + + // API METHODS + /// Evaluate the model. Application must call when inputs change. + void eval() { eval_step(); } + /// Evaluate when calling multiple units/models per time step. + void eval_step(); + /// Evaluate at end of a timestep for tracing, when using eval_step(). + /// Application must call after all eval() and before time changes. + void eval_end_step() {} + /// Simulation complete, run final blocks. Application must call on completion. + void final(); + + // INTERNAL METHODS + private: + static void _eval_initial_loop(VVX_cache__Syms* __restrict vlSymsp); + public: + void __Vconfigure(VVX_cache__Syms* symsp, bool first); + private: + static QData _change_request(VVX_cache__Syms* __restrict vlSymsp); + public: + static void _combo__TOP__2(VVX_cache__Syms* __restrict vlSymsp); + static void _combo__TOP__5(VVX_cache__Syms* __restrict vlSymsp); + private: + void _ctor_var_reset() VL_ATTR_COLD; + public: + static void _eval(VVX_cache__Syms* __restrict vlSymsp); + private: +#ifdef VL_DEBUG + void _eval_debug_assertions(); +#endif // VL_DEBUG + public: + static void _eval_initial(VVX_cache__Syms* __restrict vlSymsp) VL_ATTR_COLD; + static void _eval_settle(VVX_cache__Syms* __restrict vlSymsp) VL_ATTR_COLD; + static void _initial__TOP__1(VVX_cache__Syms* __restrict vlSymsp) VL_ATTR_COLD; + static void _sequent__TOP__4(VVX_cache__Syms* __restrict vlSymsp); + static void _settle__TOP__3(VVX_cache__Syms* __restrict vlSymsp) VL_ATTR_COLD; + static void traceChgThis(VVX_cache__Syms* __restrict vlSymsp, VerilatedVcd* vcdp, uint32_t code); + static void traceChgThis__2(VVX_cache__Syms* __restrict vlSymsp, VerilatedVcd* vcdp, uint32_t code); + static void traceChgThis__3(VVX_cache__Syms* __restrict vlSymsp, VerilatedVcd* vcdp, uint32_t code); + static void traceChgThis__4(VVX_cache__Syms* __restrict vlSymsp, VerilatedVcd* vcdp, uint32_t code); + static void traceChgThis__5(VVX_cache__Syms* __restrict vlSymsp, VerilatedVcd* vcdp, uint32_t code); + static void traceChgThis__6(VVX_cache__Syms* __restrict vlSymsp, VerilatedVcd* vcdp, uint32_t code); + static void traceFullThis(VVX_cache__Syms* __restrict vlSymsp, VerilatedVcd* vcdp, uint32_t code) VL_ATTR_COLD; + static void traceFullThis__1(VVX_cache__Syms* __restrict vlSymsp, VerilatedVcd* vcdp, uint32_t code) VL_ATTR_COLD; + static void traceInitThis(VVX_cache__Syms* __restrict vlSymsp, VerilatedVcd* vcdp, uint32_t code) VL_ATTR_COLD; + static void traceInitThis__1(VVX_cache__Syms* __restrict vlSymsp, VerilatedVcd* vcdp, uint32_t code) VL_ATTR_COLD; + static void traceInit(VerilatedVcd* vcdp, void* userthis, uint32_t code); + static void traceFull(VerilatedVcd* vcdp, void* userthis, uint32_t code); + static void traceChg(VerilatedVcd* vcdp, void* userthis, uint32_t code); +} VL_ATTR_ALIGNED(VL_CACHE_LINE_BYTES); + +//---------- + + +#endif // guard diff --git a/hw/unit_tests/cache/obj_dir/VVX_cache.mk b/hw/unit_tests/cache/obj_dir/VVX_cache.mk new file mode 100644 index 00000000..2d37632a --- /dev/null +++ b/hw/unit_tests/cache/obj_dir/VVX_cache.mk @@ -0,0 +1,70 @@ +# Verilated -*- Makefile -*- +# DESCRIPTION: Verilator output: Makefile for building Verilated archive or executable +# +# Execute this makefile from the object directory: +# make -f VVX_cache.mk + +default: VVX_cache + +### Constants... +# Perl executable (from $PERL) +PERL = perl +# Path to Verilator kit (from $VERILATOR_ROOT) +VERILATOR_ROOT = /usr/local/share/verilator +# SystemC include directory with systemc.h (from $SYSTEMC_INCLUDE) +SYSTEMC_INCLUDE ?= +# SystemC library directory with libsystemc.a (from $SYSTEMC_LIBDIR) +SYSTEMC_LIBDIR ?= + +### Switches... +# SystemC output mode? 0/1 (from --sc) +VM_SC = 0 +# Legacy or SystemC output mode? 0/1 (from --sc) +VM_SP_OR_SC = $(VM_SC) +# Deprecated +VM_PCLI = 1 +# Deprecated: SystemC architecture to find link library path (from $SYSTEMC_ARCH) +VM_SC_TARGET_ARCH = linux + +### Vars... +# Design prefix (from --prefix) +VM_PREFIX = VVX_cache +# Module prefix (from --prefix) +VM_MODPREFIX = VVX_cache +# User CFLAGS (from -CFLAGS on Verilator command line) +VM_USER_CFLAGS = \ + -std=c++11 -fms-extensions -I../.. -DNDEBUG -DCACHE_SIZE=4096 -DWORD_SIZE=4 -DBANK_LINE_SIZE=16 -DNUM_BANKS=4 -DCREQ_SIZE=4 -DMRVQ_SIZE=16 -DDFPQ_SIZE=16 -DSNRQ_SIZE=16 -DCWBQ_SIZE=4 -DDWBQ_SIZE=4 -DFQQ_SIZE=4 \ + +# User LDLIBS (from -LDFLAGS on Verilator command line) +VM_USER_LDLIBS = \ + +# User .cpp files (from .cpp's on Verilator command line) +VM_USER_CLASSES = \ + cachesim \ + testbench \ + +# User .cpp directories (from .cpp's on Verilator command line) +VM_USER_DIR = \ + . \ + + +### Default rules... +# Include list of all generated classes +include VVX_cache_classes.mk +# Include global rules +include $(VERILATOR_ROOT)/include/verilated.mk + +### Executable rules... (from --exe) +VPATH += $(VM_USER_DIR) + +cachesim.o: cachesim.cpp + $(OBJCACHE) $(CXX) $(CXXFLAGS) $(CPPFLAGS) $(OPT_FAST) -c -o $@ $< +testbench.o: testbench.cpp + $(OBJCACHE) $(CXX) $(CXXFLAGS) $(CPPFLAGS) $(OPT_FAST) -c -o $@ $< + +### Link rules... (from --exe) +VVX_cache: $(VK_USER_OBJS) $(VK_GLOBAL_OBJS) $(VM_PREFIX)__ALL.a + $(LINK) $(LDFLAGS) $^ $(LOADLIBES) $(LDLIBS) -o $@ $(LIBS) $(SC_LIBS) + + +# Verilated -*- Makefile -*- diff --git a/hw/unit_tests/cache/obj_dir/VVX_cache__ALL.a b/hw/unit_tests/cache/obj_dir/VVX_cache__ALL.a new file mode 100644 index 00000000..a6bb3656 Binary files /dev/null and b/hw/unit_tests/cache/obj_dir/VVX_cache__ALL.a differ diff --git a/hw/unit_tests/cache/obj_dir/VVX_cache__ALLcls.cpp b/hw/unit_tests/cache/obj_dir/VVX_cache__ALLcls.cpp new file mode 100644 index 00000000..ef997202 --- /dev/null +++ b/hw/unit_tests/cache/obj_dir/VVX_cache__ALLcls.cpp @@ -0,0 +1,3 @@ +// DESCRIPTION: Generated by verilator_includer via makefile +#define VL_INCLUDE_OPT include +#include "VVX_cache.cpp" diff --git a/hw/unit_tests/cache/obj_dir/VVX_cache__ALLcls.d b/hw/unit_tests/cache/obj_dir/VVX_cache__ALLcls.d new file mode 100644 index 00000000..2cfba2f9 --- /dev/null +++ b/hw/unit_tests/cache/obj_dir/VVX_cache__ALLcls.d @@ -0,0 +1,4 @@ +VVX_cache__ALLcls.o: VVX_cache__ALLcls.cpp VVX_cache.cpp VVX_cache.h \ + /usr/local/share/verilator/include/verilated_heavy.h \ + /usr/local/share/verilator/include/verilated.h \ + /usr/local/share/verilator/include/verilatedos.h VVX_cache__Syms.h diff --git a/hw/unit_tests/cache/obj_dir/VVX_cache__ALLcls.o b/hw/unit_tests/cache/obj_dir/VVX_cache__ALLcls.o new file mode 100644 index 00000000..ca600f24 Binary files /dev/null and b/hw/unit_tests/cache/obj_dir/VVX_cache__ALLcls.o differ diff --git a/hw/unit_tests/cache/obj_dir/VVX_cache__ALLsup.cpp b/hw/unit_tests/cache/obj_dir/VVX_cache__ALLsup.cpp new file mode 100644 index 00000000..1cfc236e --- /dev/null +++ b/hw/unit_tests/cache/obj_dir/VVX_cache__ALLsup.cpp @@ -0,0 +1,5 @@ +// DESCRIPTION: Generated by verilator_includer via makefile +#define VL_INCLUDE_OPT include +#include "VVX_cache__Trace.cpp" +#include "VVX_cache__Syms.cpp" +#include "VVX_cache__Trace__Slow.cpp" diff --git a/hw/unit_tests/cache/obj_dir/VVX_cache__ALLsup.d b/hw/unit_tests/cache/obj_dir/VVX_cache__ALLsup.d new file mode 100644 index 00000000..e6af5a49 --- /dev/null +++ b/hw/unit_tests/cache/obj_dir/VVX_cache__ALLsup.d @@ -0,0 +1,6 @@ +VVX_cache__ALLsup.o: VVX_cache__ALLsup.cpp VVX_cache__Trace.cpp \ + /usr/local/share/verilator/include/verilated_vcd_c.h \ + /usr/local/share/verilator/include/verilatedos.h \ + /usr/local/share/verilator/include/verilated.h VVX_cache__Syms.h \ + /usr/local/share/verilator/include/verilated_heavy.h VVX_cache.h \ + VVX_cache__Syms.cpp VVX_cache__Trace__Slow.cpp diff --git a/hw/unit_tests/cache/obj_dir/VVX_cache__ALLsup.o b/hw/unit_tests/cache/obj_dir/VVX_cache__ALLsup.o new file mode 100644 index 00000000..3400b126 Binary files /dev/null and b/hw/unit_tests/cache/obj_dir/VVX_cache__ALLsup.o differ diff --git a/hw/unit_tests/cache/obj_dir/VVX_cache__Syms.cpp b/hw/unit_tests/cache/obj_dir/VVX_cache__Syms.cpp new file mode 100644 index 00000000..3bb16217 --- /dev/null +++ b/hw/unit_tests/cache/obj_dir/VVX_cache__Syms.cpp @@ -0,0 +1,65 @@ +// Verilated -*- C++ -*- +// DESCRIPTION: Verilator output: Symbol table implementation internals + +#include "VVX_cache__Syms.h" +#include "VVX_cache.h" + + + +// FUNCTIONS +VVX_cache__Syms::VVX_cache__Syms(VVX_cache* topp, const char* namep) + // Setup locals + : __Vm_namep(namep) + , __Vm_activity(false) + , __Vm_didInit(false) + // Setup submodule names +{ + // Pointer to top level + TOPp = topp; + // Setup each module's pointers to their submodules + // Setup each module's pointer back to symbol table (for public functions) + TOPp->__Vconfigure(this, true); + // Setup scopes + __Vscope_VX_cache__cache_dram_req_arb__dram_fill_arb__dfqq_queue.configure(this, name(), "VX_cache.cache_dram_req_arb.dram_fill_arb.dfqq_queue", "dfqq_queue", VerilatedScope::SCOPE_OTHER); + __Vscope_VX_cache__cache_dram_req_arb__dram_fill_arb__dfqq_queue__genblk3__genblk2.configure(this, name(), "VX_cache.cache_dram_req_arb.dram_fill_arb.dfqq_queue.genblk3.genblk2", "genblk2", VerilatedScope::SCOPE_OTHER); + __Vscope_VX_cache__genblk5__BRA__0__KET____bank__core_req_arb__reqq_queue.configure(this, name(), "VX_cache.genblk5[0].bank.core_req_arb.reqq_queue", "reqq_queue", VerilatedScope::SCOPE_OTHER); + __Vscope_VX_cache__genblk5__BRA__0__KET____bank__core_req_arb__reqq_queue__genblk3__genblk2.configure(this, name(), "VX_cache.genblk5[0].bank.core_req_arb.reqq_queue.genblk3.genblk2", "genblk2", VerilatedScope::SCOPE_OTHER); + __Vscope_VX_cache__genblk5__BRA__0__KET____bank__cwb_queue.configure(this, name(), "VX_cache.genblk5[0].bank.cwb_queue", "cwb_queue", VerilatedScope::SCOPE_OTHER); + __Vscope_VX_cache__genblk5__BRA__0__KET____bank__cwb_queue__genblk3__genblk2.configure(this, name(), "VX_cache.genblk5[0].bank.cwb_queue.genblk3.genblk2", "genblk2", VerilatedScope::SCOPE_OTHER); + __Vscope_VX_cache__genblk5__BRA__0__KET____bank__dfp_queue.configure(this, name(), "VX_cache.genblk5[0].bank.dfp_queue", "dfp_queue", VerilatedScope::SCOPE_OTHER); + __Vscope_VX_cache__genblk5__BRA__0__KET____bank__dfp_queue__genblk3__genblk2.configure(this, name(), "VX_cache.genblk5[0].bank.dfp_queue.genblk3.genblk2", "genblk2", VerilatedScope::SCOPE_OTHER); + __Vscope_VX_cache__genblk5__BRA__0__KET____bank__dwb_queue.configure(this, name(), "VX_cache.genblk5[0].bank.dwb_queue", "dwb_queue", VerilatedScope::SCOPE_OTHER); + __Vscope_VX_cache__genblk5__BRA__0__KET____bank__dwb_queue__genblk3__genblk2.configure(this, name(), "VX_cache.genblk5[0].bank.dwb_queue.genblk3.genblk2", "genblk2", VerilatedScope::SCOPE_OTHER); + __Vscope_VX_cache__genblk5__BRA__0__KET____bank__snp_req_queue.configure(this, name(), "VX_cache.genblk5[0].bank.snp_req_queue", "snp_req_queue", VerilatedScope::SCOPE_OTHER); + __Vscope_VX_cache__genblk5__BRA__0__KET____bank__snp_req_queue__genblk3__genblk2.configure(this, name(), "VX_cache.genblk5[0].bank.snp_req_queue.genblk3.genblk2", "genblk2", VerilatedScope::SCOPE_OTHER); + __Vscope_VX_cache__genblk5__BRA__1__KET____bank__core_req_arb__reqq_queue.configure(this, name(), "VX_cache.genblk5[1].bank.core_req_arb.reqq_queue", "reqq_queue", VerilatedScope::SCOPE_OTHER); + __Vscope_VX_cache__genblk5__BRA__1__KET____bank__core_req_arb__reqq_queue__genblk3__genblk2.configure(this, name(), "VX_cache.genblk5[1].bank.core_req_arb.reqq_queue.genblk3.genblk2", "genblk2", VerilatedScope::SCOPE_OTHER); + __Vscope_VX_cache__genblk5__BRA__1__KET____bank__cwb_queue.configure(this, name(), "VX_cache.genblk5[1].bank.cwb_queue", "cwb_queue", VerilatedScope::SCOPE_OTHER); + __Vscope_VX_cache__genblk5__BRA__1__KET____bank__cwb_queue__genblk3__genblk2.configure(this, name(), "VX_cache.genblk5[1].bank.cwb_queue.genblk3.genblk2", "genblk2", VerilatedScope::SCOPE_OTHER); + __Vscope_VX_cache__genblk5__BRA__1__KET____bank__dfp_queue.configure(this, name(), "VX_cache.genblk5[1].bank.dfp_queue", "dfp_queue", VerilatedScope::SCOPE_OTHER); + __Vscope_VX_cache__genblk5__BRA__1__KET____bank__dfp_queue__genblk3__genblk2.configure(this, name(), "VX_cache.genblk5[1].bank.dfp_queue.genblk3.genblk2", "genblk2", VerilatedScope::SCOPE_OTHER); + __Vscope_VX_cache__genblk5__BRA__1__KET____bank__dwb_queue.configure(this, name(), "VX_cache.genblk5[1].bank.dwb_queue", "dwb_queue", VerilatedScope::SCOPE_OTHER); + __Vscope_VX_cache__genblk5__BRA__1__KET____bank__dwb_queue__genblk3__genblk2.configure(this, name(), "VX_cache.genblk5[1].bank.dwb_queue.genblk3.genblk2", "genblk2", VerilatedScope::SCOPE_OTHER); + __Vscope_VX_cache__genblk5__BRA__1__KET____bank__snp_req_queue.configure(this, name(), "VX_cache.genblk5[1].bank.snp_req_queue", "snp_req_queue", VerilatedScope::SCOPE_OTHER); + __Vscope_VX_cache__genblk5__BRA__1__KET____bank__snp_req_queue__genblk3__genblk2.configure(this, name(), "VX_cache.genblk5[1].bank.snp_req_queue.genblk3.genblk2", "genblk2", VerilatedScope::SCOPE_OTHER); + __Vscope_VX_cache__genblk5__BRA__2__KET____bank__core_req_arb__reqq_queue.configure(this, name(), "VX_cache.genblk5[2].bank.core_req_arb.reqq_queue", "reqq_queue", VerilatedScope::SCOPE_OTHER); + __Vscope_VX_cache__genblk5__BRA__2__KET____bank__core_req_arb__reqq_queue__genblk3__genblk2.configure(this, name(), "VX_cache.genblk5[2].bank.core_req_arb.reqq_queue.genblk3.genblk2", "genblk2", VerilatedScope::SCOPE_OTHER); + __Vscope_VX_cache__genblk5__BRA__2__KET____bank__cwb_queue.configure(this, name(), "VX_cache.genblk5[2].bank.cwb_queue", "cwb_queue", VerilatedScope::SCOPE_OTHER); + __Vscope_VX_cache__genblk5__BRA__2__KET____bank__cwb_queue__genblk3__genblk2.configure(this, name(), "VX_cache.genblk5[2].bank.cwb_queue.genblk3.genblk2", "genblk2", VerilatedScope::SCOPE_OTHER); + __Vscope_VX_cache__genblk5__BRA__2__KET____bank__dfp_queue.configure(this, name(), "VX_cache.genblk5[2].bank.dfp_queue", "dfp_queue", VerilatedScope::SCOPE_OTHER); + __Vscope_VX_cache__genblk5__BRA__2__KET____bank__dfp_queue__genblk3__genblk2.configure(this, name(), "VX_cache.genblk5[2].bank.dfp_queue.genblk3.genblk2", "genblk2", VerilatedScope::SCOPE_OTHER); + __Vscope_VX_cache__genblk5__BRA__2__KET____bank__dwb_queue.configure(this, name(), "VX_cache.genblk5[2].bank.dwb_queue", "dwb_queue", VerilatedScope::SCOPE_OTHER); + __Vscope_VX_cache__genblk5__BRA__2__KET____bank__dwb_queue__genblk3__genblk2.configure(this, name(), "VX_cache.genblk5[2].bank.dwb_queue.genblk3.genblk2", "genblk2", VerilatedScope::SCOPE_OTHER); + __Vscope_VX_cache__genblk5__BRA__2__KET____bank__snp_req_queue.configure(this, name(), "VX_cache.genblk5[2].bank.snp_req_queue", "snp_req_queue", VerilatedScope::SCOPE_OTHER); + __Vscope_VX_cache__genblk5__BRA__2__KET____bank__snp_req_queue__genblk3__genblk2.configure(this, name(), "VX_cache.genblk5[2].bank.snp_req_queue.genblk3.genblk2", "genblk2", VerilatedScope::SCOPE_OTHER); + __Vscope_VX_cache__genblk5__BRA__3__KET____bank__core_req_arb__reqq_queue.configure(this, name(), "VX_cache.genblk5[3].bank.core_req_arb.reqq_queue", "reqq_queue", VerilatedScope::SCOPE_OTHER); + __Vscope_VX_cache__genblk5__BRA__3__KET____bank__core_req_arb__reqq_queue__genblk3__genblk2.configure(this, name(), "VX_cache.genblk5[3].bank.core_req_arb.reqq_queue.genblk3.genblk2", "genblk2", VerilatedScope::SCOPE_OTHER); + __Vscope_VX_cache__genblk5__BRA__3__KET____bank__cwb_queue.configure(this, name(), "VX_cache.genblk5[3].bank.cwb_queue", "cwb_queue", VerilatedScope::SCOPE_OTHER); + __Vscope_VX_cache__genblk5__BRA__3__KET____bank__cwb_queue__genblk3__genblk2.configure(this, name(), "VX_cache.genblk5[3].bank.cwb_queue.genblk3.genblk2", "genblk2", VerilatedScope::SCOPE_OTHER); + __Vscope_VX_cache__genblk5__BRA__3__KET____bank__dfp_queue.configure(this, name(), "VX_cache.genblk5[3].bank.dfp_queue", "dfp_queue", VerilatedScope::SCOPE_OTHER); + __Vscope_VX_cache__genblk5__BRA__3__KET____bank__dfp_queue__genblk3__genblk2.configure(this, name(), "VX_cache.genblk5[3].bank.dfp_queue.genblk3.genblk2", "genblk2", VerilatedScope::SCOPE_OTHER); + __Vscope_VX_cache__genblk5__BRA__3__KET____bank__dwb_queue.configure(this, name(), "VX_cache.genblk5[3].bank.dwb_queue", "dwb_queue", VerilatedScope::SCOPE_OTHER); + __Vscope_VX_cache__genblk5__BRA__3__KET____bank__dwb_queue__genblk3__genblk2.configure(this, name(), "VX_cache.genblk5[3].bank.dwb_queue.genblk3.genblk2", "genblk2", VerilatedScope::SCOPE_OTHER); + __Vscope_VX_cache__genblk5__BRA__3__KET____bank__snp_req_queue.configure(this, name(), "VX_cache.genblk5[3].bank.snp_req_queue", "snp_req_queue", VerilatedScope::SCOPE_OTHER); + __Vscope_VX_cache__genblk5__BRA__3__KET____bank__snp_req_queue__genblk3__genblk2.configure(this, name(), "VX_cache.genblk5[3].bank.snp_req_queue.genblk3.genblk2", "genblk2", VerilatedScope::SCOPE_OTHER); +} diff --git a/hw/unit_tests/cache/obj_dir/VVX_cache__Syms.h b/hw/unit_tests/cache/obj_dir/VVX_cache__Syms.h new file mode 100644 index 00000000..c6de6125 --- /dev/null +++ b/hw/unit_tests/cache/obj_dir/VVX_cache__Syms.h @@ -0,0 +1,81 @@ +// Verilated -*- C++ -*- +// DESCRIPTION: Verilator output: Symbol table internal header +// +// Internal details; most calling programs do not need this header, +// unless using verilator public meta comments. + +#ifndef _VVX_CACHE__SYMS_H_ +#define _VVX_CACHE__SYMS_H_ // guard + +#include "verilated_heavy.h" + +// INCLUDE MODULE CLASSES +#include "VVX_cache.h" + +// SYMS CLASS +class VVX_cache__Syms : public VerilatedSyms { + public: + + // LOCAL STATE + const char* __Vm_namep; + bool __Vm_activity; ///< Used by trace routines to determine change occurred + bool __Vm_didInit; + + // SUBCELL STATE + VVX_cache* TOPp; + + // SCOPE NAMES + VerilatedScope __Vscope_VX_cache__cache_dram_req_arb__dram_fill_arb__dfqq_queue; + VerilatedScope __Vscope_VX_cache__cache_dram_req_arb__dram_fill_arb__dfqq_queue__genblk3__genblk2; + VerilatedScope __Vscope_VX_cache__genblk5__BRA__0__KET____bank__core_req_arb__reqq_queue; + VerilatedScope __Vscope_VX_cache__genblk5__BRA__0__KET____bank__core_req_arb__reqq_queue__genblk3__genblk2; + VerilatedScope __Vscope_VX_cache__genblk5__BRA__0__KET____bank__cwb_queue; + VerilatedScope __Vscope_VX_cache__genblk5__BRA__0__KET____bank__cwb_queue__genblk3__genblk2; + VerilatedScope __Vscope_VX_cache__genblk5__BRA__0__KET____bank__dfp_queue; + VerilatedScope __Vscope_VX_cache__genblk5__BRA__0__KET____bank__dfp_queue__genblk3__genblk2; + VerilatedScope __Vscope_VX_cache__genblk5__BRA__0__KET____bank__dwb_queue; + VerilatedScope __Vscope_VX_cache__genblk5__BRA__0__KET____bank__dwb_queue__genblk3__genblk2; + VerilatedScope __Vscope_VX_cache__genblk5__BRA__0__KET____bank__snp_req_queue; + VerilatedScope __Vscope_VX_cache__genblk5__BRA__0__KET____bank__snp_req_queue__genblk3__genblk2; + VerilatedScope __Vscope_VX_cache__genblk5__BRA__1__KET____bank__core_req_arb__reqq_queue; + VerilatedScope __Vscope_VX_cache__genblk5__BRA__1__KET____bank__core_req_arb__reqq_queue__genblk3__genblk2; + VerilatedScope __Vscope_VX_cache__genblk5__BRA__1__KET____bank__cwb_queue; + VerilatedScope __Vscope_VX_cache__genblk5__BRA__1__KET____bank__cwb_queue__genblk3__genblk2; + VerilatedScope __Vscope_VX_cache__genblk5__BRA__1__KET____bank__dfp_queue; + VerilatedScope __Vscope_VX_cache__genblk5__BRA__1__KET____bank__dfp_queue__genblk3__genblk2; + VerilatedScope __Vscope_VX_cache__genblk5__BRA__1__KET____bank__dwb_queue; + VerilatedScope __Vscope_VX_cache__genblk5__BRA__1__KET____bank__dwb_queue__genblk3__genblk2; + VerilatedScope __Vscope_VX_cache__genblk5__BRA__1__KET____bank__snp_req_queue; + VerilatedScope __Vscope_VX_cache__genblk5__BRA__1__KET____bank__snp_req_queue__genblk3__genblk2; + VerilatedScope __Vscope_VX_cache__genblk5__BRA__2__KET____bank__core_req_arb__reqq_queue; + VerilatedScope __Vscope_VX_cache__genblk5__BRA__2__KET____bank__core_req_arb__reqq_queue__genblk3__genblk2; + VerilatedScope __Vscope_VX_cache__genblk5__BRA__2__KET____bank__cwb_queue; + VerilatedScope __Vscope_VX_cache__genblk5__BRA__2__KET____bank__cwb_queue__genblk3__genblk2; + VerilatedScope __Vscope_VX_cache__genblk5__BRA__2__KET____bank__dfp_queue; + VerilatedScope __Vscope_VX_cache__genblk5__BRA__2__KET____bank__dfp_queue__genblk3__genblk2; + VerilatedScope __Vscope_VX_cache__genblk5__BRA__2__KET____bank__dwb_queue; + VerilatedScope __Vscope_VX_cache__genblk5__BRA__2__KET____bank__dwb_queue__genblk3__genblk2; + VerilatedScope __Vscope_VX_cache__genblk5__BRA__2__KET____bank__snp_req_queue; + VerilatedScope __Vscope_VX_cache__genblk5__BRA__2__KET____bank__snp_req_queue__genblk3__genblk2; + VerilatedScope __Vscope_VX_cache__genblk5__BRA__3__KET____bank__core_req_arb__reqq_queue; + VerilatedScope __Vscope_VX_cache__genblk5__BRA__3__KET____bank__core_req_arb__reqq_queue__genblk3__genblk2; + VerilatedScope __Vscope_VX_cache__genblk5__BRA__3__KET____bank__cwb_queue; + VerilatedScope __Vscope_VX_cache__genblk5__BRA__3__KET____bank__cwb_queue__genblk3__genblk2; + VerilatedScope __Vscope_VX_cache__genblk5__BRA__3__KET____bank__dfp_queue; + VerilatedScope __Vscope_VX_cache__genblk5__BRA__3__KET____bank__dfp_queue__genblk3__genblk2; + VerilatedScope __Vscope_VX_cache__genblk5__BRA__3__KET____bank__dwb_queue; + VerilatedScope __Vscope_VX_cache__genblk5__BRA__3__KET____bank__dwb_queue__genblk3__genblk2; + VerilatedScope __Vscope_VX_cache__genblk5__BRA__3__KET____bank__snp_req_queue; + VerilatedScope __Vscope_VX_cache__genblk5__BRA__3__KET____bank__snp_req_queue__genblk3__genblk2; + + // CREATORS + VVX_cache__Syms(VVX_cache* topp, const char* namep); + ~VVX_cache__Syms() {} + + // METHODS + inline const char* name() { return __Vm_namep; } + inline bool getClearActivity() { bool r=__Vm_activity; __Vm_activity=false; return r; } + +} VL_ATTR_ALIGNED(VL_CACHE_LINE_BYTES); + +#endif // guard diff --git a/hw/unit_tests/cache/obj_dir/VVX_cache__Trace.cpp b/hw/unit_tests/cache/obj_dir/VVX_cache__Trace.cpp new file mode 100644 index 00000000..8f72ecc5 --- /dev/null +++ b/hw/unit_tests/cache/obj_dir/VVX_cache__Trace.cpp @@ -0,0 +1,4066 @@ +// Verilated -*- C++ -*- +// DESCRIPTION: Verilator output: Tracing implementation internals +#include "verilated_vcd_c.h" +#include "VVX_cache__Syms.h" + + +//====================== + +void VVX_cache::traceChg(VerilatedVcd* vcdp, void* userthis, uint32_t code) { + // Callback from vcd->dump() + VVX_cache* t = (VVX_cache*)userthis; + VVX_cache__Syms* __restrict vlSymsp = t->__VlSymsp; // Setup global symbol table + if (vlSymsp->getClearActivity()) { + t->traceChgThis(vlSymsp, vcdp, code); + } +} + +//====================== + + +void VVX_cache::traceChgThis(VVX_cache__Syms* __restrict vlSymsp, VerilatedVcd* vcdp, uint32_t code) { + VVX_cache* __restrict vlTOPp VL_ATTR_UNUSED = vlSymsp->TOPp; + int c = code; + if (0 && vcdp && c) {} // Prevent unused + // Body + { + if (VL_UNLIKELY((1U & (vlTOPp->__Vm_traceActivity + | (vlTOPp->__Vm_traceActivity + >> 1U))))) { + vlTOPp->traceChgThis__2(vlSymsp, vcdp, code); + } + if (VL_UNLIKELY((1U & ((vlTOPp->__Vm_traceActivity + | (vlTOPp->__Vm_traceActivity + >> 1U)) | (vlTOPp->__Vm_traceActivity + >> 2U))))) { + vlTOPp->traceChgThis__3(vlSymsp, vcdp, code); + } + if (VL_UNLIKELY((1U & (vlTOPp->__Vm_traceActivity + | (vlTOPp->__Vm_traceActivity + >> 2U))))) { + vlTOPp->traceChgThis__4(vlSymsp, vcdp, code); + } + if (VL_UNLIKELY((4U & vlTOPp->__Vm_traceActivity))) { + vlTOPp->traceChgThis__5(vlSymsp, vcdp, code); + } + vlTOPp->traceChgThis__6(vlSymsp, vcdp, code); + } + // Final + vlTOPp->__Vm_traceActivity = 0U; +} + +void VVX_cache::traceChgThis__2(VVX_cache__Syms* __restrict vlSymsp, VerilatedVcd* vcdp, uint32_t code) { + VVX_cache* __restrict vlTOPp VL_ATTR_UNUSED = vlSymsp->TOPp; + int c = code; + if (0 && vcdp && c) {} // Prevent unused + // Body + { + vcdp->chgBus(c+1,(vlTOPp->VX_cache__DOT____Vcellout__cache_core_req_bank_sel__per_bank_valid),16); + vcdp->chgBus(c+9,(vlTOPp->VX_cache__DOT__per_bank_core_rsp_ready),4); + vcdp->chgBus(c+17,(vlTOPp->VX_cache__DOT__per_bank_dram_wb_req_ready),4); + vcdp->chgBus(c+25,(vlTOPp->VX_cache__DOT__per_bank_snp_rsp_ready),4); + vcdp->chgBus(c+33,(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__curr_bank_core_req_valid),4); + vcdp->chgBit(c+41,((1U & (IData)(vlTOPp->VX_cache__DOT__per_bank_core_rsp_ready)))); + vcdp->chgBit(c+49,((1U & (IData)(vlTOPp->VX_cache__DOT__per_bank_dram_wb_req_ready)))); + vcdp->chgBit(c+57,((1U & (IData)(vlTOPp->VX_cache__DOT__per_bank_snp_rsp_ready)))); + vcdp->chgBus(c+65,(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__curr_bank_core_req_valid),4); + vcdp->chgBit(c+73,((1U & ((IData)(vlTOPp->VX_cache__DOT__per_bank_core_rsp_ready) + >> 1U)))); + vcdp->chgBit(c+81,((1U & ((IData)(vlTOPp->VX_cache__DOT__per_bank_dram_wb_req_ready) + >> 1U)))); + vcdp->chgBit(c+89,((1U & ((IData)(vlTOPp->VX_cache__DOT__per_bank_snp_rsp_ready) + >> 1U)))); + vcdp->chgBus(c+97,(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__curr_bank_core_req_valid),4); + vcdp->chgBit(c+105,((1U & ((IData)(vlTOPp->VX_cache__DOT__per_bank_core_rsp_ready) + >> 2U)))); + vcdp->chgBit(c+113,((1U & ((IData)(vlTOPp->VX_cache__DOT__per_bank_dram_wb_req_ready) + >> 2U)))); + vcdp->chgBit(c+121,((1U & ((IData)(vlTOPp->VX_cache__DOT__per_bank_snp_rsp_ready) + >> 2U)))); + vcdp->chgBus(c+129,(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__curr_bank_core_req_valid),4); + vcdp->chgBit(c+137,((1U & ((IData)(vlTOPp->VX_cache__DOT__per_bank_core_rsp_ready) + >> 3U)))); + vcdp->chgBit(c+145,((1U & ((IData)(vlTOPp->VX_cache__DOT__per_bank_dram_wb_req_ready) + >> 3U)))); + vcdp->chgBit(c+153,((1U & ((IData)(vlTOPp->VX_cache__DOT__per_bank_snp_rsp_ready) + >> 3U)))); + vcdp->chgBus(c+161,(vlTOPp->VX_cache__DOT__cache_core_req_bank_sel__DOT__genblk2__DOT__per_bank_ready_sel),4); + vcdp->chgBit(c+169,(vlTOPp->VX_cache__DOT__cache_dram_req_arb__DOT__dfqq_pop)); + vcdp->chgBit(c+177,(vlTOPp->VX_cache__DOT__cache_dram_req_arb__DOT__dram_fill_arb__DOT__dfqq_queue__DOT__reading)); + vcdp->chgBit(c+185,(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__dram_wb_req_fire)); + vcdp->chgBit(c+193,(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__snp_rsp_fire)); + vcdp->chgQuad(c+201,(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT____Vcellinp__snp_req_queue__data_in),55); + vcdp->chgBit(c+217,(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__snp_req_queue__DOT__writing)); + vcdp->chgArray(c+225,(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT____Vcellinp__dfp_queue__data_in),154); + vcdp->chgBit(c+265,(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__dfp_queue__DOT__writing)); + vcdp->chgArray(c+273,(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__core_req_arb__DOT____Vcellinp__reqq_queue__data_in),314); + vcdp->chgBit(c+353,(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__writing)); + vcdp->chgBit(c+361,(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cwb_queue__DOT__reading)); + vcdp->chgBit(c+369,(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__dwb_queue__DOT__reading)); + vcdp->chgBit(c+377,(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__dram_wb_req_fire)); + vcdp->chgBit(c+385,(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__snp_rsp_fire)); + vcdp->chgQuad(c+393,(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT____Vcellinp__snp_req_queue__data_in),55); + vcdp->chgBit(c+409,(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__snp_req_queue__DOT__writing)); + vcdp->chgArray(c+417,(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT____Vcellinp__dfp_queue__data_in),154); + vcdp->chgBit(c+457,(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__dfp_queue__DOT__writing)); + vcdp->chgArray(c+465,(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__core_req_arb__DOT____Vcellinp__reqq_queue__data_in),314); + vcdp->chgBit(c+545,(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__writing)); + vcdp->chgBit(c+553,(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__cwb_queue__DOT__reading)); + vcdp->chgBit(c+561,(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__dwb_queue__DOT__reading)); + vcdp->chgBit(c+569,(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__dram_wb_req_fire)); + vcdp->chgBit(c+577,(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__snp_rsp_fire)); + vcdp->chgQuad(c+585,(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT____Vcellinp__snp_req_queue__data_in),55); + vcdp->chgBit(c+601,(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__snp_req_queue__DOT__writing)); + vcdp->chgArray(c+609,(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT____Vcellinp__dfp_queue__data_in),154); + vcdp->chgBit(c+649,(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__dfp_queue__DOT__writing)); + vcdp->chgArray(c+657,(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__core_req_arb__DOT____Vcellinp__reqq_queue__data_in),314); + vcdp->chgBit(c+737,(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__writing)); + vcdp->chgBit(c+745,(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__cwb_queue__DOT__reading)); + vcdp->chgBit(c+753,(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__dwb_queue__DOT__reading)); + vcdp->chgBit(c+761,(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__dram_wb_req_fire)); + vcdp->chgBit(c+769,(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__snp_rsp_fire)); + vcdp->chgQuad(c+777,(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT____Vcellinp__snp_req_queue__data_in),55); + vcdp->chgBit(c+793,(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__snp_req_queue__DOT__writing)); + vcdp->chgArray(c+801,(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT____Vcellinp__dfp_queue__data_in),154); + vcdp->chgBit(c+841,(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__dfp_queue__DOT__writing)); + vcdp->chgArray(c+849,(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__core_req_arb__DOT____Vcellinp__reqq_queue__data_in),314); + vcdp->chgBit(c+929,(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__writing)); + vcdp->chgBit(c+937,(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cwb_queue__DOT__reading)); + vcdp->chgBit(c+945,(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__dwb_queue__DOT__reading)); + } +} + +void VVX_cache::traceChgThis__3(VVX_cache__Syms* __restrict vlSymsp, VerilatedVcd* vcdp, uint32_t code) { + VVX_cache* __restrict vlTOPp VL_ATTR_UNUSED = vlSymsp->TOPp; + int c = code; + if (0 && vcdp && c) {} // Prevent unused + // Body + { + vcdp->chgBit(c+953,((((IData)(vlTOPp->VX_cache__DOT__cache_dram_req_arb__DOT__dfqq_pop) + & (~ (IData)((0U != (IData)(vlTOPp->VX_cache__DOT__cache_dram_req_arb__DOT__dram_fill_arb__DOT__use_per_bank_dram_fill_req_valid))))) + & (~ ((~ (IData)((0U != + (0xfU + & (vlTOPp->VX_cache__DOT__cache_dram_req_arb__DOT__dram_fill_arb__DOT____Vcellout__dfqq_queue__data_out[3U] + >> 0x10U))))) + | (IData)(vlTOPp->VX_cache__DOT__cache_dram_req_arb__DOT__dram_fill_arb__DOT__dfqq_queue__DOT__genblk3__DOT__genblk2__DOT__empty_r)))))); + vcdp->chgBit(c+961,(((0U != (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__curr_bank_core_req_valid)) + & (~ (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__full_r))))); + vcdp->chgBit(c+969,((1U & ((~ (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cwb_queue__DOT__genblk3__DOT__genblk2__DOT__empty_r)) + & (IData)(vlTOPp->VX_cache__DOT__per_bank_core_rsp_ready))))); + vcdp->chgBit(c+977,((((((vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT____Vcellout__dwb_queue__data_out[6U] + >> 7U) & (~ (vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT____Vcellout__dwb_queue__data_out[6U] + >> 6U))) + & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__dram_wb_req_fire)) + | (((vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT____Vcellout__dwb_queue__data_out[6U] + >> 6U) & (~ (vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT____Vcellout__dwb_queue__data_out[6U] + >> 7U))) + & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__snp_rsp_fire))) + | (((vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT____Vcellout__dwb_queue__data_out[6U] + >> 7U) & (vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT____Vcellout__dwb_queue__data_out[6U] + >> 6U)) + & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__snp_rsp_fire))))); + vcdp->chgBit(c+985,((((0U != (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__curr_bank_core_req_valid)) + & (~ (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__full_r))) + & (~ (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__full_r))))); + vcdp->chgBit(c+993,(((0U != (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__curr_bank_core_req_valid)) + & (~ (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__full_r))))); + vcdp->chgBit(c+1001,((1U & ((~ (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__cwb_queue__DOT__genblk3__DOT__genblk2__DOT__empty_r)) + & ((IData)(vlTOPp->VX_cache__DOT__per_bank_core_rsp_ready) + >> 1U))))); + vcdp->chgBit(c+1009,((((((vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT____Vcellout__dwb_queue__data_out[6U] + >> 7U) & (~ (vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT____Vcellout__dwb_queue__data_out[6U] + >> 6U))) + & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__dram_wb_req_fire)) + | (((vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT____Vcellout__dwb_queue__data_out[6U] + >> 6U) & (~ (vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT____Vcellout__dwb_queue__data_out[6U] + >> 7U))) + & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__snp_rsp_fire))) + | (((vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT____Vcellout__dwb_queue__data_out[6U] + >> 7U) & (vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT____Vcellout__dwb_queue__data_out[6U] + >> 6U)) + & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__snp_rsp_fire))))); + vcdp->chgBit(c+1017,((((0U != (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__curr_bank_core_req_valid)) + & (~ (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__full_r))) + & (~ (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__full_r))))); + vcdp->chgBit(c+1025,(((0U != (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__curr_bank_core_req_valid)) + & (~ (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__full_r))))); + vcdp->chgBit(c+1033,((1U & ((~ (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__cwb_queue__DOT__genblk3__DOT__genblk2__DOT__empty_r)) + & ((IData)(vlTOPp->VX_cache__DOT__per_bank_core_rsp_ready) + >> 2U))))); + vcdp->chgBit(c+1041,((((((vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT____Vcellout__dwb_queue__data_out[6U] + >> 7U) & (~ (vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT____Vcellout__dwb_queue__data_out[6U] + >> 6U))) + & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__dram_wb_req_fire)) + | (((vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT____Vcellout__dwb_queue__data_out[6U] + >> 6U) & (~ (vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT____Vcellout__dwb_queue__data_out[6U] + >> 7U))) + & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__snp_rsp_fire))) + | (((vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT____Vcellout__dwb_queue__data_out[6U] + >> 7U) & (vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT____Vcellout__dwb_queue__data_out[6U] + >> 6U)) + & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__snp_rsp_fire))))); + vcdp->chgBit(c+1049,((((0U != (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__curr_bank_core_req_valid)) + & (~ (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__full_r))) + & (~ (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__full_r))))); + vcdp->chgBit(c+1057,(((0U != (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__curr_bank_core_req_valid)) + & (~ (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__full_r))))); + vcdp->chgBit(c+1065,((1U & ((~ (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cwb_queue__DOT__genblk3__DOT__genblk2__DOT__empty_r)) + & ((IData)(vlTOPp->VX_cache__DOT__per_bank_core_rsp_ready) + >> 3U))))); + vcdp->chgBit(c+1073,((((((vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT____Vcellout__dwb_queue__data_out[6U] + >> 7U) & (~ (vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT____Vcellout__dwb_queue__data_out[6U] + >> 6U))) + & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__dram_wb_req_fire)) + | (((vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT____Vcellout__dwb_queue__data_out[6U] + >> 6U) & (~ (vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT____Vcellout__dwb_queue__data_out[6U] + >> 7U))) + & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__snp_rsp_fire))) + | (((vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT____Vcellout__dwb_queue__data_out[6U] + >> 7U) & (vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT____Vcellout__dwb_queue__data_out[6U] + >> 6U)) + & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__snp_rsp_fire))))); + vcdp->chgBit(c+1081,((((0U != (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__curr_bank_core_req_valid)) + & (~ (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__full_r))) + & (~ (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__full_r))))); + } +} + +void VVX_cache::traceChgThis__4(VVX_cache__Syms* __restrict vlSymsp, VerilatedVcd* vcdp, uint32_t code) { + VVX_cache* __restrict vlTOPp VL_ATTR_UNUSED = vlSymsp->TOPp; + int c = code; + if (0 && vcdp && c) {} // Prevent unused + // Variables + WData/*127:0*/ __Vtemp662[4]; + WData/*127:0*/ __Vtemp681[4]; + WData/*127:0*/ __Vtemp700[4]; + WData/*127:0*/ __Vtemp719[4]; + WData/*127:0*/ __Vtemp637[4]; + WData/*127:0*/ __Vtemp638[4]; + WData/*127:0*/ __Vtemp639[4]; + WData/*127:0*/ __Vtemp640[4]; + WData/*127:0*/ __Vtemp643[4]; + WData/*127:0*/ __Vtemp644[4]; + WData/*127:0*/ __Vtemp649[4]; + WData/*127:0*/ __Vtemp655[4]; + WData/*127:0*/ __Vtemp656[4]; + WData/*127:0*/ __Vtemp659[4]; + WData/*127:0*/ __Vtemp660[4]; + WData/*127:0*/ __Vtemp661[4]; + WData/*127:0*/ __Vtemp663[4]; + WData/*127:0*/ __Vtemp668[4]; + WData/*127:0*/ __Vtemp674[4]; + WData/*127:0*/ __Vtemp675[4]; + WData/*127:0*/ __Vtemp678[4]; + WData/*127:0*/ __Vtemp679[4]; + WData/*127:0*/ __Vtemp680[4]; + WData/*127:0*/ __Vtemp682[4]; + WData/*127:0*/ __Vtemp687[4]; + WData/*127:0*/ __Vtemp693[4]; + WData/*127:0*/ __Vtemp694[4]; + WData/*127:0*/ __Vtemp697[4]; + WData/*127:0*/ __Vtemp698[4]; + WData/*127:0*/ __Vtemp699[4]; + WData/*127:0*/ __Vtemp701[4]; + WData/*127:0*/ __Vtemp706[4]; + WData/*127:0*/ __Vtemp712[4]; + WData/*127:0*/ __Vtemp713[4]; + WData/*127:0*/ __Vtemp716[4]; + WData/*127:0*/ __Vtemp717[4]; + WData/*127:0*/ __Vtemp718[4]; + // Body + { + vcdp->chgBus(c+1089,(vlTOPp->VX_cache__DOT__per_bank_core_req_ready),4); + vcdp->chgBus(c+1097,(vlTOPp->VX_cache__DOT__per_bank_core_rsp_valid),4); + vcdp->chgBus(c+1105,(vlTOPp->VX_cache__DOT__per_bank_core_rsp_tid),8); + vcdp->chgArray(c+1113,(vlTOPp->VX_cache__DOT__per_bank_core_rsp_data),128); + vcdp->chgArray(c+1145,(vlTOPp->VX_cache__DOT__per_bank_core_rsp_tag),168); + vcdp->chgBus(c+1193,(vlTOPp->VX_cache__DOT__per_bank_dram_fill_req_valid),4); + vcdp->chgArray(c+1201,(vlTOPp->VX_cache__DOT__per_bank_dram_fill_req_addr),112); + vcdp->chgBus(c+1233,(vlTOPp->VX_cache__DOT__per_bank_dram_fill_rsp_ready),4); + vcdp->chgBus(c+1241,(vlTOPp->VX_cache__DOT__per_bank_dram_wb_req_valid),4); + vcdp->chgQuad(c+1249,(vlTOPp->VX_cache__DOT__per_bank_dram_wb_req_byteen),64); + vcdp->chgArray(c+1265,(vlTOPp->VX_cache__DOT__per_bank_dram_wb_req_addr),112); + vcdp->chgArray(c+1297,(vlTOPp->VX_cache__DOT__per_bank_dram_wb_req_data),512); + vcdp->chgBus(c+1425,(vlTOPp->VX_cache__DOT__per_bank_snp_req_ready),4); + vcdp->chgBus(c+1433,(vlTOPp->VX_cache__DOT__per_bank_snp_rsp_valid),4); + vcdp->chgArray(c+1441,(vlTOPp->VX_cache__DOT__per_bank_snp_rsp_tag),112); + vcdp->chgBus(c+1473,((3U & (vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT____Vcellout__cwb_queue__data_out[2U] + >> 0xaU))),2); + vcdp->chgBus(c+1481,(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT____Vcellout__cwb_queue__data_out[0U]),32); + vcdp->chgQuad(c+1489,((VL_ULL(0x3ffffffffff) + & (((QData)((IData)( + vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT____Vcellout__cwb_queue__data_out[2U])) + << 0x20U) | (QData)((IData)( + vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT____Vcellout__cwb_queue__data_out[1U]))))),42); + vcdp->chgBit(c+1505,((((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__miss_add_unqual) + & ((~ (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__mrvq_init_ready_state_st2)) + | ((vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__st_1e_2__DOT__value[9U] + >> 0x1aU) & (~ + (vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__st_1e_2__DOT__value[9U] + >> 0x1bU))))) + & (~ (((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__dwbq_push_stall) + | (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__mrvq_push_stall)) + | (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cwbq_push_stall)))))); + vcdp->chgBit(c+1513,(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__curr_bank_dram_wb_req_valid)); + vcdp->chgBus(c+1521,((0xffffU & ((vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT____Vcellout__dwb_queue__data_out[6U] + << 0xaU) + | (vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT____Vcellout__dwb_queue__data_out[5U] + >> 0x16U)))),16); + vcdp->chgBus(c+1529,((0x3ffffffU & ((vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT____Vcellout__dwb_queue__data_out[5U] + << 4U) + | (vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT____Vcellout__dwb_queue__data_out[4U] + >> 0x1cU)))),26); + __Vtemp637[0U] = ((vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT____Vcellout__dwb_queue__data_out[1U] + << 4U) | (vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT____Vcellout__dwb_queue__data_out[0U] + >> 0x1cU)); + __Vtemp637[1U] = ((vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT____Vcellout__dwb_queue__data_out[2U] + << 4U) | (vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT____Vcellout__dwb_queue__data_out[1U] + >> 0x1cU)); + __Vtemp637[2U] = ((vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT____Vcellout__dwb_queue__data_out[3U] + << 4U) | (vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT____Vcellout__dwb_queue__data_out[2U] + >> 0x1cU)); + __Vtemp637[3U] = ((vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT____Vcellout__dwb_queue__data_out[4U] + << 4U) | (vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT____Vcellout__dwb_queue__data_out[3U] + >> 0x1cU)); + vcdp->chgArray(c+1537,(__Vtemp637),128); + vcdp->chgBit(c+1569,(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__curr_bank_snp_rsp_valid)); + vcdp->chgBus(c+1577,((0xfffffffU & vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT____Vcellout__dwb_queue__data_out[0U])),28); + vcdp->chgBus(c+1585,((3U & (vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT____Vcellout__cwb_queue__data_out[2U] + >> 0xaU))),2); + vcdp->chgBus(c+1593,(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT____Vcellout__cwb_queue__data_out[0U]),32); + vcdp->chgQuad(c+1601,((VL_ULL(0x3ffffffffff) + & (((QData)((IData)( + vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT____Vcellout__cwb_queue__data_out[2U])) + << 0x20U) | (QData)((IData)( + vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT____Vcellout__cwb_queue__data_out[1U]))))),42); + vcdp->chgBit(c+1617,((((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__miss_add_unqual) + & ((~ (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__mrvq_init_ready_state_st2)) + | ((vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__st_1e_2__DOT__value[9U] + >> 0x1aU) & (~ + (vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__st_1e_2__DOT__value[9U] + >> 0x1bU))))) + & (~ (((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__dwbq_push_stall) + | (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__mrvq_push_stall)) + | (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__cwbq_push_stall)))))); + vcdp->chgBit(c+1625,(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__curr_bank_dram_wb_req_valid)); + vcdp->chgBus(c+1633,((0xffffU & ((vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT____Vcellout__dwb_queue__data_out[6U] + << 0xaU) + | (vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT____Vcellout__dwb_queue__data_out[5U] + >> 0x16U)))),16); + vcdp->chgBus(c+1641,((0x3ffffffU & ((vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT____Vcellout__dwb_queue__data_out[5U] + << 4U) + | (vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT____Vcellout__dwb_queue__data_out[4U] + >> 0x1cU)))),26); + __Vtemp638[0U] = ((vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT____Vcellout__dwb_queue__data_out[1U] + << 4U) | (vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT____Vcellout__dwb_queue__data_out[0U] + >> 0x1cU)); + __Vtemp638[1U] = ((vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT____Vcellout__dwb_queue__data_out[2U] + << 4U) | (vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT____Vcellout__dwb_queue__data_out[1U] + >> 0x1cU)); + __Vtemp638[2U] = ((vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT____Vcellout__dwb_queue__data_out[3U] + << 4U) | (vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT____Vcellout__dwb_queue__data_out[2U] + >> 0x1cU)); + __Vtemp638[3U] = ((vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT____Vcellout__dwb_queue__data_out[4U] + << 4U) | (vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT____Vcellout__dwb_queue__data_out[3U] + >> 0x1cU)); + vcdp->chgArray(c+1649,(__Vtemp638),128); + vcdp->chgBit(c+1681,(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__curr_bank_snp_rsp_valid)); + vcdp->chgBus(c+1689,((0xfffffffU & vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT____Vcellout__dwb_queue__data_out[0U])),28); + vcdp->chgBus(c+1697,((3U & (vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT____Vcellout__cwb_queue__data_out[2U] + >> 0xaU))),2); + vcdp->chgBus(c+1705,(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT____Vcellout__cwb_queue__data_out[0U]),32); + vcdp->chgQuad(c+1713,((VL_ULL(0x3ffffffffff) + & (((QData)((IData)( + vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT____Vcellout__cwb_queue__data_out[2U])) + << 0x20U) | (QData)((IData)( + vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT____Vcellout__cwb_queue__data_out[1U]))))),42); + vcdp->chgBit(c+1729,((((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__miss_add_unqual) + & ((~ (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__mrvq_init_ready_state_st2)) + | ((vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__st_1e_2__DOT__value[9U] + >> 0x1aU) & (~ + (vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__st_1e_2__DOT__value[9U] + >> 0x1bU))))) + & (~ (((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__dwbq_push_stall) + | (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__mrvq_push_stall)) + | (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__cwbq_push_stall)))))); + vcdp->chgBit(c+1737,(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__curr_bank_dram_wb_req_valid)); + vcdp->chgBus(c+1745,((0xffffU & ((vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT____Vcellout__dwb_queue__data_out[6U] + << 0xaU) + | (vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT____Vcellout__dwb_queue__data_out[5U] + >> 0x16U)))),16); + vcdp->chgBus(c+1753,((0x3ffffffU & ((vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT____Vcellout__dwb_queue__data_out[5U] + << 4U) + | (vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT____Vcellout__dwb_queue__data_out[4U] + >> 0x1cU)))),26); + __Vtemp639[0U] = ((vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT____Vcellout__dwb_queue__data_out[1U] + << 4U) | (vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT____Vcellout__dwb_queue__data_out[0U] + >> 0x1cU)); + __Vtemp639[1U] = ((vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT____Vcellout__dwb_queue__data_out[2U] + << 4U) | (vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT____Vcellout__dwb_queue__data_out[1U] + >> 0x1cU)); + __Vtemp639[2U] = ((vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT____Vcellout__dwb_queue__data_out[3U] + << 4U) | (vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT____Vcellout__dwb_queue__data_out[2U] + >> 0x1cU)); + __Vtemp639[3U] = ((vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT____Vcellout__dwb_queue__data_out[4U] + << 4U) | (vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT____Vcellout__dwb_queue__data_out[3U] + >> 0x1cU)); + vcdp->chgArray(c+1761,(__Vtemp639),128); + vcdp->chgBit(c+1793,(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__curr_bank_snp_rsp_valid)); + vcdp->chgBus(c+1801,((0xfffffffU & vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT____Vcellout__dwb_queue__data_out[0U])),28); + vcdp->chgBus(c+1809,((3U & (vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT____Vcellout__cwb_queue__data_out[2U] + >> 0xaU))),2); + vcdp->chgBus(c+1817,(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT____Vcellout__cwb_queue__data_out[0U]),32); + vcdp->chgQuad(c+1825,((VL_ULL(0x3ffffffffff) + & (((QData)((IData)( + vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT____Vcellout__cwb_queue__data_out[2U])) + << 0x20U) | (QData)((IData)( + vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT____Vcellout__cwb_queue__data_out[1U]))))),42); + vcdp->chgBit(c+1841,((((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__miss_add_unqual) + & ((~ (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__mrvq_init_ready_state_st2)) + | ((vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__st_1e_2__DOT__value[9U] + >> 0x1aU) & (~ + (vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__st_1e_2__DOT__value[9U] + >> 0x1bU))))) + & (~ (((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__dwbq_push_stall) + | (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__mrvq_push_stall)) + | (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cwbq_push_stall)))))); + vcdp->chgBit(c+1849,(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__curr_bank_dram_wb_req_valid)); + vcdp->chgBus(c+1857,((0xffffU & ((vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT____Vcellout__dwb_queue__data_out[6U] + << 0xaU) + | (vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT____Vcellout__dwb_queue__data_out[5U] + >> 0x16U)))),16); + vcdp->chgBus(c+1865,((0x3ffffffU & ((vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT____Vcellout__dwb_queue__data_out[5U] + << 4U) + | (vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT____Vcellout__dwb_queue__data_out[4U] + >> 0x1cU)))),26); + __Vtemp640[0U] = ((vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT____Vcellout__dwb_queue__data_out[1U] + << 4U) | (vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT____Vcellout__dwb_queue__data_out[0U] + >> 0x1cU)); + __Vtemp640[1U] = ((vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT____Vcellout__dwb_queue__data_out[2U] + << 4U) | (vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT____Vcellout__dwb_queue__data_out[1U] + >> 0x1cU)); + __Vtemp640[2U] = ((vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT____Vcellout__dwb_queue__data_out[3U] + << 4U) | (vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT____Vcellout__dwb_queue__data_out[2U] + >> 0x1cU)); + __Vtemp640[3U] = ((vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT____Vcellout__dwb_queue__data_out[4U] + << 4U) | (vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT____Vcellout__dwb_queue__data_out[3U] + >> 0x1cU)); + vcdp->chgArray(c+1873,(__Vtemp640),128); + vcdp->chgBit(c+1905,(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__curr_bank_snp_rsp_valid)); + vcdp->chgBus(c+1913,((0xfffffffU & vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT____Vcellout__dwb_queue__data_out[0U])),28); + vcdp->chgBit(c+1921,(vlTOPp->VX_cache__DOT__cache_dram_req_arb__DOT__dwb_valid)); + vcdp->chgBit(c+1929,(vlTOPp->VX_cache__DOT__cache_dram_req_arb__DOT__dfqq_req)); + vcdp->chgBus(c+1937,(((0x6fU >= (0x7fU & ((IData)(0x1cU) + * (IData)(vlTOPp->VX_cache__DOT__cache_dram_req_arb__DOT__dram_fill_arb__DOT__qual_request_index)))) + ? (0xfffffffU & (((0U + == + (0x1fU + & ((IData)(0x1cU) + * (IData)(vlTOPp->VX_cache__DOT__cache_dram_req_arb__DOT__dram_fill_arb__DOT__qual_request_index)))) + ? 0U + : + (vlTOPp->VX_cache__DOT__cache_dram_req_arb__DOT__dram_fill_arb__DOT__qual_bank_dram_fill_req_addr[ + ((IData)(1U) + + + (3U + & (((IData)(0x1cU) + * (IData)(vlTOPp->VX_cache__DOT__cache_dram_req_arb__DOT__dram_fill_arb__DOT__qual_request_index)) + >> 5U)))] + << + ((IData)(0x20U) + - + (0x1fU + & ((IData)(0x1cU) + * (IData)(vlTOPp->VX_cache__DOT__cache_dram_req_arb__DOT__dram_fill_arb__DOT__qual_request_index)))))) + | (vlTOPp->VX_cache__DOT__cache_dram_req_arb__DOT__dram_fill_arb__DOT__qual_bank_dram_fill_req_addr[ + (3U + & (((IData)(0x1cU) + * (IData)(vlTOPp->VX_cache__DOT__cache_dram_req_arb__DOT__dram_fill_arb__DOT__qual_request_index)) + >> 5U))] + >> + (0x1fU + & ((IData)(0x1cU) + * (IData)(vlTOPp->VX_cache__DOT__cache_dram_req_arb__DOT__dram_fill_arb__DOT__qual_request_index)))))) + : 0U)),28); + vcdp->chgBit(c+1945,((1U & (~ (IData)(vlTOPp->VX_cache__DOT__cache_dram_req_arb__DOT__dram_fill_arb__DOT__qual_has_request))))); + vcdp->chgBit(c+1953,((0U != (IData)(vlTOPp->VX_cache__DOT__per_bank_dram_fill_req_valid)))); + vcdp->chgBus(c+1961,(vlTOPp->VX_cache__DOT__cache_dram_req_arb__DOT__dwb_bank),2); + vcdp->chgBit(c+1969,(vlTOPp->VX_cache__DOT__cache_dram_req_arb__DOT__prfqq__DOT__update_use)); + vcdp->chgBit(c+1977,(vlTOPp->VX_cache__DOT__cache_dram_req_arb__DOT__prfqq__DOT__pfq_queue__DOT__reading)); + vcdp->chgBit(c+1985,(vlTOPp->VX_cache__DOT__cache_dram_req_arb__DOT__prfqq__DOT__pfq_queue__DOT__writing)); + vcdp->chgBus(c+1993,((0xfU & (vlTOPp->VX_cache__DOT__cache_dram_req_arb__DOT__dram_fill_arb__DOT____Vcellout__dfqq_queue__data_out[3U] + >> 0x10U))),4); + __Vtemp643[0U] = vlTOPp->VX_cache__DOT__cache_dram_req_arb__DOT__dram_fill_arb__DOT____Vcellout__dfqq_queue__data_out[0U]; + __Vtemp643[1U] = vlTOPp->VX_cache__DOT__cache_dram_req_arb__DOT__dram_fill_arb__DOT____Vcellout__dfqq_queue__data_out[1U]; + __Vtemp643[2U] = vlTOPp->VX_cache__DOT__cache_dram_req_arb__DOT__dram_fill_arb__DOT____Vcellout__dfqq_queue__data_out[2U]; + __Vtemp643[3U] = (0xffffU & vlTOPp->VX_cache__DOT__cache_dram_req_arb__DOT__dram_fill_arb__DOT____Vcellout__dfqq_queue__data_out[3U]); + vcdp->chgArray(c+2001,(__Vtemp643),112); + vcdp->chgBus(c+2033,(vlTOPp->VX_cache__DOT__cache_dram_req_arb__DOT__dram_fill_arb__DOT__use_per_bqual_bank_dram_fill_req_valid),4); + vcdp->chgArray(c+2041,(vlTOPp->VX_cache__DOT__cache_dram_req_arb__DOT__dram_fill_arb__DOT__qual_bank_dram_fill_req_addr),112); + vcdp->chgBus(c+2073,(((IData)(vlTOPp->VX_cache__DOT__cache_dram_req_arb__DOT__dram_fill_arb__DOT__use_per_bqual_bank_dram_fill_req_valid) + & (~ ((IData)(1U) << (IData)(vlTOPp->VX_cache__DOT__cache_dram_req_arb__DOT__dram_fill_arb__DOT__qual_request_index))))),4); + vcdp->chgBit(c+2081,((1U & ((~ (IData)((0U + != + (0xfU + & (vlTOPp->VX_cache__DOT__cache_dram_req_arb__DOT__dram_fill_arb__DOT____Vcellout__dfqq_queue__data_out[3U] + >> 0x10U))))) + | (IData)(vlTOPp->VX_cache__DOT__cache_dram_req_arb__DOT__dram_fill_arb__DOT__dfqq_queue__DOT__genblk3__DOT__genblk2__DOT__empty_r))))); + vcdp->chgBit(c+2089,(((0U != (IData)(vlTOPp->VX_cache__DOT__per_bank_dram_fill_req_valid)) + & (~ (IData)(vlTOPp->VX_cache__DOT__cache_dram_req_arb__DOT__dram_fill_arb__DOT__dfqq_queue__DOT__genblk3__DOT__genblk2__DOT__full_r))))); + vcdp->chgBus(c+2097,(vlTOPp->VX_cache__DOT__cache_dram_req_arb__DOT__dram_fill_arb__DOT__qual_request_index),2); + vcdp->chgBit(c+2105,(vlTOPp->VX_cache__DOT__cache_dram_req_arb__DOT__dram_fill_arb__DOT__qual_has_request)); + vcdp->chgArray(c+2113,(vlTOPp->VX_cache__DOT__cache_dram_req_arb__DOT__dram_fill_arb__DOT____Vcellinp__dfqq_queue__data_in),116); + vcdp->chgArray(c+2145,(vlTOPp->VX_cache__DOT__cache_dram_req_arb__DOT__dram_fill_arb__DOT____Vcellout__dfqq_queue__data_out),116); + vcdp->chgBit(c+2177,(vlTOPp->VX_cache__DOT__cache_dram_req_arb__DOT__dram_fill_arb__DOT__dfqq_queue__DOT__writing)); + vcdp->chgBus(c+2185,(vlTOPp->VX_cache__DOT__cache_dram_req_arb__DOT__dram_fill_arb__DOT__sel_bank__DOT__genblk2__DOT__grant_onehot_r),4); + vcdp->chgBus(c+2193,(vlTOPp->VX_cache__DOT__cache_dram_req_arb__DOT__dram_fill_arb__DOT__sel_bank__DOT__genblk2__DOT__priority_encoder__DOT__i),32); + vcdp->chgBus(c+2201,(vlTOPp->VX_cache__DOT__cache_dram_req_arb__DOT__sel_dwb__DOT__genblk2__DOT__grant_onehot_r),4); + vcdp->chgBus(c+2209,(vlTOPp->VX_cache__DOT__cache_dram_req_arb__DOT__sel_dwb__DOT__genblk2__DOT__priority_encoder__DOT__i),32); + vcdp->chgArray(c+2217,(vlTOPp->VX_cache__DOT____Vcellout__cache_core_rsp_merge__core_rsp_data),128); + vcdp->chgQuad(c+2249,(((0xa7U >= (0xffU & ((IData)(0x2aU) + * (IData)(vlTOPp->VX_cache__DOT__cache_core_rsp_merge__DOT__main_bank_index)))) + ? (VL_ULL(0x3ffffffffff) + & (((0U == (0x1fU + & ((IData)(0x2aU) + * (IData)(vlTOPp->VX_cache__DOT__cache_core_rsp_merge__DOT__main_bank_index)))) + ? VL_ULL(0) + : ((QData)((IData)( + vlTOPp->VX_cache__DOT__per_bank_core_rsp_tag[ + ((IData)(2U) + + + (7U + & (((IData)(0x2aU) + * (IData)(vlTOPp->VX_cache__DOT__cache_core_rsp_merge__DOT__main_bank_index)) + >> 5U)))])) + << ((IData)(0x40U) + - (0x1fU + & ((IData)(0x2aU) + * (IData)(vlTOPp->VX_cache__DOT__cache_core_rsp_merge__DOT__main_bank_index)))))) + | (((QData)((IData)( + vlTOPp->VX_cache__DOT__per_bank_core_rsp_tag[ + ((IData)(1U) + + + (7U + & (((IData)(0x2aU) + * (IData)(vlTOPp->VX_cache__DOT__cache_core_rsp_merge__DOT__main_bank_index)) + >> 5U)))])) + << ((0U == + (0x1fU + & ((IData)(0x2aU) + * (IData)(vlTOPp->VX_cache__DOT__cache_core_rsp_merge__DOT__main_bank_index)))) + ? 0x20U + : ((IData)(0x20U) + - + (0x1fU + & ((IData)(0x2aU) + * (IData)(vlTOPp->VX_cache__DOT__cache_core_rsp_merge__DOT__main_bank_index)))))) + | ((QData)((IData)( + vlTOPp->VX_cache__DOT__per_bank_core_rsp_tag[ + (7U + & (((IData)(0x2aU) + * (IData)(vlTOPp->VX_cache__DOT__cache_core_rsp_merge__DOT__main_bank_index)) + >> 5U))])) + >> (0x1fU + & ((IData)(0x2aU) + * (IData)(vlTOPp->VX_cache__DOT__cache_core_rsp_merge__DOT__main_bank_index))))))) + : VL_ULL(0))),42); + vcdp->chgBus(c+2265,(vlTOPp->VX_cache__DOT__cache_core_rsp_merge__DOT__main_bank_index),2); + vcdp->chgBus(c+2273,(vlTOPp->VX_cache__DOT__cache_core_rsp_merge__DOT__per_bank_core_rsp_pop_unqual),4); + vcdp->chgBus(c+2281,(vlTOPp->VX_cache__DOT__cache_core_rsp_merge__DOT__sel_bank__DOT__genblk2__DOT__grant_onehot_r),4); + vcdp->chgBit(c+2289,(vlTOPp->VX_cache__DOT__cache_core_rsp_merge__DOT__sel_bank__DOT__grant_valid)); + vcdp->chgBus(c+2297,((((IData)(vlTOPp->VX_cache__DOT__cache_core_rsp_merge__DOT__sel_bank__DOT__genblk2__DOT__requests_use) + & (~ (IData)(vlTOPp->VX_cache__DOT__cache_core_rsp_merge__DOT__sel_bank__DOT__genblk2__DOT__grant_onehot_r))) + | (((IData)(vlTOPp->VX_cache__DOT__cache_core_rsp_merge__DOT__sel_bank__DOT__genblk2__DOT__refill_original) + ^ (IData)(vlTOPp->VX_cache__DOT__per_bank_core_rsp_valid)) + & (~ (IData)(vlTOPp->VX_cache__DOT__cache_core_rsp_merge__DOT__sel_bank__DOT__genblk2__DOT__refill_original))))),4); + vcdp->chgBus(c+2305,((((IData)(vlTOPp->VX_cache__DOT__cache_core_rsp_merge__DOT__sel_bank__DOT__genblk2__DOT__refill_original) + ^ (IData)(vlTOPp->VX_cache__DOT__per_bank_core_rsp_valid)) + & (~ (IData)(vlTOPp->VX_cache__DOT__cache_core_rsp_merge__DOT__sel_bank__DOT__genblk2__DOT__refill_original)))),4); + vcdp->chgBus(c+2313,(vlTOPp->VX_cache__DOT__cache_core_rsp_merge__DOT__sel_bank__DOT__genblk2__DOT__priority_encoder__DOT__i),32); + vcdp->chgBus(c+2321,(vlTOPp->VX_cache__DOT__snp_rsp_arb__DOT__fsq_bank),2); + vcdp->chgBit(c+2329,(vlTOPp->VX_cache__DOT__snp_rsp_arb__DOT__fsq_valid)); + vcdp->chgBus(c+2337,(vlTOPp->VX_cache__DOT__snp_rsp_arb__DOT__sel_ffsq__DOT__genblk2__DOT__grant_onehot_r),4); + vcdp->chgBus(c+2345,(vlTOPp->VX_cache__DOT__snp_rsp_arb__DOT__sel_ffsq__DOT__genblk2__DOT__priority_encoder__DOT__i),32); + vcdp->chgBit(c+2353,(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__snrq_pop)); + vcdp->chgBus(c+2361,((0x3ffffffU & (IData)( + (vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT____Vcellout__snp_req_queue__data_out + >> 0x1dU)))),26); + vcdp->chgBit(c+2369,((1U & (IData)((vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT____Vcellout__snp_req_queue__data_out + >> 0x1cU))))); + vcdp->chgBus(c+2377,((0xfffffffU & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT____Vcellout__snp_req_queue__data_out))),28); + vcdp->chgBit(c+2385,(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__dfpq_pop)); + vcdp->chgBus(c+2393,((0x3ffffffU & vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT____Vcellout__dfp_queue__data_out[4U])),26); + __Vtemp644[0U] = vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT____Vcellout__dfp_queue__data_out[0U]; + __Vtemp644[1U] = vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT____Vcellout__dfp_queue__data_out[1U]; + __Vtemp644[2U] = vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT____Vcellout__dfp_queue__data_out[2U]; + __Vtemp644[3U] = vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT____Vcellout__dfp_queue__data_out[3U]; + vcdp->chgArray(c+2401,(__Vtemp644),128); + vcdp->chgBit(c+2433,(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__reqq_pop)); + vcdp->chgBit(c+2441,((1U & (~ (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__core_req_arb__DOT__qual_has_request))))); + vcdp->chgBit(c+2449,(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__core_req_arb__DOT__qual_has_request)); + vcdp->chgBus(c+2457,(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__core_req_arb__DOT__qual_request_index),2); + vcdp->chgBit(c+2465,(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__reqq_req_rw_st0)); + vcdp->chgBus(c+2473,((0xfU & ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__core_req_arb__DOT__use_per_byteen) + >> (0xfU & ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__core_req_arb__DOT__qual_request_index) + << 2U))))),4); + vcdp->chgBus(c+2481,(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__reqq_req_addr_st0),30); + vcdp->chgBus(c+2489,((((0U == (0x1fU & ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__core_req_arb__DOT__qual_request_index) + << 5U))) + ? 0U : (vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__core_req_arb__DOT__use_per_writedata[ + ((IData)(1U) + + (3U & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__core_req_arb__DOT__qual_request_index)))] + << ((IData)(0x20U) + - (0x1fU + & ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__core_req_arb__DOT__qual_request_index) + << 5U))))) + | (vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__core_req_arb__DOT__use_per_writedata[ + (3U & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__core_req_arb__DOT__qual_request_index))] + >> (0x1fU & ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__core_req_arb__DOT__qual_request_index) + << 5U))))),32); + vcdp->chgBit(c+2497,(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__mrvq_pop)); + vcdp->chgBit(c+2505,(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cache_miss_resrv__DOT__dequeue_possible)); + vcdp->chgBit(c+2513,(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__mrvq_rw_st0)); + vcdp->chgBit(c+2521,((0U != (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cache_miss_resrv__DOT__valid_address_match)))); + vcdp->chgBit(c+2529,(((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__miss_add_because_miss) + & (((0x3ffffffU & ((vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__st_1e_2__DOT__value[9U] + << 7U) + | (vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__st_1e_2__DOT__value[8U] + >> 0x19U))) + == vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__addr_st1 + [0U]) & (~ (vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__st_1e_2__DOT__value[9U] + >> 0x14U)))))); + vcdp->chgBit(c+2537,(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__force_request_miss_st1e)); + vcdp->chgBit(c+2545,(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__recover_mrvq_state_st2)); + vcdp->chgBit(c+2553,(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__mrvq_push_stall)); + vcdp->chgBit(c+2561,(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cwbq_push_stall)); + vcdp->chgBit(c+2569,(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__dwbq_push_stall)); + vcdp->chgBit(c+2577,(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__dram_fill_req_stall)); + vcdp->chgBit(c+2585,(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__stall_bank_pipe)); + vcdp->chgBit(c+2593,(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__is_fill_in_pipe)); + vcdp->chgBit(c+2601,(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__is_fill_st1[0])); + vcdp->chgBit(c+2609,(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__going_to_write_st1[0])); + vcdp->chgBit(c+2617,(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__dfpq_pop_unqual)); + vcdp->chgBit(c+2625,(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__reqq_pop_unqual)); + vcdp->chgBit(c+2633,(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__snrq_pop_unqual)); + vcdp->chgBit(c+2641,(((((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__dfpq_pop) + | (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__mrvq_pop)) + | (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__reqq_pop)) + | (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__snrq_pop)))); + vcdp->chgBus(c+2649,((0x3ffffffU & ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__dfpq_pop_unqual) + ? (0x3ffffffU + & vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT____Vcellout__dfp_queue__data_out[4U]) + : ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cache_miss_resrv__DOT__dequeue_possible) + ? + ((0x19fU + >= + (0x1ffU + & ((IData)(0x1aU) + * (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr)))) + ? + (0x3ffffffU + & (((0U + == + (0x1fU + & ((IData)(0x1aU) + * (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr)))) + ? 0U + : + (vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cache_miss_resrv__DOT__addr_table[ + ((IData)(1U) + + + (0xfU + & (((IData)(0x1aU) + * (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr)) + >> 5U)))] + << + ((IData)(0x20U) + - + (0x1fU + & ((IData)(0x1aU) + * (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr)))))) + | (vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cache_miss_resrv__DOT__addr_table[ + (0xfU + & (((IData)(0x1aU) + * (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr)) + >> 5U))] + >> + (0x1fU + & ((IData)(0x1aU) + * (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr)))))) + : 0U) + : + ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__reqq_pop_unqual) + ? + (0x3ffffffU + & (vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__reqq_req_addr_st0 + >> 4U)) + : + ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__snrq_pop_unqual) + ? + (0x3ffffffU + & (IData)( + (vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT____Vcellout__snp_req_queue__data_out + >> 0x1dU))) + : 0U)))))),26); + vcdp->chgBus(c+2657,((3U & ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__reqq_pop_unqual) + ? (3U & vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__reqq_req_addr_st0) + : ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cache_miss_resrv__DOT__dequeue_possible) + ? (3U & (( + vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cache_miss_resrv__DOT__metadata_table + [vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr][1U] + << 0x1eU) + | (vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cache_miss_resrv__DOT__metadata_table + [vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr][0U] + >> 2U))) + : 0U)))),2); + vcdp->chgBus(c+2665,(((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cache_miss_resrv__DOT__dequeue_possible) + ? ((vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cache_miss_resrv__DOT__metadata_table + [vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr][2U] + << 0xbU) | (vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cache_miss_resrv__DOT__metadata_table + [vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr][1U] + >> 0x15U)) + : ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__reqq_pop_unqual) + ? (((0U == (0x1fU + & ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__core_req_arb__DOT__qual_request_index) + << 5U))) + ? 0U : (vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__core_req_arb__DOT__use_per_writedata[ + ((IData)(1U) + + + (3U + & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__core_req_arb__DOT__qual_request_index)))] + << + ((IData)(0x20U) + - + (0x1fU + & ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__core_req_arb__DOT__qual_request_index) + << 5U))))) + | (vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__core_req_arb__DOT__use_per_writedata[ + (3U & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__core_req_arb__DOT__qual_request_index))] + >> (0x1fU + & ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__core_req_arb__DOT__qual_request_index) + << 5U)))) + : 0U))),32); + __Vtemp649[0U] = ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__dfpq_pop_unqual) + ? vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT____Vcellout__dfp_queue__data_out[0U] + : 0x39U); + __Vtemp649[1U] = ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__dfpq_pop_unqual) + ? vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT____Vcellout__dfp_queue__data_out[1U] + : 0U); + __Vtemp649[2U] = ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__dfpq_pop_unqual) + ? vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT____Vcellout__dfp_queue__data_out[2U] + : 0U); + __Vtemp649[3U] = ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__dfpq_pop_unqual) + ? vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT____Vcellout__dfp_queue__data_out[3U] + : 0U); + vcdp->chgArray(c+2673,(__Vtemp649),128); + vcdp->chgQuad(c+2705,(((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cache_miss_resrv__DOT__dequeue_possible) + ? ((VL_ULL(0x1ffffffffff80) + & (((QData)((IData)( + vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cache_miss_resrv__DOT__metadata_table + [vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr][2U])) + << 0x3eU) | + (((QData)((IData)( + vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cache_miss_resrv__DOT__metadata_table + [vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr][1U])) + << 0x1eU) + | (VL_ULL(0x3fffffffffffff80) + & ((QData)((IData)( + vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cache_miss_resrv__DOT__metadata_table + [vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr][0U])) + >> 2U))))) + | (QData)((IData)( + (((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__mrvq_rw_st0) + << 6U) + | ((0x3cU + & ((vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cache_miss_resrv__DOT__metadata_table + [vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr][1U] + << 0x1eU) + | (0x3ffffffcU + & (vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cache_miss_resrv__DOT__metadata_table + [vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr][0U] + >> 2U)))) + | (3U + & ((vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cache_miss_resrv__DOT__metadata_table + [vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr][2U] + << 0xdU) + | (vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cache_miss_resrv__DOT__metadata_table + [vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr][1U] + >> 0x13U)))))))) + : ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__reqq_pop_unqual) + ? ((vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__core_req_arb__DOT__use_per_tag + << 7U) | (QData)((IData)( + (((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__reqq_req_rw_st0) + << 6U) + | ((0x3cU + & (((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__core_req_arb__DOT__use_per_byteen) + >> + (0xfU + & ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__core_req_arb__DOT__qual_request_index) + << 2U))) + << 2U)) + | (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__core_req_arb__DOT__qual_request_index)))))) + : ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__snrq_pop_unqual) + ? ((QData)((IData)( + (0xfffffffU + & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT____Vcellout__snp_req_queue__data_out)))) + << 7U) : VL_ULL(0))))),49); + vcdp->chgBit(c+2721,(((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__dfpq_pop_unqual) + ? 1U : (((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cache_miss_resrv__DOT__dequeue_possible) + & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__mrvq_rw_st0)) + ? 1U : (((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__reqq_pop_unqual) + & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__reqq_req_rw_st0)) + ? 1U + : 0U))))); + vcdp->chgBit(c+2729,((1U & ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cache_miss_resrv__DOT__dequeue_possible) + ? (1U & (vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cache_miss_resrv__DOT__metadata_table + [vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr][0U] + >> 1U)) + : ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__snrq_pop_unqual) + ? 1U : 0U))))); + vcdp->chgBit(c+2737,((1U & ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cache_miss_resrv__DOT__dequeue_possible) + ? (1U & vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cache_miss_resrv__DOT__metadata_table + [vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr][0U]) + : ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__snrq_pop_unqual) + ? (1U & (IData)( + (vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT____Vcellout__snp_req_queue__data_out + >> 0x1cU))) + : 0U))))); + vcdp->chgBit(c+2745,(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__valid_st1[0])); + vcdp->chgBus(c+2753,(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__addr_st1[0]),26); + vcdp->chgBus(c+2761,(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__wsel_st1[0]),2); + vcdp->chgBus(c+2769,(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__writeword_st1[0]),32); + vcdp->chgQuad(c+2777,(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__inst_meta_st1[0]),49); + vcdp->chgArray(c+2793,(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__writedata_st1[0]),128); + vcdp->chgBit(c+2825,(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__is_snp_st1[0])); + vcdp->chgBit(c+2833,(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__snp_invalidate_st1[0])); + vcdp->chgBit(c+2841,(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__is_mrvq_st1[0])); + __Vtemp655[0U] = vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__tag_data_access__DOT__read_data_st1c + [0U][0U]; + __Vtemp655[1U] = vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__tag_data_access__DOT__read_data_st1c + [0U][1U]; + __Vtemp655[2U] = vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__tag_data_access__DOT__read_data_st1c + [0U][2U]; + __Vtemp655[3U] = vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__tag_data_access__DOT__read_data_st1c + [0U][3U]; + vcdp->chgBus(c+2849,((((0U == (0x1fU & (vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__wsel_st1 + [0U] + << 5U))) + ? 0U : (__Vtemp655[ + ((IData)(1U) + + (3U & vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__wsel_st1 + [0U]))] + << ((IData)(0x20U) + - (0x1fU + & (vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__wsel_st1 + [0U] + << 5U))))) + | (__Vtemp655[(3U & vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__wsel_st1 + [0U])] + >> (0x1fU & (vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__wsel_st1 + [0U] + << 5U))))),32); + __Vtemp656[0U] = vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__tag_data_access__DOT__read_data_st1c + [0U][0U]; + __Vtemp656[1U] = vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__tag_data_access__DOT__read_data_st1c + [0U][1U]; + __Vtemp656[2U] = vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__tag_data_access__DOT__read_data_st1c + [0U][2U]; + __Vtemp656[3U] = vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__tag_data_access__DOT__read_data_st1c + [0U][3U]; + vcdp->chgArray(c+2857,(__Vtemp656),128); + vcdp->chgBus(c+2889,(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__tag_data_access__DOT__read_tag_st1c + [0U]),20); + vcdp->chgBit(c+2897,(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__miss_st1e)); + vcdp->chgBit(c+2905,(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__dirty_st1e)); + vcdp->chgBus(c+2913,(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__tag_data_access__DOT__read_dirtyb_st1c + [0U]),16); + vcdp->chgQuad(c+2921,((VL_ULL(0x3ffffffffff) + & (vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__inst_meta_st1 + [0U] >> 7U))),42); + vcdp->chgBus(c+2937,((3U & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__inst_meta_st1 + [0U]))),2); + vcdp->chgBit(c+2945,((1U & (IData)((vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__inst_meta_st1 + [0U] >> 6U))))); + vcdp->chgBus(c+2953,((0xfU & (IData)((vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__inst_meta_st1 + [0U] + >> 2U)))),4); + vcdp->chgBit(c+2961,(((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__tag_data_access__DOT__real_writefill) + & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__dirty_st1e)))); + vcdp->chgBit(c+2969,(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__is_snp_st1 + [0U])); + vcdp->chgBit(c+2977,(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__snp_invalidate_st1 + [0U])); + vcdp->chgBit(c+2985,(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__snp_to_mrvq_st1e)); + vcdp->chgBit(c+2993,(((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__snp_to_mrvq_st1e) + | ((((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__force_request_miss_st1e) + & (~ vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__is_snp_st1 + [0U])) & (~ vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__is_fill_st1 + [0U])) + & vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__valid_st1 + [0U])))); + vcdp->chgBit(c+3001,(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__miss_add_because_miss)); + vcdp->chgBit(c+3009,(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__valid_st1 + [0U])); + vcdp->chgBit(c+3017,(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__is_mrvq_st1 + [0U])); + vcdp->chgBit(c+3025,((((vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__valid_st1 + [0U] & vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__is_mrvq_st1 + [0U]) & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__recover_mrvq_state_st2)) + & ((0x3ffffffU & ((vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__st_1e_2__DOT__value[9U] + << 7U) + | (vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__st_1e_2__DOT__value[8U] + >> 0x19U))) + == vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__addr_st1 + [0U])))); + vcdp->chgBus(c+3033,(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__addr_st1 + [0U]),26); + vcdp->chgBit(c+3041,((vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__valid_st1 + [0U] & (~ vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__is_fill_st1 + [0U])))); + vcdp->chgBit(c+3049,(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__mrvq_init_ready_state_st2)); + vcdp->chgBit(c+3057,((((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__miss_add_unqual) + & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__dfpq_pop_unqual)) + & ((0x3ffffffU & ((vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__st_1e_2__DOT__value[9U] + << 7U) + | (vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__st_1e_2__DOT__value[8U] + >> 0x19U))) + == (0x3ffffffU & vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT____Vcellout__dfp_queue__data_out[4U]))))); + vcdp->chgBit(c+3065,((((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__miss_add_unqual) + & vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__is_fill_st1 + [0U]) & ((0x3ffffffU + & ((vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__st_1e_2__DOT__value[9U] + << 7U) + | (vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__st_1e_2__DOT__value[8U] + >> 0x19U))) + == vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__addr_st1 + [0U])))); + vcdp->chgBit(c+3073,(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__miss_add_unqual)); + vcdp->chgBit(c+3081,(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__miss_add)); + vcdp->chgBit(c+3089,(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__miss_add_is_mrvq)); + vcdp->chgBit(c+3097,(((((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cwbq_push_unqual) + & (~ (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cwb_queue__DOT__genblk3__DOT__genblk2__DOT__full_r))) + & (~ (vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__st_1e_2__DOT__value[0U] + >> 6U))) & (~ + (((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__dwbq_push_stall) + | (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__mrvq_push_stall)) + | (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__dram_fill_req_stall)))))); + vcdp->chgBit(c+3105,(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cwbq_push_unqual)); + vcdp->chgBit(c+3113,(((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__miss_add_unqual) + & ((~ (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__mrvq_init_ready_state_st2)) + | ((vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__st_1e_2__DOT__value[9U] + >> 0x1aU) & (~ + (vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__st_1e_2__DOT__value[9U] + >> 0x1bU))))))); + vcdp->chgBit(c+3121,((((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__dwbq_push_unqual) + & (~ (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__genblk2__DOT__full_r))) + & (~ (((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cwbq_push_stall) + | (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__mrvq_push_stall)) + | (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__dram_fill_req_stall)))))); + vcdp->chgBit(c+3129,(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__dwbq_is_dwb_in)); + vcdp->chgBit(c+3137,(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__dwbq_is_snp_in)); + vcdp->chgBit(c+3145,((1U & (vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT____Vcellout__dwb_queue__data_out[6U] + >> 7U)))); + vcdp->chgBit(c+3153,((1U & (vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT____Vcellout__dwb_queue__data_out[6U] + >> 6U)))); + vcdp->chgBit(c+3161,(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__dwbq_push_unqual)); + vcdp->chgQuad(c+3169,(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT____Vcellout__snp_req_queue__data_out),55); + vcdp->chgBit(c+3185,(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__snp_req_queue__DOT__reading)); + vcdp->chgArray(c+3193,(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT____Vcellout__dfp_queue__data_out),154); + vcdp->chgBit(c+3233,(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__dfp_queue__DOT__reading)); + vcdp->chgBus(c+3241,((0xfU & (vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__core_req_arb__DOT____Vcellout__reqq_queue__data_out[9U] + >> 0x16U))),4); + vcdp->chgBus(c+3249,((0xfU & (vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__core_req_arb__DOT____Vcellout__reqq_queue__data_out[9U] + >> 0x12U))),4); + vcdp->chgBus(c+3257,((0xffffU & (vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__core_req_arb__DOT____Vcellout__reqq_queue__data_out[9U] + >> 2U))),16); + __Vtemp659[0U] = ((vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__core_req_arb__DOT____Vcellout__reqq_queue__data_out[6U] + << 0x16U) | (vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__core_req_arb__DOT____Vcellout__reqq_queue__data_out[5U] + >> 0xaU)); + __Vtemp659[1U] = ((vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__core_req_arb__DOT____Vcellout__reqq_queue__data_out[7U] + << 0x16U) | (vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__core_req_arb__DOT____Vcellout__reqq_queue__data_out[6U] + >> 0xaU)); + __Vtemp659[2U] = ((vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__core_req_arb__DOT____Vcellout__reqq_queue__data_out[8U] + << 0x16U) | (vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__core_req_arb__DOT____Vcellout__reqq_queue__data_out[7U] + >> 0xaU)); + __Vtemp659[3U] = (0xffffffU & ((vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__core_req_arb__DOT____Vcellout__reqq_queue__data_out[9U] + << 0x16U) | + (vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__core_req_arb__DOT____Vcellout__reqq_queue__data_out[8U] + >> 0xaU))); + vcdp->chgArray(c+3265,(__Vtemp659),120); + __Vtemp660[0U] = ((vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__core_req_arb__DOT____Vcellout__reqq_queue__data_out[2U] + << 0x16U) | (vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__core_req_arb__DOT____Vcellout__reqq_queue__data_out[1U] + >> 0xaU)); + __Vtemp660[1U] = ((vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__core_req_arb__DOT____Vcellout__reqq_queue__data_out[3U] + << 0x16U) | (vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__core_req_arb__DOT____Vcellout__reqq_queue__data_out[2U] + >> 0xaU)); + __Vtemp660[2U] = ((vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__core_req_arb__DOT____Vcellout__reqq_queue__data_out[4U] + << 0x16U) | (vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__core_req_arb__DOT____Vcellout__reqq_queue__data_out[3U] + >> 0xaU)); + __Vtemp660[3U] = ((vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__core_req_arb__DOT____Vcellout__reqq_queue__data_out[5U] + << 0x16U) | (vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__core_req_arb__DOT____Vcellout__reqq_queue__data_out[4U] + >> 0xaU)); + vcdp->chgArray(c+3297,(__Vtemp660),128); + vcdp->chgQuad(c+3329,((VL_ULL(0x3ffffffffff) + & (((QData)((IData)( + vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__core_req_arb__DOT____Vcellout__reqq_queue__data_out[1U])) + << 0x20U) | (QData)((IData)( + vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__core_req_arb__DOT____Vcellout__reqq_queue__data_out[0U]))))),42); + vcdp->chgBit(c+3345,(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__core_req_arb__DOT__out_empty)); + vcdp->chgBit(c+3353,(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__core_req_arb__DOT__pop_qual)); + vcdp->chgBus(c+3361,((0xfU & ((vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__core_req_arb__DOT____Vcellout__reqq_queue__data_out[9U] + >> 0x16U) & + VL_NEGATE_I((IData)( + (1U + & (~ (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__core_req_arb__DOT__out_empty)))))))),4); + vcdp->chgArray(c+3369,(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__core_req_arb__DOT____Vcellout__reqq_queue__data_out),314); + vcdp->chgBit(c+3449,(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__reading)); + vcdp->chgBus(c+3457,(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__core_req_arb__DOT__sel_bank__DOT__genblk2__DOT__grant_onehot_r),4); + vcdp->chgBus(c+3465,(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__core_req_arb__DOT__sel_bank__DOT__genblk2__DOT__priority_encoder__DOT__i),32); + vcdp->chgArray(c+3473,(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT____Vcellinp__s0_1_c0__in),243); + vcdp->chgBus(c+3537,((0x3fU & vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__addr_st1 + [0U])),6); + vcdp->chgBit(c+3545,(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__is_fill_st1 + [0U])); + vcdp->chgBus(c+3553,(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__writeword_st1 + [0U]),32); + __Vtemp661[0U] = vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__writedata_st1 + [0U][0U]; + __Vtemp661[1U] = vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__writedata_st1 + [0U][1U]; + __Vtemp661[2U] = vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__writedata_st1 + [0U][2U]; + __Vtemp661[3U] = vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__writedata_st1 + [0U][3U]; + vcdp->chgArray(c+3561,(__Vtemp661),128); + vcdp->chgBus(c+3593,(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__wsel_st1 + [0U]),2); + vcdp->chgBit(c+3601,(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__tag_data_access__DOT__read_valid_st1c[0])); + vcdp->chgBit(c+3609,(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__tag_data_access__DOT__read_dirty_st1c[0])); + vcdp->chgBus(c+3617,(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__tag_data_access__DOT__read_dirtyb_st1c[0]),16); + vcdp->chgBus(c+3625,(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__tag_data_access__DOT__read_tag_st1c[0]),20); + vcdp->chgArray(c+3633,(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__tag_data_access__DOT__read_data_st1c[0]),128); + vcdp->chgBit(c+3665,((1U & (IData)((vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__valid + >> (0x3fU + & vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__addr_st1 + [0U])))))); + vcdp->chgBit(c+3673,((1U & (IData)((vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__dirty + >> (0x3fU + & vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__addr_st1 + [0U])))))); + vcdp->chgBus(c+3681,(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__dirtyb + [(0x3fU & vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__addr_st1 + [0U])]),16); + vcdp->chgBus(c+3689,(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__tag + [(0x3fU & vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__addr_st1 + [0U])]),20); + __Vtemp662[0U] = vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__data + [(0x3fU & vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__addr_st1 + [0U])][0U]; + __Vtemp662[1U] = vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__data + [(0x3fU & vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__addr_st1 + [0U])][1U]; + __Vtemp662[2U] = vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__data + [(0x3fU & vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__addr_st1 + [0U])][2U]; + __Vtemp662[3U] = vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__data + [(0x3fU & vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__addr_st1 + [0U])][3U]; + vcdp->chgArray(c+3697,(__Vtemp662),128); + vcdp->chgBit(c+3729,(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__tag_data_access__DOT__read_valid_st1c + [0U])); + vcdp->chgBit(c+3737,(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__tag_data_access__DOT__read_dirty_st1c + [0U])); + vcdp->chgBus(c+3745,(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__tag_data_access__DOT__use_write_enable),16); + vcdp->chgArray(c+3753,(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__tag_data_access__DOT__data_write),128); + vcdp->chgBit(c+3785,(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__tag_data_access__DOT__snoop_hit_no_pending)); + vcdp->chgBit(c+3793,(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__tag_data_access__DOT__tags_match)); + vcdp->chgBit(c+3801,(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__tag_data_access__DOT__real_writefill)); + vcdp->chgBus(c+3809,((0xfffffU & (vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__addr_st1 + [0U] >> 6U))),20); + vcdp->chgBus(c+3817,(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__tag_data_access__DOT__we),16); + vcdp->chgBit(c+3825,(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__tag_data_access__DOT__should_write)); + vcdp->chgBit(c+3833,((((vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__valid_st1 + [0U] & (~ vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__is_snp_st1 + [0U])) & (~ + vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__tag_data_access__DOT__read_valid_st1c + [0U])) + & (~ vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__is_fill_st1 + [0U])))); + vcdp->chgBit(c+3841,(((((vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__valid_st1 + [0U] & (~ vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__is_snp_st1 + [0U])) & vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__tag_data_access__DOT__read_valid_st1c + [0U]) & (~ vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__is_fill_st1 + [0U])) & (~ (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__tag_data_access__DOT__tags_match))))); + vcdp->chgBit(c+3849,(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__tag_data_access__DOT__real_miss)); + vcdp->chgBit(c+3857,((((((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__force_request_miss_st1e) + & (~ vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__is_snp_st1 + [0U])) & (~ vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__is_fill_st1 + [0U])) + & vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__valid_st1 + [0U]) & (~ (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__tag_data_access__DOT__real_miss))))); + vcdp->chgBit(c+3865,(((0U == vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__wsel_st1 + [0U]) & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__tag_data_access__DOT__should_write)))); + vcdp->chgBit(c+3873,(((1U == vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__wsel_st1 + [0U]) & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__tag_data_access__DOT__should_write)))); + vcdp->chgBit(c+3881,(((2U == vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__wsel_st1 + [0U]) & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__tag_data_access__DOT__should_write)))); + vcdp->chgBit(c+3889,(((3U == vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__wsel_st1 + [0U]) & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__tag_data_access__DOT__should_write)))); + vcdp->chgBit(c+3897,((0U != (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__tag_data_access__DOT__use_write_enable)))); + vcdp->chgArray(c+3905,(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__tag_data_access__DOT____Vcellinp__s0_1_c0__in),166); + vcdp->chgArray(c+3953,(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT____Vcellinp__st_1e_2__in),316); + vcdp->chgBus(c+4033,(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cache_miss_resrv__DOT__make_ready),16); + vcdp->chgBus(c+4041,((0xffffU & (((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cache_miss_resrv__DOT__mrvq_push) + & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__mrvq_init_ready_state_st2)) + << (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cache_miss_resrv__DOT__tail_ptr)))),16); + vcdp->chgBus(c+4049,(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cache_miss_resrv__DOT__valid_address_match),16); + vcdp->chgBit(c+4057,(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cache_miss_resrv__DOT__mrvq_push)); + vcdp->chgBit(c+4065,(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cache_miss_resrv__DOT__mrvq_pop)); + vcdp->chgBit(c+4073,(((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__miss_add) + & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__miss_add_is_mrvq)))); + vcdp->chgBit(c+4081,(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cache_miss_resrv__DOT__increment_head)); + vcdp->chgBit(c+4089,((0U != (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cache_miss_resrv__DOT__make_ready)))); + vcdp->chgBit(c+4097,(((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cache_miss_resrv__DOT__mrvq_push) + & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__mrvq_init_ready_state_st2)))); + vcdp->chgArray(c+4105,(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT____Vcellinp__cwb_queue__data_in),76); + vcdp->chgArray(c+4129,(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT____Vcellout__cwb_queue__data_out),76); + vcdp->chgBit(c+4153,(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cwb_queue__DOT__writing)); + vcdp->chgArray(c+4161,(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT____Vcellinp__dwb_queue__data_in),200); + vcdp->chgArray(c+4217,(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT____Vcellout__dwb_queue__data_out),200); + vcdp->chgBit(c+4273,(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__dwb_queue__DOT__writing)); + vcdp->chgBit(c+4281,(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__snrq_pop)); + vcdp->chgBus(c+4289,((0x3ffffffU & (IData)( + (vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT____Vcellout__snp_req_queue__data_out + >> 0x1dU)))),26); + vcdp->chgBit(c+4297,((1U & (IData)((vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT____Vcellout__snp_req_queue__data_out + >> 0x1cU))))); + vcdp->chgBus(c+4305,((0xfffffffU & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT____Vcellout__snp_req_queue__data_out))),28); + vcdp->chgBit(c+4313,(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__dfpq_pop)); + vcdp->chgBus(c+4321,((0x3ffffffU & vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT____Vcellout__dfp_queue__data_out[4U])),26); + __Vtemp663[0U] = vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT____Vcellout__dfp_queue__data_out[0U]; + __Vtemp663[1U] = vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT____Vcellout__dfp_queue__data_out[1U]; + __Vtemp663[2U] = vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT____Vcellout__dfp_queue__data_out[2U]; + __Vtemp663[3U] = vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT____Vcellout__dfp_queue__data_out[3U]; + vcdp->chgArray(c+4329,(__Vtemp663),128); + vcdp->chgBit(c+4361,(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__reqq_pop)); + vcdp->chgBit(c+4369,((1U & (~ (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__core_req_arb__DOT__qual_has_request))))); + vcdp->chgBit(c+4377,(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__core_req_arb__DOT__qual_has_request)); + vcdp->chgBus(c+4385,(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__core_req_arb__DOT__qual_request_index),2); + vcdp->chgBit(c+4393,(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__reqq_req_rw_st0)); + vcdp->chgBus(c+4401,((0xfU & ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__core_req_arb__DOT__use_per_byteen) + >> (0xfU & ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__core_req_arb__DOT__qual_request_index) + << 2U))))),4); + vcdp->chgBus(c+4409,(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__reqq_req_addr_st0),30); + vcdp->chgBus(c+4417,((((0U == (0x1fU & ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__core_req_arb__DOT__qual_request_index) + << 5U))) + ? 0U : (vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__core_req_arb__DOT__use_per_writedata[ + ((IData)(1U) + + (3U & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__core_req_arb__DOT__qual_request_index)))] + << ((IData)(0x20U) + - (0x1fU + & ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__core_req_arb__DOT__qual_request_index) + << 5U))))) + | (vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__core_req_arb__DOT__use_per_writedata[ + (3U & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__core_req_arb__DOT__qual_request_index))] + >> (0x1fU & ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__core_req_arb__DOT__qual_request_index) + << 5U))))),32); + vcdp->chgBit(c+4425,(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__mrvq_pop)); + vcdp->chgBit(c+4433,(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__cache_miss_resrv__DOT__dequeue_possible)); + vcdp->chgBit(c+4441,(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__mrvq_rw_st0)); + vcdp->chgBit(c+4449,((0U != (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__cache_miss_resrv__DOT__valid_address_match)))); + vcdp->chgBit(c+4457,(((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__miss_add_because_miss) + & (((0x3ffffffU & ((vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__st_1e_2__DOT__value[9U] + << 7U) + | (vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__st_1e_2__DOT__value[8U] + >> 0x19U))) + == vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__addr_st1 + [0U]) & (~ (vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__st_1e_2__DOT__value[9U] + >> 0x14U)))))); + vcdp->chgBit(c+4465,(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__force_request_miss_st1e)); + vcdp->chgBit(c+4473,(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__recover_mrvq_state_st2)); + vcdp->chgBit(c+4481,(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__mrvq_push_stall)); + vcdp->chgBit(c+4489,(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__cwbq_push_stall)); + vcdp->chgBit(c+4497,(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__dwbq_push_stall)); + vcdp->chgBit(c+4505,(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__dram_fill_req_stall)); + vcdp->chgBit(c+4513,(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__stall_bank_pipe)); + vcdp->chgBit(c+4521,(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__is_fill_in_pipe)); + vcdp->chgBit(c+4529,(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__is_fill_st1[0])); + vcdp->chgBit(c+4537,(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__going_to_write_st1[0])); + vcdp->chgBit(c+4545,(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__dfpq_pop_unqual)); + vcdp->chgBit(c+4553,(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__reqq_pop_unqual)); + vcdp->chgBit(c+4561,(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__snrq_pop_unqual)); + vcdp->chgBit(c+4569,(((((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__dfpq_pop) + | (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__mrvq_pop)) + | (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__reqq_pop)) + | (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__snrq_pop)))); + vcdp->chgBus(c+4577,((0x3ffffffU & ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__dfpq_pop_unqual) + ? (0x3ffffffU + & vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT____Vcellout__dfp_queue__data_out[4U]) + : ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__cache_miss_resrv__DOT__dequeue_possible) + ? + ((0x19fU + >= + (0x1ffU + & ((IData)(0x1aU) + * (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr)))) + ? + (0x3ffffffU + & (((0U + == + (0x1fU + & ((IData)(0x1aU) + * (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr)))) + ? 0U + : + (vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__cache_miss_resrv__DOT__addr_table[ + ((IData)(1U) + + + (0xfU + & (((IData)(0x1aU) + * (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr)) + >> 5U)))] + << + ((IData)(0x20U) + - + (0x1fU + & ((IData)(0x1aU) + * (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr)))))) + | (vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__cache_miss_resrv__DOT__addr_table[ + (0xfU + & (((IData)(0x1aU) + * (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr)) + >> 5U))] + >> + (0x1fU + & ((IData)(0x1aU) + * (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr)))))) + : 0U) + : + ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__reqq_pop_unqual) + ? + (0x3ffffffU + & (vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__reqq_req_addr_st0 + >> 4U)) + : + ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__snrq_pop_unqual) + ? + (0x3ffffffU + & (IData)( + (vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT____Vcellout__snp_req_queue__data_out + >> 0x1dU))) + : 0U)))))),26); + vcdp->chgBus(c+4585,((3U & ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__reqq_pop_unqual) + ? (3U & vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__reqq_req_addr_st0) + : ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__cache_miss_resrv__DOT__dequeue_possible) + ? (3U & (( + vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__cache_miss_resrv__DOT__metadata_table + [vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr][1U] + << 0x1eU) + | (vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__cache_miss_resrv__DOT__metadata_table + [vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr][0U] + >> 2U))) + : 0U)))),2); + vcdp->chgBus(c+4593,(((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__cache_miss_resrv__DOT__dequeue_possible) + ? ((vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__cache_miss_resrv__DOT__metadata_table + [vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr][2U] + << 0xbU) | (vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__cache_miss_resrv__DOT__metadata_table + [vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr][1U] + >> 0x15U)) + : ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__reqq_pop_unqual) + ? (((0U == (0x1fU + & ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__core_req_arb__DOT__qual_request_index) + << 5U))) + ? 0U : (vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__core_req_arb__DOT__use_per_writedata[ + ((IData)(1U) + + + (3U + & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__core_req_arb__DOT__qual_request_index)))] + << + ((IData)(0x20U) + - + (0x1fU + & ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__core_req_arb__DOT__qual_request_index) + << 5U))))) + | (vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__core_req_arb__DOT__use_per_writedata[ + (3U & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__core_req_arb__DOT__qual_request_index))] + >> (0x1fU + & ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__core_req_arb__DOT__qual_request_index) + << 5U)))) + : 0U))),32); + __Vtemp668[0U] = ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__dfpq_pop_unqual) + ? vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT____Vcellout__dfp_queue__data_out[0U] + : 0x39U); + __Vtemp668[1U] = ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__dfpq_pop_unqual) + ? vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT____Vcellout__dfp_queue__data_out[1U] + : 0U); + __Vtemp668[2U] = ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__dfpq_pop_unqual) + ? vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT____Vcellout__dfp_queue__data_out[2U] + : 0U); + __Vtemp668[3U] = ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__dfpq_pop_unqual) + ? vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT____Vcellout__dfp_queue__data_out[3U] + : 0U); + vcdp->chgArray(c+4601,(__Vtemp668),128); + vcdp->chgQuad(c+4633,(((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__cache_miss_resrv__DOT__dequeue_possible) + ? ((VL_ULL(0x1ffffffffff80) + & (((QData)((IData)( + vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__cache_miss_resrv__DOT__metadata_table + [vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr][2U])) + << 0x3eU) | + (((QData)((IData)( + vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__cache_miss_resrv__DOT__metadata_table + [vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr][1U])) + << 0x1eU) + | (VL_ULL(0x3fffffffffffff80) + & ((QData)((IData)( + vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__cache_miss_resrv__DOT__metadata_table + [vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr][0U])) + >> 2U))))) + | (QData)((IData)( + (((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__mrvq_rw_st0) + << 6U) + | ((0x3cU + & ((vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__cache_miss_resrv__DOT__metadata_table + [vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr][1U] + << 0x1eU) + | (0x3ffffffcU + & (vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__cache_miss_resrv__DOT__metadata_table + [vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr][0U] + >> 2U)))) + | (3U + & ((vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__cache_miss_resrv__DOT__metadata_table + [vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr][2U] + << 0xdU) + | (vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__cache_miss_resrv__DOT__metadata_table + [vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr][1U] + >> 0x13U)))))))) + : ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__reqq_pop_unqual) + ? ((vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__core_req_arb__DOT__use_per_tag + << 7U) | (QData)((IData)( + (((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__reqq_req_rw_st0) + << 6U) + | ((0x3cU + & (((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__core_req_arb__DOT__use_per_byteen) + >> + (0xfU + & ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__core_req_arb__DOT__qual_request_index) + << 2U))) + << 2U)) + | (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__core_req_arb__DOT__qual_request_index)))))) + : ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__snrq_pop_unqual) + ? ((QData)((IData)( + (0xfffffffU + & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT____Vcellout__snp_req_queue__data_out)))) + << 7U) : VL_ULL(0))))),49); + vcdp->chgBit(c+4649,(((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__dfpq_pop_unqual) + ? 1U : (((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__cache_miss_resrv__DOT__dequeue_possible) + & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__mrvq_rw_st0)) + ? 1U : (((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__reqq_pop_unqual) + & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__reqq_req_rw_st0)) + ? 1U + : 0U))))); + vcdp->chgBit(c+4657,((1U & ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__cache_miss_resrv__DOT__dequeue_possible) + ? (1U & (vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__cache_miss_resrv__DOT__metadata_table + [vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr][0U] + >> 1U)) + : ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__snrq_pop_unqual) + ? 1U : 0U))))); + vcdp->chgBit(c+4665,((1U & ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__cache_miss_resrv__DOT__dequeue_possible) + ? (1U & vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__cache_miss_resrv__DOT__metadata_table + [vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr][0U]) + : ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__snrq_pop_unqual) + ? (1U & (IData)( + (vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT____Vcellout__snp_req_queue__data_out + >> 0x1cU))) + : 0U))))); + vcdp->chgBit(c+4673,(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__valid_st1[0])); + vcdp->chgBus(c+4681,(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__addr_st1[0]),26); + vcdp->chgBus(c+4689,(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__wsel_st1[0]),2); + vcdp->chgBus(c+4697,(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__writeword_st1[0]),32); + vcdp->chgQuad(c+4705,(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__inst_meta_st1[0]),49); + vcdp->chgArray(c+4721,(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__writedata_st1[0]),128); + vcdp->chgBit(c+4753,(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__is_snp_st1[0])); + vcdp->chgBit(c+4761,(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__snp_invalidate_st1[0])); + vcdp->chgBit(c+4769,(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__is_mrvq_st1[0])); + __Vtemp674[0U] = vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__tag_data_access__DOT__read_data_st1c + [0U][0U]; + __Vtemp674[1U] = vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__tag_data_access__DOT__read_data_st1c + [0U][1U]; + __Vtemp674[2U] = vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__tag_data_access__DOT__read_data_st1c + [0U][2U]; + __Vtemp674[3U] = vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__tag_data_access__DOT__read_data_st1c + [0U][3U]; + vcdp->chgBus(c+4777,((((0U == (0x1fU & (vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__wsel_st1 + [0U] + << 5U))) + ? 0U : (__Vtemp674[ + ((IData)(1U) + + (3U & vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__wsel_st1 + [0U]))] + << ((IData)(0x20U) + - (0x1fU + & (vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__wsel_st1 + [0U] + << 5U))))) + | (__Vtemp674[(3U & vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__wsel_st1 + [0U])] + >> (0x1fU & (vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__wsel_st1 + [0U] + << 5U))))),32); + __Vtemp675[0U] = vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__tag_data_access__DOT__read_data_st1c + [0U][0U]; + __Vtemp675[1U] = vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__tag_data_access__DOT__read_data_st1c + [0U][1U]; + __Vtemp675[2U] = vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__tag_data_access__DOT__read_data_st1c + [0U][2U]; + __Vtemp675[3U] = vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__tag_data_access__DOT__read_data_st1c + [0U][3U]; + vcdp->chgArray(c+4785,(__Vtemp675),128); + vcdp->chgBus(c+4817,(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__tag_data_access__DOT__read_tag_st1c + [0U]),20); + vcdp->chgBit(c+4825,(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__miss_st1e)); + vcdp->chgBit(c+4833,(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__dirty_st1e)); + vcdp->chgBus(c+4841,(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__tag_data_access__DOT__read_dirtyb_st1c + [0U]),16); + vcdp->chgQuad(c+4849,((VL_ULL(0x3ffffffffff) + & (vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__inst_meta_st1 + [0U] >> 7U))),42); + vcdp->chgBus(c+4865,((3U & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__inst_meta_st1 + [0U]))),2); + vcdp->chgBit(c+4873,((1U & (IData)((vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__inst_meta_st1 + [0U] >> 6U))))); + vcdp->chgBus(c+4881,((0xfU & (IData)((vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__inst_meta_st1 + [0U] + >> 2U)))),4); + vcdp->chgBit(c+4889,(((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__tag_data_access__DOT__real_writefill) + & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__dirty_st1e)))); + vcdp->chgBit(c+4897,(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__is_snp_st1 + [0U])); + vcdp->chgBit(c+4905,(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__snp_invalidate_st1 + [0U])); + vcdp->chgBit(c+4913,(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__snp_to_mrvq_st1e)); + vcdp->chgBit(c+4921,(((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__snp_to_mrvq_st1e) + | ((((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__force_request_miss_st1e) + & (~ vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__is_snp_st1 + [0U])) & (~ vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__is_fill_st1 + [0U])) + & vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__valid_st1 + [0U])))); + vcdp->chgBit(c+4929,(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__miss_add_because_miss)); + vcdp->chgBit(c+4937,(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__valid_st1 + [0U])); + vcdp->chgBit(c+4945,(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__is_mrvq_st1 + [0U])); + vcdp->chgBit(c+4953,((((vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__valid_st1 + [0U] & vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__is_mrvq_st1 + [0U]) & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__recover_mrvq_state_st2)) + & ((0x3ffffffU & ((vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__st_1e_2__DOT__value[9U] + << 7U) + | (vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__st_1e_2__DOT__value[8U] + >> 0x19U))) + == vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__addr_st1 + [0U])))); + vcdp->chgBus(c+4961,(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__addr_st1 + [0U]),26); + vcdp->chgBit(c+4969,((vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__valid_st1 + [0U] & (~ vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__is_fill_st1 + [0U])))); + vcdp->chgBit(c+4977,(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__mrvq_init_ready_state_st2)); + vcdp->chgBit(c+4985,((((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__miss_add_unqual) + & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__dfpq_pop_unqual)) + & ((0x3ffffffU & ((vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__st_1e_2__DOT__value[9U] + << 7U) + | (vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__st_1e_2__DOT__value[8U] + >> 0x19U))) + == (0x3ffffffU & vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT____Vcellout__dfp_queue__data_out[4U]))))); + vcdp->chgBit(c+4993,((((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__miss_add_unqual) + & vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__is_fill_st1 + [0U]) & ((0x3ffffffU + & ((vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__st_1e_2__DOT__value[9U] + << 7U) + | (vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__st_1e_2__DOT__value[8U] + >> 0x19U))) + == vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__addr_st1 + [0U])))); + vcdp->chgBit(c+5001,(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__miss_add_unqual)); + vcdp->chgBit(c+5009,(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__miss_add)); + vcdp->chgBit(c+5017,(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__miss_add_is_mrvq)); + vcdp->chgBit(c+5025,(((((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__cwbq_push_unqual) + & (~ (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__cwb_queue__DOT__genblk3__DOT__genblk2__DOT__full_r))) + & (~ (vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__st_1e_2__DOT__value[0U] + >> 6U))) & (~ + (((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__dwbq_push_stall) + | (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__mrvq_push_stall)) + | (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__dram_fill_req_stall)))))); + vcdp->chgBit(c+5033,(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__cwbq_push_unqual)); + vcdp->chgBit(c+5041,(((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__miss_add_unqual) + & ((~ (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__mrvq_init_ready_state_st2)) + | ((vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__st_1e_2__DOT__value[9U] + >> 0x1aU) & (~ + (vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__st_1e_2__DOT__value[9U] + >> 0x1bU))))))); + vcdp->chgBit(c+5049,((((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__dwbq_push_unqual) + & (~ (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__genblk2__DOT__full_r))) + & (~ (((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__cwbq_push_stall) + | (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__mrvq_push_stall)) + | (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__dram_fill_req_stall)))))); + vcdp->chgBit(c+5057,(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__dwbq_is_dwb_in)); + vcdp->chgBit(c+5065,(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__dwbq_is_snp_in)); + vcdp->chgBit(c+5073,((1U & (vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT____Vcellout__dwb_queue__data_out[6U] + >> 7U)))); + vcdp->chgBit(c+5081,((1U & (vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT____Vcellout__dwb_queue__data_out[6U] + >> 6U)))); + vcdp->chgBit(c+5089,(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__dwbq_push_unqual)); + vcdp->chgQuad(c+5097,(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT____Vcellout__snp_req_queue__data_out),55); + vcdp->chgBit(c+5113,(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__snp_req_queue__DOT__reading)); + vcdp->chgArray(c+5121,(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT____Vcellout__dfp_queue__data_out),154); + vcdp->chgBit(c+5161,(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__dfp_queue__DOT__reading)); + vcdp->chgBus(c+5169,((0xfU & (vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__core_req_arb__DOT____Vcellout__reqq_queue__data_out[9U] + >> 0x16U))),4); + vcdp->chgBus(c+5177,((0xfU & (vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__core_req_arb__DOT____Vcellout__reqq_queue__data_out[9U] + >> 0x12U))),4); + vcdp->chgBus(c+5185,((0xffffU & (vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__core_req_arb__DOT____Vcellout__reqq_queue__data_out[9U] + >> 2U))),16); + __Vtemp678[0U] = ((vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__core_req_arb__DOT____Vcellout__reqq_queue__data_out[6U] + << 0x16U) | (vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__core_req_arb__DOT____Vcellout__reqq_queue__data_out[5U] + >> 0xaU)); + __Vtemp678[1U] = ((vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__core_req_arb__DOT____Vcellout__reqq_queue__data_out[7U] + << 0x16U) | (vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__core_req_arb__DOT____Vcellout__reqq_queue__data_out[6U] + >> 0xaU)); + __Vtemp678[2U] = ((vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__core_req_arb__DOT____Vcellout__reqq_queue__data_out[8U] + << 0x16U) | (vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__core_req_arb__DOT____Vcellout__reqq_queue__data_out[7U] + >> 0xaU)); + __Vtemp678[3U] = (0xffffffU & ((vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__core_req_arb__DOT____Vcellout__reqq_queue__data_out[9U] + << 0x16U) | + (vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__core_req_arb__DOT____Vcellout__reqq_queue__data_out[8U] + >> 0xaU))); + vcdp->chgArray(c+5193,(__Vtemp678),120); + __Vtemp679[0U] = ((vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__core_req_arb__DOT____Vcellout__reqq_queue__data_out[2U] + << 0x16U) | (vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__core_req_arb__DOT____Vcellout__reqq_queue__data_out[1U] + >> 0xaU)); + __Vtemp679[1U] = ((vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__core_req_arb__DOT____Vcellout__reqq_queue__data_out[3U] + << 0x16U) | (vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__core_req_arb__DOT____Vcellout__reqq_queue__data_out[2U] + >> 0xaU)); + __Vtemp679[2U] = ((vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__core_req_arb__DOT____Vcellout__reqq_queue__data_out[4U] + << 0x16U) | (vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__core_req_arb__DOT____Vcellout__reqq_queue__data_out[3U] + >> 0xaU)); + __Vtemp679[3U] = ((vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__core_req_arb__DOT____Vcellout__reqq_queue__data_out[5U] + << 0x16U) | (vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__core_req_arb__DOT____Vcellout__reqq_queue__data_out[4U] + >> 0xaU)); + vcdp->chgArray(c+5225,(__Vtemp679),128); + vcdp->chgQuad(c+5257,((VL_ULL(0x3ffffffffff) + & (((QData)((IData)( + vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__core_req_arb__DOT____Vcellout__reqq_queue__data_out[1U])) + << 0x20U) | (QData)((IData)( + vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__core_req_arb__DOT____Vcellout__reqq_queue__data_out[0U]))))),42); + vcdp->chgBit(c+5273,(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__core_req_arb__DOT__out_empty)); + vcdp->chgBit(c+5281,(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__core_req_arb__DOT__pop_qual)); + vcdp->chgBus(c+5289,((0xfU & ((vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__core_req_arb__DOT____Vcellout__reqq_queue__data_out[9U] + >> 0x16U) & + VL_NEGATE_I((IData)( + (1U + & (~ (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__core_req_arb__DOT__out_empty)))))))),4); + vcdp->chgArray(c+5297,(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__core_req_arb__DOT____Vcellout__reqq_queue__data_out),314); + vcdp->chgBit(c+5377,(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__reading)); + vcdp->chgBus(c+5385,(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__core_req_arb__DOT__sel_bank__DOT__genblk2__DOT__grant_onehot_r),4); + vcdp->chgBus(c+5393,(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__core_req_arb__DOT__sel_bank__DOT__genblk2__DOT__priority_encoder__DOT__i),32); + vcdp->chgArray(c+5401,(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT____Vcellinp__s0_1_c0__in),243); + vcdp->chgBus(c+5465,((0x3fU & vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__addr_st1 + [0U])),6); + vcdp->chgBit(c+5473,(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__is_fill_st1 + [0U])); + vcdp->chgBus(c+5481,(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__writeword_st1 + [0U]),32); + __Vtemp680[0U] = vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__writedata_st1 + [0U][0U]; + __Vtemp680[1U] = vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__writedata_st1 + [0U][1U]; + __Vtemp680[2U] = vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__writedata_st1 + [0U][2U]; + __Vtemp680[3U] = vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__writedata_st1 + [0U][3U]; + vcdp->chgArray(c+5489,(__Vtemp680),128); + vcdp->chgBus(c+5521,(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__wsel_st1 + [0U]),2); + vcdp->chgBit(c+5529,(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__tag_data_access__DOT__read_valid_st1c[0])); + vcdp->chgBit(c+5537,(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__tag_data_access__DOT__read_dirty_st1c[0])); + vcdp->chgBus(c+5545,(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__tag_data_access__DOT__read_dirtyb_st1c[0]),16); + vcdp->chgBus(c+5553,(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__tag_data_access__DOT__read_tag_st1c[0]),20); + vcdp->chgArray(c+5561,(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__tag_data_access__DOT__read_data_st1c[0]),128); + vcdp->chgBit(c+5593,((1U & (IData)((vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__valid + >> (0x3fU + & vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__addr_st1 + [0U])))))); + vcdp->chgBit(c+5601,((1U & (IData)((vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__dirty + >> (0x3fU + & vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__addr_st1 + [0U])))))); + vcdp->chgBus(c+5609,(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__dirtyb + [(0x3fU & vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__addr_st1 + [0U])]),16); + vcdp->chgBus(c+5617,(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__tag + [(0x3fU & vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__addr_st1 + [0U])]),20); + __Vtemp681[0U] = vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__data + [(0x3fU & vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__addr_st1 + [0U])][0U]; + __Vtemp681[1U] = vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__data + [(0x3fU & vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__addr_st1 + [0U])][1U]; + __Vtemp681[2U] = vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__data + [(0x3fU & vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__addr_st1 + [0U])][2U]; + __Vtemp681[3U] = vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__data + [(0x3fU & vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__addr_st1 + [0U])][3U]; + vcdp->chgArray(c+5625,(__Vtemp681),128); + vcdp->chgBit(c+5657,(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__tag_data_access__DOT__read_valid_st1c + [0U])); + vcdp->chgBit(c+5665,(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__tag_data_access__DOT__read_dirty_st1c + [0U])); + vcdp->chgBus(c+5673,(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__tag_data_access__DOT__use_write_enable),16); + vcdp->chgArray(c+5681,(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__tag_data_access__DOT__data_write),128); + vcdp->chgBit(c+5713,(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__tag_data_access__DOT__snoop_hit_no_pending)); + vcdp->chgBit(c+5721,(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__tag_data_access__DOT__tags_match)); + vcdp->chgBit(c+5729,(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__tag_data_access__DOT__real_writefill)); + vcdp->chgBus(c+5737,((0xfffffU & (vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__addr_st1 + [0U] >> 6U))),20); + vcdp->chgBus(c+5745,(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__tag_data_access__DOT__we),16); + vcdp->chgBit(c+5753,(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__tag_data_access__DOT__should_write)); + vcdp->chgBit(c+5761,((((vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__valid_st1 + [0U] & (~ vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__is_snp_st1 + [0U])) & (~ + vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__tag_data_access__DOT__read_valid_st1c + [0U])) + & (~ vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__is_fill_st1 + [0U])))); + vcdp->chgBit(c+5769,(((((vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__valid_st1 + [0U] & (~ vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__is_snp_st1 + [0U])) & vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__tag_data_access__DOT__read_valid_st1c + [0U]) & (~ vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__is_fill_st1 + [0U])) & (~ (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__tag_data_access__DOT__tags_match))))); + vcdp->chgBit(c+5777,(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__tag_data_access__DOT__real_miss)); + vcdp->chgBit(c+5785,((((((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__force_request_miss_st1e) + & (~ vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__is_snp_st1 + [0U])) & (~ vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__is_fill_st1 + [0U])) + & vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__valid_st1 + [0U]) & (~ (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__tag_data_access__DOT__real_miss))))); + vcdp->chgBit(c+5793,(((0U == vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__wsel_st1 + [0U]) & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__tag_data_access__DOT__should_write)))); + vcdp->chgBit(c+5801,(((1U == vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__wsel_st1 + [0U]) & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__tag_data_access__DOT__should_write)))); + vcdp->chgBit(c+5809,(((2U == vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__wsel_st1 + [0U]) & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__tag_data_access__DOT__should_write)))); + vcdp->chgBit(c+5817,(((3U == vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__wsel_st1 + [0U]) & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__tag_data_access__DOT__should_write)))); + vcdp->chgBit(c+5825,((0U != (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__tag_data_access__DOT__use_write_enable)))); + vcdp->chgArray(c+5833,(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__tag_data_access__DOT____Vcellinp__s0_1_c0__in),166); + vcdp->chgArray(c+5881,(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT____Vcellinp__st_1e_2__in),316); + vcdp->chgBus(c+5961,(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__cache_miss_resrv__DOT__make_ready),16); + vcdp->chgBus(c+5969,((0xffffU & (((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__cache_miss_resrv__DOT__mrvq_push) + & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__mrvq_init_ready_state_st2)) + << (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__cache_miss_resrv__DOT__tail_ptr)))),16); + vcdp->chgBus(c+5977,(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__cache_miss_resrv__DOT__valid_address_match),16); + vcdp->chgBit(c+5985,(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__cache_miss_resrv__DOT__mrvq_push)); + vcdp->chgBit(c+5993,(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__cache_miss_resrv__DOT__mrvq_pop)); + vcdp->chgBit(c+6001,(((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__miss_add) + & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__miss_add_is_mrvq)))); + vcdp->chgBit(c+6009,(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__cache_miss_resrv__DOT__increment_head)); + vcdp->chgBit(c+6017,((0U != (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__cache_miss_resrv__DOT__make_ready)))); + vcdp->chgBit(c+6025,(((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__cache_miss_resrv__DOT__mrvq_push) + & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__mrvq_init_ready_state_st2)))); + vcdp->chgArray(c+6033,(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT____Vcellinp__cwb_queue__data_in),76); + vcdp->chgArray(c+6057,(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT____Vcellout__cwb_queue__data_out),76); + vcdp->chgBit(c+6081,(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__cwb_queue__DOT__writing)); + vcdp->chgArray(c+6089,(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT____Vcellinp__dwb_queue__data_in),200); + vcdp->chgArray(c+6145,(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT____Vcellout__dwb_queue__data_out),200); + vcdp->chgBit(c+6201,(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__dwb_queue__DOT__writing)); + vcdp->chgBit(c+6209,(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__snrq_pop)); + vcdp->chgBus(c+6217,((0x3ffffffU & (IData)( + (vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT____Vcellout__snp_req_queue__data_out + >> 0x1dU)))),26); + vcdp->chgBit(c+6225,((1U & (IData)((vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT____Vcellout__snp_req_queue__data_out + >> 0x1cU))))); + vcdp->chgBus(c+6233,((0xfffffffU & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT____Vcellout__snp_req_queue__data_out))),28); + vcdp->chgBit(c+6241,(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__dfpq_pop)); + vcdp->chgBus(c+6249,((0x3ffffffU & vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT____Vcellout__dfp_queue__data_out[4U])),26); + __Vtemp682[0U] = vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT____Vcellout__dfp_queue__data_out[0U]; + __Vtemp682[1U] = vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT____Vcellout__dfp_queue__data_out[1U]; + __Vtemp682[2U] = vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT____Vcellout__dfp_queue__data_out[2U]; + __Vtemp682[3U] = vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT____Vcellout__dfp_queue__data_out[3U]; + vcdp->chgArray(c+6257,(__Vtemp682),128); + vcdp->chgBit(c+6289,(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__reqq_pop)); + vcdp->chgBit(c+6297,((1U & (~ (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__core_req_arb__DOT__qual_has_request))))); + vcdp->chgBit(c+6305,(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__core_req_arb__DOT__qual_has_request)); + vcdp->chgBus(c+6313,(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__core_req_arb__DOT__qual_request_index),2); + vcdp->chgBit(c+6321,(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__reqq_req_rw_st0)); + vcdp->chgBus(c+6329,((0xfU & ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__core_req_arb__DOT__use_per_byteen) + >> (0xfU & ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__core_req_arb__DOT__qual_request_index) + << 2U))))),4); + vcdp->chgBus(c+6337,(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__reqq_req_addr_st0),30); + vcdp->chgBus(c+6345,((((0U == (0x1fU & ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__core_req_arb__DOT__qual_request_index) + << 5U))) + ? 0U : (vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__core_req_arb__DOT__use_per_writedata[ + ((IData)(1U) + + (3U & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__core_req_arb__DOT__qual_request_index)))] + << ((IData)(0x20U) + - (0x1fU + & ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__core_req_arb__DOT__qual_request_index) + << 5U))))) + | (vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__core_req_arb__DOT__use_per_writedata[ + (3U & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__core_req_arb__DOT__qual_request_index))] + >> (0x1fU & ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__core_req_arb__DOT__qual_request_index) + << 5U))))),32); + vcdp->chgBit(c+6353,(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__mrvq_pop)); + vcdp->chgBit(c+6361,(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__cache_miss_resrv__DOT__dequeue_possible)); + vcdp->chgBit(c+6369,(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__mrvq_rw_st0)); + vcdp->chgBit(c+6377,((0U != (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__cache_miss_resrv__DOT__valid_address_match)))); + vcdp->chgBit(c+6385,(((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__miss_add_because_miss) + & (((0x3ffffffU & ((vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__st_1e_2__DOT__value[9U] + << 7U) + | (vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__st_1e_2__DOT__value[8U] + >> 0x19U))) + == vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__addr_st1 + [0U]) & (~ (vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__st_1e_2__DOT__value[9U] + >> 0x14U)))))); + vcdp->chgBit(c+6393,(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__force_request_miss_st1e)); + vcdp->chgBit(c+6401,(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__recover_mrvq_state_st2)); + vcdp->chgBit(c+6409,(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__mrvq_push_stall)); + vcdp->chgBit(c+6417,(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__cwbq_push_stall)); + vcdp->chgBit(c+6425,(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__dwbq_push_stall)); + vcdp->chgBit(c+6433,(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__dram_fill_req_stall)); + vcdp->chgBit(c+6441,(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__stall_bank_pipe)); + vcdp->chgBit(c+6449,(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__is_fill_in_pipe)); + vcdp->chgBit(c+6457,(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__is_fill_st1[0])); + vcdp->chgBit(c+6465,(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__going_to_write_st1[0])); + vcdp->chgBit(c+6473,(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__dfpq_pop_unqual)); + vcdp->chgBit(c+6481,(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__reqq_pop_unqual)); + vcdp->chgBit(c+6489,(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__snrq_pop_unqual)); + vcdp->chgBit(c+6497,(((((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__dfpq_pop) + | (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__mrvq_pop)) + | (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__reqq_pop)) + | (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__snrq_pop)))); + vcdp->chgBus(c+6505,((0x3ffffffU & ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__dfpq_pop_unqual) + ? (0x3ffffffU + & vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT____Vcellout__dfp_queue__data_out[4U]) + : ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__cache_miss_resrv__DOT__dequeue_possible) + ? + ((0x19fU + >= + (0x1ffU + & ((IData)(0x1aU) + * (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr)))) + ? + (0x3ffffffU + & (((0U + == + (0x1fU + & ((IData)(0x1aU) + * (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr)))) + ? 0U + : + (vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__cache_miss_resrv__DOT__addr_table[ + ((IData)(1U) + + + (0xfU + & (((IData)(0x1aU) + * (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr)) + >> 5U)))] + << + ((IData)(0x20U) + - + (0x1fU + & ((IData)(0x1aU) + * (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr)))))) + | (vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__cache_miss_resrv__DOT__addr_table[ + (0xfU + & (((IData)(0x1aU) + * (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr)) + >> 5U))] + >> + (0x1fU + & ((IData)(0x1aU) + * (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr)))))) + : 0U) + : + ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__reqq_pop_unqual) + ? + (0x3ffffffU + & (vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__reqq_req_addr_st0 + >> 4U)) + : + ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__snrq_pop_unqual) + ? + (0x3ffffffU + & (IData)( + (vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT____Vcellout__snp_req_queue__data_out + >> 0x1dU))) + : 0U)))))),26); + vcdp->chgBus(c+6513,((3U & ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__reqq_pop_unqual) + ? (3U & vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__reqq_req_addr_st0) + : ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__cache_miss_resrv__DOT__dequeue_possible) + ? (3U & (( + vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__cache_miss_resrv__DOT__metadata_table + [vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr][1U] + << 0x1eU) + | (vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__cache_miss_resrv__DOT__metadata_table + [vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr][0U] + >> 2U))) + : 0U)))),2); + vcdp->chgBus(c+6521,(((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__cache_miss_resrv__DOT__dequeue_possible) + ? ((vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__cache_miss_resrv__DOT__metadata_table + [vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr][2U] + << 0xbU) | (vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__cache_miss_resrv__DOT__metadata_table + [vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr][1U] + >> 0x15U)) + : ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__reqq_pop_unqual) + ? (((0U == (0x1fU + & ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__core_req_arb__DOT__qual_request_index) + << 5U))) + ? 0U : (vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__core_req_arb__DOT__use_per_writedata[ + ((IData)(1U) + + + (3U + & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__core_req_arb__DOT__qual_request_index)))] + << + ((IData)(0x20U) + - + (0x1fU + & ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__core_req_arb__DOT__qual_request_index) + << 5U))))) + | (vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__core_req_arb__DOT__use_per_writedata[ + (3U & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__core_req_arb__DOT__qual_request_index))] + >> (0x1fU + & ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__core_req_arb__DOT__qual_request_index) + << 5U)))) + : 0U))),32); + __Vtemp687[0U] = ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__dfpq_pop_unqual) + ? vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT____Vcellout__dfp_queue__data_out[0U] + : 0x39U); + __Vtemp687[1U] = ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__dfpq_pop_unqual) + ? vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT____Vcellout__dfp_queue__data_out[1U] + : 0U); + __Vtemp687[2U] = ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__dfpq_pop_unqual) + ? vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT____Vcellout__dfp_queue__data_out[2U] + : 0U); + __Vtemp687[3U] = ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__dfpq_pop_unqual) + ? vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT____Vcellout__dfp_queue__data_out[3U] + : 0U); + vcdp->chgArray(c+6529,(__Vtemp687),128); + vcdp->chgQuad(c+6561,(((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__cache_miss_resrv__DOT__dequeue_possible) + ? ((VL_ULL(0x1ffffffffff80) + & (((QData)((IData)( + vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__cache_miss_resrv__DOT__metadata_table + [vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr][2U])) + << 0x3eU) | + (((QData)((IData)( + vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__cache_miss_resrv__DOT__metadata_table + [vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr][1U])) + << 0x1eU) + | (VL_ULL(0x3fffffffffffff80) + & ((QData)((IData)( + vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__cache_miss_resrv__DOT__metadata_table + [vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr][0U])) + >> 2U))))) + | (QData)((IData)( + (((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__mrvq_rw_st0) + << 6U) + | ((0x3cU + & ((vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__cache_miss_resrv__DOT__metadata_table + [vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr][1U] + << 0x1eU) + | (0x3ffffffcU + & (vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__cache_miss_resrv__DOT__metadata_table + [vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr][0U] + >> 2U)))) + | (3U + & ((vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__cache_miss_resrv__DOT__metadata_table + [vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr][2U] + << 0xdU) + | (vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__cache_miss_resrv__DOT__metadata_table + [vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr][1U] + >> 0x13U)))))))) + : ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__reqq_pop_unqual) + ? ((vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__core_req_arb__DOT__use_per_tag + << 7U) | (QData)((IData)( + (((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__reqq_req_rw_st0) + << 6U) + | ((0x3cU + & (((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__core_req_arb__DOT__use_per_byteen) + >> + (0xfU + & ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__core_req_arb__DOT__qual_request_index) + << 2U))) + << 2U)) + | (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__core_req_arb__DOT__qual_request_index)))))) + : ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__snrq_pop_unqual) + ? ((QData)((IData)( + (0xfffffffU + & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT____Vcellout__snp_req_queue__data_out)))) + << 7U) : VL_ULL(0))))),49); + vcdp->chgBit(c+6577,(((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__dfpq_pop_unqual) + ? 1U : (((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__cache_miss_resrv__DOT__dequeue_possible) + & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__mrvq_rw_st0)) + ? 1U : (((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__reqq_pop_unqual) + & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__reqq_req_rw_st0)) + ? 1U + : 0U))))); + vcdp->chgBit(c+6585,((1U & ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__cache_miss_resrv__DOT__dequeue_possible) + ? (1U & (vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__cache_miss_resrv__DOT__metadata_table + [vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr][0U] + >> 1U)) + : ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__snrq_pop_unqual) + ? 1U : 0U))))); + vcdp->chgBit(c+6593,((1U & ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__cache_miss_resrv__DOT__dequeue_possible) + ? (1U & vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__cache_miss_resrv__DOT__metadata_table + [vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr][0U]) + : ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__snrq_pop_unqual) + ? (1U & (IData)( + (vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT____Vcellout__snp_req_queue__data_out + >> 0x1cU))) + : 0U))))); + vcdp->chgBit(c+6601,(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__valid_st1[0])); + vcdp->chgBus(c+6609,(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__addr_st1[0]),26); + vcdp->chgBus(c+6617,(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__wsel_st1[0]),2); + vcdp->chgBus(c+6625,(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__writeword_st1[0]),32); + vcdp->chgQuad(c+6633,(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__inst_meta_st1[0]),49); + vcdp->chgArray(c+6649,(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__writedata_st1[0]),128); + vcdp->chgBit(c+6681,(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__is_snp_st1[0])); + vcdp->chgBit(c+6689,(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__snp_invalidate_st1[0])); + vcdp->chgBit(c+6697,(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__is_mrvq_st1[0])); + __Vtemp693[0U] = vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__tag_data_access__DOT__read_data_st1c + [0U][0U]; + __Vtemp693[1U] = vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__tag_data_access__DOT__read_data_st1c + [0U][1U]; + __Vtemp693[2U] = vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__tag_data_access__DOT__read_data_st1c + [0U][2U]; + __Vtemp693[3U] = vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__tag_data_access__DOT__read_data_st1c + [0U][3U]; + vcdp->chgBus(c+6705,((((0U == (0x1fU & (vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__wsel_st1 + [0U] + << 5U))) + ? 0U : (__Vtemp693[ + ((IData)(1U) + + (3U & vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__wsel_st1 + [0U]))] + << ((IData)(0x20U) + - (0x1fU + & (vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__wsel_st1 + [0U] + << 5U))))) + | (__Vtemp693[(3U & vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__wsel_st1 + [0U])] + >> (0x1fU & (vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__wsel_st1 + [0U] + << 5U))))),32); + __Vtemp694[0U] = vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__tag_data_access__DOT__read_data_st1c + [0U][0U]; + __Vtemp694[1U] = vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__tag_data_access__DOT__read_data_st1c + [0U][1U]; + __Vtemp694[2U] = vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__tag_data_access__DOT__read_data_st1c + [0U][2U]; + __Vtemp694[3U] = vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__tag_data_access__DOT__read_data_st1c + [0U][3U]; + vcdp->chgArray(c+6713,(__Vtemp694),128); + vcdp->chgBus(c+6745,(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__tag_data_access__DOT__read_tag_st1c + [0U]),20); + vcdp->chgBit(c+6753,(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__miss_st1e)); + vcdp->chgBit(c+6761,(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__dirty_st1e)); + vcdp->chgBus(c+6769,(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__tag_data_access__DOT__read_dirtyb_st1c + [0U]),16); + vcdp->chgQuad(c+6777,((VL_ULL(0x3ffffffffff) + & (vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__inst_meta_st1 + [0U] >> 7U))),42); + vcdp->chgBus(c+6793,((3U & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__inst_meta_st1 + [0U]))),2); + vcdp->chgBit(c+6801,((1U & (IData)((vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__inst_meta_st1 + [0U] >> 6U))))); + vcdp->chgBus(c+6809,((0xfU & (IData)((vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__inst_meta_st1 + [0U] + >> 2U)))),4); + vcdp->chgBit(c+6817,(((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__tag_data_access__DOT__real_writefill) + & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__dirty_st1e)))); + vcdp->chgBit(c+6825,(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__is_snp_st1 + [0U])); + vcdp->chgBit(c+6833,(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__snp_invalidate_st1 + [0U])); + vcdp->chgBit(c+6841,(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__snp_to_mrvq_st1e)); + vcdp->chgBit(c+6849,(((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__snp_to_mrvq_st1e) + | ((((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__force_request_miss_st1e) + & (~ vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__is_snp_st1 + [0U])) & (~ vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__is_fill_st1 + [0U])) + & vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__valid_st1 + [0U])))); + vcdp->chgBit(c+6857,(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__miss_add_because_miss)); + vcdp->chgBit(c+6865,(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__valid_st1 + [0U])); + vcdp->chgBit(c+6873,(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__is_mrvq_st1 + [0U])); + vcdp->chgBit(c+6881,((((vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__valid_st1 + [0U] & vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__is_mrvq_st1 + [0U]) & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__recover_mrvq_state_st2)) + & ((0x3ffffffU & ((vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__st_1e_2__DOT__value[9U] + << 7U) + | (vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__st_1e_2__DOT__value[8U] + >> 0x19U))) + == vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__addr_st1 + [0U])))); + vcdp->chgBus(c+6889,(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__addr_st1 + [0U]),26); + vcdp->chgBit(c+6897,((vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__valid_st1 + [0U] & (~ vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__is_fill_st1 + [0U])))); + vcdp->chgBit(c+6905,(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__mrvq_init_ready_state_st2)); + vcdp->chgBit(c+6913,((((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__miss_add_unqual) + & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__dfpq_pop_unqual)) + & ((0x3ffffffU & ((vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__st_1e_2__DOT__value[9U] + << 7U) + | (vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__st_1e_2__DOT__value[8U] + >> 0x19U))) + == (0x3ffffffU & vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT____Vcellout__dfp_queue__data_out[4U]))))); + vcdp->chgBit(c+6921,((((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__miss_add_unqual) + & vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__is_fill_st1 + [0U]) & ((0x3ffffffU + & ((vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__st_1e_2__DOT__value[9U] + << 7U) + | (vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__st_1e_2__DOT__value[8U] + >> 0x19U))) + == vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__addr_st1 + [0U])))); + vcdp->chgBit(c+6929,(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__miss_add_unqual)); + vcdp->chgBit(c+6937,(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__miss_add)); + vcdp->chgBit(c+6945,(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__miss_add_is_mrvq)); + vcdp->chgBit(c+6953,(((((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__cwbq_push_unqual) + & (~ (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__cwb_queue__DOT__genblk3__DOT__genblk2__DOT__full_r))) + & (~ (vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__st_1e_2__DOT__value[0U] + >> 6U))) & (~ + (((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__dwbq_push_stall) + | (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__mrvq_push_stall)) + | (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__dram_fill_req_stall)))))); + vcdp->chgBit(c+6961,(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__cwbq_push_unqual)); + vcdp->chgBit(c+6969,(((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__miss_add_unqual) + & ((~ (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__mrvq_init_ready_state_st2)) + | ((vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__st_1e_2__DOT__value[9U] + >> 0x1aU) & (~ + (vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__st_1e_2__DOT__value[9U] + >> 0x1bU))))))); + vcdp->chgBit(c+6977,((((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__dwbq_push_unqual) + & (~ (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__genblk2__DOT__full_r))) + & (~ (((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__cwbq_push_stall) + | (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__mrvq_push_stall)) + | (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__dram_fill_req_stall)))))); + vcdp->chgBit(c+6985,(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__dwbq_is_dwb_in)); + vcdp->chgBit(c+6993,(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__dwbq_is_snp_in)); + vcdp->chgBit(c+7001,((1U & (vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT____Vcellout__dwb_queue__data_out[6U] + >> 7U)))); + vcdp->chgBit(c+7009,((1U & (vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT____Vcellout__dwb_queue__data_out[6U] + >> 6U)))); + vcdp->chgBit(c+7017,(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__dwbq_push_unqual)); + vcdp->chgQuad(c+7025,(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT____Vcellout__snp_req_queue__data_out),55); + vcdp->chgBit(c+7041,(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__snp_req_queue__DOT__reading)); + vcdp->chgArray(c+7049,(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT____Vcellout__dfp_queue__data_out),154); + vcdp->chgBit(c+7089,(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__dfp_queue__DOT__reading)); + vcdp->chgBus(c+7097,((0xfU & (vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__core_req_arb__DOT____Vcellout__reqq_queue__data_out[9U] + >> 0x16U))),4); + vcdp->chgBus(c+7105,((0xfU & (vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__core_req_arb__DOT____Vcellout__reqq_queue__data_out[9U] + >> 0x12U))),4); + vcdp->chgBus(c+7113,((0xffffU & (vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__core_req_arb__DOT____Vcellout__reqq_queue__data_out[9U] + >> 2U))),16); + __Vtemp697[0U] = ((vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__core_req_arb__DOT____Vcellout__reqq_queue__data_out[6U] + << 0x16U) | (vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__core_req_arb__DOT____Vcellout__reqq_queue__data_out[5U] + >> 0xaU)); + __Vtemp697[1U] = ((vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__core_req_arb__DOT____Vcellout__reqq_queue__data_out[7U] + << 0x16U) | (vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__core_req_arb__DOT____Vcellout__reqq_queue__data_out[6U] + >> 0xaU)); + __Vtemp697[2U] = ((vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__core_req_arb__DOT____Vcellout__reqq_queue__data_out[8U] + << 0x16U) | (vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__core_req_arb__DOT____Vcellout__reqq_queue__data_out[7U] + >> 0xaU)); + __Vtemp697[3U] = (0xffffffU & ((vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__core_req_arb__DOT____Vcellout__reqq_queue__data_out[9U] + << 0x16U) | + (vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__core_req_arb__DOT____Vcellout__reqq_queue__data_out[8U] + >> 0xaU))); + vcdp->chgArray(c+7121,(__Vtemp697),120); + __Vtemp698[0U] = ((vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__core_req_arb__DOT____Vcellout__reqq_queue__data_out[2U] + << 0x16U) | (vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__core_req_arb__DOT____Vcellout__reqq_queue__data_out[1U] + >> 0xaU)); + __Vtemp698[1U] = ((vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__core_req_arb__DOT____Vcellout__reqq_queue__data_out[3U] + << 0x16U) | (vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__core_req_arb__DOT____Vcellout__reqq_queue__data_out[2U] + >> 0xaU)); + __Vtemp698[2U] = ((vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__core_req_arb__DOT____Vcellout__reqq_queue__data_out[4U] + << 0x16U) | (vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__core_req_arb__DOT____Vcellout__reqq_queue__data_out[3U] + >> 0xaU)); + __Vtemp698[3U] = ((vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__core_req_arb__DOT____Vcellout__reqq_queue__data_out[5U] + << 0x16U) | (vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__core_req_arb__DOT____Vcellout__reqq_queue__data_out[4U] + >> 0xaU)); + vcdp->chgArray(c+7153,(__Vtemp698),128); + vcdp->chgQuad(c+7185,((VL_ULL(0x3ffffffffff) + & (((QData)((IData)( + vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__core_req_arb__DOT____Vcellout__reqq_queue__data_out[1U])) + << 0x20U) | (QData)((IData)( + vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__core_req_arb__DOT____Vcellout__reqq_queue__data_out[0U]))))),42); + vcdp->chgBit(c+7201,(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__core_req_arb__DOT__out_empty)); + vcdp->chgBit(c+7209,(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__core_req_arb__DOT__pop_qual)); + vcdp->chgBus(c+7217,((0xfU & ((vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__core_req_arb__DOT____Vcellout__reqq_queue__data_out[9U] + >> 0x16U) & + VL_NEGATE_I((IData)( + (1U + & (~ (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__core_req_arb__DOT__out_empty)))))))),4); + vcdp->chgArray(c+7225,(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__core_req_arb__DOT____Vcellout__reqq_queue__data_out),314); + vcdp->chgBit(c+7305,(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__reading)); + vcdp->chgBus(c+7313,(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__core_req_arb__DOT__sel_bank__DOT__genblk2__DOT__grant_onehot_r),4); + vcdp->chgBus(c+7321,(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__core_req_arb__DOT__sel_bank__DOT__genblk2__DOT__priority_encoder__DOT__i),32); + vcdp->chgArray(c+7329,(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT____Vcellinp__s0_1_c0__in),243); + vcdp->chgBus(c+7393,((0x3fU & vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__addr_st1 + [0U])),6); + vcdp->chgBit(c+7401,(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__is_fill_st1 + [0U])); + vcdp->chgBus(c+7409,(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__writeword_st1 + [0U]),32); + __Vtemp699[0U] = vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__writedata_st1 + [0U][0U]; + __Vtemp699[1U] = vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__writedata_st1 + [0U][1U]; + __Vtemp699[2U] = vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__writedata_st1 + [0U][2U]; + __Vtemp699[3U] = vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__writedata_st1 + [0U][3U]; + vcdp->chgArray(c+7417,(__Vtemp699),128); + vcdp->chgBus(c+7449,(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__wsel_st1 + [0U]),2); + vcdp->chgBit(c+7457,(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__tag_data_access__DOT__read_valid_st1c[0])); + vcdp->chgBit(c+7465,(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__tag_data_access__DOT__read_dirty_st1c[0])); + vcdp->chgBus(c+7473,(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__tag_data_access__DOT__read_dirtyb_st1c[0]),16); + vcdp->chgBus(c+7481,(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__tag_data_access__DOT__read_tag_st1c[0]),20); + vcdp->chgArray(c+7489,(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__tag_data_access__DOT__read_data_st1c[0]),128); + vcdp->chgBit(c+7521,((1U & (IData)((vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__valid + >> (0x3fU + & vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__addr_st1 + [0U])))))); + vcdp->chgBit(c+7529,((1U & (IData)((vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__dirty + >> (0x3fU + & vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__addr_st1 + [0U])))))); + vcdp->chgBus(c+7537,(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__dirtyb + [(0x3fU & vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__addr_st1 + [0U])]),16); + vcdp->chgBus(c+7545,(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__tag + [(0x3fU & vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__addr_st1 + [0U])]),20); + __Vtemp700[0U] = vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__data + [(0x3fU & vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__addr_st1 + [0U])][0U]; + __Vtemp700[1U] = vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__data + [(0x3fU & vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__addr_st1 + [0U])][1U]; + __Vtemp700[2U] = vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__data + [(0x3fU & vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__addr_st1 + [0U])][2U]; + __Vtemp700[3U] = vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__data + [(0x3fU & vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__addr_st1 + [0U])][3U]; + vcdp->chgArray(c+7553,(__Vtemp700),128); + vcdp->chgBit(c+7585,(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__tag_data_access__DOT__read_valid_st1c + [0U])); + vcdp->chgBit(c+7593,(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__tag_data_access__DOT__read_dirty_st1c + [0U])); + vcdp->chgBus(c+7601,(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__tag_data_access__DOT__use_write_enable),16); + vcdp->chgArray(c+7609,(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__tag_data_access__DOT__data_write),128); + vcdp->chgBit(c+7641,(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__tag_data_access__DOT__snoop_hit_no_pending)); + vcdp->chgBit(c+7649,(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__tag_data_access__DOT__tags_match)); + vcdp->chgBit(c+7657,(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__tag_data_access__DOT__real_writefill)); + vcdp->chgBus(c+7665,((0xfffffU & (vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__addr_st1 + [0U] >> 6U))),20); + vcdp->chgBus(c+7673,(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__tag_data_access__DOT__we),16); + vcdp->chgBit(c+7681,(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__tag_data_access__DOT__should_write)); + vcdp->chgBit(c+7689,((((vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__valid_st1 + [0U] & (~ vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__is_snp_st1 + [0U])) & (~ + vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__tag_data_access__DOT__read_valid_st1c + [0U])) + & (~ vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__is_fill_st1 + [0U])))); + vcdp->chgBit(c+7697,(((((vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__valid_st1 + [0U] & (~ vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__is_snp_st1 + [0U])) & vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__tag_data_access__DOT__read_valid_st1c + [0U]) & (~ vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__is_fill_st1 + [0U])) & (~ (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__tag_data_access__DOT__tags_match))))); + vcdp->chgBit(c+7705,(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__tag_data_access__DOT__real_miss)); + vcdp->chgBit(c+7713,((((((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__force_request_miss_st1e) + & (~ vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__is_snp_st1 + [0U])) & (~ vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__is_fill_st1 + [0U])) + & vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__valid_st1 + [0U]) & (~ (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__tag_data_access__DOT__real_miss))))); + vcdp->chgBit(c+7721,(((0U == vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__wsel_st1 + [0U]) & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__tag_data_access__DOT__should_write)))); + vcdp->chgBit(c+7729,(((1U == vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__wsel_st1 + [0U]) & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__tag_data_access__DOT__should_write)))); + vcdp->chgBit(c+7737,(((2U == vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__wsel_st1 + [0U]) & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__tag_data_access__DOT__should_write)))); + vcdp->chgBit(c+7745,(((3U == vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__wsel_st1 + [0U]) & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__tag_data_access__DOT__should_write)))); + vcdp->chgBit(c+7753,((0U != (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__tag_data_access__DOT__use_write_enable)))); + vcdp->chgArray(c+7761,(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__tag_data_access__DOT____Vcellinp__s0_1_c0__in),166); + vcdp->chgArray(c+7809,(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT____Vcellinp__st_1e_2__in),316); + vcdp->chgBus(c+7889,(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__cache_miss_resrv__DOT__make_ready),16); + vcdp->chgBus(c+7897,((0xffffU & (((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__cache_miss_resrv__DOT__mrvq_push) + & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__mrvq_init_ready_state_st2)) + << (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__cache_miss_resrv__DOT__tail_ptr)))),16); + vcdp->chgBus(c+7905,(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__cache_miss_resrv__DOT__valid_address_match),16); + vcdp->chgBit(c+7913,(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__cache_miss_resrv__DOT__mrvq_push)); + vcdp->chgBit(c+7921,(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__cache_miss_resrv__DOT__mrvq_pop)); + vcdp->chgBit(c+7929,(((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__miss_add) + & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__miss_add_is_mrvq)))); + vcdp->chgBit(c+7937,(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__cache_miss_resrv__DOT__increment_head)); + vcdp->chgBit(c+7945,((0U != (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__cache_miss_resrv__DOT__make_ready)))); + vcdp->chgBit(c+7953,(((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__cache_miss_resrv__DOT__mrvq_push) + & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__mrvq_init_ready_state_st2)))); + vcdp->chgArray(c+7961,(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT____Vcellinp__cwb_queue__data_in),76); + vcdp->chgArray(c+7985,(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT____Vcellout__cwb_queue__data_out),76); + vcdp->chgBit(c+8009,(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__cwb_queue__DOT__writing)); + vcdp->chgArray(c+8017,(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT____Vcellinp__dwb_queue__data_in),200); + vcdp->chgArray(c+8073,(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT____Vcellout__dwb_queue__data_out),200); + vcdp->chgBit(c+8129,(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__dwb_queue__DOT__writing)); + vcdp->chgBit(c+8137,(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__snrq_pop)); + vcdp->chgBus(c+8145,((0x3ffffffU & (IData)( + (vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT____Vcellout__snp_req_queue__data_out + >> 0x1dU)))),26); + vcdp->chgBit(c+8153,((1U & (IData)((vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT____Vcellout__snp_req_queue__data_out + >> 0x1cU))))); + vcdp->chgBus(c+8161,((0xfffffffU & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT____Vcellout__snp_req_queue__data_out))),28); + vcdp->chgBit(c+8169,(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__dfpq_pop)); + vcdp->chgBus(c+8177,((0x3ffffffU & vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT____Vcellout__dfp_queue__data_out[4U])),26); + __Vtemp701[0U] = vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT____Vcellout__dfp_queue__data_out[0U]; + __Vtemp701[1U] = vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT____Vcellout__dfp_queue__data_out[1U]; + __Vtemp701[2U] = vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT____Vcellout__dfp_queue__data_out[2U]; + __Vtemp701[3U] = vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT____Vcellout__dfp_queue__data_out[3U]; + vcdp->chgArray(c+8185,(__Vtemp701),128); + vcdp->chgBit(c+8217,(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__reqq_pop)); + vcdp->chgBit(c+8225,((1U & (~ (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__core_req_arb__DOT__qual_has_request))))); + vcdp->chgBit(c+8233,(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__core_req_arb__DOT__qual_has_request)); + vcdp->chgBus(c+8241,(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__core_req_arb__DOT__qual_request_index),2); + vcdp->chgBit(c+8249,(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__reqq_req_rw_st0)); + vcdp->chgBus(c+8257,((0xfU & ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__core_req_arb__DOT__use_per_byteen) + >> (0xfU & ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__core_req_arb__DOT__qual_request_index) + << 2U))))),4); + vcdp->chgBus(c+8265,(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__reqq_req_addr_st0),30); + vcdp->chgBus(c+8273,((((0U == (0x1fU & ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__core_req_arb__DOT__qual_request_index) + << 5U))) + ? 0U : (vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__core_req_arb__DOT__use_per_writedata[ + ((IData)(1U) + + (3U & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__core_req_arb__DOT__qual_request_index)))] + << ((IData)(0x20U) + - (0x1fU + & ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__core_req_arb__DOT__qual_request_index) + << 5U))))) + | (vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__core_req_arb__DOT__use_per_writedata[ + (3U & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__core_req_arb__DOT__qual_request_index))] + >> (0x1fU & ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__core_req_arb__DOT__qual_request_index) + << 5U))))),32); + vcdp->chgBit(c+8281,(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__mrvq_pop)); + vcdp->chgBit(c+8289,(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cache_miss_resrv__DOT__dequeue_possible)); + vcdp->chgBit(c+8297,(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__mrvq_rw_st0)); + vcdp->chgBit(c+8305,((0U != (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cache_miss_resrv__DOT__valid_address_match)))); + vcdp->chgBit(c+8313,(((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__miss_add_because_miss) + & (((0x3ffffffU & ((vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__st_1e_2__DOT__value[9U] + << 7U) + | (vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__st_1e_2__DOT__value[8U] + >> 0x19U))) + == vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__addr_st1 + [0U]) & (~ (vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__st_1e_2__DOT__value[9U] + >> 0x14U)))))); + vcdp->chgBit(c+8321,(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__force_request_miss_st1e)); + vcdp->chgBit(c+8329,(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__recover_mrvq_state_st2)); + vcdp->chgBit(c+8337,(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__mrvq_push_stall)); + vcdp->chgBit(c+8345,(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cwbq_push_stall)); + vcdp->chgBit(c+8353,(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__dwbq_push_stall)); + vcdp->chgBit(c+8361,(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__dram_fill_req_stall)); + vcdp->chgBit(c+8369,(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__stall_bank_pipe)); + vcdp->chgBit(c+8377,(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__is_fill_in_pipe)); + vcdp->chgBit(c+8385,(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__is_fill_st1[0])); + vcdp->chgBit(c+8393,(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__going_to_write_st1[0])); + vcdp->chgBit(c+8401,(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__dfpq_pop_unqual)); + vcdp->chgBit(c+8409,(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__reqq_pop_unqual)); + vcdp->chgBit(c+8417,(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__snrq_pop_unqual)); + vcdp->chgBit(c+8425,(((((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__dfpq_pop) + | (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__mrvq_pop)) + | (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__reqq_pop)) + | (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__snrq_pop)))); + vcdp->chgBus(c+8433,((0x3ffffffU & ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__dfpq_pop_unqual) + ? (0x3ffffffU + & vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT____Vcellout__dfp_queue__data_out[4U]) + : ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cache_miss_resrv__DOT__dequeue_possible) + ? + ((0x19fU + >= + (0x1ffU + & ((IData)(0x1aU) + * (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr)))) + ? + (0x3ffffffU + & (((0U + == + (0x1fU + & ((IData)(0x1aU) + * (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr)))) + ? 0U + : + (vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cache_miss_resrv__DOT__addr_table[ + ((IData)(1U) + + + (0xfU + & (((IData)(0x1aU) + * (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr)) + >> 5U)))] + << + ((IData)(0x20U) + - + (0x1fU + & ((IData)(0x1aU) + * (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr)))))) + | (vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cache_miss_resrv__DOT__addr_table[ + (0xfU + & (((IData)(0x1aU) + * (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr)) + >> 5U))] + >> + (0x1fU + & ((IData)(0x1aU) + * (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr)))))) + : 0U) + : + ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__reqq_pop_unqual) + ? + (0x3ffffffU + & (vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__reqq_req_addr_st0 + >> 4U)) + : + ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__snrq_pop_unqual) + ? + (0x3ffffffU + & (IData)( + (vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT____Vcellout__snp_req_queue__data_out + >> 0x1dU))) + : 0U)))))),26); + vcdp->chgBus(c+8441,((3U & ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__reqq_pop_unqual) + ? (3U & vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__reqq_req_addr_st0) + : ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cache_miss_resrv__DOT__dequeue_possible) + ? (3U & (( + vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cache_miss_resrv__DOT__metadata_table + [vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr][1U] + << 0x1eU) + | (vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cache_miss_resrv__DOT__metadata_table + [vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr][0U] + >> 2U))) + : 0U)))),2); + vcdp->chgBus(c+8449,(((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cache_miss_resrv__DOT__dequeue_possible) + ? ((vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cache_miss_resrv__DOT__metadata_table + [vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr][2U] + << 0xbU) | (vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cache_miss_resrv__DOT__metadata_table + [vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr][1U] + >> 0x15U)) + : ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__reqq_pop_unqual) + ? (((0U == (0x1fU + & ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__core_req_arb__DOT__qual_request_index) + << 5U))) + ? 0U : (vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__core_req_arb__DOT__use_per_writedata[ + ((IData)(1U) + + + (3U + & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__core_req_arb__DOT__qual_request_index)))] + << + ((IData)(0x20U) + - + (0x1fU + & ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__core_req_arb__DOT__qual_request_index) + << 5U))))) + | (vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__core_req_arb__DOT__use_per_writedata[ + (3U & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__core_req_arb__DOT__qual_request_index))] + >> (0x1fU + & ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__core_req_arb__DOT__qual_request_index) + << 5U)))) + : 0U))),32); + __Vtemp706[0U] = ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__dfpq_pop_unqual) + ? vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT____Vcellout__dfp_queue__data_out[0U] + : 0x39U); + __Vtemp706[1U] = ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__dfpq_pop_unqual) + ? vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT____Vcellout__dfp_queue__data_out[1U] + : 0U); + __Vtemp706[2U] = ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__dfpq_pop_unqual) + ? vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT____Vcellout__dfp_queue__data_out[2U] + : 0U); + __Vtemp706[3U] = ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__dfpq_pop_unqual) + ? vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT____Vcellout__dfp_queue__data_out[3U] + : 0U); + vcdp->chgArray(c+8457,(__Vtemp706),128); + vcdp->chgQuad(c+8489,(((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cache_miss_resrv__DOT__dequeue_possible) + ? ((VL_ULL(0x1ffffffffff80) + & (((QData)((IData)( + vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cache_miss_resrv__DOT__metadata_table + [vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr][2U])) + << 0x3eU) | + (((QData)((IData)( + vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cache_miss_resrv__DOT__metadata_table + [vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr][1U])) + << 0x1eU) + | (VL_ULL(0x3fffffffffffff80) + & ((QData)((IData)( + vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cache_miss_resrv__DOT__metadata_table + [vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr][0U])) + >> 2U))))) + | (QData)((IData)( + (((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__mrvq_rw_st0) + << 6U) + | ((0x3cU + & ((vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cache_miss_resrv__DOT__metadata_table + [vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr][1U] + << 0x1eU) + | (0x3ffffffcU + & (vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cache_miss_resrv__DOT__metadata_table + [vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr][0U] + >> 2U)))) + | (3U + & ((vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cache_miss_resrv__DOT__metadata_table + [vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr][2U] + << 0xdU) + | (vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cache_miss_resrv__DOT__metadata_table + [vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr][1U] + >> 0x13U)))))))) + : ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__reqq_pop_unqual) + ? ((vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__core_req_arb__DOT__use_per_tag + << 7U) | (QData)((IData)( + (((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__reqq_req_rw_st0) + << 6U) + | ((0x3cU + & (((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__core_req_arb__DOT__use_per_byteen) + >> + (0xfU + & ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__core_req_arb__DOT__qual_request_index) + << 2U))) + << 2U)) + | (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__core_req_arb__DOT__qual_request_index)))))) + : ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__snrq_pop_unqual) + ? ((QData)((IData)( + (0xfffffffU + & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT____Vcellout__snp_req_queue__data_out)))) + << 7U) : VL_ULL(0))))),49); + vcdp->chgBit(c+8505,(((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__dfpq_pop_unqual) + ? 1U : (((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cache_miss_resrv__DOT__dequeue_possible) + & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__mrvq_rw_st0)) + ? 1U : (((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__reqq_pop_unqual) + & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__reqq_req_rw_st0)) + ? 1U + : 0U))))); + vcdp->chgBit(c+8513,((1U & ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cache_miss_resrv__DOT__dequeue_possible) + ? (1U & (vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cache_miss_resrv__DOT__metadata_table + [vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr][0U] + >> 1U)) + : ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__snrq_pop_unqual) + ? 1U : 0U))))); + vcdp->chgBit(c+8521,((1U & ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cache_miss_resrv__DOT__dequeue_possible) + ? (1U & vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cache_miss_resrv__DOT__metadata_table + [vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr][0U]) + : ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__snrq_pop_unqual) + ? (1U & (IData)( + (vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT____Vcellout__snp_req_queue__data_out + >> 0x1cU))) + : 0U))))); + vcdp->chgBit(c+8529,(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__valid_st1[0])); + vcdp->chgBus(c+8537,(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__addr_st1[0]),26); + vcdp->chgBus(c+8545,(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__wsel_st1[0]),2); + vcdp->chgBus(c+8553,(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__writeword_st1[0]),32); + vcdp->chgQuad(c+8561,(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__inst_meta_st1[0]),49); + vcdp->chgArray(c+8577,(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__writedata_st1[0]),128); + vcdp->chgBit(c+8609,(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__is_snp_st1[0])); + vcdp->chgBit(c+8617,(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__snp_invalidate_st1[0])); + vcdp->chgBit(c+8625,(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__is_mrvq_st1[0])); + __Vtemp712[0U] = vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__tag_data_access__DOT__read_data_st1c + [0U][0U]; + __Vtemp712[1U] = vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__tag_data_access__DOT__read_data_st1c + [0U][1U]; + __Vtemp712[2U] = vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__tag_data_access__DOT__read_data_st1c + [0U][2U]; + __Vtemp712[3U] = vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__tag_data_access__DOT__read_data_st1c + [0U][3U]; + vcdp->chgBus(c+8633,((((0U == (0x1fU & (vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__wsel_st1 + [0U] + << 5U))) + ? 0U : (__Vtemp712[ + ((IData)(1U) + + (3U & vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__wsel_st1 + [0U]))] + << ((IData)(0x20U) + - (0x1fU + & (vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__wsel_st1 + [0U] + << 5U))))) + | (__Vtemp712[(3U & vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__wsel_st1 + [0U])] + >> (0x1fU & (vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__wsel_st1 + [0U] + << 5U))))),32); + __Vtemp713[0U] = vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__tag_data_access__DOT__read_data_st1c + [0U][0U]; + __Vtemp713[1U] = vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__tag_data_access__DOT__read_data_st1c + [0U][1U]; + __Vtemp713[2U] = vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__tag_data_access__DOT__read_data_st1c + [0U][2U]; + __Vtemp713[3U] = vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__tag_data_access__DOT__read_data_st1c + [0U][3U]; + vcdp->chgArray(c+8641,(__Vtemp713),128); + vcdp->chgBus(c+8673,(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__tag_data_access__DOT__read_tag_st1c + [0U]),20); + vcdp->chgBit(c+8681,(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__miss_st1e)); + vcdp->chgBit(c+8689,(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__dirty_st1e)); + vcdp->chgBus(c+8697,(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__tag_data_access__DOT__read_dirtyb_st1c + [0U]),16); + vcdp->chgQuad(c+8705,((VL_ULL(0x3ffffffffff) + & (vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__inst_meta_st1 + [0U] >> 7U))),42); + vcdp->chgBus(c+8721,((3U & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__inst_meta_st1 + [0U]))),2); + vcdp->chgBit(c+8729,((1U & (IData)((vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__inst_meta_st1 + [0U] >> 6U))))); + vcdp->chgBus(c+8737,((0xfU & (IData)((vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__inst_meta_st1 + [0U] + >> 2U)))),4); + vcdp->chgBit(c+8745,(((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__tag_data_access__DOT__real_writefill) + & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__dirty_st1e)))); + vcdp->chgBit(c+8753,(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__is_snp_st1 + [0U])); + vcdp->chgBit(c+8761,(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__snp_invalidate_st1 + [0U])); + vcdp->chgBit(c+8769,(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__snp_to_mrvq_st1e)); + vcdp->chgBit(c+8777,(((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__snp_to_mrvq_st1e) + | ((((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__force_request_miss_st1e) + & (~ vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__is_snp_st1 + [0U])) & (~ vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__is_fill_st1 + [0U])) + & vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__valid_st1 + [0U])))); + vcdp->chgBit(c+8785,(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__miss_add_because_miss)); + vcdp->chgBit(c+8793,(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__valid_st1 + [0U])); + vcdp->chgBit(c+8801,(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__is_mrvq_st1 + [0U])); + vcdp->chgBit(c+8809,((((vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__valid_st1 + [0U] & vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__is_mrvq_st1 + [0U]) & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__recover_mrvq_state_st2)) + & ((0x3ffffffU & ((vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__st_1e_2__DOT__value[9U] + << 7U) + | (vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__st_1e_2__DOT__value[8U] + >> 0x19U))) + == vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__addr_st1 + [0U])))); + vcdp->chgBus(c+8817,(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__addr_st1 + [0U]),26); + vcdp->chgBit(c+8825,((vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__valid_st1 + [0U] & (~ vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__is_fill_st1 + [0U])))); + vcdp->chgBit(c+8833,(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__mrvq_init_ready_state_st2)); + vcdp->chgBit(c+8841,((((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__miss_add_unqual) + & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__dfpq_pop_unqual)) + & ((0x3ffffffU & ((vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__st_1e_2__DOT__value[9U] + << 7U) + | (vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__st_1e_2__DOT__value[8U] + >> 0x19U))) + == (0x3ffffffU & vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT____Vcellout__dfp_queue__data_out[4U]))))); + vcdp->chgBit(c+8849,((((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__miss_add_unqual) + & vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__is_fill_st1 + [0U]) & ((0x3ffffffU + & ((vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__st_1e_2__DOT__value[9U] + << 7U) + | (vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__st_1e_2__DOT__value[8U] + >> 0x19U))) + == vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__addr_st1 + [0U])))); + vcdp->chgBit(c+8857,(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__miss_add_unqual)); + vcdp->chgBit(c+8865,(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__miss_add)); + vcdp->chgBit(c+8873,(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__miss_add_is_mrvq)); + vcdp->chgBit(c+8881,(((((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cwbq_push_unqual) + & (~ (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cwb_queue__DOT__genblk3__DOT__genblk2__DOT__full_r))) + & (~ (vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__st_1e_2__DOT__value[0U] + >> 6U))) & (~ + (((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__dwbq_push_stall) + | (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__mrvq_push_stall)) + | (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__dram_fill_req_stall)))))); + vcdp->chgBit(c+8889,(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cwbq_push_unqual)); + vcdp->chgBit(c+8897,(((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__miss_add_unqual) + & ((~ (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__mrvq_init_ready_state_st2)) + | ((vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__st_1e_2__DOT__value[9U] + >> 0x1aU) & (~ + (vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__st_1e_2__DOT__value[9U] + >> 0x1bU))))))); + vcdp->chgBit(c+8905,((((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__dwbq_push_unqual) + & (~ (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__genblk2__DOT__full_r))) + & (~ (((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cwbq_push_stall) + | (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__mrvq_push_stall)) + | (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__dram_fill_req_stall)))))); + vcdp->chgBit(c+8913,(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__dwbq_is_dwb_in)); + vcdp->chgBit(c+8921,(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__dwbq_is_snp_in)); + vcdp->chgBit(c+8929,((1U & (vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT____Vcellout__dwb_queue__data_out[6U] + >> 7U)))); + vcdp->chgBit(c+8937,((1U & (vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT____Vcellout__dwb_queue__data_out[6U] + >> 6U)))); + vcdp->chgBit(c+8945,(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__dwbq_push_unqual)); + vcdp->chgQuad(c+8953,(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT____Vcellout__snp_req_queue__data_out),55); + vcdp->chgBit(c+8969,(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__snp_req_queue__DOT__reading)); + vcdp->chgArray(c+8977,(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT____Vcellout__dfp_queue__data_out),154); + vcdp->chgBit(c+9017,(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__dfp_queue__DOT__reading)); + vcdp->chgBus(c+9025,((0xfU & (vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__core_req_arb__DOT____Vcellout__reqq_queue__data_out[9U] + >> 0x16U))),4); + vcdp->chgBus(c+9033,((0xfU & (vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__core_req_arb__DOT____Vcellout__reqq_queue__data_out[9U] + >> 0x12U))),4); + vcdp->chgBus(c+9041,((0xffffU & (vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__core_req_arb__DOT____Vcellout__reqq_queue__data_out[9U] + >> 2U))),16); + __Vtemp716[0U] = ((vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__core_req_arb__DOT____Vcellout__reqq_queue__data_out[6U] + << 0x16U) | (vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__core_req_arb__DOT____Vcellout__reqq_queue__data_out[5U] + >> 0xaU)); + __Vtemp716[1U] = ((vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__core_req_arb__DOT____Vcellout__reqq_queue__data_out[7U] + << 0x16U) | (vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__core_req_arb__DOT____Vcellout__reqq_queue__data_out[6U] + >> 0xaU)); + __Vtemp716[2U] = ((vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__core_req_arb__DOT____Vcellout__reqq_queue__data_out[8U] + << 0x16U) | (vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__core_req_arb__DOT____Vcellout__reqq_queue__data_out[7U] + >> 0xaU)); + __Vtemp716[3U] = (0xffffffU & ((vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__core_req_arb__DOT____Vcellout__reqq_queue__data_out[9U] + << 0x16U) | + (vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__core_req_arb__DOT____Vcellout__reqq_queue__data_out[8U] + >> 0xaU))); + vcdp->chgArray(c+9049,(__Vtemp716),120); + __Vtemp717[0U] = ((vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__core_req_arb__DOT____Vcellout__reqq_queue__data_out[2U] + << 0x16U) | (vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__core_req_arb__DOT____Vcellout__reqq_queue__data_out[1U] + >> 0xaU)); + __Vtemp717[1U] = ((vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__core_req_arb__DOT____Vcellout__reqq_queue__data_out[3U] + << 0x16U) | (vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__core_req_arb__DOT____Vcellout__reqq_queue__data_out[2U] + >> 0xaU)); + __Vtemp717[2U] = ((vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__core_req_arb__DOT____Vcellout__reqq_queue__data_out[4U] + << 0x16U) | (vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__core_req_arb__DOT____Vcellout__reqq_queue__data_out[3U] + >> 0xaU)); + __Vtemp717[3U] = ((vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__core_req_arb__DOT____Vcellout__reqq_queue__data_out[5U] + << 0x16U) | (vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__core_req_arb__DOT____Vcellout__reqq_queue__data_out[4U] + >> 0xaU)); + vcdp->chgArray(c+9081,(__Vtemp717),128); + vcdp->chgQuad(c+9113,((VL_ULL(0x3ffffffffff) + & (((QData)((IData)( + vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__core_req_arb__DOT____Vcellout__reqq_queue__data_out[1U])) + << 0x20U) | (QData)((IData)( + vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__core_req_arb__DOT____Vcellout__reqq_queue__data_out[0U]))))),42); + vcdp->chgBit(c+9129,(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__core_req_arb__DOT__out_empty)); + vcdp->chgBit(c+9137,(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__core_req_arb__DOT__pop_qual)); + vcdp->chgBus(c+9145,((0xfU & ((vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__core_req_arb__DOT____Vcellout__reqq_queue__data_out[9U] + >> 0x16U) & + VL_NEGATE_I((IData)( + (1U + & (~ (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__core_req_arb__DOT__out_empty)))))))),4); + vcdp->chgArray(c+9153,(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__core_req_arb__DOT____Vcellout__reqq_queue__data_out),314); + vcdp->chgBit(c+9233,(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__reading)); + vcdp->chgBus(c+9241,(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__core_req_arb__DOT__sel_bank__DOT__genblk2__DOT__grant_onehot_r),4); + vcdp->chgBus(c+9249,(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__core_req_arb__DOT__sel_bank__DOT__genblk2__DOT__priority_encoder__DOT__i),32); + vcdp->chgArray(c+9257,(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT____Vcellinp__s0_1_c0__in),243); + vcdp->chgBus(c+9321,((0x3fU & vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__addr_st1 + [0U])),6); + vcdp->chgBit(c+9329,(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__is_fill_st1 + [0U])); + vcdp->chgBus(c+9337,(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__writeword_st1 + [0U]),32); + __Vtemp718[0U] = vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__writedata_st1 + [0U][0U]; + __Vtemp718[1U] = vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__writedata_st1 + [0U][1U]; + __Vtemp718[2U] = vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__writedata_st1 + [0U][2U]; + __Vtemp718[3U] = vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__writedata_st1 + [0U][3U]; + vcdp->chgArray(c+9345,(__Vtemp718),128); + vcdp->chgBus(c+9377,(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__wsel_st1 + [0U]),2); + vcdp->chgBit(c+9385,(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__tag_data_access__DOT__read_valid_st1c[0])); + vcdp->chgBit(c+9393,(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__tag_data_access__DOT__read_dirty_st1c[0])); + vcdp->chgBus(c+9401,(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__tag_data_access__DOT__read_dirtyb_st1c[0]),16); + vcdp->chgBus(c+9409,(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__tag_data_access__DOT__read_tag_st1c[0]),20); + vcdp->chgArray(c+9417,(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__tag_data_access__DOT__read_data_st1c[0]),128); + vcdp->chgBit(c+9449,((1U & (IData)((vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__valid + >> (0x3fU + & vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__addr_st1 + [0U])))))); + vcdp->chgBit(c+9457,((1U & (IData)((vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__dirty + >> (0x3fU + & vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__addr_st1 + [0U])))))); + vcdp->chgBus(c+9465,(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__dirtyb + [(0x3fU & vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__addr_st1 + [0U])]),16); + vcdp->chgBus(c+9473,(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__tag + [(0x3fU & vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__addr_st1 + [0U])]),20); + __Vtemp719[0U] = vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__data + [(0x3fU & vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__addr_st1 + [0U])][0U]; + __Vtemp719[1U] = vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__data + [(0x3fU & vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__addr_st1 + [0U])][1U]; + __Vtemp719[2U] = vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__data + [(0x3fU & vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__addr_st1 + [0U])][2U]; + __Vtemp719[3U] = vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__data + [(0x3fU & vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__addr_st1 + [0U])][3U]; + vcdp->chgArray(c+9481,(__Vtemp719),128); + vcdp->chgBit(c+9513,(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__tag_data_access__DOT__read_valid_st1c + [0U])); + vcdp->chgBit(c+9521,(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__tag_data_access__DOT__read_dirty_st1c + [0U])); + vcdp->chgBus(c+9529,(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__tag_data_access__DOT__use_write_enable),16); + vcdp->chgArray(c+9537,(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__tag_data_access__DOT__data_write),128); + vcdp->chgBit(c+9569,(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__tag_data_access__DOT__snoop_hit_no_pending)); + vcdp->chgBit(c+9577,(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__tag_data_access__DOT__tags_match)); + vcdp->chgBit(c+9585,(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__tag_data_access__DOT__real_writefill)); + vcdp->chgBus(c+9593,((0xfffffU & (vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__addr_st1 + [0U] >> 6U))),20); + vcdp->chgBus(c+9601,(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__tag_data_access__DOT__we),16); + vcdp->chgBit(c+9609,(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__tag_data_access__DOT__should_write)); + vcdp->chgBit(c+9617,((((vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__valid_st1 + [0U] & (~ vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__is_snp_st1 + [0U])) & (~ + vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__tag_data_access__DOT__read_valid_st1c + [0U])) + & (~ vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__is_fill_st1 + [0U])))); + vcdp->chgBit(c+9625,(((((vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__valid_st1 + [0U] & (~ vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__is_snp_st1 + [0U])) & vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__tag_data_access__DOT__read_valid_st1c + [0U]) & (~ vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__is_fill_st1 + [0U])) & (~ (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__tag_data_access__DOT__tags_match))))); + vcdp->chgBit(c+9633,(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__tag_data_access__DOT__real_miss)); + vcdp->chgBit(c+9641,((((((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__force_request_miss_st1e) + & (~ vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__is_snp_st1 + [0U])) & (~ vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__is_fill_st1 + [0U])) + & vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__valid_st1 + [0U]) & (~ (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__tag_data_access__DOT__real_miss))))); + vcdp->chgBit(c+9649,(((0U == vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__wsel_st1 + [0U]) & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__tag_data_access__DOT__should_write)))); + vcdp->chgBit(c+9657,(((1U == vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__wsel_st1 + [0U]) & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__tag_data_access__DOT__should_write)))); + vcdp->chgBit(c+9665,(((2U == vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__wsel_st1 + [0U]) & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__tag_data_access__DOT__should_write)))); + vcdp->chgBit(c+9673,(((3U == vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__wsel_st1 + [0U]) & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__tag_data_access__DOT__should_write)))); + vcdp->chgBit(c+9681,((0U != (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__tag_data_access__DOT__use_write_enable)))); + vcdp->chgArray(c+9689,(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__tag_data_access__DOT____Vcellinp__s0_1_c0__in),166); + vcdp->chgArray(c+9737,(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT____Vcellinp__st_1e_2__in),316); + vcdp->chgBus(c+9817,(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cache_miss_resrv__DOT__make_ready),16); + vcdp->chgBus(c+9825,((0xffffU & (((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cache_miss_resrv__DOT__mrvq_push) + & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__mrvq_init_ready_state_st2)) + << (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cache_miss_resrv__DOT__tail_ptr)))),16); + vcdp->chgBus(c+9833,(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cache_miss_resrv__DOT__valid_address_match),16); + vcdp->chgBit(c+9841,(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cache_miss_resrv__DOT__mrvq_push)); + vcdp->chgBit(c+9849,(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cache_miss_resrv__DOT__mrvq_pop)); + vcdp->chgBit(c+9857,(((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__miss_add) + & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__miss_add_is_mrvq)))); + vcdp->chgBit(c+9865,(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cache_miss_resrv__DOT__increment_head)); + vcdp->chgBit(c+9873,((0U != (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cache_miss_resrv__DOT__make_ready)))); + vcdp->chgBit(c+9881,(((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cache_miss_resrv__DOT__mrvq_push) + & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__mrvq_init_ready_state_st2)))); + vcdp->chgArray(c+9889,(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT____Vcellinp__cwb_queue__data_in),76); + vcdp->chgArray(c+9913,(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT____Vcellout__cwb_queue__data_out),76); + vcdp->chgBit(c+9937,(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cwb_queue__DOT__writing)); + vcdp->chgArray(c+9945,(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT____Vcellinp__dwb_queue__data_in),200); + vcdp->chgArray(c+10001,(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT____Vcellout__dwb_queue__data_out),200); + vcdp->chgBit(c+10057,(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__dwb_queue__DOT__writing)); + } +} + +void VVX_cache::traceChgThis__5(VVX_cache__Syms* __restrict vlSymsp, VerilatedVcd* vcdp, uint32_t code) { + VVX_cache* __restrict vlTOPp VL_ATTR_UNUSED = vlSymsp->TOPp; + int c = code; + if (0 && vcdp && c) {} // Prevent unused + // Variables + WData/*127:0*/ __Vtemp727[4]; + WData/*127:0*/ __Vtemp735[4]; + WData/*127:0*/ __Vtemp743[4]; + WData/*127:0*/ __Vtemp751[4]; + // Body + { + vcdp->chgBit(c+10065,((1U & (~ (IData)(vlTOPp->VX_cache__DOT__cache_dram_req_arb__DOT__dram_fill_arb__DOT__dfqq_queue__DOT__genblk3__DOT__genblk2__DOT__full_r))))); + vcdp->chgBit(c+10073,((1U & (~ (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cwb_queue__DOT__genblk3__DOT__genblk2__DOT__empty_r))))); + vcdp->chgBit(c+10081,((1U & (~ (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__dfp_queue__DOT__genblk3__DOT__genblk2__DOT__full_r))))); + vcdp->chgBus(c+10089,((0x3ffffffU & ((vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__st_1e_2__DOT__value[9U] + << 7U) + | (vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__st_1e_2__DOT__value[8U] + >> 0x19U)))),26); + vcdp->chgBit(c+10097,((1U & (~ (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__snp_req_queue__DOT__genblk3__DOT__genblk2__DOT__full_r))))); + vcdp->chgBit(c+10105,((1U & (~ (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__full_r))))); + vcdp->chgBit(c+10113,((1U & (~ (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__cwb_queue__DOT__genblk3__DOT__genblk2__DOT__empty_r))))); + vcdp->chgBit(c+10121,((1U & (~ (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__dfp_queue__DOT__genblk3__DOT__genblk2__DOT__full_r))))); + vcdp->chgBus(c+10129,((0x3ffffffU & ((vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__st_1e_2__DOT__value[9U] + << 7U) + | (vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__st_1e_2__DOT__value[8U] + >> 0x19U)))),26); + vcdp->chgBit(c+10137,((1U & (~ (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__snp_req_queue__DOT__genblk3__DOT__genblk2__DOT__full_r))))); + vcdp->chgBit(c+10145,((1U & (~ (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__full_r))))); + vcdp->chgBit(c+10153,((1U & (~ (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__cwb_queue__DOT__genblk3__DOT__genblk2__DOT__empty_r))))); + vcdp->chgBit(c+10161,((1U & (~ (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__dfp_queue__DOT__genblk3__DOT__genblk2__DOT__full_r))))); + vcdp->chgBus(c+10169,((0x3ffffffU & ((vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__st_1e_2__DOT__value[9U] + << 7U) + | (vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__st_1e_2__DOT__value[8U] + >> 0x19U)))),26); + vcdp->chgBit(c+10177,((1U & (~ (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__snp_req_queue__DOT__genblk3__DOT__genblk2__DOT__full_r))))); + vcdp->chgBit(c+10185,((1U & (~ (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__full_r))))); + vcdp->chgBit(c+10193,((1U & (~ (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cwb_queue__DOT__genblk3__DOT__genblk2__DOT__empty_r))))); + vcdp->chgBit(c+10201,((1U & (~ (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__dfp_queue__DOT__genblk3__DOT__genblk2__DOT__full_r))))); + vcdp->chgBus(c+10209,((0x3ffffffU & ((vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__st_1e_2__DOT__value[9U] + << 7U) + | (vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__st_1e_2__DOT__value[8U] + >> 0x19U)))),26); + vcdp->chgBit(c+10217,((1U & (~ (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__snp_req_queue__DOT__genblk3__DOT__genblk2__DOT__full_r))))); + vcdp->chgBit(c+10225,((1U & (~ (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__full_r))))); + vcdp->chgBus(c+10233,(vlTOPp->VX_cache__DOT__cache_dram_req_arb__DOT__prfqq__DOT__use_addr),28); + vcdp->chgBit(c+10241,(vlTOPp->VX_cache__DOT__cache_dram_req_arb__DOT__dram_fill_arb__DOT__dfqq_queue__DOT__genblk3__DOT__genblk2__DOT__full_r)); + vcdp->chgBus(c+10249,(vlTOPp->VX_cache__DOT__cache_dram_req_arb__DOT__prfqq__DOT__use_valid),2); + vcdp->chgBit(c+10257,(vlTOPp->VX_cache__DOT__cache_dram_req_arb__DOT__prfqq__DOT__pfq_queue__DOT__size_r)); + vcdp->chgBus(c+10265,(vlTOPp->VX_cache__DOT__cache_dram_req_arb__DOT__prfqq__DOT__pfq_queue__DOT__genblk2__DOT__head_r),28); + vcdp->chgBit(c+10273,((1U & (~ (IData)(vlTOPp->VX_cache__DOT__cache_dram_req_arb__DOT__prfqq__DOT__pfq_queue__DOT__size_r))))); + vcdp->chgBit(c+10281,(vlTOPp->VX_cache__DOT__cache_dram_req_arb__DOT__prfqq__DOT__pfq_queue__DOT__size_r)); + vcdp->chgBus(c+10289,(vlTOPp->VX_cache__DOT__cache_dram_req_arb__DOT__dram_fill_arb__DOT__use_per_bank_dram_fill_req_valid),4); + vcdp->chgArray(c+10297,(vlTOPp->VX_cache__DOT__cache_dram_req_arb__DOT__dram_fill_arb__DOT__use_per_bank_dram_fill_req_addr),112); + vcdp->chgBit(c+10329,(vlTOPp->VX_cache__DOT__cache_dram_req_arb__DOT__dram_fill_arb__DOT__dfqq_queue__DOT__genblk3__DOT__genblk2__DOT__empty_r)); + vcdp->chgBit(c+10337,((1U & (~ (IData)((0U + != (IData)(vlTOPp->VX_cache__DOT__cache_dram_req_arb__DOT__dram_fill_arb__DOT__use_per_bank_dram_fill_req_valid))))))); + vcdp->chgBus(c+10345,(vlTOPp->VX_cache__DOT__cache_dram_req_arb__DOT__dram_fill_arb__DOT__dfqq_queue__DOT__size_r),3); + vcdp->chgArray(c+10353,(vlTOPp->VX_cache__DOT__cache_dram_req_arb__DOT__dram_fill_arb__DOT__dfqq_queue__DOT__genblk3__DOT__data[0]),116); + vcdp->chgArray(c+10357,(vlTOPp->VX_cache__DOT__cache_dram_req_arb__DOT__dram_fill_arb__DOT__dfqq_queue__DOT__genblk3__DOT__data[1]),116); + vcdp->chgArray(c+10361,(vlTOPp->VX_cache__DOT__cache_dram_req_arb__DOT__dram_fill_arb__DOT__dfqq_queue__DOT__genblk3__DOT__data[2]),116); + vcdp->chgArray(c+10365,(vlTOPp->VX_cache__DOT__cache_dram_req_arb__DOT__dram_fill_arb__DOT__dfqq_queue__DOT__genblk3__DOT__data[3]),116); + vcdp->chgArray(c+10481,(vlTOPp->VX_cache__DOT__cache_dram_req_arb__DOT__dram_fill_arb__DOT__dfqq_queue__DOT__genblk3__DOT__genblk2__DOT__head_r),116); + vcdp->chgArray(c+10513,(vlTOPp->VX_cache__DOT__cache_dram_req_arb__DOT__dram_fill_arb__DOT__dfqq_queue__DOT__genblk3__DOT__genblk2__DOT__curr_r),116); + vcdp->chgBus(c+10545,(vlTOPp->VX_cache__DOT__cache_dram_req_arb__DOT__dram_fill_arb__DOT__dfqq_queue__DOT__genblk3__DOT__genblk2__DOT__wr_ptr_r),2); + vcdp->chgBus(c+10553,(vlTOPp->VX_cache__DOT__cache_dram_req_arb__DOT__dram_fill_arb__DOT__dfqq_queue__DOT__genblk3__DOT__genblk2__DOT__rd_ptr_r),2); + vcdp->chgBus(c+10561,(vlTOPp->VX_cache__DOT__cache_dram_req_arb__DOT__dram_fill_arb__DOT__dfqq_queue__DOT__genblk3__DOT__genblk2__DOT__rd_ptr_next_r),2); + vcdp->chgBit(c+10569,(vlTOPp->VX_cache__DOT__cache_dram_req_arb__DOT__dram_fill_arb__DOT__dfqq_queue__DOT__genblk3__DOT__genblk2__DOT__bypass_r)); + vcdp->chgBus(c+10577,(vlTOPp->VX_cache__DOT__cache_core_rsp_merge__DOT__sel_bank__DOT__genblk2__DOT__requests_use),4); + vcdp->chgBit(c+10585,((0U == (IData)(vlTOPp->VX_cache__DOT__cache_core_rsp_merge__DOT__sel_bank__DOT__genblk2__DOT__requests_use)))); + vcdp->chgBus(c+10593,(vlTOPp->VX_cache__DOT__cache_core_rsp_merge__DOT__sel_bank__DOT__genblk2__DOT__refill_original),4); + vcdp->chgBit(c+10601,(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__snp_req_queue__DOT__genblk3__DOT__genblk2__DOT__empty_r)); + vcdp->chgBit(c+10609,(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__snp_req_queue__DOT__genblk3__DOT__genblk2__DOT__full_r)); + vcdp->chgBit(c+10617,(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__dfp_queue__DOT__genblk3__DOT__genblk2__DOT__empty_r)); + vcdp->chgBit(c+10625,(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__dfp_queue__DOT__genblk3__DOT__genblk2__DOT__full_r)); + vcdp->chgBit(c+10633,(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__full_r)); + vcdp->chgQuad(c+10641,(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__core_req_arb__DOT__use_per_tag),42); + vcdp->chgBit(c+10657,((0x10U == (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cache_miss_resrv__DOT__size)))); + vcdp->chgBit(c+10665,((0xbU < (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cache_miss_resrv__DOT__size)))); + vcdp->chgBus(c+10673,((3U & ((vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cache_miss_resrv__DOT__metadata_table + [vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr][2U] + << 0xdU) | (vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cache_miss_resrv__DOT__metadata_table + [vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr][1U] + >> 0x13U)))),2); + vcdp->chgBus(c+10681,(((0x19fU >= (0x1ffU & + ((IData)(0x1aU) + * (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr)))) + ? (0x3ffffffU & (((0U + == + (0x1fU + & ((IData)(0x1aU) + * (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr)))) + ? 0U + : + (vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cache_miss_resrv__DOT__addr_table[ + ((IData)(1U) + + + (0xfU + & (((IData)(0x1aU) + * (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr)) + >> 5U)))] + << + ((IData)(0x20U) + - + (0x1fU + & ((IData)(0x1aU) + * (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr)))))) + | (vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cache_miss_resrv__DOT__addr_table[ + (0xfU + & (((IData)(0x1aU) + * (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr)) + >> 5U))] + >> + (0x1fU + & ((IData)(0x1aU) + * (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr)))))) + : 0U)),26); + vcdp->chgBus(c+10689,((3U & ((vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cache_miss_resrv__DOT__metadata_table + [vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr][1U] + << 0x1eU) | ( + vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cache_miss_resrv__DOT__metadata_table + [vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr][0U] + >> 2U)))),2); + vcdp->chgBus(c+10697,(((vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cache_miss_resrv__DOT__metadata_table + [vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr][2U] + << 0xbU) | (vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cache_miss_resrv__DOT__metadata_table + [vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr][1U] + >> 0x15U))),32); + vcdp->chgQuad(c+10705,((VL_ULL(0x3ffffffffff) + & (((QData)((IData)( + vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cache_miss_resrv__DOT__metadata_table + [vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr][2U])) + << 0x37U) | (((QData)((IData)( + vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cache_miss_resrv__DOT__metadata_table + [vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr][1U])) + << 0x17U) + | ((QData)((IData)( + vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cache_miss_resrv__DOT__metadata_table + [vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr][0U])) + >> 9U))))),42); + vcdp->chgBus(c+10721,((0xfU & ((vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cache_miss_resrv__DOT__metadata_table + [vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr][1U] + << 0x1cU) | + (vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cache_miss_resrv__DOT__metadata_table + [vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr][0U] + >> 4U)))),4); + vcdp->chgBit(c+10729,((1U & (vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cache_miss_resrv__DOT__metadata_table + [vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr][0U] + >> 1U)))); + vcdp->chgBit(c+10737,((1U & vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cache_miss_resrv__DOT__metadata_table + [vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr][0U]))); + vcdp->chgBus(c+10745,((3U & vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__st_1e_2__DOT__value[0U])),2); + vcdp->chgQuad(c+10753,((VL_ULL(0x3ffffffffff) + & (((QData)((IData)( + vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__st_1e_2__DOT__value[2U])) + << 0x39U) | (((QData)((IData)( + vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__st_1e_2__DOT__value[1U])) + << 0x19U) + | ((QData)((IData)( + vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__st_1e_2__DOT__value[0U])) + >> 7U))))),42); + vcdp->chgBit(c+10769,((1U & (vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__st_1e_2__DOT__value[0U] + >> 6U)))); + vcdp->chgBus(c+10777,((0xfU & ((vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__st_1e_2__DOT__value[1U] + << 0x1eU) | + (vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__st_1e_2__DOT__value[0U] + >> 2U)))),4); + vcdp->chgBit(c+10785,((1U & (vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__st_1e_2__DOT__value[9U] + >> 0x14U)))); + vcdp->chgBit(c+10793,((1U & (vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__st_1e_2__DOT__value[9U] + >> 0x13U)))); + vcdp->chgBus(c+10801,((3U & ((vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__st_1e_2__DOT__value[9U] + << 9U) | (vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__st_1e_2__DOT__value[8U] + >> 0x17U)))),2); + vcdp->chgBus(c+10809,(((vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__st_1e_2__DOT__value[8U] + << 9U) | (vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__st_1e_2__DOT__value[7U] + >> 0x17U))),32); + vcdp->chgBus(c+10817,(((vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__st_1e_2__DOT__value[7U] + << 9U) | (vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__st_1e_2__DOT__value[6U] + >> 0x17U))),32); + __Vtemp727[0U] = ((vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__st_1e_2__DOT__value[3U] + << 9U) | (vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__st_1e_2__DOT__value[2U] + >> 0x17U)); + __Vtemp727[1U] = ((vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__st_1e_2__DOT__value[4U] + << 9U) | (vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__st_1e_2__DOT__value[3U] + >> 0x17U)); + __Vtemp727[2U] = ((vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__st_1e_2__DOT__value[5U] + << 9U) | (vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__st_1e_2__DOT__value[4U] + >> 0x17U)); + __Vtemp727[3U] = ((vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__st_1e_2__DOT__value[6U] + << 9U) | (vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__st_1e_2__DOT__value[5U] + >> 0x17U)); + vcdp->chgArray(c+10825,(__Vtemp727),128); + vcdp->chgBit(c+10857,((1U & (vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__st_1e_2__DOT__value[2U] + >> 2U)))); + vcdp->chgBit(c+10865,((1U & (vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__st_1e_2__DOT__value[2U] + >> 1U)))); + vcdp->chgBus(c+10873,((0xffffU & ((vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__st_1e_2__DOT__value[2U] + << 0xfU) + | (vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__st_1e_2__DOT__value[1U] + >> 0x11U)))),16); + vcdp->chgQuad(c+10881,((VL_ULL(0x1ffffffffffff) + & (((QData)((IData)( + vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__st_1e_2__DOT__value[1U])) + << 0x20U) | (QData)((IData)( + vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__st_1e_2__DOT__value[0U]))))),49); + vcdp->chgBus(c+10897,((0xfffffU & ((vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__st_1e_2__DOT__value[3U] + << 0x1dU) + | (vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__st_1e_2__DOT__value[2U] + >> 3U)))),20); + vcdp->chgBit(c+10905,((1U & (vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__st_1e_2__DOT__value[9U] + >> 0x15U)))); + vcdp->chgBit(c+10913,((1U & (vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__st_1e_2__DOT__value[9U] + >> 0x17U)))); + vcdp->chgBit(c+10921,((1U & (vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__st_1e_2__DOT__value[9U] + >> 0x16U)))); + vcdp->chgBit(c+10929,((1U & (vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__st_1e_2__DOT__value[9U] + >> 0x18U)))); + vcdp->chgBit(c+10937,((1U & (vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__st_1e_2__DOT__value[9U] + >> 0x1aU)))); + vcdp->chgBit(c+10945,((1U & (vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__st_1e_2__DOT__value[9U] + >> 0x1bU)))); + vcdp->chgBit(c+10953,((1U & (vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__st_1e_2__DOT__value[9U] + >> 0x19U)))); + vcdp->chgBit(c+10961,(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cwb_queue__DOT__genblk3__DOT__genblk2__DOT__empty_r)); + vcdp->chgBit(c+10969,(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cwb_queue__DOT__genblk3__DOT__genblk2__DOT__full_r)); + vcdp->chgBit(c+10977,(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__genblk2__DOT__empty_r)); + vcdp->chgBit(c+10985,(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__genblk2__DOT__full_r)); + vcdp->chgBus(c+10993,(((0x3ffffc0U & (vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__st_1e_2__DOT__value[2U] + << 3U)) + | (0x3fU & ((vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__st_1e_2__DOT__value[9U] + << 7U) + | (vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__st_1e_2__DOT__value[8U] + >> 0x19U))))),26); + vcdp->chgBus(c+11001,((0xfffffffU & ((vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__st_1e_2__DOT__value[1U] + << 0x19U) + | (vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__st_1e_2__DOT__value[0U] + >> 7U)))),28); + vcdp->chgBit(c+11009,(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__dwbq_dual_valid_sel)); + vcdp->chgBus(c+11017,(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__snp_req_queue__DOT__size_r),5); + vcdp->chgQuad(c+11025,(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__snp_req_queue__DOT__genblk3__DOT__data[0]),55); + vcdp->chgQuad(c+11027,(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__snp_req_queue__DOT__genblk3__DOT__data[1]),55); + vcdp->chgQuad(c+11029,(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__snp_req_queue__DOT__genblk3__DOT__data[2]),55); + vcdp->chgQuad(c+11031,(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__snp_req_queue__DOT__genblk3__DOT__data[3]),55); + vcdp->chgQuad(c+11033,(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__snp_req_queue__DOT__genblk3__DOT__data[4]),55); + vcdp->chgQuad(c+11035,(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__snp_req_queue__DOT__genblk3__DOT__data[5]),55); + vcdp->chgQuad(c+11037,(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__snp_req_queue__DOT__genblk3__DOT__data[6]),55); + vcdp->chgQuad(c+11039,(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__snp_req_queue__DOT__genblk3__DOT__data[7]),55); + vcdp->chgQuad(c+11041,(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__snp_req_queue__DOT__genblk3__DOT__data[8]),55); + vcdp->chgQuad(c+11043,(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__snp_req_queue__DOT__genblk3__DOT__data[9]),55); + vcdp->chgQuad(c+11045,(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__snp_req_queue__DOT__genblk3__DOT__data[10]),55); + vcdp->chgQuad(c+11047,(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__snp_req_queue__DOT__genblk3__DOT__data[11]),55); + vcdp->chgQuad(c+11049,(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__snp_req_queue__DOT__genblk3__DOT__data[12]),55); + vcdp->chgQuad(c+11051,(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__snp_req_queue__DOT__genblk3__DOT__data[13]),55); + vcdp->chgQuad(c+11053,(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__snp_req_queue__DOT__genblk3__DOT__data[14]),55); + vcdp->chgQuad(c+11055,(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__snp_req_queue__DOT__genblk3__DOT__data[15]),55); + vcdp->chgQuad(c+11281,(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__snp_req_queue__DOT__genblk3__DOT__genblk2__DOT__head_r),55); + vcdp->chgQuad(c+11297,(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__snp_req_queue__DOT__genblk3__DOT__genblk2__DOT__curr_r),55); + vcdp->chgBus(c+11313,(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__snp_req_queue__DOT__genblk3__DOT__genblk2__DOT__wr_ptr_r),4); + vcdp->chgBus(c+11321,(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__snp_req_queue__DOT__genblk3__DOT__genblk2__DOT__rd_ptr_r),4); + vcdp->chgBus(c+11329,(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__snp_req_queue__DOT__genblk3__DOT__genblk2__DOT__rd_ptr_next_r),4); + vcdp->chgBit(c+11337,(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__snp_req_queue__DOT__genblk3__DOT__genblk2__DOT__bypass_r)); + vcdp->chgBus(c+11345,(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__dfp_queue__DOT__size_r),5); + vcdp->chgArray(c+11353,(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__dfp_queue__DOT__genblk3__DOT__data[0]),154); + vcdp->chgArray(c+11358,(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__dfp_queue__DOT__genblk3__DOT__data[1]),154); + vcdp->chgArray(c+11363,(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__dfp_queue__DOT__genblk3__DOT__data[2]),154); + vcdp->chgArray(c+11368,(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__dfp_queue__DOT__genblk3__DOT__data[3]),154); + vcdp->chgArray(c+11373,(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__dfp_queue__DOT__genblk3__DOT__data[4]),154); + vcdp->chgArray(c+11378,(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__dfp_queue__DOT__genblk3__DOT__data[5]),154); + vcdp->chgArray(c+11383,(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__dfp_queue__DOT__genblk3__DOT__data[6]),154); + vcdp->chgArray(c+11388,(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__dfp_queue__DOT__genblk3__DOT__data[7]),154); + vcdp->chgArray(c+11393,(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__dfp_queue__DOT__genblk3__DOT__data[8]),154); + vcdp->chgArray(c+11398,(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__dfp_queue__DOT__genblk3__DOT__data[9]),154); + vcdp->chgArray(c+11403,(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__dfp_queue__DOT__genblk3__DOT__data[10]),154); + vcdp->chgArray(c+11408,(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__dfp_queue__DOT__genblk3__DOT__data[11]),154); + vcdp->chgArray(c+11413,(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__dfp_queue__DOT__genblk3__DOT__data[12]),154); + vcdp->chgArray(c+11418,(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__dfp_queue__DOT__genblk3__DOT__data[13]),154); + vcdp->chgArray(c+11423,(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__dfp_queue__DOT__genblk3__DOT__data[14]),154); + vcdp->chgArray(c+11428,(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__dfp_queue__DOT__genblk3__DOT__data[15]),154); + vcdp->chgArray(c+11993,(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__dfp_queue__DOT__genblk3__DOT__genblk2__DOT__head_r),154); + vcdp->chgArray(c+12033,(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__dfp_queue__DOT__genblk3__DOT__genblk2__DOT__curr_r),154); + vcdp->chgBus(c+12073,(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__dfp_queue__DOT__genblk3__DOT__genblk2__DOT__wr_ptr_r),4); + vcdp->chgBus(c+12081,(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__dfp_queue__DOT__genblk3__DOT__genblk2__DOT__rd_ptr_r),4); + vcdp->chgBus(c+12089,(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__dfp_queue__DOT__genblk3__DOT__genblk2__DOT__rd_ptr_next_r),4); + vcdp->chgBit(c+12097,(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__dfp_queue__DOT__genblk3__DOT__genblk2__DOT__bypass_r)); + vcdp->chgBus(c+12105,(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__core_req_arb__DOT__use_per_valids),4); + vcdp->chgBus(c+12113,(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__core_req_arb__DOT__use_per_rw),4); + vcdp->chgBus(c+12121,(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__core_req_arb__DOT__use_per_byteen),16); + vcdp->chgArray(c+12129,(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__core_req_arb__DOT__use_per_addr),120); + vcdp->chgArray(c+12161,(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__core_req_arb__DOT__use_per_writedata),128); + vcdp->chgBit(c+12193,(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__empty_r)); + vcdp->chgBit(c+12201,((1U & (~ (IData)((0U + != (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__core_req_arb__DOT__use_per_valids))))))); + vcdp->chgBus(c+12209,(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__size_r),3); + vcdp->chgArray(c+12217,(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__data[0]),314); + vcdp->chgArray(c+12227,(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__data[1]),314); + vcdp->chgArray(c+12237,(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__data[2]),314); + vcdp->chgArray(c+12247,(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__data[3]),314); + vcdp->chgArray(c+12537,(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__head_r),314); + vcdp->chgArray(c+12617,(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__curr_r),314); + vcdp->chgBus(c+12697,(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__wr_ptr_r),2); + vcdp->chgBus(c+12705,(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__rd_ptr_r),2); + vcdp->chgBus(c+12713,(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__rd_ptr_next_r),2); + vcdp->chgBit(c+12721,(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__bypass_r)); + vcdp->chgArray(c+12729,(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__s0_1_c0__DOT__value),243); + vcdp->chgQuad(c+12793,(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__dirty),64); + vcdp->chgQuad(c+12809,(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__valid),64); + vcdp->chgBus(c+12825,(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__i),32); + vcdp->chgBus(c+12833,(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__j),32); + vcdp->chgArray(c+12841,(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__tag_data_access__DOT__s0_1_c0__DOT__value),166); + vcdp->chgArray(c+12889,(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__st_1e_2__DOT__value),316); + vcdp->chgArray(c+12969,(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cache_miss_resrv__DOT__metadata_table[0]),85); + vcdp->chgArray(c+12972,(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cache_miss_resrv__DOT__metadata_table[1]),85); + vcdp->chgArray(c+12975,(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cache_miss_resrv__DOT__metadata_table[2]),85); + vcdp->chgArray(c+12978,(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cache_miss_resrv__DOT__metadata_table[3]),85); + vcdp->chgArray(c+12981,(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cache_miss_resrv__DOT__metadata_table[4]),85); + vcdp->chgArray(c+12984,(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cache_miss_resrv__DOT__metadata_table[5]),85); + vcdp->chgArray(c+12987,(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cache_miss_resrv__DOT__metadata_table[6]),85); + vcdp->chgArray(c+12990,(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cache_miss_resrv__DOT__metadata_table[7]),85); + vcdp->chgArray(c+12993,(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cache_miss_resrv__DOT__metadata_table[8]),85); + vcdp->chgArray(c+12996,(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cache_miss_resrv__DOT__metadata_table[9]),85); + vcdp->chgArray(c+12999,(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cache_miss_resrv__DOT__metadata_table[10]),85); + vcdp->chgArray(c+13002,(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cache_miss_resrv__DOT__metadata_table[11]),85); + vcdp->chgArray(c+13005,(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cache_miss_resrv__DOT__metadata_table[12]),85); + vcdp->chgArray(c+13008,(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cache_miss_resrv__DOT__metadata_table[13]),85); + vcdp->chgArray(c+13011,(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cache_miss_resrv__DOT__metadata_table[14]),85); + vcdp->chgArray(c+13014,(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cache_miss_resrv__DOT__metadata_table[15]),85); + vcdp->chgArray(c+13353,(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cache_miss_resrv__DOT__addr_table),416); + vcdp->chgBus(c+13457,(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cache_miss_resrv__DOT__valid_table),16); + vcdp->chgBus(c+13465,(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cache_miss_resrv__DOT__ready_table),16); + vcdp->chgBus(c+13473,(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr),4); + vcdp->chgBus(c+13481,(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cache_miss_resrv__DOT__head_ptr),4); + vcdp->chgBus(c+13489,(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cache_miss_resrv__DOT__tail_ptr),4); + vcdp->chgBus(c+13497,(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cache_miss_resrv__DOT__size),5); + vcdp->chgBit(c+13505,((0x10U != (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cache_miss_resrv__DOT__size)))); + vcdp->chgBus(c+13513,(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cwb_queue__DOT__size_r),3); + vcdp->chgArray(c+13521,(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cwb_queue__DOT__genblk3__DOT__data[0]),76); + vcdp->chgArray(c+13524,(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cwb_queue__DOT__genblk3__DOT__data[1]),76); + vcdp->chgArray(c+13527,(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cwb_queue__DOT__genblk3__DOT__data[2]),76); + vcdp->chgArray(c+13530,(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cwb_queue__DOT__genblk3__DOT__data[3]),76); + vcdp->chgArray(c+13617,(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cwb_queue__DOT__genblk3__DOT__genblk2__DOT__head_r),76); + vcdp->chgArray(c+13641,(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cwb_queue__DOT__genblk3__DOT__genblk2__DOT__curr_r),76); + vcdp->chgBus(c+13665,(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cwb_queue__DOT__genblk3__DOT__genblk2__DOT__wr_ptr_r),2); + vcdp->chgBus(c+13673,(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cwb_queue__DOT__genblk3__DOT__genblk2__DOT__rd_ptr_r),2); + vcdp->chgBus(c+13681,(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cwb_queue__DOT__genblk3__DOT__genblk2__DOT__rd_ptr_next_r),2); + vcdp->chgBit(c+13689,(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cwb_queue__DOT__genblk3__DOT__genblk2__DOT__bypass_r)); + vcdp->chgBus(c+13697,(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__dwb_queue__DOT__size_r),3); + vcdp->chgArray(c+13705,(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__data[0]),200); + vcdp->chgArray(c+13712,(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__data[1]),200); + vcdp->chgArray(c+13719,(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__data[2]),200); + vcdp->chgArray(c+13726,(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__data[3]),200); + vcdp->chgArray(c+13929,(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__genblk2__DOT__head_r),200); + vcdp->chgArray(c+13985,(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__genblk2__DOT__curr_r),200); + vcdp->chgBus(c+14041,(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__genblk2__DOT__wr_ptr_r),2); + vcdp->chgBus(c+14049,(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__genblk2__DOT__rd_ptr_r),2); + vcdp->chgBus(c+14057,(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__genblk2__DOT__rd_ptr_next_r),2); + vcdp->chgBit(c+14065,(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__genblk2__DOT__bypass_r)); + vcdp->chgBit(c+14073,(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__snp_req_queue__DOT__genblk3__DOT__genblk2__DOT__empty_r)); + vcdp->chgBit(c+14081,(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__snp_req_queue__DOT__genblk3__DOT__genblk2__DOT__full_r)); + vcdp->chgBit(c+14089,(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__dfp_queue__DOT__genblk3__DOT__genblk2__DOT__empty_r)); + vcdp->chgBit(c+14097,(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__dfp_queue__DOT__genblk3__DOT__genblk2__DOT__full_r)); + vcdp->chgBit(c+14105,(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__full_r)); + vcdp->chgQuad(c+14113,(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__core_req_arb__DOT__use_per_tag),42); + vcdp->chgBit(c+14129,((0x10U == (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__cache_miss_resrv__DOT__size)))); + vcdp->chgBit(c+14137,((0xbU < (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__cache_miss_resrv__DOT__size)))); + vcdp->chgBus(c+14145,((3U & ((vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__cache_miss_resrv__DOT__metadata_table + [vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr][2U] + << 0xdU) | (vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__cache_miss_resrv__DOT__metadata_table + [vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr][1U] + >> 0x13U)))),2); + vcdp->chgBus(c+14153,(((0x19fU >= (0x1ffU & + ((IData)(0x1aU) + * (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr)))) + ? (0x3ffffffU & (((0U + == + (0x1fU + & ((IData)(0x1aU) + * (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr)))) + ? 0U + : + (vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__cache_miss_resrv__DOT__addr_table[ + ((IData)(1U) + + + (0xfU + & (((IData)(0x1aU) + * (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr)) + >> 5U)))] + << + ((IData)(0x20U) + - + (0x1fU + & ((IData)(0x1aU) + * (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr)))))) + | (vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__cache_miss_resrv__DOT__addr_table[ + (0xfU + & (((IData)(0x1aU) + * (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr)) + >> 5U))] + >> + (0x1fU + & ((IData)(0x1aU) + * (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr)))))) + : 0U)),26); + vcdp->chgBus(c+14161,((3U & ((vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__cache_miss_resrv__DOT__metadata_table + [vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr][1U] + << 0x1eU) | ( + vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__cache_miss_resrv__DOT__metadata_table + [vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr][0U] + >> 2U)))),2); + vcdp->chgBus(c+14169,(((vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__cache_miss_resrv__DOT__metadata_table + [vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr][2U] + << 0xbU) | (vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__cache_miss_resrv__DOT__metadata_table + [vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr][1U] + >> 0x15U))),32); + vcdp->chgQuad(c+14177,((VL_ULL(0x3ffffffffff) + & (((QData)((IData)( + vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__cache_miss_resrv__DOT__metadata_table + [vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr][2U])) + << 0x37U) | (((QData)((IData)( + vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__cache_miss_resrv__DOT__metadata_table + [vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr][1U])) + << 0x17U) + | ((QData)((IData)( + vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__cache_miss_resrv__DOT__metadata_table + [vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr][0U])) + >> 9U))))),42); + vcdp->chgBus(c+14193,((0xfU & ((vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__cache_miss_resrv__DOT__metadata_table + [vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr][1U] + << 0x1cU) | + (vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__cache_miss_resrv__DOT__metadata_table + [vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr][0U] + >> 4U)))),4); + vcdp->chgBit(c+14201,((1U & (vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__cache_miss_resrv__DOT__metadata_table + [vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr][0U] + >> 1U)))); + vcdp->chgBit(c+14209,((1U & vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__cache_miss_resrv__DOT__metadata_table + [vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr][0U]))); + vcdp->chgBus(c+14217,((3U & vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__st_1e_2__DOT__value[0U])),2); + vcdp->chgQuad(c+14225,((VL_ULL(0x3ffffffffff) + & (((QData)((IData)( + vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__st_1e_2__DOT__value[2U])) + << 0x39U) | (((QData)((IData)( + vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__st_1e_2__DOT__value[1U])) + << 0x19U) + | ((QData)((IData)( + vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__st_1e_2__DOT__value[0U])) + >> 7U))))),42); + vcdp->chgBit(c+14241,((1U & (vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__st_1e_2__DOT__value[0U] + >> 6U)))); + vcdp->chgBus(c+14249,((0xfU & ((vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__st_1e_2__DOT__value[1U] + << 0x1eU) | + (vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__st_1e_2__DOT__value[0U] + >> 2U)))),4); + vcdp->chgBit(c+14257,((1U & (vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__st_1e_2__DOT__value[9U] + >> 0x14U)))); + vcdp->chgBit(c+14265,((1U & (vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__st_1e_2__DOT__value[9U] + >> 0x13U)))); + vcdp->chgBus(c+14273,((3U & ((vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__st_1e_2__DOT__value[9U] + << 9U) | (vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__st_1e_2__DOT__value[8U] + >> 0x17U)))),2); + vcdp->chgBus(c+14281,(((vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__st_1e_2__DOT__value[8U] + << 9U) | (vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__st_1e_2__DOT__value[7U] + >> 0x17U))),32); + vcdp->chgBus(c+14289,(((vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__st_1e_2__DOT__value[7U] + << 9U) | (vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__st_1e_2__DOT__value[6U] + >> 0x17U))),32); + __Vtemp735[0U] = ((vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__st_1e_2__DOT__value[3U] + << 9U) | (vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__st_1e_2__DOT__value[2U] + >> 0x17U)); + __Vtemp735[1U] = ((vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__st_1e_2__DOT__value[4U] + << 9U) | (vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__st_1e_2__DOT__value[3U] + >> 0x17U)); + __Vtemp735[2U] = ((vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__st_1e_2__DOT__value[5U] + << 9U) | (vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__st_1e_2__DOT__value[4U] + >> 0x17U)); + __Vtemp735[3U] = ((vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__st_1e_2__DOT__value[6U] + << 9U) | (vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__st_1e_2__DOT__value[5U] + >> 0x17U)); + vcdp->chgArray(c+14297,(__Vtemp735),128); + vcdp->chgBit(c+14329,((1U & (vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__st_1e_2__DOT__value[2U] + >> 2U)))); + vcdp->chgBit(c+14337,((1U & (vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__st_1e_2__DOT__value[2U] + >> 1U)))); + vcdp->chgBus(c+14345,((0xffffU & ((vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__st_1e_2__DOT__value[2U] + << 0xfU) + | (vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__st_1e_2__DOT__value[1U] + >> 0x11U)))),16); + vcdp->chgQuad(c+14353,((VL_ULL(0x1ffffffffffff) + & (((QData)((IData)( + vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__st_1e_2__DOT__value[1U])) + << 0x20U) | (QData)((IData)( + vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__st_1e_2__DOT__value[0U]))))),49); + vcdp->chgBus(c+14369,((0xfffffU & ((vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__st_1e_2__DOT__value[3U] + << 0x1dU) + | (vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__st_1e_2__DOT__value[2U] + >> 3U)))),20); + vcdp->chgBit(c+14377,((1U & (vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__st_1e_2__DOT__value[9U] + >> 0x15U)))); + vcdp->chgBit(c+14385,((1U & (vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__st_1e_2__DOT__value[9U] + >> 0x17U)))); + vcdp->chgBit(c+14393,((1U & (vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__st_1e_2__DOT__value[9U] + >> 0x16U)))); + vcdp->chgBit(c+14401,((1U & (vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__st_1e_2__DOT__value[9U] + >> 0x18U)))); + vcdp->chgBit(c+14409,((1U & (vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__st_1e_2__DOT__value[9U] + >> 0x1aU)))); + vcdp->chgBit(c+14417,((1U & (vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__st_1e_2__DOT__value[9U] + >> 0x1bU)))); + vcdp->chgBit(c+14425,((1U & (vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__st_1e_2__DOT__value[9U] + >> 0x19U)))); + vcdp->chgBit(c+14433,(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__cwb_queue__DOT__genblk3__DOT__genblk2__DOT__empty_r)); + vcdp->chgBit(c+14441,(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__cwb_queue__DOT__genblk3__DOT__genblk2__DOT__full_r)); + vcdp->chgBit(c+14449,(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__genblk2__DOT__empty_r)); + vcdp->chgBit(c+14457,(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__genblk2__DOT__full_r)); + vcdp->chgBus(c+14465,(((0x3ffffc0U & (vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__st_1e_2__DOT__value[2U] + << 3U)) + | (0x3fU & ((vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__st_1e_2__DOT__value[9U] + << 7U) + | (vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__st_1e_2__DOT__value[8U] + >> 0x19U))))),26); + vcdp->chgBus(c+14473,((0xfffffffU & ((vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__st_1e_2__DOT__value[1U] + << 0x19U) + | (vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__st_1e_2__DOT__value[0U] + >> 7U)))),28); + vcdp->chgBit(c+14481,(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__dwbq_dual_valid_sel)); + vcdp->chgBus(c+14489,(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__snp_req_queue__DOT__size_r),5); + vcdp->chgQuad(c+14497,(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__snp_req_queue__DOT__genblk3__DOT__data[0]),55); + vcdp->chgQuad(c+14499,(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__snp_req_queue__DOT__genblk3__DOT__data[1]),55); + vcdp->chgQuad(c+14501,(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__snp_req_queue__DOT__genblk3__DOT__data[2]),55); + vcdp->chgQuad(c+14503,(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__snp_req_queue__DOT__genblk3__DOT__data[3]),55); + vcdp->chgQuad(c+14505,(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__snp_req_queue__DOT__genblk3__DOT__data[4]),55); + vcdp->chgQuad(c+14507,(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__snp_req_queue__DOT__genblk3__DOT__data[5]),55); + vcdp->chgQuad(c+14509,(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__snp_req_queue__DOT__genblk3__DOT__data[6]),55); + vcdp->chgQuad(c+14511,(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__snp_req_queue__DOT__genblk3__DOT__data[7]),55); + vcdp->chgQuad(c+14513,(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__snp_req_queue__DOT__genblk3__DOT__data[8]),55); + vcdp->chgQuad(c+14515,(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__snp_req_queue__DOT__genblk3__DOT__data[9]),55); + vcdp->chgQuad(c+14517,(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__snp_req_queue__DOT__genblk3__DOT__data[10]),55); + vcdp->chgQuad(c+14519,(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__snp_req_queue__DOT__genblk3__DOT__data[11]),55); + vcdp->chgQuad(c+14521,(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__snp_req_queue__DOT__genblk3__DOT__data[12]),55); + vcdp->chgQuad(c+14523,(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__snp_req_queue__DOT__genblk3__DOT__data[13]),55); + vcdp->chgQuad(c+14525,(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__snp_req_queue__DOT__genblk3__DOT__data[14]),55); + vcdp->chgQuad(c+14527,(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__snp_req_queue__DOT__genblk3__DOT__data[15]),55); + vcdp->chgQuad(c+14753,(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__snp_req_queue__DOT__genblk3__DOT__genblk2__DOT__head_r),55); + vcdp->chgQuad(c+14769,(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__snp_req_queue__DOT__genblk3__DOT__genblk2__DOT__curr_r),55); + vcdp->chgBus(c+14785,(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__snp_req_queue__DOT__genblk3__DOT__genblk2__DOT__wr_ptr_r),4); + vcdp->chgBus(c+14793,(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__snp_req_queue__DOT__genblk3__DOT__genblk2__DOT__rd_ptr_r),4); + vcdp->chgBus(c+14801,(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__snp_req_queue__DOT__genblk3__DOT__genblk2__DOT__rd_ptr_next_r),4); + vcdp->chgBit(c+14809,(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__snp_req_queue__DOT__genblk3__DOT__genblk2__DOT__bypass_r)); + vcdp->chgBus(c+14817,(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__dfp_queue__DOT__size_r),5); + vcdp->chgArray(c+14825,(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__dfp_queue__DOT__genblk3__DOT__data[0]),154); + vcdp->chgArray(c+14830,(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__dfp_queue__DOT__genblk3__DOT__data[1]),154); + vcdp->chgArray(c+14835,(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__dfp_queue__DOT__genblk3__DOT__data[2]),154); + vcdp->chgArray(c+14840,(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__dfp_queue__DOT__genblk3__DOT__data[3]),154); + vcdp->chgArray(c+14845,(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__dfp_queue__DOT__genblk3__DOT__data[4]),154); + vcdp->chgArray(c+14850,(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__dfp_queue__DOT__genblk3__DOT__data[5]),154); + vcdp->chgArray(c+14855,(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__dfp_queue__DOT__genblk3__DOT__data[6]),154); + vcdp->chgArray(c+14860,(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__dfp_queue__DOT__genblk3__DOT__data[7]),154); + vcdp->chgArray(c+14865,(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__dfp_queue__DOT__genblk3__DOT__data[8]),154); + vcdp->chgArray(c+14870,(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__dfp_queue__DOT__genblk3__DOT__data[9]),154); + vcdp->chgArray(c+14875,(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__dfp_queue__DOT__genblk3__DOT__data[10]),154); + vcdp->chgArray(c+14880,(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__dfp_queue__DOT__genblk3__DOT__data[11]),154); + vcdp->chgArray(c+14885,(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__dfp_queue__DOT__genblk3__DOT__data[12]),154); + vcdp->chgArray(c+14890,(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__dfp_queue__DOT__genblk3__DOT__data[13]),154); + vcdp->chgArray(c+14895,(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__dfp_queue__DOT__genblk3__DOT__data[14]),154); + vcdp->chgArray(c+14900,(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__dfp_queue__DOT__genblk3__DOT__data[15]),154); + vcdp->chgArray(c+15465,(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__dfp_queue__DOT__genblk3__DOT__genblk2__DOT__head_r),154); + vcdp->chgArray(c+15505,(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__dfp_queue__DOT__genblk3__DOT__genblk2__DOT__curr_r),154); + vcdp->chgBus(c+15545,(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__dfp_queue__DOT__genblk3__DOT__genblk2__DOT__wr_ptr_r),4); + vcdp->chgBus(c+15553,(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__dfp_queue__DOT__genblk3__DOT__genblk2__DOT__rd_ptr_r),4); + vcdp->chgBus(c+15561,(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__dfp_queue__DOT__genblk3__DOT__genblk2__DOT__rd_ptr_next_r),4); + vcdp->chgBit(c+15569,(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__dfp_queue__DOT__genblk3__DOT__genblk2__DOT__bypass_r)); + vcdp->chgBus(c+15577,(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__core_req_arb__DOT__use_per_valids),4); + vcdp->chgBus(c+15585,(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__core_req_arb__DOT__use_per_rw),4); + vcdp->chgBus(c+15593,(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__core_req_arb__DOT__use_per_byteen),16); + vcdp->chgArray(c+15601,(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__core_req_arb__DOT__use_per_addr),120); + vcdp->chgArray(c+15633,(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__core_req_arb__DOT__use_per_writedata),128); + vcdp->chgBit(c+15665,(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__empty_r)); + vcdp->chgBit(c+15673,((1U & (~ (IData)((0U + != (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__core_req_arb__DOT__use_per_valids))))))); + vcdp->chgBus(c+15681,(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__size_r),3); + vcdp->chgArray(c+15689,(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__data[0]),314); + vcdp->chgArray(c+15699,(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__data[1]),314); + vcdp->chgArray(c+15709,(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__data[2]),314); + vcdp->chgArray(c+15719,(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__data[3]),314); + vcdp->chgArray(c+16009,(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__head_r),314); + vcdp->chgArray(c+16089,(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__curr_r),314); + vcdp->chgBus(c+16169,(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__wr_ptr_r),2); + vcdp->chgBus(c+16177,(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__rd_ptr_r),2); + vcdp->chgBus(c+16185,(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__rd_ptr_next_r),2); + vcdp->chgBit(c+16193,(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__bypass_r)); + vcdp->chgArray(c+16201,(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__s0_1_c0__DOT__value),243); + vcdp->chgQuad(c+16265,(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__dirty),64); + vcdp->chgQuad(c+16281,(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__valid),64); + vcdp->chgBus(c+16297,(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__i),32); + vcdp->chgBus(c+16305,(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__j),32); + vcdp->chgArray(c+16313,(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__tag_data_access__DOT__s0_1_c0__DOT__value),166); + vcdp->chgArray(c+16361,(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__st_1e_2__DOT__value),316); + vcdp->chgArray(c+16441,(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__cache_miss_resrv__DOT__metadata_table[0]),85); + vcdp->chgArray(c+16444,(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__cache_miss_resrv__DOT__metadata_table[1]),85); + vcdp->chgArray(c+16447,(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__cache_miss_resrv__DOT__metadata_table[2]),85); + vcdp->chgArray(c+16450,(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__cache_miss_resrv__DOT__metadata_table[3]),85); + vcdp->chgArray(c+16453,(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__cache_miss_resrv__DOT__metadata_table[4]),85); + vcdp->chgArray(c+16456,(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__cache_miss_resrv__DOT__metadata_table[5]),85); + vcdp->chgArray(c+16459,(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__cache_miss_resrv__DOT__metadata_table[6]),85); + vcdp->chgArray(c+16462,(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__cache_miss_resrv__DOT__metadata_table[7]),85); + vcdp->chgArray(c+16465,(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__cache_miss_resrv__DOT__metadata_table[8]),85); + vcdp->chgArray(c+16468,(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__cache_miss_resrv__DOT__metadata_table[9]),85); + vcdp->chgArray(c+16471,(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__cache_miss_resrv__DOT__metadata_table[10]),85); + vcdp->chgArray(c+16474,(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__cache_miss_resrv__DOT__metadata_table[11]),85); + vcdp->chgArray(c+16477,(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__cache_miss_resrv__DOT__metadata_table[12]),85); + vcdp->chgArray(c+16480,(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__cache_miss_resrv__DOT__metadata_table[13]),85); + vcdp->chgArray(c+16483,(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__cache_miss_resrv__DOT__metadata_table[14]),85); + vcdp->chgArray(c+16486,(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__cache_miss_resrv__DOT__metadata_table[15]),85); + vcdp->chgArray(c+16825,(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__cache_miss_resrv__DOT__addr_table),416); + vcdp->chgBus(c+16929,(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__cache_miss_resrv__DOT__valid_table),16); + vcdp->chgBus(c+16937,(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__cache_miss_resrv__DOT__ready_table),16); + vcdp->chgBus(c+16945,(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr),4); + vcdp->chgBus(c+16953,(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__cache_miss_resrv__DOT__head_ptr),4); + vcdp->chgBus(c+16961,(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__cache_miss_resrv__DOT__tail_ptr),4); + vcdp->chgBus(c+16969,(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__cache_miss_resrv__DOT__size),5); + vcdp->chgBit(c+16977,((0x10U != (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__cache_miss_resrv__DOT__size)))); + vcdp->chgBus(c+16985,(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__cwb_queue__DOT__size_r),3); + vcdp->chgArray(c+16993,(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__cwb_queue__DOT__genblk3__DOT__data[0]),76); + vcdp->chgArray(c+16996,(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__cwb_queue__DOT__genblk3__DOT__data[1]),76); + vcdp->chgArray(c+16999,(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__cwb_queue__DOT__genblk3__DOT__data[2]),76); + vcdp->chgArray(c+17002,(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__cwb_queue__DOT__genblk3__DOT__data[3]),76); + vcdp->chgArray(c+17089,(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__cwb_queue__DOT__genblk3__DOT__genblk2__DOT__head_r),76); + vcdp->chgArray(c+17113,(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__cwb_queue__DOT__genblk3__DOT__genblk2__DOT__curr_r),76); + vcdp->chgBus(c+17137,(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__cwb_queue__DOT__genblk3__DOT__genblk2__DOT__wr_ptr_r),2); + vcdp->chgBus(c+17145,(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__cwb_queue__DOT__genblk3__DOT__genblk2__DOT__rd_ptr_r),2); + vcdp->chgBus(c+17153,(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__cwb_queue__DOT__genblk3__DOT__genblk2__DOT__rd_ptr_next_r),2); + vcdp->chgBit(c+17161,(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__cwb_queue__DOT__genblk3__DOT__genblk2__DOT__bypass_r)); + vcdp->chgBus(c+17169,(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__dwb_queue__DOT__size_r),3); + vcdp->chgArray(c+17177,(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__data[0]),200); + vcdp->chgArray(c+17184,(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__data[1]),200); + vcdp->chgArray(c+17191,(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__data[2]),200); + vcdp->chgArray(c+17198,(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__data[3]),200); + vcdp->chgArray(c+17401,(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__genblk2__DOT__head_r),200); + vcdp->chgArray(c+17457,(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__genblk2__DOT__curr_r),200); + vcdp->chgBus(c+17513,(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__genblk2__DOT__wr_ptr_r),2); + vcdp->chgBus(c+17521,(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__genblk2__DOT__rd_ptr_r),2); + vcdp->chgBus(c+17529,(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__genblk2__DOT__rd_ptr_next_r),2); + vcdp->chgBit(c+17537,(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__genblk2__DOT__bypass_r)); + vcdp->chgBit(c+17545,(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__snp_req_queue__DOT__genblk3__DOT__genblk2__DOT__empty_r)); + vcdp->chgBit(c+17553,(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__snp_req_queue__DOT__genblk3__DOT__genblk2__DOT__full_r)); + vcdp->chgBit(c+17561,(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__dfp_queue__DOT__genblk3__DOT__genblk2__DOT__empty_r)); + vcdp->chgBit(c+17569,(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__dfp_queue__DOT__genblk3__DOT__genblk2__DOT__full_r)); + vcdp->chgBit(c+17577,(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__full_r)); + vcdp->chgQuad(c+17585,(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__core_req_arb__DOT__use_per_tag),42); + vcdp->chgBit(c+17601,((0x10U == (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__cache_miss_resrv__DOT__size)))); + vcdp->chgBit(c+17609,((0xbU < (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__cache_miss_resrv__DOT__size)))); + vcdp->chgBus(c+17617,((3U & ((vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__cache_miss_resrv__DOT__metadata_table + [vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr][2U] + << 0xdU) | (vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__cache_miss_resrv__DOT__metadata_table + [vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr][1U] + >> 0x13U)))),2); + vcdp->chgBus(c+17625,(((0x19fU >= (0x1ffU & + ((IData)(0x1aU) + * (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr)))) + ? (0x3ffffffU & (((0U + == + (0x1fU + & ((IData)(0x1aU) + * (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr)))) + ? 0U + : + (vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__cache_miss_resrv__DOT__addr_table[ + ((IData)(1U) + + + (0xfU + & (((IData)(0x1aU) + * (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr)) + >> 5U)))] + << + ((IData)(0x20U) + - + (0x1fU + & ((IData)(0x1aU) + * (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr)))))) + | (vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__cache_miss_resrv__DOT__addr_table[ + (0xfU + & (((IData)(0x1aU) + * (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr)) + >> 5U))] + >> + (0x1fU + & ((IData)(0x1aU) + * (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr)))))) + : 0U)),26); + vcdp->chgBus(c+17633,((3U & ((vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__cache_miss_resrv__DOT__metadata_table + [vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr][1U] + << 0x1eU) | ( + vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__cache_miss_resrv__DOT__metadata_table + [vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr][0U] + >> 2U)))),2); + vcdp->chgBus(c+17641,(((vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__cache_miss_resrv__DOT__metadata_table + [vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr][2U] + << 0xbU) | (vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__cache_miss_resrv__DOT__metadata_table + [vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr][1U] + >> 0x15U))),32); + vcdp->chgQuad(c+17649,((VL_ULL(0x3ffffffffff) + & (((QData)((IData)( + vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__cache_miss_resrv__DOT__metadata_table + [vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr][2U])) + << 0x37U) | (((QData)((IData)( + vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__cache_miss_resrv__DOT__metadata_table + [vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr][1U])) + << 0x17U) + | ((QData)((IData)( + vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__cache_miss_resrv__DOT__metadata_table + [vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr][0U])) + >> 9U))))),42); + vcdp->chgBus(c+17665,((0xfU & ((vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__cache_miss_resrv__DOT__metadata_table + [vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr][1U] + << 0x1cU) | + (vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__cache_miss_resrv__DOT__metadata_table + [vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr][0U] + >> 4U)))),4); + vcdp->chgBit(c+17673,((1U & (vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__cache_miss_resrv__DOT__metadata_table + [vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr][0U] + >> 1U)))); + vcdp->chgBit(c+17681,((1U & vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__cache_miss_resrv__DOT__metadata_table + [vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr][0U]))); + vcdp->chgBus(c+17689,((3U & vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__st_1e_2__DOT__value[0U])),2); + vcdp->chgQuad(c+17697,((VL_ULL(0x3ffffffffff) + & (((QData)((IData)( + vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__st_1e_2__DOT__value[2U])) + << 0x39U) | (((QData)((IData)( + vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__st_1e_2__DOT__value[1U])) + << 0x19U) + | ((QData)((IData)( + vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__st_1e_2__DOT__value[0U])) + >> 7U))))),42); + vcdp->chgBit(c+17713,((1U & (vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__st_1e_2__DOT__value[0U] + >> 6U)))); + vcdp->chgBus(c+17721,((0xfU & ((vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__st_1e_2__DOT__value[1U] + << 0x1eU) | + (vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__st_1e_2__DOT__value[0U] + >> 2U)))),4); + vcdp->chgBit(c+17729,((1U & (vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__st_1e_2__DOT__value[9U] + >> 0x14U)))); + vcdp->chgBit(c+17737,((1U & (vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__st_1e_2__DOT__value[9U] + >> 0x13U)))); + vcdp->chgBus(c+17745,((3U & ((vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__st_1e_2__DOT__value[9U] + << 9U) | (vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__st_1e_2__DOT__value[8U] + >> 0x17U)))),2); + vcdp->chgBus(c+17753,(((vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__st_1e_2__DOT__value[8U] + << 9U) | (vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__st_1e_2__DOT__value[7U] + >> 0x17U))),32); + vcdp->chgBus(c+17761,(((vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__st_1e_2__DOT__value[7U] + << 9U) | (vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__st_1e_2__DOT__value[6U] + >> 0x17U))),32); + __Vtemp743[0U] = ((vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__st_1e_2__DOT__value[3U] + << 9U) | (vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__st_1e_2__DOT__value[2U] + >> 0x17U)); + __Vtemp743[1U] = ((vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__st_1e_2__DOT__value[4U] + << 9U) | (vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__st_1e_2__DOT__value[3U] + >> 0x17U)); + __Vtemp743[2U] = ((vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__st_1e_2__DOT__value[5U] + << 9U) | (vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__st_1e_2__DOT__value[4U] + >> 0x17U)); + __Vtemp743[3U] = ((vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__st_1e_2__DOT__value[6U] + << 9U) | (vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__st_1e_2__DOT__value[5U] + >> 0x17U)); + vcdp->chgArray(c+17769,(__Vtemp743),128); + vcdp->chgBit(c+17801,((1U & (vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__st_1e_2__DOT__value[2U] + >> 2U)))); + vcdp->chgBit(c+17809,((1U & (vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__st_1e_2__DOT__value[2U] + >> 1U)))); + vcdp->chgBus(c+17817,((0xffffU & ((vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__st_1e_2__DOT__value[2U] + << 0xfU) + | (vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__st_1e_2__DOT__value[1U] + >> 0x11U)))),16); + vcdp->chgQuad(c+17825,((VL_ULL(0x1ffffffffffff) + & (((QData)((IData)( + vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__st_1e_2__DOT__value[1U])) + << 0x20U) | (QData)((IData)( + vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__st_1e_2__DOT__value[0U]))))),49); + vcdp->chgBus(c+17841,((0xfffffU & ((vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__st_1e_2__DOT__value[3U] + << 0x1dU) + | (vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__st_1e_2__DOT__value[2U] + >> 3U)))),20); + vcdp->chgBit(c+17849,((1U & (vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__st_1e_2__DOT__value[9U] + >> 0x15U)))); + vcdp->chgBit(c+17857,((1U & (vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__st_1e_2__DOT__value[9U] + >> 0x17U)))); + vcdp->chgBit(c+17865,((1U & (vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__st_1e_2__DOT__value[9U] + >> 0x16U)))); + vcdp->chgBit(c+17873,((1U & (vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__st_1e_2__DOT__value[9U] + >> 0x18U)))); + vcdp->chgBit(c+17881,((1U & (vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__st_1e_2__DOT__value[9U] + >> 0x1aU)))); + vcdp->chgBit(c+17889,((1U & (vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__st_1e_2__DOT__value[9U] + >> 0x1bU)))); + vcdp->chgBit(c+17897,((1U & (vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__st_1e_2__DOT__value[9U] + >> 0x19U)))); + vcdp->chgBit(c+17905,(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__cwb_queue__DOT__genblk3__DOT__genblk2__DOT__empty_r)); + vcdp->chgBit(c+17913,(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__cwb_queue__DOT__genblk3__DOT__genblk2__DOT__full_r)); + vcdp->chgBit(c+17921,(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__genblk2__DOT__empty_r)); + vcdp->chgBit(c+17929,(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__genblk2__DOT__full_r)); + vcdp->chgBus(c+17937,(((0x3ffffc0U & (vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__st_1e_2__DOT__value[2U] + << 3U)) + | (0x3fU & ((vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__st_1e_2__DOT__value[9U] + << 7U) + | (vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__st_1e_2__DOT__value[8U] + >> 0x19U))))),26); + vcdp->chgBus(c+17945,((0xfffffffU & ((vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__st_1e_2__DOT__value[1U] + << 0x19U) + | (vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__st_1e_2__DOT__value[0U] + >> 7U)))),28); + vcdp->chgBit(c+17953,(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__dwbq_dual_valid_sel)); + vcdp->chgBus(c+17961,(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__snp_req_queue__DOT__size_r),5); + vcdp->chgQuad(c+17969,(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__snp_req_queue__DOT__genblk3__DOT__data[0]),55); + vcdp->chgQuad(c+17971,(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__snp_req_queue__DOT__genblk3__DOT__data[1]),55); + vcdp->chgQuad(c+17973,(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__snp_req_queue__DOT__genblk3__DOT__data[2]),55); + vcdp->chgQuad(c+17975,(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__snp_req_queue__DOT__genblk3__DOT__data[3]),55); + vcdp->chgQuad(c+17977,(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__snp_req_queue__DOT__genblk3__DOT__data[4]),55); + vcdp->chgQuad(c+17979,(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__snp_req_queue__DOT__genblk3__DOT__data[5]),55); + vcdp->chgQuad(c+17981,(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__snp_req_queue__DOT__genblk3__DOT__data[6]),55); + vcdp->chgQuad(c+17983,(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__snp_req_queue__DOT__genblk3__DOT__data[7]),55); + vcdp->chgQuad(c+17985,(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__snp_req_queue__DOT__genblk3__DOT__data[8]),55); + vcdp->chgQuad(c+17987,(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__snp_req_queue__DOT__genblk3__DOT__data[9]),55); + vcdp->chgQuad(c+17989,(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__snp_req_queue__DOT__genblk3__DOT__data[10]),55); + vcdp->chgQuad(c+17991,(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__snp_req_queue__DOT__genblk3__DOT__data[11]),55); + vcdp->chgQuad(c+17993,(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__snp_req_queue__DOT__genblk3__DOT__data[12]),55); + vcdp->chgQuad(c+17995,(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__snp_req_queue__DOT__genblk3__DOT__data[13]),55); + vcdp->chgQuad(c+17997,(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__snp_req_queue__DOT__genblk3__DOT__data[14]),55); + vcdp->chgQuad(c+17999,(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__snp_req_queue__DOT__genblk3__DOT__data[15]),55); + vcdp->chgQuad(c+18225,(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__snp_req_queue__DOT__genblk3__DOT__genblk2__DOT__head_r),55); + vcdp->chgQuad(c+18241,(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__snp_req_queue__DOT__genblk3__DOT__genblk2__DOT__curr_r),55); + vcdp->chgBus(c+18257,(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__snp_req_queue__DOT__genblk3__DOT__genblk2__DOT__wr_ptr_r),4); + vcdp->chgBus(c+18265,(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__snp_req_queue__DOT__genblk3__DOT__genblk2__DOT__rd_ptr_r),4); + vcdp->chgBus(c+18273,(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__snp_req_queue__DOT__genblk3__DOT__genblk2__DOT__rd_ptr_next_r),4); + vcdp->chgBit(c+18281,(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__snp_req_queue__DOT__genblk3__DOT__genblk2__DOT__bypass_r)); + vcdp->chgBus(c+18289,(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__dfp_queue__DOT__size_r),5); + vcdp->chgArray(c+18297,(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__dfp_queue__DOT__genblk3__DOT__data[0]),154); + vcdp->chgArray(c+18302,(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__dfp_queue__DOT__genblk3__DOT__data[1]),154); + vcdp->chgArray(c+18307,(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__dfp_queue__DOT__genblk3__DOT__data[2]),154); + vcdp->chgArray(c+18312,(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__dfp_queue__DOT__genblk3__DOT__data[3]),154); + vcdp->chgArray(c+18317,(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__dfp_queue__DOT__genblk3__DOT__data[4]),154); + vcdp->chgArray(c+18322,(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__dfp_queue__DOT__genblk3__DOT__data[5]),154); + vcdp->chgArray(c+18327,(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__dfp_queue__DOT__genblk3__DOT__data[6]),154); + vcdp->chgArray(c+18332,(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__dfp_queue__DOT__genblk3__DOT__data[7]),154); + vcdp->chgArray(c+18337,(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__dfp_queue__DOT__genblk3__DOT__data[8]),154); + vcdp->chgArray(c+18342,(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__dfp_queue__DOT__genblk3__DOT__data[9]),154); + vcdp->chgArray(c+18347,(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__dfp_queue__DOT__genblk3__DOT__data[10]),154); + vcdp->chgArray(c+18352,(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__dfp_queue__DOT__genblk3__DOT__data[11]),154); + vcdp->chgArray(c+18357,(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__dfp_queue__DOT__genblk3__DOT__data[12]),154); + vcdp->chgArray(c+18362,(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__dfp_queue__DOT__genblk3__DOT__data[13]),154); + vcdp->chgArray(c+18367,(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__dfp_queue__DOT__genblk3__DOT__data[14]),154); + vcdp->chgArray(c+18372,(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__dfp_queue__DOT__genblk3__DOT__data[15]),154); + vcdp->chgArray(c+18937,(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__dfp_queue__DOT__genblk3__DOT__genblk2__DOT__head_r),154); + vcdp->chgArray(c+18977,(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__dfp_queue__DOT__genblk3__DOT__genblk2__DOT__curr_r),154); + vcdp->chgBus(c+19017,(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__dfp_queue__DOT__genblk3__DOT__genblk2__DOT__wr_ptr_r),4); + vcdp->chgBus(c+19025,(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__dfp_queue__DOT__genblk3__DOT__genblk2__DOT__rd_ptr_r),4); + vcdp->chgBus(c+19033,(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__dfp_queue__DOT__genblk3__DOT__genblk2__DOT__rd_ptr_next_r),4); + vcdp->chgBit(c+19041,(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__dfp_queue__DOT__genblk3__DOT__genblk2__DOT__bypass_r)); + vcdp->chgBus(c+19049,(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__core_req_arb__DOT__use_per_valids),4); + vcdp->chgBus(c+19057,(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__core_req_arb__DOT__use_per_rw),4); + vcdp->chgBus(c+19065,(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__core_req_arb__DOT__use_per_byteen),16); + vcdp->chgArray(c+19073,(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__core_req_arb__DOT__use_per_addr),120); + vcdp->chgArray(c+19105,(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__core_req_arb__DOT__use_per_writedata),128); + vcdp->chgBit(c+19137,(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__empty_r)); + vcdp->chgBit(c+19145,((1U & (~ (IData)((0U + != (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__core_req_arb__DOT__use_per_valids))))))); + vcdp->chgBus(c+19153,(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__size_r),3); + vcdp->chgArray(c+19161,(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__data[0]),314); + vcdp->chgArray(c+19171,(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__data[1]),314); + vcdp->chgArray(c+19181,(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__data[2]),314); + vcdp->chgArray(c+19191,(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__data[3]),314); + vcdp->chgArray(c+19481,(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__head_r),314); + vcdp->chgArray(c+19561,(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__curr_r),314); + vcdp->chgBus(c+19641,(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__wr_ptr_r),2); + vcdp->chgBus(c+19649,(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__rd_ptr_r),2); + vcdp->chgBus(c+19657,(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__rd_ptr_next_r),2); + vcdp->chgBit(c+19665,(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__bypass_r)); + vcdp->chgArray(c+19673,(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__s0_1_c0__DOT__value),243); + vcdp->chgQuad(c+19737,(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__dirty),64); + vcdp->chgQuad(c+19753,(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__valid),64); + vcdp->chgBus(c+19769,(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__i),32); + vcdp->chgBus(c+19777,(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__j),32); + vcdp->chgArray(c+19785,(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__tag_data_access__DOT__s0_1_c0__DOT__value),166); + vcdp->chgArray(c+19833,(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__st_1e_2__DOT__value),316); + vcdp->chgArray(c+19913,(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__cache_miss_resrv__DOT__metadata_table[0]),85); + vcdp->chgArray(c+19916,(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__cache_miss_resrv__DOT__metadata_table[1]),85); + vcdp->chgArray(c+19919,(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__cache_miss_resrv__DOT__metadata_table[2]),85); + vcdp->chgArray(c+19922,(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__cache_miss_resrv__DOT__metadata_table[3]),85); + vcdp->chgArray(c+19925,(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__cache_miss_resrv__DOT__metadata_table[4]),85); + vcdp->chgArray(c+19928,(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__cache_miss_resrv__DOT__metadata_table[5]),85); + vcdp->chgArray(c+19931,(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__cache_miss_resrv__DOT__metadata_table[6]),85); + vcdp->chgArray(c+19934,(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__cache_miss_resrv__DOT__metadata_table[7]),85); + vcdp->chgArray(c+19937,(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__cache_miss_resrv__DOT__metadata_table[8]),85); + vcdp->chgArray(c+19940,(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__cache_miss_resrv__DOT__metadata_table[9]),85); + vcdp->chgArray(c+19943,(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__cache_miss_resrv__DOT__metadata_table[10]),85); + vcdp->chgArray(c+19946,(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__cache_miss_resrv__DOT__metadata_table[11]),85); + vcdp->chgArray(c+19949,(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__cache_miss_resrv__DOT__metadata_table[12]),85); + vcdp->chgArray(c+19952,(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__cache_miss_resrv__DOT__metadata_table[13]),85); + vcdp->chgArray(c+19955,(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__cache_miss_resrv__DOT__metadata_table[14]),85); + vcdp->chgArray(c+19958,(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__cache_miss_resrv__DOT__metadata_table[15]),85); + vcdp->chgArray(c+20297,(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__cache_miss_resrv__DOT__addr_table),416); + vcdp->chgBus(c+20401,(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__cache_miss_resrv__DOT__valid_table),16); + vcdp->chgBus(c+20409,(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__cache_miss_resrv__DOT__ready_table),16); + vcdp->chgBus(c+20417,(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr),4); + vcdp->chgBus(c+20425,(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__cache_miss_resrv__DOT__head_ptr),4); + vcdp->chgBus(c+20433,(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__cache_miss_resrv__DOT__tail_ptr),4); + vcdp->chgBus(c+20441,(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__cache_miss_resrv__DOT__size),5); + vcdp->chgBit(c+20449,((0x10U != (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__cache_miss_resrv__DOT__size)))); + vcdp->chgBus(c+20457,(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__cwb_queue__DOT__size_r),3); + vcdp->chgArray(c+20465,(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__cwb_queue__DOT__genblk3__DOT__data[0]),76); + vcdp->chgArray(c+20468,(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__cwb_queue__DOT__genblk3__DOT__data[1]),76); + vcdp->chgArray(c+20471,(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__cwb_queue__DOT__genblk3__DOT__data[2]),76); + vcdp->chgArray(c+20474,(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__cwb_queue__DOT__genblk3__DOT__data[3]),76); + vcdp->chgArray(c+20561,(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__cwb_queue__DOT__genblk3__DOT__genblk2__DOT__head_r),76); + vcdp->chgArray(c+20585,(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__cwb_queue__DOT__genblk3__DOT__genblk2__DOT__curr_r),76); + vcdp->chgBus(c+20609,(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__cwb_queue__DOT__genblk3__DOT__genblk2__DOT__wr_ptr_r),2); + vcdp->chgBus(c+20617,(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__cwb_queue__DOT__genblk3__DOT__genblk2__DOT__rd_ptr_r),2); + vcdp->chgBus(c+20625,(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__cwb_queue__DOT__genblk3__DOT__genblk2__DOT__rd_ptr_next_r),2); + vcdp->chgBit(c+20633,(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__cwb_queue__DOT__genblk3__DOT__genblk2__DOT__bypass_r)); + vcdp->chgBus(c+20641,(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__dwb_queue__DOT__size_r),3); + vcdp->chgArray(c+20649,(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__data[0]),200); + vcdp->chgArray(c+20656,(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__data[1]),200); + vcdp->chgArray(c+20663,(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__data[2]),200); + vcdp->chgArray(c+20670,(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__data[3]),200); + vcdp->chgArray(c+20873,(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__genblk2__DOT__head_r),200); + vcdp->chgArray(c+20929,(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__genblk2__DOT__curr_r),200); + vcdp->chgBus(c+20985,(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__genblk2__DOT__wr_ptr_r),2); + vcdp->chgBus(c+20993,(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__genblk2__DOT__rd_ptr_r),2); + vcdp->chgBus(c+21001,(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__genblk2__DOT__rd_ptr_next_r),2); + vcdp->chgBit(c+21009,(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__genblk2__DOT__bypass_r)); + vcdp->chgBit(c+21017,(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__snp_req_queue__DOT__genblk3__DOT__genblk2__DOT__empty_r)); + vcdp->chgBit(c+21025,(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__snp_req_queue__DOT__genblk3__DOT__genblk2__DOT__full_r)); + vcdp->chgBit(c+21033,(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__dfp_queue__DOT__genblk3__DOT__genblk2__DOT__empty_r)); + vcdp->chgBit(c+21041,(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__dfp_queue__DOT__genblk3__DOT__genblk2__DOT__full_r)); + vcdp->chgBit(c+21049,(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__full_r)); + vcdp->chgQuad(c+21057,(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__core_req_arb__DOT__use_per_tag),42); + vcdp->chgBit(c+21073,((0x10U == (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cache_miss_resrv__DOT__size)))); + vcdp->chgBit(c+21081,((0xbU < (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cache_miss_resrv__DOT__size)))); + vcdp->chgBus(c+21089,((3U & ((vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cache_miss_resrv__DOT__metadata_table + [vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr][2U] + << 0xdU) | (vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cache_miss_resrv__DOT__metadata_table + [vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr][1U] + >> 0x13U)))),2); + vcdp->chgBus(c+21097,(((0x19fU >= (0x1ffU & + ((IData)(0x1aU) + * (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr)))) + ? (0x3ffffffU & (((0U + == + (0x1fU + & ((IData)(0x1aU) + * (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr)))) + ? 0U + : + (vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cache_miss_resrv__DOT__addr_table[ + ((IData)(1U) + + + (0xfU + & (((IData)(0x1aU) + * (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr)) + >> 5U)))] + << + ((IData)(0x20U) + - + (0x1fU + & ((IData)(0x1aU) + * (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr)))))) + | (vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cache_miss_resrv__DOT__addr_table[ + (0xfU + & (((IData)(0x1aU) + * (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr)) + >> 5U))] + >> + (0x1fU + & ((IData)(0x1aU) + * (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr)))))) + : 0U)),26); + vcdp->chgBus(c+21105,((3U & ((vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cache_miss_resrv__DOT__metadata_table + [vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr][1U] + << 0x1eU) | ( + vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cache_miss_resrv__DOT__metadata_table + [vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr][0U] + >> 2U)))),2); + vcdp->chgBus(c+21113,(((vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cache_miss_resrv__DOT__metadata_table + [vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr][2U] + << 0xbU) | (vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cache_miss_resrv__DOT__metadata_table + [vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr][1U] + >> 0x15U))),32); + vcdp->chgQuad(c+21121,((VL_ULL(0x3ffffffffff) + & (((QData)((IData)( + vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cache_miss_resrv__DOT__metadata_table + [vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr][2U])) + << 0x37U) | (((QData)((IData)( + vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cache_miss_resrv__DOT__metadata_table + [vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr][1U])) + << 0x17U) + | ((QData)((IData)( + vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cache_miss_resrv__DOT__metadata_table + [vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr][0U])) + >> 9U))))),42); + vcdp->chgBus(c+21137,((0xfU & ((vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cache_miss_resrv__DOT__metadata_table + [vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr][1U] + << 0x1cU) | + (vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cache_miss_resrv__DOT__metadata_table + [vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr][0U] + >> 4U)))),4); + vcdp->chgBit(c+21145,((1U & (vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cache_miss_resrv__DOT__metadata_table + [vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr][0U] + >> 1U)))); + vcdp->chgBit(c+21153,((1U & vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cache_miss_resrv__DOT__metadata_table + [vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr][0U]))); + vcdp->chgBus(c+21161,((3U & vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__st_1e_2__DOT__value[0U])),2); + vcdp->chgQuad(c+21169,((VL_ULL(0x3ffffffffff) + & (((QData)((IData)( + vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__st_1e_2__DOT__value[2U])) + << 0x39U) | (((QData)((IData)( + vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__st_1e_2__DOT__value[1U])) + << 0x19U) + | ((QData)((IData)( + vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__st_1e_2__DOT__value[0U])) + >> 7U))))),42); + vcdp->chgBit(c+21185,((1U & (vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__st_1e_2__DOT__value[0U] + >> 6U)))); + vcdp->chgBus(c+21193,((0xfU & ((vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__st_1e_2__DOT__value[1U] + << 0x1eU) | + (vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__st_1e_2__DOT__value[0U] + >> 2U)))),4); + vcdp->chgBit(c+21201,((1U & (vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__st_1e_2__DOT__value[9U] + >> 0x14U)))); + vcdp->chgBit(c+21209,((1U & (vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__st_1e_2__DOT__value[9U] + >> 0x13U)))); + vcdp->chgBus(c+21217,((3U & ((vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__st_1e_2__DOT__value[9U] + << 9U) | (vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__st_1e_2__DOT__value[8U] + >> 0x17U)))),2); + vcdp->chgBus(c+21225,(((vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__st_1e_2__DOT__value[8U] + << 9U) | (vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__st_1e_2__DOT__value[7U] + >> 0x17U))),32); + vcdp->chgBus(c+21233,(((vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__st_1e_2__DOT__value[7U] + << 9U) | (vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__st_1e_2__DOT__value[6U] + >> 0x17U))),32); + __Vtemp751[0U] = ((vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__st_1e_2__DOT__value[3U] + << 9U) | (vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__st_1e_2__DOT__value[2U] + >> 0x17U)); + __Vtemp751[1U] = ((vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__st_1e_2__DOT__value[4U] + << 9U) | (vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__st_1e_2__DOT__value[3U] + >> 0x17U)); + __Vtemp751[2U] = ((vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__st_1e_2__DOT__value[5U] + << 9U) | (vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__st_1e_2__DOT__value[4U] + >> 0x17U)); + __Vtemp751[3U] = ((vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__st_1e_2__DOT__value[6U] + << 9U) | (vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__st_1e_2__DOT__value[5U] + >> 0x17U)); + vcdp->chgArray(c+21241,(__Vtemp751),128); + vcdp->chgBit(c+21273,((1U & (vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__st_1e_2__DOT__value[2U] + >> 2U)))); + vcdp->chgBit(c+21281,((1U & (vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__st_1e_2__DOT__value[2U] + >> 1U)))); + vcdp->chgBus(c+21289,((0xffffU & ((vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__st_1e_2__DOT__value[2U] + << 0xfU) + | (vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__st_1e_2__DOT__value[1U] + >> 0x11U)))),16); + vcdp->chgQuad(c+21297,((VL_ULL(0x1ffffffffffff) + & (((QData)((IData)( + vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__st_1e_2__DOT__value[1U])) + << 0x20U) | (QData)((IData)( + vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__st_1e_2__DOT__value[0U]))))),49); + vcdp->chgBus(c+21313,((0xfffffU & ((vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__st_1e_2__DOT__value[3U] + << 0x1dU) + | (vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__st_1e_2__DOT__value[2U] + >> 3U)))),20); + vcdp->chgBit(c+21321,((1U & (vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__st_1e_2__DOT__value[9U] + >> 0x15U)))); + vcdp->chgBit(c+21329,((1U & (vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__st_1e_2__DOT__value[9U] + >> 0x17U)))); + vcdp->chgBit(c+21337,((1U & (vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__st_1e_2__DOT__value[9U] + >> 0x16U)))); + vcdp->chgBit(c+21345,((1U & (vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__st_1e_2__DOT__value[9U] + >> 0x18U)))); + vcdp->chgBit(c+21353,((1U & (vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__st_1e_2__DOT__value[9U] + >> 0x1aU)))); + vcdp->chgBit(c+21361,((1U & (vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__st_1e_2__DOT__value[9U] + >> 0x1bU)))); + vcdp->chgBit(c+21369,((1U & (vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__st_1e_2__DOT__value[9U] + >> 0x19U)))); + vcdp->chgBit(c+21377,(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cwb_queue__DOT__genblk3__DOT__genblk2__DOT__empty_r)); + vcdp->chgBit(c+21385,(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cwb_queue__DOT__genblk3__DOT__genblk2__DOT__full_r)); + vcdp->chgBit(c+21393,(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__genblk2__DOT__empty_r)); + vcdp->chgBit(c+21401,(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__genblk2__DOT__full_r)); + vcdp->chgBus(c+21409,(((0x3ffffc0U & (vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__st_1e_2__DOT__value[2U] + << 3U)) + | (0x3fU & ((vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__st_1e_2__DOT__value[9U] + << 7U) + | (vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__st_1e_2__DOT__value[8U] + >> 0x19U))))),26); + vcdp->chgBus(c+21417,((0xfffffffU & ((vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__st_1e_2__DOT__value[1U] + << 0x19U) + | (vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__st_1e_2__DOT__value[0U] + >> 7U)))),28); + vcdp->chgBit(c+21425,(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__dwbq_dual_valid_sel)); + vcdp->chgBus(c+21433,(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__snp_req_queue__DOT__size_r),5); + vcdp->chgQuad(c+21441,(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__snp_req_queue__DOT__genblk3__DOT__data[0]),55); + vcdp->chgQuad(c+21443,(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__snp_req_queue__DOT__genblk3__DOT__data[1]),55); + vcdp->chgQuad(c+21445,(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__snp_req_queue__DOT__genblk3__DOT__data[2]),55); + vcdp->chgQuad(c+21447,(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__snp_req_queue__DOT__genblk3__DOT__data[3]),55); + vcdp->chgQuad(c+21449,(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__snp_req_queue__DOT__genblk3__DOT__data[4]),55); + vcdp->chgQuad(c+21451,(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__snp_req_queue__DOT__genblk3__DOT__data[5]),55); + vcdp->chgQuad(c+21453,(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__snp_req_queue__DOT__genblk3__DOT__data[6]),55); + vcdp->chgQuad(c+21455,(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__snp_req_queue__DOT__genblk3__DOT__data[7]),55); + vcdp->chgQuad(c+21457,(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__snp_req_queue__DOT__genblk3__DOT__data[8]),55); + vcdp->chgQuad(c+21459,(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__snp_req_queue__DOT__genblk3__DOT__data[9]),55); + vcdp->chgQuad(c+21461,(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__snp_req_queue__DOT__genblk3__DOT__data[10]),55); + vcdp->chgQuad(c+21463,(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__snp_req_queue__DOT__genblk3__DOT__data[11]),55); + vcdp->chgQuad(c+21465,(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__snp_req_queue__DOT__genblk3__DOT__data[12]),55); + vcdp->chgQuad(c+21467,(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__snp_req_queue__DOT__genblk3__DOT__data[13]),55); + vcdp->chgQuad(c+21469,(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__snp_req_queue__DOT__genblk3__DOT__data[14]),55); + vcdp->chgQuad(c+21471,(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__snp_req_queue__DOT__genblk3__DOT__data[15]),55); + vcdp->chgQuad(c+21697,(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__snp_req_queue__DOT__genblk3__DOT__genblk2__DOT__head_r),55); + vcdp->chgQuad(c+21713,(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__snp_req_queue__DOT__genblk3__DOT__genblk2__DOT__curr_r),55); + vcdp->chgBus(c+21729,(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__snp_req_queue__DOT__genblk3__DOT__genblk2__DOT__wr_ptr_r),4); + vcdp->chgBus(c+21737,(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__snp_req_queue__DOT__genblk3__DOT__genblk2__DOT__rd_ptr_r),4); + vcdp->chgBus(c+21745,(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__snp_req_queue__DOT__genblk3__DOT__genblk2__DOT__rd_ptr_next_r),4); + vcdp->chgBit(c+21753,(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__snp_req_queue__DOT__genblk3__DOT__genblk2__DOT__bypass_r)); + vcdp->chgBus(c+21761,(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__dfp_queue__DOT__size_r),5); + vcdp->chgArray(c+21769,(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__dfp_queue__DOT__genblk3__DOT__data[0]),154); + vcdp->chgArray(c+21774,(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__dfp_queue__DOT__genblk3__DOT__data[1]),154); + vcdp->chgArray(c+21779,(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__dfp_queue__DOT__genblk3__DOT__data[2]),154); + vcdp->chgArray(c+21784,(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__dfp_queue__DOT__genblk3__DOT__data[3]),154); + vcdp->chgArray(c+21789,(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__dfp_queue__DOT__genblk3__DOT__data[4]),154); + vcdp->chgArray(c+21794,(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__dfp_queue__DOT__genblk3__DOT__data[5]),154); + vcdp->chgArray(c+21799,(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__dfp_queue__DOT__genblk3__DOT__data[6]),154); + vcdp->chgArray(c+21804,(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__dfp_queue__DOT__genblk3__DOT__data[7]),154); + vcdp->chgArray(c+21809,(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__dfp_queue__DOT__genblk3__DOT__data[8]),154); + vcdp->chgArray(c+21814,(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__dfp_queue__DOT__genblk3__DOT__data[9]),154); + vcdp->chgArray(c+21819,(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__dfp_queue__DOT__genblk3__DOT__data[10]),154); + vcdp->chgArray(c+21824,(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__dfp_queue__DOT__genblk3__DOT__data[11]),154); + vcdp->chgArray(c+21829,(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__dfp_queue__DOT__genblk3__DOT__data[12]),154); + vcdp->chgArray(c+21834,(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__dfp_queue__DOT__genblk3__DOT__data[13]),154); + vcdp->chgArray(c+21839,(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__dfp_queue__DOT__genblk3__DOT__data[14]),154); + vcdp->chgArray(c+21844,(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__dfp_queue__DOT__genblk3__DOT__data[15]),154); + vcdp->chgArray(c+22409,(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__dfp_queue__DOT__genblk3__DOT__genblk2__DOT__head_r),154); + vcdp->chgArray(c+22449,(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__dfp_queue__DOT__genblk3__DOT__genblk2__DOT__curr_r),154); + vcdp->chgBus(c+22489,(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__dfp_queue__DOT__genblk3__DOT__genblk2__DOT__wr_ptr_r),4); + vcdp->chgBus(c+22497,(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__dfp_queue__DOT__genblk3__DOT__genblk2__DOT__rd_ptr_r),4); + vcdp->chgBus(c+22505,(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__dfp_queue__DOT__genblk3__DOT__genblk2__DOT__rd_ptr_next_r),4); + vcdp->chgBit(c+22513,(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__dfp_queue__DOT__genblk3__DOT__genblk2__DOT__bypass_r)); + vcdp->chgBus(c+22521,(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__core_req_arb__DOT__use_per_valids),4); + vcdp->chgBus(c+22529,(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__core_req_arb__DOT__use_per_rw),4); + vcdp->chgBus(c+22537,(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__core_req_arb__DOT__use_per_byteen),16); + vcdp->chgArray(c+22545,(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__core_req_arb__DOT__use_per_addr),120); + vcdp->chgArray(c+22577,(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__core_req_arb__DOT__use_per_writedata),128); + vcdp->chgBit(c+22609,(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__empty_r)); + vcdp->chgBit(c+22617,((1U & (~ (IData)((0U + != (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__core_req_arb__DOT__use_per_valids))))))); + vcdp->chgBus(c+22625,(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__size_r),3); + vcdp->chgArray(c+22633,(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__data[0]),314); + vcdp->chgArray(c+22643,(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__data[1]),314); + vcdp->chgArray(c+22653,(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__data[2]),314); + vcdp->chgArray(c+22663,(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__data[3]),314); + vcdp->chgArray(c+22953,(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__head_r),314); + vcdp->chgArray(c+23033,(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__curr_r),314); + vcdp->chgBus(c+23113,(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__wr_ptr_r),2); + vcdp->chgBus(c+23121,(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__rd_ptr_r),2); + vcdp->chgBus(c+23129,(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__rd_ptr_next_r),2); + vcdp->chgBit(c+23137,(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__bypass_r)); + vcdp->chgArray(c+23145,(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__s0_1_c0__DOT__value),243); + vcdp->chgQuad(c+23209,(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__dirty),64); + vcdp->chgQuad(c+23225,(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__valid),64); + vcdp->chgBus(c+23241,(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__i),32); + vcdp->chgBus(c+23249,(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__j),32); + vcdp->chgArray(c+23257,(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__tag_data_access__DOT__s0_1_c0__DOT__value),166); + vcdp->chgArray(c+23305,(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__st_1e_2__DOT__value),316); + vcdp->chgArray(c+23385,(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cache_miss_resrv__DOT__metadata_table[0]),85); + vcdp->chgArray(c+23388,(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cache_miss_resrv__DOT__metadata_table[1]),85); + vcdp->chgArray(c+23391,(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cache_miss_resrv__DOT__metadata_table[2]),85); + vcdp->chgArray(c+23394,(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cache_miss_resrv__DOT__metadata_table[3]),85); + vcdp->chgArray(c+23397,(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cache_miss_resrv__DOT__metadata_table[4]),85); + vcdp->chgArray(c+23400,(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cache_miss_resrv__DOT__metadata_table[5]),85); + vcdp->chgArray(c+23403,(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cache_miss_resrv__DOT__metadata_table[6]),85); + vcdp->chgArray(c+23406,(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cache_miss_resrv__DOT__metadata_table[7]),85); + vcdp->chgArray(c+23409,(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cache_miss_resrv__DOT__metadata_table[8]),85); + vcdp->chgArray(c+23412,(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cache_miss_resrv__DOT__metadata_table[9]),85); + vcdp->chgArray(c+23415,(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cache_miss_resrv__DOT__metadata_table[10]),85); + vcdp->chgArray(c+23418,(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cache_miss_resrv__DOT__metadata_table[11]),85); + vcdp->chgArray(c+23421,(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cache_miss_resrv__DOT__metadata_table[12]),85); + vcdp->chgArray(c+23424,(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cache_miss_resrv__DOT__metadata_table[13]),85); + vcdp->chgArray(c+23427,(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cache_miss_resrv__DOT__metadata_table[14]),85); + vcdp->chgArray(c+23430,(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cache_miss_resrv__DOT__metadata_table[15]),85); + vcdp->chgArray(c+23769,(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cache_miss_resrv__DOT__addr_table),416); + vcdp->chgBus(c+23873,(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cache_miss_resrv__DOT__valid_table),16); + vcdp->chgBus(c+23881,(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cache_miss_resrv__DOT__ready_table),16); + vcdp->chgBus(c+23889,(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr),4); + vcdp->chgBus(c+23897,(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cache_miss_resrv__DOT__head_ptr),4); + vcdp->chgBus(c+23905,(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cache_miss_resrv__DOT__tail_ptr),4); + vcdp->chgBus(c+23913,(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cache_miss_resrv__DOT__size),5); + vcdp->chgBit(c+23921,((0x10U != (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cache_miss_resrv__DOT__size)))); + vcdp->chgBus(c+23929,(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cwb_queue__DOT__size_r),3); + vcdp->chgArray(c+23937,(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cwb_queue__DOT__genblk3__DOT__data[0]),76); + vcdp->chgArray(c+23940,(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cwb_queue__DOT__genblk3__DOT__data[1]),76); + vcdp->chgArray(c+23943,(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cwb_queue__DOT__genblk3__DOT__data[2]),76); + vcdp->chgArray(c+23946,(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cwb_queue__DOT__genblk3__DOT__data[3]),76); + vcdp->chgArray(c+24033,(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cwb_queue__DOT__genblk3__DOT__genblk2__DOT__head_r),76); + vcdp->chgArray(c+24057,(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cwb_queue__DOT__genblk3__DOT__genblk2__DOT__curr_r),76); + vcdp->chgBus(c+24081,(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cwb_queue__DOT__genblk3__DOT__genblk2__DOT__wr_ptr_r),2); + vcdp->chgBus(c+24089,(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cwb_queue__DOT__genblk3__DOT__genblk2__DOT__rd_ptr_r),2); + vcdp->chgBus(c+24097,(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cwb_queue__DOT__genblk3__DOT__genblk2__DOT__rd_ptr_next_r),2); + vcdp->chgBit(c+24105,(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cwb_queue__DOT__genblk3__DOT__genblk2__DOT__bypass_r)); + vcdp->chgBus(c+24113,(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__dwb_queue__DOT__size_r),3); + vcdp->chgArray(c+24121,(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__data[0]),200); + vcdp->chgArray(c+24128,(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__data[1]),200); + vcdp->chgArray(c+24135,(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__data[2]),200); + vcdp->chgArray(c+24142,(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__data[3]),200); + vcdp->chgArray(c+24345,(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__genblk2__DOT__head_r),200); + vcdp->chgArray(c+24401,(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__genblk2__DOT__curr_r),200); + vcdp->chgBus(c+24457,(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__genblk2__DOT__wr_ptr_r),2); + vcdp->chgBus(c+24465,(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__genblk2__DOT__rd_ptr_r),2); + vcdp->chgBus(c+24473,(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__genblk2__DOT__rd_ptr_next_r),2); + vcdp->chgBit(c+24481,(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__genblk2__DOT__bypass_r)); + } +} + +void VVX_cache::traceChgThis__6(VVX_cache__Syms* __restrict vlSymsp, VerilatedVcd* vcdp, uint32_t code) { + VVX_cache* __restrict vlTOPp VL_ATTR_UNUSED = vlSymsp->TOPp; + int c = code; + if (0 && vcdp && c) {} // Prevent unused + // Body + { + vcdp->chgBit(c+24489,(vlTOPp->clk)); + vcdp->chgBit(c+24497,(vlTOPp->reset)); + vcdp->chgBus(c+24505,(vlTOPp->core_req_valid),4); + vcdp->chgBus(c+24513,(vlTOPp->core_req_rw),4); + vcdp->chgBus(c+24521,(vlTOPp->core_req_byteen),16); + vcdp->chgArray(c+24529,(vlTOPp->core_req_addr),120); + vcdp->chgArray(c+24561,(vlTOPp->core_req_data),128); + vcdp->chgQuad(c+24593,(vlTOPp->core_req_tag),42); + vcdp->chgBit(c+24609,(vlTOPp->core_req_ready)); + vcdp->chgBus(c+24617,(vlTOPp->core_rsp_valid),4); + vcdp->chgArray(c+24625,(vlTOPp->core_rsp_data),128); + vcdp->chgQuad(c+24657,(vlTOPp->core_rsp_tag),42); + vcdp->chgBit(c+24673,(vlTOPp->core_rsp_ready)); + vcdp->chgBit(c+24681,(vlTOPp->dram_req_valid)); + vcdp->chgBit(c+24689,(vlTOPp->dram_req_rw)); + vcdp->chgBus(c+24697,(vlTOPp->dram_req_byteen),16); + vcdp->chgBus(c+24705,(vlTOPp->dram_req_addr),28); + vcdp->chgArray(c+24713,(vlTOPp->dram_req_data),128); + vcdp->chgBus(c+24745,(vlTOPp->dram_req_tag),28); + vcdp->chgBit(c+24753,(vlTOPp->dram_req_ready)); + vcdp->chgBit(c+24761,(vlTOPp->dram_rsp_valid)); + vcdp->chgArray(c+24769,(vlTOPp->dram_rsp_data),128); + vcdp->chgBus(c+24801,(vlTOPp->dram_rsp_tag),28); + vcdp->chgBit(c+24809,(vlTOPp->dram_rsp_ready)); + vcdp->chgBit(c+24817,(vlTOPp->snp_req_valid)); + vcdp->chgBus(c+24825,(vlTOPp->snp_req_addr),28); + vcdp->chgBit(c+24833,(vlTOPp->snp_req_invalidate)); + vcdp->chgBus(c+24841,(vlTOPp->snp_req_tag),28); + vcdp->chgBit(c+24849,(vlTOPp->snp_req_ready)); + vcdp->chgBit(c+24857,(vlTOPp->snp_rsp_valid)); + vcdp->chgBus(c+24865,(vlTOPp->snp_rsp_tag),28); + vcdp->chgBit(c+24873,(vlTOPp->snp_rsp_ready)); + vcdp->chgBus(c+24881,(vlTOPp->snp_fwdout_valid),2); + vcdp->chgQuad(c+24889,(vlTOPp->snp_fwdout_addr),56); + vcdp->chgBus(c+24905,(vlTOPp->snp_fwdout_invalidate),2); + vcdp->chgBus(c+24913,(vlTOPp->snp_fwdout_tag),2); + vcdp->chgBus(c+24921,(vlTOPp->snp_fwdout_ready),2); + vcdp->chgBus(c+24929,(vlTOPp->snp_fwdin_valid),2); + vcdp->chgBus(c+24937,(vlTOPp->snp_fwdin_tag),2); + vcdp->chgBus(c+24945,(vlTOPp->snp_fwdin_ready),2); + vcdp->chgBit(c+24953,((1U & ((IData)(vlTOPp->VX_cache__DOT__per_bank_snp_req_ready) + >> (3U & vlTOPp->snp_req_addr))))); + vcdp->chgBit(c+24961,(((IData)(vlTOPp->dram_rsp_valid) + & (0U == (3U & vlTOPp->dram_rsp_tag))))); + vcdp->chgBus(c+24969,((0x3ffffffU & (vlTOPp->dram_rsp_tag + >> 2U))),26); + vcdp->chgBit(c+24977,(((IData)(vlTOPp->snp_req_valid) + & (0U == (3U & vlTOPp->snp_req_addr))))); + vcdp->chgBus(c+24985,((0x3ffffffU & (vlTOPp->snp_req_addr + >> 2U))),26); + vcdp->chgBit(c+24993,(((IData)(vlTOPp->dram_rsp_valid) + & (1U == (3U & vlTOPp->dram_rsp_tag))))); + vcdp->chgBit(c+25001,(((IData)(vlTOPp->snp_req_valid) + & (1U == (3U & vlTOPp->snp_req_addr))))); + vcdp->chgBit(c+25009,(((IData)(vlTOPp->dram_rsp_valid) + & (2U == (3U & vlTOPp->dram_rsp_tag))))); + vcdp->chgBit(c+25017,(((IData)(vlTOPp->snp_req_valid) + & (2U == (3U & vlTOPp->snp_req_addr))))); + vcdp->chgBit(c+25025,(((IData)(vlTOPp->dram_rsp_valid) + & (3U == (3U & vlTOPp->dram_rsp_tag))))); + vcdp->chgBit(c+25033,(((IData)(vlTOPp->snp_req_valid) + & (3U == (3U & vlTOPp->snp_req_addr))))); + vcdp->chgBit(c+25041,(((IData)(vlTOPp->dram_req_valid) + & (~ (IData)(vlTOPp->dram_req_rw))))); + vcdp->chgBit(c+25049,((((IData)(vlTOPp->dram_req_valid) + & (~ (IData)(vlTOPp->dram_req_rw))) + & (~ (IData)(vlTOPp->VX_cache__DOT__cache_dram_req_arb__DOT__prfqq__DOT__pfq_queue__DOT__size_r))))); + } +} diff --git a/hw/unit_tests/cache/obj_dir/VVX_cache__Trace__Slow.cpp b/hw/unit_tests/cache/obj_dir/VVX_cache__Trace__Slow.cpp new file mode 100644 index 00000000..d54d85df --- /dev/null +++ b/hw/unit_tests/cache/obj_dir/VVX_cache__Trace__Slow.cpp @@ -0,0 +1,6948 @@ +// Verilated -*- C++ -*- +// DESCRIPTION: Verilator output: Tracing implementation internals +#include "verilated_vcd_c.h" +#include "VVX_cache__Syms.h" + + +//====================== + +void VVX_cache::trace(VerilatedVcdC* tfp, int, int) { + tfp->spTrace()->addCallback(&VVX_cache::traceInit, &VVX_cache::traceFull, &VVX_cache::traceChg, this); +} +void VVX_cache::traceInit(VerilatedVcd* vcdp, void* userthis, uint32_t code) { + // Callback from vcd->open() + VVX_cache* t = (VVX_cache*)userthis; + VVX_cache__Syms* __restrict vlSymsp = t->__VlSymsp; // Setup global symbol table + if (!Verilated::calcUnusedSigs()) { + VL_FATAL_MT(__FILE__, __LINE__, __FILE__, + "Turning on wave traces requires Verilated::traceEverOn(true) call before time 0."); + } + vcdp->scopeEscape(' '); + t->traceInitThis(vlSymsp, vcdp, code); + vcdp->scopeEscape('.'); +} +void VVX_cache::traceFull(VerilatedVcd* vcdp, void* userthis, uint32_t code) { + // Callback from vcd->dump() + VVX_cache* t = (VVX_cache*)userthis; + VVX_cache__Syms* __restrict vlSymsp = t->__VlSymsp; // Setup global symbol table + t->traceFullThis(vlSymsp, vcdp, code); +} + +//====================== + + +void VVX_cache::traceInitThis(VVX_cache__Syms* __restrict vlSymsp, VerilatedVcd* vcdp, uint32_t code) { + VVX_cache* __restrict vlTOPp VL_ATTR_UNUSED = vlSymsp->TOPp; + int c = code; + if (0 && vcdp && c) {} // Prevent unused + vcdp->module(vlSymsp->name()); // Setup signal names + // Body + { + vlTOPp->traceInitThis__1(vlSymsp, vcdp, code); + } +} + +void VVX_cache::traceFullThis(VVX_cache__Syms* __restrict vlSymsp, VerilatedVcd* vcdp, uint32_t code) { + VVX_cache* __restrict vlTOPp VL_ATTR_UNUSED = vlSymsp->TOPp; + int c = code; + if (0 && vcdp && c) {} // Prevent unused + // Body + { + vlTOPp->traceFullThis__1(vlSymsp, vcdp, code); + } + // Final + vlTOPp->__Vm_traceActivity = 0U; +} + +void VVX_cache::traceInitThis__1(VVX_cache__Syms* __restrict vlSymsp, VerilatedVcd* vcdp, uint32_t code) { + VVX_cache* __restrict vlTOPp VL_ATTR_UNUSED = vlSymsp->TOPp; + int c = code; + if (0 && vcdp && c) {} // Prevent unused + // Body + { + vcdp->declBit(c+24489,"clk", false,-1); + vcdp->declBit(c+24497,"reset", false,-1); + vcdp->declBus(c+24505,"core_req_valid", false,-1, 3,0); + vcdp->declBus(c+24513,"core_req_rw", false,-1, 3,0); + vcdp->declBus(c+24521,"core_req_byteen", false,-1, 15,0); + vcdp->declArray(c+24529,"core_req_addr", false,-1, 119,0); + vcdp->declArray(c+24561,"core_req_data", false,-1, 127,0); + vcdp->declQuad(c+24593,"core_req_tag", false,-1, 41,0); + vcdp->declBit(c+24609,"core_req_ready", false,-1); + vcdp->declBus(c+24617,"core_rsp_valid", false,-1, 3,0); + vcdp->declArray(c+24625,"core_rsp_data", false,-1, 127,0); + vcdp->declQuad(c+24657,"core_rsp_tag", false,-1, 41,0); + vcdp->declBit(c+24673,"core_rsp_ready", false,-1); + vcdp->declBit(c+24681,"dram_req_valid", false,-1); + vcdp->declBit(c+24689,"dram_req_rw", false,-1); + vcdp->declBus(c+24697,"dram_req_byteen", false,-1, 15,0); + vcdp->declBus(c+24705,"dram_req_addr", false,-1, 27,0); + vcdp->declArray(c+24713,"dram_req_data", false,-1, 127,0); + vcdp->declBus(c+24745,"dram_req_tag", false,-1, 27,0); + vcdp->declBit(c+24753,"dram_req_ready", false,-1); + vcdp->declBit(c+24761,"dram_rsp_valid", false,-1); + vcdp->declArray(c+24769,"dram_rsp_data", false,-1, 127,0); + vcdp->declBus(c+24801,"dram_rsp_tag", false,-1, 27,0); + vcdp->declBit(c+24809,"dram_rsp_ready", false,-1); + vcdp->declBit(c+24817,"snp_req_valid", false,-1); + vcdp->declBus(c+24825,"snp_req_addr", false,-1, 27,0); + vcdp->declBit(c+24833,"snp_req_invalidate", false,-1); + vcdp->declBus(c+24841,"snp_req_tag", false,-1, 27,0); + vcdp->declBit(c+24849,"snp_req_ready", false,-1); + vcdp->declBit(c+24857,"snp_rsp_valid", false,-1); + vcdp->declBus(c+24865,"snp_rsp_tag", false,-1, 27,0); + vcdp->declBit(c+24873,"snp_rsp_ready", false,-1); + vcdp->declBus(c+24881,"snp_fwdout_valid", false,-1, 1,0); + vcdp->declQuad(c+24889,"snp_fwdout_addr", false,-1, 55,0); + vcdp->declBus(c+24905,"snp_fwdout_invalidate", false,-1, 1,0); + vcdp->declBus(c+24913,"snp_fwdout_tag", false,-1, 1,0); + vcdp->declBus(c+24921,"snp_fwdout_ready", false,-1, 1,0); + vcdp->declBus(c+24929,"snp_fwdin_valid", false,-1, 1,0); + vcdp->declBus(c+24937,"snp_fwdin_tag", false,-1, 1,0); + vcdp->declBus(c+24945,"snp_fwdin_ready", false,-1, 1,0); + vcdp->declBus(c+25057,"VX_cache CACHE_ID", false,-1, 31,0); + vcdp->declBus(c+25065,"VX_cache CACHE_SIZE", false,-1, 31,0); + vcdp->declBus(c+25073,"VX_cache BANK_LINE_SIZE", false,-1, 31,0); + vcdp->declBus(c+25081,"VX_cache NUM_BANKS", false,-1, 31,0); + vcdp->declBus(c+25081,"VX_cache WORD_SIZE", false,-1, 31,0); + vcdp->declBus(c+25081,"VX_cache NUM_REQUESTS", false,-1, 31,0); + vcdp->declBus(c+25089,"VX_cache STAGE_1_CYCLES", false,-1, 31,0); + vcdp->declBus(c+25081,"VX_cache CREQ_SIZE", false,-1, 31,0); + vcdp->declBus(c+25073,"VX_cache MRVQ_SIZE", false,-1, 31,0); + vcdp->declBus(c+25073,"VX_cache DFPQ_SIZE", false,-1, 31,0); + vcdp->declBus(c+25073,"VX_cache SNRQ_SIZE", false,-1, 31,0); + vcdp->declBus(c+25081,"VX_cache CWBQ_SIZE", false,-1, 31,0); + vcdp->declBus(c+25081,"VX_cache DWBQ_SIZE", false,-1, 31,0); + vcdp->declBus(c+25081,"VX_cache DFQQ_SIZE", false,-1, 31,0); + vcdp->declBus(c+25089,"VX_cache WRITE_ENABLE", false,-1, 31,0); + vcdp->declBus(c+25089,"VX_cache DRAM_ENABLE", false,-1, 31,0); + vcdp->declBus(c+25057,"VX_cache SNOOP_FORWARDING", false,-1, 31,0); + vcdp->declBus(c+25089,"VX_cache PRFQ_SIZE", false,-1, 31,0); + vcdp->declBus(c+25057,"VX_cache PRFQ_STRIDE", false,-1, 31,0); + vcdp->declBus(c+25097,"VX_cache CORE_TAG_WIDTH", false,-1, 31,0); + vcdp->declBus(c+25105,"VX_cache CORE_TAG_ID_BITS", false,-1, 31,0); + vcdp->declBus(c+25113,"VX_cache DRAM_TAG_WIDTH", false,-1, 31,0); + vcdp->declBus(c+25121,"VX_cache NUM_SNP_REQUESTS", false,-1, 31,0); + vcdp->declBus(c+25113,"VX_cache SNP_REQ_TAG_WIDTH", false,-1, 31,0); + vcdp->declBus(c+25089,"VX_cache SNP_FWD_TAG_WIDTH", false,-1, 31,0); + vcdp->declBit(c+24489,"VX_cache clk", false,-1); + vcdp->declBit(c+24497,"VX_cache reset", false,-1); + vcdp->declBus(c+24505,"VX_cache core_req_valid", false,-1, 3,0); + vcdp->declBus(c+24513,"VX_cache core_req_rw", false,-1, 3,0); + vcdp->declBus(c+24521,"VX_cache core_req_byteen", false,-1, 15,0); + vcdp->declArray(c+24529,"VX_cache core_req_addr", false,-1, 119,0); + vcdp->declArray(c+24561,"VX_cache core_req_data", false,-1, 127,0); + vcdp->declQuad(c+24593,"VX_cache core_req_tag", false,-1, 41,0); + vcdp->declBit(c+24609,"VX_cache core_req_ready", false,-1); + vcdp->declBus(c+24617,"VX_cache core_rsp_valid", false,-1, 3,0); + vcdp->declArray(c+24625,"VX_cache core_rsp_data", false,-1, 127,0); + vcdp->declQuad(c+24657,"VX_cache core_rsp_tag", false,-1, 41,0); + vcdp->declBit(c+24673,"VX_cache core_rsp_ready", false,-1); + vcdp->declBit(c+24681,"VX_cache dram_req_valid", false,-1); + vcdp->declBit(c+24689,"VX_cache dram_req_rw", false,-1); + vcdp->declBus(c+24697,"VX_cache dram_req_byteen", false,-1, 15,0); + vcdp->declBus(c+24705,"VX_cache dram_req_addr", false,-1, 27,0); + vcdp->declArray(c+24713,"VX_cache dram_req_data", false,-1, 127,0); + vcdp->declBus(c+24745,"VX_cache dram_req_tag", false,-1, 27,0); + vcdp->declBit(c+24753,"VX_cache dram_req_ready", false,-1); + vcdp->declBit(c+24761,"VX_cache dram_rsp_valid", false,-1); + vcdp->declArray(c+24769,"VX_cache dram_rsp_data", false,-1, 127,0); + vcdp->declBus(c+24801,"VX_cache dram_rsp_tag", false,-1, 27,0); + vcdp->declBit(c+24809,"VX_cache dram_rsp_ready", false,-1); + vcdp->declBit(c+24817,"VX_cache snp_req_valid", false,-1); + vcdp->declBus(c+24825,"VX_cache snp_req_addr", false,-1, 27,0); + vcdp->declBit(c+24833,"VX_cache snp_req_invalidate", false,-1); + vcdp->declBus(c+24841,"VX_cache snp_req_tag", false,-1, 27,0); + vcdp->declBit(c+24849,"VX_cache snp_req_ready", false,-1); + vcdp->declBit(c+24857,"VX_cache snp_rsp_valid", false,-1); + vcdp->declBus(c+24865,"VX_cache snp_rsp_tag", false,-1, 27,0); + vcdp->declBit(c+24873,"VX_cache snp_rsp_ready", false,-1); + vcdp->declBus(c+24881,"VX_cache snp_fwdout_valid", false,-1, 1,0); + vcdp->declQuad(c+24889,"VX_cache snp_fwdout_addr", false,-1, 55,0); + vcdp->declBus(c+24905,"VX_cache snp_fwdout_invalidate", false,-1, 1,0); + vcdp->declBus(c+24913,"VX_cache snp_fwdout_tag", false,-1, 1,0); + vcdp->declBus(c+24921,"VX_cache snp_fwdout_ready", false,-1, 1,0); + vcdp->declBus(c+24929,"VX_cache snp_fwdin_valid", false,-1, 1,0); + vcdp->declBus(c+24937,"VX_cache snp_fwdin_tag", false,-1, 1,0); + vcdp->declBus(c+24945,"VX_cache snp_fwdin_ready", false,-1, 1,0); + vcdp->declBus(c+1,"VX_cache per_bank_valid", false,-1, 15,0); + vcdp->declBus(c+1089,"VX_cache per_bank_core_req_ready", false,-1, 3,0); + vcdp->declBus(c+1097,"VX_cache per_bank_core_rsp_valid", false,-1, 3,0); + vcdp->declBus(c+1105,"VX_cache per_bank_core_rsp_tid", false,-1, 7,0); + vcdp->declArray(c+1113,"VX_cache per_bank_core_rsp_data", false,-1, 127,0); + vcdp->declArray(c+1145,"VX_cache per_bank_core_rsp_tag", false,-1, 167,0); + vcdp->declBus(c+9,"VX_cache per_bank_core_rsp_ready", false,-1, 3,0); + vcdp->declBus(c+1193,"VX_cache per_bank_dram_fill_req_valid", false,-1, 3,0); + vcdp->declArray(c+1201,"VX_cache per_bank_dram_fill_req_addr", false,-1, 111,0); + vcdp->declBit(c+10065,"VX_cache dram_fill_req_ready", false,-1); + vcdp->declBus(c+1233,"VX_cache per_bank_dram_fill_rsp_ready", false,-1, 3,0); + vcdp->declBus(c+17,"VX_cache per_bank_dram_wb_req_ready", false,-1, 3,0); + vcdp->declBus(c+1241,"VX_cache per_bank_dram_wb_req_valid", false,-1, 3,0); + vcdp->declQuad(c+1249,"VX_cache per_bank_dram_wb_req_byteen", false,-1, 63,0); + vcdp->declArray(c+1265,"VX_cache per_bank_dram_wb_req_addr", false,-1, 111,0); + vcdp->declArray(c+1297,"VX_cache per_bank_dram_wb_req_data", false,-1, 511,0); + vcdp->declBus(c+1425,"VX_cache per_bank_snp_req_ready", false,-1, 3,0); + vcdp->declBus(c+1433,"VX_cache per_bank_snp_rsp_valid", false,-1, 3,0); + vcdp->declArray(c+1441,"VX_cache per_bank_snp_rsp_tag", false,-1, 111,0); + vcdp->declBus(c+25,"VX_cache per_bank_snp_rsp_ready", false,-1, 3,0); + vcdp->declBit(c+24817,"VX_cache snp_req_valid_qual", false,-1); + vcdp->declBus(c+24825,"VX_cache snp_req_addr_qual", false,-1, 27,0); + vcdp->declBit(c+24833,"VX_cache snp_req_invalidate_qual", false,-1); + vcdp->declBus(c+24841,"VX_cache snp_req_tag_qual", false,-1, 27,0); + vcdp->declBit(c+24953,"VX_cache snp_req_ready_qual", false,-1); + vcdp->declBus(c+33,"VX_cache genblk5[0] curr_bank_core_req_valid", false,-1, 3,0); + vcdp->declBus(c+24513,"VX_cache genblk5[0] curr_bank_core_req_rw", false,-1, 3,0); + vcdp->declBus(c+24521,"VX_cache genblk5[0] curr_bank_core_req_byteen", false,-1, 15,0); + vcdp->declArray(c+24529,"VX_cache genblk5[0] curr_bank_core_req_addr", false,-1, 119,0); + vcdp->declQuad(c+24593,"VX_cache genblk5[0] curr_bank_core_req_tag", false,-1, 41,0); + vcdp->declArray(c+24561,"VX_cache genblk5[0] curr_bank_core_req_data", false,-1, 127,0); + vcdp->declBit(c+10073,"VX_cache genblk5[0] curr_bank_core_rsp_valid", false,-1); + vcdp->declBus(c+1473,"VX_cache genblk5[0] curr_bank_core_rsp_tid", false,-1, 1,0); + vcdp->declBus(c+1481,"VX_cache genblk5[0] curr_bank_core_rsp_data", false,-1, 31,0); + vcdp->declQuad(c+1489,"VX_cache genblk5[0] curr_bank_core_rsp_tag", false,-1, 41,0); + vcdp->declBit(c+41,"VX_cache genblk5[0] curr_bank_core_rsp_ready", false,-1); + vcdp->declBit(c+24961,"VX_cache genblk5[0] curr_bank_dram_fill_rsp_valid", false,-1); + vcdp->declArray(c+24769,"VX_cache genblk5[0] curr_bank_dram_fill_rsp_data", false,-1, 127,0); + vcdp->declBus(c+24969,"VX_cache genblk5[0] curr_bank_dram_fill_rsp_addr", false,-1, 25,0); + vcdp->declBit(c+10081,"VX_cache genblk5[0] curr_bank_dram_fill_rsp_ready", false,-1); + vcdp->declBit(c+1505,"VX_cache genblk5[0] curr_bank_dram_fill_req_valid", false,-1); + vcdp->declBus(c+10089,"VX_cache genblk5[0] curr_bank_dram_fill_req_addr", false,-1, 25,0); + vcdp->declBit(c+10065,"VX_cache genblk5[0] curr_bank_dram_fill_req_ready", false,-1); + vcdp->declBit(c+1513,"VX_cache genblk5[0] curr_bank_dram_wb_req_valid", false,-1); + vcdp->declBus(c+1521,"VX_cache genblk5[0] curr_bank_dram_wb_req_byteen", false,-1, 15,0); + vcdp->declBus(c+1529,"VX_cache genblk5[0] curr_bank_dram_wb_req_addr", false,-1, 25,0); + vcdp->declArray(c+1537,"VX_cache genblk5[0] curr_bank_dram_wb_req_data", false,-1, 127,0); + vcdp->declBit(c+49,"VX_cache genblk5[0] curr_bank_dram_wb_req_ready", false,-1); + vcdp->declBit(c+24977,"VX_cache genblk5[0] curr_bank_snp_req_valid", false,-1); + vcdp->declBus(c+24985,"VX_cache genblk5[0] curr_bank_snp_req_addr", false,-1, 25,0); + vcdp->declBit(c+24833,"VX_cache genblk5[0] curr_bank_snp_req_invalidate", false,-1); + vcdp->declBus(c+24841,"VX_cache genblk5[0] curr_bank_snp_req_tag", false,-1, 27,0); + vcdp->declBit(c+10097,"VX_cache genblk5[0] curr_bank_snp_req_ready", false,-1); + vcdp->declBit(c+1569,"VX_cache genblk5[0] curr_bank_snp_rsp_valid", false,-1); + vcdp->declBus(c+1577,"VX_cache genblk5[0] curr_bank_snp_rsp_tag", false,-1, 27,0); + vcdp->declBit(c+57,"VX_cache genblk5[0] curr_bank_snp_rsp_ready", false,-1); + vcdp->declBit(c+10105,"VX_cache genblk5[0] curr_bank_core_req_ready", false,-1); + vcdp->declBus(c+65,"VX_cache genblk5[1] curr_bank_core_req_valid", false,-1, 3,0); + vcdp->declBus(c+24513,"VX_cache genblk5[1] curr_bank_core_req_rw", false,-1, 3,0); + vcdp->declBus(c+24521,"VX_cache genblk5[1] curr_bank_core_req_byteen", false,-1, 15,0); + vcdp->declArray(c+24529,"VX_cache genblk5[1] curr_bank_core_req_addr", false,-1, 119,0); + vcdp->declQuad(c+24593,"VX_cache genblk5[1] curr_bank_core_req_tag", false,-1, 41,0); + vcdp->declArray(c+24561,"VX_cache genblk5[1] curr_bank_core_req_data", false,-1, 127,0); + vcdp->declBit(c+10113,"VX_cache genblk5[1] curr_bank_core_rsp_valid", false,-1); + vcdp->declBus(c+1585,"VX_cache genblk5[1] curr_bank_core_rsp_tid", false,-1, 1,0); + vcdp->declBus(c+1593,"VX_cache genblk5[1] curr_bank_core_rsp_data", false,-1, 31,0); + vcdp->declQuad(c+1601,"VX_cache genblk5[1] curr_bank_core_rsp_tag", false,-1, 41,0); + vcdp->declBit(c+73,"VX_cache genblk5[1] curr_bank_core_rsp_ready", false,-1); + vcdp->declBit(c+24993,"VX_cache genblk5[1] curr_bank_dram_fill_rsp_valid", false,-1); + vcdp->declArray(c+24769,"VX_cache genblk5[1] curr_bank_dram_fill_rsp_data", false,-1, 127,0); + vcdp->declBus(c+24969,"VX_cache genblk5[1] curr_bank_dram_fill_rsp_addr", false,-1, 25,0); + vcdp->declBit(c+10121,"VX_cache genblk5[1] curr_bank_dram_fill_rsp_ready", false,-1); + vcdp->declBit(c+1617,"VX_cache genblk5[1] curr_bank_dram_fill_req_valid", false,-1); + vcdp->declBus(c+10129,"VX_cache genblk5[1] curr_bank_dram_fill_req_addr", false,-1, 25,0); + vcdp->declBit(c+10065,"VX_cache genblk5[1] curr_bank_dram_fill_req_ready", false,-1); + vcdp->declBit(c+1625,"VX_cache genblk5[1] curr_bank_dram_wb_req_valid", false,-1); + vcdp->declBus(c+1633,"VX_cache genblk5[1] curr_bank_dram_wb_req_byteen", false,-1, 15,0); + vcdp->declBus(c+1641,"VX_cache genblk5[1] curr_bank_dram_wb_req_addr", false,-1, 25,0); + vcdp->declArray(c+1649,"VX_cache genblk5[1] curr_bank_dram_wb_req_data", false,-1, 127,0); + vcdp->declBit(c+81,"VX_cache genblk5[1] curr_bank_dram_wb_req_ready", false,-1); + vcdp->declBit(c+25001,"VX_cache genblk5[1] curr_bank_snp_req_valid", false,-1); + vcdp->declBus(c+24985,"VX_cache genblk5[1] curr_bank_snp_req_addr", false,-1, 25,0); + vcdp->declBit(c+24833,"VX_cache genblk5[1] curr_bank_snp_req_invalidate", false,-1); + vcdp->declBus(c+24841,"VX_cache genblk5[1] curr_bank_snp_req_tag", false,-1, 27,0); + vcdp->declBit(c+10137,"VX_cache genblk5[1] curr_bank_snp_req_ready", false,-1); + vcdp->declBit(c+1681,"VX_cache genblk5[1] curr_bank_snp_rsp_valid", false,-1); + vcdp->declBus(c+1689,"VX_cache genblk5[1] curr_bank_snp_rsp_tag", false,-1, 27,0); + vcdp->declBit(c+89,"VX_cache genblk5[1] curr_bank_snp_rsp_ready", false,-1); + vcdp->declBit(c+10145,"VX_cache genblk5[1] curr_bank_core_req_ready", false,-1); + vcdp->declBus(c+97,"VX_cache genblk5[2] curr_bank_core_req_valid", false,-1, 3,0); + vcdp->declBus(c+24513,"VX_cache genblk5[2] curr_bank_core_req_rw", false,-1, 3,0); + vcdp->declBus(c+24521,"VX_cache genblk5[2] curr_bank_core_req_byteen", false,-1, 15,0); + vcdp->declArray(c+24529,"VX_cache genblk5[2] curr_bank_core_req_addr", false,-1, 119,0); + vcdp->declQuad(c+24593,"VX_cache genblk5[2] curr_bank_core_req_tag", false,-1, 41,0); + vcdp->declArray(c+24561,"VX_cache genblk5[2] curr_bank_core_req_data", false,-1, 127,0); + vcdp->declBit(c+10153,"VX_cache genblk5[2] curr_bank_core_rsp_valid", false,-1); + vcdp->declBus(c+1697,"VX_cache genblk5[2] curr_bank_core_rsp_tid", false,-1, 1,0); + vcdp->declBus(c+1705,"VX_cache genblk5[2] curr_bank_core_rsp_data", false,-1, 31,0); + vcdp->declQuad(c+1713,"VX_cache genblk5[2] curr_bank_core_rsp_tag", false,-1, 41,0); + vcdp->declBit(c+105,"VX_cache genblk5[2] curr_bank_core_rsp_ready", false,-1); + vcdp->declBit(c+25009,"VX_cache genblk5[2] curr_bank_dram_fill_rsp_valid", false,-1); + vcdp->declArray(c+24769,"VX_cache genblk5[2] curr_bank_dram_fill_rsp_data", false,-1, 127,0); + vcdp->declBus(c+24969,"VX_cache genblk5[2] curr_bank_dram_fill_rsp_addr", false,-1, 25,0); + vcdp->declBit(c+10161,"VX_cache genblk5[2] curr_bank_dram_fill_rsp_ready", false,-1); + vcdp->declBit(c+1729,"VX_cache genblk5[2] curr_bank_dram_fill_req_valid", false,-1); + vcdp->declBus(c+10169,"VX_cache genblk5[2] curr_bank_dram_fill_req_addr", false,-1, 25,0); + vcdp->declBit(c+10065,"VX_cache genblk5[2] curr_bank_dram_fill_req_ready", false,-1); + vcdp->declBit(c+1737,"VX_cache genblk5[2] curr_bank_dram_wb_req_valid", false,-1); + vcdp->declBus(c+1745,"VX_cache genblk5[2] curr_bank_dram_wb_req_byteen", false,-1, 15,0); + vcdp->declBus(c+1753,"VX_cache genblk5[2] curr_bank_dram_wb_req_addr", false,-1, 25,0); + vcdp->declArray(c+1761,"VX_cache genblk5[2] curr_bank_dram_wb_req_data", false,-1, 127,0); + vcdp->declBit(c+113,"VX_cache genblk5[2] curr_bank_dram_wb_req_ready", false,-1); + vcdp->declBit(c+25017,"VX_cache genblk5[2] curr_bank_snp_req_valid", false,-1); + vcdp->declBus(c+24985,"VX_cache genblk5[2] curr_bank_snp_req_addr", false,-1, 25,0); + vcdp->declBit(c+24833,"VX_cache genblk5[2] curr_bank_snp_req_invalidate", false,-1); + vcdp->declBus(c+24841,"VX_cache genblk5[2] curr_bank_snp_req_tag", false,-1, 27,0); + vcdp->declBit(c+10177,"VX_cache genblk5[2] curr_bank_snp_req_ready", false,-1); + vcdp->declBit(c+1793,"VX_cache genblk5[2] curr_bank_snp_rsp_valid", false,-1); + vcdp->declBus(c+1801,"VX_cache genblk5[2] curr_bank_snp_rsp_tag", false,-1, 27,0); + vcdp->declBit(c+121,"VX_cache genblk5[2] curr_bank_snp_rsp_ready", false,-1); + vcdp->declBit(c+10185,"VX_cache genblk5[2] curr_bank_core_req_ready", false,-1); + vcdp->declBus(c+129,"VX_cache genblk5[3] curr_bank_core_req_valid", false,-1, 3,0); + vcdp->declBus(c+24513,"VX_cache genblk5[3] curr_bank_core_req_rw", false,-1, 3,0); + vcdp->declBus(c+24521,"VX_cache genblk5[3] curr_bank_core_req_byteen", false,-1, 15,0); + vcdp->declArray(c+24529,"VX_cache genblk5[3] curr_bank_core_req_addr", false,-1, 119,0); + vcdp->declQuad(c+24593,"VX_cache genblk5[3] curr_bank_core_req_tag", false,-1, 41,0); + vcdp->declArray(c+24561,"VX_cache genblk5[3] curr_bank_core_req_data", false,-1, 127,0); + vcdp->declBit(c+10193,"VX_cache genblk5[3] curr_bank_core_rsp_valid", false,-1); + vcdp->declBus(c+1809,"VX_cache genblk5[3] curr_bank_core_rsp_tid", false,-1, 1,0); + vcdp->declBus(c+1817,"VX_cache genblk5[3] curr_bank_core_rsp_data", false,-1, 31,0); + vcdp->declQuad(c+1825,"VX_cache genblk5[3] curr_bank_core_rsp_tag", false,-1, 41,0); + vcdp->declBit(c+137,"VX_cache genblk5[3] curr_bank_core_rsp_ready", false,-1); + vcdp->declBit(c+25025,"VX_cache genblk5[3] curr_bank_dram_fill_rsp_valid", false,-1); + vcdp->declArray(c+24769,"VX_cache genblk5[3] curr_bank_dram_fill_rsp_data", false,-1, 127,0); + vcdp->declBus(c+24969,"VX_cache genblk5[3] curr_bank_dram_fill_rsp_addr", false,-1, 25,0); + vcdp->declBit(c+10201,"VX_cache genblk5[3] curr_bank_dram_fill_rsp_ready", false,-1); + vcdp->declBit(c+1841,"VX_cache genblk5[3] curr_bank_dram_fill_req_valid", false,-1); + vcdp->declBus(c+10209,"VX_cache genblk5[3] curr_bank_dram_fill_req_addr", false,-1, 25,0); + vcdp->declBit(c+10065,"VX_cache genblk5[3] curr_bank_dram_fill_req_ready", false,-1); + vcdp->declBit(c+1849,"VX_cache genblk5[3] curr_bank_dram_wb_req_valid", false,-1); + vcdp->declBus(c+1857,"VX_cache genblk5[3] curr_bank_dram_wb_req_byteen", false,-1, 15,0); + vcdp->declBus(c+1865,"VX_cache genblk5[3] curr_bank_dram_wb_req_addr", false,-1, 25,0); + vcdp->declArray(c+1873,"VX_cache genblk5[3] curr_bank_dram_wb_req_data", false,-1, 127,0); + vcdp->declBit(c+145,"VX_cache genblk5[3] curr_bank_dram_wb_req_ready", false,-1); + vcdp->declBit(c+25033,"VX_cache genblk5[3] curr_bank_snp_req_valid", false,-1); + vcdp->declBus(c+24985,"VX_cache genblk5[3] curr_bank_snp_req_addr", false,-1, 25,0); + vcdp->declBit(c+24833,"VX_cache genblk5[3] curr_bank_snp_req_invalidate", false,-1); + vcdp->declBus(c+24841,"VX_cache genblk5[3] curr_bank_snp_req_tag", false,-1, 27,0); + vcdp->declBit(c+10217,"VX_cache genblk5[3] curr_bank_snp_req_ready", false,-1); + vcdp->declBit(c+1905,"VX_cache genblk5[3] curr_bank_snp_rsp_valid", false,-1); + vcdp->declBus(c+1913,"VX_cache genblk5[3] curr_bank_snp_rsp_tag", false,-1, 27,0); + vcdp->declBit(c+153,"VX_cache genblk5[3] curr_bank_snp_rsp_ready", false,-1); + vcdp->declBit(c+10225,"VX_cache genblk5[3] curr_bank_core_req_ready", false,-1); + vcdp->declBus(c+25073,"VX_cache cache_core_req_bank_sel BANK_LINE_SIZE", false,-1, 31,0); + vcdp->declBus(c+25081,"VX_cache cache_core_req_bank_sel WORD_SIZE", false,-1, 31,0); + vcdp->declBus(c+25081,"VX_cache cache_core_req_bank_sel NUM_BANKS", false,-1, 31,0); + vcdp->declBus(c+25081,"VX_cache cache_core_req_bank_sel NUM_REQUESTS", false,-1, 31,0); + vcdp->declBus(c+24505,"VX_cache cache_core_req_bank_sel core_req_valid", false,-1, 3,0); + vcdp->declArray(c+24529,"VX_cache cache_core_req_bank_sel core_req_addr", false,-1, 119,0); + vcdp->declBus(c+1089,"VX_cache cache_core_req_bank_sel per_bank_ready", false,-1, 3,0); + vcdp->declBus(c+1,"VX_cache cache_core_req_bank_sel per_bank_valid", false,-1, 15,0); + vcdp->declBit(c+24609,"VX_cache cache_core_req_bank_sel core_req_ready", false,-1); + vcdp->declBus(c+25129,"VX_cache cache_core_req_bank_sel i", false,-1, 31,0); + vcdp->declBus(c+161,"VX_cache cache_core_req_bank_sel genblk2 per_bank_ready_sel", false,-1, 3,0); + vcdp->declBus(c+25073,"VX_cache cache_dram_req_arb BANK_LINE_SIZE", false,-1, 31,0); + vcdp->declBus(c+25081,"VX_cache cache_dram_req_arb NUM_BANKS", false,-1, 31,0); + vcdp->declBus(c+25081,"VX_cache cache_dram_req_arb WORD_SIZE", false,-1, 31,0); + vcdp->declBus(c+25081,"VX_cache cache_dram_req_arb DFQQ_SIZE", false,-1, 31,0); + vcdp->declBus(c+25089,"VX_cache cache_dram_req_arb PRFQ_SIZE", false,-1, 31,0); + vcdp->declBus(c+25057,"VX_cache cache_dram_req_arb PRFQ_STRIDE", false,-1, 31,0); + vcdp->declBit(c+24489,"VX_cache cache_dram_req_arb clk", false,-1); + vcdp->declBit(c+24497,"VX_cache cache_dram_req_arb reset", false,-1); + vcdp->declBus(c+1193,"VX_cache cache_dram_req_arb per_bank_dram_fill_req_valid", false,-1, 3,0); + vcdp->declArray(c+1201,"VX_cache cache_dram_req_arb per_bank_dram_fill_req_addr", false,-1, 111,0); + vcdp->declBit(c+10065,"VX_cache cache_dram_req_arb dram_fill_req_ready", false,-1); + vcdp->declBus(c+1241,"VX_cache cache_dram_req_arb per_bank_dram_wb_req_valid", false,-1, 3,0); + vcdp->declQuad(c+1249,"VX_cache cache_dram_req_arb per_bank_dram_wb_req_byteen", false,-1, 63,0); + vcdp->declArray(c+1265,"VX_cache cache_dram_req_arb per_bank_dram_wb_req_addr", false,-1, 111,0); + vcdp->declArray(c+1297,"VX_cache cache_dram_req_arb per_bank_dram_wb_req_data", false,-1, 511,0); + vcdp->declBus(c+17,"VX_cache cache_dram_req_arb per_bank_dram_wb_req_ready", false,-1, 3,0); + vcdp->declBit(c+24681,"VX_cache cache_dram_req_arb dram_req_valid", false,-1); + vcdp->declBit(c+24689,"VX_cache cache_dram_req_arb dram_req_rw", false,-1); + vcdp->declBus(c+24697,"VX_cache cache_dram_req_arb dram_req_byteen", false,-1, 15,0); + vcdp->declBus(c+24705,"VX_cache cache_dram_req_arb dram_req_addr", false,-1, 27,0); + vcdp->declArray(c+24713,"VX_cache cache_dram_req_arb dram_req_data", false,-1, 127,0); + vcdp->declBit(c+24753,"VX_cache cache_dram_req_arb dram_req_ready", false,-1); + vcdp->declBit(c+25137,"VX_cache cache_dram_req_arb pref_pop", false,-1); + vcdp->declBit(c+25137,"VX_cache cache_dram_req_arb pref_valid", false,-1); + vcdp->declBus(c+10233,"VX_cache cache_dram_req_arb pref_addr", false,-1, 27,0); + vcdp->declBit(c+1921,"VX_cache cache_dram_req_arb dwb_valid", false,-1); + vcdp->declBit(c+1929,"VX_cache cache_dram_req_arb dfqq_req", false,-1); + vcdp->declBus(c+1937,"VX_cache cache_dram_req_arb dfqq_req_addr", false,-1, 27,0); + vcdp->declBit(c+1945,"VX_cache cache_dram_req_arb dfqq_empty", false,-1); + vcdp->declBit(c+169,"VX_cache cache_dram_req_arb dfqq_pop", false,-1); + vcdp->declBit(c+1953,"VX_cache cache_dram_req_arb dfqq_push", false,-1); + vcdp->declBit(c+10241,"VX_cache cache_dram_req_arb dfqq_full", false,-1); + vcdp->declBus(c+1961,"VX_cache cache_dram_req_arb dwb_bank", false,-1, 1,0); + vcdp->declBus(c+25073,"VX_cache cache_dram_req_arb prfqq BANK_LINE_SIZE", false,-1, 31,0); + vcdp->declBus(c+25081,"VX_cache cache_dram_req_arb prfqq WORD_SIZE", false,-1, 31,0); + vcdp->declBus(c+25089,"VX_cache cache_dram_req_arb prfqq PRFQ_SIZE", false,-1, 31,0); + vcdp->declBus(c+25057,"VX_cache cache_dram_req_arb prfqq PRFQ_STRIDE", false,-1, 31,0); + vcdp->declBit(c+24489,"VX_cache cache_dram_req_arb prfqq clk", false,-1); + vcdp->declBit(c+24497,"VX_cache cache_dram_req_arb prfqq reset", false,-1); + vcdp->declBit(c+25041,"VX_cache cache_dram_req_arb prfqq dram_req", false,-1); + vcdp->declBus(c+24705,"VX_cache cache_dram_req_arb prfqq dram_req_addr", false,-1, 27,0); + vcdp->declBit(c+25137,"VX_cache cache_dram_req_arb prfqq pref_pop", false,-1); + vcdp->declBit(c+25137,"VX_cache cache_dram_req_arb prfqq pref_valid", false,-1); + vcdp->declBus(c+10233,"VX_cache cache_dram_req_arb prfqq pref_addr", false,-1, 27,0); + vcdp->declBus(c+10249,"VX_cache cache_dram_req_arb prfqq use_valid", false,-1, 1,0); + vcdp->declBus(c+10233,"VX_cache cache_dram_req_arb prfqq use_addr", false,-1, 27,0); + vcdp->declBit(c+10257,"VX_cache cache_dram_req_arb prfqq current_valid", false,-1); + vcdp->declBus(c+10265,"VX_cache cache_dram_req_arb prfqq current_addr", false,-1, 27,0); + vcdp->declBit(c+10257,"VX_cache cache_dram_req_arb prfqq current_full", false,-1); + vcdp->declBit(c+10273,"VX_cache cache_dram_req_arb prfqq current_empty", false,-1); + vcdp->declBit(c+1969,"VX_cache cache_dram_req_arb prfqq update_use", false,-1); + vcdp->declBus(c+25113,"VX_cache cache_dram_req_arb prfqq pfq_queue DATAW", false,-1, 31,0); + vcdp->declBus(c+25089,"VX_cache cache_dram_req_arb prfqq pfq_queue SIZE", false,-1, 31,0); + vcdp->declBus(c+25089,"VX_cache cache_dram_req_arb prfqq pfq_queue BUFFERED_OUTPUT", false,-1, 31,0); + vcdp->declBit(c+24489,"VX_cache cache_dram_req_arb prfqq pfq_queue clk", false,-1); + vcdp->declBit(c+24497,"VX_cache cache_dram_req_arb prfqq pfq_queue reset", false,-1); + vcdp->declBit(c+25049,"VX_cache cache_dram_req_arb prfqq pfq_queue push", false,-1); + vcdp->declBit(c+1969,"VX_cache cache_dram_req_arb prfqq pfq_queue pop", false,-1); + vcdp->declBus(c+24705,"VX_cache cache_dram_req_arb prfqq pfq_queue data_in", false,-1, 27,0); + vcdp->declBus(c+10265,"VX_cache cache_dram_req_arb prfqq pfq_queue data_out", false,-1, 27,0); + vcdp->declBit(c+10273,"VX_cache cache_dram_req_arb prfqq pfq_queue empty", false,-1); + vcdp->declBit(c+10257,"VX_cache cache_dram_req_arb prfqq pfq_queue full", false,-1); + vcdp->declBus(c+10281,"VX_cache cache_dram_req_arb prfqq pfq_queue size", false,-1, 0,0); + vcdp->declBus(c+10281,"VX_cache cache_dram_req_arb prfqq pfq_queue size_r", false,-1, 0,0); + vcdp->declBit(c+1977,"VX_cache cache_dram_req_arb prfqq pfq_queue reading", false,-1); + vcdp->declBit(c+1985,"VX_cache cache_dram_req_arb prfqq pfq_queue writing", false,-1); + vcdp->declBus(c+10265,"VX_cache cache_dram_req_arb prfqq pfq_queue genblk2 head_r", false,-1, 27,0); + vcdp->declBus(c+25073,"VX_cache cache_dram_req_arb dram_fill_arb BANK_LINE_SIZE", false,-1, 31,0); + vcdp->declBus(c+25081,"VX_cache cache_dram_req_arb dram_fill_arb NUM_BANKS", false,-1, 31,0); + vcdp->declBus(c+25081,"VX_cache cache_dram_req_arb dram_fill_arb DFQQ_SIZE", false,-1, 31,0); + vcdp->declBit(c+24489,"VX_cache cache_dram_req_arb dram_fill_arb clk", false,-1); + vcdp->declBit(c+24497,"VX_cache cache_dram_req_arb dram_fill_arb reset", false,-1); + vcdp->declBit(c+1953,"VX_cache cache_dram_req_arb dram_fill_arb dfqq_push", false,-1); + vcdp->declBus(c+1193,"VX_cache cache_dram_req_arb dram_fill_arb per_bank_dram_fill_req_valid", false,-1, 3,0); + vcdp->declArray(c+1201,"VX_cache cache_dram_req_arb dram_fill_arb per_bank_dram_fill_req_addr", false,-1, 111,0); + vcdp->declBit(c+169,"VX_cache cache_dram_req_arb dram_fill_arb dfqq_pop", false,-1); + vcdp->declBit(c+1929,"VX_cache cache_dram_req_arb dram_fill_arb dfqq_req", false,-1); + vcdp->declBus(c+1937,"VX_cache cache_dram_req_arb dram_fill_arb dfqq_req_addr", false,-1, 27,0); + vcdp->declBit(c+1945,"VX_cache cache_dram_req_arb dram_fill_arb dfqq_empty", false,-1); + vcdp->declBit(c+10241,"VX_cache cache_dram_req_arb dram_fill_arb dfqq_full", false,-1); + vcdp->declBus(c+10289,"VX_cache cache_dram_req_arb dram_fill_arb use_per_bank_dram_fill_req_valid", false,-1, 3,0); + vcdp->declArray(c+10297,"VX_cache cache_dram_req_arb dram_fill_arb use_per_bank_dram_fill_req_addr", false,-1, 111,0); + vcdp->declBus(c+1993,"VX_cache cache_dram_req_arb dram_fill_arb out_per_bank_dram_fill_req_valid", false,-1, 3,0); + vcdp->declArray(c+2001,"VX_cache cache_dram_req_arb dram_fill_arb out_per_bank_dram_fill_req_addr", false,-1, 111,0); + vcdp->declBus(c+2033,"VX_cache cache_dram_req_arb dram_fill_arb use_per_bqual_bank_dram_fill_req_valid", false,-1, 3,0); + vcdp->declArray(c+2041,"VX_cache cache_dram_req_arb dram_fill_arb qual_bank_dram_fill_req_addr", false,-1, 111,0); + vcdp->declBus(c+2073,"VX_cache cache_dram_req_arb dram_fill_arb updated_bank_dram_fill_req_valid", false,-1, 3,0); + vcdp->declBit(c+10329,"VX_cache cache_dram_req_arb dram_fill_arb o_empty", false,-1); + vcdp->declBit(c+10337,"VX_cache cache_dram_req_arb dram_fill_arb use_empty", false,-1); + vcdp->declBit(c+2081,"VX_cache cache_dram_req_arb dram_fill_arb out_empty", false,-1); + vcdp->declBit(c+2089,"VX_cache cache_dram_req_arb dram_fill_arb push_qual", false,-1); + vcdp->declBit(c+953,"VX_cache cache_dram_req_arb dram_fill_arb pop_qual", false,-1); + vcdp->declBus(c+2097,"VX_cache cache_dram_req_arb dram_fill_arb qual_request_index", false,-1, 1,0); + vcdp->declBit(c+2105,"VX_cache cache_dram_req_arb dram_fill_arb qual_has_request", false,-1); + vcdp->declBus(c+25145,"VX_cache cache_dram_req_arb dram_fill_arb dfqq_queue DATAW", false,-1, 31,0); + vcdp->declBus(c+25081,"VX_cache cache_dram_req_arb dram_fill_arb dfqq_queue SIZE", false,-1, 31,0); + vcdp->declBus(c+25089,"VX_cache cache_dram_req_arb dram_fill_arb dfqq_queue BUFFERED_OUTPUT", false,-1, 31,0); + vcdp->declBit(c+24489,"VX_cache cache_dram_req_arb dram_fill_arb dfqq_queue clk", false,-1); + vcdp->declBit(c+24497,"VX_cache cache_dram_req_arb dram_fill_arb dfqq_queue reset", false,-1); + vcdp->declBit(c+2089,"VX_cache cache_dram_req_arb dram_fill_arb dfqq_queue push", false,-1); + vcdp->declBit(c+953,"VX_cache cache_dram_req_arb dram_fill_arb dfqq_queue pop", false,-1); + vcdp->declArray(c+2113,"VX_cache cache_dram_req_arb dram_fill_arb dfqq_queue data_in", false,-1, 115,0); + vcdp->declArray(c+2145,"VX_cache cache_dram_req_arb dram_fill_arb dfqq_queue data_out", false,-1, 115,0); + vcdp->declBit(c+10329,"VX_cache cache_dram_req_arb dram_fill_arb dfqq_queue empty", false,-1); + vcdp->declBit(c+10241,"VX_cache cache_dram_req_arb dram_fill_arb dfqq_queue full", false,-1); + vcdp->declBus(c+10345,"VX_cache cache_dram_req_arb dram_fill_arb dfqq_queue size", false,-1, 2,0); + vcdp->declBus(c+10345,"VX_cache cache_dram_req_arb dram_fill_arb dfqq_queue size_r", false,-1, 2,0); + vcdp->declBit(c+177,"VX_cache cache_dram_req_arb dram_fill_arb dfqq_queue reading", false,-1); + vcdp->declBit(c+2177,"VX_cache cache_dram_req_arb dram_fill_arb dfqq_queue writing", false,-1); + {int i; for (i=0; i<4; i++) { + vcdp->declArray(c+10353+i*4,"VX_cache cache_dram_req_arb dram_fill_arb dfqq_queue genblk3 data", true,(i+0), 115,0);}} + vcdp->declArray(c+10481,"VX_cache cache_dram_req_arb dram_fill_arb dfqq_queue genblk3 genblk2 head_r", false,-1, 115,0); + vcdp->declArray(c+10513,"VX_cache cache_dram_req_arb dram_fill_arb dfqq_queue genblk3 genblk2 curr_r", false,-1, 115,0); + vcdp->declBus(c+10545,"VX_cache cache_dram_req_arb dram_fill_arb dfqq_queue genblk3 genblk2 wr_ptr_r", false,-1, 1,0); + vcdp->declBus(c+10553,"VX_cache cache_dram_req_arb dram_fill_arb dfqq_queue genblk3 genblk2 rd_ptr_r", false,-1, 1,0); + vcdp->declBus(c+10561,"VX_cache cache_dram_req_arb dram_fill_arb dfqq_queue genblk3 genblk2 rd_ptr_next_r", false,-1, 1,0); + vcdp->declBit(c+10329,"VX_cache cache_dram_req_arb dram_fill_arb dfqq_queue genblk3 genblk2 empty_r", false,-1); + vcdp->declBit(c+10241,"VX_cache cache_dram_req_arb dram_fill_arb dfqq_queue genblk3 genblk2 full_r", false,-1); + vcdp->declBit(c+10569,"VX_cache cache_dram_req_arb dram_fill_arb dfqq_queue genblk3 genblk2 bypass_r", false,-1); + vcdp->declBus(c+25081,"VX_cache cache_dram_req_arb dram_fill_arb sel_bank N", false,-1, 31,0); + vcdp->declBit(c+24489,"VX_cache cache_dram_req_arb dram_fill_arb sel_bank clk", false,-1); + vcdp->declBit(c+24497,"VX_cache cache_dram_req_arb dram_fill_arb sel_bank reset", false,-1); + vcdp->declBus(c+2033,"VX_cache cache_dram_req_arb dram_fill_arb sel_bank requests", false,-1, 3,0); + vcdp->declBus(c+2097,"VX_cache cache_dram_req_arb dram_fill_arb sel_bank grant_index", false,-1, 1,0); + vcdp->declBus(c+2185,"VX_cache cache_dram_req_arb dram_fill_arb sel_bank grant_onehot", false,-1, 3,0); + vcdp->declBit(c+2105,"VX_cache cache_dram_req_arb dram_fill_arb sel_bank grant_valid", false,-1); + vcdp->declBus(c+2185,"VX_cache cache_dram_req_arb dram_fill_arb sel_bank genblk2 grant_onehot_r", false,-1, 3,0); + vcdp->declBus(c+25081,"VX_cache cache_dram_req_arb dram_fill_arb sel_bank genblk2 priority_encoder N", false,-1, 31,0); + vcdp->declBus(c+2033,"VX_cache cache_dram_req_arb dram_fill_arb sel_bank genblk2 priority_encoder data_in", false,-1, 3,0); + vcdp->declBus(c+2097,"VX_cache cache_dram_req_arb dram_fill_arb sel_bank genblk2 priority_encoder data_out", false,-1, 1,0); + vcdp->declBit(c+2105,"VX_cache cache_dram_req_arb dram_fill_arb sel_bank genblk2 priority_encoder valid_out", false,-1); + vcdp->declBus(c+2193,"VX_cache cache_dram_req_arb dram_fill_arb sel_bank genblk2 priority_encoder i", false,-1, 31,0); + vcdp->declBus(c+25081,"VX_cache cache_dram_req_arb sel_dwb N", false,-1, 31,0); + vcdp->declBit(c+24489,"VX_cache cache_dram_req_arb sel_dwb clk", false,-1); + vcdp->declBit(c+24497,"VX_cache cache_dram_req_arb sel_dwb reset", false,-1); + vcdp->declBus(c+1241,"VX_cache cache_dram_req_arb sel_dwb requests", false,-1, 3,0); + vcdp->declBus(c+1961,"VX_cache cache_dram_req_arb sel_dwb grant_index", false,-1, 1,0); + vcdp->declBus(c+2201,"VX_cache cache_dram_req_arb sel_dwb grant_onehot", false,-1, 3,0); + vcdp->declBit(c+1921,"VX_cache cache_dram_req_arb sel_dwb grant_valid", false,-1); + vcdp->declBus(c+2201,"VX_cache cache_dram_req_arb sel_dwb genblk2 grant_onehot_r", false,-1, 3,0); + vcdp->declBus(c+25081,"VX_cache cache_dram_req_arb sel_dwb genblk2 priority_encoder N", false,-1, 31,0); + vcdp->declBus(c+1241,"VX_cache cache_dram_req_arb sel_dwb genblk2 priority_encoder data_in", false,-1, 3,0); + vcdp->declBus(c+1961,"VX_cache cache_dram_req_arb sel_dwb genblk2 priority_encoder data_out", false,-1, 1,0); + vcdp->declBit(c+1921,"VX_cache cache_dram_req_arb sel_dwb genblk2 priority_encoder valid_out", false,-1); + vcdp->declBus(c+2209,"VX_cache cache_dram_req_arb sel_dwb genblk2 priority_encoder i", false,-1, 31,0); + vcdp->declBus(c+25081,"VX_cache cache_core_rsp_merge NUM_BANKS", false,-1, 31,0); + vcdp->declBus(c+25081,"VX_cache cache_core_rsp_merge WORD_SIZE", false,-1, 31,0); + vcdp->declBus(c+25081,"VX_cache cache_core_rsp_merge NUM_REQUESTS", false,-1, 31,0); + vcdp->declBus(c+25097,"VX_cache cache_core_rsp_merge CORE_TAG_WIDTH", false,-1, 31,0); + vcdp->declBus(c+25105,"VX_cache cache_core_rsp_merge CORE_TAG_ID_BITS", false,-1, 31,0); + vcdp->declBit(c+24489,"VX_cache cache_core_rsp_merge clk", false,-1); + vcdp->declBit(c+24497,"VX_cache cache_core_rsp_merge reset", false,-1); + vcdp->declBus(c+1105,"VX_cache cache_core_rsp_merge per_bank_core_rsp_tid", false,-1, 7,0); + vcdp->declBus(c+1097,"VX_cache cache_core_rsp_merge per_bank_core_rsp_valid", false,-1, 3,0); + vcdp->declArray(c+1113,"VX_cache cache_core_rsp_merge per_bank_core_rsp_data", false,-1, 127,0); + vcdp->declArray(c+1145,"VX_cache cache_core_rsp_merge per_bank_core_rsp_tag", false,-1, 167,0); + vcdp->declBus(c+9,"VX_cache cache_core_rsp_merge per_bank_core_rsp_ready", false,-1, 3,0); + vcdp->declBus(c+24617,"VX_cache cache_core_rsp_merge core_rsp_valid", false,-1, 3,0); + vcdp->declArray(c+2217,"VX_cache cache_core_rsp_merge core_rsp_data", false,-1, 127,0); + vcdp->declQuad(c+2249,"VX_cache cache_core_rsp_merge core_rsp_tag", false,-1, 41,0); + vcdp->declBit(c+24673,"VX_cache cache_core_rsp_merge core_rsp_ready", false,-1); + vcdp->declBus(c+2265,"VX_cache cache_core_rsp_merge main_bank_index", false,-1, 1,0); + vcdp->declBus(c+2273,"VX_cache cache_core_rsp_merge per_bank_core_rsp_pop_unqual", false,-1, 3,0); + vcdp->declBus(c+25129,"VX_cache cache_core_rsp_merge i", false,-1, 31,0); + vcdp->declBus(c+25081,"VX_cache cache_core_rsp_merge sel_bank N", false,-1, 31,0); + vcdp->declBit(c+24489,"VX_cache cache_core_rsp_merge sel_bank clk", false,-1); + vcdp->declBit(c+24497,"VX_cache cache_core_rsp_merge sel_bank reset", false,-1); + vcdp->declBus(c+1097,"VX_cache cache_core_rsp_merge sel_bank requests", false,-1, 3,0); + vcdp->declBus(c+2265,"VX_cache cache_core_rsp_merge sel_bank grant_index", false,-1, 1,0); + vcdp->declBus(c+2281,"VX_cache cache_core_rsp_merge sel_bank grant_onehot", false,-1, 3,0); + vcdp->declBit(c+2289,"VX_cache cache_core_rsp_merge sel_bank grant_valid", false,-1); + vcdp->declBus(c+10577,"VX_cache cache_core_rsp_merge sel_bank genblk2 requests_use", false,-1, 3,0); + vcdp->declBus(c+2297,"VX_cache cache_core_rsp_merge sel_bank genblk2 update_value", false,-1, 3,0); + vcdp->declBus(c+2305,"VX_cache cache_core_rsp_merge sel_bank genblk2 late_value", false,-1, 3,0); + vcdp->declBit(c+10585,"VX_cache cache_core_rsp_merge sel_bank genblk2 refill", false,-1); + vcdp->declBus(c+1097,"VX_cache cache_core_rsp_merge sel_bank genblk2 refill_value", false,-1, 3,0); + vcdp->declBus(c+10593,"VX_cache cache_core_rsp_merge sel_bank genblk2 refill_original", false,-1, 3,0); + vcdp->declBus(c+2281,"VX_cache cache_core_rsp_merge sel_bank genblk2 grant_onehot_r", false,-1, 3,0); + vcdp->declBus(c+25081,"VX_cache cache_core_rsp_merge sel_bank genblk2 priority_encoder N", false,-1, 31,0); + vcdp->declBus(c+10577,"VX_cache cache_core_rsp_merge sel_bank genblk2 priority_encoder data_in", false,-1, 3,0); + vcdp->declBus(c+2265,"VX_cache cache_core_rsp_merge sel_bank genblk2 priority_encoder data_out", false,-1, 1,0); + vcdp->declBit(c+2289,"VX_cache cache_core_rsp_merge sel_bank genblk2 priority_encoder valid_out", false,-1); + vcdp->declBus(c+2313,"VX_cache cache_core_rsp_merge sel_bank genblk2 priority_encoder i", false,-1, 31,0); + vcdp->declBus(c+25081,"VX_cache snp_rsp_arb NUM_BANKS", false,-1, 31,0); + vcdp->declBus(c+25073,"VX_cache snp_rsp_arb BANK_LINE_SIZE", false,-1, 31,0); + vcdp->declBus(c+25113,"VX_cache snp_rsp_arb SNP_REQ_TAG_WIDTH", false,-1, 31,0); + vcdp->declBit(c+24489,"VX_cache snp_rsp_arb clk", false,-1); + vcdp->declBit(c+24497,"VX_cache snp_rsp_arb reset", false,-1); + vcdp->declBus(c+1433,"VX_cache snp_rsp_arb per_bank_snp_rsp_valid", false,-1, 3,0); + vcdp->declArray(c+1441,"VX_cache snp_rsp_arb per_bank_snp_rsp_tag", false,-1, 111,0); + vcdp->declBus(c+25,"VX_cache snp_rsp_arb per_bank_snp_rsp_ready", false,-1, 3,0); + vcdp->declBit(c+24857,"VX_cache snp_rsp_arb snp_rsp_valid", false,-1); + vcdp->declBus(c+24865,"VX_cache snp_rsp_arb snp_rsp_tag", false,-1, 27,0); + vcdp->declBit(c+24873,"VX_cache snp_rsp_arb snp_rsp_ready", false,-1); + vcdp->declBus(c+2321,"VX_cache snp_rsp_arb fsq_bank", false,-1, 1,0); + vcdp->declBit(c+2329,"VX_cache snp_rsp_arb fsq_valid", false,-1); + vcdp->declBus(c+25081,"VX_cache snp_rsp_arb sel_ffsq N", false,-1, 31,0); + vcdp->declBit(c+24489,"VX_cache snp_rsp_arb sel_ffsq clk", false,-1); + vcdp->declBit(c+24497,"VX_cache snp_rsp_arb sel_ffsq reset", false,-1); + vcdp->declBus(c+1433,"VX_cache snp_rsp_arb sel_ffsq requests", false,-1, 3,0); + vcdp->declBus(c+2321,"VX_cache snp_rsp_arb sel_ffsq grant_index", false,-1, 1,0); + vcdp->declBus(c+2337,"VX_cache snp_rsp_arb sel_ffsq grant_onehot", false,-1, 3,0); + vcdp->declBit(c+2329,"VX_cache snp_rsp_arb sel_ffsq grant_valid", false,-1); + vcdp->declBus(c+2337,"VX_cache snp_rsp_arb sel_ffsq genblk2 grant_onehot_r", false,-1, 3,0); + vcdp->declBus(c+25081,"VX_cache snp_rsp_arb sel_ffsq genblk2 priority_encoder N", false,-1, 31,0); + vcdp->declBus(c+1433,"VX_cache snp_rsp_arb sel_ffsq genblk2 priority_encoder data_in", false,-1, 3,0); + vcdp->declBus(c+2321,"VX_cache snp_rsp_arb sel_ffsq genblk2 priority_encoder data_out", false,-1, 1,0); + vcdp->declBit(c+2329,"VX_cache snp_rsp_arb sel_ffsq genblk2 priority_encoder valid_out", false,-1); + vcdp->declBus(c+2345,"VX_cache snp_rsp_arb sel_ffsq genblk2 priority_encoder i", false,-1, 31,0); + vcdp->declBus(c+25057,"VX_cache genblk5[0] bank CACHE_ID", false,-1, 31,0); + vcdp->declBus(c+25153,"VX_cache genblk5[0] bank BANK_ID", false,-1, 31,0); + vcdp->declBus(c+25065,"VX_cache genblk5[0] bank CACHE_SIZE", false,-1, 31,0); + vcdp->declBus(c+25073,"VX_cache genblk5[0] bank BANK_LINE_SIZE", false,-1, 31,0); + vcdp->declBus(c+25081,"VX_cache genblk5[0] bank NUM_BANKS", false,-1, 31,0); + vcdp->declBus(c+25081,"VX_cache genblk5[0] bank WORD_SIZE", false,-1, 31,0); + vcdp->declBus(c+25081,"VX_cache genblk5[0] bank NUM_REQUESTS", false,-1, 31,0); + vcdp->declBus(c+25089,"VX_cache genblk5[0] bank STAGE_1_CYCLES", false,-1, 31,0); + vcdp->declBus(c+25081,"VX_cache genblk5[0] bank CREQ_SIZE", false,-1, 31,0); + vcdp->declBus(c+25073,"VX_cache genblk5[0] bank MRVQ_SIZE", false,-1, 31,0); + vcdp->declBus(c+25073,"VX_cache genblk5[0] bank DFPQ_SIZE", false,-1, 31,0); + vcdp->declBus(c+25073,"VX_cache genblk5[0] bank SNRQ_SIZE", false,-1, 31,0); + vcdp->declBus(c+25081,"VX_cache genblk5[0] bank CWBQ_SIZE", false,-1, 31,0); + vcdp->declBus(c+25081,"VX_cache genblk5[0] bank DWBQ_SIZE", false,-1, 31,0); + vcdp->declBus(c+25081,"VX_cache genblk5[0] bank DFQQ_SIZE", false,-1, 31,0); + vcdp->declBus(c+25089,"VX_cache genblk5[0] bank WRITE_ENABLE", false,-1, 31,0); + vcdp->declBus(c+25089,"VX_cache genblk5[0] bank DRAM_ENABLE", false,-1, 31,0); + vcdp->declBus(c+25057,"VX_cache genblk5[0] bank SNOOP_FORWARDING", false,-1, 31,0); + vcdp->declBus(c+25097,"VX_cache genblk5[0] bank CORE_TAG_WIDTH", false,-1, 31,0); + vcdp->declBus(c+25105,"VX_cache genblk5[0] bank CORE_TAG_ID_BITS", false,-1, 31,0); + vcdp->declBus(c+25113,"VX_cache genblk5[0] bank SNP_REQ_TAG_WIDTH", false,-1, 31,0); + vcdp->declBit(c+24489,"VX_cache genblk5[0] bank clk", false,-1); + vcdp->declBit(c+24497,"VX_cache genblk5[0] bank reset", false,-1); + vcdp->declBus(c+33,"VX_cache genblk5[0] bank core_req_valid", false,-1, 3,0); + vcdp->declBus(c+24513,"VX_cache genblk5[0] bank core_req_rw", false,-1, 3,0); + vcdp->declBus(c+24521,"VX_cache genblk5[0] bank core_req_byteen", false,-1, 15,0); + vcdp->declArray(c+24529,"VX_cache genblk5[0] bank core_req_addr", false,-1, 119,0); + vcdp->declArray(c+24561,"VX_cache genblk5[0] bank core_req_data", false,-1, 127,0); + vcdp->declQuad(c+24593,"VX_cache genblk5[0] bank core_req_tag", false,-1, 41,0); + vcdp->declBit(c+10105,"VX_cache genblk5[0] bank core_req_ready", false,-1); + vcdp->declBit(c+10073,"VX_cache genblk5[0] bank core_rsp_valid", false,-1); + vcdp->declBus(c+1473,"VX_cache genblk5[0] bank core_rsp_tid", false,-1, 1,0); + vcdp->declBus(c+1481,"VX_cache genblk5[0] bank core_rsp_data", false,-1, 31,0); + vcdp->declQuad(c+1489,"VX_cache genblk5[0] bank core_rsp_tag", false,-1, 41,0); + vcdp->declBit(c+41,"VX_cache genblk5[0] bank core_rsp_ready", false,-1); + vcdp->declBit(c+1505,"VX_cache genblk5[0] bank dram_fill_req_valid", false,-1); + vcdp->declBus(c+10089,"VX_cache genblk5[0] bank dram_fill_req_addr", false,-1, 25,0); + vcdp->declBit(c+10065,"VX_cache genblk5[0] bank dram_fill_req_ready", false,-1); + vcdp->declBit(c+24961,"VX_cache genblk5[0] bank dram_fill_rsp_valid", false,-1); + vcdp->declArray(c+24769,"VX_cache genblk5[0] bank dram_fill_rsp_data", false,-1, 127,0); + vcdp->declBus(c+24969,"VX_cache genblk5[0] bank dram_fill_rsp_addr", false,-1, 25,0); + vcdp->declBit(c+10081,"VX_cache genblk5[0] bank dram_fill_rsp_ready", false,-1); + vcdp->declBit(c+1513,"VX_cache genblk5[0] bank dram_wb_req_valid", false,-1); + vcdp->declBus(c+1521,"VX_cache genblk5[0] bank dram_wb_req_byteen", false,-1, 15,0); + vcdp->declBus(c+1529,"VX_cache genblk5[0] bank dram_wb_req_addr", false,-1, 25,0); + vcdp->declArray(c+1537,"VX_cache genblk5[0] bank dram_wb_req_data", false,-1, 127,0); + vcdp->declBit(c+49,"VX_cache genblk5[0] bank dram_wb_req_ready", false,-1); + vcdp->declBit(c+24977,"VX_cache genblk5[0] bank snp_req_valid", false,-1); + vcdp->declBus(c+24985,"VX_cache genblk5[0] bank snp_req_addr", false,-1, 25,0); + vcdp->declBit(c+24833,"VX_cache genblk5[0] bank snp_req_invalidate", false,-1); + vcdp->declBus(c+24841,"VX_cache genblk5[0] bank snp_req_tag", false,-1, 27,0); + vcdp->declBit(c+10097,"VX_cache genblk5[0] bank snp_req_ready", false,-1); + vcdp->declBit(c+1569,"VX_cache genblk5[0] bank snp_rsp_valid", false,-1); + vcdp->declBus(c+1577,"VX_cache genblk5[0] bank snp_rsp_tag", false,-1, 27,0); + vcdp->declBit(c+57,"VX_cache genblk5[0] bank snp_rsp_ready", false,-1); + vcdp->declBit(c+2353,"VX_cache genblk5[0] bank snrq_pop", false,-1); + vcdp->declBit(c+10601,"VX_cache genblk5[0] bank snrq_empty", false,-1); + vcdp->declBit(c+10609,"VX_cache genblk5[0] bank snrq_full", false,-1); + vcdp->declBus(c+2361,"VX_cache genblk5[0] bank snrq_addr_st0", false,-1, 25,0); + vcdp->declBit(c+2369,"VX_cache genblk5[0] bank snrq_invalidate_st0", false,-1); + vcdp->declBus(c+2377,"VX_cache genblk5[0] bank snrq_tag_st0", false,-1, 27,0); + vcdp->declBit(c+2385,"VX_cache genblk5[0] bank dfpq_pop", false,-1); + vcdp->declBit(c+10617,"VX_cache genblk5[0] bank dfpq_empty", false,-1); + vcdp->declBit(c+10625,"VX_cache genblk5[0] bank dfpq_full", false,-1); + vcdp->declBus(c+2393,"VX_cache genblk5[0] bank dfpq_addr_st0", false,-1, 25,0); + vcdp->declArray(c+2401,"VX_cache genblk5[0] bank dfpq_filldata_st0", false,-1, 127,0); + vcdp->declBit(c+2433,"VX_cache genblk5[0] bank reqq_pop", false,-1); + vcdp->declBit(c+961,"VX_cache genblk5[0] bank reqq_push", false,-1); + vcdp->declBit(c+2441,"VX_cache genblk5[0] bank reqq_empty", false,-1); + vcdp->declBit(c+10633,"VX_cache genblk5[0] bank reqq_full", false,-1); + vcdp->declBit(c+2449,"VX_cache genblk5[0] bank reqq_req_st0", false,-1); + vcdp->declBus(c+2457,"VX_cache genblk5[0] bank reqq_req_tid_st0", false,-1, 1,0); + vcdp->declBit(c+2465,"VX_cache genblk5[0] bank reqq_req_rw_st0", false,-1); + vcdp->declBus(c+2473,"VX_cache genblk5[0] bank reqq_req_byteen_st0", false,-1, 3,0); + vcdp->declBus(c+2481,"VX_cache genblk5[0] bank reqq_req_addr_st0", false,-1, 29,0); + vcdp->declBus(c+2489,"VX_cache genblk5[0] bank reqq_req_writeword_st0", false,-1, 31,0); + vcdp->declQuad(c+10641,"VX_cache genblk5[0] bank reqq_req_tag_st0", false,-1, 41,0); + vcdp->declBit(c+2497,"VX_cache genblk5[0] bank mrvq_pop", false,-1); + vcdp->declBit(c+10657,"VX_cache genblk5[0] bank mrvq_full", false,-1); + vcdp->declBit(c+10665,"VX_cache genblk5[0] bank mrvq_stop", false,-1); + vcdp->declBit(c+2505,"VX_cache genblk5[0] bank mrvq_valid_st0", false,-1); + vcdp->declBus(c+10673,"VX_cache genblk5[0] bank mrvq_tid_st0", false,-1, 1,0); + vcdp->declBus(c+10681,"VX_cache genblk5[0] bank mrvq_addr_st0", false,-1, 25,0); + vcdp->declBus(c+10689,"VX_cache genblk5[0] bank mrvq_wsel_st0", false,-1, 1,0); + vcdp->declBus(c+10697,"VX_cache genblk5[0] bank mrvq_writeword_st0", false,-1, 31,0); + vcdp->declQuad(c+10705,"VX_cache genblk5[0] bank mrvq_tag_st0", false,-1, 41,0); + vcdp->declBit(c+2513,"VX_cache genblk5[0] bank mrvq_rw_st0", false,-1); + vcdp->declBus(c+10721,"VX_cache genblk5[0] bank mrvq_byteen_st0", false,-1, 3,0); + vcdp->declBit(c+10729,"VX_cache genblk5[0] bank mrvq_is_snp_st0", false,-1); + vcdp->declBit(c+10737,"VX_cache genblk5[0] bank mrvq_snp_invalidate_st0", false,-1); + vcdp->declBit(c+2521,"VX_cache genblk5[0] bank mrvq_pending_hazard_st1e", false,-1); + vcdp->declBit(c+2529,"VX_cache genblk5[0] bank st2_pending_hazard_st1e", false,-1); + vcdp->declBit(c+2537,"VX_cache genblk5[0] bank force_request_miss_st1e", false,-1); + vcdp->declBus(c+10745,"VX_cache genblk5[0] bank miss_add_tid", false,-1, 1,0); + vcdp->declQuad(c+10753,"VX_cache genblk5[0] bank miss_add_tag", false,-1, 41,0); + vcdp->declBit(c+10769,"VX_cache genblk5[0] bank miss_add_rw", false,-1); + vcdp->declBus(c+10777,"VX_cache genblk5[0] bank miss_add_byteen", false,-1, 3,0); + vcdp->declBus(c+10089,"VX_cache genblk5[0] bank addr_st2", false,-1, 25,0); + vcdp->declBit(c+10785,"VX_cache genblk5[0] bank is_fill_st2", false,-1); + vcdp->declBit(c+2545,"VX_cache genblk5[0] bank recover_mrvq_state_st2", false,-1); + vcdp->declBit(c+2553,"VX_cache genblk5[0] bank mrvq_push_stall", false,-1); + vcdp->declBit(c+2561,"VX_cache genblk5[0] bank cwbq_push_stall", false,-1); + vcdp->declBit(c+2569,"VX_cache genblk5[0] bank dwbq_push_stall", false,-1); + vcdp->declBit(c+2577,"VX_cache genblk5[0] bank dram_fill_req_stall", false,-1); + vcdp->declBit(c+2585,"VX_cache genblk5[0] bank stall_bank_pipe", false,-1); + vcdp->declBit(c+2593,"VX_cache genblk5[0] bank is_fill_in_pipe", false,-1); + {int i; for (i=0; i<1; i++) { + vcdp->declBit(c+2601+i*1,"VX_cache genblk5[0] bank is_fill_st1", true,(i+0));}} + {int i; for (i=0; i<1; i++) { + vcdp->declBit(c+2609+i*1,"VX_cache genblk5[0] bank going_to_write_st1", true,(i+0));}} + vcdp->declBus(c+25161,"VX_cache genblk5[0] bank j", false,-1, 31,0); + vcdp->declBit(c+2505,"VX_cache genblk5[0] bank mrvq_pop_unqual", false,-1); + vcdp->declBit(c+2617,"VX_cache genblk5[0] bank dfpq_pop_unqual", false,-1); + vcdp->declBit(c+2625,"VX_cache genblk5[0] bank reqq_pop_unqual", false,-1); + vcdp->declBit(c+2633,"VX_cache genblk5[0] bank snrq_pop_unqual", false,-1); + vcdp->declBit(c+2617,"VX_cache genblk5[0] bank qual_is_fill_st0", false,-1); + vcdp->declBit(c+2641,"VX_cache genblk5[0] bank qual_valid_st0", false,-1); + vcdp->declBus(c+2649,"VX_cache genblk5[0] bank qual_addr_st0", false,-1, 25,0); + vcdp->declBus(c+2657,"VX_cache genblk5[0] bank qual_wsel_st0", false,-1, 1,0); + vcdp->declBit(c+2505,"VX_cache genblk5[0] bank qual_is_mrvq_st0", false,-1); + vcdp->declBus(c+2665,"VX_cache genblk5[0] bank qual_writeword_st0", false,-1, 31,0); + vcdp->declArray(c+2673,"VX_cache genblk5[0] bank qual_writedata_st0", false,-1, 127,0); + vcdp->declQuad(c+2705,"VX_cache genblk5[0] bank qual_inst_meta_st0", false,-1, 48,0); + vcdp->declBit(c+2721,"VX_cache genblk5[0] bank qual_going_to_write_st0", false,-1); + vcdp->declBit(c+2729,"VX_cache genblk5[0] bank qual_is_snp_st0", false,-1); + vcdp->declBit(c+2737,"VX_cache genblk5[0] bank qual_snp_invalidate_st0", false,-1); + {int i; for (i=0; i<1; i++) { + vcdp->declBit(c+2745+i*1,"VX_cache genblk5[0] bank valid_st1", true,(i+0));}} + {int i; for (i=0; i<1; i++) { + vcdp->declBus(c+2753+i*1,"VX_cache genblk5[0] bank addr_st1", true,(i+0), 25,0);}} + {int i; for (i=0; i<1; i++) { + vcdp->declBus(c+2761+i*1,"VX_cache genblk5[0] bank wsel_st1", true,(i+0), 1,0);}} + {int i; for (i=0; i<1; i++) { + vcdp->declBus(c+2769+i*1,"VX_cache genblk5[0] bank writeword_st1", true,(i+0), 31,0);}} + {int i; for (i=0; i<1; i++) { + vcdp->declQuad(c+2777+i*2,"VX_cache genblk5[0] bank inst_meta_st1", true,(i+0), 48,0);}} + {int i; for (i=0; i<1; i++) { + vcdp->declArray(c+2793+i*4,"VX_cache genblk5[0] bank writedata_st1", true,(i+0), 127,0);}} + {int i; for (i=0; i<1; i++) { + vcdp->declBit(c+2825+i*1,"VX_cache genblk5[0] bank is_snp_st1", true,(i+0));}} + {int i; for (i=0; i<1; i++) { + vcdp->declBit(c+2833+i*1,"VX_cache genblk5[0] bank snp_invalidate_st1", true,(i+0));}} + {int i; for (i=0; i<1; i++) { + vcdp->declBit(c+2841+i*1,"VX_cache genblk5[0] bank is_mrvq_st1", true,(i+0));}} + vcdp->declBus(c+2849,"VX_cache genblk5[0] bank readword_st1e", false,-1, 31,0); + vcdp->declArray(c+2857,"VX_cache genblk5[0] bank readdata_st1e", false,-1, 127,0); + vcdp->declBus(c+2889,"VX_cache genblk5[0] bank readtag_st1e", false,-1, 19,0); + vcdp->declBit(c+2897,"VX_cache genblk5[0] bank miss_st1e", false,-1); + vcdp->declBit(c+2905,"VX_cache genblk5[0] bank dirty_st1e", false,-1); + vcdp->declBus(c+2913,"VX_cache genblk5[0] bank dirtyb_st1e", false,-1, 15,0); + vcdp->declQuad(c+2921,"VX_cache genblk5[0] bank tag_st1e", false,-1, 41,0); + vcdp->declBus(c+2937,"VX_cache genblk5[0] bank tid_st1e", false,-1, 1,0); + vcdp->declBit(c+2945,"VX_cache genblk5[0] bank mem_rw_st1e", false,-1); + vcdp->declBus(c+2953,"VX_cache genblk5[0] bank mem_byteen_st1e", false,-1, 3,0); + vcdp->declBit(c+2961,"VX_cache genblk5[0] bank fill_saw_dirty_st1e", false,-1); + vcdp->declBit(c+2969,"VX_cache genblk5[0] bank is_snp_st1e", false,-1); + vcdp->declBit(c+2977,"VX_cache genblk5[0] bank snp_invalidate_st1e", false,-1); + vcdp->declBit(c+2985,"VX_cache genblk5[0] bank snp_to_mrvq_st1e", false,-1); + vcdp->declBit(c+2993,"VX_cache genblk5[0] bank mrvq_init_ready_state_st1e", false,-1); + vcdp->declBit(c+3001,"VX_cache genblk5[0] bank miss_add_because_miss", false,-1); + vcdp->declBit(c+3009,"VX_cache genblk5[0] bank valid_st1e", false,-1); + vcdp->declBit(c+3017,"VX_cache genblk5[0] bank is_mrvq_st1e", false,-1); + vcdp->declBit(c+3025,"VX_cache genblk5[0] bank mrvq_recover_ready_state_st1e", false,-1); + vcdp->declBus(c+3033,"VX_cache genblk5[0] bank addr_st1e", false,-1, 25,0); + vcdp->declBit(c+3041,"VX_cache genblk5[0] bank qual_valid_st1e_2", false,-1); + vcdp->declBit(c+3017,"VX_cache genblk5[0] bank is_mrvq_st1e_st2", false,-1); + vcdp->declBit(c+10793,"VX_cache genblk5[0] bank valid_st2", false,-1); + vcdp->declBus(c+10801,"VX_cache genblk5[0] bank wsel_st2", false,-1, 1,0); + vcdp->declBus(c+10809,"VX_cache genblk5[0] bank writeword_st2", false,-1, 31,0); + vcdp->declBus(c+10817,"VX_cache genblk5[0] bank readword_st2", false,-1, 31,0); + vcdp->declArray(c+10825,"VX_cache genblk5[0] bank readdata_st2", false,-1, 127,0); + vcdp->declBit(c+10857,"VX_cache genblk5[0] bank miss_st2", false,-1); + vcdp->declBit(c+10865,"VX_cache genblk5[0] bank dirty_st2", false,-1); + vcdp->declBus(c+10873,"VX_cache genblk5[0] bank dirtyb_st2", false,-1, 15,0); + vcdp->declQuad(c+10881,"VX_cache genblk5[0] bank inst_meta_st2", false,-1, 48,0); + vcdp->declBus(c+10897,"VX_cache genblk5[0] bank readtag_st2", false,-1, 19,0); + vcdp->declBit(c+10905,"VX_cache genblk5[0] bank fill_saw_dirty_st2", false,-1); + vcdp->declBit(c+10913,"VX_cache genblk5[0] bank is_snp_st2", false,-1); + vcdp->declBit(c+10921,"VX_cache genblk5[0] bank snp_invalidate_st2", false,-1); + vcdp->declBit(c+10929,"VX_cache genblk5[0] bank snp_to_mrvq_st2", false,-1); + vcdp->declBit(c+10937,"VX_cache genblk5[0] bank is_mrvq_st2", false,-1); + vcdp->declBit(c+3049,"VX_cache genblk5[0] bank mrvq_init_ready_state_st2", false,-1); + vcdp->declBit(c+10945,"VX_cache genblk5[0] bank mrvq_recover_ready_state_st2", false,-1); + vcdp->declBit(c+10953,"VX_cache genblk5[0] bank mrvq_init_ready_state_unqual_st2", false,-1); + vcdp->declBit(c+3057,"VX_cache genblk5[0] bank mrvq_init_ready_state_hazard_st0_st1", false,-1); + vcdp->declBit(c+3065,"VX_cache genblk5[0] bank mrvq_init_ready_state_hazard_st1e_st1", false,-1); + vcdp->declBit(c+10929,"VX_cache genblk5[0] bank miss_add_because_pending", false,-1); + vcdp->declBit(c+3073,"VX_cache genblk5[0] bank miss_add_unqual", false,-1); + vcdp->declBit(c+3081,"VX_cache genblk5[0] bank miss_add", false,-1); + vcdp->declBus(c+10089,"VX_cache genblk5[0] bank miss_add_addr", false,-1, 25,0); + vcdp->declBus(c+10801,"VX_cache genblk5[0] bank miss_add_wsel", false,-1, 1,0); + vcdp->declBus(c+10809,"VX_cache genblk5[0] bank miss_add_data", false,-1, 31,0); + vcdp->declBit(c+10913,"VX_cache genblk5[0] bank miss_add_is_snp", false,-1); + vcdp->declBit(c+10921,"VX_cache genblk5[0] bank miss_add_snp_invalidate", false,-1); + vcdp->declBit(c+3089,"VX_cache genblk5[0] bank miss_add_is_mrvq", false,-1); + vcdp->declBit(c+3097,"VX_cache genblk5[0] bank cwbq_push", false,-1); + vcdp->declBit(c+969,"VX_cache genblk5[0] bank cwbq_pop", false,-1); + vcdp->declBit(c+10961,"VX_cache genblk5[0] bank cwbq_empty", false,-1); + vcdp->declBit(c+10969,"VX_cache genblk5[0] bank cwbq_full", false,-1); + vcdp->declBit(c+3105,"VX_cache genblk5[0] bank cwbq_push_unqual", false,-1); + vcdp->declBus(c+10817,"VX_cache genblk5[0] bank cwbq_data", false,-1, 31,0); + vcdp->declBus(c+10745,"VX_cache genblk5[0] bank cwbq_tid", false,-1, 1,0); + vcdp->declQuad(c+10753,"VX_cache genblk5[0] bank cwbq_tag", false,-1, 41,0); + vcdp->declBit(c+3073,"VX_cache genblk5[0] bank dram_fill_req_fast", false,-1); + vcdp->declBit(c+3113,"VX_cache genblk5[0] bank dram_fill_req_unqual", false,-1); + vcdp->declBit(c+3121,"VX_cache genblk5[0] bank dwbq_push", false,-1); + vcdp->declBit(c+977,"VX_cache genblk5[0] bank dwbq_pop", false,-1); + vcdp->declBit(c+10977,"VX_cache genblk5[0] bank dwbq_empty", false,-1); + vcdp->declBit(c+10985,"VX_cache genblk5[0] bank dwbq_full", false,-1); + vcdp->declBit(c+3129,"VX_cache genblk5[0] bank dwbq_is_dwb_in", false,-1); + vcdp->declBit(c+3137,"VX_cache genblk5[0] bank dwbq_is_snp_in", false,-1); + vcdp->declBit(c+3145,"VX_cache genblk5[0] bank dwbq_is_dwb_out", false,-1); + vcdp->declBit(c+3153,"VX_cache genblk5[0] bank dwbq_is_snp_out", false,-1); + vcdp->declBit(c+3161,"VX_cache genblk5[0] bank dwbq_push_unqual", false,-1); + vcdp->declBus(c+10993,"VX_cache genblk5[0] bank dwbq_req_addr", false,-1, 25,0); + vcdp->declBus(c+11001,"VX_cache genblk5[0] bank snrq_tag_st2", false,-1, 27,0); + vcdp->declBit(c+185,"VX_cache genblk5[0] bank dram_wb_req_fire", false,-1); + vcdp->declBit(c+193,"VX_cache genblk5[0] bank snp_rsp_fire", false,-1); + vcdp->declBit(c+11009,"VX_cache genblk5[0] bank dwbq_dual_valid_sel", false,-1); + vcdp->declBus(c+25169,"VX_cache genblk5[0] bank snp_req_queue DATAW", false,-1, 31,0); + vcdp->declBus(c+25073,"VX_cache genblk5[0] bank snp_req_queue SIZE", false,-1, 31,0); + vcdp->declBus(c+25089,"VX_cache genblk5[0] bank snp_req_queue BUFFERED_OUTPUT", false,-1, 31,0); + vcdp->declBit(c+24489,"VX_cache genblk5[0] bank snp_req_queue clk", false,-1); + vcdp->declBit(c+24497,"VX_cache genblk5[0] bank snp_req_queue reset", false,-1); + vcdp->declBit(c+24977,"VX_cache genblk5[0] bank snp_req_queue push", false,-1); + vcdp->declBit(c+2353,"VX_cache genblk5[0] bank snp_req_queue pop", false,-1); + vcdp->declQuad(c+201,"VX_cache genblk5[0] bank snp_req_queue data_in", false,-1, 54,0); + vcdp->declQuad(c+3169,"VX_cache genblk5[0] bank snp_req_queue data_out", false,-1, 54,0); + vcdp->declBit(c+10601,"VX_cache genblk5[0] bank snp_req_queue empty", false,-1); + vcdp->declBit(c+10609,"VX_cache genblk5[0] bank snp_req_queue full", false,-1); + vcdp->declBus(c+11017,"VX_cache genblk5[0] bank snp_req_queue size", false,-1, 4,0); + vcdp->declBus(c+11017,"VX_cache genblk5[0] bank snp_req_queue size_r", false,-1, 4,0); + vcdp->declBit(c+3185,"VX_cache genblk5[0] bank snp_req_queue reading", false,-1); + vcdp->declBit(c+217,"VX_cache genblk5[0] bank snp_req_queue writing", false,-1); + {int i; for (i=0; i<16; i++) { + vcdp->declQuad(c+11025+i*2,"VX_cache genblk5[0] bank snp_req_queue genblk3 data", true,(i+0), 54,0);}} + vcdp->declQuad(c+11281,"VX_cache genblk5[0] bank snp_req_queue genblk3 genblk2 head_r", false,-1, 54,0); + vcdp->declQuad(c+11297,"VX_cache genblk5[0] bank snp_req_queue genblk3 genblk2 curr_r", false,-1, 54,0); + vcdp->declBus(c+11313,"VX_cache genblk5[0] bank snp_req_queue genblk3 genblk2 wr_ptr_r", false,-1, 3,0); + vcdp->declBus(c+11321,"VX_cache genblk5[0] bank snp_req_queue genblk3 genblk2 rd_ptr_r", false,-1, 3,0); + vcdp->declBus(c+11329,"VX_cache genblk5[0] bank snp_req_queue genblk3 genblk2 rd_ptr_next_r", false,-1, 3,0); + vcdp->declBit(c+10601,"VX_cache genblk5[0] bank snp_req_queue genblk3 genblk2 empty_r", false,-1); + vcdp->declBit(c+10609,"VX_cache genblk5[0] bank snp_req_queue genblk3 genblk2 full_r", false,-1); + vcdp->declBit(c+11337,"VX_cache genblk5[0] bank snp_req_queue genblk3 genblk2 bypass_r", false,-1); + vcdp->declBus(c+25177,"VX_cache genblk5[0] bank dfp_queue DATAW", false,-1, 31,0); + vcdp->declBus(c+25073,"VX_cache genblk5[0] bank dfp_queue SIZE", false,-1, 31,0); + vcdp->declBus(c+25089,"VX_cache genblk5[0] bank dfp_queue BUFFERED_OUTPUT", false,-1, 31,0); + vcdp->declBit(c+24489,"VX_cache genblk5[0] bank dfp_queue clk", false,-1); + vcdp->declBit(c+24497,"VX_cache genblk5[0] bank dfp_queue reset", false,-1); + vcdp->declBit(c+24961,"VX_cache genblk5[0] bank dfp_queue push", false,-1); + vcdp->declBit(c+2385,"VX_cache genblk5[0] bank dfp_queue pop", false,-1); + vcdp->declArray(c+225,"VX_cache genblk5[0] bank dfp_queue data_in", false,-1, 153,0); + vcdp->declArray(c+3193,"VX_cache genblk5[0] bank dfp_queue data_out", false,-1, 153,0); + vcdp->declBit(c+10617,"VX_cache genblk5[0] bank dfp_queue empty", false,-1); + vcdp->declBit(c+10625,"VX_cache genblk5[0] bank dfp_queue full", false,-1); + vcdp->declBus(c+11345,"VX_cache genblk5[0] bank dfp_queue size", false,-1, 4,0); + vcdp->declBus(c+11345,"VX_cache genblk5[0] bank dfp_queue size_r", false,-1, 4,0); + vcdp->declBit(c+3233,"VX_cache genblk5[0] bank dfp_queue reading", false,-1); + vcdp->declBit(c+265,"VX_cache genblk5[0] bank dfp_queue writing", false,-1); + {int i; for (i=0; i<16; i++) { + vcdp->declArray(c+11353+i*5,"VX_cache genblk5[0] bank dfp_queue genblk3 data", true,(i+0), 153,0);}} + vcdp->declArray(c+11993,"VX_cache genblk5[0] bank dfp_queue genblk3 genblk2 head_r", false,-1, 153,0); + vcdp->declArray(c+12033,"VX_cache genblk5[0] bank dfp_queue genblk3 genblk2 curr_r", false,-1, 153,0); + vcdp->declBus(c+12073,"VX_cache genblk5[0] bank dfp_queue genblk3 genblk2 wr_ptr_r", false,-1, 3,0); + vcdp->declBus(c+12081,"VX_cache genblk5[0] bank dfp_queue genblk3 genblk2 rd_ptr_r", false,-1, 3,0); + vcdp->declBus(c+12089,"VX_cache genblk5[0] bank dfp_queue genblk3 genblk2 rd_ptr_next_r", false,-1, 3,0); + vcdp->declBit(c+10617,"VX_cache genblk5[0] bank dfp_queue genblk3 genblk2 empty_r", false,-1); + vcdp->declBit(c+10625,"VX_cache genblk5[0] bank dfp_queue genblk3 genblk2 full_r", false,-1); + vcdp->declBit(c+12097,"VX_cache genblk5[0] bank dfp_queue genblk3 genblk2 bypass_r", false,-1); + vcdp->declBus(c+25081,"VX_cache genblk5[0] bank core_req_arb WORD_SIZE", false,-1, 31,0); + vcdp->declBus(c+25081,"VX_cache genblk5[0] bank core_req_arb NUM_REQUESTS", false,-1, 31,0); + vcdp->declBus(c+25081,"VX_cache genblk5[0] bank core_req_arb CREQ_SIZE", false,-1, 31,0); + vcdp->declBus(c+25097,"VX_cache genblk5[0] bank core_req_arb CORE_TAG_WIDTH", false,-1, 31,0); + vcdp->declBus(c+25105,"VX_cache genblk5[0] bank core_req_arb CORE_TAG_ID_BITS", false,-1, 31,0); + vcdp->declBit(c+24489,"VX_cache genblk5[0] bank core_req_arb clk", false,-1); + vcdp->declBit(c+24497,"VX_cache genblk5[0] bank core_req_arb reset", false,-1); + vcdp->declBit(c+961,"VX_cache genblk5[0] bank core_req_arb reqq_push", false,-1); + vcdp->declBus(c+33,"VX_cache genblk5[0] bank core_req_arb bank_valids", false,-1, 3,0); + vcdp->declBus(c+24513,"VX_cache genblk5[0] bank core_req_arb bank_rw", false,-1, 3,0); + vcdp->declBus(c+24521,"VX_cache genblk5[0] bank core_req_arb bank_byteen", false,-1, 15,0); + vcdp->declArray(c+24561,"VX_cache genblk5[0] bank core_req_arb bank_writedata", false,-1, 127,0); + vcdp->declArray(c+24529,"VX_cache genblk5[0] bank core_req_arb bank_addr", false,-1, 119,0); + vcdp->declQuad(c+24593,"VX_cache genblk5[0] bank core_req_arb bank_tag", false,-1, 41,0); + vcdp->declBit(c+2433,"VX_cache genblk5[0] bank core_req_arb reqq_pop", false,-1); + vcdp->declBit(c+2449,"VX_cache genblk5[0] bank core_req_arb reqq_req_st0", false,-1); + vcdp->declBus(c+2457,"VX_cache genblk5[0] bank core_req_arb reqq_req_tid_st0", false,-1, 1,0); + vcdp->declBit(c+2465,"VX_cache genblk5[0] bank core_req_arb reqq_req_rw_st0", false,-1); + vcdp->declBus(c+2473,"VX_cache genblk5[0] bank core_req_arb reqq_req_byteen_st0", false,-1, 3,0); + vcdp->declBus(c+2481,"VX_cache genblk5[0] bank core_req_arb reqq_req_addr_st0", false,-1, 29,0); + vcdp->declBus(c+2489,"VX_cache genblk5[0] bank core_req_arb reqq_req_writedata_st0", false,-1, 31,0); + vcdp->declQuad(c+10641,"VX_cache genblk5[0] bank core_req_arb reqq_req_tag_st0", false,-1, 41,0); + vcdp->declBit(c+2441,"VX_cache genblk5[0] bank core_req_arb reqq_empty", false,-1); + vcdp->declBit(c+10633,"VX_cache genblk5[0] bank core_req_arb reqq_full", false,-1); + vcdp->declBus(c+3241,"VX_cache genblk5[0] bank core_req_arb out_per_valids", false,-1, 3,0); + vcdp->declBus(c+3249,"VX_cache genblk5[0] bank core_req_arb out_per_rw", false,-1, 3,0); + vcdp->declBus(c+3257,"VX_cache genblk5[0] bank core_req_arb out_per_byteen", false,-1, 15,0); + vcdp->declArray(c+3265,"VX_cache genblk5[0] bank core_req_arb out_per_addr", false,-1, 119,0); + vcdp->declArray(c+3297,"VX_cache genblk5[0] bank core_req_arb out_per_writedata", false,-1, 127,0); + vcdp->declQuad(c+3329,"VX_cache genblk5[0] bank core_req_arb out_per_tag", false,-1, 41,0); + vcdp->declBus(c+12105,"VX_cache genblk5[0] bank core_req_arb use_per_valids", false,-1, 3,0); + vcdp->declBus(c+12113,"VX_cache genblk5[0] bank core_req_arb use_per_rw", false,-1, 3,0); + vcdp->declBus(c+12121,"VX_cache genblk5[0] bank core_req_arb use_per_byteen", false,-1, 15,0); + vcdp->declArray(c+12129,"VX_cache genblk5[0] bank core_req_arb use_per_addr", false,-1, 119,0); + vcdp->declArray(c+12161,"VX_cache genblk5[0] bank core_req_arb use_per_writedata", false,-1, 127,0); + vcdp->declQuad(c+10641,"VX_cache genblk5[0] bank core_req_arb use_per_tag", false,-1, 41,0); + vcdp->declBus(c+12105,"VX_cache genblk5[0] bank core_req_arb qual_valids", false,-1, 3,0); + vcdp->declBus(c+12113,"VX_cache genblk5[0] bank core_req_arb qual_rw", false,-1, 3,0); + vcdp->declBus(c+12121,"VX_cache genblk5[0] bank core_req_arb qual_byteen", false,-1, 15,0); + vcdp->declArray(c+12129,"VX_cache genblk5[0] bank core_req_arb qual_addr", false,-1, 119,0); + vcdp->declArray(c+12161,"VX_cache genblk5[0] bank core_req_arb qual_writedata", false,-1, 127,0); + vcdp->declQuad(c+10641,"VX_cache genblk5[0] bank core_req_arb qual_tag", false,-1, 41,0); + vcdp->declBit(c+12193,"VX_cache genblk5[0] bank core_req_arb o_empty", false,-1); + vcdp->declBit(c+12201,"VX_cache genblk5[0] bank core_req_arb use_empty", false,-1); + vcdp->declBit(c+3345,"VX_cache genblk5[0] bank core_req_arb out_empty", false,-1); + vcdp->declBit(c+985,"VX_cache genblk5[0] bank core_req_arb push_qual", false,-1); + vcdp->declBit(c+3353,"VX_cache genblk5[0] bank core_req_arb pop_qual", false,-1); + vcdp->declBus(c+3361,"VX_cache genblk5[0] bank core_req_arb real_out_per_valids", false,-1, 3,0); + vcdp->declBus(c+2457,"VX_cache genblk5[0] bank core_req_arb qual_request_index", false,-1, 1,0); + vcdp->declBit(c+2449,"VX_cache genblk5[0] bank core_req_arb qual_has_request", false,-1); + vcdp->declBus(c+25185,"VX_cache genblk5[0] bank core_req_arb reqq_queue DATAW", false,-1, 31,0); + vcdp->declBus(c+25081,"VX_cache genblk5[0] bank core_req_arb reqq_queue SIZE", false,-1, 31,0); + vcdp->declBus(c+25089,"VX_cache genblk5[0] bank core_req_arb reqq_queue BUFFERED_OUTPUT", false,-1, 31,0); + vcdp->declBit(c+24489,"VX_cache genblk5[0] bank core_req_arb reqq_queue clk", false,-1); + vcdp->declBit(c+24497,"VX_cache genblk5[0] bank core_req_arb reqq_queue reset", false,-1); + vcdp->declBit(c+985,"VX_cache genblk5[0] bank core_req_arb reqq_queue push", false,-1); + vcdp->declBit(c+3353,"VX_cache genblk5[0] bank core_req_arb reqq_queue pop", false,-1); + vcdp->declArray(c+273,"VX_cache genblk5[0] bank core_req_arb reqq_queue data_in", false,-1, 313,0); + vcdp->declArray(c+3369,"VX_cache genblk5[0] bank core_req_arb reqq_queue data_out", false,-1, 313,0); + vcdp->declBit(c+12193,"VX_cache genblk5[0] bank core_req_arb reqq_queue empty", false,-1); + vcdp->declBit(c+10633,"VX_cache genblk5[0] bank core_req_arb reqq_queue full", false,-1); + vcdp->declBus(c+12209,"VX_cache genblk5[0] bank core_req_arb reqq_queue size", false,-1, 2,0); + vcdp->declBus(c+12209,"VX_cache genblk5[0] bank core_req_arb reqq_queue size_r", false,-1, 2,0); + vcdp->declBit(c+3449,"VX_cache genblk5[0] bank core_req_arb reqq_queue reading", false,-1); + vcdp->declBit(c+353,"VX_cache genblk5[0] bank core_req_arb reqq_queue writing", false,-1); + {int i; for (i=0; i<4; i++) { + vcdp->declArray(c+12217+i*10,"VX_cache genblk5[0] bank core_req_arb reqq_queue genblk3 data", true,(i+0), 313,0);}} + vcdp->declArray(c+12537,"VX_cache genblk5[0] bank core_req_arb reqq_queue genblk3 genblk2 head_r", false,-1, 313,0); + vcdp->declArray(c+12617,"VX_cache genblk5[0] bank core_req_arb reqq_queue genblk3 genblk2 curr_r", false,-1, 313,0); + vcdp->declBus(c+12697,"VX_cache genblk5[0] bank core_req_arb reqq_queue genblk3 genblk2 wr_ptr_r", false,-1, 1,0); + vcdp->declBus(c+12705,"VX_cache genblk5[0] bank core_req_arb reqq_queue genblk3 genblk2 rd_ptr_r", false,-1, 1,0); + vcdp->declBus(c+12713,"VX_cache genblk5[0] bank core_req_arb reqq_queue genblk3 genblk2 rd_ptr_next_r", false,-1, 1,0); + vcdp->declBit(c+12193,"VX_cache genblk5[0] bank core_req_arb reqq_queue genblk3 genblk2 empty_r", false,-1); + vcdp->declBit(c+10633,"VX_cache genblk5[0] bank core_req_arb reqq_queue genblk3 genblk2 full_r", false,-1); + vcdp->declBit(c+12721,"VX_cache genblk5[0] bank core_req_arb reqq_queue genblk3 genblk2 bypass_r", false,-1); + vcdp->declBus(c+25081,"VX_cache genblk5[0] bank core_req_arb sel_bank N", false,-1, 31,0); + vcdp->declBit(c+24489,"VX_cache genblk5[0] bank core_req_arb sel_bank clk", false,-1); + vcdp->declBit(c+24497,"VX_cache genblk5[0] bank core_req_arb sel_bank reset", false,-1); + vcdp->declBus(c+12105,"VX_cache genblk5[0] bank core_req_arb sel_bank requests", false,-1, 3,0); + vcdp->declBus(c+2457,"VX_cache genblk5[0] bank core_req_arb sel_bank grant_index", false,-1, 1,0); + vcdp->declBus(c+3457,"VX_cache genblk5[0] bank core_req_arb sel_bank grant_onehot", false,-1, 3,0); + vcdp->declBit(c+2449,"VX_cache genblk5[0] bank core_req_arb sel_bank grant_valid", false,-1); + vcdp->declBus(c+3457,"VX_cache genblk5[0] bank core_req_arb sel_bank genblk2 grant_onehot_r", false,-1, 3,0); + vcdp->declBus(c+25081,"VX_cache genblk5[0] bank core_req_arb sel_bank genblk2 priority_encoder N", false,-1, 31,0); + vcdp->declBus(c+12105,"VX_cache genblk5[0] bank core_req_arb sel_bank genblk2 priority_encoder data_in", false,-1, 3,0); + vcdp->declBus(c+2457,"VX_cache genblk5[0] bank core_req_arb sel_bank genblk2 priority_encoder data_out", false,-1, 1,0); + vcdp->declBit(c+2449,"VX_cache genblk5[0] bank core_req_arb sel_bank genblk2 priority_encoder valid_out", false,-1); + vcdp->declBus(c+3465,"VX_cache genblk5[0] bank core_req_arb sel_bank genblk2 priority_encoder i", false,-1, 31,0); + vcdp->declBus(c+25193,"VX_cache genblk5[0] bank s0_1_c0 N", false,-1, 31,0); + vcdp->declBus(c+25057,"VX_cache genblk5[0] bank s0_1_c0 PASSTHRU", false,-1, 31,0); + vcdp->declBit(c+24489,"VX_cache genblk5[0] bank s0_1_c0 clk", false,-1); + vcdp->declBit(c+24497,"VX_cache genblk5[0] bank s0_1_c0 reset", false,-1); + vcdp->declBit(c+2585,"VX_cache genblk5[0] bank s0_1_c0 stall", false,-1); + vcdp->declBit(c+25137,"VX_cache genblk5[0] bank s0_1_c0 flush", false,-1); + vcdp->declArray(c+3473,"VX_cache genblk5[0] bank s0_1_c0 in", false,-1, 242,0); + vcdp->declArray(c+12729,"VX_cache genblk5[0] bank s0_1_c0 out", false,-1, 242,0); + vcdp->declArray(c+12729,"VX_cache genblk5[0] bank s0_1_c0 value", false,-1, 242,0); + vcdp->declBus(c+25065,"VX_cache genblk5[0] bank tag_data_access CACHE_SIZE", false,-1, 31,0); + vcdp->declBus(c+25073,"VX_cache genblk5[0] bank tag_data_access BANK_LINE_SIZE", false,-1, 31,0); + vcdp->declBus(c+25081,"VX_cache genblk5[0] bank tag_data_access NUM_BANKS", false,-1, 31,0); + vcdp->declBus(c+25081,"VX_cache genblk5[0] bank tag_data_access WORD_SIZE", false,-1, 31,0); + vcdp->declBus(c+25089,"VX_cache genblk5[0] bank tag_data_access STAGE_1_CYCLES", false,-1, 31,0); + vcdp->declBus(c+25089,"VX_cache genblk5[0] bank tag_data_access WRITE_ENABLE", false,-1, 31,0); + vcdp->declBus(c+25089,"VX_cache genblk5[0] bank tag_data_access DRAM_ENABLE", false,-1, 31,0); + vcdp->declBit(c+24489,"VX_cache genblk5[0] bank tag_data_access clk", false,-1); + vcdp->declBit(c+24497,"VX_cache genblk5[0] bank tag_data_access reset", false,-1); + vcdp->declBit(c+2585,"VX_cache genblk5[0] bank tag_data_access stall", false,-1); + vcdp->declBit(c+2969,"VX_cache genblk5[0] bank tag_data_access is_snp_st1e", false,-1); + vcdp->declBit(c+2977,"VX_cache genblk5[0] bank tag_data_access snp_invalidate_st1e", false,-1); + vcdp->declBit(c+2585,"VX_cache genblk5[0] bank tag_data_access stall_bank_pipe", false,-1); + vcdp->declBit(c+2537,"VX_cache genblk5[0] bank tag_data_access force_request_miss_st1e", false,-1); + vcdp->declBus(c+3537,"VX_cache genblk5[0] bank tag_data_access readaddr_st10", false,-1, 5,0); + vcdp->declBus(c+3033,"VX_cache genblk5[0] bank tag_data_access writeaddr_st1e", false,-1, 25,0); + vcdp->declBit(c+3009,"VX_cache genblk5[0] bank tag_data_access valid_req_st1e", false,-1); + vcdp->declBit(c+3545,"VX_cache genblk5[0] bank tag_data_access writefill_st1e", false,-1); + vcdp->declBus(c+3553,"VX_cache genblk5[0] bank tag_data_access writeword_st1e", false,-1, 31,0); + vcdp->declArray(c+3561,"VX_cache genblk5[0] bank tag_data_access writedata_st1e", false,-1, 127,0); + vcdp->declBit(c+2945,"VX_cache genblk5[0] bank tag_data_access mem_rw_st1e", false,-1); + vcdp->declBus(c+2953,"VX_cache genblk5[0] bank tag_data_access mem_byteen_st1e", false,-1, 3,0); + vcdp->declBus(c+3593,"VX_cache genblk5[0] bank tag_data_access wordsel_st1e", false,-1, 1,0); + vcdp->declBus(c+2849,"VX_cache genblk5[0] bank tag_data_access readword_st1e", false,-1, 31,0); + vcdp->declArray(c+2857,"VX_cache genblk5[0] bank tag_data_access readdata_st1e", false,-1, 127,0); + vcdp->declBus(c+2889,"VX_cache genblk5[0] bank tag_data_access readtag_st1e", false,-1, 19,0); + vcdp->declBit(c+2897,"VX_cache genblk5[0] bank tag_data_access miss_st1e", false,-1); + vcdp->declBit(c+2905,"VX_cache genblk5[0] bank tag_data_access dirty_st1e", false,-1); + vcdp->declBus(c+2913,"VX_cache genblk5[0] bank tag_data_access dirtyb_st1e", false,-1, 15,0); + vcdp->declBit(c+2961,"VX_cache genblk5[0] bank tag_data_access fill_saw_dirty_st1e", false,-1); + vcdp->declBit(c+2985,"VX_cache genblk5[0] bank tag_data_access snp_to_mrvq_st1e", false,-1); + vcdp->declBit(c+2993,"VX_cache genblk5[0] bank tag_data_access mrvq_init_ready_state_st1e", false,-1); + {int i; for (i=0; i<1; i++) { + vcdp->declBit(c+3601+i*1,"VX_cache genblk5[0] bank tag_data_access read_valid_st1c", true,(i+0));}} + {int i; for (i=0; i<1; i++) { + vcdp->declBit(c+3609+i*1,"VX_cache genblk5[0] bank tag_data_access read_dirty_st1c", true,(i+0));}} + {int i; for (i=0; i<1; i++) { + vcdp->declBus(c+3617+i*1,"VX_cache genblk5[0] bank tag_data_access read_dirtyb_st1c", true,(i+0), 15,0);}} + {int i; for (i=0; i<1; i++) { + vcdp->declBus(c+3625+i*1,"VX_cache genblk5[0] bank tag_data_access read_tag_st1c", true,(i+0), 19,0);}} + {int i; for (i=0; i<1; i++) { + vcdp->declArray(c+3633+i*4,"VX_cache genblk5[0] bank tag_data_access read_data_st1c", true,(i+0), 127,0);}} + vcdp->declBit(c+3665,"VX_cache genblk5[0] bank tag_data_access qual_read_valid_st1", false,-1); + vcdp->declBit(c+3673,"VX_cache genblk5[0] bank tag_data_access qual_read_dirty_st1", false,-1); + vcdp->declBus(c+3681,"VX_cache genblk5[0] bank tag_data_access qual_read_dirtyb_st1", false,-1, 15,0); + vcdp->declBus(c+3689,"VX_cache genblk5[0] bank tag_data_access qual_read_tag_st1", false,-1, 19,0); + vcdp->declArray(c+3697,"VX_cache genblk5[0] bank tag_data_access qual_read_data_st1", false,-1, 127,0); + vcdp->declBit(c+3729,"VX_cache genblk5[0] bank tag_data_access use_read_valid_st1e", false,-1); + vcdp->declBit(c+3737,"VX_cache genblk5[0] bank tag_data_access use_read_dirty_st1e", false,-1); + vcdp->declBus(c+2913,"VX_cache genblk5[0] bank tag_data_access use_read_dirtyb_st1e", false,-1, 15,0); + vcdp->declBus(c+2889,"VX_cache genblk5[0] bank tag_data_access use_read_tag_st1e", false,-1, 19,0); + vcdp->declArray(c+2857,"VX_cache genblk5[0] bank tag_data_access use_read_data_st1e", false,-1, 127,0); + vcdp->declBus(c+3745,"VX_cache genblk5[0] bank tag_data_access use_write_enable", false,-1, 15,0); + vcdp->declArray(c+3753,"VX_cache genblk5[0] bank tag_data_access use_write_data", false,-1, 127,0); + vcdp->declBit(c+2897,"VX_cache genblk5[0] bank tag_data_access fill_sent", false,-1); + vcdp->declBit(c+3785,"VX_cache genblk5[0] bank tag_data_access invalidate_line", false,-1); + vcdp->declBit(c+3793,"VX_cache genblk5[0] bank tag_data_access tags_match", false,-1); + vcdp->declBit(c+3801,"VX_cache genblk5[0] bank tag_data_access real_writefill", false,-1); + vcdp->declBus(c+3809,"VX_cache genblk5[0] bank tag_data_access writetag_st1e", false,-1, 19,0); + vcdp->declBus(c+3537,"VX_cache genblk5[0] bank tag_data_access writeladdr_st1e", false,-1, 5,0); + vcdp->declBus(c+3817,"VX_cache genblk5[0] bank tag_data_access we", false,-1, 15,0); + vcdp->declArray(c+3753,"VX_cache genblk5[0] bank tag_data_access data_write", false,-1, 127,0); + vcdp->declBit(c+3825,"VX_cache genblk5[0] bank tag_data_access should_write", false,-1); + vcdp->declBit(c+3785,"VX_cache genblk5[0] bank tag_data_access snoop_hit_no_pending", false,-1); + vcdp->declBit(c+3833,"VX_cache genblk5[0] bank tag_data_access req_invalid", false,-1); + vcdp->declBit(c+3841,"VX_cache genblk5[0] bank tag_data_access req_miss", false,-1); + vcdp->declBit(c+3849,"VX_cache genblk5[0] bank tag_data_access real_miss", false,-1); + vcdp->declBit(c+3857,"VX_cache genblk5[0] bank tag_data_access force_core_miss", false,-1); + vcdp->declBit(c+3865,"VX_cache genblk5[0] bank tag_data_access genblk4[0] normal_write", false,-1); + vcdp->declBit(c+3873,"VX_cache genblk5[0] bank tag_data_access genblk4[1] normal_write", false,-1); + vcdp->declBit(c+3881,"VX_cache genblk5[0] bank tag_data_access genblk4[2] normal_write", false,-1); + vcdp->declBit(c+3889,"VX_cache genblk5[0] bank tag_data_access genblk4[3] normal_write", false,-1); + vcdp->declBus(c+25065,"VX_cache genblk5[0] bank tag_data_access tag_data_structure CACHE_SIZE", false,-1, 31,0); + vcdp->declBus(c+25073,"VX_cache genblk5[0] bank tag_data_access tag_data_structure BANK_LINE_SIZE", false,-1, 31,0); + vcdp->declBus(c+25081,"VX_cache genblk5[0] bank tag_data_access tag_data_structure NUM_BANKS", false,-1, 31,0); + vcdp->declBus(c+25081,"VX_cache genblk5[0] bank tag_data_access tag_data_structure WORD_SIZE", false,-1, 31,0); + vcdp->declBit(c+24489,"VX_cache genblk5[0] bank tag_data_access tag_data_structure clk", false,-1); + vcdp->declBit(c+24497,"VX_cache genblk5[0] bank tag_data_access tag_data_structure reset", false,-1); + vcdp->declBit(c+2585,"VX_cache genblk5[0] bank tag_data_access tag_data_structure stall_bank_pipe", false,-1); + vcdp->declBus(c+3537,"VX_cache genblk5[0] bank tag_data_access tag_data_structure read_addr", false,-1, 5,0); + vcdp->declBit(c+3665,"VX_cache genblk5[0] bank tag_data_access tag_data_structure read_valid", false,-1); + vcdp->declBit(c+3673,"VX_cache genblk5[0] bank tag_data_access tag_data_structure read_dirty", false,-1); + vcdp->declBus(c+3681,"VX_cache genblk5[0] bank tag_data_access tag_data_structure read_dirtyb", false,-1, 15,0); + vcdp->declBus(c+3689,"VX_cache genblk5[0] bank tag_data_access tag_data_structure read_tag", false,-1, 19,0); + vcdp->declArray(c+3697,"VX_cache genblk5[0] bank tag_data_access tag_data_structure read_data", false,-1, 127,0); + vcdp->declBit(c+3785,"VX_cache genblk5[0] bank tag_data_access tag_data_structure invalidate", false,-1); + vcdp->declBus(c+3745,"VX_cache genblk5[0] bank tag_data_access tag_data_structure write_enable", false,-1, 15,0); + vcdp->declBit(c+3801,"VX_cache genblk5[0] bank tag_data_access tag_data_structure write_fill", false,-1); + vcdp->declBus(c+3537,"VX_cache genblk5[0] bank tag_data_access tag_data_structure write_addr", false,-1, 5,0); + vcdp->declBus(c+3809,"VX_cache genblk5[0] bank tag_data_access tag_data_structure tag_index", false,-1, 19,0); + vcdp->declArray(c+3753,"VX_cache genblk5[0] bank tag_data_access tag_data_structure write_data", false,-1, 127,0); + vcdp->declBit(c+2897,"VX_cache genblk5[0] bank tag_data_access tag_data_structure fill_sent", false,-1); + vcdp->declQuad(c+12793,"VX_cache genblk5[0] bank tag_data_access tag_data_structure dirty", false,-1, 63,0); + vcdp->declQuad(c+12809,"VX_cache genblk5[0] bank tag_data_access tag_data_structure valid", false,-1, 63,0); + vcdp->declBit(c+3897,"VX_cache genblk5[0] bank tag_data_access tag_data_structure do_write", false,-1); + vcdp->declBus(c+12825,"VX_cache genblk5[0] bank tag_data_access tag_data_structure i", false,-1, 31,0); + vcdp->declBus(c+12833,"VX_cache genblk5[0] bank tag_data_access tag_data_structure j", false,-1, 31,0); + vcdp->declBus(c+25201,"VX_cache genblk5[0] bank tag_data_access s0_1_c0 N", false,-1, 31,0); + vcdp->declBus(c+25089,"VX_cache genblk5[0] bank tag_data_access s0_1_c0 PASSTHRU", false,-1, 31,0); + vcdp->declBit(c+24489,"VX_cache genblk5[0] bank tag_data_access s0_1_c0 clk", false,-1); + vcdp->declBit(c+24497,"VX_cache genblk5[0] bank tag_data_access s0_1_c0 reset", false,-1); + vcdp->declBit(c+2585,"VX_cache genblk5[0] bank tag_data_access s0_1_c0 stall", false,-1); + vcdp->declBit(c+25137,"VX_cache genblk5[0] bank tag_data_access s0_1_c0 flush", false,-1); + vcdp->declArray(c+3905,"VX_cache genblk5[0] bank tag_data_access s0_1_c0 in", false,-1, 165,0); + vcdp->declArray(c+3905,"VX_cache genblk5[0] bank tag_data_access s0_1_c0 out", false,-1, 165,0); + vcdp->declArray(c+12841,"VX_cache genblk5[0] bank tag_data_access s0_1_c0 value", false,-1, 165,0); + vcdp->declBus(c+25209,"VX_cache genblk5[0] bank st_1e_2 N", false,-1, 31,0); + vcdp->declBus(c+25057,"VX_cache genblk5[0] bank st_1e_2 PASSTHRU", false,-1, 31,0); + vcdp->declBit(c+24489,"VX_cache genblk5[0] bank st_1e_2 clk", false,-1); + vcdp->declBit(c+24497,"VX_cache genblk5[0] bank st_1e_2 reset", false,-1); + vcdp->declBit(c+2585,"VX_cache genblk5[0] bank st_1e_2 stall", false,-1); + vcdp->declBit(c+25137,"VX_cache genblk5[0] bank st_1e_2 flush", false,-1); + vcdp->declArray(c+3953,"VX_cache genblk5[0] bank st_1e_2 in", false,-1, 315,0); + vcdp->declArray(c+12889,"VX_cache genblk5[0] bank st_1e_2 out", false,-1, 315,0); + vcdp->declArray(c+12889,"VX_cache genblk5[0] bank st_1e_2 value", false,-1, 315,0); + vcdp->declBus(c+25057,"VX_cache genblk5[0] bank cache_miss_resrv CACHE_ID", false,-1, 31,0); + vcdp->declBus(c+25153,"VX_cache genblk5[0] bank cache_miss_resrv BANK_ID", false,-1, 31,0); + vcdp->declBus(c+25073,"VX_cache genblk5[0] bank cache_miss_resrv BANK_LINE_SIZE", false,-1, 31,0); + vcdp->declBus(c+25081,"VX_cache genblk5[0] bank cache_miss_resrv NUM_BANKS", false,-1, 31,0); + vcdp->declBus(c+25081,"VX_cache genblk5[0] bank cache_miss_resrv WORD_SIZE", false,-1, 31,0); + vcdp->declBus(c+25081,"VX_cache genblk5[0] bank cache_miss_resrv NUM_REQUESTS", false,-1, 31,0); + vcdp->declBus(c+25073,"VX_cache genblk5[0] bank cache_miss_resrv MRVQ_SIZE", false,-1, 31,0); + vcdp->declBus(c+25097,"VX_cache genblk5[0] bank cache_miss_resrv CORE_TAG_WIDTH", false,-1, 31,0); + vcdp->declBus(c+25113,"VX_cache genblk5[0] bank cache_miss_resrv SNP_REQ_TAG_WIDTH", false,-1, 31,0); + vcdp->declBit(c+24489,"VX_cache genblk5[0] bank cache_miss_resrv clk", false,-1); + vcdp->declBit(c+24497,"VX_cache genblk5[0] bank cache_miss_resrv reset", false,-1); + vcdp->declBit(c+3081,"VX_cache genblk5[0] bank cache_miss_resrv miss_add", false,-1); + vcdp->declBit(c+3089,"VX_cache genblk5[0] bank cache_miss_resrv is_mrvq", false,-1); + vcdp->declBus(c+10089,"VX_cache genblk5[0] bank cache_miss_resrv miss_add_addr", false,-1, 25,0); + vcdp->declBus(c+10801,"VX_cache genblk5[0] bank cache_miss_resrv miss_add_wsel", false,-1, 1,0); + vcdp->declBus(c+10809,"VX_cache genblk5[0] bank cache_miss_resrv miss_add_data", false,-1, 31,0); + vcdp->declBus(c+10745,"VX_cache genblk5[0] bank cache_miss_resrv miss_add_tid", false,-1, 1,0); + vcdp->declQuad(c+10753,"VX_cache genblk5[0] bank cache_miss_resrv miss_add_tag", false,-1, 41,0); + vcdp->declBit(c+10769,"VX_cache genblk5[0] bank cache_miss_resrv miss_add_rw", false,-1); + vcdp->declBus(c+10777,"VX_cache genblk5[0] bank cache_miss_resrv miss_add_byteen", false,-1, 3,0); + vcdp->declBit(c+3049,"VX_cache genblk5[0] bank cache_miss_resrv mrvq_init_ready_state", false,-1); + vcdp->declBit(c+10913,"VX_cache genblk5[0] bank cache_miss_resrv miss_add_is_snp", false,-1); + vcdp->declBit(c+10921,"VX_cache genblk5[0] bank cache_miss_resrv miss_add_snp_invalidate", false,-1); + vcdp->declBit(c+10657,"VX_cache genblk5[0] bank cache_miss_resrv miss_resrv_full", false,-1); + vcdp->declBit(c+10665,"VX_cache genblk5[0] bank cache_miss_resrv miss_resrv_stop", false,-1); + vcdp->declBit(c+3545,"VX_cache genblk5[0] bank cache_miss_resrv is_fill_st1", false,-1); + vcdp->declBus(c+3033,"VX_cache genblk5[0] bank cache_miss_resrv fill_addr_st1", false,-1, 25,0); + vcdp->declBit(c+2521,"VX_cache genblk5[0] bank cache_miss_resrv pending_hazard", false,-1); + vcdp->declBit(c+2497,"VX_cache genblk5[0] bank cache_miss_resrv miss_resrv_pop", false,-1); + vcdp->declBit(c+2505,"VX_cache genblk5[0] bank cache_miss_resrv miss_resrv_valid_st0", false,-1); + vcdp->declBus(c+10681,"VX_cache genblk5[0] bank cache_miss_resrv miss_resrv_addr_st0", false,-1, 25,0); + vcdp->declBus(c+10689,"VX_cache genblk5[0] bank cache_miss_resrv miss_resrv_wsel_st0", false,-1, 1,0); + vcdp->declBus(c+10697,"VX_cache genblk5[0] bank cache_miss_resrv miss_resrv_data_st0", false,-1, 31,0); + vcdp->declBus(c+10673,"VX_cache genblk5[0] bank cache_miss_resrv miss_resrv_tid_st0", false,-1, 1,0); + vcdp->declQuad(c+10705,"VX_cache genblk5[0] bank cache_miss_resrv miss_resrv_tag_st0", false,-1, 41,0); + vcdp->declBit(c+2513,"VX_cache genblk5[0] bank cache_miss_resrv miss_resrv_rw_st0", false,-1); + vcdp->declBus(c+10721,"VX_cache genblk5[0] bank cache_miss_resrv miss_resrv_byteen_st0", false,-1, 3,0); + vcdp->declBit(c+10729,"VX_cache genblk5[0] bank cache_miss_resrv miss_resrv_is_snp_st0", false,-1); + vcdp->declBit(c+10737,"VX_cache genblk5[0] bank cache_miss_resrv miss_resrv_snp_invalidate_st0", false,-1); + {int i; for (i=0; i<16; i++) { + vcdp->declArray(c+12969+i*3,"VX_cache genblk5[0] bank cache_miss_resrv metadata_table", true,(i+0), 84,0);}} + vcdp->declArray(c+13353,"VX_cache genblk5[0] bank cache_miss_resrv addr_table", false,-1, 415,0); + vcdp->declBus(c+13457,"VX_cache genblk5[0] bank cache_miss_resrv valid_table", false,-1, 15,0); + vcdp->declBus(c+13465,"VX_cache genblk5[0] bank cache_miss_resrv ready_table", false,-1, 15,0); + vcdp->declBus(c+13473,"VX_cache genblk5[0] bank cache_miss_resrv schedule_ptr", false,-1, 3,0); + vcdp->declBus(c+13481,"VX_cache genblk5[0] bank cache_miss_resrv head_ptr", false,-1, 3,0); + vcdp->declBus(c+13489,"VX_cache genblk5[0] bank cache_miss_resrv tail_ptr", false,-1, 3,0); + vcdp->declBus(c+13497,"VX_cache genblk5[0] bank cache_miss_resrv size", false,-1, 4,0); + vcdp->declBit(c+13505,"VX_cache genblk5[0] bank cache_miss_resrv enqueue_possible", false,-1); + vcdp->declBus(c+13489,"VX_cache genblk5[0] bank cache_miss_resrv enqueue_index", false,-1, 3,0); + vcdp->declBus(c+4033,"VX_cache genblk5[0] bank cache_miss_resrv make_ready", false,-1, 15,0); + vcdp->declBus(c+4041,"VX_cache genblk5[0] bank cache_miss_resrv make_ready_push", false,-1, 15,0); + vcdp->declBus(c+4049,"VX_cache genblk5[0] bank cache_miss_resrv valid_address_match", false,-1, 15,0); + vcdp->declBit(c+2505,"VX_cache genblk5[0] bank cache_miss_resrv dequeue_possible", false,-1); + vcdp->declBus(c+13473,"VX_cache genblk5[0] bank cache_miss_resrv dequeue_index", false,-1, 3,0); + vcdp->declBit(c+4057,"VX_cache genblk5[0] bank cache_miss_resrv mrvq_push", false,-1); + vcdp->declBit(c+4065,"VX_cache genblk5[0] bank cache_miss_resrv mrvq_pop", false,-1); + vcdp->declBit(c+4073,"VX_cache genblk5[0] bank cache_miss_resrv recover_state", false,-1); + vcdp->declBit(c+4081,"VX_cache genblk5[0] bank cache_miss_resrv increment_head", false,-1); + vcdp->declBit(c+4089,"VX_cache genblk5[0] bank cache_miss_resrv update_ready", false,-1); + vcdp->declBit(c+4097,"VX_cache genblk5[0] bank cache_miss_resrv qual_mrvq_init", false,-1); + vcdp->declBus(c+25217,"VX_cache genblk5[0] bank cwb_queue DATAW", false,-1, 31,0); + vcdp->declBus(c+25081,"VX_cache genblk5[0] bank cwb_queue SIZE", false,-1, 31,0); + vcdp->declBus(c+25089,"VX_cache genblk5[0] bank cwb_queue BUFFERED_OUTPUT", false,-1, 31,0); + vcdp->declBit(c+24489,"VX_cache genblk5[0] bank cwb_queue clk", false,-1); + vcdp->declBit(c+24497,"VX_cache genblk5[0] bank cwb_queue reset", false,-1); + vcdp->declBit(c+3097,"VX_cache genblk5[0] bank cwb_queue push", false,-1); + vcdp->declBit(c+969,"VX_cache genblk5[0] bank cwb_queue pop", false,-1); + vcdp->declArray(c+4105,"VX_cache genblk5[0] bank cwb_queue data_in", false,-1, 75,0); + vcdp->declArray(c+4129,"VX_cache genblk5[0] bank cwb_queue data_out", false,-1, 75,0); + vcdp->declBit(c+10961,"VX_cache genblk5[0] bank cwb_queue empty", false,-1); + vcdp->declBit(c+10969,"VX_cache genblk5[0] bank cwb_queue full", false,-1); + vcdp->declBus(c+13513,"VX_cache genblk5[0] bank cwb_queue size", false,-1, 2,0); + vcdp->declBus(c+13513,"VX_cache genblk5[0] bank cwb_queue size_r", false,-1, 2,0); + vcdp->declBit(c+361,"VX_cache genblk5[0] bank cwb_queue reading", false,-1); + vcdp->declBit(c+4153,"VX_cache genblk5[0] bank cwb_queue writing", false,-1); + {int i; for (i=0; i<4; i++) { + vcdp->declArray(c+13521+i*3,"VX_cache genblk5[0] bank cwb_queue genblk3 data", true,(i+0), 75,0);}} + vcdp->declArray(c+13617,"VX_cache genblk5[0] bank cwb_queue genblk3 genblk2 head_r", false,-1, 75,0); + vcdp->declArray(c+13641,"VX_cache genblk5[0] bank cwb_queue genblk3 genblk2 curr_r", false,-1, 75,0); + vcdp->declBus(c+13665,"VX_cache genblk5[0] bank cwb_queue genblk3 genblk2 wr_ptr_r", false,-1, 1,0); + vcdp->declBus(c+13673,"VX_cache genblk5[0] bank cwb_queue genblk3 genblk2 rd_ptr_r", false,-1, 1,0); + vcdp->declBus(c+13681,"VX_cache genblk5[0] bank cwb_queue genblk3 genblk2 rd_ptr_next_r", false,-1, 1,0); + vcdp->declBit(c+10961,"VX_cache genblk5[0] bank cwb_queue genblk3 genblk2 empty_r", false,-1); + vcdp->declBit(c+10969,"VX_cache genblk5[0] bank cwb_queue genblk3 genblk2 full_r", false,-1); + vcdp->declBit(c+13689,"VX_cache genblk5[0] bank cwb_queue genblk3 genblk2 bypass_r", false,-1); + vcdp->declBus(c+25225,"VX_cache genblk5[0] bank dwb_queue DATAW", false,-1, 31,0); + vcdp->declBus(c+25081,"VX_cache genblk5[0] bank dwb_queue SIZE", false,-1, 31,0); + vcdp->declBus(c+25089,"VX_cache genblk5[0] bank dwb_queue BUFFERED_OUTPUT", false,-1, 31,0); + vcdp->declBit(c+24489,"VX_cache genblk5[0] bank dwb_queue clk", false,-1); + vcdp->declBit(c+24497,"VX_cache genblk5[0] bank dwb_queue reset", false,-1); + vcdp->declBit(c+3121,"VX_cache genblk5[0] bank dwb_queue push", false,-1); + vcdp->declBit(c+977,"VX_cache genblk5[0] bank dwb_queue pop", false,-1); + vcdp->declArray(c+4161,"VX_cache genblk5[0] bank dwb_queue data_in", false,-1, 199,0); + vcdp->declArray(c+4217,"VX_cache genblk5[0] bank dwb_queue data_out", false,-1, 199,0); + vcdp->declBit(c+10977,"VX_cache genblk5[0] bank dwb_queue empty", false,-1); + vcdp->declBit(c+10985,"VX_cache genblk5[0] bank dwb_queue full", false,-1); + vcdp->declBus(c+13697,"VX_cache genblk5[0] bank dwb_queue size", false,-1, 2,0); + vcdp->declBus(c+13697,"VX_cache genblk5[0] bank dwb_queue size_r", false,-1, 2,0); + vcdp->declBit(c+369,"VX_cache genblk5[0] bank dwb_queue reading", false,-1); + vcdp->declBit(c+4273,"VX_cache genblk5[0] bank dwb_queue writing", false,-1); + {int i; for (i=0; i<4; i++) { + vcdp->declArray(c+13705+i*7,"VX_cache genblk5[0] bank dwb_queue genblk3 data", true,(i+0), 199,0);}} + vcdp->declArray(c+13929,"VX_cache genblk5[0] bank dwb_queue genblk3 genblk2 head_r", false,-1, 199,0); + vcdp->declArray(c+13985,"VX_cache genblk5[0] bank dwb_queue genblk3 genblk2 curr_r", false,-1, 199,0); + vcdp->declBus(c+14041,"VX_cache genblk5[0] bank dwb_queue genblk3 genblk2 wr_ptr_r", false,-1, 1,0); + vcdp->declBus(c+14049,"VX_cache genblk5[0] bank dwb_queue genblk3 genblk2 rd_ptr_r", false,-1, 1,0); + vcdp->declBus(c+14057,"VX_cache genblk5[0] bank dwb_queue genblk3 genblk2 rd_ptr_next_r", false,-1, 1,0); + vcdp->declBit(c+10977,"VX_cache genblk5[0] bank dwb_queue genblk3 genblk2 empty_r", false,-1); + vcdp->declBit(c+10985,"VX_cache genblk5[0] bank dwb_queue genblk3 genblk2 full_r", false,-1); + vcdp->declBit(c+14065,"VX_cache genblk5[0] bank dwb_queue genblk3 genblk2 bypass_r", false,-1); + vcdp->declBus(c+25057,"VX_cache genblk5[1] bank CACHE_ID", false,-1, 31,0); + vcdp->declBus(c+25161,"VX_cache genblk5[1] bank BANK_ID", false,-1, 31,0); + vcdp->declBus(c+25065,"VX_cache genblk5[1] bank CACHE_SIZE", false,-1, 31,0); + vcdp->declBus(c+25073,"VX_cache genblk5[1] bank BANK_LINE_SIZE", false,-1, 31,0); + vcdp->declBus(c+25081,"VX_cache genblk5[1] bank NUM_BANKS", false,-1, 31,0); + vcdp->declBus(c+25081,"VX_cache genblk5[1] bank WORD_SIZE", false,-1, 31,0); + vcdp->declBus(c+25081,"VX_cache genblk5[1] bank NUM_REQUESTS", false,-1, 31,0); + vcdp->declBus(c+25089,"VX_cache genblk5[1] bank STAGE_1_CYCLES", false,-1, 31,0); + vcdp->declBus(c+25081,"VX_cache genblk5[1] bank CREQ_SIZE", false,-1, 31,0); + vcdp->declBus(c+25073,"VX_cache genblk5[1] bank MRVQ_SIZE", false,-1, 31,0); + vcdp->declBus(c+25073,"VX_cache genblk5[1] bank DFPQ_SIZE", false,-1, 31,0); + vcdp->declBus(c+25073,"VX_cache genblk5[1] bank SNRQ_SIZE", false,-1, 31,0); + vcdp->declBus(c+25081,"VX_cache genblk5[1] bank CWBQ_SIZE", false,-1, 31,0); + vcdp->declBus(c+25081,"VX_cache genblk5[1] bank DWBQ_SIZE", false,-1, 31,0); + vcdp->declBus(c+25081,"VX_cache genblk5[1] bank DFQQ_SIZE", false,-1, 31,0); + vcdp->declBus(c+25089,"VX_cache genblk5[1] bank WRITE_ENABLE", false,-1, 31,0); + vcdp->declBus(c+25089,"VX_cache genblk5[1] bank DRAM_ENABLE", false,-1, 31,0); + vcdp->declBus(c+25057,"VX_cache genblk5[1] bank SNOOP_FORWARDING", false,-1, 31,0); + vcdp->declBus(c+25097,"VX_cache genblk5[1] bank CORE_TAG_WIDTH", false,-1, 31,0); + vcdp->declBus(c+25105,"VX_cache genblk5[1] bank CORE_TAG_ID_BITS", false,-1, 31,0); + vcdp->declBus(c+25113,"VX_cache genblk5[1] bank SNP_REQ_TAG_WIDTH", false,-1, 31,0); + vcdp->declBit(c+24489,"VX_cache genblk5[1] bank clk", false,-1); + vcdp->declBit(c+24497,"VX_cache genblk5[1] bank reset", false,-1); + vcdp->declBus(c+65,"VX_cache genblk5[1] bank core_req_valid", false,-1, 3,0); + vcdp->declBus(c+24513,"VX_cache genblk5[1] bank core_req_rw", false,-1, 3,0); + vcdp->declBus(c+24521,"VX_cache genblk5[1] bank core_req_byteen", false,-1, 15,0); + vcdp->declArray(c+24529,"VX_cache genblk5[1] bank core_req_addr", false,-1, 119,0); + vcdp->declArray(c+24561,"VX_cache genblk5[1] bank core_req_data", false,-1, 127,0); + vcdp->declQuad(c+24593,"VX_cache genblk5[1] bank core_req_tag", false,-1, 41,0); + vcdp->declBit(c+10145,"VX_cache genblk5[1] bank core_req_ready", false,-1); + vcdp->declBit(c+10113,"VX_cache genblk5[1] bank core_rsp_valid", false,-1); + vcdp->declBus(c+1585,"VX_cache genblk5[1] bank core_rsp_tid", false,-1, 1,0); + vcdp->declBus(c+1593,"VX_cache genblk5[1] bank core_rsp_data", false,-1, 31,0); + vcdp->declQuad(c+1601,"VX_cache genblk5[1] bank core_rsp_tag", false,-1, 41,0); + vcdp->declBit(c+73,"VX_cache genblk5[1] bank core_rsp_ready", false,-1); + vcdp->declBit(c+1617,"VX_cache genblk5[1] bank dram_fill_req_valid", false,-1); + vcdp->declBus(c+10129,"VX_cache genblk5[1] bank dram_fill_req_addr", false,-1, 25,0); + vcdp->declBit(c+10065,"VX_cache genblk5[1] bank dram_fill_req_ready", false,-1); + vcdp->declBit(c+24993,"VX_cache genblk5[1] bank dram_fill_rsp_valid", false,-1); + vcdp->declArray(c+24769,"VX_cache genblk5[1] bank dram_fill_rsp_data", false,-1, 127,0); + vcdp->declBus(c+24969,"VX_cache genblk5[1] bank dram_fill_rsp_addr", false,-1, 25,0); + vcdp->declBit(c+10121,"VX_cache genblk5[1] bank dram_fill_rsp_ready", false,-1); + vcdp->declBit(c+1625,"VX_cache genblk5[1] bank dram_wb_req_valid", false,-1); + vcdp->declBus(c+1633,"VX_cache genblk5[1] bank dram_wb_req_byteen", false,-1, 15,0); + vcdp->declBus(c+1641,"VX_cache genblk5[1] bank dram_wb_req_addr", false,-1, 25,0); + vcdp->declArray(c+1649,"VX_cache genblk5[1] bank dram_wb_req_data", false,-1, 127,0); + vcdp->declBit(c+81,"VX_cache genblk5[1] bank dram_wb_req_ready", false,-1); + vcdp->declBit(c+25001,"VX_cache genblk5[1] bank snp_req_valid", false,-1); + vcdp->declBus(c+24985,"VX_cache genblk5[1] bank snp_req_addr", false,-1, 25,0); + vcdp->declBit(c+24833,"VX_cache genblk5[1] bank snp_req_invalidate", false,-1); + vcdp->declBus(c+24841,"VX_cache genblk5[1] bank snp_req_tag", false,-1, 27,0); + vcdp->declBit(c+10137,"VX_cache genblk5[1] bank snp_req_ready", false,-1); + vcdp->declBit(c+1681,"VX_cache genblk5[1] bank snp_rsp_valid", false,-1); + vcdp->declBus(c+1689,"VX_cache genblk5[1] bank snp_rsp_tag", false,-1, 27,0); + vcdp->declBit(c+89,"VX_cache genblk5[1] bank snp_rsp_ready", false,-1); + vcdp->declBit(c+4281,"VX_cache genblk5[1] bank snrq_pop", false,-1); + vcdp->declBit(c+14073,"VX_cache genblk5[1] bank snrq_empty", false,-1); + vcdp->declBit(c+14081,"VX_cache genblk5[1] bank snrq_full", false,-1); + vcdp->declBus(c+4289,"VX_cache genblk5[1] bank snrq_addr_st0", false,-1, 25,0); + vcdp->declBit(c+4297,"VX_cache genblk5[1] bank snrq_invalidate_st0", false,-1); + vcdp->declBus(c+4305,"VX_cache genblk5[1] bank snrq_tag_st0", false,-1, 27,0); + vcdp->declBit(c+4313,"VX_cache genblk5[1] bank dfpq_pop", false,-1); + vcdp->declBit(c+14089,"VX_cache genblk5[1] bank dfpq_empty", false,-1); + vcdp->declBit(c+14097,"VX_cache genblk5[1] bank dfpq_full", false,-1); + vcdp->declBus(c+4321,"VX_cache genblk5[1] bank dfpq_addr_st0", false,-1, 25,0); + vcdp->declArray(c+4329,"VX_cache genblk5[1] bank dfpq_filldata_st0", false,-1, 127,0); + vcdp->declBit(c+4361,"VX_cache genblk5[1] bank reqq_pop", false,-1); + vcdp->declBit(c+993,"VX_cache genblk5[1] bank reqq_push", false,-1); + vcdp->declBit(c+4369,"VX_cache genblk5[1] bank reqq_empty", false,-1); + vcdp->declBit(c+14105,"VX_cache genblk5[1] bank reqq_full", false,-1); + vcdp->declBit(c+4377,"VX_cache genblk5[1] bank reqq_req_st0", false,-1); + vcdp->declBus(c+4385,"VX_cache genblk5[1] bank reqq_req_tid_st0", false,-1, 1,0); + vcdp->declBit(c+4393,"VX_cache genblk5[1] bank reqq_req_rw_st0", false,-1); + vcdp->declBus(c+4401,"VX_cache genblk5[1] bank reqq_req_byteen_st0", false,-1, 3,0); + vcdp->declBus(c+4409,"VX_cache genblk5[1] bank reqq_req_addr_st0", false,-1, 29,0); + vcdp->declBus(c+4417,"VX_cache genblk5[1] bank reqq_req_writeword_st0", false,-1, 31,0); + vcdp->declQuad(c+14113,"VX_cache genblk5[1] bank reqq_req_tag_st0", false,-1, 41,0); + vcdp->declBit(c+4425,"VX_cache genblk5[1] bank mrvq_pop", false,-1); + vcdp->declBit(c+14129,"VX_cache genblk5[1] bank mrvq_full", false,-1); + vcdp->declBit(c+14137,"VX_cache genblk5[1] bank mrvq_stop", false,-1); + vcdp->declBit(c+4433,"VX_cache genblk5[1] bank mrvq_valid_st0", false,-1); + vcdp->declBus(c+14145,"VX_cache genblk5[1] bank mrvq_tid_st0", false,-1, 1,0); + vcdp->declBus(c+14153,"VX_cache genblk5[1] bank mrvq_addr_st0", false,-1, 25,0); + vcdp->declBus(c+14161,"VX_cache genblk5[1] bank mrvq_wsel_st0", false,-1, 1,0); + vcdp->declBus(c+14169,"VX_cache genblk5[1] bank mrvq_writeword_st0", false,-1, 31,0); + vcdp->declQuad(c+14177,"VX_cache genblk5[1] bank mrvq_tag_st0", false,-1, 41,0); + vcdp->declBit(c+4441,"VX_cache genblk5[1] bank mrvq_rw_st0", false,-1); + vcdp->declBus(c+14193,"VX_cache genblk5[1] bank mrvq_byteen_st0", false,-1, 3,0); + vcdp->declBit(c+14201,"VX_cache genblk5[1] bank mrvq_is_snp_st0", false,-1); + vcdp->declBit(c+14209,"VX_cache genblk5[1] bank mrvq_snp_invalidate_st0", false,-1); + vcdp->declBit(c+4449,"VX_cache genblk5[1] bank mrvq_pending_hazard_st1e", false,-1); + vcdp->declBit(c+4457,"VX_cache genblk5[1] bank st2_pending_hazard_st1e", false,-1); + vcdp->declBit(c+4465,"VX_cache genblk5[1] bank force_request_miss_st1e", false,-1); + vcdp->declBus(c+14217,"VX_cache genblk5[1] bank miss_add_tid", false,-1, 1,0); + vcdp->declQuad(c+14225,"VX_cache genblk5[1] bank miss_add_tag", false,-1, 41,0); + vcdp->declBit(c+14241,"VX_cache genblk5[1] bank miss_add_rw", false,-1); + vcdp->declBus(c+14249,"VX_cache genblk5[1] bank miss_add_byteen", false,-1, 3,0); + vcdp->declBus(c+10129,"VX_cache genblk5[1] bank addr_st2", false,-1, 25,0); + vcdp->declBit(c+14257,"VX_cache genblk5[1] bank is_fill_st2", false,-1); + vcdp->declBit(c+4473,"VX_cache genblk5[1] bank recover_mrvq_state_st2", false,-1); + vcdp->declBit(c+4481,"VX_cache genblk5[1] bank mrvq_push_stall", false,-1); + vcdp->declBit(c+4489,"VX_cache genblk5[1] bank cwbq_push_stall", false,-1); + vcdp->declBit(c+4497,"VX_cache genblk5[1] bank dwbq_push_stall", false,-1); + vcdp->declBit(c+4505,"VX_cache genblk5[1] bank dram_fill_req_stall", false,-1); + vcdp->declBit(c+4513,"VX_cache genblk5[1] bank stall_bank_pipe", false,-1); + vcdp->declBit(c+4521,"VX_cache genblk5[1] bank is_fill_in_pipe", false,-1); + {int i; for (i=0; i<1; i++) { + vcdp->declBit(c+4529+i*1,"VX_cache genblk5[1] bank is_fill_st1", true,(i+0));}} + {int i; for (i=0; i<1; i++) { + vcdp->declBit(c+4537+i*1,"VX_cache genblk5[1] bank going_to_write_st1", true,(i+0));}} + vcdp->declBus(c+25161,"VX_cache genblk5[1] bank j", false,-1, 31,0); + vcdp->declBit(c+4433,"VX_cache genblk5[1] bank mrvq_pop_unqual", false,-1); + vcdp->declBit(c+4545,"VX_cache genblk5[1] bank dfpq_pop_unqual", false,-1); + vcdp->declBit(c+4553,"VX_cache genblk5[1] bank reqq_pop_unqual", false,-1); + vcdp->declBit(c+4561,"VX_cache genblk5[1] bank snrq_pop_unqual", false,-1); + vcdp->declBit(c+4545,"VX_cache genblk5[1] bank qual_is_fill_st0", false,-1); + vcdp->declBit(c+4569,"VX_cache genblk5[1] bank qual_valid_st0", false,-1); + vcdp->declBus(c+4577,"VX_cache genblk5[1] bank qual_addr_st0", false,-1, 25,0); + vcdp->declBus(c+4585,"VX_cache genblk5[1] bank qual_wsel_st0", false,-1, 1,0); + vcdp->declBit(c+4433,"VX_cache genblk5[1] bank qual_is_mrvq_st0", false,-1); + vcdp->declBus(c+4593,"VX_cache genblk5[1] bank qual_writeword_st0", false,-1, 31,0); + vcdp->declArray(c+4601,"VX_cache genblk5[1] bank qual_writedata_st0", false,-1, 127,0); + vcdp->declQuad(c+4633,"VX_cache genblk5[1] bank qual_inst_meta_st0", false,-1, 48,0); + vcdp->declBit(c+4649,"VX_cache genblk5[1] bank qual_going_to_write_st0", false,-1); + vcdp->declBit(c+4657,"VX_cache genblk5[1] bank qual_is_snp_st0", false,-1); + vcdp->declBit(c+4665,"VX_cache genblk5[1] bank qual_snp_invalidate_st0", false,-1); + {int i; for (i=0; i<1; i++) { + vcdp->declBit(c+4673+i*1,"VX_cache genblk5[1] bank valid_st1", true,(i+0));}} + {int i; for (i=0; i<1; i++) { + vcdp->declBus(c+4681+i*1,"VX_cache genblk5[1] bank addr_st1", true,(i+0), 25,0);}} + {int i; for (i=0; i<1; i++) { + vcdp->declBus(c+4689+i*1,"VX_cache genblk5[1] bank wsel_st1", true,(i+0), 1,0);}} + {int i; for (i=0; i<1; i++) { + vcdp->declBus(c+4697+i*1,"VX_cache genblk5[1] bank writeword_st1", true,(i+0), 31,0);}} + {int i; for (i=0; i<1; i++) { + vcdp->declQuad(c+4705+i*2,"VX_cache genblk5[1] bank inst_meta_st1", true,(i+0), 48,0);}} + {int i; for (i=0; i<1; i++) { + vcdp->declArray(c+4721+i*4,"VX_cache genblk5[1] bank writedata_st1", true,(i+0), 127,0);}} + {int i; for (i=0; i<1; i++) { + vcdp->declBit(c+4753+i*1,"VX_cache genblk5[1] bank is_snp_st1", true,(i+0));}} + {int i; for (i=0; i<1; i++) { + vcdp->declBit(c+4761+i*1,"VX_cache genblk5[1] bank snp_invalidate_st1", true,(i+0));}} + {int i; for (i=0; i<1; i++) { + vcdp->declBit(c+4769+i*1,"VX_cache genblk5[1] bank is_mrvq_st1", true,(i+0));}} + vcdp->declBus(c+4777,"VX_cache genblk5[1] bank readword_st1e", false,-1, 31,0); + vcdp->declArray(c+4785,"VX_cache genblk5[1] bank readdata_st1e", false,-1, 127,0); + vcdp->declBus(c+4817,"VX_cache genblk5[1] bank readtag_st1e", false,-1, 19,0); + vcdp->declBit(c+4825,"VX_cache genblk5[1] bank miss_st1e", false,-1); + vcdp->declBit(c+4833,"VX_cache genblk5[1] bank dirty_st1e", false,-1); + vcdp->declBus(c+4841,"VX_cache genblk5[1] bank dirtyb_st1e", false,-1, 15,0); + vcdp->declQuad(c+4849,"VX_cache genblk5[1] bank tag_st1e", false,-1, 41,0); + vcdp->declBus(c+4865,"VX_cache genblk5[1] bank tid_st1e", false,-1, 1,0); + vcdp->declBit(c+4873,"VX_cache genblk5[1] bank mem_rw_st1e", false,-1); + vcdp->declBus(c+4881,"VX_cache genblk5[1] bank mem_byteen_st1e", false,-1, 3,0); + vcdp->declBit(c+4889,"VX_cache genblk5[1] bank fill_saw_dirty_st1e", false,-1); + vcdp->declBit(c+4897,"VX_cache genblk5[1] bank is_snp_st1e", false,-1); + vcdp->declBit(c+4905,"VX_cache genblk5[1] bank snp_invalidate_st1e", false,-1); + vcdp->declBit(c+4913,"VX_cache genblk5[1] bank snp_to_mrvq_st1e", false,-1); + vcdp->declBit(c+4921,"VX_cache genblk5[1] bank mrvq_init_ready_state_st1e", false,-1); + vcdp->declBit(c+4929,"VX_cache genblk5[1] bank miss_add_because_miss", false,-1); + vcdp->declBit(c+4937,"VX_cache genblk5[1] bank valid_st1e", false,-1); + vcdp->declBit(c+4945,"VX_cache genblk5[1] bank is_mrvq_st1e", false,-1); + vcdp->declBit(c+4953,"VX_cache genblk5[1] bank mrvq_recover_ready_state_st1e", false,-1); + vcdp->declBus(c+4961,"VX_cache genblk5[1] bank addr_st1e", false,-1, 25,0); + vcdp->declBit(c+4969,"VX_cache genblk5[1] bank qual_valid_st1e_2", false,-1); + vcdp->declBit(c+4945,"VX_cache genblk5[1] bank is_mrvq_st1e_st2", false,-1); + vcdp->declBit(c+14265,"VX_cache genblk5[1] bank valid_st2", false,-1); + vcdp->declBus(c+14273,"VX_cache genblk5[1] bank wsel_st2", false,-1, 1,0); + vcdp->declBus(c+14281,"VX_cache genblk5[1] bank writeword_st2", false,-1, 31,0); + vcdp->declBus(c+14289,"VX_cache genblk5[1] bank readword_st2", false,-1, 31,0); + vcdp->declArray(c+14297,"VX_cache genblk5[1] bank readdata_st2", false,-1, 127,0); + vcdp->declBit(c+14329,"VX_cache genblk5[1] bank miss_st2", false,-1); + vcdp->declBit(c+14337,"VX_cache genblk5[1] bank dirty_st2", false,-1); + vcdp->declBus(c+14345,"VX_cache genblk5[1] bank dirtyb_st2", false,-1, 15,0); + vcdp->declQuad(c+14353,"VX_cache genblk5[1] bank inst_meta_st2", false,-1, 48,0); + vcdp->declBus(c+14369,"VX_cache genblk5[1] bank readtag_st2", false,-1, 19,0); + vcdp->declBit(c+14377,"VX_cache genblk5[1] bank fill_saw_dirty_st2", false,-1); + vcdp->declBit(c+14385,"VX_cache genblk5[1] bank is_snp_st2", false,-1); + vcdp->declBit(c+14393,"VX_cache genblk5[1] bank snp_invalidate_st2", false,-1); + vcdp->declBit(c+14401,"VX_cache genblk5[1] bank snp_to_mrvq_st2", false,-1); + vcdp->declBit(c+14409,"VX_cache genblk5[1] bank is_mrvq_st2", false,-1); + vcdp->declBit(c+4977,"VX_cache genblk5[1] bank mrvq_init_ready_state_st2", false,-1); + vcdp->declBit(c+14417,"VX_cache genblk5[1] bank mrvq_recover_ready_state_st2", false,-1); + vcdp->declBit(c+14425,"VX_cache genblk5[1] bank mrvq_init_ready_state_unqual_st2", false,-1); + vcdp->declBit(c+4985,"VX_cache genblk5[1] bank mrvq_init_ready_state_hazard_st0_st1", false,-1); + vcdp->declBit(c+4993,"VX_cache genblk5[1] bank mrvq_init_ready_state_hazard_st1e_st1", false,-1); + vcdp->declBit(c+14401,"VX_cache genblk5[1] bank miss_add_because_pending", false,-1); + vcdp->declBit(c+5001,"VX_cache genblk5[1] bank miss_add_unqual", false,-1); + vcdp->declBit(c+5009,"VX_cache genblk5[1] bank miss_add", false,-1); + vcdp->declBus(c+10129,"VX_cache genblk5[1] bank miss_add_addr", false,-1, 25,0); + vcdp->declBus(c+14273,"VX_cache genblk5[1] bank miss_add_wsel", false,-1, 1,0); + vcdp->declBus(c+14281,"VX_cache genblk5[1] bank miss_add_data", false,-1, 31,0); + vcdp->declBit(c+14385,"VX_cache genblk5[1] bank miss_add_is_snp", false,-1); + vcdp->declBit(c+14393,"VX_cache genblk5[1] bank miss_add_snp_invalidate", false,-1); + vcdp->declBit(c+5017,"VX_cache genblk5[1] bank miss_add_is_mrvq", false,-1); + vcdp->declBit(c+5025,"VX_cache genblk5[1] bank cwbq_push", false,-1); + vcdp->declBit(c+1001,"VX_cache genblk5[1] bank cwbq_pop", false,-1); + vcdp->declBit(c+14433,"VX_cache genblk5[1] bank cwbq_empty", false,-1); + vcdp->declBit(c+14441,"VX_cache genblk5[1] bank cwbq_full", false,-1); + vcdp->declBit(c+5033,"VX_cache genblk5[1] bank cwbq_push_unqual", false,-1); + vcdp->declBus(c+14289,"VX_cache genblk5[1] bank cwbq_data", false,-1, 31,0); + vcdp->declBus(c+14217,"VX_cache genblk5[1] bank cwbq_tid", false,-1, 1,0); + vcdp->declQuad(c+14225,"VX_cache genblk5[1] bank cwbq_tag", false,-1, 41,0); + vcdp->declBit(c+5001,"VX_cache genblk5[1] bank dram_fill_req_fast", false,-1); + vcdp->declBit(c+5041,"VX_cache genblk5[1] bank dram_fill_req_unqual", false,-1); + vcdp->declBit(c+5049,"VX_cache genblk5[1] bank dwbq_push", false,-1); + vcdp->declBit(c+1009,"VX_cache genblk5[1] bank dwbq_pop", false,-1); + vcdp->declBit(c+14449,"VX_cache genblk5[1] bank dwbq_empty", false,-1); + vcdp->declBit(c+14457,"VX_cache genblk5[1] bank dwbq_full", false,-1); + vcdp->declBit(c+5057,"VX_cache genblk5[1] bank dwbq_is_dwb_in", false,-1); + vcdp->declBit(c+5065,"VX_cache genblk5[1] bank dwbq_is_snp_in", false,-1); + vcdp->declBit(c+5073,"VX_cache genblk5[1] bank dwbq_is_dwb_out", false,-1); + vcdp->declBit(c+5081,"VX_cache genblk5[1] bank dwbq_is_snp_out", false,-1); + vcdp->declBit(c+5089,"VX_cache genblk5[1] bank dwbq_push_unqual", false,-1); + vcdp->declBus(c+14465,"VX_cache genblk5[1] bank dwbq_req_addr", false,-1, 25,0); + vcdp->declBus(c+14473,"VX_cache genblk5[1] bank snrq_tag_st2", false,-1, 27,0); + vcdp->declBit(c+377,"VX_cache genblk5[1] bank dram_wb_req_fire", false,-1); + vcdp->declBit(c+385,"VX_cache genblk5[1] bank snp_rsp_fire", false,-1); + vcdp->declBit(c+14481,"VX_cache genblk5[1] bank dwbq_dual_valid_sel", false,-1); + vcdp->declBus(c+25169,"VX_cache genblk5[1] bank snp_req_queue DATAW", false,-1, 31,0); + vcdp->declBus(c+25073,"VX_cache genblk5[1] bank snp_req_queue SIZE", false,-1, 31,0); + vcdp->declBus(c+25089,"VX_cache genblk5[1] bank snp_req_queue BUFFERED_OUTPUT", false,-1, 31,0); + vcdp->declBit(c+24489,"VX_cache genblk5[1] bank snp_req_queue clk", false,-1); + vcdp->declBit(c+24497,"VX_cache genblk5[1] bank snp_req_queue reset", false,-1); + vcdp->declBit(c+25001,"VX_cache genblk5[1] bank snp_req_queue push", false,-1); + vcdp->declBit(c+4281,"VX_cache genblk5[1] bank snp_req_queue pop", false,-1); + vcdp->declQuad(c+393,"VX_cache genblk5[1] bank snp_req_queue data_in", false,-1, 54,0); + vcdp->declQuad(c+5097,"VX_cache genblk5[1] bank snp_req_queue data_out", false,-1, 54,0); + vcdp->declBit(c+14073,"VX_cache genblk5[1] bank snp_req_queue empty", false,-1); + vcdp->declBit(c+14081,"VX_cache genblk5[1] bank snp_req_queue full", false,-1); + vcdp->declBus(c+14489,"VX_cache genblk5[1] bank snp_req_queue size", false,-1, 4,0); + vcdp->declBus(c+14489,"VX_cache genblk5[1] bank snp_req_queue size_r", false,-1, 4,0); + vcdp->declBit(c+5113,"VX_cache genblk5[1] bank snp_req_queue reading", false,-1); + vcdp->declBit(c+409,"VX_cache genblk5[1] bank snp_req_queue writing", false,-1); + {int i; for (i=0; i<16; i++) { + vcdp->declQuad(c+14497+i*2,"VX_cache genblk5[1] bank snp_req_queue genblk3 data", true,(i+0), 54,0);}} + vcdp->declQuad(c+14753,"VX_cache genblk5[1] bank snp_req_queue genblk3 genblk2 head_r", false,-1, 54,0); + vcdp->declQuad(c+14769,"VX_cache genblk5[1] bank snp_req_queue genblk3 genblk2 curr_r", false,-1, 54,0); + vcdp->declBus(c+14785,"VX_cache genblk5[1] bank snp_req_queue genblk3 genblk2 wr_ptr_r", false,-1, 3,0); + vcdp->declBus(c+14793,"VX_cache genblk5[1] bank snp_req_queue genblk3 genblk2 rd_ptr_r", false,-1, 3,0); + vcdp->declBus(c+14801,"VX_cache genblk5[1] bank snp_req_queue genblk3 genblk2 rd_ptr_next_r", false,-1, 3,0); + vcdp->declBit(c+14073,"VX_cache genblk5[1] bank snp_req_queue genblk3 genblk2 empty_r", false,-1); + vcdp->declBit(c+14081,"VX_cache genblk5[1] bank snp_req_queue genblk3 genblk2 full_r", false,-1); + vcdp->declBit(c+14809,"VX_cache genblk5[1] bank snp_req_queue genblk3 genblk2 bypass_r", false,-1); + vcdp->declBus(c+25177,"VX_cache genblk5[1] bank dfp_queue DATAW", false,-1, 31,0); + vcdp->declBus(c+25073,"VX_cache genblk5[1] bank dfp_queue SIZE", false,-1, 31,0); + vcdp->declBus(c+25089,"VX_cache genblk5[1] bank dfp_queue BUFFERED_OUTPUT", false,-1, 31,0); + vcdp->declBit(c+24489,"VX_cache genblk5[1] bank dfp_queue clk", false,-1); + vcdp->declBit(c+24497,"VX_cache genblk5[1] bank dfp_queue reset", false,-1); + vcdp->declBit(c+24993,"VX_cache genblk5[1] bank dfp_queue push", false,-1); + vcdp->declBit(c+4313,"VX_cache genblk5[1] bank dfp_queue pop", false,-1); + vcdp->declArray(c+417,"VX_cache genblk5[1] bank dfp_queue data_in", false,-1, 153,0); + vcdp->declArray(c+5121,"VX_cache genblk5[1] bank dfp_queue data_out", false,-1, 153,0); + vcdp->declBit(c+14089,"VX_cache genblk5[1] bank dfp_queue empty", false,-1); + vcdp->declBit(c+14097,"VX_cache genblk5[1] bank dfp_queue full", false,-1); + vcdp->declBus(c+14817,"VX_cache genblk5[1] bank dfp_queue size", false,-1, 4,0); + vcdp->declBus(c+14817,"VX_cache genblk5[1] bank dfp_queue size_r", false,-1, 4,0); + vcdp->declBit(c+5161,"VX_cache genblk5[1] bank dfp_queue reading", false,-1); + vcdp->declBit(c+457,"VX_cache genblk5[1] bank dfp_queue writing", false,-1); + {int i; for (i=0; i<16; i++) { + vcdp->declArray(c+14825+i*5,"VX_cache genblk5[1] bank dfp_queue genblk3 data", true,(i+0), 153,0);}} + vcdp->declArray(c+15465,"VX_cache genblk5[1] bank dfp_queue genblk3 genblk2 head_r", false,-1, 153,0); + vcdp->declArray(c+15505,"VX_cache genblk5[1] bank dfp_queue genblk3 genblk2 curr_r", false,-1, 153,0); + vcdp->declBus(c+15545,"VX_cache genblk5[1] bank dfp_queue genblk3 genblk2 wr_ptr_r", false,-1, 3,0); + vcdp->declBus(c+15553,"VX_cache genblk5[1] bank dfp_queue genblk3 genblk2 rd_ptr_r", false,-1, 3,0); + vcdp->declBus(c+15561,"VX_cache genblk5[1] bank dfp_queue genblk3 genblk2 rd_ptr_next_r", false,-1, 3,0); + vcdp->declBit(c+14089,"VX_cache genblk5[1] bank dfp_queue genblk3 genblk2 empty_r", false,-1); + vcdp->declBit(c+14097,"VX_cache genblk5[1] bank dfp_queue genblk3 genblk2 full_r", false,-1); + vcdp->declBit(c+15569,"VX_cache genblk5[1] bank dfp_queue genblk3 genblk2 bypass_r", false,-1); + vcdp->declBus(c+25081,"VX_cache genblk5[1] bank core_req_arb WORD_SIZE", false,-1, 31,0); + vcdp->declBus(c+25081,"VX_cache genblk5[1] bank core_req_arb NUM_REQUESTS", false,-1, 31,0); + vcdp->declBus(c+25081,"VX_cache genblk5[1] bank core_req_arb CREQ_SIZE", false,-1, 31,0); + vcdp->declBus(c+25097,"VX_cache genblk5[1] bank core_req_arb CORE_TAG_WIDTH", false,-1, 31,0); + vcdp->declBus(c+25105,"VX_cache genblk5[1] bank core_req_arb CORE_TAG_ID_BITS", false,-1, 31,0); + vcdp->declBit(c+24489,"VX_cache genblk5[1] bank core_req_arb clk", false,-1); + vcdp->declBit(c+24497,"VX_cache genblk5[1] bank core_req_arb reset", false,-1); + vcdp->declBit(c+993,"VX_cache genblk5[1] bank core_req_arb reqq_push", false,-1); + vcdp->declBus(c+65,"VX_cache genblk5[1] bank core_req_arb bank_valids", false,-1, 3,0); + vcdp->declBus(c+24513,"VX_cache genblk5[1] bank core_req_arb bank_rw", false,-1, 3,0); + vcdp->declBus(c+24521,"VX_cache genblk5[1] bank core_req_arb bank_byteen", false,-1, 15,0); + vcdp->declArray(c+24561,"VX_cache genblk5[1] bank core_req_arb bank_writedata", false,-1, 127,0); + vcdp->declArray(c+24529,"VX_cache genblk5[1] bank core_req_arb bank_addr", false,-1, 119,0); + vcdp->declQuad(c+24593,"VX_cache genblk5[1] bank core_req_arb bank_tag", false,-1, 41,0); + vcdp->declBit(c+4361,"VX_cache genblk5[1] bank core_req_arb reqq_pop", false,-1); + vcdp->declBit(c+4377,"VX_cache genblk5[1] bank core_req_arb reqq_req_st0", false,-1); + vcdp->declBus(c+4385,"VX_cache genblk5[1] bank core_req_arb reqq_req_tid_st0", false,-1, 1,0); + vcdp->declBit(c+4393,"VX_cache genblk5[1] bank core_req_arb reqq_req_rw_st0", false,-1); + vcdp->declBus(c+4401,"VX_cache genblk5[1] bank core_req_arb reqq_req_byteen_st0", false,-1, 3,0); + vcdp->declBus(c+4409,"VX_cache genblk5[1] bank core_req_arb reqq_req_addr_st0", false,-1, 29,0); + vcdp->declBus(c+4417,"VX_cache genblk5[1] bank core_req_arb reqq_req_writedata_st0", false,-1, 31,0); + vcdp->declQuad(c+14113,"VX_cache genblk5[1] bank core_req_arb reqq_req_tag_st0", false,-1, 41,0); + vcdp->declBit(c+4369,"VX_cache genblk5[1] bank core_req_arb reqq_empty", false,-1); + vcdp->declBit(c+14105,"VX_cache genblk5[1] bank core_req_arb reqq_full", false,-1); + vcdp->declBus(c+5169,"VX_cache genblk5[1] bank core_req_arb out_per_valids", false,-1, 3,0); + vcdp->declBus(c+5177,"VX_cache genblk5[1] bank core_req_arb out_per_rw", false,-1, 3,0); + vcdp->declBus(c+5185,"VX_cache genblk5[1] bank core_req_arb out_per_byteen", false,-1, 15,0); + vcdp->declArray(c+5193,"VX_cache genblk5[1] bank core_req_arb out_per_addr", false,-1, 119,0); + vcdp->declArray(c+5225,"VX_cache genblk5[1] bank core_req_arb out_per_writedata", false,-1, 127,0); + vcdp->declQuad(c+5257,"VX_cache genblk5[1] bank core_req_arb out_per_tag", false,-1, 41,0); + vcdp->declBus(c+15577,"VX_cache genblk5[1] bank core_req_arb use_per_valids", false,-1, 3,0); + vcdp->declBus(c+15585,"VX_cache genblk5[1] bank core_req_arb use_per_rw", false,-1, 3,0); + vcdp->declBus(c+15593,"VX_cache genblk5[1] bank core_req_arb use_per_byteen", false,-1, 15,0); + vcdp->declArray(c+15601,"VX_cache genblk5[1] bank core_req_arb use_per_addr", false,-1, 119,0); + vcdp->declArray(c+15633,"VX_cache genblk5[1] bank core_req_arb use_per_writedata", false,-1, 127,0); + vcdp->declQuad(c+14113,"VX_cache genblk5[1] bank core_req_arb use_per_tag", false,-1, 41,0); + vcdp->declBus(c+15577,"VX_cache genblk5[1] bank core_req_arb qual_valids", false,-1, 3,0); + vcdp->declBus(c+15585,"VX_cache genblk5[1] bank core_req_arb qual_rw", false,-1, 3,0); + vcdp->declBus(c+15593,"VX_cache genblk5[1] bank core_req_arb qual_byteen", false,-1, 15,0); + vcdp->declArray(c+15601,"VX_cache genblk5[1] bank core_req_arb qual_addr", false,-1, 119,0); + vcdp->declArray(c+15633,"VX_cache genblk5[1] bank core_req_arb qual_writedata", false,-1, 127,0); + vcdp->declQuad(c+14113,"VX_cache genblk5[1] bank core_req_arb qual_tag", false,-1, 41,0); + vcdp->declBit(c+15665,"VX_cache genblk5[1] bank core_req_arb o_empty", false,-1); + vcdp->declBit(c+15673,"VX_cache genblk5[1] bank core_req_arb use_empty", false,-1); + vcdp->declBit(c+5273,"VX_cache genblk5[1] bank core_req_arb out_empty", false,-1); + vcdp->declBit(c+1017,"VX_cache genblk5[1] bank core_req_arb push_qual", false,-1); + vcdp->declBit(c+5281,"VX_cache genblk5[1] bank core_req_arb pop_qual", false,-1); + vcdp->declBus(c+5289,"VX_cache genblk5[1] bank core_req_arb real_out_per_valids", false,-1, 3,0); + vcdp->declBus(c+4385,"VX_cache genblk5[1] bank core_req_arb qual_request_index", false,-1, 1,0); + vcdp->declBit(c+4377,"VX_cache genblk5[1] bank core_req_arb qual_has_request", false,-1); + vcdp->declBus(c+25185,"VX_cache genblk5[1] bank core_req_arb reqq_queue DATAW", false,-1, 31,0); + vcdp->declBus(c+25081,"VX_cache genblk5[1] bank core_req_arb reqq_queue SIZE", false,-1, 31,0); + vcdp->declBus(c+25089,"VX_cache genblk5[1] bank core_req_arb reqq_queue BUFFERED_OUTPUT", false,-1, 31,0); + vcdp->declBit(c+24489,"VX_cache genblk5[1] bank core_req_arb reqq_queue clk", false,-1); + vcdp->declBit(c+24497,"VX_cache genblk5[1] bank core_req_arb reqq_queue reset", false,-1); + vcdp->declBit(c+1017,"VX_cache genblk5[1] bank core_req_arb reqq_queue push", false,-1); + vcdp->declBit(c+5281,"VX_cache genblk5[1] bank core_req_arb reqq_queue pop", false,-1); + vcdp->declArray(c+465,"VX_cache genblk5[1] bank core_req_arb reqq_queue data_in", false,-1, 313,0); + vcdp->declArray(c+5297,"VX_cache genblk5[1] bank core_req_arb reqq_queue data_out", false,-1, 313,0); + vcdp->declBit(c+15665,"VX_cache genblk5[1] bank core_req_arb reqq_queue empty", false,-1); + vcdp->declBit(c+14105,"VX_cache genblk5[1] bank core_req_arb reqq_queue full", false,-1); + vcdp->declBus(c+15681,"VX_cache genblk5[1] bank core_req_arb reqq_queue size", false,-1, 2,0); + vcdp->declBus(c+15681,"VX_cache genblk5[1] bank core_req_arb reqq_queue size_r", false,-1, 2,0); + vcdp->declBit(c+5377,"VX_cache genblk5[1] bank core_req_arb reqq_queue reading", false,-1); + vcdp->declBit(c+545,"VX_cache genblk5[1] bank core_req_arb reqq_queue writing", false,-1); + {int i; for (i=0; i<4; i++) { + vcdp->declArray(c+15689+i*10,"VX_cache genblk5[1] bank core_req_arb reqq_queue genblk3 data", true,(i+0), 313,0);}} + vcdp->declArray(c+16009,"VX_cache genblk5[1] bank core_req_arb reqq_queue genblk3 genblk2 head_r", false,-1, 313,0); + vcdp->declArray(c+16089,"VX_cache genblk5[1] bank core_req_arb reqq_queue genblk3 genblk2 curr_r", false,-1, 313,0); + vcdp->declBus(c+16169,"VX_cache genblk5[1] bank core_req_arb reqq_queue genblk3 genblk2 wr_ptr_r", false,-1, 1,0); + vcdp->declBus(c+16177,"VX_cache genblk5[1] bank core_req_arb reqq_queue genblk3 genblk2 rd_ptr_r", false,-1, 1,0); + vcdp->declBus(c+16185,"VX_cache genblk5[1] bank core_req_arb reqq_queue genblk3 genblk2 rd_ptr_next_r", false,-1, 1,0); + vcdp->declBit(c+15665,"VX_cache genblk5[1] bank core_req_arb reqq_queue genblk3 genblk2 empty_r", false,-1); + vcdp->declBit(c+14105,"VX_cache genblk5[1] bank core_req_arb reqq_queue genblk3 genblk2 full_r", false,-1); + vcdp->declBit(c+16193,"VX_cache genblk5[1] bank core_req_arb reqq_queue genblk3 genblk2 bypass_r", false,-1); + vcdp->declBus(c+25081,"VX_cache genblk5[1] bank core_req_arb sel_bank N", false,-1, 31,0); + vcdp->declBit(c+24489,"VX_cache genblk5[1] bank core_req_arb sel_bank clk", false,-1); + vcdp->declBit(c+24497,"VX_cache genblk5[1] bank core_req_arb sel_bank reset", false,-1); + vcdp->declBus(c+15577,"VX_cache genblk5[1] bank core_req_arb sel_bank requests", false,-1, 3,0); + vcdp->declBus(c+4385,"VX_cache genblk5[1] bank core_req_arb sel_bank grant_index", false,-1, 1,0); + vcdp->declBus(c+5385,"VX_cache genblk5[1] bank core_req_arb sel_bank grant_onehot", false,-1, 3,0); + vcdp->declBit(c+4377,"VX_cache genblk5[1] bank core_req_arb sel_bank grant_valid", false,-1); + vcdp->declBus(c+5385,"VX_cache genblk5[1] bank core_req_arb sel_bank genblk2 grant_onehot_r", false,-1, 3,0); + vcdp->declBus(c+25081,"VX_cache genblk5[1] bank core_req_arb sel_bank genblk2 priority_encoder N", false,-1, 31,0); + vcdp->declBus(c+15577,"VX_cache genblk5[1] bank core_req_arb sel_bank genblk2 priority_encoder data_in", false,-1, 3,0); + vcdp->declBus(c+4385,"VX_cache genblk5[1] bank core_req_arb sel_bank genblk2 priority_encoder data_out", false,-1, 1,0); + vcdp->declBit(c+4377,"VX_cache genblk5[1] bank core_req_arb sel_bank genblk2 priority_encoder valid_out", false,-1); + vcdp->declBus(c+5393,"VX_cache genblk5[1] bank core_req_arb sel_bank genblk2 priority_encoder i", false,-1, 31,0); + vcdp->declBus(c+25193,"VX_cache genblk5[1] bank s0_1_c0 N", false,-1, 31,0); + vcdp->declBus(c+25057,"VX_cache genblk5[1] bank s0_1_c0 PASSTHRU", false,-1, 31,0); + vcdp->declBit(c+24489,"VX_cache genblk5[1] bank s0_1_c0 clk", false,-1); + vcdp->declBit(c+24497,"VX_cache genblk5[1] bank s0_1_c0 reset", false,-1); + vcdp->declBit(c+4513,"VX_cache genblk5[1] bank s0_1_c0 stall", false,-1); + vcdp->declBit(c+25137,"VX_cache genblk5[1] bank s0_1_c0 flush", false,-1); + vcdp->declArray(c+5401,"VX_cache genblk5[1] bank s0_1_c0 in", false,-1, 242,0); + vcdp->declArray(c+16201,"VX_cache genblk5[1] bank s0_1_c0 out", false,-1, 242,0); + vcdp->declArray(c+16201,"VX_cache genblk5[1] bank s0_1_c0 value", false,-1, 242,0); + vcdp->declBus(c+25065,"VX_cache genblk5[1] bank tag_data_access CACHE_SIZE", false,-1, 31,0); + vcdp->declBus(c+25073,"VX_cache genblk5[1] bank tag_data_access BANK_LINE_SIZE", false,-1, 31,0); + vcdp->declBus(c+25081,"VX_cache genblk5[1] bank tag_data_access NUM_BANKS", false,-1, 31,0); + vcdp->declBus(c+25081,"VX_cache genblk5[1] bank tag_data_access WORD_SIZE", false,-1, 31,0); + vcdp->declBus(c+25089,"VX_cache genblk5[1] bank tag_data_access STAGE_1_CYCLES", false,-1, 31,0); + vcdp->declBus(c+25089,"VX_cache genblk5[1] bank tag_data_access WRITE_ENABLE", false,-1, 31,0); + vcdp->declBus(c+25089,"VX_cache genblk5[1] bank tag_data_access DRAM_ENABLE", false,-1, 31,0); + vcdp->declBit(c+24489,"VX_cache genblk5[1] bank tag_data_access clk", false,-1); + vcdp->declBit(c+24497,"VX_cache genblk5[1] bank tag_data_access reset", false,-1); + vcdp->declBit(c+4513,"VX_cache genblk5[1] bank tag_data_access stall", false,-1); + vcdp->declBit(c+4897,"VX_cache genblk5[1] bank tag_data_access is_snp_st1e", false,-1); + vcdp->declBit(c+4905,"VX_cache genblk5[1] bank tag_data_access snp_invalidate_st1e", false,-1); + vcdp->declBit(c+4513,"VX_cache genblk5[1] bank tag_data_access stall_bank_pipe", false,-1); + vcdp->declBit(c+4465,"VX_cache genblk5[1] bank tag_data_access force_request_miss_st1e", false,-1); + vcdp->declBus(c+5465,"VX_cache genblk5[1] bank tag_data_access readaddr_st10", false,-1, 5,0); + vcdp->declBus(c+4961,"VX_cache genblk5[1] bank tag_data_access writeaddr_st1e", false,-1, 25,0); + vcdp->declBit(c+4937,"VX_cache genblk5[1] bank tag_data_access valid_req_st1e", false,-1); + vcdp->declBit(c+5473,"VX_cache genblk5[1] bank tag_data_access writefill_st1e", false,-1); + vcdp->declBus(c+5481,"VX_cache genblk5[1] bank tag_data_access writeword_st1e", false,-1, 31,0); + vcdp->declArray(c+5489,"VX_cache genblk5[1] bank tag_data_access writedata_st1e", false,-1, 127,0); + vcdp->declBit(c+4873,"VX_cache genblk5[1] bank tag_data_access mem_rw_st1e", false,-1); + vcdp->declBus(c+4881,"VX_cache genblk5[1] bank tag_data_access mem_byteen_st1e", false,-1, 3,0); + vcdp->declBus(c+5521,"VX_cache genblk5[1] bank tag_data_access wordsel_st1e", false,-1, 1,0); + vcdp->declBus(c+4777,"VX_cache genblk5[1] bank tag_data_access readword_st1e", false,-1, 31,0); + vcdp->declArray(c+4785,"VX_cache genblk5[1] bank tag_data_access readdata_st1e", false,-1, 127,0); + vcdp->declBus(c+4817,"VX_cache genblk5[1] bank tag_data_access readtag_st1e", false,-1, 19,0); + vcdp->declBit(c+4825,"VX_cache genblk5[1] bank tag_data_access miss_st1e", false,-1); + vcdp->declBit(c+4833,"VX_cache genblk5[1] bank tag_data_access dirty_st1e", false,-1); + vcdp->declBus(c+4841,"VX_cache genblk5[1] bank tag_data_access dirtyb_st1e", false,-1, 15,0); + vcdp->declBit(c+4889,"VX_cache genblk5[1] bank tag_data_access fill_saw_dirty_st1e", false,-1); + vcdp->declBit(c+4913,"VX_cache genblk5[1] bank tag_data_access snp_to_mrvq_st1e", false,-1); + vcdp->declBit(c+4921,"VX_cache genblk5[1] bank tag_data_access mrvq_init_ready_state_st1e", false,-1); + {int i; for (i=0; i<1; i++) { + vcdp->declBit(c+5529+i*1,"VX_cache genblk5[1] bank tag_data_access read_valid_st1c", true,(i+0));}} + {int i; for (i=0; i<1; i++) { + vcdp->declBit(c+5537+i*1,"VX_cache genblk5[1] bank tag_data_access read_dirty_st1c", true,(i+0));}} + {int i; for (i=0; i<1; i++) { + vcdp->declBus(c+5545+i*1,"VX_cache genblk5[1] bank tag_data_access read_dirtyb_st1c", true,(i+0), 15,0);}} + {int i; for (i=0; i<1; i++) { + vcdp->declBus(c+5553+i*1,"VX_cache genblk5[1] bank tag_data_access read_tag_st1c", true,(i+0), 19,0);}} + {int i; for (i=0; i<1; i++) { + vcdp->declArray(c+5561+i*4,"VX_cache genblk5[1] bank tag_data_access read_data_st1c", true,(i+0), 127,0);}} + vcdp->declBit(c+5593,"VX_cache genblk5[1] bank tag_data_access qual_read_valid_st1", false,-1); + vcdp->declBit(c+5601,"VX_cache genblk5[1] bank tag_data_access qual_read_dirty_st1", false,-1); + vcdp->declBus(c+5609,"VX_cache genblk5[1] bank tag_data_access qual_read_dirtyb_st1", false,-1, 15,0); + vcdp->declBus(c+5617,"VX_cache genblk5[1] bank tag_data_access qual_read_tag_st1", false,-1, 19,0); + vcdp->declArray(c+5625,"VX_cache genblk5[1] bank tag_data_access qual_read_data_st1", false,-1, 127,0); + vcdp->declBit(c+5657,"VX_cache genblk5[1] bank tag_data_access use_read_valid_st1e", false,-1); + vcdp->declBit(c+5665,"VX_cache genblk5[1] bank tag_data_access use_read_dirty_st1e", false,-1); + vcdp->declBus(c+4841,"VX_cache genblk5[1] bank tag_data_access use_read_dirtyb_st1e", false,-1, 15,0); + vcdp->declBus(c+4817,"VX_cache genblk5[1] bank tag_data_access use_read_tag_st1e", false,-1, 19,0); + vcdp->declArray(c+4785,"VX_cache genblk5[1] bank tag_data_access use_read_data_st1e", false,-1, 127,0); + vcdp->declBus(c+5673,"VX_cache genblk5[1] bank tag_data_access use_write_enable", false,-1, 15,0); + vcdp->declArray(c+5681,"VX_cache genblk5[1] bank tag_data_access use_write_data", false,-1, 127,0); + vcdp->declBit(c+4825,"VX_cache genblk5[1] bank tag_data_access fill_sent", false,-1); + vcdp->declBit(c+5713,"VX_cache genblk5[1] bank tag_data_access invalidate_line", false,-1); + vcdp->declBit(c+5721,"VX_cache genblk5[1] bank tag_data_access tags_match", false,-1); + vcdp->declBit(c+5729,"VX_cache genblk5[1] bank tag_data_access real_writefill", false,-1); + vcdp->declBus(c+5737,"VX_cache genblk5[1] bank tag_data_access writetag_st1e", false,-1, 19,0); + vcdp->declBus(c+5465,"VX_cache genblk5[1] bank tag_data_access writeladdr_st1e", false,-1, 5,0); + vcdp->declBus(c+5745,"VX_cache genblk5[1] bank tag_data_access we", false,-1, 15,0); + vcdp->declArray(c+5681,"VX_cache genblk5[1] bank tag_data_access data_write", false,-1, 127,0); + vcdp->declBit(c+5753,"VX_cache genblk5[1] bank tag_data_access should_write", false,-1); + vcdp->declBit(c+5713,"VX_cache genblk5[1] bank tag_data_access snoop_hit_no_pending", false,-1); + vcdp->declBit(c+5761,"VX_cache genblk5[1] bank tag_data_access req_invalid", false,-1); + vcdp->declBit(c+5769,"VX_cache genblk5[1] bank tag_data_access req_miss", false,-1); + vcdp->declBit(c+5777,"VX_cache genblk5[1] bank tag_data_access real_miss", false,-1); + vcdp->declBit(c+5785,"VX_cache genblk5[1] bank tag_data_access force_core_miss", false,-1); + vcdp->declBit(c+5793,"VX_cache genblk5[1] bank tag_data_access genblk4[0] normal_write", false,-1); + vcdp->declBit(c+5801,"VX_cache genblk5[1] bank tag_data_access genblk4[1] normal_write", false,-1); + vcdp->declBit(c+5809,"VX_cache genblk5[1] bank tag_data_access genblk4[2] normal_write", false,-1); + vcdp->declBit(c+5817,"VX_cache genblk5[1] bank tag_data_access genblk4[3] normal_write", false,-1); + vcdp->declBus(c+25065,"VX_cache genblk5[1] bank tag_data_access tag_data_structure CACHE_SIZE", false,-1, 31,0); + vcdp->declBus(c+25073,"VX_cache genblk5[1] bank tag_data_access tag_data_structure BANK_LINE_SIZE", false,-1, 31,0); + vcdp->declBus(c+25081,"VX_cache genblk5[1] bank tag_data_access tag_data_structure NUM_BANKS", false,-1, 31,0); + vcdp->declBus(c+25081,"VX_cache genblk5[1] bank tag_data_access tag_data_structure WORD_SIZE", false,-1, 31,0); + vcdp->declBit(c+24489,"VX_cache genblk5[1] bank tag_data_access tag_data_structure clk", false,-1); + vcdp->declBit(c+24497,"VX_cache genblk5[1] bank tag_data_access tag_data_structure reset", false,-1); + vcdp->declBit(c+4513,"VX_cache genblk5[1] bank tag_data_access tag_data_structure stall_bank_pipe", false,-1); + vcdp->declBus(c+5465,"VX_cache genblk5[1] bank tag_data_access tag_data_structure read_addr", false,-1, 5,0); + vcdp->declBit(c+5593,"VX_cache genblk5[1] bank tag_data_access tag_data_structure read_valid", false,-1); + vcdp->declBit(c+5601,"VX_cache genblk5[1] bank tag_data_access tag_data_structure read_dirty", false,-1); + vcdp->declBus(c+5609,"VX_cache genblk5[1] bank tag_data_access tag_data_structure read_dirtyb", false,-1, 15,0); + vcdp->declBus(c+5617,"VX_cache genblk5[1] bank tag_data_access tag_data_structure read_tag", false,-1, 19,0); + vcdp->declArray(c+5625,"VX_cache genblk5[1] bank tag_data_access tag_data_structure read_data", false,-1, 127,0); + vcdp->declBit(c+5713,"VX_cache genblk5[1] bank tag_data_access tag_data_structure invalidate", false,-1); + vcdp->declBus(c+5673,"VX_cache genblk5[1] bank tag_data_access tag_data_structure write_enable", false,-1, 15,0); + vcdp->declBit(c+5729,"VX_cache genblk5[1] bank tag_data_access tag_data_structure write_fill", false,-1); + vcdp->declBus(c+5465,"VX_cache genblk5[1] bank tag_data_access tag_data_structure write_addr", false,-1, 5,0); + vcdp->declBus(c+5737,"VX_cache genblk5[1] bank tag_data_access tag_data_structure tag_index", false,-1, 19,0); + vcdp->declArray(c+5681,"VX_cache genblk5[1] bank tag_data_access tag_data_structure write_data", false,-1, 127,0); + vcdp->declBit(c+4825,"VX_cache genblk5[1] bank tag_data_access tag_data_structure fill_sent", false,-1); + vcdp->declQuad(c+16265,"VX_cache genblk5[1] bank tag_data_access tag_data_structure dirty", false,-1, 63,0); + vcdp->declQuad(c+16281,"VX_cache genblk5[1] bank tag_data_access tag_data_structure valid", false,-1, 63,0); + vcdp->declBit(c+5825,"VX_cache genblk5[1] bank tag_data_access tag_data_structure do_write", false,-1); + vcdp->declBus(c+16297,"VX_cache genblk5[1] bank tag_data_access tag_data_structure i", false,-1, 31,0); + vcdp->declBus(c+16305,"VX_cache genblk5[1] bank tag_data_access tag_data_structure j", false,-1, 31,0); + vcdp->declBus(c+25201,"VX_cache genblk5[1] bank tag_data_access s0_1_c0 N", false,-1, 31,0); + vcdp->declBus(c+25089,"VX_cache genblk5[1] bank tag_data_access s0_1_c0 PASSTHRU", false,-1, 31,0); + vcdp->declBit(c+24489,"VX_cache genblk5[1] bank tag_data_access s0_1_c0 clk", false,-1); + vcdp->declBit(c+24497,"VX_cache genblk5[1] bank tag_data_access s0_1_c0 reset", false,-1); + vcdp->declBit(c+4513,"VX_cache genblk5[1] bank tag_data_access s0_1_c0 stall", false,-1); + vcdp->declBit(c+25137,"VX_cache genblk5[1] bank tag_data_access s0_1_c0 flush", false,-1); + vcdp->declArray(c+5833,"VX_cache genblk5[1] bank tag_data_access s0_1_c0 in", false,-1, 165,0); + vcdp->declArray(c+5833,"VX_cache genblk5[1] bank tag_data_access s0_1_c0 out", false,-1, 165,0); + vcdp->declArray(c+16313,"VX_cache genblk5[1] bank tag_data_access s0_1_c0 value", false,-1, 165,0); + vcdp->declBus(c+25209,"VX_cache genblk5[1] bank st_1e_2 N", false,-1, 31,0); + vcdp->declBus(c+25057,"VX_cache genblk5[1] bank st_1e_2 PASSTHRU", false,-1, 31,0); + vcdp->declBit(c+24489,"VX_cache genblk5[1] bank st_1e_2 clk", false,-1); + vcdp->declBit(c+24497,"VX_cache genblk5[1] bank st_1e_2 reset", false,-1); + vcdp->declBit(c+4513,"VX_cache genblk5[1] bank st_1e_2 stall", false,-1); + vcdp->declBit(c+25137,"VX_cache genblk5[1] bank st_1e_2 flush", false,-1); + vcdp->declArray(c+5881,"VX_cache genblk5[1] bank st_1e_2 in", false,-1, 315,0); + vcdp->declArray(c+16361,"VX_cache genblk5[1] bank st_1e_2 out", false,-1, 315,0); + vcdp->declArray(c+16361,"VX_cache genblk5[1] bank st_1e_2 value", false,-1, 315,0); + vcdp->declBus(c+25057,"VX_cache genblk5[1] bank cache_miss_resrv CACHE_ID", false,-1, 31,0); + vcdp->declBus(c+25161,"VX_cache genblk5[1] bank cache_miss_resrv BANK_ID", false,-1, 31,0); + vcdp->declBus(c+25073,"VX_cache genblk5[1] bank cache_miss_resrv BANK_LINE_SIZE", false,-1, 31,0); + vcdp->declBus(c+25081,"VX_cache genblk5[1] bank cache_miss_resrv NUM_BANKS", false,-1, 31,0); + vcdp->declBus(c+25081,"VX_cache genblk5[1] bank cache_miss_resrv WORD_SIZE", false,-1, 31,0); + vcdp->declBus(c+25081,"VX_cache genblk5[1] bank cache_miss_resrv NUM_REQUESTS", false,-1, 31,0); + vcdp->declBus(c+25073,"VX_cache genblk5[1] bank cache_miss_resrv MRVQ_SIZE", false,-1, 31,0); + vcdp->declBus(c+25097,"VX_cache genblk5[1] bank cache_miss_resrv CORE_TAG_WIDTH", false,-1, 31,0); + vcdp->declBus(c+25113,"VX_cache genblk5[1] bank cache_miss_resrv SNP_REQ_TAG_WIDTH", false,-1, 31,0); + vcdp->declBit(c+24489,"VX_cache genblk5[1] bank cache_miss_resrv clk", false,-1); + vcdp->declBit(c+24497,"VX_cache genblk5[1] bank cache_miss_resrv reset", false,-1); + vcdp->declBit(c+5009,"VX_cache genblk5[1] bank cache_miss_resrv miss_add", false,-1); + vcdp->declBit(c+5017,"VX_cache genblk5[1] bank cache_miss_resrv is_mrvq", false,-1); + vcdp->declBus(c+10129,"VX_cache genblk5[1] bank cache_miss_resrv miss_add_addr", false,-1, 25,0); + vcdp->declBus(c+14273,"VX_cache genblk5[1] bank cache_miss_resrv miss_add_wsel", false,-1, 1,0); + vcdp->declBus(c+14281,"VX_cache genblk5[1] bank cache_miss_resrv miss_add_data", false,-1, 31,0); + vcdp->declBus(c+14217,"VX_cache genblk5[1] bank cache_miss_resrv miss_add_tid", false,-1, 1,0); + vcdp->declQuad(c+14225,"VX_cache genblk5[1] bank cache_miss_resrv miss_add_tag", false,-1, 41,0); + vcdp->declBit(c+14241,"VX_cache genblk5[1] bank cache_miss_resrv miss_add_rw", false,-1); + vcdp->declBus(c+14249,"VX_cache genblk5[1] bank cache_miss_resrv miss_add_byteen", false,-1, 3,0); + vcdp->declBit(c+4977,"VX_cache genblk5[1] bank cache_miss_resrv mrvq_init_ready_state", false,-1); + vcdp->declBit(c+14385,"VX_cache genblk5[1] bank cache_miss_resrv miss_add_is_snp", false,-1); + vcdp->declBit(c+14393,"VX_cache genblk5[1] bank cache_miss_resrv miss_add_snp_invalidate", false,-1); + vcdp->declBit(c+14129,"VX_cache genblk5[1] bank cache_miss_resrv miss_resrv_full", false,-1); + vcdp->declBit(c+14137,"VX_cache genblk5[1] bank cache_miss_resrv miss_resrv_stop", false,-1); + vcdp->declBit(c+5473,"VX_cache genblk5[1] bank cache_miss_resrv is_fill_st1", false,-1); + vcdp->declBus(c+4961,"VX_cache genblk5[1] bank cache_miss_resrv fill_addr_st1", false,-1, 25,0); + vcdp->declBit(c+4449,"VX_cache genblk5[1] bank cache_miss_resrv pending_hazard", false,-1); + vcdp->declBit(c+4425,"VX_cache genblk5[1] bank cache_miss_resrv miss_resrv_pop", false,-1); + vcdp->declBit(c+4433,"VX_cache genblk5[1] bank cache_miss_resrv miss_resrv_valid_st0", false,-1); + vcdp->declBus(c+14153,"VX_cache genblk5[1] bank cache_miss_resrv miss_resrv_addr_st0", false,-1, 25,0); + vcdp->declBus(c+14161,"VX_cache genblk5[1] bank cache_miss_resrv miss_resrv_wsel_st0", false,-1, 1,0); + vcdp->declBus(c+14169,"VX_cache genblk5[1] bank cache_miss_resrv miss_resrv_data_st0", false,-1, 31,0); + vcdp->declBus(c+14145,"VX_cache genblk5[1] bank cache_miss_resrv miss_resrv_tid_st0", false,-1, 1,0); + vcdp->declQuad(c+14177,"VX_cache genblk5[1] bank cache_miss_resrv miss_resrv_tag_st0", false,-1, 41,0); + vcdp->declBit(c+4441,"VX_cache genblk5[1] bank cache_miss_resrv miss_resrv_rw_st0", false,-1); + vcdp->declBus(c+14193,"VX_cache genblk5[1] bank cache_miss_resrv miss_resrv_byteen_st0", false,-1, 3,0); + vcdp->declBit(c+14201,"VX_cache genblk5[1] bank cache_miss_resrv miss_resrv_is_snp_st0", false,-1); + vcdp->declBit(c+14209,"VX_cache genblk5[1] bank cache_miss_resrv miss_resrv_snp_invalidate_st0", false,-1); + {int i; for (i=0; i<16; i++) { + vcdp->declArray(c+16441+i*3,"VX_cache genblk5[1] bank cache_miss_resrv metadata_table", true,(i+0), 84,0);}} + vcdp->declArray(c+16825,"VX_cache genblk5[1] bank cache_miss_resrv addr_table", false,-1, 415,0); + vcdp->declBus(c+16929,"VX_cache genblk5[1] bank cache_miss_resrv valid_table", false,-1, 15,0); + vcdp->declBus(c+16937,"VX_cache genblk5[1] bank cache_miss_resrv ready_table", false,-1, 15,0); + vcdp->declBus(c+16945,"VX_cache genblk5[1] bank cache_miss_resrv schedule_ptr", false,-1, 3,0); + vcdp->declBus(c+16953,"VX_cache genblk5[1] bank cache_miss_resrv head_ptr", false,-1, 3,0); + vcdp->declBus(c+16961,"VX_cache genblk5[1] bank cache_miss_resrv tail_ptr", false,-1, 3,0); + vcdp->declBus(c+16969,"VX_cache genblk5[1] bank cache_miss_resrv size", false,-1, 4,0); + vcdp->declBit(c+16977,"VX_cache genblk5[1] bank cache_miss_resrv enqueue_possible", false,-1); + vcdp->declBus(c+16961,"VX_cache genblk5[1] bank cache_miss_resrv enqueue_index", false,-1, 3,0); + vcdp->declBus(c+5961,"VX_cache genblk5[1] bank cache_miss_resrv make_ready", false,-1, 15,0); + vcdp->declBus(c+5969,"VX_cache genblk5[1] bank cache_miss_resrv make_ready_push", false,-1, 15,0); + vcdp->declBus(c+5977,"VX_cache genblk5[1] bank cache_miss_resrv valid_address_match", false,-1, 15,0); + vcdp->declBit(c+4433,"VX_cache genblk5[1] bank cache_miss_resrv dequeue_possible", false,-1); + vcdp->declBus(c+16945,"VX_cache genblk5[1] bank cache_miss_resrv dequeue_index", false,-1, 3,0); + vcdp->declBit(c+5985,"VX_cache genblk5[1] bank cache_miss_resrv mrvq_push", false,-1); + vcdp->declBit(c+5993,"VX_cache genblk5[1] bank cache_miss_resrv mrvq_pop", false,-1); + vcdp->declBit(c+6001,"VX_cache genblk5[1] bank cache_miss_resrv recover_state", false,-1); + vcdp->declBit(c+6009,"VX_cache genblk5[1] bank cache_miss_resrv increment_head", false,-1); + vcdp->declBit(c+6017,"VX_cache genblk5[1] bank cache_miss_resrv update_ready", false,-1); + vcdp->declBit(c+6025,"VX_cache genblk5[1] bank cache_miss_resrv qual_mrvq_init", false,-1); + vcdp->declBus(c+25217,"VX_cache genblk5[1] bank cwb_queue DATAW", false,-1, 31,0); + vcdp->declBus(c+25081,"VX_cache genblk5[1] bank cwb_queue SIZE", false,-1, 31,0); + vcdp->declBus(c+25089,"VX_cache genblk5[1] bank cwb_queue BUFFERED_OUTPUT", false,-1, 31,0); + vcdp->declBit(c+24489,"VX_cache genblk5[1] bank cwb_queue clk", false,-1); + vcdp->declBit(c+24497,"VX_cache genblk5[1] bank cwb_queue reset", false,-1); + vcdp->declBit(c+5025,"VX_cache genblk5[1] bank cwb_queue push", false,-1); + vcdp->declBit(c+1001,"VX_cache genblk5[1] bank cwb_queue pop", false,-1); + vcdp->declArray(c+6033,"VX_cache genblk5[1] bank cwb_queue data_in", false,-1, 75,0); + vcdp->declArray(c+6057,"VX_cache genblk5[1] bank cwb_queue data_out", false,-1, 75,0); + vcdp->declBit(c+14433,"VX_cache genblk5[1] bank cwb_queue empty", false,-1); + vcdp->declBit(c+14441,"VX_cache genblk5[1] bank cwb_queue full", false,-1); + vcdp->declBus(c+16985,"VX_cache genblk5[1] bank cwb_queue size", false,-1, 2,0); + vcdp->declBus(c+16985,"VX_cache genblk5[1] bank cwb_queue size_r", false,-1, 2,0); + vcdp->declBit(c+553,"VX_cache genblk5[1] bank cwb_queue reading", false,-1); + vcdp->declBit(c+6081,"VX_cache genblk5[1] bank cwb_queue writing", false,-1); + {int i; for (i=0; i<4; i++) { + vcdp->declArray(c+16993+i*3,"VX_cache genblk5[1] bank cwb_queue genblk3 data", true,(i+0), 75,0);}} + vcdp->declArray(c+17089,"VX_cache genblk5[1] bank cwb_queue genblk3 genblk2 head_r", false,-1, 75,0); + vcdp->declArray(c+17113,"VX_cache genblk5[1] bank cwb_queue genblk3 genblk2 curr_r", false,-1, 75,0); + vcdp->declBus(c+17137,"VX_cache genblk5[1] bank cwb_queue genblk3 genblk2 wr_ptr_r", false,-1, 1,0); + vcdp->declBus(c+17145,"VX_cache genblk5[1] bank cwb_queue genblk3 genblk2 rd_ptr_r", false,-1, 1,0); + vcdp->declBus(c+17153,"VX_cache genblk5[1] bank cwb_queue genblk3 genblk2 rd_ptr_next_r", false,-1, 1,0); + vcdp->declBit(c+14433,"VX_cache genblk5[1] bank cwb_queue genblk3 genblk2 empty_r", false,-1); + vcdp->declBit(c+14441,"VX_cache genblk5[1] bank cwb_queue genblk3 genblk2 full_r", false,-1); + vcdp->declBit(c+17161,"VX_cache genblk5[1] bank cwb_queue genblk3 genblk2 bypass_r", false,-1); + vcdp->declBus(c+25225,"VX_cache genblk5[1] bank dwb_queue DATAW", false,-1, 31,0); + vcdp->declBus(c+25081,"VX_cache genblk5[1] bank dwb_queue SIZE", false,-1, 31,0); + vcdp->declBus(c+25089,"VX_cache genblk5[1] bank dwb_queue BUFFERED_OUTPUT", false,-1, 31,0); + vcdp->declBit(c+24489,"VX_cache genblk5[1] bank dwb_queue clk", false,-1); + vcdp->declBit(c+24497,"VX_cache genblk5[1] bank dwb_queue reset", false,-1); + vcdp->declBit(c+5049,"VX_cache genblk5[1] bank dwb_queue push", false,-1); + vcdp->declBit(c+1009,"VX_cache genblk5[1] bank dwb_queue pop", false,-1); + vcdp->declArray(c+6089,"VX_cache genblk5[1] bank dwb_queue data_in", false,-1, 199,0); + vcdp->declArray(c+6145,"VX_cache genblk5[1] bank dwb_queue data_out", false,-1, 199,0); + vcdp->declBit(c+14449,"VX_cache genblk5[1] bank dwb_queue empty", false,-1); + vcdp->declBit(c+14457,"VX_cache genblk5[1] bank dwb_queue full", false,-1); + vcdp->declBus(c+17169,"VX_cache genblk5[1] bank dwb_queue size", false,-1, 2,0); + vcdp->declBus(c+17169,"VX_cache genblk5[1] bank dwb_queue size_r", false,-1, 2,0); + vcdp->declBit(c+561,"VX_cache genblk5[1] bank dwb_queue reading", false,-1); + vcdp->declBit(c+6201,"VX_cache genblk5[1] bank dwb_queue writing", false,-1); + {int i; for (i=0; i<4; i++) { + vcdp->declArray(c+17177+i*7,"VX_cache genblk5[1] bank dwb_queue genblk3 data", true,(i+0), 199,0);}} + vcdp->declArray(c+17401,"VX_cache genblk5[1] bank dwb_queue genblk3 genblk2 head_r", false,-1, 199,0); + vcdp->declArray(c+17457,"VX_cache genblk5[1] bank dwb_queue genblk3 genblk2 curr_r", false,-1, 199,0); + vcdp->declBus(c+17513,"VX_cache genblk5[1] bank dwb_queue genblk3 genblk2 wr_ptr_r", false,-1, 1,0); + vcdp->declBus(c+17521,"VX_cache genblk5[1] bank dwb_queue genblk3 genblk2 rd_ptr_r", false,-1, 1,0); + vcdp->declBus(c+17529,"VX_cache genblk5[1] bank dwb_queue genblk3 genblk2 rd_ptr_next_r", false,-1, 1,0); + vcdp->declBit(c+14449,"VX_cache genblk5[1] bank dwb_queue genblk3 genblk2 empty_r", false,-1); + vcdp->declBit(c+14457,"VX_cache genblk5[1] bank dwb_queue genblk3 genblk2 full_r", false,-1); + vcdp->declBit(c+17537,"VX_cache genblk5[1] bank dwb_queue genblk3 genblk2 bypass_r", false,-1); + vcdp->declBus(c+25057,"VX_cache genblk5[2] bank CACHE_ID", false,-1, 31,0); + vcdp->declBus(c+25233,"VX_cache genblk5[2] bank BANK_ID", false,-1, 31,0); + vcdp->declBus(c+25065,"VX_cache genblk5[2] bank CACHE_SIZE", false,-1, 31,0); + vcdp->declBus(c+25073,"VX_cache genblk5[2] bank BANK_LINE_SIZE", false,-1, 31,0); + vcdp->declBus(c+25081,"VX_cache genblk5[2] bank NUM_BANKS", false,-1, 31,0); + vcdp->declBus(c+25081,"VX_cache genblk5[2] bank WORD_SIZE", false,-1, 31,0); + vcdp->declBus(c+25081,"VX_cache genblk5[2] bank NUM_REQUESTS", false,-1, 31,0); + vcdp->declBus(c+25089,"VX_cache genblk5[2] bank STAGE_1_CYCLES", false,-1, 31,0); + vcdp->declBus(c+25081,"VX_cache genblk5[2] bank CREQ_SIZE", false,-1, 31,0); + vcdp->declBus(c+25073,"VX_cache genblk5[2] bank MRVQ_SIZE", false,-1, 31,0); + vcdp->declBus(c+25073,"VX_cache genblk5[2] bank DFPQ_SIZE", false,-1, 31,0); + vcdp->declBus(c+25073,"VX_cache genblk5[2] bank SNRQ_SIZE", false,-1, 31,0); + vcdp->declBus(c+25081,"VX_cache genblk5[2] bank CWBQ_SIZE", false,-1, 31,0); + vcdp->declBus(c+25081,"VX_cache genblk5[2] bank DWBQ_SIZE", false,-1, 31,0); + vcdp->declBus(c+25081,"VX_cache genblk5[2] bank DFQQ_SIZE", false,-1, 31,0); + vcdp->declBus(c+25089,"VX_cache genblk5[2] bank WRITE_ENABLE", false,-1, 31,0); + vcdp->declBus(c+25089,"VX_cache genblk5[2] bank DRAM_ENABLE", false,-1, 31,0); + vcdp->declBus(c+25057,"VX_cache genblk5[2] bank SNOOP_FORWARDING", false,-1, 31,0); + vcdp->declBus(c+25097,"VX_cache genblk5[2] bank CORE_TAG_WIDTH", false,-1, 31,0); + vcdp->declBus(c+25105,"VX_cache genblk5[2] bank CORE_TAG_ID_BITS", false,-1, 31,0); + vcdp->declBus(c+25113,"VX_cache genblk5[2] bank SNP_REQ_TAG_WIDTH", false,-1, 31,0); + vcdp->declBit(c+24489,"VX_cache genblk5[2] bank clk", false,-1); + vcdp->declBit(c+24497,"VX_cache genblk5[2] bank reset", false,-1); + vcdp->declBus(c+97,"VX_cache genblk5[2] bank core_req_valid", false,-1, 3,0); + vcdp->declBus(c+24513,"VX_cache genblk5[2] bank core_req_rw", false,-1, 3,0); + vcdp->declBus(c+24521,"VX_cache genblk5[2] bank core_req_byteen", false,-1, 15,0); + vcdp->declArray(c+24529,"VX_cache genblk5[2] bank core_req_addr", false,-1, 119,0); + vcdp->declArray(c+24561,"VX_cache genblk5[2] bank core_req_data", false,-1, 127,0); + vcdp->declQuad(c+24593,"VX_cache genblk5[2] bank core_req_tag", false,-1, 41,0); + vcdp->declBit(c+10185,"VX_cache genblk5[2] bank core_req_ready", false,-1); + vcdp->declBit(c+10153,"VX_cache genblk5[2] bank core_rsp_valid", false,-1); + vcdp->declBus(c+1697,"VX_cache genblk5[2] bank core_rsp_tid", false,-1, 1,0); + vcdp->declBus(c+1705,"VX_cache genblk5[2] bank core_rsp_data", false,-1, 31,0); + vcdp->declQuad(c+1713,"VX_cache genblk5[2] bank core_rsp_tag", false,-1, 41,0); + vcdp->declBit(c+105,"VX_cache genblk5[2] bank core_rsp_ready", false,-1); + vcdp->declBit(c+1729,"VX_cache genblk5[2] bank dram_fill_req_valid", false,-1); + vcdp->declBus(c+10169,"VX_cache genblk5[2] bank dram_fill_req_addr", false,-1, 25,0); + vcdp->declBit(c+10065,"VX_cache genblk5[2] bank dram_fill_req_ready", false,-1); + vcdp->declBit(c+25009,"VX_cache genblk5[2] bank dram_fill_rsp_valid", false,-1); + vcdp->declArray(c+24769,"VX_cache genblk5[2] bank dram_fill_rsp_data", false,-1, 127,0); + vcdp->declBus(c+24969,"VX_cache genblk5[2] bank dram_fill_rsp_addr", false,-1, 25,0); + vcdp->declBit(c+10161,"VX_cache genblk5[2] bank dram_fill_rsp_ready", false,-1); + vcdp->declBit(c+1737,"VX_cache genblk5[2] bank dram_wb_req_valid", false,-1); + vcdp->declBus(c+1745,"VX_cache genblk5[2] bank dram_wb_req_byteen", false,-1, 15,0); + vcdp->declBus(c+1753,"VX_cache genblk5[2] bank dram_wb_req_addr", false,-1, 25,0); + vcdp->declArray(c+1761,"VX_cache genblk5[2] bank dram_wb_req_data", false,-1, 127,0); + vcdp->declBit(c+113,"VX_cache genblk5[2] bank dram_wb_req_ready", false,-1); + vcdp->declBit(c+25017,"VX_cache genblk5[2] bank snp_req_valid", false,-1); + vcdp->declBus(c+24985,"VX_cache genblk5[2] bank snp_req_addr", false,-1, 25,0); + vcdp->declBit(c+24833,"VX_cache genblk5[2] bank snp_req_invalidate", false,-1); + vcdp->declBus(c+24841,"VX_cache genblk5[2] bank snp_req_tag", false,-1, 27,0); + vcdp->declBit(c+10177,"VX_cache genblk5[2] bank snp_req_ready", false,-1); + vcdp->declBit(c+1793,"VX_cache genblk5[2] bank snp_rsp_valid", false,-1); + vcdp->declBus(c+1801,"VX_cache genblk5[2] bank snp_rsp_tag", false,-1, 27,0); + vcdp->declBit(c+121,"VX_cache genblk5[2] bank snp_rsp_ready", false,-1); + vcdp->declBit(c+6209,"VX_cache genblk5[2] bank snrq_pop", false,-1); + vcdp->declBit(c+17545,"VX_cache genblk5[2] bank snrq_empty", false,-1); + vcdp->declBit(c+17553,"VX_cache genblk5[2] bank snrq_full", false,-1); + vcdp->declBus(c+6217,"VX_cache genblk5[2] bank snrq_addr_st0", false,-1, 25,0); + vcdp->declBit(c+6225,"VX_cache genblk5[2] bank snrq_invalidate_st0", false,-1); + vcdp->declBus(c+6233,"VX_cache genblk5[2] bank snrq_tag_st0", false,-1, 27,0); + vcdp->declBit(c+6241,"VX_cache genblk5[2] bank dfpq_pop", false,-1); + vcdp->declBit(c+17561,"VX_cache genblk5[2] bank dfpq_empty", false,-1); + vcdp->declBit(c+17569,"VX_cache genblk5[2] bank dfpq_full", false,-1); + vcdp->declBus(c+6249,"VX_cache genblk5[2] bank dfpq_addr_st0", false,-1, 25,0); + vcdp->declArray(c+6257,"VX_cache genblk5[2] bank dfpq_filldata_st0", false,-1, 127,0); + vcdp->declBit(c+6289,"VX_cache genblk5[2] bank reqq_pop", false,-1); + vcdp->declBit(c+1025,"VX_cache genblk5[2] bank reqq_push", false,-1); + vcdp->declBit(c+6297,"VX_cache genblk5[2] bank reqq_empty", false,-1); + vcdp->declBit(c+17577,"VX_cache genblk5[2] bank reqq_full", false,-1); + vcdp->declBit(c+6305,"VX_cache genblk5[2] bank reqq_req_st0", false,-1); + vcdp->declBus(c+6313,"VX_cache genblk5[2] bank reqq_req_tid_st0", false,-1, 1,0); + vcdp->declBit(c+6321,"VX_cache genblk5[2] bank reqq_req_rw_st0", false,-1); + vcdp->declBus(c+6329,"VX_cache genblk5[2] bank reqq_req_byteen_st0", false,-1, 3,0); + vcdp->declBus(c+6337,"VX_cache genblk5[2] bank reqq_req_addr_st0", false,-1, 29,0); + vcdp->declBus(c+6345,"VX_cache genblk5[2] bank reqq_req_writeword_st0", false,-1, 31,0); + vcdp->declQuad(c+17585,"VX_cache genblk5[2] bank reqq_req_tag_st0", false,-1, 41,0); + vcdp->declBit(c+6353,"VX_cache genblk5[2] bank mrvq_pop", false,-1); + vcdp->declBit(c+17601,"VX_cache genblk5[2] bank mrvq_full", false,-1); + vcdp->declBit(c+17609,"VX_cache genblk5[2] bank mrvq_stop", false,-1); + vcdp->declBit(c+6361,"VX_cache genblk5[2] bank mrvq_valid_st0", false,-1); + vcdp->declBus(c+17617,"VX_cache genblk5[2] bank mrvq_tid_st0", false,-1, 1,0); + vcdp->declBus(c+17625,"VX_cache genblk5[2] bank mrvq_addr_st0", false,-1, 25,0); + vcdp->declBus(c+17633,"VX_cache genblk5[2] bank mrvq_wsel_st0", false,-1, 1,0); + vcdp->declBus(c+17641,"VX_cache genblk5[2] bank mrvq_writeword_st0", false,-1, 31,0); + vcdp->declQuad(c+17649,"VX_cache genblk5[2] bank mrvq_tag_st0", false,-1, 41,0); + vcdp->declBit(c+6369,"VX_cache genblk5[2] bank mrvq_rw_st0", false,-1); + vcdp->declBus(c+17665,"VX_cache genblk5[2] bank mrvq_byteen_st0", false,-1, 3,0); + vcdp->declBit(c+17673,"VX_cache genblk5[2] bank mrvq_is_snp_st0", false,-1); + vcdp->declBit(c+17681,"VX_cache genblk5[2] bank mrvq_snp_invalidate_st0", false,-1); + vcdp->declBit(c+6377,"VX_cache genblk5[2] bank mrvq_pending_hazard_st1e", false,-1); + vcdp->declBit(c+6385,"VX_cache genblk5[2] bank st2_pending_hazard_st1e", false,-1); + vcdp->declBit(c+6393,"VX_cache genblk5[2] bank force_request_miss_st1e", false,-1); + vcdp->declBus(c+17689,"VX_cache genblk5[2] bank miss_add_tid", false,-1, 1,0); + vcdp->declQuad(c+17697,"VX_cache genblk5[2] bank miss_add_tag", false,-1, 41,0); + vcdp->declBit(c+17713,"VX_cache genblk5[2] bank miss_add_rw", false,-1); + vcdp->declBus(c+17721,"VX_cache genblk5[2] bank miss_add_byteen", false,-1, 3,0); + vcdp->declBus(c+10169,"VX_cache genblk5[2] bank addr_st2", false,-1, 25,0); + vcdp->declBit(c+17729,"VX_cache genblk5[2] bank is_fill_st2", false,-1); + vcdp->declBit(c+6401,"VX_cache genblk5[2] bank recover_mrvq_state_st2", false,-1); + vcdp->declBit(c+6409,"VX_cache genblk5[2] bank mrvq_push_stall", false,-1); + vcdp->declBit(c+6417,"VX_cache genblk5[2] bank cwbq_push_stall", false,-1); + vcdp->declBit(c+6425,"VX_cache genblk5[2] bank dwbq_push_stall", false,-1); + vcdp->declBit(c+6433,"VX_cache genblk5[2] bank dram_fill_req_stall", false,-1); + vcdp->declBit(c+6441,"VX_cache genblk5[2] bank stall_bank_pipe", false,-1); + vcdp->declBit(c+6449,"VX_cache genblk5[2] bank is_fill_in_pipe", false,-1); + {int i; for (i=0; i<1; i++) { + vcdp->declBit(c+6457+i*1,"VX_cache genblk5[2] bank is_fill_st1", true,(i+0));}} + {int i; for (i=0; i<1; i++) { + vcdp->declBit(c+6465+i*1,"VX_cache genblk5[2] bank going_to_write_st1", true,(i+0));}} + vcdp->declBus(c+25161,"VX_cache genblk5[2] bank j", false,-1, 31,0); + vcdp->declBit(c+6361,"VX_cache genblk5[2] bank mrvq_pop_unqual", false,-1); + vcdp->declBit(c+6473,"VX_cache genblk5[2] bank dfpq_pop_unqual", false,-1); + vcdp->declBit(c+6481,"VX_cache genblk5[2] bank reqq_pop_unqual", false,-1); + vcdp->declBit(c+6489,"VX_cache genblk5[2] bank snrq_pop_unqual", false,-1); + vcdp->declBit(c+6473,"VX_cache genblk5[2] bank qual_is_fill_st0", false,-1); + vcdp->declBit(c+6497,"VX_cache genblk5[2] bank qual_valid_st0", false,-1); + vcdp->declBus(c+6505,"VX_cache genblk5[2] bank qual_addr_st0", false,-1, 25,0); + vcdp->declBus(c+6513,"VX_cache genblk5[2] bank qual_wsel_st0", false,-1, 1,0); + vcdp->declBit(c+6361,"VX_cache genblk5[2] bank qual_is_mrvq_st0", false,-1); + vcdp->declBus(c+6521,"VX_cache genblk5[2] bank qual_writeword_st0", false,-1, 31,0); + vcdp->declArray(c+6529,"VX_cache genblk5[2] bank qual_writedata_st0", false,-1, 127,0); + vcdp->declQuad(c+6561,"VX_cache genblk5[2] bank qual_inst_meta_st0", false,-1, 48,0); + vcdp->declBit(c+6577,"VX_cache genblk5[2] bank qual_going_to_write_st0", false,-1); + vcdp->declBit(c+6585,"VX_cache genblk5[2] bank qual_is_snp_st0", false,-1); + vcdp->declBit(c+6593,"VX_cache genblk5[2] bank qual_snp_invalidate_st0", false,-1); + {int i; for (i=0; i<1; i++) { + vcdp->declBit(c+6601+i*1,"VX_cache genblk5[2] bank valid_st1", true,(i+0));}} + {int i; for (i=0; i<1; i++) { + vcdp->declBus(c+6609+i*1,"VX_cache genblk5[2] bank addr_st1", true,(i+0), 25,0);}} + {int i; for (i=0; i<1; i++) { + vcdp->declBus(c+6617+i*1,"VX_cache genblk5[2] bank wsel_st1", true,(i+0), 1,0);}} + {int i; for (i=0; i<1; i++) { + vcdp->declBus(c+6625+i*1,"VX_cache genblk5[2] bank writeword_st1", true,(i+0), 31,0);}} + {int i; for (i=0; i<1; i++) { + vcdp->declQuad(c+6633+i*2,"VX_cache genblk5[2] bank inst_meta_st1", true,(i+0), 48,0);}} + {int i; for (i=0; i<1; i++) { + vcdp->declArray(c+6649+i*4,"VX_cache genblk5[2] bank writedata_st1", true,(i+0), 127,0);}} + {int i; for (i=0; i<1; i++) { + vcdp->declBit(c+6681+i*1,"VX_cache genblk5[2] bank is_snp_st1", true,(i+0));}} + {int i; for (i=0; i<1; i++) { + vcdp->declBit(c+6689+i*1,"VX_cache genblk5[2] bank snp_invalidate_st1", true,(i+0));}} + {int i; for (i=0; i<1; i++) { + vcdp->declBit(c+6697+i*1,"VX_cache genblk5[2] bank is_mrvq_st1", true,(i+0));}} + vcdp->declBus(c+6705,"VX_cache genblk5[2] bank readword_st1e", false,-1, 31,0); + vcdp->declArray(c+6713,"VX_cache genblk5[2] bank readdata_st1e", false,-1, 127,0); + vcdp->declBus(c+6745,"VX_cache genblk5[2] bank readtag_st1e", false,-1, 19,0); + vcdp->declBit(c+6753,"VX_cache genblk5[2] bank miss_st1e", false,-1); + vcdp->declBit(c+6761,"VX_cache genblk5[2] bank dirty_st1e", false,-1); + vcdp->declBus(c+6769,"VX_cache genblk5[2] bank dirtyb_st1e", false,-1, 15,0); + vcdp->declQuad(c+6777,"VX_cache genblk5[2] bank tag_st1e", false,-1, 41,0); + vcdp->declBus(c+6793,"VX_cache genblk5[2] bank tid_st1e", false,-1, 1,0); + vcdp->declBit(c+6801,"VX_cache genblk5[2] bank mem_rw_st1e", false,-1); + vcdp->declBus(c+6809,"VX_cache genblk5[2] bank mem_byteen_st1e", false,-1, 3,0); + vcdp->declBit(c+6817,"VX_cache genblk5[2] bank fill_saw_dirty_st1e", false,-1); + vcdp->declBit(c+6825,"VX_cache genblk5[2] bank is_snp_st1e", false,-1); + vcdp->declBit(c+6833,"VX_cache genblk5[2] bank snp_invalidate_st1e", false,-1); + vcdp->declBit(c+6841,"VX_cache genblk5[2] bank snp_to_mrvq_st1e", false,-1); + vcdp->declBit(c+6849,"VX_cache genblk5[2] bank mrvq_init_ready_state_st1e", false,-1); + vcdp->declBit(c+6857,"VX_cache genblk5[2] bank miss_add_because_miss", false,-1); + vcdp->declBit(c+6865,"VX_cache genblk5[2] bank valid_st1e", false,-1); + vcdp->declBit(c+6873,"VX_cache genblk5[2] bank is_mrvq_st1e", false,-1); + vcdp->declBit(c+6881,"VX_cache genblk5[2] bank mrvq_recover_ready_state_st1e", false,-1); + vcdp->declBus(c+6889,"VX_cache genblk5[2] bank addr_st1e", false,-1, 25,0); + vcdp->declBit(c+6897,"VX_cache genblk5[2] bank qual_valid_st1e_2", false,-1); + vcdp->declBit(c+6873,"VX_cache genblk5[2] bank is_mrvq_st1e_st2", false,-1); + vcdp->declBit(c+17737,"VX_cache genblk5[2] bank valid_st2", false,-1); + vcdp->declBus(c+17745,"VX_cache genblk5[2] bank wsel_st2", false,-1, 1,0); + vcdp->declBus(c+17753,"VX_cache genblk5[2] bank writeword_st2", false,-1, 31,0); + vcdp->declBus(c+17761,"VX_cache genblk5[2] bank readword_st2", false,-1, 31,0); + vcdp->declArray(c+17769,"VX_cache genblk5[2] bank readdata_st2", false,-1, 127,0); + vcdp->declBit(c+17801,"VX_cache genblk5[2] bank miss_st2", false,-1); + vcdp->declBit(c+17809,"VX_cache genblk5[2] bank dirty_st2", false,-1); + vcdp->declBus(c+17817,"VX_cache genblk5[2] bank dirtyb_st2", false,-1, 15,0); + vcdp->declQuad(c+17825,"VX_cache genblk5[2] bank inst_meta_st2", false,-1, 48,0); + vcdp->declBus(c+17841,"VX_cache genblk5[2] bank readtag_st2", false,-1, 19,0); + vcdp->declBit(c+17849,"VX_cache genblk5[2] bank fill_saw_dirty_st2", false,-1); + vcdp->declBit(c+17857,"VX_cache genblk5[2] bank is_snp_st2", false,-1); + vcdp->declBit(c+17865,"VX_cache genblk5[2] bank snp_invalidate_st2", false,-1); + vcdp->declBit(c+17873,"VX_cache genblk5[2] bank snp_to_mrvq_st2", false,-1); + vcdp->declBit(c+17881,"VX_cache genblk5[2] bank is_mrvq_st2", false,-1); + vcdp->declBit(c+6905,"VX_cache genblk5[2] bank mrvq_init_ready_state_st2", false,-1); + vcdp->declBit(c+17889,"VX_cache genblk5[2] bank mrvq_recover_ready_state_st2", false,-1); + vcdp->declBit(c+17897,"VX_cache genblk5[2] bank mrvq_init_ready_state_unqual_st2", false,-1); + vcdp->declBit(c+6913,"VX_cache genblk5[2] bank mrvq_init_ready_state_hazard_st0_st1", false,-1); + vcdp->declBit(c+6921,"VX_cache genblk5[2] bank mrvq_init_ready_state_hazard_st1e_st1", false,-1); + vcdp->declBit(c+17873,"VX_cache genblk5[2] bank miss_add_because_pending", false,-1); + vcdp->declBit(c+6929,"VX_cache genblk5[2] bank miss_add_unqual", false,-1); + vcdp->declBit(c+6937,"VX_cache genblk5[2] bank miss_add", false,-1); + vcdp->declBus(c+10169,"VX_cache genblk5[2] bank miss_add_addr", false,-1, 25,0); + vcdp->declBus(c+17745,"VX_cache genblk5[2] bank miss_add_wsel", false,-1, 1,0); + vcdp->declBus(c+17753,"VX_cache genblk5[2] bank miss_add_data", false,-1, 31,0); + vcdp->declBit(c+17857,"VX_cache genblk5[2] bank miss_add_is_snp", false,-1); + vcdp->declBit(c+17865,"VX_cache genblk5[2] bank miss_add_snp_invalidate", false,-1); + vcdp->declBit(c+6945,"VX_cache genblk5[2] bank miss_add_is_mrvq", false,-1); + vcdp->declBit(c+6953,"VX_cache genblk5[2] bank cwbq_push", false,-1); + vcdp->declBit(c+1033,"VX_cache genblk5[2] bank cwbq_pop", false,-1); + vcdp->declBit(c+17905,"VX_cache genblk5[2] bank cwbq_empty", false,-1); + vcdp->declBit(c+17913,"VX_cache genblk5[2] bank cwbq_full", false,-1); + vcdp->declBit(c+6961,"VX_cache genblk5[2] bank cwbq_push_unqual", false,-1); + vcdp->declBus(c+17761,"VX_cache genblk5[2] bank cwbq_data", false,-1, 31,0); + vcdp->declBus(c+17689,"VX_cache genblk5[2] bank cwbq_tid", false,-1, 1,0); + vcdp->declQuad(c+17697,"VX_cache genblk5[2] bank cwbq_tag", false,-1, 41,0); + vcdp->declBit(c+6929,"VX_cache genblk5[2] bank dram_fill_req_fast", false,-1); + vcdp->declBit(c+6969,"VX_cache genblk5[2] bank dram_fill_req_unqual", false,-1); + vcdp->declBit(c+6977,"VX_cache genblk5[2] bank dwbq_push", false,-1); + vcdp->declBit(c+1041,"VX_cache genblk5[2] bank dwbq_pop", false,-1); + vcdp->declBit(c+17921,"VX_cache genblk5[2] bank dwbq_empty", false,-1); + vcdp->declBit(c+17929,"VX_cache genblk5[2] bank dwbq_full", false,-1); + vcdp->declBit(c+6985,"VX_cache genblk5[2] bank dwbq_is_dwb_in", false,-1); + vcdp->declBit(c+6993,"VX_cache genblk5[2] bank dwbq_is_snp_in", false,-1); + vcdp->declBit(c+7001,"VX_cache genblk5[2] bank dwbq_is_dwb_out", false,-1); + vcdp->declBit(c+7009,"VX_cache genblk5[2] bank dwbq_is_snp_out", false,-1); + vcdp->declBit(c+7017,"VX_cache genblk5[2] bank dwbq_push_unqual", false,-1); + vcdp->declBus(c+17937,"VX_cache genblk5[2] bank dwbq_req_addr", false,-1, 25,0); + vcdp->declBus(c+17945,"VX_cache genblk5[2] bank snrq_tag_st2", false,-1, 27,0); + vcdp->declBit(c+569,"VX_cache genblk5[2] bank dram_wb_req_fire", false,-1); + vcdp->declBit(c+577,"VX_cache genblk5[2] bank snp_rsp_fire", false,-1); + vcdp->declBit(c+17953,"VX_cache genblk5[2] bank dwbq_dual_valid_sel", false,-1); + vcdp->declBus(c+25169,"VX_cache genblk5[2] bank snp_req_queue DATAW", false,-1, 31,0); + vcdp->declBus(c+25073,"VX_cache genblk5[2] bank snp_req_queue SIZE", false,-1, 31,0); + vcdp->declBus(c+25089,"VX_cache genblk5[2] bank snp_req_queue BUFFERED_OUTPUT", false,-1, 31,0); + vcdp->declBit(c+24489,"VX_cache genblk5[2] bank snp_req_queue clk", false,-1); + vcdp->declBit(c+24497,"VX_cache genblk5[2] bank snp_req_queue reset", false,-1); + vcdp->declBit(c+25017,"VX_cache genblk5[2] bank snp_req_queue push", false,-1); + vcdp->declBit(c+6209,"VX_cache genblk5[2] bank snp_req_queue pop", false,-1); + vcdp->declQuad(c+585,"VX_cache genblk5[2] bank snp_req_queue data_in", false,-1, 54,0); + vcdp->declQuad(c+7025,"VX_cache genblk5[2] bank snp_req_queue data_out", false,-1, 54,0); + vcdp->declBit(c+17545,"VX_cache genblk5[2] bank snp_req_queue empty", false,-1); + vcdp->declBit(c+17553,"VX_cache genblk5[2] bank snp_req_queue full", false,-1); + vcdp->declBus(c+17961,"VX_cache genblk5[2] bank snp_req_queue size", false,-1, 4,0); + vcdp->declBus(c+17961,"VX_cache genblk5[2] bank snp_req_queue size_r", false,-1, 4,0); + vcdp->declBit(c+7041,"VX_cache genblk5[2] bank snp_req_queue reading", false,-1); + vcdp->declBit(c+601,"VX_cache genblk5[2] bank snp_req_queue writing", false,-1); + {int i; for (i=0; i<16; i++) { + vcdp->declQuad(c+17969+i*2,"VX_cache genblk5[2] bank snp_req_queue genblk3 data", true,(i+0), 54,0);}} + vcdp->declQuad(c+18225,"VX_cache genblk5[2] bank snp_req_queue genblk3 genblk2 head_r", false,-1, 54,0); + vcdp->declQuad(c+18241,"VX_cache genblk5[2] bank snp_req_queue genblk3 genblk2 curr_r", false,-1, 54,0); + vcdp->declBus(c+18257,"VX_cache genblk5[2] bank snp_req_queue genblk3 genblk2 wr_ptr_r", false,-1, 3,0); + vcdp->declBus(c+18265,"VX_cache genblk5[2] bank snp_req_queue genblk3 genblk2 rd_ptr_r", false,-1, 3,0); + vcdp->declBus(c+18273,"VX_cache genblk5[2] bank snp_req_queue genblk3 genblk2 rd_ptr_next_r", false,-1, 3,0); + vcdp->declBit(c+17545,"VX_cache genblk5[2] bank snp_req_queue genblk3 genblk2 empty_r", false,-1); + vcdp->declBit(c+17553,"VX_cache genblk5[2] bank snp_req_queue genblk3 genblk2 full_r", false,-1); + vcdp->declBit(c+18281,"VX_cache genblk5[2] bank snp_req_queue genblk3 genblk2 bypass_r", false,-1); + vcdp->declBus(c+25177,"VX_cache genblk5[2] bank dfp_queue DATAW", false,-1, 31,0); + vcdp->declBus(c+25073,"VX_cache genblk5[2] bank dfp_queue SIZE", false,-1, 31,0); + vcdp->declBus(c+25089,"VX_cache genblk5[2] bank dfp_queue BUFFERED_OUTPUT", false,-1, 31,0); + vcdp->declBit(c+24489,"VX_cache genblk5[2] bank dfp_queue clk", false,-1); + vcdp->declBit(c+24497,"VX_cache genblk5[2] bank dfp_queue reset", false,-1); + vcdp->declBit(c+25009,"VX_cache genblk5[2] bank dfp_queue push", false,-1); + vcdp->declBit(c+6241,"VX_cache genblk5[2] bank dfp_queue pop", false,-1); + vcdp->declArray(c+609,"VX_cache genblk5[2] bank dfp_queue data_in", false,-1, 153,0); + vcdp->declArray(c+7049,"VX_cache genblk5[2] bank dfp_queue data_out", false,-1, 153,0); + vcdp->declBit(c+17561,"VX_cache genblk5[2] bank dfp_queue empty", false,-1); + vcdp->declBit(c+17569,"VX_cache genblk5[2] bank dfp_queue full", false,-1); + vcdp->declBus(c+18289,"VX_cache genblk5[2] bank dfp_queue size", false,-1, 4,0); + vcdp->declBus(c+18289,"VX_cache genblk5[2] bank dfp_queue size_r", false,-1, 4,0); + vcdp->declBit(c+7089,"VX_cache genblk5[2] bank dfp_queue reading", false,-1); + vcdp->declBit(c+649,"VX_cache genblk5[2] bank dfp_queue writing", false,-1); + {int i; for (i=0; i<16; i++) { + vcdp->declArray(c+18297+i*5,"VX_cache genblk5[2] bank dfp_queue genblk3 data", true,(i+0), 153,0);}} + vcdp->declArray(c+18937,"VX_cache genblk5[2] bank dfp_queue genblk3 genblk2 head_r", false,-1, 153,0); + vcdp->declArray(c+18977,"VX_cache genblk5[2] bank dfp_queue genblk3 genblk2 curr_r", false,-1, 153,0); + vcdp->declBus(c+19017,"VX_cache genblk5[2] bank dfp_queue genblk3 genblk2 wr_ptr_r", false,-1, 3,0); + vcdp->declBus(c+19025,"VX_cache genblk5[2] bank dfp_queue genblk3 genblk2 rd_ptr_r", false,-1, 3,0); + vcdp->declBus(c+19033,"VX_cache genblk5[2] bank dfp_queue genblk3 genblk2 rd_ptr_next_r", false,-1, 3,0); + vcdp->declBit(c+17561,"VX_cache genblk5[2] bank dfp_queue genblk3 genblk2 empty_r", false,-1); + vcdp->declBit(c+17569,"VX_cache genblk5[2] bank dfp_queue genblk3 genblk2 full_r", false,-1); + vcdp->declBit(c+19041,"VX_cache genblk5[2] bank dfp_queue genblk3 genblk2 bypass_r", false,-1); + vcdp->declBus(c+25081,"VX_cache genblk5[2] bank core_req_arb WORD_SIZE", false,-1, 31,0); + vcdp->declBus(c+25081,"VX_cache genblk5[2] bank core_req_arb NUM_REQUESTS", false,-1, 31,0); + vcdp->declBus(c+25081,"VX_cache genblk5[2] bank core_req_arb CREQ_SIZE", false,-1, 31,0); + vcdp->declBus(c+25097,"VX_cache genblk5[2] bank core_req_arb CORE_TAG_WIDTH", false,-1, 31,0); + vcdp->declBus(c+25105,"VX_cache genblk5[2] bank core_req_arb CORE_TAG_ID_BITS", false,-1, 31,0); + vcdp->declBit(c+24489,"VX_cache genblk5[2] bank core_req_arb clk", false,-1); + vcdp->declBit(c+24497,"VX_cache genblk5[2] bank core_req_arb reset", false,-1); + vcdp->declBit(c+1025,"VX_cache genblk5[2] bank core_req_arb reqq_push", false,-1); + vcdp->declBus(c+97,"VX_cache genblk5[2] bank core_req_arb bank_valids", false,-1, 3,0); + vcdp->declBus(c+24513,"VX_cache genblk5[2] bank core_req_arb bank_rw", false,-1, 3,0); + vcdp->declBus(c+24521,"VX_cache genblk5[2] bank core_req_arb bank_byteen", false,-1, 15,0); + vcdp->declArray(c+24561,"VX_cache genblk5[2] bank core_req_arb bank_writedata", false,-1, 127,0); + vcdp->declArray(c+24529,"VX_cache genblk5[2] bank core_req_arb bank_addr", false,-1, 119,0); + vcdp->declQuad(c+24593,"VX_cache genblk5[2] bank core_req_arb bank_tag", false,-1, 41,0); + vcdp->declBit(c+6289,"VX_cache genblk5[2] bank core_req_arb reqq_pop", false,-1); + vcdp->declBit(c+6305,"VX_cache genblk5[2] bank core_req_arb reqq_req_st0", false,-1); + vcdp->declBus(c+6313,"VX_cache genblk5[2] bank core_req_arb reqq_req_tid_st0", false,-1, 1,0); + vcdp->declBit(c+6321,"VX_cache genblk5[2] bank core_req_arb reqq_req_rw_st0", false,-1); + vcdp->declBus(c+6329,"VX_cache genblk5[2] bank core_req_arb reqq_req_byteen_st0", false,-1, 3,0); + vcdp->declBus(c+6337,"VX_cache genblk5[2] bank core_req_arb reqq_req_addr_st0", false,-1, 29,0); + vcdp->declBus(c+6345,"VX_cache genblk5[2] bank core_req_arb reqq_req_writedata_st0", false,-1, 31,0); + vcdp->declQuad(c+17585,"VX_cache genblk5[2] bank core_req_arb reqq_req_tag_st0", false,-1, 41,0); + vcdp->declBit(c+6297,"VX_cache genblk5[2] bank core_req_arb reqq_empty", false,-1); + vcdp->declBit(c+17577,"VX_cache genblk5[2] bank core_req_arb reqq_full", false,-1); + vcdp->declBus(c+7097,"VX_cache genblk5[2] bank core_req_arb out_per_valids", false,-1, 3,0); + vcdp->declBus(c+7105,"VX_cache genblk5[2] bank core_req_arb out_per_rw", false,-1, 3,0); + vcdp->declBus(c+7113,"VX_cache genblk5[2] bank core_req_arb out_per_byteen", false,-1, 15,0); + vcdp->declArray(c+7121,"VX_cache genblk5[2] bank core_req_arb out_per_addr", false,-1, 119,0); + vcdp->declArray(c+7153,"VX_cache genblk5[2] bank core_req_arb out_per_writedata", false,-1, 127,0); + vcdp->declQuad(c+7185,"VX_cache genblk5[2] bank core_req_arb out_per_tag", false,-1, 41,0); + vcdp->declBus(c+19049,"VX_cache genblk5[2] bank core_req_arb use_per_valids", false,-1, 3,0); + vcdp->declBus(c+19057,"VX_cache genblk5[2] bank core_req_arb use_per_rw", false,-1, 3,0); + vcdp->declBus(c+19065,"VX_cache genblk5[2] bank core_req_arb use_per_byteen", false,-1, 15,0); + vcdp->declArray(c+19073,"VX_cache genblk5[2] bank core_req_arb use_per_addr", false,-1, 119,0); + vcdp->declArray(c+19105,"VX_cache genblk5[2] bank core_req_arb use_per_writedata", false,-1, 127,0); + vcdp->declQuad(c+17585,"VX_cache genblk5[2] bank core_req_arb use_per_tag", false,-1, 41,0); + vcdp->declBus(c+19049,"VX_cache genblk5[2] bank core_req_arb qual_valids", false,-1, 3,0); + vcdp->declBus(c+19057,"VX_cache genblk5[2] bank core_req_arb qual_rw", false,-1, 3,0); + vcdp->declBus(c+19065,"VX_cache genblk5[2] bank core_req_arb qual_byteen", false,-1, 15,0); + vcdp->declArray(c+19073,"VX_cache genblk5[2] bank core_req_arb qual_addr", false,-1, 119,0); + vcdp->declArray(c+19105,"VX_cache genblk5[2] bank core_req_arb qual_writedata", false,-1, 127,0); + vcdp->declQuad(c+17585,"VX_cache genblk5[2] bank core_req_arb qual_tag", false,-1, 41,0); + vcdp->declBit(c+19137,"VX_cache genblk5[2] bank core_req_arb o_empty", false,-1); + vcdp->declBit(c+19145,"VX_cache genblk5[2] bank core_req_arb use_empty", false,-1); + vcdp->declBit(c+7201,"VX_cache genblk5[2] bank core_req_arb out_empty", false,-1); + vcdp->declBit(c+1049,"VX_cache genblk5[2] bank core_req_arb push_qual", false,-1); + vcdp->declBit(c+7209,"VX_cache genblk5[2] bank core_req_arb pop_qual", false,-1); + vcdp->declBus(c+7217,"VX_cache genblk5[2] bank core_req_arb real_out_per_valids", false,-1, 3,0); + vcdp->declBus(c+6313,"VX_cache genblk5[2] bank core_req_arb qual_request_index", false,-1, 1,0); + vcdp->declBit(c+6305,"VX_cache genblk5[2] bank core_req_arb qual_has_request", false,-1); + vcdp->declBus(c+25185,"VX_cache genblk5[2] bank core_req_arb reqq_queue DATAW", false,-1, 31,0); + vcdp->declBus(c+25081,"VX_cache genblk5[2] bank core_req_arb reqq_queue SIZE", false,-1, 31,0); + vcdp->declBus(c+25089,"VX_cache genblk5[2] bank core_req_arb reqq_queue BUFFERED_OUTPUT", false,-1, 31,0); + vcdp->declBit(c+24489,"VX_cache genblk5[2] bank core_req_arb reqq_queue clk", false,-1); + vcdp->declBit(c+24497,"VX_cache genblk5[2] bank core_req_arb reqq_queue reset", false,-1); + vcdp->declBit(c+1049,"VX_cache genblk5[2] bank core_req_arb reqq_queue push", false,-1); + vcdp->declBit(c+7209,"VX_cache genblk5[2] bank core_req_arb reqq_queue pop", false,-1); + vcdp->declArray(c+657,"VX_cache genblk5[2] bank core_req_arb reqq_queue data_in", false,-1, 313,0); + vcdp->declArray(c+7225,"VX_cache genblk5[2] bank core_req_arb reqq_queue data_out", false,-1, 313,0); + vcdp->declBit(c+19137,"VX_cache genblk5[2] bank core_req_arb reqq_queue empty", false,-1); + vcdp->declBit(c+17577,"VX_cache genblk5[2] bank core_req_arb reqq_queue full", false,-1); + vcdp->declBus(c+19153,"VX_cache genblk5[2] bank core_req_arb reqq_queue size", false,-1, 2,0); + vcdp->declBus(c+19153,"VX_cache genblk5[2] bank core_req_arb reqq_queue size_r", false,-1, 2,0); + vcdp->declBit(c+7305,"VX_cache genblk5[2] bank core_req_arb reqq_queue reading", false,-1); + vcdp->declBit(c+737,"VX_cache genblk5[2] bank core_req_arb reqq_queue writing", false,-1); + {int i; for (i=0; i<4; i++) { + vcdp->declArray(c+19161+i*10,"VX_cache genblk5[2] bank core_req_arb reqq_queue genblk3 data", true,(i+0), 313,0);}} + vcdp->declArray(c+19481,"VX_cache genblk5[2] bank core_req_arb reqq_queue genblk3 genblk2 head_r", false,-1, 313,0); + vcdp->declArray(c+19561,"VX_cache genblk5[2] bank core_req_arb reqq_queue genblk3 genblk2 curr_r", false,-1, 313,0); + vcdp->declBus(c+19641,"VX_cache genblk5[2] bank core_req_arb reqq_queue genblk3 genblk2 wr_ptr_r", false,-1, 1,0); + vcdp->declBus(c+19649,"VX_cache genblk5[2] bank core_req_arb reqq_queue genblk3 genblk2 rd_ptr_r", false,-1, 1,0); + vcdp->declBus(c+19657,"VX_cache genblk5[2] bank core_req_arb reqq_queue genblk3 genblk2 rd_ptr_next_r", false,-1, 1,0); + vcdp->declBit(c+19137,"VX_cache genblk5[2] bank core_req_arb reqq_queue genblk3 genblk2 empty_r", false,-1); + vcdp->declBit(c+17577,"VX_cache genblk5[2] bank core_req_arb reqq_queue genblk3 genblk2 full_r", false,-1); + vcdp->declBit(c+19665,"VX_cache genblk5[2] bank core_req_arb reqq_queue genblk3 genblk2 bypass_r", false,-1); + vcdp->declBus(c+25081,"VX_cache genblk5[2] bank core_req_arb sel_bank N", false,-1, 31,0); + vcdp->declBit(c+24489,"VX_cache genblk5[2] bank core_req_arb sel_bank clk", false,-1); + vcdp->declBit(c+24497,"VX_cache genblk5[2] bank core_req_arb sel_bank reset", false,-1); + vcdp->declBus(c+19049,"VX_cache genblk5[2] bank core_req_arb sel_bank requests", false,-1, 3,0); + vcdp->declBus(c+6313,"VX_cache genblk5[2] bank core_req_arb sel_bank grant_index", false,-1, 1,0); + vcdp->declBus(c+7313,"VX_cache genblk5[2] bank core_req_arb sel_bank grant_onehot", false,-1, 3,0); + vcdp->declBit(c+6305,"VX_cache genblk5[2] bank core_req_arb sel_bank grant_valid", false,-1); + vcdp->declBus(c+7313,"VX_cache genblk5[2] bank core_req_arb sel_bank genblk2 grant_onehot_r", false,-1, 3,0); + vcdp->declBus(c+25081,"VX_cache genblk5[2] bank core_req_arb sel_bank genblk2 priority_encoder N", false,-1, 31,0); + vcdp->declBus(c+19049,"VX_cache genblk5[2] bank core_req_arb sel_bank genblk2 priority_encoder data_in", false,-1, 3,0); + vcdp->declBus(c+6313,"VX_cache genblk5[2] bank core_req_arb sel_bank genblk2 priority_encoder data_out", false,-1, 1,0); + vcdp->declBit(c+6305,"VX_cache genblk5[2] bank core_req_arb sel_bank genblk2 priority_encoder valid_out", false,-1); + vcdp->declBus(c+7321,"VX_cache genblk5[2] bank core_req_arb sel_bank genblk2 priority_encoder i", false,-1, 31,0); + vcdp->declBus(c+25193,"VX_cache genblk5[2] bank s0_1_c0 N", false,-1, 31,0); + vcdp->declBus(c+25057,"VX_cache genblk5[2] bank s0_1_c0 PASSTHRU", false,-1, 31,0); + vcdp->declBit(c+24489,"VX_cache genblk5[2] bank s0_1_c0 clk", false,-1); + vcdp->declBit(c+24497,"VX_cache genblk5[2] bank s0_1_c0 reset", false,-1); + vcdp->declBit(c+6441,"VX_cache genblk5[2] bank s0_1_c0 stall", false,-1); + vcdp->declBit(c+25137,"VX_cache genblk5[2] bank s0_1_c0 flush", false,-1); + vcdp->declArray(c+7329,"VX_cache genblk5[2] bank s0_1_c0 in", false,-1, 242,0); + vcdp->declArray(c+19673,"VX_cache genblk5[2] bank s0_1_c0 out", false,-1, 242,0); + vcdp->declArray(c+19673,"VX_cache genblk5[2] bank s0_1_c0 value", false,-1, 242,0); + vcdp->declBus(c+25065,"VX_cache genblk5[2] bank tag_data_access CACHE_SIZE", false,-1, 31,0); + vcdp->declBus(c+25073,"VX_cache genblk5[2] bank tag_data_access BANK_LINE_SIZE", false,-1, 31,0); + vcdp->declBus(c+25081,"VX_cache genblk5[2] bank tag_data_access NUM_BANKS", false,-1, 31,0); + vcdp->declBus(c+25081,"VX_cache genblk5[2] bank tag_data_access WORD_SIZE", false,-1, 31,0); + vcdp->declBus(c+25089,"VX_cache genblk5[2] bank tag_data_access STAGE_1_CYCLES", false,-1, 31,0); + vcdp->declBus(c+25089,"VX_cache genblk5[2] bank tag_data_access WRITE_ENABLE", false,-1, 31,0); + vcdp->declBus(c+25089,"VX_cache genblk5[2] bank tag_data_access DRAM_ENABLE", false,-1, 31,0); + vcdp->declBit(c+24489,"VX_cache genblk5[2] bank tag_data_access clk", false,-1); + vcdp->declBit(c+24497,"VX_cache genblk5[2] bank tag_data_access reset", false,-1); + vcdp->declBit(c+6441,"VX_cache genblk5[2] bank tag_data_access stall", false,-1); + vcdp->declBit(c+6825,"VX_cache genblk5[2] bank tag_data_access is_snp_st1e", false,-1); + vcdp->declBit(c+6833,"VX_cache genblk5[2] bank tag_data_access snp_invalidate_st1e", false,-1); + vcdp->declBit(c+6441,"VX_cache genblk5[2] bank tag_data_access stall_bank_pipe", false,-1); + vcdp->declBit(c+6393,"VX_cache genblk5[2] bank tag_data_access force_request_miss_st1e", false,-1); + vcdp->declBus(c+7393,"VX_cache genblk5[2] bank tag_data_access readaddr_st10", false,-1, 5,0); + vcdp->declBus(c+6889,"VX_cache genblk5[2] bank tag_data_access writeaddr_st1e", false,-1, 25,0); + vcdp->declBit(c+6865,"VX_cache genblk5[2] bank tag_data_access valid_req_st1e", false,-1); + vcdp->declBit(c+7401,"VX_cache genblk5[2] bank tag_data_access writefill_st1e", false,-1); + vcdp->declBus(c+7409,"VX_cache genblk5[2] bank tag_data_access writeword_st1e", false,-1, 31,0); + vcdp->declArray(c+7417,"VX_cache genblk5[2] bank tag_data_access writedata_st1e", false,-1, 127,0); + vcdp->declBit(c+6801,"VX_cache genblk5[2] bank tag_data_access mem_rw_st1e", false,-1); + vcdp->declBus(c+6809,"VX_cache genblk5[2] bank tag_data_access mem_byteen_st1e", false,-1, 3,0); + vcdp->declBus(c+7449,"VX_cache genblk5[2] bank tag_data_access wordsel_st1e", false,-1, 1,0); + vcdp->declBus(c+6705,"VX_cache genblk5[2] bank tag_data_access readword_st1e", false,-1, 31,0); + vcdp->declArray(c+6713,"VX_cache genblk5[2] bank tag_data_access readdata_st1e", false,-1, 127,0); + vcdp->declBus(c+6745,"VX_cache genblk5[2] bank tag_data_access readtag_st1e", false,-1, 19,0); + vcdp->declBit(c+6753,"VX_cache genblk5[2] bank tag_data_access miss_st1e", false,-1); + vcdp->declBit(c+6761,"VX_cache genblk5[2] bank tag_data_access dirty_st1e", false,-1); + vcdp->declBus(c+6769,"VX_cache genblk5[2] bank tag_data_access dirtyb_st1e", false,-1, 15,0); + vcdp->declBit(c+6817,"VX_cache genblk5[2] bank tag_data_access fill_saw_dirty_st1e", false,-1); + vcdp->declBit(c+6841,"VX_cache genblk5[2] bank tag_data_access snp_to_mrvq_st1e", false,-1); + vcdp->declBit(c+6849,"VX_cache genblk5[2] bank tag_data_access mrvq_init_ready_state_st1e", false,-1); + {int i; for (i=0; i<1; i++) { + vcdp->declBit(c+7457+i*1,"VX_cache genblk5[2] bank tag_data_access read_valid_st1c", true,(i+0));}} + {int i; for (i=0; i<1; i++) { + vcdp->declBit(c+7465+i*1,"VX_cache genblk5[2] bank tag_data_access read_dirty_st1c", true,(i+0));}} + {int i; for (i=0; i<1; i++) { + vcdp->declBus(c+7473+i*1,"VX_cache genblk5[2] bank tag_data_access read_dirtyb_st1c", true,(i+0), 15,0);}} + {int i; for (i=0; i<1; i++) { + vcdp->declBus(c+7481+i*1,"VX_cache genblk5[2] bank tag_data_access read_tag_st1c", true,(i+0), 19,0);}} + {int i; for (i=0; i<1; i++) { + vcdp->declArray(c+7489+i*4,"VX_cache genblk5[2] bank tag_data_access read_data_st1c", true,(i+0), 127,0);}} + vcdp->declBit(c+7521,"VX_cache genblk5[2] bank tag_data_access qual_read_valid_st1", false,-1); + vcdp->declBit(c+7529,"VX_cache genblk5[2] bank tag_data_access qual_read_dirty_st1", false,-1); + vcdp->declBus(c+7537,"VX_cache genblk5[2] bank tag_data_access qual_read_dirtyb_st1", false,-1, 15,0); + vcdp->declBus(c+7545,"VX_cache genblk5[2] bank tag_data_access qual_read_tag_st1", false,-1, 19,0); + vcdp->declArray(c+7553,"VX_cache genblk5[2] bank tag_data_access qual_read_data_st1", false,-1, 127,0); + vcdp->declBit(c+7585,"VX_cache genblk5[2] bank tag_data_access use_read_valid_st1e", false,-1); + vcdp->declBit(c+7593,"VX_cache genblk5[2] bank tag_data_access use_read_dirty_st1e", false,-1); + vcdp->declBus(c+6769,"VX_cache genblk5[2] bank tag_data_access use_read_dirtyb_st1e", false,-1, 15,0); + vcdp->declBus(c+6745,"VX_cache genblk5[2] bank tag_data_access use_read_tag_st1e", false,-1, 19,0); + vcdp->declArray(c+6713,"VX_cache genblk5[2] bank tag_data_access use_read_data_st1e", false,-1, 127,0); + vcdp->declBus(c+7601,"VX_cache genblk5[2] bank tag_data_access use_write_enable", false,-1, 15,0); + vcdp->declArray(c+7609,"VX_cache genblk5[2] bank tag_data_access use_write_data", false,-1, 127,0); + vcdp->declBit(c+6753,"VX_cache genblk5[2] bank tag_data_access fill_sent", false,-1); + vcdp->declBit(c+7641,"VX_cache genblk5[2] bank tag_data_access invalidate_line", false,-1); + vcdp->declBit(c+7649,"VX_cache genblk5[2] bank tag_data_access tags_match", false,-1); + vcdp->declBit(c+7657,"VX_cache genblk5[2] bank tag_data_access real_writefill", false,-1); + vcdp->declBus(c+7665,"VX_cache genblk5[2] bank tag_data_access writetag_st1e", false,-1, 19,0); + vcdp->declBus(c+7393,"VX_cache genblk5[2] bank tag_data_access writeladdr_st1e", false,-1, 5,0); + vcdp->declBus(c+7673,"VX_cache genblk5[2] bank tag_data_access we", false,-1, 15,0); + vcdp->declArray(c+7609,"VX_cache genblk5[2] bank tag_data_access data_write", false,-1, 127,0); + vcdp->declBit(c+7681,"VX_cache genblk5[2] bank tag_data_access should_write", false,-1); + vcdp->declBit(c+7641,"VX_cache genblk5[2] bank tag_data_access snoop_hit_no_pending", false,-1); + vcdp->declBit(c+7689,"VX_cache genblk5[2] bank tag_data_access req_invalid", false,-1); + vcdp->declBit(c+7697,"VX_cache genblk5[2] bank tag_data_access req_miss", false,-1); + vcdp->declBit(c+7705,"VX_cache genblk5[2] bank tag_data_access real_miss", false,-1); + vcdp->declBit(c+7713,"VX_cache genblk5[2] bank tag_data_access force_core_miss", false,-1); + vcdp->declBit(c+7721,"VX_cache genblk5[2] bank tag_data_access genblk4[0] normal_write", false,-1); + vcdp->declBit(c+7729,"VX_cache genblk5[2] bank tag_data_access genblk4[1] normal_write", false,-1); + vcdp->declBit(c+7737,"VX_cache genblk5[2] bank tag_data_access genblk4[2] normal_write", false,-1); + vcdp->declBit(c+7745,"VX_cache genblk5[2] bank tag_data_access genblk4[3] normal_write", false,-1); + vcdp->declBus(c+25065,"VX_cache genblk5[2] bank tag_data_access tag_data_structure CACHE_SIZE", false,-1, 31,0); + vcdp->declBus(c+25073,"VX_cache genblk5[2] bank tag_data_access tag_data_structure BANK_LINE_SIZE", false,-1, 31,0); + vcdp->declBus(c+25081,"VX_cache genblk5[2] bank tag_data_access tag_data_structure NUM_BANKS", false,-1, 31,0); + vcdp->declBus(c+25081,"VX_cache genblk5[2] bank tag_data_access tag_data_structure WORD_SIZE", false,-1, 31,0); + vcdp->declBit(c+24489,"VX_cache genblk5[2] bank tag_data_access tag_data_structure clk", false,-1); + vcdp->declBit(c+24497,"VX_cache genblk5[2] bank tag_data_access tag_data_structure reset", false,-1); + vcdp->declBit(c+6441,"VX_cache genblk5[2] bank tag_data_access tag_data_structure stall_bank_pipe", false,-1); + vcdp->declBus(c+7393,"VX_cache genblk5[2] bank tag_data_access tag_data_structure read_addr", false,-1, 5,0); + vcdp->declBit(c+7521,"VX_cache genblk5[2] bank tag_data_access tag_data_structure read_valid", false,-1); + vcdp->declBit(c+7529,"VX_cache genblk5[2] bank tag_data_access tag_data_structure read_dirty", false,-1); + vcdp->declBus(c+7537,"VX_cache genblk5[2] bank tag_data_access tag_data_structure read_dirtyb", false,-1, 15,0); + vcdp->declBus(c+7545,"VX_cache genblk5[2] bank tag_data_access tag_data_structure read_tag", false,-1, 19,0); + vcdp->declArray(c+7553,"VX_cache genblk5[2] bank tag_data_access tag_data_structure read_data", false,-1, 127,0); + vcdp->declBit(c+7641,"VX_cache genblk5[2] bank tag_data_access tag_data_structure invalidate", false,-1); + vcdp->declBus(c+7601,"VX_cache genblk5[2] bank tag_data_access tag_data_structure write_enable", false,-1, 15,0); + vcdp->declBit(c+7657,"VX_cache genblk5[2] bank tag_data_access tag_data_structure write_fill", false,-1); + vcdp->declBus(c+7393,"VX_cache genblk5[2] bank tag_data_access tag_data_structure write_addr", false,-1, 5,0); + vcdp->declBus(c+7665,"VX_cache genblk5[2] bank tag_data_access tag_data_structure tag_index", false,-1, 19,0); + vcdp->declArray(c+7609,"VX_cache genblk5[2] bank tag_data_access tag_data_structure write_data", false,-1, 127,0); + vcdp->declBit(c+6753,"VX_cache genblk5[2] bank tag_data_access tag_data_structure fill_sent", false,-1); + vcdp->declQuad(c+19737,"VX_cache genblk5[2] bank tag_data_access tag_data_structure dirty", false,-1, 63,0); + vcdp->declQuad(c+19753,"VX_cache genblk5[2] bank tag_data_access tag_data_structure valid", false,-1, 63,0); + vcdp->declBit(c+7753,"VX_cache genblk5[2] bank tag_data_access tag_data_structure do_write", false,-1); + vcdp->declBus(c+19769,"VX_cache genblk5[2] bank tag_data_access tag_data_structure i", false,-1, 31,0); + vcdp->declBus(c+19777,"VX_cache genblk5[2] bank tag_data_access tag_data_structure j", false,-1, 31,0); + vcdp->declBus(c+25201,"VX_cache genblk5[2] bank tag_data_access s0_1_c0 N", false,-1, 31,0); + vcdp->declBus(c+25089,"VX_cache genblk5[2] bank tag_data_access s0_1_c0 PASSTHRU", false,-1, 31,0); + vcdp->declBit(c+24489,"VX_cache genblk5[2] bank tag_data_access s0_1_c0 clk", false,-1); + vcdp->declBit(c+24497,"VX_cache genblk5[2] bank tag_data_access s0_1_c0 reset", false,-1); + vcdp->declBit(c+6441,"VX_cache genblk5[2] bank tag_data_access s0_1_c0 stall", false,-1); + vcdp->declBit(c+25137,"VX_cache genblk5[2] bank tag_data_access s0_1_c0 flush", false,-1); + vcdp->declArray(c+7761,"VX_cache genblk5[2] bank tag_data_access s0_1_c0 in", false,-1, 165,0); + vcdp->declArray(c+7761,"VX_cache genblk5[2] bank tag_data_access s0_1_c0 out", false,-1, 165,0); + vcdp->declArray(c+19785,"VX_cache genblk5[2] bank tag_data_access s0_1_c0 value", false,-1, 165,0); + vcdp->declBus(c+25209,"VX_cache genblk5[2] bank st_1e_2 N", false,-1, 31,0); + vcdp->declBus(c+25057,"VX_cache genblk5[2] bank st_1e_2 PASSTHRU", false,-1, 31,0); + vcdp->declBit(c+24489,"VX_cache genblk5[2] bank st_1e_2 clk", false,-1); + vcdp->declBit(c+24497,"VX_cache genblk5[2] bank st_1e_2 reset", false,-1); + vcdp->declBit(c+6441,"VX_cache genblk5[2] bank st_1e_2 stall", false,-1); + vcdp->declBit(c+25137,"VX_cache genblk5[2] bank st_1e_2 flush", false,-1); + vcdp->declArray(c+7809,"VX_cache genblk5[2] bank st_1e_2 in", false,-1, 315,0); + vcdp->declArray(c+19833,"VX_cache genblk5[2] bank st_1e_2 out", false,-1, 315,0); + vcdp->declArray(c+19833,"VX_cache genblk5[2] bank st_1e_2 value", false,-1, 315,0); + vcdp->declBus(c+25057,"VX_cache genblk5[2] bank cache_miss_resrv CACHE_ID", false,-1, 31,0); + vcdp->declBus(c+25233,"VX_cache genblk5[2] bank cache_miss_resrv BANK_ID", false,-1, 31,0); + vcdp->declBus(c+25073,"VX_cache genblk5[2] bank cache_miss_resrv BANK_LINE_SIZE", false,-1, 31,0); + vcdp->declBus(c+25081,"VX_cache genblk5[2] bank cache_miss_resrv NUM_BANKS", false,-1, 31,0); + vcdp->declBus(c+25081,"VX_cache genblk5[2] bank cache_miss_resrv WORD_SIZE", false,-1, 31,0); + vcdp->declBus(c+25081,"VX_cache genblk5[2] bank cache_miss_resrv NUM_REQUESTS", false,-1, 31,0); + vcdp->declBus(c+25073,"VX_cache genblk5[2] bank cache_miss_resrv MRVQ_SIZE", false,-1, 31,0); + vcdp->declBus(c+25097,"VX_cache genblk5[2] bank cache_miss_resrv CORE_TAG_WIDTH", false,-1, 31,0); + vcdp->declBus(c+25113,"VX_cache genblk5[2] bank cache_miss_resrv SNP_REQ_TAG_WIDTH", false,-1, 31,0); + vcdp->declBit(c+24489,"VX_cache genblk5[2] bank cache_miss_resrv clk", false,-1); + vcdp->declBit(c+24497,"VX_cache genblk5[2] bank cache_miss_resrv reset", false,-1); + vcdp->declBit(c+6937,"VX_cache genblk5[2] bank cache_miss_resrv miss_add", false,-1); + vcdp->declBit(c+6945,"VX_cache genblk5[2] bank cache_miss_resrv is_mrvq", false,-1); + vcdp->declBus(c+10169,"VX_cache genblk5[2] bank cache_miss_resrv miss_add_addr", false,-1, 25,0); + vcdp->declBus(c+17745,"VX_cache genblk5[2] bank cache_miss_resrv miss_add_wsel", false,-1, 1,0); + vcdp->declBus(c+17753,"VX_cache genblk5[2] bank cache_miss_resrv miss_add_data", false,-1, 31,0); + vcdp->declBus(c+17689,"VX_cache genblk5[2] bank cache_miss_resrv miss_add_tid", false,-1, 1,0); + vcdp->declQuad(c+17697,"VX_cache genblk5[2] bank cache_miss_resrv miss_add_tag", false,-1, 41,0); + vcdp->declBit(c+17713,"VX_cache genblk5[2] bank cache_miss_resrv miss_add_rw", false,-1); + vcdp->declBus(c+17721,"VX_cache genblk5[2] bank cache_miss_resrv miss_add_byteen", false,-1, 3,0); + vcdp->declBit(c+6905,"VX_cache genblk5[2] bank cache_miss_resrv mrvq_init_ready_state", false,-1); + vcdp->declBit(c+17857,"VX_cache genblk5[2] bank cache_miss_resrv miss_add_is_snp", false,-1); + vcdp->declBit(c+17865,"VX_cache genblk5[2] bank cache_miss_resrv miss_add_snp_invalidate", false,-1); + vcdp->declBit(c+17601,"VX_cache genblk5[2] bank cache_miss_resrv miss_resrv_full", false,-1); + vcdp->declBit(c+17609,"VX_cache genblk5[2] bank cache_miss_resrv miss_resrv_stop", false,-1); + vcdp->declBit(c+7401,"VX_cache genblk5[2] bank cache_miss_resrv is_fill_st1", false,-1); + vcdp->declBus(c+6889,"VX_cache genblk5[2] bank cache_miss_resrv fill_addr_st1", false,-1, 25,0); + vcdp->declBit(c+6377,"VX_cache genblk5[2] bank cache_miss_resrv pending_hazard", false,-1); + vcdp->declBit(c+6353,"VX_cache genblk5[2] bank cache_miss_resrv miss_resrv_pop", false,-1); + vcdp->declBit(c+6361,"VX_cache genblk5[2] bank cache_miss_resrv miss_resrv_valid_st0", false,-1); + vcdp->declBus(c+17625,"VX_cache genblk5[2] bank cache_miss_resrv miss_resrv_addr_st0", false,-1, 25,0); + vcdp->declBus(c+17633,"VX_cache genblk5[2] bank cache_miss_resrv miss_resrv_wsel_st0", false,-1, 1,0); + vcdp->declBus(c+17641,"VX_cache genblk5[2] bank cache_miss_resrv miss_resrv_data_st0", false,-1, 31,0); + vcdp->declBus(c+17617,"VX_cache genblk5[2] bank cache_miss_resrv miss_resrv_tid_st0", false,-1, 1,0); + vcdp->declQuad(c+17649,"VX_cache genblk5[2] bank cache_miss_resrv miss_resrv_tag_st0", false,-1, 41,0); + vcdp->declBit(c+6369,"VX_cache genblk5[2] bank cache_miss_resrv miss_resrv_rw_st0", false,-1); + vcdp->declBus(c+17665,"VX_cache genblk5[2] bank cache_miss_resrv miss_resrv_byteen_st0", false,-1, 3,0); + vcdp->declBit(c+17673,"VX_cache genblk5[2] bank cache_miss_resrv miss_resrv_is_snp_st0", false,-1); + vcdp->declBit(c+17681,"VX_cache genblk5[2] bank cache_miss_resrv miss_resrv_snp_invalidate_st0", false,-1); + {int i; for (i=0; i<16; i++) { + vcdp->declArray(c+19913+i*3,"VX_cache genblk5[2] bank cache_miss_resrv metadata_table", true,(i+0), 84,0);}} + vcdp->declArray(c+20297,"VX_cache genblk5[2] bank cache_miss_resrv addr_table", false,-1, 415,0); + vcdp->declBus(c+20401,"VX_cache genblk5[2] bank cache_miss_resrv valid_table", false,-1, 15,0); + vcdp->declBus(c+20409,"VX_cache genblk5[2] bank cache_miss_resrv ready_table", false,-1, 15,0); + vcdp->declBus(c+20417,"VX_cache genblk5[2] bank cache_miss_resrv schedule_ptr", false,-1, 3,0); + vcdp->declBus(c+20425,"VX_cache genblk5[2] bank cache_miss_resrv head_ptr", false,-1, 3,0); + vcdp->declBus(c+20433,"VX_cache genblk5[2] bank cache_miss_resrv tail_ptr", false,-1, 3,0); + vcdp->declBus(c+20441,"VX_cache genblk5[2] bank cache_miss_resrv size", false,-1, 4,0); + vcdp->declBit(c+20449,"VX_cache genblk5[2] bank cache_miss_resrv enqueue_possible", false,-1); + vcdp->declBus(c+20433,"VX_cache genblk5[2] bank cache_miss_resrv enqueue_index", false,-1, 3,0); + vcdp->declBus(c+7889,"VX_cache genblk5[2] bank cache_miss_resrv make_ready", false,-1, 15,0); + vcdp->declBus(c+7897,"VX_cache genblk5[2] bank cache_miss_resrv make_ready_push", false,-1, 15,0); + vcdp->declBus(c+7905,"VX_cache genblk5[2] bank cache_miss_resrv valid_address_match", false,-1, 15,0); + vcdp->declBit(c+6361,"VX_cache genblk5[2] bank cache_miss_resrv dequeue_possible", false,-1); + vcdp->declBus(c+20417,"VX_cache genblk5[2] bank cache_miss_resrv dequeue_index", false,-1, 3,0); + vcdp->declBit(c+7913,"VX_cache genblk5[2] bank cache_miss_resrv mrvq_push", false,-1); + vcdp->declBit(c+7921,"VX_cache genblk5[2] bank cache_miss_resrv mrvq_pop", false,-1); + vcdp->declBit(c+7929,"VX_cache genblk5[2] bank cache_miss_resrv recover_state", false,-1); + vcdp->declBit(c+7937,"VX_cache genblk5[2] bank cache_miss_resrv increment_head", false,-1); + vcdp->declBit(c+7945,"VX_cache genblk5[2] bank cache_miss_resrv update_ready", false,-1); + vcdp->declBit(c+7953,"VX_cache genblk5[2] bank cache_miss_resrv qual_mrvq_init", false,-1); + vcdp->declBus(c+25217,"VX_cache genblk5[2] bank cwb_queue DATAW", false,-1, 31,0); + vcdp->declBus(c+25081,"VX_cache genblk5[2] bank cwb_queue SIZE", false,-1, 31,0); + vcdp->declBus(c+25089,"VX_cache genblk5[2] bank cwb_queue BUFFERED_OUTPUT", false,-1, 31,0); + vcdp->declBit(c+24489,"VX_cache genblk5[2] bank cwb_queue clk", false,-1); + vcdp->declBit(c+24497,"VX_cache genblk5[2] bank cwb_queue reset", false,-1); + vcdp->declBit(c+6953,"VX_cache genblk5[2] bank cwb_queue push", false,-1); + vcdp->declBit(c+1033,"VX_cache genblk5[2] bank cwb_queue pop", false,-1); + vcdp->declArray(c+7961,"VX_cache genblk5[2] bank cwb_queue data_in", false,-1, 75,0); + vcdp->declArray(c+7985,"VX_cache genblk5[2] bank cwb_queue data_out", false,-1, 75,0); + vcdp->declBit(c+17905,"VX_cache genblk5[2] bank cwb_queue empty", false,-1); + vcdp->declBit(c+17913,"VX_cache genblk5[2] bank cwb_queue full", false,-1); + vcdp->declBus(c+20457,"VX_cache genblk5[2] bank cwb_queue size", false,-1, 2,0); + vcdp->declBus(c+20457,"VX_cache genblk5[2] bank cwb_queue size_r", false,-1, 2,0); + vcdp->declBit(c+745,"VX_cache genblk5[2] bank cwb_queue reading", false,-1); + vcdp->declBit(c+8009,"VX_cache genblk5[2] bank cwb_queue writing", false,-1); + {int i; for (i=0; i<4; i++) { + vcdp->declArray(c+20465+i*3,"VX_cache genblk5[2] bank cwb_queue genblk3 data", true,(i+0), 75,0);}} + vcdp->declArray(c+20561,"VX_cache genblk5[2] bank cwb_queue genblk3 genblk2 head_r", false,-1, 75,0); + vcdp->declArray(c+20585,"VX_cache genblk5[2] bank cwb_queue genblk3 genblk2 curr_r", false,-1, 75,0); + vcdp->declBus(c+20609,"VX_cache genblk5[2] bank cwb_queue genblk3 genblk2 wr_ptr_r", false,-1, 1,0); + vcdp->declBus(c+20617,"VX_cache genblk5[2] bank cwb_queue genblk3 genblk2 rd_ptr_r", false,-1, 1,0); + vcdp->declBus(c+20625,"VX_cache genblk5[2] bank cwb_queue genblk3 genblk2 rd_ptr_next_r", false,-1, 1,0); + vcdp->declBit(c+17905,"VX_cache genblk5[2] bank cwb_queue genblk3 genblk2 empty_r", false,-1); + vcdp->declBit(c+17913,"VX_cache genblk5[2] bank cwb_queue genblk3 genblk2 full_r", false,-1); + vcdp->declBit(c+20633,"VX_cache genblk5[2] bank cwb_queue genblk3 genblk2 bypass_r", false,-1); + vcdp->declBus(c+25225,"VX_cache genblk5[2] bank dwb_queue DATAW", false,-1, 31,0); + vcdp->declBus(c+25081,"VX_cache genblk5[2] bank dwb_queue SIZE", false,-1, 31,0); + vcdp->declBus(c+25089,"VX_cache genblk5[2] bank dwb_queue BUFFERED_OUTPUT", false,-1, 31,0); + vcdp->declBit(c+24489,"VX_cache genblk5[2] bank dwb_queue clk", false,-1); + vcdp->declBit(c+24497,"VX_cache genblk5[2] bank dwb_queue reset", false,-1); + vcdp->declBit(c+6977,"VX_cache genblk5[2] bank dwb_queue push", false,-1); + vcdp->declBit(c+1041,"VX_cache genblk5[2] bank dwb_queue pop", false,-1); + vcdp->declArray(c+8017,"VX_cache genblk5[2] bank dwb_queue data_in", false,-1, 199,0); + vcdp->declArray(c+8073,"VX_cache genblk5[2] bank dwb_queue data_out", false,-1, 199,0); + vcdp->declBit(c+17921,"VX_cache genblk5[2] bank dwb_queue empty", false,-1); + vcdp->declBit(c+17929,"VX_cache genblk5[2] bank dwb_queue full", false,-1); + vcdp->declBus(c+20641,"VX_cache genblk5[2] bank dwb_queue size", false,-1, 2,0); + vcdp->declBus(c+20641,"VX_cache genblk5[2] bank dwb_queue size_r", false,-1, 2,0); + vcdp->declBit(c+753,"VX_cache genblk5[2] bank dwb_queue reading", false,-1); + vcdp->declBit(c+8129,"VX_cache genblk5[2] bank dwb_queue writing", false,-1); + {int i; for (i=0; i<4; i++) { + vcdp->declArray(c+20649+i*7,"VX_cache genblk5[2] bank dwb_queue genblk3 data", true,(i+0), 199,0);}} + vcdp->declArray(c+20873,"VX_cache genblk5[2] bank dwb_queue genblk3 genblk2 head_r", false,-1, 199,0); + vcdp->declArray(c+20929,"VX_cache genblk5[2] bank dwb_queue genblk3 genblk2 curr_r", false,-1, 199,0); + vcdp->declBus(c+20985,"VX_cache genblk5[2] bank dwb_queue genblk3 genblk2 wr_ptr_r", false,-1, 1,0); + vcdp->declBus(c+20993,"VX_cache genblk5[2] bank dwb_queue genblk3 genblk2 rd_ptr_r", false,-1, 1,0); + vcdp->declBus(c+21001,"VX_cache genblk5[2] bank dwb_queue genblk3 genblk2 rd_ptr_next_r", false,-1, 1,0); + vcdp->declBit(c+17921,"VX_cache genblk5[2] bank dwb_queue genblk3 genblk2 empty_r", false,-1); + vcdp->declBit(c+17929,"VX_cache genblk5[2] bank dwb_queue genblk3 genblk2 full_r", false,-1); + vcdp->declBit(c+21009,"VX_cache genblk5[2] bank dwb_queue genblk3 genblk2 bypass_r", false,-1); + vcdp->declBus(c+25057,"VX_cache genblk5[3] bank CACHE_ID", false,-1, 31,0); + vcdp->declBus(c+25241,"VX_cache genblk5[3] bank BANK_ID", false,-1, 31,0); + vcdp->declBus(c+25065,"VX_cache genblk5[3] bank CACHE_SIZE", false,-1, 31,0); + vcdp->declBus(c+25073,"VX_cache genblk5[3] bank BANK_LINE_SIZE", false,-1, 31,0); + vcdp->declBus(c+25081,"VX_cache genblk5[3] bank NUM_BANKS", false,-1, 31,0); + vcdp->declBus(c+25081,"VX_cache genblk5[3] bank WORD_SIZE", false,-1, 31,0); + vcdp->declBus(c+25081,"VX_cache genblk5[3] bank NUM_REQUESTS", false,-1, 31,0); + vcdp->declBus(c+25089,"VX_cache genblk5[3] bank STAGE_1_CYCLES", false,-1, 31,0); + vcdp->declBus(c+25081,"VX_cache genblk5[3] bank CREQ_SIZE", false,-1, 31,0); + vcdp->declBus(c+25073,"VX_cache genblk5[3] bank MRVQ_SIZE", false,-1, 31,0); + vcdp->declBus(c+25073,"VX_cache genblk5[3] bank DFPQ_SIZE", false,-1, 31,0); + vcdp->declBus(c+25073,"VX_cache genblk5[3] bank SNRQ_SIZE", false,-1, 31,0); + vcdp->declBus(c+25081,"VX_cache genblk5[3] bank CWBQ_SIZE", false,-1, 31,0); + vcdp->declBus(c+25081,"VX_cache genblk5[3] bank DWBQ_SIZE", false,-1, 31,0); + vcdp->declBus(c+25081,"VX_cache genblk5[3] bank DFQQ_SIZE", false,-1, 31,0); + vcdp->declBus(c+25089,"VX_cache genblk5[3] bank WRITE_ENABLE", false,-1, 31,0); + vcdp->declBus(c+25089,"VX_cache genblk5[3] bank DRAM_ENABLE", false,-1, 31,0); + vcdp->declBus(c+25057,"VX_cache genblk5[3] bank SNOOP_FORWARDING", false,-1, 31,0); + vcdp->declBus(c+25097,"VX_cache genblk5[3] bank CORE_TAG_WIDTH", false,-1, 31,0); + vcdp->declBus(c+25105,"VX_cache genblk5[3] bank CORE_TAG_ID_BITS", false,-1, 31,0); + vcdp->declBus(c+25113,"VX_cache genblk5[3] bank SNP_REQ_TAG_WIDTH", false,-1, 31,0); + vcdp->declBit(c+24489,"VX_cache genblk5[3] bank clk", false,-1); + vcdp->declBit(c+24497,"VX_cache genblk5[3] bank reset", false,-1); + vcdp->declBus(c+129,"VX_cache genblk5[3] bank core_req_valid", false,-1, 3,0); + vcdp->declBus(c+24513,"VX_cache genblk5[3] bank core_req_rw", false,-1, 3,0); + vcdp->declBus(c+24521,"VX_cache genblk5[3] bank core_req_byteen", false,-1, 15,0); + vcdp->declArray(c+24529,"VX_cache genblk5[3] bank core_req_addr", false,-1, 119,0); + vcdp->declArray(c+24561,"VX_cache genblk5[3] bank core_req_data", false,-1, 127,0); + vcdp->declQuad(c+24593,"VX_cache genblk5[3] bank core_req_tag", false,-1, 41,0); + vcdp->declBit(c+10225,"VX_cache genblk5[3] bank core_req_ready", false,-1); + vcdp->declBit(c+10193,"VX_cache genblk5[3] bank core_rsp_valid", false,-1); + vcdp->declBus(c+1809,"VX_cache genblk5[3] bank core_rsp_tid", false,-1, 1,0); + vcdp->declBus(c+1817,"VX_cache genblk5[3] bank core_rsp_data", false,-1, 31,0); + vcdp->declQuad(c+1825,"VX_cache genblk5[3] bank core_rsp_tag", false,-1, 41,0); + vcdp->declBit(c+137,"VX_cache genblk5[3] bank core_rsp_ready", false,-1); + vcdp->declBit(c+1841,"VX_cache genblk5[3] bank dram_fill_req_valid", false,-1); + vcdp->declBus(c+10209,"VX_cache genblk5[3] bank dram_fill_req_addr", false,-1, 25,0); + vcdp->declBit(c+10065,"VX_cache genblk5[3] bank dram_fill_req_ready", false,-1); + vcdp->declBit(c+25025,"VX_cache genblk5[3] bank dram_fill_rsp_valid", false,-1); + vcdp->declArray(c+24769,"VX_cache genblk5[3] bank dram_fill_rsp_data", false,-1, 127,0); + vcdp->declBus(c+24969,"VX_cache genblk5[3] bank dram_fill_rsp_addr", false,-1, 25,0); + vcdp->declBit(c+10201,"VX_cache genblk5[3] bank dram_fill_rsp_ready", false,-1); + vcdp->declBit(c+1849,"VX_cache genblk5[3] bank dram_wb_req_valid", false,-1); + vcdp->declBus(c+1857,"VX_cache genblk5[3] bank dram_wb_req_byteen", false,-1, 15,0); + vcdp->declBus(c+1865,"VX_cache genblk5[3] bank dram_wb_req_addr", false,-1, 25,0); + vcdp->declArray(c+1873,"VX_cache genblk5[3] bank dram_wb_req_data", false,-1, 127,0); + vcdp->declBit(c+145,"VX_cache genblk5[3] bank dram_wb_req_ready", false,-1); + vcdp->declBit(c+25033,"VX_cache genblk5[3] bank snp_req_valid", false,-1); + vcdp->declBus(c+24985,"VX_cache genblk5[3] bank snp_req_addr", false,-1, 25,0); + vcdp->declBit(c+24833,"VX_cache genblk5[3] bank snp_req_invalidate", false,-1); + vcdp->declBus(c+24841,"VX_cache genblk5[3] bank snp_req_tag", false,-1, 27,0); + vcdp->declBit(c+10217,"VX_cache genblk5[3] bank snp_req_ready", false,-1); + vcdp->declBit(c+1905,"VX_cache genblk5[3] bank snp_rsp_valid", false,-1); + vcdp->declBus(c+1913,"VX_cache genblk5[3] bank snp_rsp_tag", false,-1, 27,0); + vcdp->declBit(c+153,"VX_cache genblk5[3] bank snp_rsp_ready", false,-1); + vcdp->declBit(c+8137,"VX_cache genblk5[3] bank snrq_pop", false,-1); + vcdp->declBit(c+21017,"VX_cache genblk5[3] bank snrq_empty", false,-1); + vcdp->declBit(c+21025,"VX_cache genblk5[3] bank snrq_full", false,-1); + vcdp->declBus(c+8145,"VX_cache genblk5[3] bank snrq_addr_st0", false,-1, 25,0); + vcdp->declBit(c+8153,"VX_cache genblk5[3] bank snrq_invalidate_st0", false,-1); + vcdp->declBus(c+8161,"VX_cache genblk5[3] bank snrq_tag_st0", false,-1, 27,0); + vcdp->declBit(c+8169,"VX_cache genblk5[3] bank dfpq_pop", false,-1); + vcdp->declBit(c+21033,"VX_cache genblk5[3] bank dfpq_empty", false,-1); + vcdp->declBit(c+21041,"VX_cache genblk5[3] bank dfpq_full", false,-1); + vcdp->declBus(c+8177,"VX_cache genblk5[3] bank dfpq_addr_st0", false,-1, 25,0); + vcdp->declArray(c+8185,"VX_cache genblk5[3] bank dfpq_filldata_st0", false,-1, 127,0); + vcdp->declBit(c+8217,"VX_cache genblk5[3] bank reqq_pop", false,-1); + vcdp->declBit(c+1057,"VX_cache genblk5[3] bank reqq_push", false,-1); + vcdp->declBit(c+8225,"VX_cache genblk5[3] bank reqq_empty", false,-1); + vcdp->declBit(c+21049,"VX_cache genblk5[3] bank reqq_full", false,-1); + vcdp->declBit(c+8233,"VX_cache genblk5[3] bank reqq_req_st0", false,-1); + vcdp->declBus(c+8241,"VX_cache genblk5[3] bank reqq_req_tid_st0", false,-1, 1,0); + vcdp->declBit(c+8249,"VX_cache genblk5[3] bank reqq_req_rw_st0", false,-1); + vcdp->declBus(c+8257,"VX_cache genblk5[3] bank reqq_req_byteen_st0", false,-1, 3,0); + vcdp->declBus(c+8265,"VX_cache genblk5[3] bank reqq_req_addr_st0", false,-1, 29,0); + vcdp->declBus(c+8273,"VX_cache genblk5[3] bank reqq_req_writeword_st0", false,-1, 31,0); + vcdp->declQuad(c+21057,"VX_cache genblk5[3] bank reqq_req_tag_st0", false,-1, 41,0); + vcdp->declBit(c+8281,"VX_cache genblk5[3] bank mrvq_pop", false,-1); + vcdp->declBit(c+21073,"VX_cache genblk5[3] bank mrvq_full", false,-1); + vcdp->declBit(c+21081,"VX_cache genblk5[3] bank mrvq_stop", false,-1); + vcdp->declBit(c+8289,"VX_cache genblk5[3] bank mrvq_valid_st0", false,-1); + vcdp->declBus(c+21089,"VX_cache genblk5[3] bank mrvq_tid_st0", false,-1, 1,0); + vcdp->declBus(c+21097,"VX_cache genblk5[3] bank mrvq_addr_st0", false,-1, 25,0); + vcdp->declBus(c+21105,"VX_cache genblk5[3] bank mrvq_wsel_st0", false,-1, 1,0); + vcdp->declBus(c+21113,"VX_cache genblk5[3] bank mrvq_writeword_st0", false,-1, 31,0); + vcdp->declQuad(c+21121,"VX_cache genblk5[3] bank mrvq_tag_st0", false,-1, 41,0); + vcdp->declBit(c+8297,"VX_cache genblk5[3] bank mrvq_rw_st0", false,-1); + vcdp->declBus(c+21137,"VX_cache genblk5[3] bank mrvq_byteen_st0", false,-1, 3,0); + vcdp->declBit(c+21145,"VX_cache genblk5[3] bank mrvq_is_snp_st0", false,-1); + vcdp->declBit(c+21153,"VX_cache genblk5[3] bank mrvq_snp_invalidate_st0", false,-1); + vcdp->declBit(c+8305,"VX_cache genblk5[3] bank mrvq_pending_hazard_st1e", false,-1); + vcdp->declBit(c+8313,"VX_cache genblk5[3] bank st2_pending_hazard_st1e", false,-1); + vcdp->declBit(c+8321,"VX_cache genblk5[3] bank force_request_miss_st1e", false,-1); + vcdp->declBus(c+21161,"VX_cache genblk5[3] bank miss_add_tid", false,-1, 1,0); + vcdp->declQuad(c+21169,"VX_cache genblk5[3] bank miss_add_tag", false,-1, 41,0); + vcdp->declBit(c+21185,"VX_cache genblk5[3] bank miss_add_rw", false,-1); + vcdp->declBus(c+21193,"VX_cache genblk5[3] bank miss_add_byteen", false,-1, 3,0); + vcdp->declBus(c+10209,"VX_cache genblk5[3] bank addr_st2", false,-1, 25,0); + vcdp->declBit(c+21201,"VX_cache genblk5[3] bank is_fill_st2", false,-1); + vcdp->declBit(c+8329,"VX_cache genblk5[3] bank recover_mrvq_state_st2", false,-1); + vcdp->declBit(c+8337,"VX_cache genblk5[3] bank mrvq_push_stall", false,-1); + vcdp->declBit(c+8345,"VX_cache genblk5[3] bank cwbq_push_stall", false,-1); + vcdp->declBit(c+8353,"VX_cache genblk5[3] bank dwbq_push_stall", false,-1); + vcdp->declBit(c+8361,"VX_cache genblk5[3] bank dram_fill_req_stall", false,-1); + vcdp->declBit(c+8369,"VX_cache genblk5[3] bank stall_bank_pipe", false,-1); + vcdp->declBit(c+8377,"VX_cache genblk5[3] bank is_fill_in_pipe", false,-1); + {int i; for (i=0; i<1; i++) { + vcdp->declBit(c+8385+i*1,"VX_cache genblk5[3] bank is_fill_st1", true,(i+0));}} + {int i; for (i=0; i<1; i++) { + vcdp->declBit(c+8393+i*1,"VX_cache genblk5[3] bank going_to_write_st1", true,(i+0));}} + vcdp->declBus(c+25161,"VX_cache genblk5[3] bank j", false,-1, 31,0); + vcdp->declBit(c+8289,"VX_cache genblk5[3] bank mrvq_pop_unqual", false,-1); + vcdp->declBit(c+8401,"VX_cache genblk5[3] bank dfpq_pop_unqual", false,-1); + vcdp->declBit(c+8409,"VX_cache genblk5[3] bank reqq_pop_unqual", false,-1); + vcdp->declBit(c+8417,"VX_cache genblk5[3] bank snrq_pop_unqual", false,-1); + vcdp->declBit(c+8401,"VX_cache genblk5[3] bank qual_is_fill_st0", false,-1); + vcdp->declBit(c+8425,"VX_cache genblk5[3] bank qual_valid_st0", false,-1); + vcdp->declBus(c+8433,"VX_cache genblk5[3] bank qual_addr_st0", false,-1, 25,0); + vcdp->declBus(c+8441,"VX_cache genblk5[3] bank qual_wsel_st0", false,-1, 1,0); + vcdp->declBit(c+8289,"VX_cache genblk5[3] bank qual_is_mrvq_st0", false,-1); + vcdp->declBus(c+8449,"VX_cache genblk5[3] bank qual_writeword_st0", false,-1, 31,0); + vcdp->declArray(c+8457,"VX_cache genblk5[3] bank qual_writedata_st0", false,-1, 127,0); + vcdp->declQuad(c+8489,"VX_cache genblk5[3] bank qual_inst_meta_st0", false,-1, 48,0); + vcdp->declBit(c+8505,"VX_cache genblk5[3] bank qual_going_to_write_st0", false,-1); + vcdp->declBit(c+8513,"VX_cache genblk5[3] bank qual_is_snp_st0", false,-1); + vcdp->declBit(c+8521,"VX_cache genblk5[3] bank qual_snp_invalidate_st0", false,-1); + {int i; for (i=0; i<1; i++) { + vcdp->declBit(c+8529+i*1,"VX_cache genblk5[3] bank valid_st1", true,(i+0));}} + {int i; for (i=0; i<1; i++) { + vcdp->declBus(c+8537+i*1,"VX_cache genblk5[3] bank addr_st1", true,(i+0), 25,0);}} + {int i; for (i=0; i<1; i++) { + vcdp->declBus(c+8545+i*1,"VX_cache genblk5[3] bank wsel_st1", true,(i+0), 1,0);}} + {int i; for (i=0; i<1; i++) { + vcdp->declBus(c+8553+i*1,"VX_cache genblk5[3] bank writeword_st1", true,(i+0), 31,0);}} + {int i; for (i=0; i<1; i++) { + vcdp->declQuad(c+8561+i*2,"VX_cache genblk5[3] bank inst_meta_st1", true,(i+0), 48,0);}} + {int i; for (i=0; i<1; i++) { + vcdp->declArray(c+8577+i*4,"VX_cache genblk5[3] bank writedata_st1", true,(i+0), 127,0);}} + {int i; for (i=0; i<1; i++) { + vcdp->declBit(c+8609+i*1,"VX_cache genblk5[3] bank is_snp_st1", true,(i+0));}} + {int i; for (i=0; i<1; i++) { + vcdp->declBit(c+8617+i*1,"VX_cache genblk5[3] bank snp_invalidate_st1", true,(i+0));}} + {int i; for (i=0; i<1; i++) { + vcdp->declBit(c+8625+i*1,"VX_cache genblk5[3] bank is_mrvq_st1", true,(i+0));}} + vcdp->declBus(c+8633,"VX_cache genblk5[3] bank readword_st1e", false,-1, 31,0); + vcdp->declArray(c+8641,"VX_cache genblk5[3] bank readdata_st1e", false,-1, 127,0); + vcdp->declBus(c+8673,"VX_cache genblk5[3] bank readtag_st1e", false,-1, 19,0); + vcdp->declBit(c+8681,"VX_cache genblk5[3] bank miss_st1e", false,-1); + vcdp->declBit(c+8689,"VX_cache genblk5[3] bank dirty_st1e", false,-1); + vcdp->declBus(c+8697,"VX_cache genblk5[3] bank dirtyb_st1e", false,-1, 15,0); + vcdp->declQuad(c+8705,"VX_cache genblk5[3] bank tag_st1e", false,-1, 41,0); + vcdp->declBus(c+8721,"VX_cache genblk5[3] bank tid_st1e", false,-1, 1,0); + vcdp->declBit(c+8729,"VX_cache genblk5[3] bank mem_rw_st1e", false,-1); + vcdp->declBus(c+8737,"VX_cache genblk5[3] bank mem_byteen_st1e", false,-1, 3,0); + vcdp->declBit(c+8745,"VX_cache genblk5[3] bank fill_saw_dirty_st1e", false,-1); + vcdp->declBit(c+8753,"VX_cache genblk5[3] bank is_snp_st1e", false,-1); + vcdp->declBit(c+8761,"VX_cache genblk5[3] bank snp_invalidate_st1e", false,-1); + vcdp->declBit(c+8769,"VX_cache genblk5[3] bank snp_to_mrvq_st1e", false,-1); + vcdp->declBit(c+8777,"VX_cache genblk5[3] bank mrvq_init_ready_state_st1e", false,-1); + vcdp->declBit(c+8785,"VX_cache genblk5[3] bank miss_add_because_miss", false,-1); + vcdp->declBit(c+8793,"VX_cache genblk5[3] bank valid_st1e", false,-1); + vcdp->declBit(c+8801,"VX_cache genblk5[3] bank is_mrvq_st1e", false,-1); + vcdp->declBit(c+8809,"VX_cache genblk5[3] bank mrvq_recover_ready_state_st1e", false,-1); + vcdp->declBus(c+8817,"VX_cache genblk5[3] bank addr_st1e", false,-1, 25,0); + vcdp->declBit(c+8825,"VX_cache genblk5[3] bank qual_valid_st1e_2", false,-1); + vcdp->declBit(c+8801,"VX_cache genblk5[3] bank is_mrvq_st1e_st2", false,-1); + vcdp->declBit(c+21209,"VX_cache genblk5[3] bank valid_st2", false,-1); + vcdp->declBus(c+21217,"VX_cache genblk5[3] bank wsel_st2", false,-1, 1,0); + vcdp->declBus(c+21225,"VX_cache genblk5[3] bank writeword_st2", false,-1, 31,0); + vcdp->declBus(c+21233,"VX_cache genblk5[3] bank readword_st2", false,-1, 31,0); + vcdp->declArray(c+21241,"VX_cache genblk5[3] bank readdata_st2", false,-1, 127,0); + vcdp->declBit(c+21273,"VX_cache genblk5[3] bank miss_st2", false,-1); + vcdp->declBit(c+21281,"VX_cache genblk5[3] bank dirty_st2", false,-1); + vcdp->declBus(c+21289,"VX_cache genblk5[3] bank dirtyb_st2", false,-1, 15,0); + vcdp->declQuad(c+21297,"VX_cache genblk5[3] bank inst_meta_st2", false,-1, 48,0); + vcdp->declBus(c+21313,"VX_cache genblk5[3] bank readtag_st2", false,-1, 19,0); + vcdp->declBit(c+21321,"VX_cache genblk5[3] bank fill_saw_dirty_st2", false,-1); + vcdp->declBit(c+21329,"VX_cache genblk5[3] bank is_snp_st2", false,-1); + vcdp->declBit(c+21337,"VX_cache genblk5[3] bank snp_invalidate_st2", false,-1); + vcdp->declBit(c+21345,"VX_cache genblk5[3] bank snp_to_mrvq_st2", false,-1); + vcdp->declBit(c+21353,"VX_cache genblk5[3] bank is_mrvq_st2", false,-1); + vcdp->declBit(c+8833,"VX_cache genblk5[3] bank mrvq_init_ready_state_st2", false,-1); + vcdp->declBit(c+21361,"VX_cache genblk5[3] bank mrvq_recover_ready_state_st2", false,-1); + vcdp->declBit(c+21369,"VX_cache genblk5[3] bank mrvq_init_ready_state_unqual_st2", false,-1); + vcdp->declBit(c+8841,"VX_cache genblk5[3] bank mrvq_init_ready_state_hazard_st0_st1", false,-1); + vcdp->declBit(c+8849,"VX_cache genblk5[3] bank mrvq_init_ready_state_hazard_st1e_st1", false,-1); + vcdp->declBit(c+21345,"VX_cache genblk5[3] bank miss_add_because_pending", false,-1); + vcdp->declBit(c+8857,"VX_cache genblk5[3] bank miss_add_unqual", false,-1); + vcdp->declBit(c+8865,"VX_cache genblk5[3] bank miss_add", false,-1); + vcdp->declBus(c+10209,"VX_cache genblk5[3] bank miss_add_addr", false,-1, 25,0); + vcdp->declBus(c+21217,"VX_cache genblk5[3] bank miss_add_wsel", false,-1, 1,0); + vcdp->declBus(c+21225,"VX_cache genblk5[3] bank miss_add_data", false,-1, 31,0); + vcdp->declBit(c+21329,"VX_cache genblk5[3] bank miss_add_is_snp", false,-1); + vcdp->declBit(c+21337,"VX_cache genblk5[3] bank miss_add_snp_invalidate", false,-1); + vcdp->declBit(c+8873,"VX_cache genblk5[3] bank miss_add_is_mrvq", false,-1); + vcdp->declBit(c+8881,"VX_cache genblk5[3] bank cwbq_push", false,-1); + vcdp->declBit(c+1065,"VX_cache genblk5[3] bank cwbq_pop", false,-1); + vcdp->declBit(c+21377,"VX_cache genblk5[3] bank cwbq_empty", false,-1); + vcdp->declBit(c+21385,"VX_cache genblk5[3] bank cwbq_full", false,-1); + vcdp->declBit(c+8889,"VX_cache genblk5[3] bank cwbq_push_unqual", false,-1); + vcdp->declBus(c+21233,"VX_cache genblk5[3] bank cwbq_data", false,-1, 31,0); + vcdp->declBus(c+21161,"VX_cache genblk5[3] bank cwbq_tid", false,-1, 1,0); + vcdp->declQuad(c+21169,"VX_cache genblk5[3] bank cwbq_tag", false,-1, 41,0); + vcdp->declBit(c+8857,"VX_cache genblk5[3] bank dram_fill_req_fast", false,-1); + vcdp->declBit(c+8897,"VX_cache genblk5[3] bank dram_fill_req_unqual", false,-1); + vcdp->declBit(c+8905,"VX_cache genblk5[3] bank dwbq_push", false,-1); + vcdp->declBit(c+1073,"VX_cache genblk5[3] bank dwbq_pop", false,-1); + vcdp->declBit(c+21393,"VX_cache genblk5[3] bank dwbq_empty", false,-1); + vcdp->declBit(c+21401,"VX_cache genblk5[3] bank dwbq_full", false,-1); + vcdp->declBit(c+8913,"VX_cache genblk5[3] bank dwbq_is_dwb_in", false,-1); + vcdp->declBit(c+8921,"VX_cache genblk5[3] bank dwbq_is_snp_in", false,-1); + vcdp->declBit(c+8929,"VX_cache genblk5[3] bank dwbq_is_dwb_out", false,-1); + vcdp->declBit(c+8937,"VX_cache genblk5[3] bank dwbq_is_snp_out", false,-1); + vcdp->declBit(c+8945,"VX_cache genblk5[3] bank dwbq_push_unqual", false,-1); + vcdp->declBus(c+21409,"VX_cache genblk5[3] bank dwbq_req_addr", false,-1, 25,0); + vcdp->declBus(c+21417,"VX_cache genblk5[3] bank snrq_tag_st2", false,-1, 27,0); + vcdp->declBit(c+761,"VX_cache genblk5[3] bank dram_wb_req_fire", false,-1); + vcdp->declBit(c+769,"VX_cache genblk5[3] bank snp_rsp_fire", false,-1); + vcdp->declBit(c+21425,"VX_cache genblk5[3] bank dwbq_dual_valid_sel", false,-1); + vcdp->declBus(c+25169,"VX_cache genblk5[3] bank snp_req_queue DATAW", false,-1, 31,0); + vcdp->declBus(c+25073,"VX_cache genblk5[3] bank snp_req_queue SIZE", false,-1, 31,0); + vcdp->declBus(c+25089,"VX_cache genblk5[3] bank snp_req_queue BUFFERED_OUTPUT", false,-1, 31,0); + vcdp->declBit(c+24489,"VX_cache genblk5[3] bank snp_req_queue clk", false,-1); + vcdp->declBit(c+24497,"VX_cache genblk5[3] bank snp_req_queue reset", false,-1); + vcdp->declBit(c+25033,"VX_cache genblk5[3] bank snp_req_queue push", false,-1); + vcdp->declBit(c+8137,"VX_cache genblk5[3] bank snp_req_queue pop", false,-1); + vcdp->declQuad(c+777,"VX_cache genblk5[3] bank snp_req_queue data_in", false,-1, 54,0); + vcdp->declQuad(c+8953,"VX_cache genblk5[3] bank snp_req_queue data_out", false,-1, 54,0); + vcdp->declBit(c+21017,"VX_cache genblk5[3] bank snp_req_queue empty", false,-1); + vcdp->declBit(c+21025,"VX_cache genblk5[3] bank snp_req_queue full", false,-1); + vcdp->declBus(c+21433,"VX_cache genblk5[3] bank snp_req_queue size", false,-1, 4,0); + vcdp->declBus(c+21433,"VX_cache genblk5[3] bank snp_req_queue size_r", false,-1, 4,0); + vcdp->declBit(c+8969,"VX_cache genblk5[3] bank snp_req_queue reading", false,-1); + vcdp->declBit(c+793,"VX_cache genblk5[3] bank snp_req_queue writing", false,-1); + {int i; for (i=0; i<16; i++) { + vcdp->declQuad(c+21441+i*2,"VX_cache genblk5[3] bank snp_req_queue genblk3 data", true,(i+0), 54,0);}} + vcdp->declQuad(c+21697,"VX_cache genblk5[3] bank snp_req_queue genblk3 genblk2 head_r", false,-1, 54,0); + vcdp->declQuad(c+21713,"VX_cache genblk5[3] bank snp_req_queue genblk3 genblk2 curr_r", false,-1, 54,0); + vcdp->declBus(c+21729,"VX_cache genblk5[3] bank snp_req_queue genblk3 genblk2 wr_ptr_r", false,-1, 3,0); + vcdp->declBus(c+21737,"VX_cache genblk5[3] bank snp_req_queue genblk3 genblk2 rd_ptr_r", false,-1, 3,0); + vcdp->declBus(c+21745,"VX_cache genblk5[3] bank snp_req_queue genblk3 genblk2 rd_ptr_next_r", false,-1, 3,0); + vcdp->declBit(c+21017,"VX_cache genblk5[3] bank snp_req_queue genblk3 genblk2 empty_r", false,-1); + vcdp->declBit(c+21025,"VX_cache genblk5[3] bank snp_req_queue genblk3 genblk2 full_r", false,-1); + vcdp->declBit(c+21753,"VX_cache genblk5[3] bank snp_req_queue genblk3 genblk2 bypass_r", false,-1); + vcdp->declBus(c+25177,"VX_cache genblk5[3] bank dfp_queue DATAW", false,-1, 31,0); + vcdp->declBus(c+25073,"VX_cache genblk5[3] bank dfp_queue SIZE", false,-1, 31,0); + vcdp->declBus(c+25089,"VX_cache genblk5[3] bank dfp_queue BUFFERED_OUTPUT", false,-1, 31,0); + vcdp->declBit(c+24489,"VX_cache genblk5[3] bank dfp_queue clk", false,-1); + vcdp->declBit(c+24497,"VX_cache genblk5[3] bank dfp_queue reset", false,-1); + vcdp->declBit(c+25025,"VX_cache genblk5[3] bank dfp_queue push", false,-1); + vcdp->declBit(c+8169,"VX_cache genblk5[3] bank dfp_queue pop", false,-1); + vcdp->declArray(c+801,"VX_cache genblk5[3] bank dfp_queue data_in", false,-1, 153,0); + vcdp->declArray(c+8977,"VX_cache genblk5[3] bank dfp_queue data_out", false,-1, 153,0); + vcdp->declBit(c+21033,"VX_cache genblk5[3] bank dfp_queue empty", false,-1); + vcdp->declBit(c+21041,"VX_cache genblk5[3] bank dfp_queue full", false,-1); + vcdp->declBus(c+21761,"VX_cache genblk5[3] bank dfp_queue size", false,-1, 4,0); + vcdp->declBus(c+21761,"VX_cache genblk5[3] bank dfp_queue size_r", false,-1, 4,0); + vcdp->declBit(c+9017,"VX_cache genblk5[3] bank dfp_queue reading", false,-1); + vcdp->declBit(c+841,"VX_cache genblk5[3] bank dfp_queue writing", false,-1); + {int i; for (i=0; i<16; i++) { + vcdp->declArray(c+21769+i*5,"VX_cache genblk5[3] bank dfp_queue genblk3 data", true,(i+0), 153,0);}} + vcdp->declArray(c+22409,"VX_cache genblk5[3] bank dfp_queue genblk3 genblk2 head_r", false,-1, 153,0); + vcdp->declArray(c+22449,"VX_cache genblk5[3] bank dfp_queue genblk3 genblk2 curr_r", false,-1, 153,0); + vcdp->declBus(c+22489,"VX_cache genblk5[3] bank dfp_queue genblk3 genblk2 wr_ptr_r", false,-1, 3,0); + vcdp->declBus(c+22497,"VX_cache genblk5[3] bank dfp_queue genblk3 genblk2 rd_ptr_r", false,-1, 3,0); + vcdp->declBus(c+22505,"VX_cache genblk5[3] bank dfp_queue genblk3 genblk2 rd_ptr_next_r", false,-1, 3,0); + vcdp->declBit(c+21033,"VX_cache genblk5[3] bank dfp_queue genblk3 genblk2 empty_r", false,-1); + vcdp->declBit(c+21041,"VX_cache genblk5[3] bank dfp_queue genblk3 genblk2 full_r", false,-1); + vcdp->declBit(c+22513,"VX_cache genblk5[3] bank dfp_queue genblk3 genblk2 bypass_r", false,-1); + vcdp->declBus(c+25081,"VX_cache genblk5[3] bank core_req_arb WORD_SIZE", false,-1, 31,0); + vcdp->declBus(c+25081,"VX_cache genblk5[3] bank core_req_arb NUM_REQUESTS", false,-1, 31,0); + vcdp->declBus(c+25081,"VX_cache genblk5[3] bank core_req_arb CREQ_SIZE", false,-1, 31,0); + vcdp->declBus(c+25097,"VX_cache genblk5[3] bank core_req_arb CORE_TAG_WIDTH", false,-1, 31,0); + vcdp->declBus(c+25105,"VX_cache genblk5[3] bank core_req_arb CORE_TAG_ID_BITS", false,-1, 31,0); + vcdp->declBit(c+24489,"VX_cache genblk5[3] bank core_req_arb clk", false,-1); + vcdp->declBit(c+24497,"VX_cache genblk5[3] bank core_req_arb reset", false,-1); + vcdp->declBit(c+1057,"VX_cache genblk5[3] bank core_req_arb reqq_push", false,-1); + vcdp->declBus(c+129,"VX_cache genblk5[3] bank core_req_arb bank_valids", false,-1, 3,0); + vcdp->declBus(c+24513,"VX_cache genblk5[3] bank core_req_arb bank_rw", false,-1, 3,0); + vcdp->declBus(c+24521,"VX_cache genblk5[3] bank core_req_arb bank_byteen", false,-1, 15,0); + vcdp->declArray(c+24561,"VX_cache genblk5[3] bank core_req_arb bank_writedata", false,-1, 127,0); + vcdp->declArray(c+24529,"VX_cache genblk5[3] bank core_req_arb bank_addr", false,-1, 119,0); + vcdp->declQuad(c+24593,"VX_cache genblk5[3] bank core_req_arb bank_tag", false,-1, 41,0); + vcdp->declBit(c+8217,"VX_cache genblk5[3] bank core_req_arb reqq_pop", false,-1); + vcdp->declBit(c+8233,"VX_cache genblk5[3] bank core_req_arb reqq_req_st0", false,-1); + vcdp->declBus(c+8241,"VX_cache genblk5[3] bank core_req_arb reqq_req_tid_st0", false,-1, 1,0); + vcdp->declBit(c+8249,"VX_cache genblk5[3] bank core_req_arb reqq_req_rw_st0", false,-1); + vcdp->declBus(c+8257,"VX_cache genblk5[3] bank core_req_arb reqq_req_byteen_st0", false,-1, 3,0); + vcdp->declBus(c+8265,"VX_cache genblk5[3] bank core_req_arb reqq_req_addr_st0", false,-1, 29,0); + vcdp->declBus(c+8273,"VX_cache genblk5[3] bank core_req_arb reqq_req_writedata_st0", false,-1, 31,0); + vcdp->declQuad(c+21057,"VX_cache genblk5[3] bank core_req_arb reqq_req_tag_st0", false,-1, 41,0); + vcdp->declBit(c+8225,"VX_cache genblk5[3] bank core_req_arb reqq_empty", false,-1); + vcdp->declBit(c+21049,"VX_cache genblk5[3] bank core_req_arb reqq_full", false,-1); + vcdp->declBus(c+9025,"VX_cache genblk5[3] bank core_req_arb out_per_valids", false,-1, 3,0); + vcdp->declBus(c+9033,"VX_cache genblk5[3] bank core_req_arb out_per_rw", false,-1, 3,0); + vcdp->declBus(c+9041,"VX_cache genblk5[3] bank core_req_arb out_per_byteen", false,-1, 15,0); + vcdp->declArray(c+9049,"VX_cache genblk5[3] bank core_req_arb out_per_addr", false,-1, 119,0); + vcdp->declArray(c+9081,"VX_cache genblk5[3] bank core_req_arb out_per_writedata", false,-1, 127,0); + vcdp->declQuad(c+9113,"VX_cache genblk5[3] bank core_req_arb out_per_tag", false,-1, 41,0); + vcdp->declBus(c+22521,"VX_cache genblk5[3] bank core_req_arb use_per_valids", false,-1, 3,0); + vcdp->declBus(c+22529,"VX_cache genblk5[3] bank core_req_arb use_per_rw", false,-1, 3,0); + vcdp->declBus(c+22537,"VX_cache genblk5[3] bank core_req_arb use_per_byteen", false,-1, 15,0); + vcdp->declArray(c+22545,"VX_cache genblk5[3] bank core_req_arb use_per_addr", false,-1, 119,0); + vcdp->declArray(c+22577,"VX_cache genblk5[3] bank core_req_arb use_per_writedata", false,-1, 127,0); + vcdp->declQuad(c+21057,"VX_cache genblk5[3] bank core_req_arb use_per_tag", false,-1, 41,0); + vcdp->declBus(c+22521,"VX_cache genblk5[3] bank core_req_arb qual_valids", false,-1, 3,0); + vcdp->declBus(c+22529,"VX_cache genblk5[3] bank core_req_arb qual_rw", false,-1, 3,0); + vcdp->declBus(c+22537,"VX_cache genblk5[3] bank core_req_arb qual_byteen", false,-1, 15,0); + vcdp->declArray(c+22545,"VX_cache genblk5[3] bank core_req_arb qual_addr", false,-1, 119,0); + vcdp->declArray(c+22577,"VX_cache genblk5[3] bank core_req_arb qual_writedata", false,-1, 127,0); + vcdp->declQuad(c+21057,"VX_cache genblk5[3] bank core_req_arb qual_tag", false,-1, 41,0); + vcdp->declBit(c+22609,"VX_cache genblk5[3] bank core_req_arb o_empty", false,-1); + vcdp->declBit(c+22617,"VX_cache genblk5[3] bank core_req_arb use_empty", false,-1); + vcdp->declBit(c+9129,"VX_cache genblk5[3] bank core_req_arb out_empty", false,-1); + vcdp->declBit(c+1081,"VX_cache genblk5[3] bank core_req_arb push_qual", false,-1); + vcdp->declBit(c+9137,"VX_cache genblk5[3] bank core_req_arb pop_qual", false,-1); + vcdp->declBus(c+9145,"VX_cache genblk5[3] bank core_req_arb real_out_per_valids", false,-1, 3,0); + vcdp->declBus(c+8241,"VX_cache genblk5[3] bank core_req_arb qual_request_index", false,-1, 1,0); + vcdp->declBit(c+8233,"VX_cache genblk5[3] bank core_req_arb qual_has_request", false,-1); + vcdp->declBus(c+25185,"VX_cache genblk5[3] bank core_req_arb reqq_queue DATAW", false,-1, 31,0); + vcdp->declBus(c+25081,"VX_cache genblk5[3] bank core_req_arb reqq_queue SIZE", false,-1, 31,0); + vcdp->declBus(c+25089,"VX_cache genblk5[3] bank core_req_arb reqq_queue BUFFERED_OUTPUT", false,-1, 31,0); + vcdp->declBit(c+24489,"VX_cache genblk5[3] bank core_req_arb reqq_queue clk", false,-1); + vcdp->declBit(c+24497,"VX_cache genblk5[3] bank core_req_arb reqq_queue reset", false,-1); + vcdp->declBit(c+1081,"VX_cache genblk5[3] bank core_req_arb reqq_queue push", false,-1); + vcdp->declBit(c+9137,"VX_cache genblk5[3] bank core_req_arb reqq_queue pop", false,-1); + vcdp->declArray(c+849,"VX_cache genblk5[3] bank core_req_arb reqq_queue data_in", false,-1, 313,0); + vcdp->declArray(c+9153,"VX_cache genblk5[3] bank core_req_arb reqq_queue data_out", false,-1, 313,0); + vcdp->declBit(c+22609,"VX_cache genblk5[3] bank core_req_arb reqq_queue empty", false,-1); + vcdp->declBit(c+21049,"VX_cache genblk5[3] bank core_req_arb reqq_queue full", false,-1); + vcdp->declBus(c+22625,"VX_cache genblk5[3] bank core_req_arb reqq_queue size", false,-1, 2,0); + vcdp->declBus(c+22625,"VX_cache genblk5[3] bank core_req_arb reqq_queue size_r", false,-1, 2,0); + vcdp->declBit(c+9233,"VX_cache genblk5[3] bank core_req_arb reqq_queue reading", false,-1); + vcdp->declBit(c+929,"VX_cache genblk5[3] bank core_req_arb reqq_queue writing", false,-1); + {int i; for (i=0; i<4; i++) { + vcdp->declArray(c+22633+i*10,"VX_cache genblk5[3] bank core_req_arb reqq_queue genblk3 data", true,(i+0), 313,0);}} + vcdp->declArray(c+22953,"VX_cache genblk5[3] bank core_req_arb reqq_queue genblk3 genblk2 head_r", false,-1, 313,0); + vcdp->declArray(c+23033,"VX_cache genblk5[3] bank core_req_arb reqq_queue genblk3 genblk2 curr_r", false,-1, 313,0); + vcdp->declBus(c+23113,"VX_cache genblk5[3] bank core_req_arb reqq_queue genblk3 genblk2 wr_ptr_r", false,-1, 1,0); + vcdp->declBus(c+23121,"VX_cache genblk5[3] bank core_req_arb reqq_queue genblk3 genblk2 rd_ptr_r", false,-1, 1,0); + vcdp->declBus(c+23129,"VX_cache genblk5[3] bank core_req_arb reqq_queue genblk3 genblk2 rd_ptr_next_r", false,-1, 1,0); + vcdp->declBit(c+22609,"VX_cache genblk5[3] bank core_req_arb reqq_queue genblk3 genblk2 empty_r", false,-1); + vcdp->declBit(c+21049,"VX_cache genblk5[3] bank core_req_arb reqq_queue genblk3 genblk2 full_r", false,-1); + vcdp->declBit(c+23137,"VX_cache genblk5[3] bank core_req_arb reqq_queue genblk3 genblk2 bypass_r", false,-1); + vcdp->declBus(c+25081,"VX_cache genblk5[3] bank core_req_arb sel_bank N", false,-1, 31,0); + vcdp->declBit(c+24489,"VX_cache genblk5[3] bank core_req_arb sel_bank clk", false,-1); + vcdp->declBit(c+24497,"VX_cache genblk5[3] bank core_req_arb sel_bank reset", false,-1); + vcdp->declBus(c+22521,"VX_cache genblk5[3] bank core_req_arb sel_bank requests", false,-1, 3,0); + vcdp->declBus(c+8241,"VX_cache genblk5[3] bank core_req_arb sel_bank grant_index", false,-1, 1,0); + vcdp->declBus(c+9241,"VX_cache genblk5[3] bank core_req_arb sel_bank grant_onehot", false,-1, 3,0); + vcdp->declBit(c+8233,"VX_cache genblk5[3] bank core_req_arb sel_bank grant_valid", false,-1); + vcdp->declBus(c+9241,"VX_cache genblk5[3] bank core_req_arb sel_bank genblk2 grant_onehot_r", false,-1, 3,0); + vcdp->declBus(c+25081,"VX_cache genblk5[3] bank core_req_arb sel_bank genblk2 priority_encoder N", false,-1, 31,0); + vcdp->declBus(c+22521,"VX_cache genblk5[3] bank core_req_arb sel_bank genblk2 priority_encoder data_in", false,-1, 3,0); + vcdp->declBus(c+8241,"VX_cache genblk5[3] bank core_req_arb sel_bank genblk2 priority_encoder data_out", false,-1, 1,0); + vcdp->declBit(c+8233,"VX_cache genblk5[3] bank core_req_arb sel_bank genblk2 priority_encoder valid_out", false,-1); + vcdp->declBus(c+9249,"VX_cache genblk5[3] bank core_req_arb sel_bank genblk2 priority_encoder i", false,-1, 31,0); + vcdp->declBus(c+25193,"VX_cache genblk5[3] bank s0_1_c0 N", false,-1, 31,0); + vcdp->declBus(c+25057,"VX_cache genblk5[3] bank s0_1_c0 PASSTHRU", false,-1, 31,0); + vcdp->declBit(c+24489,"VX_cache genblk5[3] bank s0_1_c0 clk", false,-1); + vcdp->declBit(c+24497,"VX_cache genblk5[3] bank s0_1_c0 reset", false,-1); + vcdp->declBit(c+8369,"VX_cache genblk5[3] bank s0_1_c0 stall", false,-1); + vcdp->declBit(c+25137,"VX_cache genblk5[3] bank s0_1_c0 flush", false,-1); + vcdp->declArray(c+9257,"VX_cache genblk5[3] bank s0_1_c0 in", false,-1, 242,0); + vcdp->declArray(c+23145,"VX_cache genblk5[3] bank s0_1_c0 out", false,-1, 242,0); + vcdp->declArray(c+23145,"VX_cache genblk5[3] bank s0_1_c0 value", false,-1, 242,0); + vcdp->declBus(c+25065,"VX_cache genblk5[3] bank tag_data_access CACHE_SIZE", false,-1, 31,0); + vcdp->declBus(c+25073,"VX_cache genblk5[3] bank tag_data_access BANK_LINE_SIZE", false,-1, 31,0); + vcdp->declBus(c+25081,"VX_cache genblk5[3] bank tag_data_access NUM_BANKS", false,-1, 31,0); + vcdp->declBus(c+25081,"VX_cache genblk5[3] bank tag_data_access WORD_SIZE", false,-1, 31,0); + vcdp->declBus(c+25089,"VX_cache genblk5[3] bank tag_data_access STAGE_1_CYCLES", false,-1, 31,0); + vcdp->declBus(c+25089,"VX_cache genblk5[3] bank tag_data_access WRITE_ENABLE", false,-1, 31,0); + vcdp->declBus(c+25089,"VX_cache genblk5[3] bank tag_data_access DRAM_ENABLE", false,-1, 31,0); + vcdp->declBit(c+24489,"VX_cache genblk5[3] bank tag_data_access clk", false,-1); + vcdp->declBit(c+24497,"VX_cache genblk5[3] bank tag_data_access reset", false,-1); + vcdp->declBit(c+8369,"VX_cache genblk5[3] bank tag_data_access stall", false,-1); + vcdp->declBit(c+8753,"VX_cache genblk5[3] bank tag_data_access is_snp_st1e", false,-1); + vcdp->declBit(c+8761,"VX_cache genblk5[3] bank tag_data_access snp_invalidate_st1e", false,-1); + vcdp->declBit(c+8369,"VX_cache genblk5[3] bank tag_data_access stall_bank_pipe", false,-1); + vcdp->declBit(c+8321,"VX_cache genblk5[3] bank tag_data_access force_request_miss_st1e", false,-1); + vcdp->declBus(c+9321,"VX_cache genblk5[3] bank tag_data_access readaddr_st10", false,-1, 5,0); + vcdp->declBus(c+8817,"VX_cache genblk5[3] bank tag_data_access writeaddr_st1e", false,-1, 25,0); + vcdp->declBit(c+8793,"VX_cache genblk5[3] bank tag_data_access valid_req_st1e", false,-1); + vcdp->declBit(c+9329,"VX_cache genblk5[3] bank tag_data_access writefill_st1e", false,-1); + vcdp->declBus(c+9337,"VX_cache genblk5[3] bank tag_data_access writeword_st1e", false,-1, 31,0); + vcdp->declArray(c+9345,"VX_cache genblk5[3] bank tag_data_access writedata_st1e", false,-1, 127,0); + vcdp->declBit(c+8729,"VX_cache genblk5[3] bank tag_data_access mem_rw_st1e", false,-1); + vcdp->declBus(c+8737,"VX_cache genblk5[3] bank tag_data_access mem_byteen_st1e", false,-1, 3,0); + vcdp->declBus(c+9377,"VX_cache genblk5[3] bank tag_data_access wordsel_st1e", false,-1, 1,0); + vcdp->declBus(c+8633,"VX_cache genblk5[3] bank tag_data_access readword_st1e", false,-1, 31,0); + vcdp->declArray(c+8641,"VX_cache genblk5[3] bank tag_data_access readdata_st1e", false,-1, 127,0); + vcdp->declBus(c+8673,"VX_cache genblk5[3] bank tag_data_access readtag_st1e", false,-1, 19,0); + vcdp->declBit(c+8681,"VX_cache genblk5[3] bank tag_data_access miss_st1e", false,-1); + vcdp->declBit(c+8689,"VX_cache genblk5[3] bank tag_data_access dirty_st1e", false,-1); + vcdp->declBus(c+8697,"VX_cache genblk5[3] bank tag_data_access dirtyb_st1e", false,-1, 15,0); + vcdp->declBit(c+8745,"VX_cache genblk5[3] bank tag_data_access fill_saw_dirty_st1e", false,-1); + vcdp->declBit(c+8769,"VX_cache genblk5[3] bank tag_data_access snp_to_mrvq_st1e", false,-1); + vcdp->declBit(c+8777,"VX_cache genblk5[3] bank tag_data_access mrvq_init_ready_state_st1e", false,-1); + {int i; for (i=0; i<1; i++) { + vcdp->declBit(c+9385+i*1,"VX_cache genblk5[3] bank tag_data_access read_valid_st1c", true,(i+0));}} + {int i; for (i=0; i<1; i++) { + vcdp->declBit(c+9393+i*1,"VX_cache genblk5[3] bank tag_data_access read_dirty_st1c", true,(i+0));}} + {int i; for (i=0; i<1; i++) { + vcdp->declBus(c+9401+i*1,"VX_cache genblk5[3] bank tag_data_access read_dirtyb_st1c", true,(i+0), 15,0);}} + {int i; for (i=0; i<1; i++) { + vcdp->declBus(c+9409+i*1,"VX_cache genblk5[3] bank tag_data_access read_tag_st1c", true,(i+0), 19,0);}} + {int i; for (i=0; i<1; i++) { + vcdp->declArray(c+9417+i*4,"VX_cache genblk5[3] bank tag_data_access read_data_st1c", true,(i+0), 127,0);}} + vcdp->declBit(c+9449,"VX_cache genblk5[3] bank tag_data_access qual_read_valid_st1", false,-1); + vcdp->declBit(c+9457,"VX_cache genblk5[3] bank tag_data_access qual_read_dirty_st1", false,-1); + vcdp->declBus(c+9465,"VX_cache genblk5[3] bank tag_data_access qual_read_dirtyb_st1", false,-1, 15,0); + vcdp->declBus(c+9473,"VX_cache genblk5[3] bank tag_data_access qual_read_tag_st1", false,-1, 19,0); + vcdp->declArray(c+9481,"VX_cache genblk5[3] bank tag_data_access qual_read_data_st1", false,-1, 127,0); + vcdp->declBit(c+9513,"VX_cache genblk5[3] bank tag_data_access use_read_valid_st1e", false,-1); + vcdp->declBit(c+9521,"VX_cache genblk5[3] bank tag_data_access use_read_dirty_st1e", false,-1); + vcdp->declBus(c+8697,"VX_cache genblk5[3] bank tag_data_access use_read_dirtyb_st1e", false,-1, 15,0); + vcdp->declBus(c+8673,"VX_cache genblk5[3] bank tag_data_access use_read_tag_st1e", false,-1, 19,0); + vcdp->declArray(c+8641,"VX_cache genblk5[3] bank tag_data_access use_read_data_st1e", false,-1, 127,0); + vcdp->declBus(c+9529,"VX_cache genblk5[3] bank tag_data_access use_write_enable", false,-1, 15,0); + vcdp->declArray(c+9537,"VX_cache genblk5[3] bank tag_data_access use_write_data", false,-1, 127,0); + vcdp->declBit(c+8681,"VX_cache genblk5[3] bank tag_data_access fill_sent", false,-1); + vcdp->declBit(c+9569,"VX_cache genblk5[3] bank tag_data_access invalidate_line", false,-1); + vcdp->declBit(c+9577,"VX_cache genblk5[3] bank tag_data_access tags_match", false,-1); + vcdp->declBit(c+9585,"VX_cache genblk5[3] bank tag_data_access real_writefill", false,-1); + vcdp->declBus(c+9593,"VX_cache genblk5[3] bank tag_data_access writetag_st1e", false,-1, 19,0); + vcdp->declBus(c+9321,"VX_cache genblk5[3] bank tag_data_access writeladdr_st1e", false,-1, 5,0); + vcdp->declBus(c+9601,"VX_cache genblk5[3] bank tag_data_access we", false,-1, 15,0); + vcdp->declArray(c+9537,"VX_cache genblk5[3] bank tag_data_access data_write", false,-1, 127,0); + vcdp->declBit(c+9609,"VX_cache genblk5[3] bank tag_data_access should_write", false,-1); + vcdp->declBit(c+9569,"VX_cache genblk5[3] bank tag_data_access snoop_hit_no_pending", false,-1); + vcdp->declBit(c+9617,"VX_cache genblk5[3] bank tag_data_access req_invalid", false,-1); + vcdp->declBit(c+9625,"VX_cache genblk5[3] bank tag_data_access req_miss", false,-1); + vcdp->declBit(c+9633,"VX_cache genblk5[3] bank tag_data_access real_miss", false,-1); + vcdp->declBit(c+9641,"VX_cache genblk5[3] bank tag_data_access force_core_miss", false,-1); + vcdp->declBit(c+9649,"VX_cache genblk5[3] bank tag_data_access genblk4[0] normal_write", false,-1); + vcdp->declBit(c+9657,"VX_cache genblk5[3] bank tag_data_access genblk4[1] normal_write", false,-1); + vcdp->declBit(c+9665,"VX_cache genblk5[3] bank tag_data_access genblk4[2] normal_write", false,-1); + vcdp->declBit(c+9673,"VX_cache genblk5[3] bank tag_data_access genblk4[3] normal_write", false,-1); + vcdp->declBus(c+25065,"VX_cache genblk5[3] bank tag_data_access tag_data_structure CACHE_SIZE", false,-1, 31,0); + vcdp->declBus(c+25073,"VX_cache genblk5[3] bank tag_data_access tag_data_structure BANK_LINE_SIZE", false,-1, 31,0); + vcdp->declBus(c+25081,"VX_cache genblk5[3] bank tag_data_access tag_data_structure NUM_BANKS", false,-1, 31,0); + vcdp->declBus(c+25081,"VX_cache genblk5[3] bank tag_data_access tag_data_structure WORD_SIZE", false,-1, 31,0); + vcdp->declBit(c+24489,"VX_cache genblk5[3] bank tag_data_access tag_data_structure clk", false,-1); + vcdp->declBit(c+24497,"VX_cache genblk5[3] bank tag_data_access tag_data_structure reset", false,-1); + vcdp->declBit(c+8369,"VX_cache genblk5[3] bank tag_data_access tag_data_structure stall_bank_pipe", false,-1); + vcdp->declBus(c+9321,"VX_cache genblk5[3] bank tag_data_access tag_data_structure read_addr", false,-1, 5,0); + vcdp->declBit(c+9449,"VX_cache genblk5[3] bank tag_data_access tag_data_structure read_valid", false,-1); + vcdp->declBit(c+9457,"VX_cache genblk5[3] bank tag_data_access tag_data_structure read_dirty", false,-1); + vcdp->declBus(c+9465,"VX_cache genblk5[3] bank tag_data_access tag_data_structure read_dirtyb", false,-1, 15,0); + vcdp->declBus(c+9473,"VX_cache genblk5[3] bank tag_data_access tag_data_structure read_tag", false,-1, 19,0); + vcdp->declArray(c+9481,"VX_cache genblk5[3] bank tag_data_access tag_data_structure read_data", false,-1, 127,0); + vcdp->declBit(c+9569,"VX_cache genblk5[3] bank tag_data_access tag_data_structure invalidate", false,-1); + vcdp->declBus(c+9529,"VX_cache genblk5[3] bank tag_data_access tag_data_structure write_enable", false,-1, 15,0); + vcdp->declBit(c+9585,"VX_cache genblk5[3] bank tag_data_access tag_data_structure write_fill", false,-1); + vcdp->declBus(c+9321,"VX_cache genblk5[3] bank tag_data_access tag_data_structure write_addr", false,-1, 5,0); + vcdp->declBus(c+9593,"VX_cache genblk5[3] bank tag_data_access tag_data_structure tag_index", false,-1, 19,0); + vcdp->declArray(c+9537,"VX_cache genblk5[3] bank tag_data_access tag_data_structure write_data", false,-1, 127,0); + vcdp->declBit(c+8681,"VX_cache genblk5[3] bank tag_data_access tag_data_structure fill_sent", false,-1); + vcdp->declQuad(c+23209,"VX_cache genblk5[3] bank tag_data_access tag_data_structure dirty", false,-1, 63,0); + vcdp->declQuad(c+23225,"VX_cache genblk5[3] bank tag_data_access tag_data_structure valid", false,-1, 63,0); + vcdp->declBit(c+9681,"VX_cache genblk5[3] bank tag_data_access tag_data_structure do_write", false,-1); + vcdp->declBus(c+23241,"VX_cache genblk5[3] bank tag_data_access tag_data_structure i", false,-1, 31,0); + vcdp->declBus(c+23249,"VX_cache genblk5[3] bank tag_data_access tag_data_structure j", false,-1, 31,0); + vcdp->declBus(c+25201,"VX_cache genblk5[3] bank tag_data_access s0_1_c0 N", false,-1, 31,0); + vcdp->declBus(c+25089,"VX_cache genblk5[3] bank tag_data_access s0_1_c0 PASSTHRU", false,-1, 31,0); + vcdp->declBit(c+24489,"VX_cache genblk5[3] bank tag_data_access s0_1_c0 clk", false,-1); + vcdp->declBit(c+24497,"VX_cache genblk5[3] bank tag_data_access s0_1_c0 reset", false,-1); + vcdp->declBit(c+8369,"VX_cache genblk5[3] bank tag_data_access s0_1_c0 stall", false,-1); + vcdp->declBit(c+25137,"VX_cache genblk5[3] bank tag_data_access s0_1_c0 flush", false,-1); + vcdp->declArray(c+9689,"VX_cache genblk5[3] bank tag_data_access s0_1_c0 in", false,-1, 165,0); + vcdp->declArray(c+9689,"VX_cache genblk5[3] bank tag_data_access s0_1_c0 out", false,-1, 165,0); + vcdp->declArray(c+23257,"VX_cache genblk5[3] bank tag_data_access s0_1_c0 value", false,-1, 165,0); + vcdp->declBus(c+25209,"VX_cache genblk5[3] bank st_1e_2 N", false,-1, 31,0); + vcdp->declBus(c+25057,"VX_cache genblk5[3] bank st_1e_2 PASSTHRU", false,-1, 31,0); + vcdp->declBit(c+24489,"VX_cache genblk5[3] bank st_1e_2 clk", false,-1); + vcdp->declBit(c+24497,"VX_cache genblk5[3] bank st_1e_2 reset", false,-1); + vcdp->declBit(c+8369,"VX_cache genblk5[3] bank st_1e_2 stall", false,-1); + vcdp->declBit(c+25137,"VX_cache genblk5[3] bank st_1e_2 flush", false,-1); + vcdp->declArray(c+9737,"VX_cache genblk5[3] bank st_1e_2 in", false,-1, 315,0); + vcdp->declArray(c+23305,"VX_cache genblk5[3] bank st_1e_2 out", false,-1, 315,0); + vcdp->declArray(c+23305,"VX_cache genblk5[3] bank st_1e_2 value", false,-1, 315,0); + vcdp->declBus(c+25057,"VX_cache genblk5[3] bank cache_miss_resrv CACHE_ID", false,-1, 31,0); + vcdp->declBus(c+25241,"VX_cache genblk5[3] bank cache_miss_resrv BANK_ID", false,-1, 31,0); + vcdp->declBus(c+25073,"VX_cache genblk5[3] bank cache_miss_resrv BANK_LINE_SIZE", false,-1, 31,0); + vcdp->declBus(c+25081,"VX_cache genblk5[3] bank cache_miss_resrv NUM_BANKS", false,-1, 31,0); + vcdp->declBus(c+25081,"VX_cache genblk5[3] bank cache_miss_resrv WORD_SIZE", false,-1, 31,0); + vcdp->declBus(c+25081,"VX_cache genblk5[3] bank cache_miss_resrv NUM_REQUESTS", false,-1, 31,0); + vcdp->declBus(c+25073,"VX_cache genblk5[3] bank cache_miss_resrv MRVQ_SIZE", false,-1, 31,0); + vcdp->declBus(c+25097,"VX_cache genblk5[3] bank cache_miss_resrv CORE_TAG_WIDTH", false,-1, 31,0); + vcdp->declBus(c+25113,"VX_cache genblk5[3] bank cache_miss_resrv SNP_REQ_TAG_WIDTH", false,-1, 31,0); + vcdp->declBit(c+24489,"VX_cache genblk5[3] bank cache_miss_resrv clk", false,-1); + vcdp->declBit(c+24497,"VX_cache genblk5[3] bank cache_miss_resrv reset", false,-1); + vcdp->declBit(c+8865,"VX_cache genblk5[3] bank cache_miss_resrv miss_add", false,-1); + vcdp->declBit(c+8873,"VX_cache genblk5[3] bank cache_miss_resrv is_mrvq", false,-1); + vcdp->declBus(c+10209,"VX_cache genblk5[3] bank cache_miss_resrv miss_add_addr", false,-1, 25,0); + vcdp->declBus(c+21217,"VX_cache genblk5[3] bank cache_miss_resrv miss_add_wsel", false,-1, 1,0); + vcdp->declBus(c+21225,"VX_cache genblk5[3] bank cache_miss_resrv miss_add_data", false,-1, 31,0); + vcdp->declBus(c+21161,"VX_cache genblk5[3] bank cache_miss_resrv miss_add_tid", false,-1, 1,0); + vcdp->declQuad(c+21169,"VX_cache genblk5[3] bank cache_miss_resrv miss_add_tag", false,-1, 41,0); + vcdp->declBit(c+21185,"VX_cache genblk5[3] bank cache_miss_resrv miss_add_rw", false,-1); + vcdp->declBus(c+21193,"VX_cache genblk5[3] bank cache_miss_resrv miss_add_byteen", false,-1, 3,0); + vcdp->declBit(c+8833,"VX_cache genblk5[3] bank cache_miss_resrv mrvq_init_ready_state", false,-1); + vcdp->declBit(c+21329,"VX_cache genblk5[3] bank cache_miss_resrv miss_add_is_snp", false,-1); + vcdp->declBit(c+21337,"VX_cache genblk5[3] bank cache_miss_resrv miss_add_snp_invalidate", false,-1); + vcdp->declBit(c+21073,"VX_cache genblk5[3] bank cache_miss_resrv miss_resrv_full", false,-1); + vcdp->declBit(c+21081,"VX_cache genblk5[3] bank cache_miss_resrv miss_resrv_stop", false,-1); + vcdp->declBit(c+9329,"VX_cache genblk5[3] bank cache_miss_resrv is_fill_st1", false,-1); + vcdp->declBus(c+8817,"VX_cache genblk5[3] bank cache_miss_resrv fill_addr_st1", false,-1, 25,0); + vcdp->declBit(c+8305,"VX_cache genblk5[3] bank cache_miss_resrv pending_hazard", false,-1); + vcdp->declBit(c+8281,"VX_cache genblk5[3] bank cache_miss_resrv miss_resrv_pop", false,-1); + vcdp->declBit(c+8289,"VX_cache genblk5[3] bank cache_miss_resrv miss_resrv_valid_st0", false,-1); + vcdp->declBus(c+21097,"VX_cache genblk5[3] bank cache_miss_resrv miss_resrv_addr_st0", false,-1, 25,0); + vcdp->declBus(c+21105,"VX_cache genblk5[3] bank cache_miss_resrv miss_resrv_wsel_st0", false,-1, 1,0); + vcdp->declBus(c+21113,"VX_cache genblk5[3] bank cache_miss_resrv miss_resrv_data_st0", false,-1, 31,0); + vcdp->declBus(c+21089,"VX_cache genblk5[3] bank cache_miss_resrv miss_resrv_tid_st0", false,-1, 1,0); + vcdp->declQuad(c+21121,"VX_cache genblk5[3] bank cache_miss_resrv miss_resrv_tag_st0", false,-1, 41,0); + vcdp->declBit(c+8297,"VX_cache genblk5[3] bank cache_miss_resrv miss_resrv_rw_st0", false,-1); + vcdp->declBus(c+21137,"VX_cache genblk5[3] bank cache_miss_resrv miss_resrv_byteen_st0", false,-1, 3,0); + vcdp->declBit(c+21145,"VX_cache genblk5[3] bank cache_miss_resrv miss_resrv_is_snp_st0", false,-1); + vcdp->declBit(c+21153,"VX_cache genblk5[3] bank cache_miss_resrv miss_resrv_snp_invalidate_st0", false,-1); + {int i; for (i=0; i<16; i++) { + vcdp->declArray(c+23385+i*3,"VX_cache genblk5[3] bank cache_miss_resrv metadata_table", true,(i+0), 84,0);}} + vcdp->declArray(c+23769,"VX_cache genblk5[3] bank cache_miss_resrv addr_table", false,-1, 415,0); + vcdp->declBus(c+23873,"VX_cache genblk5[3] bank cache_miss_resrv valid_table", false,-1, 15,0); + vcdp->declBus(c+23881,"VX_cache genblk5[3] bank cache_miss_resrv ready_table", false,-1, 15,0); + vcdp->declBus(c+23889,"VX_cache genblk5[3] bank cache_miss_resrv schedule_ptr", false,-1, 3,0); + vcdp->declBus(c+23897,"VX_cache genblk5[3] bank cache_miss_resrv head_ptr", false,-1, 3,0); + vcdp->declBus(c+23905,"VX_cache genblk5[3] bank cache_miss_resrv tail_ptr", false,-1, 3,0); + vcdp->declBus(c+23913,"VX_cache genblk5[3] bank cache_miss_resrv size", false,-1, 4,0); + vcdp->declBit(c+23921,"VX_cache genblk5[3] bank cache_miss_resrv enqueue_possible", false,-1); + vcdp->declBus(c+23905,"VX_cache genblk5[3] bank cache_miss_resrv enqueue_index", false,-1, 3,0); + vcdp->declBus(c+9817,"VX_cache genblk5[3] bank cache_miss_resrv make_ready", false,-1, 15,0); + vcdp->declBus(c+9825,"VX_cache genblk5[3] bank cache_miss_resrv make_ready_push", false,-1, 15,0); + vcdp->declBus(c+9833,"VX_cache genblk5[3] bank cache_miss_resrv valid_address_match", false,-1, 15,0); + vcdp->declBit(c+8289,"VX_cache genblk5[3] bank cache_miss_resrv dequeue_possible", false,-1); + vcdp->declBus(c+23889,"VX_cache genblk5[3] bank cache_miss_resrv dequeue_index", false,-1, 3,0); + vcdp->declBit(c+9841,"VX_cache genblk5[3] bank cache_miss_resrv mrvq_push", false,-1); + vcdp->declBit(c+9849,"VX_cache genblk5[3] bank cache_miss_resrv mrvq_pop", false,-1); + vcdp->declBit(c+9857,"VX_cache genblk5[3] bank cache_miss_resrv recover_state", false,-1); + vcdp->declBit(c+9865,"VX_cache genblk5[3] bank cache_miss_resrv increment_head", false,-1); + vcdp->declBit(c+9873,"VX_cache genblk5[3] bank cache_miss_resrv update_ready", false,-1); + vcdp->declBit(c+9881,"VX_cache genblk5[3] bank cache_miss_resrv qual_mrvq_init", false,-1); + vcdp->declBus(c+25217,"VX_cache genblk5[3] bank cwb_queue DATAW", false,-1, 31,0); + vcdp->declBus(c+25081,"VX_cache genblk5[3] bank cwb_queue SIZE", false,-1, 31,0); + vcdp->declBus(c+25089,"VX_cache genblk5[3] bank cwb_queue BUFFERED_OUTPUT", false,-1, 31,0); + vcdp->declBit(c+24489,"VX_cache genblk5[3] bank cwb_queue clk", false,-1); + vcdp->declBit(c+24497,"VX_cache genblk5[3] bank cwb_queue reset", false,-1); + vcdp->declBit(c+8881,"VX_cache genblk5[3] bank cwb_queue push", false,-1); + vcdp->declBit(c+1065,"VX_cache genblk5[3] bank cwb_queue pop", false,-1); + vcdp->declArray(c+9889,"VX_cache genblk5[3] bank cwb_queue data_in", false,-1, 75,0); + vcdp->declArray(c+9913,"VX_cache genblk5[3] bank cwb_queue data_out", false,-1, 75,0); + vcdp->declBit(c+21377,"VX_cache genblk5[3] bank cwb_queue empty", false,-1); + vcdp->declBit(c+21385,"VX_cache genblk5[3] bank cwb_queue full", false,-1); + vcdp->declBus(c+23929,"VX_cache genblk5[3] bank cwb_queue size", false,-1, 2,0); + vcdp->declBus(c+23929,"VX_cache genblk5[3] bank cwb_queue size_r", false,-1, 2,0); + vcdp->declBit(c+937,"VX_cache genblk5[3] bank cwb_queue reading", false,-1); + vcdp->declBit(c+9937,"VX_cache genblk5[3] bank cwb_queue writing", false,-1); + {int i; for (i=0; i<4; i++) { + vcdp->declArray(c+23937+i*3,"VX_cache genblk5[3] bank cwb_queue genblk3 data", true,(i+0), 75,0);}} + vcdp->declArray(c+24033,"VX_cache genblk5[3] bank cwb_queue genblk3 genblk2 head_r", false,-1, 75,0); + vcdp->declArray(c+24057,"VX_cache genblk5[3] bank cwb_queue genblk3 genblk2 curr_r", false,-1, 75,0); + vcdp->declBus(c+24081,"VX_cache genblk5[3] bank cwb_queue genblk3 genblk2 wr_ptr_r", false,-1, 1,0); + vcdp->declBus(c+24089,"VX_cache genblk5[3] bank cwb_queue genblk3 genblk2 rd_ptr_r", false,-1, 1,0); + vcdp->declBus(c+24097,"VX_cache genblk5[3] bank cwb_queue genblk3 genblk2 rd_ptr_next_r", false,-1, 1,0); + vcdp->declBit(c+21377,"VX_cache genblk5[3] bank cwb_queue genblk3 genblk2 empty_r", false,-1); + vcdp->declBit(c+21385,"VX_cache genblk5[3] bank cwb_queue genblk3 genblk2 full_r", false,-1); + vcdp->declBit(c+24105,"VX_cache genblk5[3] bank cwb_queue genblk3 genblk2 bypass_r", false,-1); + vcdp->declBus(c+25225,"VX_cache genblk5[3] bank dwb_queue DATAW", false,-1, 31,0); + vcdp->declBus(c+25081,"VX_cache genblk5[3] bank dwb_queue SIZE", false,-1, 31,0); + vcdp->declBus(c+25089,"VX_cache genblk5[3] bank dwb_queue BUFFERED_OUTPUT", false,-1, 31,0); + vcdp->declBit(c+24489,"VX_cache genblk5[3] bank dwb_queue clk", false,-1); + vcdp->declBit(c+24497,"VX_cache genblk5[3] bank dwb_queue reset", false,-1); + vcdp->declBit(c+8905,"VX_cache genblk5[3] bank dwb_queue push", false,-1); + vcdp->declBit(c+1073,"VX_cache genblk5[3] bank dwb_queue pop", false,-1); + vcdp->declArray(c+9945,"VX_cache genblk5[3] bank dwb_queue data_in", false,-1, 199,0); + vcdp->declArray(c+10001,"VX_cache genblk5[3] bank dwb_queue data_out", false,-1, 199,0); + vcdp->declBit(c+21393,"VX_cache genblk5[3] bank dwb_queue empty", false,-1); + vcdp->declBit(c+21401,"VX_cache genblk5[3] bank dwb_queue full", false,-1); + vcdp->declBus(c+24113,"VX_cache genblk5[3] bank dwb_queue size", false,-1, 2,0); + vcdp->declBus(c+24113,"VX_cache genblk5[3] bank dwb_queue size_r", false,-1, 2,0); + vcdp->declBit(c+945,"VX_cache genblk5[3] bank dwb_queue reading", false,-1); + vcdp->declBit(c+10057,"VX_cache genblk5[3] bank dwb_queue writing", false,-1); + {int i; for (i=0; i<4; i++) { + vcdp->declArray(c+24121+i*7,"VX_cache genblk5[3] bank dwb_queue genblk3 data", true,(i+0), 199,0);}} + vcdp->declArray(c+24345,"VX_cache genblk5[3] bank dwb_queue genblk3 genblk2 head_r", false,-1, 199,0); + vcdp->declArray(c+24401,"VX_cache genblk5[3] bank dwb_queue genblk3 genblk2 curr_r", false,-1, 199,0); + vcdp->declBus(c+24457,"VX_cache genblk5[3] bank dwb_queue genblk3 genblk2 wr_ptr_r", false,-1, 1,0); + vcdp->declBus(c+24465,"VX_cache genblk5[3] bank dwb_queue genblk3 genblk2 rd_ptr_r", false,-1, 1,0); + vcdp->declBus(c+24473,"VX_cache genblk5[3] bank dwb_queue genblk3 genblk2 rd_ptr_next_r", false,-1, 1,0); + vcdp->declBit(c+21393,"VX_cache genblk5[3] bank dwb_queue genblk3 genblk2 empty_r", false,-1); + vcdp->declBit(c+21401,"VX_cache genblk5[3] bank dwb_queue genblk3 genblk2 full_r", false,-1); + vcdp->declBit(c+24481,"VX_cache genblk5[3] bank dwb_queue genblk3 genblk2 bypass_r", false,-1); + } +} + +void VVX_cache::traceFullThis__1(VVX_cache__Syms* __restrict vlSymsp, VerilatedVcd* vcdp, uint32_t code) { + VVX_cache* __restrict vlTOPp VL_ATTR_UNUSED = vlSymsp->TOPp; + int c = code; + if (0 && vcdp && c) {} // Prevent unused + // Variables + WData/*127:0*/ __Vtemp547[4]; + WData/*127:0*/ __Vtemp566[4]; + WData/*127:0*/ __Vtemp585[4]; + WData/*127:0*/ __Vtemp604[4]; + WData/*127:0*/ __Vtemp522[4]; + WData/*127:0*/ __Vtemp523[4]; + WData/*127:0*/ __Vtemp524[4]; + WData/*127:0*/ __Vtemp525[4]; + WData/*127:0*/ __Vtemp528[4]; + WData/*127:0*/ __Vtemp529[4]; + WData/*127:0*/ __Vtemp534[4]; + WData/*127:0*/ __Vtemp540[4]; + WData/*127:0*/ __Vtemp541[4]; + WData/*127:0*/ __Vtemp544[4]; + WData/*127:0*/ __Vtemp545[4]; + WData/*127:0*/ __Vtemp546[4]; + WData/*127:0*/ __Vtemp548[4]; + WData/*127:0*/ __Vtemp553[4]; + WData/*127:0*/ __Vtemp559[4]; + WData/*127:0*/ __Vtemp560[4]; + WData/*127:0*/ __Vtemp563[4]; + WData/*127:0*/ __Vtemp564[4]; + WData/*127:0*/ __Vtemp565[4]; + WData/*127:0*/ __Vtemp567[4]; + WData/*127:0*/ __Vtemp572[4]; + WData/*127:0*/ __Vtemp578[4]; + WData/*127:0*/ __Vtemp579[4]; + WData/*127:0*/ __Vtemp582[4]; + WData/*127:0*/ __Vtemp583[4]; + WData/*127:0*/ __Vtemp584[4]; + WData/*127:0*/ __Vtemp586[4]; + WData/*127:0*/ __Vtemp591[4]; + WData/*127:0*/ __Vtemp597[4]; + WData/*127:0*/ __Vtemp598[4]; + WData/*127:0*/ __Vtemp601[4]; + WData/*127:0*/ __Vtemp602[4]; + WData/*127:0*/ __Vtemp603[4]; + WData/*127:0*/ __Vtemp612[4]; + WData/*127:0*/ __Vtemp620[4]; + WData/*127:0*/ __Vtemp628[4]; + WData/*127:0*/ __Vtemp636[4]; + // Body + { + vcdp->fullBus(c+1,(vlTOPp->VX_cache__DOT____Vcellout__cache_core_req_bank_sel__per_bank_valid),16); + vcdp->fullBus(c+9,(vlTOPp->VX_cache__DOT__per_bank_core_rsp_ready),4); + vcdp->fullBus(c+17,(vlTOPp->VX_cache__DOT__per_bank_dram_wb_req_ready),4); + vcdp->fullBus(c+25,(vlTOPp->VX_cache__DOT__per_bank_snp_rsp_ready),4); + vcdp->fullBus(c+33,(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__curr_bank_core_req_valid),4); + vcdp->fullBit(c+41,((1U & (IData)(vlTOPp->VX_cache__DOT__per_bank_core_rsp_ready)))); + vcdp->fullBit(c+49,((1U & (IData)(vlTOPp->VX_cache__DOT__per_bank_dram_wb_req_ready)))); + vcdp->fullBit(c+57,((1U & (IData)(vlTOPp->VX_cache__DOT__per_bank_snp_rsp_ready)))); + vcdp->fullBus(c+65,(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__curr_bank_core_req_valid),4); + vcdp->fullBit(c+73,((1U & ((IData)(vlTOPp->VX_cache__DOT__per_bank_core_rsp_ready) + >> 1U)))); + vcdp->fullBit(c+81,((1U & ((IData)(vlTOPp->VX_cache__DOT__per_bank_dram_wb_req_ready) + >> 1U)))); + vcdp->fullBit(c+89,((1U & ((IData)(vlTOPp->VX_cache__DOT__per_bank_snp_rsp_ready) + >> 1U)))); + vcdp->fullBus(c+97,(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__curr_bank_core_req_valid),4); + vcdp->fullBit(c+105,((1U & ((IData)(vlTOPp->VX_cache__DOT__per_bank_core_rsp_ready) + >> 2U)))); + vcdp->fullBit(c+113,((1U & ((IData)(vlTOPp->VX_cache__DOT__per_bank_dram_wb_req_ready) + >> 2U)))); + vcdp->fullBit(c+121,((1U & ((IData)(vlTOPp->VX_cache__DOT__per_bank_snp_rsp_ready) + >> 2U)))); + vcdp->fullBus(c+129,(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__curr_bank_core_req_valid),4); + vcdp->fullBit(c+137,((1U & ((IData)(vlTOPp->VX_cache__DOT__per_bank_core_rsp_ready) + >> 3U)))); + vcdp->fullBit(c+145,((1U & ((IData)(vlTOPp->VX_cache__DOT__per_bank_dram_wb_req_ready) + >> 3U)))); + vcdp->fullBit(c+153,((1U & ((IData)(vlTOPp->VX_cache__DOT__per_bank_snp_rsp_ready) + >> 3U)))); + vcdp->fullBus(c+161,(vlTOPp->VX_cache__DOT__cache_core_req_bank_sel__DOT__genblk2__DOT__per_bank_ready_sel),4); + vcdp->fullBit(c+169,(vlTOPp->VX_cache__DOT__cache_dram_req_arb__DOT__dfqq_pop)); + vcdp->fullBit(c+177,(vlTOPp->VX_cache__DOT__cache_dram_req_arb__DOT__dram_fill_arb__DOT__dfqq_queue__DOT__reading)); + vcdp->fullBit(c+185,(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__dram_wb_req_fire)); + vcdp->fullBit(c+193,(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__snp_rsp_fire)); + vcdp->fullQuad(c+201,(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT____Vcellinp__snp_req_queue__data_in),55); + vcdp->fullBit(c+217,(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__snp_req_queue__DOT__writing)); + vcdp->fullArray(c+225,(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT____Vcellinp__dfp_queue__data_in),154); + vcdp->fullBit(c+265,(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__dfp_queue__DOT__writing)); + vcdp->fullArray(c+273,(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__core_req_arb__DOT____Vcellinp__reqq_queue__data_in),314); + vcdp->fullBit(c+353,(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__writing)); + vcdp->fullBit(c+361,(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cwb_queue__DOT__reading)); + vcdp->fullBit(c+369,(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__dwb_queue__DOT__reading)); + vcdp->fullBit(c+377,(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__dram_wb_req_fire)); + vcdp->fullBit(c+385,(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__snp_rsp_fire)); + vcdp->fullQuad(c+393,(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT____Vcellinp__snp_req_queue__data_in),55); + vcdp->fullBit(c+409,(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__snp_req_queue__DOT__writing)); + vcdp->fullArray(c+417,(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT____Vcellinp__dfp_queue__data_in),154); + vcdp->fullBit(c+457,(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__dfp_queue__DOT__writing)); + vcdp->fullArray(c+465,(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__core_req_arb__DOT____Vcellinp__reqq_queue__data_in),314); + vcdp->fullBit(c+545,(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__writing)); + vcdp->fullBit(c+553,(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__cwb_queue__DOT__reading)); + vcdp->fullBit(c+561,(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__dwb_queue__DOT__reading)); + vcdp->fullBit(c+569,(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__dram_wb_req_fire)); + vcdp->fullBit(c+577,(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__snp_rsp_fire)); + vcdp->fullQuad(c+585,(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT____Vcellinp__snp_req_queue__data_in),55); + vcdp->fullBit(c+601,(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__snp_req_queue__DOT__writing)); + vcdp->fullArray(c+609,(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT____Vcellinp__dfp_queue__data_in),154); + vcdp->fullBit(c+649,(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__dfp_queue__DOT__writing)); + vcdp->fullArray(c+657,(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__core_req_arb__DOT____Vcellinp__reqq_queue__data_in),314); + vcdp->fullBit(c+737,(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__writing)); + vcdp->fullBit(c+745,(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__cwb_queue__DOT__reading)); + vcdp->fullBit(c+753,(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__dwb_queue__DOT__reading)); + vcdp->fullBit(c+761,(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__dram_wb_req_fire)); + vcdp->fullBit(c+769,(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__snp_rsp_fire)); + vcdp->fullQuad(c+777,(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT____Vcellinp__snp_req_queue__data_in),55); + vcdp->fullBit(c+793,(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__snp_req_queue__DOT__writing)); + vcdp->fullArray(c+801,(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT____Vcellinp__dfp_queue__data_in),154); + vcdp->fullBit(c+841,(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__dfp_queue__DOT__writing)); + vcdp->fullArray(c+849,(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__core_req_arb__DOT____Vcellinp__reqq_queue__data_in),314); + vcdp->fullBit(c+929,(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__writing)); + vcdp->fullBit(c+937,(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cwb_queue__DOT__reading)); + vcdp->fullBit(c+945,(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__dwb_queue__DOT__reading)); + vcdp->fullBit(c+953,((((IData)(vlTOPp->VX_cache__DOT__cache_dram_req_arb__DOT__dfqq_pop) + & (~ (IData)((0U != (IData)(vlTOPp->VX_cache__DOT__cache_dram_req_arb__DOT__dram_fill_arb__DOT__use_per_bank_dram_fill_req_valid))))) + & (~ ((~ (IData)((0U + != + (0xfU + & (vlTOPp->VX_cache__DOT__cache_dram_req_arb__DOT__dram_fill_arb__DOT____Vcellout__dfqq_queue__data_out[3U] + >> 0x10U))))) + | (IData)(vlTOPp->VX_cache__DOT__cache_dram_req_arb__DOT__dram_fill_arb__DOT__dfqq_queue__DOT__genblk3__DOT__genblk2__DOT__empty_r)))))); + vcdp->fullBit(c+961,(((0U != (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__curr_bank_core_req_valid)) + & (~ (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__full_r))))); + vcdp->fullBit(c+969,((1U & ((~ (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cwb_queue__DOT__genblk3__DOT__genblk2__DOT__empty_r)) + & (IData)(vlTOPp->VX_cache__DOT__per_bank_core_rsp_ready))))); + vcdp->fullBit(c+977,((((((vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT____Vcellout__dwb_queue__data_out[6U] + >> 7U) & (~ (vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT____Vcellout__dwb_queue__data_out[6U] + >> 6U))) + & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__dram_wb_req_fire)) + | (((vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT____Vcellout__dwb_queue__data_out[6U] + >> 6U) & (~ (vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT____Vcellout__dwb_queue__data_out[6U] + >> 7U))) + & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__snp_rsp_fire))) + | (((vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT____Vcellout__dwb_queue__data_out[6U] + >> 7U) & (vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT____Vcellout__dwb_queue__data_out[6U] + >> 6U)) + & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__snp_rsp_fire))))); + vcdp->fullBit(c+985,((((0U != (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__curr_bank_core_req_valid)) + & (~ (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__full_r))) + & (~ (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__full_r))))); + vcdp->fullBit(c+993,(((0U != (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__curr_bank_core_req_valid)) + & (~ (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__full_r))))); + vcdp->fullBit(c+1001,((1U & ((~ (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__cwb_queue__DOT__genblk3__DOT__genblk2__DOT__empty_r)) + & ((IData)(vlTOPp->VX_cache__DOT__per_bank_core_rsp_ready) + >> 1U))))); + vcdp->fullBit(c+1009,((((((vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT____Vcellout__dwb_queue__data_out[6U] + >> 7U) & (~ (vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT____Vcellout__dwb_queue__data_out[6U] + >> 6U))) + & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__dram_wb_req_fire)) + | (((vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT____Vcellout__dwb_queue__data_out[6U] + >> 6U) & (~ (vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT____Vcellout__dwb_queue__data_out[6U] + >> 7U))) + & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__snp_rsp_fire))) + | (((vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT____Vcellout__dwb_queue__data_out[6U] + >> 7U) & (vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT____Vcellout__dwb_queue__data_out[6U] + >> 6U)) + & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__snp_rsp_fire))))); + vcdp->fullBit(c+1017,((((0U != (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__curr_bank_core_req_valid)) + & (~ (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__full_r))) + & (~ (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__full_r))))); + vcdp->fullBit(c+1025,(((0U != (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__curr_bank_core_req_valid)) + & (~ (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__full_r))))); + vcdp->fullBit(c+1033,((1U & ((~ (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__cwb_queue__DOT__genblk3__DOT__genblk2__DOT__empty_r)) + & ((IData)(vlTOPp->VX_cache__DOT__per_bank_core_rsp_ready) + >> 2U))))); + vcdp->fullBit(c+1041,((((((vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT____Vcellout__dwb_queue__data_out[6U] + >> 7U) & (~ (vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT____Vcellout__dwb_queue__data_out[6U] + >> 6U))) + & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__dram_wb_req_fire)) + | (((vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT____Vcellout__dwb_queue__data_out[6U] + >> 6U) & (~ (vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT____Vcellout__dwb_queue__data_out[6U] + >> 7U))) + & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__snp_rsp_fire))) + | (((vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT____Vcellout__dwb_queue__data_out[6U] + >> 7U) & (vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT____Vcellout__dwb_queue__data_out[6U] + >> 6U)) + & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__snp_rsp_fire))))); + vcdp->fullBit(c+1049,((((0U != (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__curr_bank_core_req_valid)) + & (~ (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__full_r))) + & (~ (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__full_r))))); + vcdp->fullBit(c+1057,(((0U != (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__curr_bank_core_req_valid)) + & (~ (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__full_r))))); + vcdp->fullBit(c+1065,((1U & ((~ (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cwb_queue__DOT__genblk3__DOT__genblk2__DOT__empty_r)) + & ((IData)(vlTOPp->VX_cache__DOT__per_bank_core_rsp_ready) + >> 3U))))); + vcdp->fullBit(c+1073,((((((vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT____Vcellout__dwb_queue__data_out[6U] + >> 7U) & (~ (vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT____Vcellout__dwb_queue__data_out[6U] + >> 6U))) + & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__dram_wb_req_fire)) + | (((vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT____Vcellout__dwb_queue__data_out[6U] + >> 6U) & (~ (vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT____Vcellout__dwb_queue__data_out[6U] + >> 7U))) + & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__snp_rsp_fire))) + | (((vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT____Vcellout__dwb_queue__data_out[6U] + >> 7U) & (vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT____Vcellout__dwb_queue__data_out[6U] + >> 6U)) + & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__snp_rsp_fire))))); + vcdp->fullBit(c+1081,((((0U != (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__curr_bank_core_req_valid)) + & (~ (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__full_r))) + & (~ (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__full_r))))); + vcdp->fullBus(c+1089,(vlTOPp->VX_cache__DOT__per_bank_core_req_ready),4); + vcdp->fullBus(c+1097,(vlTOPp->VX_cache__DOT__per_bank_core_rsp_valid),4); + vcdp->fullBus(c+1105,(vlTOPp->VX_cache__DOT__per_bank_core_rsp_tid),8); + vcdp->fullArray(c+1113,(vlTOPp->VX_cache__DOT__per_bank_core_rsp_data),128); + vcdp->fullArray(c+1145,(vlTOPp->VX_cache__DOT__per_bank_core_rsp_tag),168); + vcdp->fullBus(c+1193,(vlTOPp->VX_cache__DOT__per_bank_dram_fill_req_valid),4); + vcdp->fullArray(c+1201,(vlTOPp->VX_cache__DOT__per_bank_dram_fill_req_addr),112); + vcdp->fullBus(c+1233,(vlTOPp->VX_cache__DOT__per_bank_dram_fill_rsp_ready),4); + vcdp->fullBus(c+1241,(vlTOPp->VX_cache__DOT__per_bank_dram_wb_req_valid),4); + vcdp->fullQuad(c+1249,(vlTOPp->VX_cache__DOT__per_bank_dram_wb_req_byteen),64); + vcdp->fullArray(c+1265,(vlTOPp->VX_cache__DOT__per_bank_dram_wb_req_addr),112); + vcdp->fullArray(c+1297,(vlTOPp->VX_cache__DOT__per_bank_dram_wb_req_data),512); + vcdp->fullBus(c+1425,(vlTOPp->VX_cache__DOT__per_bank_snp_req_ready),4); + vcdp->fullBus(c+1433,(vlTOPp->VX_cache__DOT__per_bank_snp_rsp_valid),4); + vcdp->fullArray(c+1441,(vlTOPp->VX_cache__DOT__per_bank_snp_rsp_tag),112); + vcdp->fullBus(c+1473,((3U & (vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT____Vcellout__cwb_queue__data_out[2U] + >> 0xaU))),2); + vcdp->fullBus(c+1481,(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT____Vcellout__cwb_queue__data_out[0U]),32); + vcdp->fullQuad(c+1489,((VL_ULL(0x3ffffffffff) + & (((QData)((IData)( + vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT____Vcellout__cwb_queue__data_out[2U])) + << 0x20U) | (QData)((IData)( + vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT____Vcellout__cwb_queue__data_out[1U]))))),42); + vcdp->fullBit(c+1505,((((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__miss_add_unqual) + & ((~ (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__mrvq_init_ready_state_st2)) + | ((vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__st_1e_2__DOT__value[9U] + >> 0x1aU) & + (~ (vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__st_1e_2__DOT__value[9U] + >> 0x1bU))))) + & (~ (((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__dwbq_push_stall) + | (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__mrvq_push_stall)) + | (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cwbq_push_stall)))))); + vcdp->fullBit(c+1513,(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__curr_bank_dram_wb_req_valid)); + vcdp->fullBus(c+1521,((0xffffU & ((vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT____Vcellout__dwb_queue__data_out[6U] + << 0xaU) + | (vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT____Vcellout__dwb_queue__data_out[5U] + >> 0x16U)))),16); + vcdp->fullBus(c+1529,((0x3ffffffU & ((vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT____Vcellout__dwb_queue__data_out[5U] + << 4U) + | (vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT____Vcellout__dwb_queue__data_out[4U] + >> 0x1cU)))),26); + __Vtemp522[0U] = ((vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT____Vcellout__dwb_queue__data_out[1U] + << 4U) | (vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT____Vcellout__dwb_queue__data_out[0U] + >> 0x1cU)); + __Vtemp522[1U] = ((vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT____Vcellout__dwb_queue__data_out[2U] + << 4U) | (vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT____Vcellout__dwb_queue__data_out[1U] + >> 0x1cU)); + __Vtemp522[2U] = ((vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT____Vcellout__dwb_queue__data_out[3U] + << 4U) | (vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT____Vcellout__dwb_queue__data_out[2U] + >> 0x1cU)); + __Vtemp522[3U] = ((vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT____Vcellout__dwb_queue__data_out[4U] + << 4U) | (vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT____Vcellout__dwb_queue__data_out[3U] + >> 0x1cU)); + vcdp->fullArray(c+1537,(__Vtemp522),128); + vcdp->fullBit(c+1569,(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__curr_bank_snp_rsp_valid)); + vcdp->fullBus(c+1577,((0xfffffffU & vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT____Vcellout__dwb_queue__data_out[0U])),28); + vcdp->fullBus(c+1585,((3U & (vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT____Vcellout__cwb_queue__data_out[2U] + >> 0xaU))),2); + vcdp->fullBus(c+1593,(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT____Vcellout__cwb_queue__data_out[0U]),32); + vcdp->fullQuad(c+1601,((VL_ULL(0x3ffffffffff) + & (((QData)((IData)( + vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT____Vcellout__cwb_queue__data_out[2U])) + << 0x20U) | (QData)((IData)( + vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT____Vcellout__cwb_queue__data_out[1U]))))),42); + vcdp->fullBit(c+1617,((((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__miss_add_unqual) + & ((~ (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__mrvq_init_ready_state_st2)) + | ((vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__st_1e_2__DOT__value[9U] + >> 0x1aU) & + (~ (vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__st_1e_2__DOT__value[9U] + >> 0x1bU))))) + & (~ (((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__dwbq_push_stall) + | (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__mrvq_push_stall)) + | (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__cwbq_push_stall)))))); + vcdp->fullBit(c+1625,(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__curr_bank_dram_wb_req_valid)); + vcdp->fullBus(c+1633,((0xffffU & ((vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT____Vcellout__dwb_queue__data_out[6U] + << 0xaU) + | (vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT____Vcellout__dwb_queue__data_out[5U] + >> 0x16U)))),16); + vcdp->fullBus(c+1641,((0x3ffffffU & ((vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT____Vcellout__dwb_queue__data_out[5U] + << 4U) + | (vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT____Vcellout__dwb_queue__data_out[4U] + >> 0x1cU)))),26); + __Vtemp523[0U] = ((vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT____Vcellout__dwb_queue__data_out[1U] + << 4U) | (vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT____Vcellout__dwb_queue__data_out[0U] + >> 0x1cU)); + __Vtemp523[1U] = ((vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT____Vcellout__dwb_queue__data_out[2U] + << 4U) | (vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT____Vcellout__dwb_queue__data_out[1U] + >> 0x1cU)); + __Vtemp523[2U] = ((vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT____Vcellout__dwb_queue__data_out[3U] + << 4U) | (vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT____Vcellout__dwb_queue__data_out[2U] + >> 0x1cU)); + __Vtemp523[3U] = ((vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT____Vcellout__dwb_queue__data_out[4U] + << 4U) | (vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT____Vcellout__dwb_queue__data_out[3U] + >> 0x1cU)); + vcdp->fullArray(c+1649,(__Vtemp523),128); + vcdp->fullBit(c+1681,(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__curr_bank_snp_rsp_valid)); + vcdp->fullBus(c+1689,((0xfffffffU & vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT____Vcellout__dwb_queue__data_out[0U])),28); + vcdp->fullBus(c+1697,((3U & (vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT____Vcellout__cwb_queue__data_out[2U] + >> 0xaU))),2); + vcdp->fullBus(c+1705,(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT____Vcellout__cwb_queue__data_out[0U]),32); + vcdp->fullQuad(c+1713,((VL_ULL(0x3ffffffffff) + & (((QData)((IData)( + vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT____Vcellout__cwb_queue__data_out[2U])) + << 0x20U) | (QData)((IData)( + vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT____Vcellout__cwb_queue__data_out[1U]))))),42); + vcdp->fullBit(c+1729,((((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__miss_add_unqual) + & ((~ (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__mrvq_init_ready_state_st2)) + | ((vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__st_1e_2__DOT__value[9U] + >> 0x1aU) & + (~ (vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__st_1e_2__DOT__value[9U] + >> 0x1bU))))) + & (~ (((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__dwbq_push_stall) + | (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__mrvq_push_stall)) + | (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__cwbq_push_stall)))))); + vcdp->fullBit(c+1737,(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__curr_bank_dram_wb_req_valid)); + vcdp->fullBus(c+1745,((0xffffU & ((vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT____Vcellout__dwb_queue__data_out[6U] + << 0xaU) + | (vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT____Vcellout__dwb_queue__data_out[5U] + >> 0x16U)))),16); + vcdp->fullBus(c+1753,((0x3ffffffU & ((vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT____Vcellout__dwb_queue__data_out[5U] + << 4U) + | (vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT____Vcellout__dwb_queue__data_out[4U] + >> 0x1cU)))),26); + __Vtemp524[0U] = ((vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT____Vcellout__dwb_queue__data_out[1U] + << 4U) | (vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT____Vcellout__dwb_queue__data_out[0U] + >> 0x1cU)); + __Vtemp524[1U] = ((vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT____Vcellout__dwb_queue__data_out[2U] + << 4U) | (vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT____Vcellout__dwb_queue__data_out[1U] + >> 0x1cU)); + __Vtemp524[2U] = ((vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT____Vcellout__dwb_queue__data_out[3U] + << 4U) | (vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT____Vcellout__dwb_queue__data_out[2U] + >> 0x1cU)); + __Vtemp524[3U] = ((vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT____Vcellout__dwb_queue__data_out[4U] + << 4U) | (vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT____Vcellout__dwb_queue__data_out[3U] + >> 0x1cU)); + vcdp->fullArray(c+1761,(__Vtemp524),128); + vcdp->fullBit(c+1793,(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__curr_bank_snp_rsp_valid)); + vcdp->fullBus(c+1801,((0xfffffffU & vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT____Vcellout__dwb_queue__data_out[0U])),28); + vcdp->fullBus(c+1809,((3U & (vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT____Vcellout__cwb_queue__data_out[2U] + >> 0xaU))),2); + vcdp->fullBus(c+1817,(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT____Vcellout__cwb_queue__data_out[0U]),32); + vcdp->fullQuad(c+1825,((VL_ULL(0x3ffffffffff) + & (((QData)((IData)( + vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT____Vcellout__cwb_queue__data_out[2U])) + << 0x20U) | (QData)((IData)( + vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT____Vcellout__cwb_queue__data_out[1U]))))),42); + vcdp->fullBit(c+1841,((((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__miss_add_unqual) + & ((~ (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__mrvq_init_ready_state_st2)) + | ((vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__st_1e_2__DOT__value[9U] + >> 0x1aU) & + (~ (vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__st_1e_2__DOT__value[9U] + >> 0x1bU))))) + & (~ (((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__dwbq_push_stall) + | (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__mrvq_push_stall)) + | (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cwbq_push_stall)))))); + vcdp->fullBit(c+1849,(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__curr_bank_dram_wb_req_valid)); + vcdp->fullBus(c+1857,((0xffffU & ((vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT____Vcellout__dwb_queue__data_out[6U] + << 0xaU) + | (vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT____Vcellout__dwb_queue__data_out[5U] + >> 0x16U)))),16); + vcdp->fullBus(c+1865,((0x3ffffffU & ((vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT____Vcellout__dwb_queue__data_out[5U] + << 4U) + | (vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT____Vcellout__dwb_queue__data_out[4U] + >> 0x1cU)))),26); + __Vtemp525[0U] = ((vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT____Vcellout__dwb_queue__data_out[1U] + << 4U) | (vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT____Vcellout__dwb_queue__data_out[0U] + >> 0x1cU)); + __Vtemp525[1U] = ((vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT____Vcellout__dwb_queue__data_out[2U] + << 4U) | (vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT____Vcellout__dwb_queue__data_out[1U] + >> 0x1cU)); + __Vtemp525[2U] = ((vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT____Vcellout__dwb_queue__data_out[3U] + << 4U) | (vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT____Vcellout__dwb_queue__data_out[2U] + >> 0x1cU)); + __Vtemp525[3U] = ((vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT____Vcellout__dwb_queue__data_out[4U] + << 4U) | (vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT____Vcellout__dwb_queue__data_out[3U] + >> 0x1cU)); + vcdp->fullArray(c+1873,(__Vtemp525),128); + vcdp->fullBit(c+1905,(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__curr_bank_snp_rsp_valid)); + vcdp->fullBus(c+1913,((0xfffffffU & vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT____Vcellout__dwb_queue__data_out[0U])),28); + vcdp->fullBit(c+1921,(vlTOPp->VX_cache__DOT__cache_dram_req_arb__DOT__dwb_valid)); + vcdp->fullBit(c+1929,(vlTOPp->VX_cache__DOT__cache_dram_req_arb__DOT__dfqq_req)); + vcdp->fullBus(c+1937,(((0x6fU >= (0x7fU & ((IData)(0x1cU) + * (IData)(vlTOPp->VX_cache__DOT__cache_dram_req_arb__DOT__dram_fill_arb__DOT__qual_request_index)))) + ? (0xfffffffU & (((0U + == + (0x1fU + & ((IData)(0x1cU) + * (IData)(vlTOPp->VX_cache__DOT__cache_dram_req_arb__DOT__dram_fill_arb__DOT__qual_request_index)))) + ? 0U + : + (vlTOPp->VX_cache__DOT__cache_dram_req_arb__DOT__dram_fill_arb__DOT__qual_bank_dram_fill_req_addr[ + ((IData)(1U) + + + (3U + & (((IData)(0x1cU) + * (IData)(vlTOPp->VX_cache__DOT__cache_dram_req_arb__DOT__dram_fill_arb__DOT__qual_request_index)) + >> 5U)))] + << + ((IData)(0x20U) + - + (0x1fU + & ((IData)(0x1cU) + * (IData)(vlTOPp->VX_cache__DOT__cache_dram_req_arb__DOT__dram_fill_arb__DOT__qual_request_index)))))) + | (vlTOPp->VX_cache__DOT__cache_dram_req_arb__DOT__dram_fill_arb__DOT__qual_bank_dram_fill_req_addr[ + (3U + & (((IData)(0x1cU) + * (IData)(vlTOPp->VX_cache__DOT__cache_dram_req_arb__DOT__dram_fill_arb__DOT__qual_request_index)) + >> 5U))] + >> + (0x1fU + & ((IData)(0x1cU) + * (IData)(vlTOPp->VX_cache__DOT__cache_dram_req_arb__DOT__dram_fill_arb__DOT__qual_request_index)))))) + : 0U)),28); + vcdp->fullBit(c+1945,((1U & (~ (IData)(vlTOPp->VX_cache__DOT__cache_dram_req_arb__DOT__dram_fill_arb__DOT__qual_has_request))))); + vcdp->fullBit(c+1953,((0U != (IData)(vlTOPp->VX_cache__DOT__per_bank_dram_fill_req_valid)))); + vcdp->fullBus(c+1961,(vlTOPp->VX_cache__DOT__cache_dram_req_arb__DOT__dwb_bank),2); + vcdp->fullBit(c+1969,(vlTOPp->VX_cache__DOT__cache_dram_req_arb__DOT__prfqq__DOT__update_use)); + vcdp->fullBit(c+1977,(vlTOPp->VX_cache__DOT__cache_dram_req_arb__DOT__prfqq__DOT__pfq_queue__DOT__reading)); + vcdp->fullBit(c+1985,(vlTOPp->VX_cache__DOT__cache_dram_req_arb__DOT__prfqq__DOT__pfq_queue__DOT__writing)); + vcdp->fullBus(c+1993,((0xfU & (vlTOPp->VX_cache__DOT__cache_dram_req_arb__DOT__dram_fill_arb__DOT____Vcellout__dfqq_queue__data_out[3U] + >> 0x10U))),4); + __Vtemp528[0U] = vlTOPp->VX_cache__DOT__cache_dram_req_arb__DOT__dram_fill_arb__DOT____Vcellout__dfqq_queue__data_out[0U]; + __Vtemp528[1U] = vlTOPp->VX_cache__DOT__cache_dram_req_arb__DOT__dram_fill_arb__DOT____Vcellout__dfqq_queue__data_out[1U]; + __Vtemp528[2U] = vlTOPp->VX_cache__DOT__cache_dram_req_arb__DOT__dram_fill_arb__DOT____Vcellout__dfqq_queue__data_out[2U]; + __Vtemp528[3U] = (0xffffU & vlTOPp->VX_cache__DOT__cache_dram_req_arb__DOT__dram_fill_arb__DOT____Vcellout__dfqq_queue__data_out[3U]); + vcdp->fullArray(c+2001,(__Vtemp528),112); + vcdp->fullBus(c+2033,(vlTOPp->VX_cache__DOT__cache_dram_req_arb__DOT__dram_fill_arb__DOT__use_per_bqual_bank_dram_fill_req_valid),4); + vcdp->fullArray(c+2041,(vlTOPp->VX_cache__DOT__cache_dram_req_arb__DOT__dram_fill_arb__DOT__qual_bank_dram_fill_req_addr),112); + vcdp->fullBus(c+2073,(((IData)(vlTOPp->VX_cache__DOT__cache_dram_req_arb__DOT__dram_fill_arb__DOT__use_per_bqual_bank_dram_fill_req_valid) + & (~ ((IData)(1U) << (IData)(vlTOPp->VX_cache__DOT__cache_dram_req_arb__DOT__dram_fill_arb__DOT__qual_request_index))))),4); + vcdp->fullBit(c+2081,((1U & ((~ (IData)((0U + != + (0xfU + & (vlTOPp->VX_cache__DOT__cache_dram_req_arb__DOT__dram_fill_arb__DOT____Vcellout__dfqq_queue__data_out[3U] + >> 0x10U))))) + | (IData)(vlTOPp->VX_cache__DOT__cache_dram_req_arb__DOT__dram_fill_arb__DOT__dfqq_queue__DOT__genblk3__DOT__genblk2__DOT__empty_r))))); + vcdp->fullBit(c+2089,(((0U != (IData)(vlTOPp->VX_cache__DOT__per_bank_dram_fill_req_valid)) + & (~ (IData)(vlTOPp->VX_cache__DOT__cache_dram_req_arb__DOT__dram_fill_arb__DOT__dfqq_queue__DOT__genblk3__DOT__genblk2__DOT__full_r))))); + vcdp->fullBus(c+2097,(vlTOPp->VX_cache__DOT__cache_dram_req_arb__DOT__dram_fill_arb__DOT__qual_request_index),2); + vcdp->fullBit(c+2105,(vlTOPp->VX_cache__DOT__cache_dram_req_arb__DOT__dram_fill_arb__DOT__qual_has_request)); + vcdp->fullArray(c+2113,(vlTOPp->VX_cache__DOT__cache_dram_req_arb__DOT__dram_fill_arb__DOT____Vcellinp__dfqq_queue__data_in),116); + vcdp->fullArray(c+2145,(vlTOPp->VX_cache__DOT__cache_dram_req_arb__DOT__dram_fill_arb__DOT____Vcellout__dfqq_queue__data_out),116); + vcdp->fullBit(c+2177,(vlTOPp->VX_cache__DOT__cache_dram_req_arb__DOT__dram_fill_arb__DOT__dfqq_queue__DOT__writing)); + vcdp->fullBus(c+2185,(vlTOPp->VX_cache__DOT__cache_dram_req_arb__DOT__dram_fill_arb__DOT__sel_bank__DOT__genblk2__DOT__grant_onehot_r),4); + vcdp->fullBus(c+2193,(vlTOPp->VX_cache__DOT__cache_dram_req_arb__DOT__dram_fill_arb__DOT__sel_bank__DOT__genblk2__DOT__priority_encoder__DOT__i),32); + vcdp->fullBus(c+2201,(vlTOPp->VX_cache__DOT__cache_dram_req_arb__DOT__sel_dwb__DOT__genblk2__DOT__grant_onehot_r),4); + vcdp->fullBus(c+2209,(vlTOPp->VX_cache__DOT__cache_dram_req_arb__DOT__sel_dwb__DOT__genblk2__DOT__priority_encoder__DOT__i),32); + vcdp->fullArray(c+2217,(vlTOPp->VX_cache__DOT____Vcellout__cache_core_rsp_merge__core_rsp_data),128); + vcdp->fullQuad(c+2249,(((0xa7U >= (0xffU & + ((IData)(0x2aU) + * (IData)(vlTOPp->VX_cache__DOT__cache_core_rsp_merge__DOT__main_bank_index)))) + ? (VL_ULL(0x3ffffffffff) + & (((0U == (0x1fU + & ((IData)(0x2aU) + * (IData)(vlTOPp->VX_cache__DOT__cache_core_rsp_merge__DOT__main_bank_index)))) + ? VL_ULL(0) + : ((QData)((IData)( + vlTOPp->VX_cache__DOT__per_bank_core_rsp_tag[ + ((IData)(2U) + + + (7U + & (((IData)(0x2aU) + * (IData)(vlTOPp->VX_cache__DOT__cache_core_rsp_merge__DOT__main_bank_index)) + >> 5U)))])) + << ((IData)(0x40U) + - (0x1fU + & ((IData)(0x2aU) + * (IData)(vlTOPp->VX_cache__DOT__cache_core_rsp_merge__DOT__main_bank_index)))))) + | (((QData)((IData)( + vlTOPp->VX_cache__DOT__per_bank_core_rsp_tag[ + ((IData)(1U) + + + (7U + & (((IData)(0x2aU) + * (IData)(vlTOPp->VX_cache__DOT__cache_core_rsp_merge__DOT__main_bank_index)) + >> 5U)))])) + << ((0U + == + (0x1fU + & ((IData)(0x2aU) + * (IData)(vlTOPp->VX_cache__DOT__cache_core_rsp_merge__DOT__main_bank_index)))) + ? 0x20U + : ((IData)(0x20U) + - + (0x1fU + & ((IData)(0x2aU) + * (IData)(vlTOPp->VX_cache__DOT__cache_core_rsp_merge__DOT__main_bank_index)))))) + | ((QData)((IData)( + vlTOPp->VX_cache__DOT__per_bank_core_rsp_tag[ + (7U + & (((IData)(0x2aU) + * (IData)(vlTOPp->VX_cache__DOT__cache_core_rsp_merge__DOT__main_bank_index)) + >> 5U))])) + >> (0x1fU + & ((IData)(0x2aU) + * (IData)(vlTOPp->VX_cache__DOT__cache_core_rsp_merge__DOT__main_bank_index))))))) + : VL_ULL(0))),42); + vcdp->fullBus(c+2265,(vlTOPp->VX_cache__DOT__cache_core_rsp_merge__DOT__main_bank_index),2); + vcdp->fullBus(c+2273,(vlTOPp->VX_cache__DOT__cache_core_rsp_merge__DOT__per_bank_core_rsp_pop_unqual),4); + vcdp->fullBus(c+2281,(vlTOPp->VX_cache__DOT__cache_core_rsp_merge__DOT__sel_bank__DOT__genblk2__DOT__grant_onehot_r),4); + vcdp->fullBit(c+2289,(vlTOPp->VX_cache__DOT__cache_core_rsp_merge__DOT__sel_bank__DOT__grant_valid)); + vcdp->fullBus(c+2297,((((IData)(vlTOPp->VX_cache__DOT__cache_core_rsp_merge__DOT__sel_bank__DOT__genblk2__DOT__requests_use) + & (~ (IData)(vlTOPp->VX_cache__DOT__cache_core_rsp_merge__DOT__sel_bank__DOT__genblk2__DOT__grant_onehot_r))) + | (((IData)(vlTOPp->VX_cache__DOT__cache_core_rsp_merge__DOT__sel_bank__DOT__genblk2__DOT__refill_original) + ^ (IData)(vlTOPp->VX_cache__DOT__per_bank_core_rsp_valid)) + & (~ (IData)(vlTOPp->VX_cache__DOT__cache_core_rsp_merge__DOT__sel_bank__DOT__genblk2__DOT__refill_original))))),4); + vcdp->fullBus(c+2305,((((IData)(vlTOPp->VX_cache__DOT__cache_core_rsp_merge__DOT__sel_bank__DOT__genblk2__DOT__refill_original) + ^ (IData)(vlTOPp->VX_cache__DOT__per_bank_core_rsp_valid)) + & (~ (IData)(vlTOPp->VX_cache__DOT__cache_core_rsp_merge__DOT__sel_bank__DOT__genblk2__DOT__refill_original)))),4); + vcdp->fullBus(c+2313,(vlTOPp->VX_cache__DOT__cache_core_rsp_merge__DOT__sel_bank__DOT__genblk2__DOT__priority_encoder__DOT__i),32); + vcdp->fullBus(c+2321,(vlTOPp->VX_cache__DOT__snp_rsp_arb__DOT__fsq_bank),2); + vcdp->fullBit(c+2329,(vlTOPp->VX_cache__DOT__snp_rsp_arb__DOT__fsq_valid)); + vcdp->fullBus(c+2337,(vlTOPp->VX_cache__DOT__snp_rsp_arb__DOT__sel_ffsq__DOT__genblk2__DOT__grant_onehot_r),4); + vcdp->fullBus(c+2345,(vlTOPp->VX_cache__DOT__snp_rsp_arb__DOT__sel_ffsq__DOT__genblk2__DOT__priority_encoder__DOT__i),32); + vcdp->fullBit(c+2353,(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__snrq_pop)); + vcdp->fullBus(c+2361,((0x3ffffffU & (IData)( + (vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT____Vcellout__snp_req_queue__data_out + >> 0x1dU)))),26); + vcdp->fullBit(c+2369,((1U & (IData)((vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT____Vcellout__snp_req_queue__data_out + >> 0x1cU))))); + vcdp->fullBus(c+2377,((0xfffffffU & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT____Vcellout__snp_req_queue__data_out))),28); + vcdp->fullBit(c+2385,(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__dfpq_pop)); + vcdp->fullBus(c+2393,((0x3ffffffU & vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT____Vcellout__dfp_queue__data_out[4U])),26); + __Vtemp529[0U] = vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT____Vcellout__dfp_queue__data_out[0U]; + __Vtemp529[1U] = vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT____Vcellout__dfp_queue__data_out[1U]; + __Vtemp529[2U] = vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT____Vcellout__dfp_queue__data_out[2U]; + __Vtemp529[3U] = vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT____Vcellout__dfp_queue__data_out[3U]; + vcdp->fullArray(c+2401,(__Vtemp529),128); + vcdp->fullBit(c+2433,(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__reqq_pop)); + vcdp->fullBit(c+2441,((1U & (~ (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__core_req_arb__DOT__qual_has_request))))); + vcdp->fullBit(c+2449,(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__core_req_arb__DOT__qual_has_request)); + vcdp->fullBus(c+2457,(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__core_req_arb__DOT__qual_request_index),2); + vcdp->fullBit(c+2465,(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__reqq_req_rw_st0)); + vcdp->fullBus(c+2473,((0xfU & ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__core_req_arb__DOT__use_per_byteen) + >> (0xfU & ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__core_req_arb__DOT__qual_request_index) + << 2U))))),4); + vcdp->fullBus(c+2481,(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__reqq_req_addr_st0),30); + vcdp->fullBus(c+2489,((((0U == (0x1fU & ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__core_req_arb__DOT__qual_request_index) + << 5U))) + ? 0U : (vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__core_req_arb__DOT__use_per_writedata[ + ((IData)(1U) + + (3U & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__core_req_arb__DOT__qual_request_index)))] + << ((IData)(0x20U) + - (0x1fU + & ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__core_req_arb__DOT__qual_request_index) + << 5U))))) + | (vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__core_req_arb__DOT__use_per_writedata[ + (3U & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__core_req_arb__DOT__qual_request_index))] + >> (0x1fU & ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__core_req_arb__DOT__qual_request_index) + << 5U))))),32); + vcdp->fullBit(c+2497,(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__mrvq_pop)); + vcdp->fullBit(c+2505,(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cache_miss_resrv__DOT__dequeue_possible)); + vcdp->fullBit(c+2513,(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__mrvq_rw_st0)); + vcdp->fullBit(c+2521,((0U != (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cache_miss_resrv__DOT__valid_address_match)))); + vcdp->fullBit(c+2529,(((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__miss_add_because_miss) + & (((0x3ffffffU & (( + vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__st_1e_2__DOT__value[9U] + << 7U) + | (vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__st_1e_2__DOT__value[8U] + >> 0x19U))) + == vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__addr_st1 + [0U]) & (~ (vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__st_1e_2__DOT__value[9U] + >> 0x14U)))))); + vcdp->fullBit(c+2537,(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__force_request_miss_st1e)); + vcdp->fullBit(c+2545,(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__recover_mrvq_state_st2)); + vcdp->fullBit(c+2553,(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__mrvq_push_stall)); + vcdp->fullBit(c+2561,(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cwbq_push_stall)); + vcdp->fullBit(c+2569,(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__dwbq_push_stall)); + vcdp->fullBit(c+2577,(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__dram_fill_req_stall)); + vcdp->fullBit(c+2585,(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__stall_bank_pipe)); + vcdp->fullBit(c+2593,(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__is_fill_in_pipe)); + vcdp->fullBit(c+2601,(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__is_fill_st1[0])); + vcdp->fullBit(c+2609,(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__going_to_write_st1[0])); + vcdp->fullBit(c+2617,(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__dfpq_pop_unqual)); + vcdp->fullBit(c+2625,(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__reqq_pop_unqual)); + vcdp->fullBit(c+2633,(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__snrq_pop_unqual)); + vcdp->fullBit(c+2641,(((((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__dfpq_pop) + | (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__mrvq_pop)) + | (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__reqq_pop)) + | (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__snrq_pop)))); + vcdp->fullBus(c+2649,((0x3ffffffU & ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__dfpq_pop_unqual) + ? (0x3ffffffU + & vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT____Vcellout__dfp_queue__data_out[4U]) + : ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cache_miss_resrv__DOT__dequeue_possible) + ? + ((0x19fU + >= + (0x1ffU + & ((IData)(0x1aU) + * (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr)))) + ? + (0x3ffffffU + & (((0U + == + (0x1fU + & ((IData)(0x1aU) + * (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr)))) + ? 0U + : + (vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cache_miss_resrv__DOT__addr_table[ + ((IData)(1U) + + + (0xfU + & (((IData)(0x1aU) + * (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr)) + >> 5U)))] + << + ((IData)(0x20U) + - + (0x1fU + & ((IData)(0x1aU) + * (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr)))))) + | (vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cache_miss_resrv__DOT__addr_table[ + (0xfU + & (((IData)(0x1aU) + * (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr)) + >> 5U))] + >> + (0x1fU + & ((IData)(0x1aU) + * (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr)))))) + : 0U) + : + ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__reqq_pop_unqual) + ? + (0x3ffffffU + & (vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__reqq_req_addr_st0 + >> 4U)) + : + ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__snrq_pop_unqual) + ? + (0x3ffffffU + & (IData)( + (vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT____Vcellout__snp_req_queue__data_out + >> 0x1dU))) + : 0U)))))),26); + vcdp->fullBus(c+2657,((3U & ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__reqq_pop_unqual) + ? (3U & vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__reqq_req_addr_st0) + : ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cache_miss_resrv__DOT__dequeue_possible) + ? (3U & ( + (vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cache_miss_resrv__DOT__metadata_table + [vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr][1U] + << 0x1eU) + | (vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cache_miss_resrv__DOT__metadata_table + [vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr][0U] + >> 2U))) + : 0U)))),2); + vcdp->fullBus(c+2665,(((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cache_miss_resrv__DOT__dequeue_possible) + ? ((vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cache_miss_resrv__DOT__metadata_table + [vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr][2U] + << 0xbU) | (vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cache_miss_resrv__DOT__metadata_table + [vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr][1U] + >> 0x15U)) + : ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__reqq_pop_unqual) + ? (((0U == (0x1fU + & ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__core_req_arb__DOT__qual_request_index) + << 5U))) + ? 0U : (vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__core_req_arb__DOT__use_per_writedata[ + ((IData)(1U) + + + (3U + & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__core_req_arb__DOT__qual_request_index)))] + << + ((IData)(0x20U) + - + (0x1fU + & ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__core_req_arb__DOT__qual_request_index) + << 5U))))) + | (vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__core_req_arb__DOT__use_per_writedata[ + (3U & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__core_req_arb__DOT__qual_request_index))] + >> (0x1fU + & ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__core_req_arb__DOT__qual_request_index) + << 5U)))) + : 0U))),32); + __Vtemp534[0U] = ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__dfpq_pop_unqual) + ? vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT____Vcellout__dfp_queue__data_out[0U] + : 0x39U); + __Vtemp534[1U] = ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__dfpq_pop_unqual) + ? vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT____Vcellout__dfp_queue__data_out[1U] + : 0U); + __Vtemp534[2U] = ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__dfpq_pop_unqual) + ? vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT____Vcellout__dfp_queue__data_out[2U] + : 0U); + __Vtemp534[3U] = ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__dfpq_pop_unqual) + ? vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT____Vcellout__dfp_queue__data_out[3U] + : 0U); + vcdp->fullArray(c+2673,(__Vtemp534),128); + vcdp->fullQuad(c+2705,(((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cache_miss_resrv__DOT__dequeue_possible) + ? ((VL_ULL(0x1ffffffffff80) + & (((QData)((IData)( + vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cache_miss_resrv__DOT__metadata_table + [vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr][2U])) + << 0x3eU) + | (((QData)((IData)( + vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cache_miss_resrv__DOT__metadata_table + [vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr][1U])) + << 0x1eU) + | (VL_ULL(0x3fffffffffffff80) + & ((QData)((IData)( + vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cache_miss_resrv__DOT__metadata_table + [vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr][0U])) + >> 2U))))) + | (QData)((IData)( + (((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__mrvq_rw_st0) + << 6U) + | ((0x3cU + & ((vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cache_miss_resrv__DOT__metadata_table + [vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr][1U] + << 0x1eU) + | (0x3ffffffcU + & (vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cache_miss_resrv__DOT__metadata_table + [vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr][0U] + >> 2U)))) + | (3U + & ((vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cache_miss_resrv__DOT__metadata_table + [vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr][2U] + << 0xdU) + | (vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cache_miss_resrv__DOT__metadata_table + [vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr][1U] + >> 0x13U)))))))) + : ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__reqq_pop_unqual) + ? ((vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__core_req_arb__DOT__use_per_tag + << 7U) | (QData)((IData)( + (((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__reqq_req_rw_st0) + << 6U) + | ((0x3cU + & (((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__core_req_arb__DOT__use_per_byteen) + >> + (0xfU + & ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__core_req_arb__DOT__qual_request_index) + << 2U))) + << 2U)) + | (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__core_req_arb__DOT__qual_request_index)))))) + : ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__snrq_pop_unqual) + ? ((QData)((IData)( + (0xfffffffU + & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT____Vcellout__snp_req_queue__data_out)))) + << 7U) : VL_ULL(0))))),49); + vcdp->fullBit(c+2721,(((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__dfpq_pop_unqual) + ? 1U : (((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cache_miss_resrv__DOT__dequeue_possible) + & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__mrvq_rw_st0)) + ? 1U : (((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__reqq_pop_unqual) + & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__reqq_req_rw_st0)) + ? 1U + : 0U))))); + vcdp->fullBit(c+2729,((1U & ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cache_miss_resrv__DOT__dequeue_possible) + ? (1U & (vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cache_miss_resrv__DOT__metadata_table + [vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr][0U] + >> 1U)) + : ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__snrq_pop_unqual) + ? 1U : 0U))))); + vcdp->fullBit(c+2737,((1U & ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cache_miss_resrv__DOT__dequeue_possible) + ? (1U & vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cache_miss_resrv__DOT__metadata_table + [vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr][0U]) + : ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__snrq_pop_unqual) + ? (1U & (IData)( + (vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT____Vcellout__snp_req_queue__data_out + >> 0x1cU))) + : 0U))))); + vcdp->fullBit(c+2745,(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__valid_st1[0])); + vcdp->fullBus(c+2753,(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__addr_st1[0]),26); + vcdp->fullBus(c+2761,(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__wsel_st1[0]),2); + vcdp->fullBus(c+2769,(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__writeword_st1[0]),32); + vcdp->fullQuad(c+2777,(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__inst_meta_st1[0]),49); + vcdp->fullArray(c+2793,(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__writedata_st1[0]),128); + vcdp->fullBit(c+2825,(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__is_snp_st1[0])); + vcdp->fullBit(c+2833,(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__snp_invalidate_st1[0])); + vcdp->fullBit(c+2841,(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__is_mrvq_st1[0])); + __Vtemp540[0U] = vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__tag_data_access__DOT__read_data_st1c + [0U][0U]; + __Vtemp540[1U] = vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__tag_data_access__DOT__read_data_st1c + [0U][1U]; + __Vtemp540[2U] = vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__tag_data_access__DOT__read_data_st1c + [0U][2U]; + __Vtemp540[3U] = vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__tag_data_access__DOT__read_data_st1c + [0U][3U]; + vcdp->fullBus(c+2849,((((0U == (0x1fU & (vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__wsel_st1 + [0U] + << 5U))) + ? 0U : (__Vtemp540[ + ((IData)(1U) + + (3U & vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__wsel_st1 + [0U]))] + << ((IData)(0x20U) + - (0x1fU + & (vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__wsel_st1 + [0U] + << 5U))))) + | (__Vtemp540[(3U & + vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__wsel_st1 + [0U])] + >> (0x1fU & (vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__wsel_st1 + [0U] + << 5U))))),32); + __Vtemp541[0U] = vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__tag_data_access__DOT__read_data_st1c + [0U][0U]; + __Vtemp541[1U] = vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__tag_data_access__DOT__read_data_st1c + [0U][1U]; + __Vtemp541[2U] = vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__tag_data_access__DOT__read_data_st1c + [0U][2U]; + __Vtemp541[3U] = vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__tag_data_access__DOT__read_data_st1c + [0U][3U]; + vcdp->fullArray(c+2857,(__Vtemp541),128); + vcdp->fullBus(c+2889,(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__tag_data_access__DOT__read_tag_st1c + [0U]),20); + vcdp->fullBit(c+2897,(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__miss_st1e)); + vcdp->fullBit(c+2905,(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__dirty_st1e)); + vcdp->fullBus(c+2913,(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__tag_data_access__DOT__read_dirtyb_st1c + [0U]),16); + vcdp->fullQuad(c+2921,((VL_ULL(0x3ffffffffff) + & (vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__inst_meta_st1 + [0U] >> 7U))),42); + vcdp->fullBus(c+2937,((3U & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__inst_meta_st1 + [0U]))),2); + vcdp->fullBit(c+2945,((1U & (IData)((vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__inst_meta_st1 + [0U] >> 6U))))); + vcdp->fullBus(c+2953,((0xfU & (IData)((vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__inst_meta_st1 + [0U] + >> 2U)))),4); + vcdp->fullBit(c+2961,(((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__tag_data_access__DOT__real_writefill) + & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__dirty_st1e)))); + vcdp->fullBit(c+2969,(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__is_snp_st1 + [0U])); + vcdp->fullBit(c+2977,(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__snp_invalidate_st1 + [0U])); + vcdp->fullBit(c+2985,(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__snp_to_mrvq_st1e)); + vcdp->fullBit(c+2993,(((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__snp_to_mrvq_st1e) + | ((((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__force_request_miss_st1e) + & (~ vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__is_snp_st1 + [0U])) & (~ + vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__is_fill_st1 + [0U])) + & vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__valid_st1 + [0U])))); + vcdp->fullBit(c+3001,(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__miss_add_because_miss)); + vcdp->fullBit(c+3009,(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__valid_st1 + [0U])); + vcdp->fullBit(c+3017,(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__is_mrvq_st1 + [0U])); + vcdp->fullBit(c+3025,((((vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__valid_st1 + [0U] & vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__is_mrvq_st1 + [0U]) & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__recover_mrvq_state_st2)) + & ((0x3ffffffU & ((vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__st_1e_2__DOT__value[9U] + << 7U) + | (vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__st_1e_2__DOT__value[8U] + >> 0x19U))) + == vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__addr_st1 + [0U])))); + vcdp->fullBus(c+3033,(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__addr_st1 + [0U]),26); + vcdp->fullBit(c+3041,((vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__valid_st1 + [0U] & (~ vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__is_fill_st1 + [0U])))); + vcdp->fullBit(c+3049,(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__mrvq_init_ready_state_st2)); + vcdp->fullBit(c+3057,((((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__miss_add_unqual) + & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__dfpq_pop_unqual)) + & ((0x3ffffffU & ((vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__st_1e_2__DOT__value[9U] + << 7U) + | (vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__st_1e_2__DOT__value[8U] + >> 0x19U))) + == (0x3ffffffU & + vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT____Vcellout__dfp_queue__data_out[4U]))))); + vcdp->fullBit(c+3065,((((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__miss_add_unqual) + & vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__is_fill_st1 + [0U]) & ((0x3ffffffU + & ((vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__st_1e_2__DOT__value[9U] + << 7U) + | (vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__st_1e_2__DOT__value[8U] + >> 0x19U))) + == vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__addr_st1 + [0U])))); + vcdp->fullBit(c+3073,(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__miss_add_unqual)); + vcdp->fullBit(c+3081,(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__miss_add)); + vcdp->fullBit(c+3089,(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__miss_add_is_mrvq)); + vcdp->fullBit(c+3097,(((((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cwbq_push_unqual) + & (~ (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cwb_queue__DOT__genblk3__DOT__genblk2__DOT__full_r))) + & (~ (vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__st_1e_2__DOT__value[0U] + >> 6U))) & (~ + (((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__dwbq_push_stall) + | (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__mrvq_push_stall)) + | (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__dram_fill_req_stall)))))); + vcdp->fullBit(c+3105,(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cwbq_push_unqual)); + vcdp->fullBit(c+3113,(((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__miss_add_unqual) + & ((~ (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__mrvq_init_ready_state_st2)) + | ((vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__st_1e_2__DOT__value[9U] + >> 0x1aU) & (~ + (vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__st_1e_2__DOT__value[9U] + >> 0x1bU))))))); + vcdp->fullBit(c+3121,((((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__dwbq_push_unqual) + & (~ (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__genblk2__DOT__full_r))) + & (~ (((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cwbq_push_stall) + | (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__mrvq_push_stall)) + | (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__dram_fill_req_stall)))))); + vcdp->fullBit(c+3129,(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__dwbq_is_dwb_in)); + vcdp->fullBit(c+3137,(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__dwbq_is_snp_in)); + vcdp->fullBit(c+3145,((1U & (vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT____Vcellout__dwb_queue__data_out[6U] + >> 7U)))); + vcdp->fullBit(c+3153,((1U & (vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT____Vcellout__dwb_queue__data_out[6U] + >> 6U)))); + vcdp->fullBit(c+3161,(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__dwbq_push_unqual)); + vcdp->fullQuad(c+3169,(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT____Vcellout__snp_req_queue__data_out),55); + vcdp->fullBit(c+3185,(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__snp_req_queue__DOT__reading)); + vcdp->fullArray(c+3193,(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT____Vcellout__dfp_queue__data_out),154); + vcdp->fullBit(c+3233,(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__dfp_queue__DOT__reading)); + vcdp->fullBus(c+3241,((0xfU & (vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__core_req_arb__DOT____Vcellout__reqq_queue__data_out[9U] + >> 0x16U))),4); + vcdp->fullBus(c+3249,((0xfU & (vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__core_req_arb__DOT____Vcellout__reqq_queue__data_out[9U] + >> 0x12U))),4); + vcdp->fullBus(c+3257,((0xffffU & (vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__core_req_arb__DOT____Vcellout__reqq_queue__data_out[9U] + >> 2U))),16); + __Vtemp544[0U] = ((vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__core_req_arb__DOT____Vcellout__reqq_queue__data_out[6U] + << 0x16U) | (vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__core_req_arb__DOT____Vcellout__reqq_queue__data_out[5U] + >> 0xaU)); + __Vtemp544[1U] = ((vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__core_req_arb__DOT____Vcellout__reqq_queue__data_out[7U] + << 0x16U) | (vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__core_req_arb__DOT____Vcellout__reqq_queue__data_out[6U] + >> 0xaU)); + __Vtemp544[2U] = ((vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__core_req_arb__DOT____Vcellout__reqq_queue__data_out[8U] + << 0x16U) | (vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__core_req_arb__DOT____Vcellout__reqq_queue__data_out[7U] + >> 0xaU)); + __Vtemp544[3U] = (0xffffffU & ((vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__core_req_arb__DOT____Vcellout__reqq_queue__data_out[9U] + << 0x16U) | + (vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__core_req_arb__DOT____Vcellout__reqq_queue__data_out[8U] + >> 0xaU))); + vcdp->fullArray(c+3265,(__Vtemp544),120); + __Vtemp545[0U] = ((vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__core_req_arb__DOT____Vcellout__reqq_queue__data_out[2U] + << 0x16U) | (vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__core_req_arb__DOT____Vcellout__reqq_queue__data_out[1U] + >> 0xaU)); + __Vtemp545[1U] = ((vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__core_req_arb__DOT____Vcellout__reqq_queue__data_out[3U] + << 0x16U) | (vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__core_req_arb__DOT____Vcellout__reqq_queue__data_out[2U] + >> 0xaU)); + __Vtemp545[2U] = ((vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__core_req_arb__DOT____Vcellout__reqq_queue__data_out[4U] + << 0x16U) | (vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__core_req_arb__DOT____Vcellout__reqq_queue__data_out[3U] + >> 0xaU)); + __Vtemp545[3U] = ((vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__core_req_arb__DOT____Vcellout__reqq_queue__data_out[5U] + << 0x16U) | (vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__core_req_arb__DOT____Vcellout__reqq_queue__data_out[4U] + >> 0xaU)); + vcdp->fullArray(c+3297,(__Vtemp545),128); + vcdp->fullQuad(c+3329,((VL_ULL(0x3ffffffffff) + & (((QData)((IData)( + vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__core_req_arb__DOT____Vcellout__reqq_queue__data_out[1U])) + << 0x20U) | (QData)((IData)( + vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__core_req_arb__DOT____Vcellout__reqq_queue__data_out[0U]))))),42); + vcdp->fullBit(c+3345,(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__core_req_arb__DOT__out_empty)); + vcdp->fullBit(c+3353,(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__core_req_arb__DOT__pop_qual)); + vcdp->fullBus(c+3361,((0xfU & ((vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__core_req_arb__DOT____Vcellout__reqq_queue__data_out[9U] + >> 0x16U) & + VL_NEGATE_I((IData)( + (1U + & (~ (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__core_req_arb__DOT__out_empty)))))))),4); + vcdp->fullArray(c+3369,(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__core_req_arb__DOT____Vcellout__reqq_queue__data_out),314); + vcdp->fullBit(c+3449,(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__reading)); + vcdp->fullBus(c+3457,(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__core_req_arb__DOT__sel_bank__DOT__genblk2__DOT__grant_onehot_r),4); + vcdp->fullBus(c+3465,(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__core_req_arb__DOT__sel_bank__DOT__genblk2__DOT__priority_encoder__DOT__i),32); + vcdp->fullArray(c+3473,(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT____Vcellinp__s0_1_c0__in),243); + vcdp->fullBus(c+3537,((0x3fU & vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__addr_st1 + [0U])),6); + vcdp->fullBit(c+3545,(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__is_fill_st1 + [0U])); + vcdp->fullBus(c+3553,(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__writeword_st1 + [0U]),32); + __Vtemp546[0U] = vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__writedata_st1 + [0U][0U]; + __Vtemp546[1U] = vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__writedata_st1 + [0U][1U]; + __Vtemp546[2U] = vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__writedata_st1 + [0U][2U]; + __Vtemp546[3U] = vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__writedata_st1 + [0U][3U]; + vcdp->fullArray(c+3561,(__Vtemp546),128); + vcdp->fullBus(c+3593,(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__wsel_st1 + [0U]),2); + vcdp->fullBit(c+3601,(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__tag_data_access__DOT__read_valid_st1c[0])); + vcdp->fullBit(c+3609,(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__tag_data_access__DOT__read_dirty_st1c[0])); + vcdp->fullBus(c+3617,(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__tag_data_access__DOT__read_dirtyb_st1c[0]),16); + vcdp->fullBus(c+3625,(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__tag_data_access__DOT__read_tag_st1c[0]),20); + vcdp->fullArray(c+3633,(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__tag_data_access__DOT__read_data_st1c[0]),128); + vcdp->fullBit(c+3665,((1U & (IData)((vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__valid + >> (0x3fU + & vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__addr_st1 + [0U])))))); + vcdp->fullBit(c+3673,((1U & (IData)((vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__dirty + >> (0x3fU + & vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__addr_st1 + [0U])))))); + vcdp->fullBus(c+3681,(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__dirtyb + [(0x3fU & vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__addr_st1 + [0U])]),16); + vcdp->fullBus(c+3689,(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__tag + [(0x3fU & vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__addr_st1 + [0U])]),20); + __Vtemp547[0U] = vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__data + [(0x3fU & vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__addr_st1 + [0U])][0U]; + __Vtemp547[1U] = vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__data + [(0x3fU & vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__addr_st1 + [0U])][1U]; + __Vtemp547[2U] = vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__data + [(0x3fU & vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__addr_st1 + [0U])][2U]; + __Vtemp547[3U] = vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__data + [(0x3fU & vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__addr_st1 + [0U])][3U]; + vcdp->fullArray(c+3697,(__Vtemp547),128); + vcdp->fullBit(c+3729,(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__tag_data_access__DOT__read_valid_st1c + [0U])); + vcdp->fullBit(c+3737,(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__tag_data_access__DOT__read_dirty_st1c + [0U])); + vcdp->fullBus(c+3745,(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__tag_data_access__DOT__use_write_enable),16); + vcdp->fullArray(c+3753,(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__tag_data_access__DOT__data_write),128); + vcdp->fullBit(c+3785,(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__tag_data_access__DOT__snoop_hit_no_pending)); + vcdp->fullBit(c+3793,(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__tag_data_access__DOT__tags_match)); + vcdp->fullBit(c+3801,(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__tag_data_access__DOT__real_writefill)); + vcdp->fullBus(c+3809,((0xfffffU & (vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__addr_st1 + [0U] >> 6U))),20); + vcdp->fullBus(c+3817,(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__tag_data_access__DOT__we),16); + vcdp->fullBit(c+3825,(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__tag_data_access__DOT__should_write)); + vcdp->fullBit(c+3833,((((vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__valid_st1 + [0U] & (~ vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__is_snp_st1 + [0U])) & (~ + vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__tag_data_access__DOT__read_valid_st1c + [0U])) + & (~ vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__is_fill_st1 + [0U])))); + vcdp->fullBit(c+3841,(((((vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__valid_st1 + [0U] & (~ vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__is_snp_st1 + [0U])) & + vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__tag_data_access__DOT__read_valid_st1c + [0U]) & (~ vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__is_fill_st1 + [0U])) & + (~ (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__tag_data_access__DOT__tags_match))))); + vcdp->fullBit(c+3849,(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__tag_data_access__DOT__real_miss)); + vcdp->fullBit(c+3857,((((((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__force_request_miss_st1e) + & (~ vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__is_snp_st1 + [0U])) & (~ vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__is_fill_st1 + [0U])) + & vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__valid_st1 + [0U]) & (~ (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__tag_data_access__DOT__real_miss))))); + vcdp->fullBit(c+3865,(((0U == vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__wsel_st1 + [0U]) & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__tag_data_access__DOT__should_write)))); + vcdp->fullBit(c+3873,(((1U == vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__wsel_st1 + [0U]) & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__tag_data_access__DOT__should_write)))); + vcdp->fullBit(c+3881,(((2U == vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__wsel_st1 + [0U]) & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__tag_data_access__DOT__should_write)))); + vcdp->fullBit(c+3889,(((3U == vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__wsel_st1 + [0U]) & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__tag_data_access__DOT__should_write)))); + vcdp->fullBit(c+3897,((0U != (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__tag_data_access__DOT__use_write_enable)))); + vcdp->fullArray(c+3905,(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__tag_data_access__DOT____Vcellinp__s0_1_c0__in),166); + vcdp->fullArray(c+3953,(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT____Vcellinp__st_1e_2__in),316); + vcdp->fullBus(c+4033,(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cache_miss_resrv__DOT__make_ready),16); + vcdp->fullBus(c+4041,((0xffffU & (((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cache_miss_resrv__DOT__mrvq_push) + & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__mrvq_init_ready_state_st2)) + << (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cache_miss_resrv__DOT__tail_ptr)))),16); + vcdp->fullBus(c+4049,(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cache_miss_resrv__DOT__valid_address_match),16); + vcdp->fullBit(c+4057,(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cache_miss_resrv__DOT__mrvq_push)); + vcdp->fullBit(c+4065,(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cache_miss_resrv__DOT__mrvq_pop)); + vcdp->fullBit(c+4073,(((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__miss_add) + & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__miss_add_is_mrvq)))); + vcdp->fullBit(c+4081,(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cache_miss_resrv__DOT__increment_head)); + vcdp->fullBit(c+4089,((0U != (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cache_miss_resrv__DOT__make_ready)))); + vcdp->fullBit(c+4097,(((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cache_miss_resrv__DOT__mrvq_push) + & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__mrvq_init_ready_state_st2)))); + vcdp->fullArray(c+4105,(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT____Vcellinp__cwb_queue__data_in),76); + vcdp->fullArray(c+4129,(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT____Vcellout__cwb_queue__data_out),76); + vcdp->fullBit(c+4153,(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cwb_queue__DOT__writing)); + vcdp->fullArray(c+4161,(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT____Vcellinp__dwb_queue__data_in),200); + vcdp->fullArray(c+4217,(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT____Vcellout__dwb_queue__data_out),200); + vcdp->fullBit(c+4273,(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__dwb_queue__DOT__writing)); + vcdp->fullBit(c+4281,(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__snrq_pop)); + vcdp->fullBus(c+4289,((0x3ffffffU & (IData)( + (vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT____Vcellout__snp_req_queue__data_out + >> 0x1dU)))),26); + vcdp->fullBit(c+4297,((1U & (IData)((vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT____Vcellout__snp_req_queue__data_out + >> 0x1cU))))); + vcdp->fullBus(c+4305,((0xfffffffU & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT____Vcellout__snp_req_queue__data_out))),28); + vcdp->fullBit(c+4313,(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__dfpq_pop)); + vcdp->fullBus(c+4321,((0x3ffffffU & vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT____Vcellout__dfp_queue__data_out[4U])),26); + __Vtemp548[0U] = vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT____Vcellout__dfp_queue__data_out[0U]; + __Vtemp548[1U] = vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT____Vcellout__dfp_queue__data_out[1U]; + __Vtemp548[2U] = vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT____Vcellout__dfp_queue__data_out[2U]; + __Vtemp548[3U] = vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT____Vcellout__dfp_queue__data_out[3U]; + vcdp->fullArray(c+4329,(__Vtemp548),128); + vcdp->fullBit(c+4361,(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__reqq_pop)); + vcdp->fullBit(c+4369,((1U & (~ (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__core_req_arb__DOT__qual_has_request))))); + vcdp->fullBit(c+4377,(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__core_req_arb__DOT__qual_has_request)); + vcdp->fullBus(c+4385,(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__core_req_arb__DOT__qual_request_index),2); + vcdp->fullBit(c+4393,(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__reqq_req_rw_st0)); + vcdp->fullBus(c+4401,((0xfU & ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__core_req_arb__DOT__use_per_byteen) + >> (0xfU & ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__core_req_arb__DOT__qual_request_index) + << 2U))))),4); + vcdp->fullBus(c+4409,(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__reqq_req_addr_st0),30); + vcdp->fullBus(c+4417,((((0U == (0x1fU & ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__core_req_arb__DOT__qual_request_index) + << 5U))) + ? 0U : (vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__core_req_arb__DOT__use_per_writedata[ + ((IData)(1U) + + (3U & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__core_req_arb__DOT__qual_request_index)))] + << ((IData)(0x20U) + - (0x1fU + & ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__core_req_arb__DOT__qual_request_index) + << 5U))))) + | (vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__core_req_arb__DOT__use_per_writedata[ + (3U & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__core_req_arb__DOT__qual_request_index))] + >> (0x1fU & ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__core_req_arb__DOT__qual_request_index) + << 5U))))),32); + vcdp->fullBit(c+4425,(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__mrvq_pop)); + vcdp->fullBit(c+4433,(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__cache_miss_resrv__DOT__dequeue_possible)); + vcdp->fullBit(c+4441,(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__mrvq_rw_st0)); + vcdp->fullBit(c+4449,((0U != (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__cache_miss_resrv__DOT__valid_address_match)))); + vcdp->fullBit(c+4457,(((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__miss_add_because_miss) + & (((0x3ffffffU & (( + vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__st_1e_2__DOT__value[9U] + << 7U) + | (vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__st_1e_2__DOT__value[8U] + >> 0x19U))) + == vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__addr_st1 + [0U]) & (~ (vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__st_1e_2__DOT__value[9U] + >> 0x14U)))))); + vcdp->fullBit(c+4465,(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__force_request_miss_st1e)); + vcdp->fullBit(c+4473,(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__recover_mrvq_state_st2)); + vcdp->fullBit(c+4481,(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__mrvq_push_stall)); + vcdp->fullBit(c+4489,(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__cwbq_push_stall)); + vcdp->fullBit(c+4497,(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__dwbq_push_stall)); + vcdp->fullBit(c+4505,(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__dram_fill_req_stall)); + vcdp->fullBit(c+4513,(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__stall_bank_pipe)); + vcdp->fullBit(c+4521,(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__is_fill_in_pipe)); + vcdp->fullBit(c+4529,(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__is_fill_st1[0])); + vcdp->fullBit(c+4537,(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__going_to_write_st1[0])); + vcdp->fullBit(c+4545,(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__dfpq_pop_unqual)); + vcdp->fullBit(c+4553,(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__reqq_pop_unqual)); + vcdp->fullBit(c+4561,(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__snrq_pop_unqual)); + vcdp->fullBit(c+4569,(((((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__dfpq_pop) + | (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__mrvq_pop)) + | (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__reqq_pop)) + | (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__snrq_pop)))); + vcdp->fullBus(c+4577,((0x3ffffffU & ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__dfpq_pop_unqual) + ? (0x3ffffffU + & vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT____Vcellout__dfp_queue__data_out[4U]) + : ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__cache_miss_resrv__DOT__dequeue_possible) + ? + ((0x19fU + >= + (0x1ffU + & ((IData)(0x1aU) + * (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr)))) + ? + (0x3ffffffU + & (((0U + == + (0x1fU + & ((IData)(0x1aU) + * (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr)))) + ? 0U + : + (vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__cache_miss_resrv__DOT__addr_table[ + ((IData)(1U) + + + (0xfU + & (((IData)(0x1aU) + * (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr)) + >> 5U)))] + << + ((IData)(0x20U) + - + (0x1fU + & ((IData)(0x1aU) + * (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr)))))) + | (vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__cache_miss_resrv__DOT__addr_table[ + (0xfU + & (((IData)(0x1aU) + * (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr)) + >> 5U))] + >> + (0x1fU + & ((IData)(0x1aU) + * (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr)))))) + : 0U) + : + ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__reqq_pop_unqual) + ? + (0x3ffffffU + & (vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__reqq_req_addr_st0 + >> 4U)) + : + ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__snrq_pop_unqual) + ? + (0x3ffffffU + & (IData)( + (vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT____Vcellout__snp_req_queue__data_out + >> 0x1dU))) + : 0U)))))),26); + vcdp->fullBus(c+4585,((3U & ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__reqq_pop_unqual) + ? (3U & vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__reqq_req_addr_st0) + : ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__cache_miss_resrv__DOT__dequeue_possible) + ? (3U & ( + (vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__cache_miss_resrv__DOT__metadata_table + [vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr][1U] + << 0x1eU) + | (vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__cache_miss_resrv__DOT__metadata_table + [vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr][0U] + >> 2U))) + : 0U)))),2); + vcdp->fullBus(c+4593,(((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__cache_miss_resrv__DOT__dequeue_possible) + ? ((vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__cache_miss_resrv__DOT__metadata_table + [vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr][2U] + << 0xbU) | (vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__cache_miss_resrv__DOT__metadata_table + [vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr][1U] + >> 0x15U)) + : ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__reqq_pop_unqual) + ? (((0U == (0x1fU + & ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__core_req_arb__DOT__qual_request_index) + << 5U))) + ? 0U : (vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__core_req_arb__DOT__use_per_writedata[ + ((IData)(1U) + + + (3U + & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__core_req_arb__DOT__qual_request_index)))] + << + ((IData)(0x20U) + - + (0x1fU + & ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__core_req_arb__DOT__qual_request_index) + << 5U))))) + | (vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__core_req_arb__DOT__use_per_writedata[ + (3U & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__core_req_arb__DOT__qual_request_index))] + >> (0x1fU + & ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__core_req_arb__DOT__qual_request_index) + << 5U)))) + : 0U))),32); + __Vtemp553[0U] = ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__dfpq_pop_unqual) + ? vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT____Vcellout__dfp_queue__data_out[0U] + : 0x39U); + __Vtemp553[1U] = ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__dfpq_pop_unqual) + ? vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT____Vcellout__dfp_queue__data_out[1U] + : 0U); + __Vtemp553[2U] = ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__dfpq_pop_unqual) + ? vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT____Vcellout__dfp_queue__data_out[2U] + : 0U); + __Vtemp553[3U] = ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__dfpq_pop_unqual) + ? vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT____Vcellout__dfp_queue__data_out[3U] + : 0U); + vcdp->fullArray(c+4601,(__Vtemp553),128); + vcdp->fullQuad(c+4633,(((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__cache_miss_resrv__DOT__dequeue_possible) + ? ((VL_ULL(0x1ffffffffff80) + & (((QData)((IData)( + vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__cache_miss_resrv__DOT__metadata_table + [vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr][2U])) + << 0x3eU) + | (((QData)((IData)( + vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__cache_miss_resrv__DOT__metadata_table + [vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr][1U])) + << 0x1eU) + | (VL_ULL(0x3fffffffffffff80) + & ((QData)((IData)( + vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__cache_miss_resrv__DOT__metadata_table + [vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr][0U])) + >> 2U))))) + | (QData)((IData)( + (((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__mrvq_rw_st0) + << 6U) + | ((0x3cU + & ((vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__cache_miss_resrv__DOT__metadata_table + [vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr][1U] + << 0x1eU) + | (0x3ffffffcU + & (vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__cache_miss_resrv__DOT__metadata_table + [vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr][0U] + >> 2U)))) + | (3U + & ((vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__cache_miss_resrv__DOT__metadata_table + [vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr][2U] + << 0xdU) + | (vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__cache_miss_resrv__DOT__metadata_table + [vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr][1U] + >> 0x13U)))))))) + : ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__reqq_pop_unqual) + ? ((vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__core_req_arb__DOT__use_per_tag + << 7U) | (QData)((IData)( + (((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__reqq_req_rw_st0) + << 6U) + | ((0x3cU + & (((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__core_req_arb__DOT__use_per_byteen) + >> + (0xfU + & ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__core_req_arb__DOT__qual_request_index) + << 2U))) + << 2U)) + | (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__core_req_arb__DOT__qual_request_index)))))) + : ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__snrq_pop_unqual) + ? ((QData)((IData)( + (0xfffffffU + & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT____Vcellout__snp_req_queue__data_out)))) + << 7U) : VL_ULL(0))))),49); + vcdp->fullBit(c+4649,(((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__dfpq_pop_unqual) + ? 1U : (((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__cache_miss_resrv__DOT__dequeue_possible) + & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__mrvq_rw_st0)) + ? 1U : (((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__reqq_pop_unqual) + & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__reqq_req_rw_st0)) + ? 1U + : 0U))))); + vcdp->fullBit(c+4657,((1U & ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__cache_miss_resrv__DOT__dequeue_possible) + ? (1U & (vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__cache_miss_resrv__DOT__metadata_table + [vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr][0U] + >> 1U)) + : ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__snrq_pop_unqual) + ? 1U : 0U))))); + vcdp->fullBit(c+4665,((1U & ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__cache_miss_resrv__DOT__dequeue_possible) + ? (1U & vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__cache_miss_resrv__DOT__metadata_table + [vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr][0U]) + : ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__snrq_pop_unqual) + ? (1U & (IData)( + (vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT____Vcellout__snp_req_queue__data_out + >> 0x1cU))) + : 0U))))); + vcdp->fullBit(c+4673,(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__valid_st1[0])); + vcdp->fullBus(c+4681,(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__addr_st1[0]),26); + vcdp->fullBus(c+4689,(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__wsel_st1[0]),2); + vcdp->fullBus(c+4697,(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__writeword_st1[0]),32); + vcdp->fullQuad(c+4705,(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__inst_meta_st1[0]),49); + vcdp->fullArray(c+4721,(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__writedata_st1[0]),128); + vcdp->fullBit(c+4753,(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__is_snp_st1[0])); + vcdp->fullBit(c+4761,(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__snp_invalidate_st1[0])); + vcdp->fullBit(c+4769,(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__is_mrvq_st1[0])); + __Vtemp559[0U] = vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__tag_data_access__DOT__read_data_st1c + [0U][0U]; + __Vtemp559[1U] = vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__tag_data_access__DOT__read_data_st1c + [0U][1U]; + __Vtemp559[2U] = vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__tag_data_access__DOT__read_data_st1c + [0U][2U]; + __Vtemp559[3U] = vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__tag_data_access__DOT__read_data_st1c + [0U][3U]; + vcdp->fullBus(c+4777,((((0U == (0x1fU & (vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__wsel_st1 + [0U] + << 5U))) + ? 0U : (__Vtemp559[ + ((IData)(1U) + + (3U & vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__wsel_st1 + [0U]))] + << ((IData)(0x20U) + - (0x1fU + & (vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__wsel_st1 + [0U] + << 5U))))) + | (__Vtemp559[(3U & + vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__wsel_st1 + [0U])] + >> (0x1fU & (vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__wsel_st1 + [0U] + << 5U))))),32); + __Vtemp560[0U] = vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__tag_data_access__DOT__read_data_st1c + [0U][0U]; + __Vtemp560[1U] = vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__tag_data_access__DOT__read_data_st1c + [0U][1U]; + __Vtemp560[2U] = vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__tag_data_access__DOT__read_data_st1c + [0U][2U]; + __Vtemp560[3U] = vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__tag_data_access__DOT__read_data_st1c + [0U][3U]; + vcdp->fullArray(c+4785,(__Vtemp560),128); + vcdp->fullBus(c+4817,(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__tag_data_access__DOT__read_tag_st1c + [0U]),20); + vcdp->fullBit(c+4825,(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__miss_st1e)); + vcdp->fullBit(c+4833,(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__dirty_st1e)); + vcdp->fullBus(c+4841,(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__tag_data_access__DOT__read_dirtyb_st1c + [0U]),16); + vcdp->fullQuad(c+4849,((VL_ULL(0x3ffffffffff) + & (vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__inst_meta_st1 + [0U] >> 7U))),42); + vcdp->fullBus(c+4865,((3U & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__inst_meta_st1 + [0U]))),2); + vcdp->fullBit(c+4873,((1U & (IData)((vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__inst_meta_st1 + [0U] >> 6U))))); + vcdp->fullBus(c+4881,((0xfU & (IData)((vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__inst_meta_st1 + [0U] + >> 2U)))),4); + vcdp->fullBit(c+4889,(((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__tag_data_access__DOT__real_writefill) + & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__dirty_st1e)))); + vcdp->fullBit(c+4897,(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__is_snp_st1 + [0U])); + vcdp->fullBit(c+4905,(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__snp_invalidate_st1 + [0U])); + vcdp->fullBit(c+4913,(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__snp_to_mrvq_st1e)); + vcdp->fullBit(c+4921,(((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__snp_to_mrvq_st1e) + | ((((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__force_request_miss_st1e) + & (~ vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__is_snp_st1 + [0U])) & (~ + vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__is_fill_st1 + [0U])) + & vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__valid_st1 + [0U])))); + vcdp->fullBit(c+4929,(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__miss_add_because_miss)); + vcdp->fullBit(c+4937,(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__valid_st1 + [0U])); + vcdp->fullBit(c+4945,(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__is_mrvq_st1 + [0U])); + vcdp->fullBit(c+4953,((((vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__valid_st1 + [0U] & vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__is_mrvq_st1 + [0U]) & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__recover_mrvq_state_st2)) + & ((0x3ffffffU & ((vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__st_1e_2__DOT__value[9U] + << 7U) + | (vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__st_1e_2__DOT__value[8U] + >> 0x19U))) + == vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__addr_st1 + [0U])))); + vcdp->fullBus(c+4961,(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__addr_st1 + [0U]),26); + vcdp->fullBit(c+4969,((vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__valid_st1 + [0U] & (~ vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__is_fill_st1 + [0U])))); + vcdp->fullBit(c+4977,(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__mrvq_init_ready_state_st2)); + vcdp->fullBit(c+4985,((((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__miss_add_unqual) + & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__dfpq_pop_unqual)) + & ((0x3ffffffU & ((vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__st_1e_2__DOT__value[9U] + << 7U) + | (vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__st_1e_2__DOT__value[8U] + >> 0x19U))) + == (0x3ffffffU & + vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT____Vcellout__dfp_queue__data_out[4U]))))); + vcdp->fullBit(c+4993,((((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__miss_add_unqual) + & vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__is_fill_st1 + [0U]) & ((0x3ffffffU + & ((vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__st_1e_2__DOT__value[9U] + << 7U) + | (vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__st_1e_2__DOT__value[8U] + >> 0x19U))) + == vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__addr_st1 + [0U])))); + vcdp->fullBit(c+5001,(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__miss_add_unqual)); + vcdp->fullBit(c+5009,(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__miss_add)); + vcdp->fullBit(c+5017,(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__miss_add_is_mrvq)); + vcdp->fullBit(c+5025,(((((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__cwbq_push_unqual) + & (~ (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__cwb_queue__DOT__genblk3__DOT__genblk2__DOT__full_r))) + & (~ (vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__st_1e_2__DOT__value[0U] + >> 6U))) & (~ + (((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__dwbq_push_stall) + | (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__mrvq_push_stall)) + | (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__dram_fill_req_stall)))))); + vcdp->fullBit(c+5033,(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__cwbq_push_unqual)); + vcdp->fullBit(c+5041,(((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__miss_add_unqual) + & ((~ (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__mrvq_init_ready_state_st2)) + | ((vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__st_1e_2__DOT__value[9U] + >> 0x1aU) & (~ + (vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__st_1e_2__DOT__value[9U] + >> 0x1bU))))))); + vcdp->fullBit(c+5049,((((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__dwbq_push_unqual) + & (~ (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__genblk2__DOT__full_r))) + & (~ (((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__cwbq_push_stall) + | (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__mrvq_push_stall)) + | (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__dram_fill_req_stall)))))); + vcdp->fullBit(c+5057,(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__dwbq_is_dwb_in)); + vcdp->fullBit(c+5065,(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__dwbq_is_snp_in)); + vcdp->fullBit(c+5073,((1U & (vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT____Vcellout__dwb_queue__data_out[6U] + >> 7U)))); + vcdp->fullBit(c+5081,((1U & (vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT____Vcellout__dwb_queue__data_out[6U] + >> 6U)))); + vcdp->fullBit(c+5089,(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__dwbq_push_unqual)); + vcdp->fullQuad(c+5097,(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT____Vcellout__snp_req_queue__data_out),55); + vcdp->fullBit(c+5113,(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__snp_req_queue__DOT__reading)); + vcdp->fullArray(c+5121,(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT____Vcellout__dfp_queue__data_out),154); + vcdp->fullBit(c+5161,(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__dfp_queue__DOT__reading)); + vcdp->fullBus(c+5169,((0xfU & (vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__core_req_arb__DOT____Vcellout__reqq_queue__data_out[9U] + >> 0x16U))),4); + vcdp->fullBus(c+5177,((0xfU & (vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__core_req_arb__DOT____Vcellout__reqq_queue__data_out[9U] + >> 0x12U))),4); + vcdp->fullBus(c+5185,((0xffffU & (vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__core_req_arb__DOT____Vcellout__reqq_queue__data_out[9U] + >> 2U))),16); + __Vtemp563[0U] = ((vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__core_req_arb__DOT____Vcellout__reqq_queue__data_out[6U] + << 0x16U) | (vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__core_req_arb__DOT____Vcellout__reqq_queue__data_out[5U] + >> 0xaU)); + __Vtemp563[1U] = ((vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__core_req_arb__DOT____Vcellout__reqq_queue__data_out[7U] + << 0x16U) | (vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__core_req_arb__DOT____Vcellout__reqq_queue__data_out[6U] + >> 0xaU)); + __Vtemp563[2U] = ((vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__core_req_arb__DOT____Vcellout__reqq_queue__data_out[8U] + << 0x16U) | (vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__core_req_arb__DOT____Vcellout__reqq_queue__data_out[7U] + >> 0xaU)); + __Vtemp563[3U] = (0xffffffU & ((vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__core_req_arb__DOT____Vcellout__reqq_queue__data_out[9U] + << 0x16U) | + (vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__core_req_arb__DOT____Vcellout__reqq_queue__data_out[8U] + >> 0xaU))); + vcdp->fullArray(c+5193,(__Vtemp563),120); + __Vtemp564[0U] = ((vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__core_req_arb__DOT____Vcellout__reqq_queue__data_out[2U] + << 0x16U) | (vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__core_req_arb__DOT____Vcellout__reqq_queue__data_out[1U] + >> 0xaU)); + __Vtemp564[1U] = ((vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__core_req_arb__DOT____Vcellout__reqq_queue__data_out[3U] + << 0x16U) | (vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__core_req_arb__DOT____Vcellout__reqq_queue__data_out[2U] + >> 0xaU)); + __Vtemp564[2U] = ((vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__core_req_arb__DOT____Vcellout__reqq_queue__data_out[4U] + << 0x16U) | (vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__core_req_arb__DOT____Vcellout__reqq_queue__data_out[3U] + >> 0xaU)); + __Vtemp564[3U] = ((vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__core_req_arb__DOT____Vcellout__reqq_queue__data_out[5U] + << 0x16U) | (vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__core_req_arb__DOT____Vcellout__reqq_queue__data_out[4U] + >> 0xaU)); + vcdp->fullArray(c+5225,(__Vtemp564),128); + vcdp->fullQuad(c+5257,((VL_ULL(0x3ffffffffff) + & (((QData)((IData)( + vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__core_req_arb__DOT____Vcellout__reqq_queue__data_out[1U])) + << 0x20U) | (QData)((IData)( + vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__core_req_arb__DOT____Vcellout__reqq_queue__data_out[0U]))))),42); + vcdp->fullBit(c+5273,(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__core_req_arb__DOT__out_empty)); + vcdp->fullBit(c+5281,(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__core_req_arb__DOT__pop_qual)); + vcdp->fullBus(c+5289,((0xfU & ((vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__core_req_arb__DOT____Vcellout__reqq_queue__data_out[9U] + >> 0x16U) & + VL_NEGATE_I((IData)( + (1U + & (~ (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__core_req_arb__DOT__out_empty)))))))),4); + vcdp->fullArray(c+5297,(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__core_req_arb__DOT____Vcellout__reqq_queue__data_out),314); + vcdp->fullBit(c+5377,(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__reading)); + vcdp->fullBus(c+5385,(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__core_req_arb__DOT__sel_bank__DOT__genblk2__DOT__grant_onehot_r),4); + vcdp->fullBus(c+5393,(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__core_req_arb__DOT__sel_bank__DOT__genblk2__DOT__priority_encoder__DOT__i),32); + vcdp->fullArray(c+5401,(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT____Vcellinp__s0_1_c0__in),243); + vcdp->fullBus(c+5465,((0x3fU & vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__addr_st1 + [0U])),6); + vcdp->fullBit(c+5473,(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__is_fill_st1 + [0U])); + vcdp->fullBus(c+5481,(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__writeword_st1 + [0U]),32); + __Vtemp565[0U] = vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__writedata_st1 + [0U][0U]; + __Vtemp565[1U] = vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__writedata_st1 + [0U][1U]; + __Vtemp565[2U] = vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__writedata_st1 + [0U][2U]; + __Vtemp565[3U] = vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__writedata_st1 + [0U][3U]; + vcdp->fullArray(c+5489,(__Vtemp565),128); + vcdp->fullBus(c+5521,(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__wsel_st1 + [0U]),2); + vcdp->fullBit(c+5529,(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__tag_data_access__DOT__read_valid_st1c[0])); + vcdp->fullBit(c+5537,(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__tag_data_access__DOT__read_dirty_st1c[0])); + vcdp->fullBus(c+5545,(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__tag_data_access__DOT__read_dirtyb_st1c[0]),16); + vcdp->fullBus(c+5553,(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__tag_data_access__DOT__read_tag_st1c[0]),20); + vcdp->fullArray(c+5561,(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__tag_data_access__DOT__read_data_st1c[0]),128); + vcdp->fullBit(c+5593,((1U & (IData)((vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__valid + >> (0x3fU + & vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__addr_st1 + [0U])))))); + vcdp->fullBit(c+5601,((1U & (IData)((vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__dirty + >> (0x3fU + & vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__addr_st1 + [0U])))))); + vcdp->fullBus(c+5609,(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__dirtyb + [(0x3fU & vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__addr_st1 + [0U])]),16); + vcdp->fullBus(c+5617,(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__tag + [(0x3fU & vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__addr_st1 + [0U])]),20); + __Vtemp566[0U] = vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__data + [(0x3fU & vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__addr_st1 + [0U])][0U]; + __Vtemp566[1U] = vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__data + [(0x3fU & vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__addr_st1 + [0U])][1U]; + __Vtemp566[2U] = vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__data + [(0x3fU & vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__addr_st1 + [0U])][2U]; + __Vtemp566[3U] = vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__data + [(0x3fU & vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__addr_st1 + [0U])][3U]; + vcdp->fullArray(c+5625,(__Vtemp566),128); + vcdp->fullBit(c+5657,(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__tag_data_access__DOT__read_valid_st1c + [0U])); + vcdp->fullBit(c+5665,(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__tag_data_access__DOT__read_dirty_st1c + [0U])); + vcdp->fullBus(c+5673,(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__tag_data_access__DOT__use_write_enable),16); + vcdp->fullArray(c+5681,(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__tag_data_access__DOT__data_write),128); + vcdp->fullBit(c+5713,(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__tag_data_access__DOT__snoop_hit_no_pending)); + vcdp->fullBit(c+5721,(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__tag_data_access__DOT__tags_match)); + vcdp->fullBit(c+5729,(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__tag_data_access__DOT__real_writefill)); + vcdp->fullBus(c+5737,((0xfffffU & (vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__addr_st1 + [0U] >> 6U))),20); + vcdp->fullBus(c+5745,(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__tag_data_access__DOT__we),16); + vcdp->fullBit(c+5753,(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__tag_data_access__DOT__should_write)); + vcdp->fullBit(c+5761,((((vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__valid_st1 + [0U] & (~ vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__is_snp_st1 + [0U])) & (~ + vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__tag_data_access__DOT__read_valid_st1c + [0U])) + & (~ vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__is_fill_st1 + [0U])))); + vcdp->fullBit(c+5769,(((((vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__valid_st1 + [0U] & (~ vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__is_snp_st1 + [0U])) & + vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__tag_data_access__DOT__read_valid_st1c + [0U]) & (~ vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__is_fill_st1 + [0U])) & + (~ (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__tag_data_access__DOT__tags_match))))); + vcdp->fullBit(c+5777,(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__tag_data_access__DOT__real_miss)); + vcdp->fullBit(c+5785,((((((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__force_request_miss_st1e) + & (~ vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__is_snp_st1 + [0U])) & (~ vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__is_fill_st1 + [0U])) + & vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__valid_st1 + [0U]) & (~ (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__tag_data_access__DOT__real_miss))))); + vcdp->fullBit(c+5793,(((0U == vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__wsel_st1 + [0U]) & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__tag_data_access__DOT__should_write)))); + vcdp->fullBit(c+5801,(((1U == vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__wsel_st1 + [0U]) & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__tag_data_access__DOT__should_write)))); + vcdp->fullBit(c+5809,(((2U == vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__wsel_st1 + [0U]) & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__tag_data_access__DOT__should_write)))); + vcdp->fullBit(c+5817,(((3U == vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__wsel_st1 + [0U]) & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__tag_data_access__DOT__should_write)))); + vcdp->fullBit(c+5825,((0U != (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__tag_data_access__DOT__use_write_enable)))); + vcdp->fullArray(c+5833,(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__tag_data_access__DOT____Vcellinp__s0_1_c0__in),166); + vcdp->fullArray(c+5881,(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT____Vcellinp__st_1e_2__in),316); + vcdp->fullBus(c+5961,(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__cache_miss_resrv__DOT__make_ready),16); + vcdp->fullBus(c+5969,((0xffffU & (((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__cache_miss_resrv__DOT__mrvq_push) + & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__mrvq_init_ready_state_st2)) + << (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__cache_miss_resrv__DOT__tail_ptr)))),16); + vcdp->fullBus(c+5977,(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__cache_miss_resrv__DOT__valid_address_match),16); + vcdp->fullBit(c+5985,(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__cache_miss_resrv__DOT__mrvq_push)); + vcdp->fullBit(c+5993,(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__cache_miss_resrv__DOT__mrvq_pop)); + vcdp->fullBit(c+6001,(((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__miss_add) + & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__miss_add_is_mrvq)))); + vcdp->fullBit(c+6009,(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__cache_miss_resrv__DOT__increment_head)); + vcdp->fullBit(c+6017,((0U != (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__cache_miss_resrv__DOT__make_ready)))); + vcdp->fullBit(c+6025,(((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__cache_miss_resrv__DOT__mrvq_push) + & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__mrvq_init_ready_state_st2)))); + vcdp->fullArray(c+6033,(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT____Vcellinp__cwb_queue__data_in),76); + vcdp->fullArray(c+6057,(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT____Vcellout__cwb_queue__data_out),76); + vcdp->fullBit(c+6081,(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__cwb_queue__DOT__writing)); + vcdp->fullArray(c+6089,(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT____Vcellinp__dwb_queue__data_in),200); + vcdp->fullArray(c+6145,(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT____Vcellout__dwb_queue__data_out),200); + vcdp->fullBit(c+6201,(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__dwb_queue__DOT__writing)); + vcdp->fullBit(c+6209,(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__snrq_pop)); + vcdp->fullBus(c+6217,((0x3ffffffU & (IData)( + (vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT____Vcellout__snp_req_queue__data_out + >> 0x1dU)))),26); + vcdp->fullBit(c+6225,((1U & (IData)((vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT____Vcellout__snp_req_queue__data_out + >> 0x1cU))))); + vcdp->fullBus(c+6233,((0xfffffffU & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT____Vcellout__snp_req_queue__data_out))),28); + vcdp->fullBit(c+6241,(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__dfpq_pop)); + vcdp->fullBus(c+6249,((0x3ffffffU & vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT____Vcellout__dfp_queue__data_out[4U])),26); + __Vtemp567[0U] = vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT____Vcellout__dfp_queue__data_out[0U]; + __Vtemp567[1U] = vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT____Vcellout__dfp_queue__data_out[1U]; + __Vtemp567[2U] = vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT____Vcellout__dfp_queue__data_out[2U]; + __Vtemp567[3U] = vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT____Vcellout__dfp_queue__data_out[3U]; + vcdp->fullArray(c+6257,(__Vtemp567),128); + vcdp->fullBit(c+6289,(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__reqq_pop)); + vcdp->fullBit(c+6297,((1U & (~ (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__core_req_arb__DOT__qual_has_request))))); + vcdp->fullBit(c+6305,(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__core_req_arb__DOT__qual_has_request)); + vcdp->fullBus(c+6313,(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__core_req_arb__DOT__qual_request_index),2); + vcdp->fullBit(c+6321,(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__reqq_req_rw_st0)); + vcdp->fullBus(c+6329,((0xfU & ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__core_req_arb__DOT__use_per_byteen) + >> (0xfU & ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__core_req_arb__DOT__qual_request_index) + << 2U))))),4); + vcdp->fullBus(c+6337,(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__reqq_req_addr_st0),30); + vcdp->fullBus(c+6345,((((0U == (0x1fU & ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__core_req_arb__DOT__qual_request_index) + << 5U))) + ? 0U : (vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__core_req_arb__DOT__use_per_writedata[ + ((IData)(1U) + + (3U & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__core_req_arb__DOT__qual_request_index)))] + << ((IData)(0x20U) + - (0x1fU + & ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__core_req_arb__DOT__qual_request_index) + << 5U))))) + | (vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__core_req_arb__DOT__use_per_writedata[ + (3U & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__core_req_arb__DOT__qual_request_index))] + >> (0x1fU & ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__core_req_arb__DOT__qual_request_index) + << 5U))))),32); + vcdp->fullBit(c+6353,(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__mrvq_pop)); + vcdp->fullBit(c+6361,(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__cache_miss_resrv__DOT__dequeue_possible)); + vcdp->fullBit(c+6369,(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__mrvq_rw_st0)); + vcdp->fullBit(c+6377,((0U != (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__cache_miss_resrv__DOT__valid_address_match)))); + vcdp->fullBit(c+6385,(((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__miss_add_because_miss) + & (((0x3ffffffU & (( + vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__st_1e_2__DOT__value[9U] + << 7U) + | (vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__st_1e_2__DOT__value[8U] + >> 0x19U))) + == vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__addr_st1 + [0U]) & (~ (vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__st_1e_2__DOT__value[9U] + >> 0x14U)))))); + vcdp->fullBit(c+6393,(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__force_request_miss_st1e)); + vcdp->fullBit(c+6401,(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__recover_mrvq_state_st2)); + vcdp->fullBit(c+6409,(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__mrvq_push_stall)); + vcdp->fullBit(c+6417,(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__cwbq_push_stall)); + vcdp->fullBit(c+6425,(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__dwbq_push_stall)); + vcdp->fullBit(c+6433,(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__dram_fill_req_stall)); + vcdp->fullBit(c+6441,(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__stall_bank_pipe)); + vcdp->fullBit(c+6449,(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__is_fill_in_pipe)); + vcdp->fullBit(c+6457,(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__is_fill_st1[0])); + vcdp->fullBit(c+6465,(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__going_to_write_st1[0])); + vcdp->fullBit(c+6473,(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__dfpq_pop_unqual)); + vcdp->fullBit(c+6481,(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__reqq_pop_unqual)); + vcdp->fullBit(c+6489,(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__snrq_pop_unqual)); + vcdp->fullBit(c+6497,(((((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__dfpq_pop) + | (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__mrvq_pop)) + | (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__reqq_pop)) + | (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__snrq_pop)))); + vcdp->fullBus(c+6505,((0x3ffffffU & ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__dfpq_pop_unqual) + ? (0x3ffffffU + & vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT____Vcellout__dfp_queue__data_out[4U]) + : ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__cache_miss_resrv__DOT__dequeue_possible) + ? + ((0x19fU + >= + (0x1ffU + & ((IData)(0x1aU) + * (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr)))) + ? + (0x3ffffffU + & (((0U + == + (0x1fU + & ((IData)(0x1aU) + * (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr)))) + ? 0U + : + (vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__cache_miss_resrv__DOT__addr_table[ + ((IData)(1U) + + + (0xfU + & (((IData)(0x1aU) + * (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr)) + >> 5U)))] + << + ((IData)(0x20U) + - + (0x1fU + & ((IData)(0x1aU) + * (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr)))))) + | (vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__cache_miss_resrv__DOT__addr_table[ + (0xfU + & (((IData)(0x1aU) + * (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr)) + >> 5U))] + >> + (0x1fU + & ((IData)(0x1aU) + * (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr)))))) + : 0U) + : + ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__reqq_pop_unqual) + ? + (0x3ffffffU + & (vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__reqq_req_addr_st0 + >> 4U)) + : + ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__snrq_pop_unqual) + ? + (0x3ffffffU + & (IData)( + (vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT____Vcellout__snp_req_queue__data_out + >> 0x1dU))) + : 0U)))))),26); + vcdp->fullBus(c+6513,((3U & ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__reqq_pop_unqual) + ? (3U & vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__reqq_req_addr_st0) + : ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__cache_miss_resrv__DOT__dequeue_possible) + ? (3U & ( + (vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__cache_miss_resrv__DOT__metadata_table + [vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr][1U] + << 0x1eU) + | (vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__cache_miss_resrv__DOT__metadata_table + [vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr][0U] + >> 2U))) + : 0U)))),2); + vcdp->fullBus(c+6521,(((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__cache_miss_resrv__DOT__dequeue_possible) + ? ((vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__cache_miss_resrv__DOT__metadata_table + [vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr][2U] + << 0xbU) | (vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__cache_miss_resrv__DOT__metadata_table + [vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr][1U] + >> 0x15U)) + : ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__reqq_pop_unqual) + ? (((0U == (0x1fU + & ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__core_req_arb__DOT__qual_request_index) + << 5U))) + ? 0U : (vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__core_req_arb__DOT__use_per_writedata[ + ((IData)(1U) + + + (3U + & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__core_req_arb__DOT__qual_request_index)))] + << + ((IData)(0x20U) + - + (0x1fU + & ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__core_req_arb__DOT__qual_request_index) + << 5U))))) + | (vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__core_req_arb__DOT__use_per_writedata[ + (3U & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__core_req_arb__DOT__qual_request_index))] + >> (0x1fU + & ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__core_req_arb__DOT__qual_request_index) + << 5U)))) + : 0U))),32); + __Vtemp572[0U] = ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__dfpq_pop_unqual) + ? vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT____Vcellout__dfp_queue__data_out[0U] + : 0x39U); + __Vtemp572[1U] = ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__dfpq_pop_unqual) + ? vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT____Vcellout__dfp_queue__data_out[1U] + : 0U); + __Vtemp572[2U] = ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__dfpq_pop_unqual) + ? vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT____Vcellout__dfp_queue__data_out[2U] + : 0U); + __Vtemp572[3U] = ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__dfpq_pop_unqual) + ? vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT____Vcellout__dfp_queue__data_out[3U] + : 0U); + vcdp->fullArray(c+6529,(__Vtemp572),128); + vcdp->fullQuad(c+6561,(((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__cache_miss_resrv__DOT__dequeue_possible) + ? ((VL_ULL(0x1ffffffffff80) + & (((QData)((IData)( + vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__cache_miss_resrv__DOT__metadata_table + [vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr][2U])) + << 0x3eU) + | (((QData)((IData)( + vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__cache_miss_resrv__DOT__metadata_table + [vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr][1U])) + << 0x1eU) + | (VL_ULL(0x3fffffffffffff80) + & ((QData)((IData)( + vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__cache_miss_resrv__DOT__metadata_table + [vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr][0U])) + >> 2U))))) + | (QData)((IData)( + (((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__mrvq_rw_st0) + << 6U) + | ((0x3cU + & ((vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__cache_miss_resrv__DOT__metadata_table + [vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr][1U] + << 0x1eU) + | (0x3ffffffcU + & (vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__cache_miss_resrv__DOT__metadata_table + [vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr][0U] + >> 2U)))) + | (3U + & ((vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__cache_miss_resrv__DOT__metadata_table + [vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr][2U] + << 0xdU) + | (vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__cache_miss_resrv__DOT__metadata_table + [vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr][1U] + >> 0x13U)))))))) + : ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__reqq_pop_unqual) + ? ((vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__core_req_arb__DOT__use_per_tag + << 7U) | (QData)((IData)( + (((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__reqq_req_rw_st0) + << 6U) + | ((0x3cU + & (((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__core_req_arb__DOT__use_per_byteen) + >> + (0xfU + & ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__core_req_arb__DOT__qual_request_index) + << 2U))) + << 2U)) + | (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__core_req_arb__DOT__qual_request_index)))))) + : ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__snrq_pop_unqual) + ? ((QData)((IData)( + (0xfffffffU + & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT____Vcellout__snp_req_queue__data_out)))) + << 7U) : VL_ULL(0))))),49); + vcdp->fullBit(c+6577,(((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__dfpq_pop_unqual) + ? 1U : (((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__cache_miss_resrv__DOT__dequeue_possible) + & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__mrvq_rw_st0)) + ? 1U : (((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__reqq_pop_unqual) + & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__reqq_req_rw_st0)) + ? 1U + : 0U))))); + vcdp->fullBit(c+6585,((1U & ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__cache_miss_resrv__DOT__dequeue_possible) + ? (1U & (vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__cache_miss_resrv__DOT__metadata_table + [vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr][0U] + >> 1U)) + : ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__snrq_pop_unqual) + ? 1U : 0U))))); + vcdp->fullBit(c+6593,((1U & ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__cache_miss_resrv__DOT__dequeue_possible) + ? (1U & vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__cache_miss_resrv__DOT__metadata_table + [vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr][0U]) + : ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__snrq_pop_unqual) + ? (1U & (IData)( + (vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT____Vcellout__snp_req_queue__data_out + >> 0x1cU))) + : 0U))))); + vcdp->fullBit(c+6601,(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__valid_st1[0])); + vcdp->fullBus(c+6609,(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__addr_st1[0]),26); + vcdp->fullBus(c+6617,(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__wsel_st1[0]),2); + vcdp->fullBus(c+6625,(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__writeword_st1[0]),32); + vcdp->fullQuad(c+6633,(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__inst_meta_st1[0]),49); + vcdp->fullArray(c+6649,(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__writedata_st1[0]),128); + vcdp->fullBit(c+6681,(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__is_snp_st1[0])); + vcdp->fullBit(c+6689,(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__snp_invalidate_st1[0])); + vcdp->fullBit(c+6697,(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__is_mrvq_st1[0])); + __Vtemp578[0U] = vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__tag_data_access__DOT__read_data_st1c + [0U][0U]; + __Vtemp578[1U] = vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__tag_data_access__DOT__read_data_st1c + [0U][1U]; + __Vtemp578[2U] = vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__tag_data_access__DOT__read_data_st1c + [0U][2U]; + __Vtemp578[3U] = vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__tag_data_access__DOT__read_data_st1c + [0U][3U]; + vcdp->fullBus(c+6705,((((0U == (0x1fU & (vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__wsel_st1 + [0U] + << 5U))) + ? 0U : (__Vtemp578[ + ((IData)(1U) + + (3U & vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__wsel_st1 + [0U]))] + << ((IData)(0x20U) + - (0x1fU + & (vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__wsel_st1 + [0U] + << 5U))))) + | (__Vtemp578[(3U & + vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__wsel_st1 + [0U])] + >> (0x1fU & (vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__wsel_st1 + [0U] + << 5U))))),32); + __Vtemp579[0U] = vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__tag_data_access__DOT__read_data_st1c + [0U][0U]; + __Vtemp579[1U] = vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__tag_data_access__DOT__read_data_st1c + [0U][1U]; + __Vtemp579[2U] = vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__tag_data_access__DOT__read_data_st1c + [0U][2U]; + __Vtemp579[3U] = vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__tag_data_access__DOT__read_data_st1c + [0U][3U]; + vcdp->fullArray(c+6713,(__Vtemp579),128); + vcdp->fullBus(c+6745,(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__tag_data_access__DOT__read_tag_st1c + [0U]),20); + vcdp->fullBit(c+6753,(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__miss_st1e)); + vcdp->fullBit(c+6761,(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__dirty_st1e)); + vcdp->fullBus(c+6769,(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__tag_data_access__DOT__read_dirtyb_st1c + [0U]),16); + vcdp->fullQuad(c+6777,((VL_ULL(0x3ffffffffff) + & (vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__inst_meta_st1 + [0U] >> 7U))),42); + vcdp->fullBus(c+6793,((3U & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__inst_meta_st1 + [0U]))),2); + vcdp->fullBit(c+6801,((1U & (IData)((vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__inst_meta_st1 + [0U] >> 6U))))); + vcdp->fullBus(c+6809,((0xfU & (IData)((vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__inst_meta_st1 + [0U] + >> 2U)))),4); + vcdp->fullBit(c+6817,(((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__tag_data_access__DOT__real_writefill) + & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__dirty_st1e)))); + vcdp->fullBit(c+6825,(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__is_snp_st1 + [0U])); + vcdp->fullBit(c+6833,(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__snp_invalidate_st1 + [0U])); + vcdp->fullBit(c+6841,(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__snp_to_mrvq_st1e)); + vcdp->fullBit(c+6849,(((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__snp_to_mrvq_st1e) + | ((((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__force_request_miss_st1e) + & (~ vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__is_snp_st1 + [0U])) & (~ + vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__is_fill_st1 + [0U])) + & vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__valid_st1 + [0U])))); + vcdp->fullBit(c+6857,(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__miss_add_because_miss)); + vcdp->fullBit(c+6865,(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__valid_st1 + [0U])); + vcdp->fullBit(c+6873,(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__is_mrvq_st1 + [0U])); + vcdp->fullBit(c+6881,((((vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__valid_st1 + [0U] & vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__is_mrvq_st1 + [0U]) & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__recover_mrvq_state_st2)) + & ((0x3ffffffU & ((vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__st_1e_2__DOT__value[9U] + << 7U) + | (vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__st_1e_2__DOT__value[8U] + >> 0x19U))) + == vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__addr_st1 + [0U])))); + vcdp->fullBus(c+6889,(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__addr_st1 + [0U]),26); + vcdp->fullBit(c+6897,((vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__valid_st1 + [0U] & (~ vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__is_fill_st1 + [0U])))); + vcdp->fullBit(c+6905,(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__mrvq_init_ready_state_st2)); + vcdp->fullBit(c+6913,((((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__miss_add_unqual) + & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__dfpq_pop_unqual)) + & ((0x3ffffffU & ((vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__st_1e_2__DOT__value[9U] + << 7U) + | (vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__st_1e_2__DOT__value[8U] + >> 0x19U))) + == (0x3ffffffU & + vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT____Vcellout__dfp_queue__data_out[4U]))))); + vcdp->fullBit(c+6921,((((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__miss_add_unqual) + & vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__is_fill_st1 + [0U]) & ((0x3ffffffU + & ((vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__st_1e_2__DOT__value[9U] + << 7U) + | (vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__st_1e_2__DOT__value[8U] + >> 0x19U))) + == vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__addr_st1 + [0U])))); + vcdp->fullBit(c+6929,(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__miss_add_unqual)); + vcdp->fullBit(c+6937,(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__miss_add)); + vcdp->fullBit(c+6945,(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__miss_add_is_mrvq)); + vcdp->fullBit(c+6953,(((((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__cwbq_push_unqual) + & (~ (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__cwb_queue__DOT__genblk3__DOT__genblk2__DOT__full_r))) + & (~ (vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__st_1e_2__DOT__value[0U] + >> 6U))) & (~ + (((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__dwbq_push_stall) + | (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__mrvq_push_stall)) + | (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__dram_fill_req_stall)))))); + vcdp->fullBit(c+6961,(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__cwbq_push_unqual)); + vcdp->fullBit(c+6969,(((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__miss_add_unqual) + & ((~ (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__mrvq_init_ready_state_st2)) + | ((vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__st_1e_2__DOT__value[9U] + >> 0x1aU) & (~ + (vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__st_1e_2__DOT__value[9U] + >> 0x1bU))))))); + vcdp->fullBit(c+6977,((((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__dwbq_push_unqual) + & (~ (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__genblk2__DOT__full_r))) + & (~ (((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__cwbq_push_stall) + | (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__mrvq_push_stall)) + | (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__dram_fill_req_stall)))))); + vcdp->fullBit(c+6985,(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__dwbq_is_dwb_in)); + vcdp->fullBit(c+6993,(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__dwbq_is_snp_in)); + vcdp->fullBit(c+7001,((1U & (vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT____Vcellout__dwb_queue__data_out[6U] + >> 7U)))); + vcdp->fullBit(c+7009,((1U & (vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT____Vcellout__dwb_queue__data_out[6U] + >> 6U)))); + vcdp->fullBit(c+7017,(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__dwbq_push_unqual)); + vcdp->fullQuad(c+7025,(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT____Vcellout__snp_req_queue__data_out),55); + vcdp->fullBit(c+7041,(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__snp_req_queue__DOT__reading)); + vcdp->fullArray(c+7049,(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT____Vcellout__dfp_queue__data_out),154); + vcdp->fullBit(c+7089,(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__dfp_queue__DOT__reading)); + vcdp->fullBus(c+7097,((0xfU & (vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__core_req_arb__DOT____Vcellout__reqq_queue__data_out[9U] + >> 0x16U))),4); + vcdp->fullBus(c+7105,((0xfU & (vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__core_req_arb__DOT____Vcellout__reqq_queue__data_out[9U] + >> 0x12U))),4); + vcdp->fullBus(c+7113,((0xffffU & (vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__core_req_arb__DOT____Vcellout__reqq_queue__data_out[9U] + >> 2U))),16); + __Vtemp582[0U] = ((vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__core_req_arb__DOT____Vcellout__reqq_queue__data_out[6U] + << 0x16U) | (vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__core_req_arb__DOT____Vcellout__reqq_queue__data_out[5U] + >> 0xaU)); + __Vtemp582[1U] = ((vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__core_req_arb__DOT____Vcellout__reqq_queue__data_out[7U] + << 0x16U) | (vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__core_req_arb__DOT____Vcellout__reqq_queue__data_out[6U] + >> 0xaU)); + __Vtemp582[2U] = ((vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__core_req_arb__DOT____Vcellout__reqq_queue__data_out[8U] + << 0x16U) | (vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__core_req_arb__DOT____Vcellout__reqq_queue__data_out[7U] + >> 0xaU)); + __Vtemp582[3U] = (0xffffffU & ((vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__core_req_arb__DOT____Vcellout__reqq_queue__data_out[9U] + << 0x16U) | + (vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__core_req_arb__DOT____Vcellout__reqq_queue__data_out[8U] + >> 0xaU))); + vcdp->fullArray(c+7121,(__Vtemp582),120); + __Vtemp583[0U] = ((vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__core_req_arb__DOT____Vcellout__reqq_queue__data_out[2U] + << 0x16U) | (vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__core_req_arb__DOT____Vcellout__reqq_queue__data_out[1U] + >> 0xaU)); + __Vtemp583[1U] = ((vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__core_req_arb__DOT____Vcellout__reqq_queue__data_out[3U] + << 0x16U) | (vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__core_req_arb__DOT____Vcellout__reqq_queue__data_out[2U] + >> 0xaU)); + __Vtemp583[2U] = ((vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__core_req_arb__DOT____Vcellout__reqq_queue__data_out[4U] + << 0x16U) | (vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__core_req_arb__DOT____Vcellout__reqq_queue__data_out[3U] + >> 0xaU)); + __Vtemp583[3U] = ((vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__core_req_arb__DOT____Vcellout__reqq_queue__data_out[5U] + << 0x16U) | (vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__core_req_arb__DOT____Vcellout__reqq_queue__data_out[4U] + >> 0xaU)); + vcdp->fullArray(c+7153,(__Vtemp583),128); + vcdp->fullQuad(c+7185,((VL_ULL(0x3ffffffffff) + & (((QData)((IData)( + vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__core_req_arb__DOT____Vcellout__reqq_queue__data_out[1U])) + << 0x20U) | (QData)((IData)( + vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__core_req_arb__DOT____Vcellout__reqq_queue__data_out[0U]))))),42); + vcdp->fullBit(c+7201,(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__core_req_arb__DOT__out_empty)); + vcdp->fullBit(c+7209,(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__core_req_arb__DOT__pop_qual)); + vcdp->fullBus(c+7217,((0xfU & ((vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__core_req_arb__DOT____Vcellout__reqq_queue__data_out[9U] + >> 0x16U) & + VL_NEGATE_I((IData)( + (1U + & (~ (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__core_req_arb__DOT__out_empty)))))))),4); + vcdp->fullArray(c+7225,(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__core_req_arb__DOT____Vcellout__reqq_queue__data_out),314); + vcdp->fullBit(c+7305,(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__reading)); + vcdp->fullBus(c+7313,(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__core_req_arb__DOT__sel_bank__DOT__genblk2__DOT__grant_onehot_r),4); + vcdp->fullBus(c+7321,(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__core_req_arb__DOT__sel_bank__DOT__genblk2__DOT__priority_encoder__DOT__i),32); + vcdp->fullArray(c+7329,(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT____Vcellinp__s0_1_c0__in),243); + vcdp->fullBus(c+7393,((0x3fU & vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__addr_st1 + [0U])),6); + vcdp->fullBit(c+7401,(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__is_fill_st1 + [0U])); + vcdp->fullBus(c+7409,(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__writeword_st1 + [0U]),32); + __Vtemp584[0U] = vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__writedata_st1 + [0U][0U]; + __Vtemp584[1U] = vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__writedata_st1 + [0U][1U]; + __Vtemp584[2U] = vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__writedata_st1 + [0U][2U]; + __Vtemp584[3U] = vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__writedata_st1 + [0U][3U]; + vcdp->fullArray(c+7417,(__Vtemp584),128); + vcdp->fullBus(c+7449,(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__wsel_st1 + [0U]),2); + vcdp->fullBit(c+7457,(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__tag_data_access__DOT__read_valid_st1c[0])); + vcdp->fullBit(c+7465,(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__tag_data_access__DOT__read_dirty_st1c[0])); + vcdp->fullBus(c+7473,(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__tag_data_access__DOT__read_dirtyb_st1c[0]),16); + vcdp->fullBus(c+7481,(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__tag_data_access__DOT__read_tag_st1c[0]),20); + vcdp->fullArray(c+7489,(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__tag_data_access__DOT__read_data_st1c[0]),128); + vcdp->fullBit(c+7521,((1U & (IData)((vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__valid + >> (0x3fU + & vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__addr_st1 + [0U])))))); + vcdp->fullBit(c+7529,((1U & (IData)((vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__dirty + >> (0x3fU + & vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__addr_st1 + [0U])))))); + vcdp->fullBus(c+7537,(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__dirtyb + [(0x3fU & vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__addr_st1 + [0U])]),16); + vcdp->fullBus(c+7545,(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__tag + [(0x3fU & vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__addr_st1 + [0U])]),20); + __Vtemp585[0U] = vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__data + [(0x3fU & vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__addr_st1 + [0U])][0U]; + __Vtemp585[1U] = vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__data + [(0x3fU & vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__addr_st1 + [0U])][1U]; + __Vtemp585[2U] = vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__data + [(0x3fU & vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__addr_st1 + [0U])][2U]; + __Vtemp585[3U] = vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__data + [(0x3fU & vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__addr_st1 + [0U])][3U]; + vcdp->fullArray(c+7553,(__Vtemp585),128); + vcdp->fullBit(c+7585,(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__tag_data_access__DOT__read_valid_st1c + [0U])); + vcdp->fullBit(c+7593,(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__tag_data_access__DOT__read_dirty_st1c + [0U])); + vcdp->fullBus(c+7601,(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__tag_data_access__DOT__use_write_enable),16); + vcdp->fullArray(c+7609,(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__tag_data_access__DOT__data_write),128); + vcdp->fullBit(c+7641,(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__tag_data_access__DOT__snoop_hit_no_pending)); + vcdp->fullBit(c+7649,(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__tag_data_access__DOT__tags_match)); + vcdp->fullBit(c+7657,(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__tag_data_access__DOT__real_writefill)); + vcdp->fullBus(c+7665,((0xfffffU & (vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__addr_st1 + [0U] >> 6U))),20); + vcdp->fullBus(c+7673,(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__tag_data_access__DOT__we),16); + vcdp->fullBit(c+7681,(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__tag_data_access__DOT__should_write)); + vcdp->fullBit(c+7689,((((vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__valid_st1 + [0U] & (~ vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__is_snp_st1 + [0U])) & (~ + vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__tag_data_access__DOT__read_valid_st1c + [0U])) + & (~ vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__is_fill_st1 + [0U])))); + vcdp->fullBit(c+7697,(((((vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__valid_st1 + [0U] & (~ vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__is_snp_st1 + [0U])) & + vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__tag_data_access__DOT__read_valid_st1c + [0U]) & (~ vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__is_fill_st1 + [0U])) & + (~ (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__tag_data_access__DOT__tags_match))))); + vcdp->fullBit(c+7705,(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__tag_data_access__DOT__real_miss)); + vcdp->fullBit(c+7713,((((((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__force_request_miss_st1e) + & (~ vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__is_snp_st1 + [0U])) & (~ vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__is_fill_st1 + [0U])) + & vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__valid_st1 + [0U]) & (~ (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__tag_data_access__DOT__real_miss))))); + vcdp->fullBit(c+7721,(((0U == vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__wsel_st1 + [0U]) & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__tag_data_access__DOT__should_write)))); + vcdp->fullBit(c+7729,(((1U == vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__wsel_st1 + [0U]) & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__tag_data_access__DOT__should_write)))); + vcdp->fullBit(c+7737,(((2U == vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__wsel_st1 + [0U]) & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__tag_data_access__DOT__should_write)))); + vcdp->fullBit(c+7745,(((3U == vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__wsel_st1 + [0U]) & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__tag_data_access__DOT__should_write)))); + vcdp->fullBit(c+7753,((0U != (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__tag_data_access__DOT__use_write_enable)))); + vcdp->fullArray(c+7761,(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__tag_data_access__DOT____Vcellinp__s0_1_c0__in),166); + vcdp->fullArray(c+7809,(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT____Vcellinp__st_1e_2__in),316); + vcdp->fullBus(c+7889,(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__cache_miss_resrv__DOT__make_ready),16); + vcdp->fullBus(c+7897,((0xffffU & (((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__cache_miss_resrv__DOT__mrvq_push) + & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__mrvq_init_ready_state_st2)) + << (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__cache_miss_resrv__DOT__tail_ptr)))),16); + vcdp->fullBus(c+7905,(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__cache_miss_resrv__DOT__valid_address_match),16); + vcdp->fullBit(c+7913,(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__cache_miss_resrv__DOT__mrvq_push)); + vcdp->fullBit(c+7921,(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__cache_miss_resrv__DOT__mrvq_pop)); + vcdp->fullBit(c+7929,(((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__miss_add) + & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__miss_add_is_mrvq)))); + vcdp->fullBit(c+7937,(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__cache_miss_resrv__DOT__increment_head)); + vcdp->fullBit(c+7945,((0U != (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__cache_miss_resrv__DOT__make_ready)))); + vcdp->fullBit(c+7953,(((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__cache_miss_resrv__DOT__mrvq_push) + & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__mrvq_init_ready_state_st2)))); + vcdp->fullArray(c+7961,(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT____Vcellinp__cwb_queue__data_in),76); + vcdp->fullArray(c+7985,(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT____Vcellout__cwb_queue__data_out),76); + vcdp->fullBit(c+8009,(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__cwb_queue__DOT__writing)); + vcdp->fullArray(c+8017,(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT____Vcellinp__dwb_queue__data_in),200); + vcdp->fullArray(c+8073,(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT____Vcellout__dwb_queue__data_out),200); + vcdp->fullBit(c+8129,(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__dwb_queue__DOT__writing)); + vcdp->fullBit(c+8137,(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__snrq_pop)); + vcdp->fullBus(c+8145,((0x3ffffffU & (IData)( + (vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT____Vcellout__snp_req_queue__data_out + >> 0x1dU)))),26); + vcdp->fullBit(c+8153,((1U & (IData)((vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT____Vcellout__snp_req_queue__data_out + >> 0x1cU))))); + vcdp->fullBus(c+8161,((0xfffffffU & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT____Vcellout__snp_req_queue__data_out))),28); + vcdp->fullBit(c+8169,(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__dfpq_pop)); + vcdp->fullBus(c+8177,((0x3ffffffU & vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT____Vcellout__dfp_queue__data_out[4U])),26); + __Vtemp586[0U] = vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT____Vcellout__dfp_queue__data_out[0U]; + __Vtemp586[1U] = vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT____Vcellout__dfp_queue__data_out[1U]; + __Vtemp586[2U] = vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT____Vcellout__dfp_queue__data_out[2U]; + __Vtemp586[3U] = vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT____Vcellout__dfp_queue__data_out[3U]; + vcdp->fullArray(c+8185,(__Vtemp586),128); + vcdp->fullBit(c+8217,(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__reqq_pop)); + vcdp->fullBit(c+8225,((1U & (~ (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__core_req_arb__DOT__qual_has_request))))); + vcdp->fullBit(c+8233,(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__core_req_arb__DOT__qual_has_request)); + vcdp->fullBus(c+8241,(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__core_req_arb__DOT__qual_request_index),2); + vcdp->fullBit(c+8249,(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__reqq_req_rw_st0)); + vcdp->fullBus(c+8257,((0xfU & ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__core_req_arb__DOT__use_per_byteen) + >> (0xfU & ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__core_req_arb__DOT__qual_request_index) + << 2U))))),4); + vcdp->fullBus(c+8265,(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__reqq_req_addr_st0),30); + vcdp->fullBus(c+8273,((((0U == (0x1fU & ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__core_req_arb__DOT__qual_request_index) + << 5U))) + ? 0U : (vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__core_req_arb__DOT__use_per_writedata[ + ((IData)(1U) + + (3U & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__core_req_arb__DOT__qual_request_index)))] + << ((IData)(0x20U) + - (0x1fU + & ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__core_req_arb__DOT__qual_request_index) + << 5U))))) + | (vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__core_req_arb__DOT__use_per_writedata[ + (3U & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__core_req_arb__DOT__qual_request_index))] + >> (0x1fU & ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__core_req_arb__DOT__qual_request_index) + << 5U))))),32); + vcdp->fullBit(c+8281,(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__mrvq_pop)); + vcdp->fullBit(c+8289,(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cache_miss_resrv__DOT__dequeue_possible)); + vcdp->fullBit(c+8297,(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__mrvq_rw_st0)); + vcdp->fullBit(c+8305,((0U != (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cache_miss_resrv__DOT__valid_address_match)))); + vcdp->fullBit(c+8313,(((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__miss_add_because_miss) + & (((0x3ffffffU & (( + vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__st_1e_2__DOT__value[9U] + << 7U) + | (vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__st_1e_2__DOT__value[8U] + >> 0x19U))) + == vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__addr_st1 + [0U]) & (~ (vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__st_1e_2__DOT__value[9U] + >> 0x14U)))))); + vcdp->fullBit(c+8321,(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__force_request_miss_st1e)); + vcdp->fullBit(c+8329,(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__recover_mrvq_state_st2)); + vcdp->fullBit(c+8337,(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__mrvq_push_stall)); + vcdp->fullBit(c+8345,(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cwbq_push_stall)); + vcdp->fullBit(c+8353,(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__dwbq_push_stall)); + vcdp->fullBit(c+8361,(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__dram_fill_req_stall)); + vcdp->fullBit(c+8369,(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__stall_bank_pipe)); + vcdp->fullBit(c+8377,(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__is_fill_in_pipe)); + vcdp->fullBit(c+8385,(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__is_fill_st1[0])); + vcdp->fullBit(c+8393,(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__going_to_write_st1[0])); + vcdp->fullBit(c+8401,(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__dfpq_pop_unqual)); + vcdp->fullBit(c+8409,(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__reqq_pop_unqual)); + vcdp->fullBit(c+8417,(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__snrq_pop_unqual)); + vcdp->fullBit(c+8425,(((((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__dfpq_pop) + | (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__mrvq_pop)) + | (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__reqq_pop)) + | (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__snrq_pop)))); + vcdp->fullBus(c+8433,((0x3ffffffU & ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__dfpq_pop_unqual) + ? (0x3ffffffU + & vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT____Vcellout__dfp_queue__data_out[4U]) + : ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cache_miss_resrv__DOT__dequeue_possible) + ? + ((0x19fU + >= + (0x1ffU + & ((IData)(0x1aU) + * (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr)))) + ? + (0x3ffffffU + & (((0U + == + (0x1fU + & ((IData)(0x1aU) + * (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr)))) + ? 0U + : + (vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cache_miss_resrv__DOT__addr_table[ + ((IData)(1U) + + + (0xfU + & (((IData)(0x1aU) + * (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr)) + >> 5U)))] + << + ((IData)(0x20U) + - + (0x1fU + & ((IData)(0x1aU) + * (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr)))))) + | (vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cache_miss_resrv__DOT__addr_table[ + (0xfU + & (((IData)(0x1aU) + * (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr)) + >> 5U))] + >> + (0x1fU + & ((IData)(0x1aU) + * (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr)))))) + : 0U) + : + ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__reqq_pop_unqual) + ? + (0x3ffffffU + & (vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__reqq_req_addr_st0 + >> 4U)) + : + ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__snrq_pop_unqual) + ? + (0x3ffffffU + & (IData)( + (vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT____Vcellout__snp_req_queue__data_out + >> 0x1dU))) + : 0U)))))),26); + vcdp->fullBus(c+8441,((3U & ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__reqq_pop_unqual) + ? (3U & vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__reqq_req_addr_st0) + : ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cache_miss_resrv__DOT__dequeue_possible) + ? (3U & ( + (vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cache_miss_resrv__DOT__metadata_table + [vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr][1U] + << 0x1eU) + | (vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cache_miss_resrv__DOT__metadata_table + [vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr][0U] + >> 2U))) + : 0U)))),2); + vcdp->fullBus(c+8449,(((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cache_miss_resrv__DOT__dequeue_possible) + ? ((vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cache_miss_resrv__DOT__metadata_table + [vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr][2U] + << 0xbU) | (vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cache_miss_resrv__DOT__metadata_table + [vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr][1U] + >> 0x15U)) + : ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__reqq_pop_unqual) + ? (((0U == (0x1fU + & ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__core_req_arb__DOT__qual_request_index) + << 5U))) + ? 0U : (vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__core_req_arb__DOT__use_per_writedata[ + ((IData)(1U) + + + (3U + & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__core_req_arb__DOT__qual_request_index)))] + << + ((IData)(0x20U) + - + (0x1fU + & ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__core_req_arb__DOT__qual_request_index) + << 5U))))) + | (vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__core_req_arb__DOT__use_per_writedata[ + (3U & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__core_req_arb__DOT__qual_request_index))] + >> (0x1fU + & ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__core_req_arb__DOT__qual_request_index) + << 5U)))) + : 0U))),32); + __Vtemp591[0U] = ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__dfpq_pop_unqual) + ? vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT____Vcellout__dfp_queue__data_out[0U] + : 0x39U); + __Vtemp591[1U] = ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__dfpq_pop_unqual) + ? vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT____Vcellout__dfp_queue__data_out[1U] + : 0U); + __Vtemp591[2U] = ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__dfpq_pop_unqual) + ? vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT____Vcellout__dfp_queue__data_out[2U] + : 0U); + __Vtemp591[3U] = ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__dfpq_pop_unqual) + ? vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT____Vcellout__dfp_queue__data_out[3U] + : 0U); + vcdp->fullArray(c+8457,(__Vtemp591),128); + vcdp->fullQuad(c+8489,(((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cache_miss_resrv__DOT__dequeue_possible) + ? ((VL_ULL(0x1ffffffffff80) + & (((QData)((IData)( + vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cache_miss_resrv__DOT__metadata_table + [vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr][2U])) + << 0x3eU) + | (((QData)((IData)( + vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cache_miss_resrv__DOT__metadata_table + [vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr][1U])) + << 0x1eU) + | (VL_ULL(0x3fffffffffffff80) + & ((QData)((IData)( + vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cache_miss_resrv__DOT__metadata_table + [vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr][0U])) + >> 2U))))) + | (QData)((IData)( + (((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__mrvq_rw_st0) + << 6U) + | ((0x3cU + & ((vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cache_miss_resrv__DOT__metadata_table + [vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr][1U] + << 0x1eU) + | (0x3ffffffcU + & (vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cache_miss_resrv__DOT__metadata_table + [vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr][0U] + >> 2U)))) + | (3U + & ((vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cache_miss_resrv__DOT__metadata_table + [vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr][2U] + << 0xdU) + | (vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cache_miss_resrv__DOT__metadata_table + [vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr][1U] + >> 0x13U)))))))) + : ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__reqq_pop_unqual) + ? ((vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__core_req_arb__DOT__use_per_tag + << 7U) | (QData)((IData)( + (((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__reqq_req_rw_st0) + << 6U) + | ((0x3cU + & (((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__core_req_arb__DOT__use_per_byteen) + >> + (0xfU + & ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__core_req_arb__DOT__qual_request_index) + << 2U))) + << 2U)) + | (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__core_req_arb__DOT__qual_request_index)))))) + : ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__snrq_pop_unqual) + ? ((QData)((IData)( + (0xfffffffU + & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT____Vcellout__snp_req_queue__data_out)))) + << 7U) : VL_ULL(0))))),49); + vcdp->fullBit(c+8505,(((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__dfpq_pop_unqual) + ? 1U : (((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cache_miss_resrv__DOT__dequeue_possible) + & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__mrvq_rw_st0)) + ? 1U : (((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__reqq_pop_unqual) + & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__reqq_req_rw_st0)) + ? 1U + : 0U))))); + vcdp->fullBit(c+8513,((1U & ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cache_miss_resrv__DOT__dequeue_possible) + ? (1U & (vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cache_miss_resrv__DOT__metadata_table + [vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr][0U] + >> 1U)) + : ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__snrq_pop_unqual) + ? 1U : 0U))))); + vcdp->fullBit(c+8521,((1U & ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cache_miss_resrv__DOT__dequeue_possible) + ? (1U & vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cache_miss_resrv__DOT__metadata_table + [vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr][0U]) + : ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__snrq_pop_unqual) + ? (1U & (IData)( + (vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT____Vcellout__snp_req_queue__data_out + >> 0x1cU))) + : 0U))))); + vcdp->fullBit(c+8529,(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__valid_st1[0])); + vcdp->fullBus(c+8537,(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__addr_st1[0]),26); + vcdp->fullBus(c+8545,(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__wsel_st1[0]),2); + vcdp->fullBus(c+8553,(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__writeword_st1[0]),32); + vcdp->fullQuad(c+8561,(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__inst_meta_st1[0]),49); + vcdp->fullArray(c+8577,(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__writedata_st1[0]),128); + vcdp->fullBit(c+8609,(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__is_snp_st1[0])); + vcdp->fullBit(c+8617,(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__snp_invalidate_st1[0])); + vcdp->fullBit(c+8625,(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__is_mrvq_st1[0])); + __Vtemp597[0U] = vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__tag_data_access__DOT__read_data_st1c + [0U][0U]; + __Vtemp597[1U] = vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__tag_data_access__DOT__read_data_st1c + [0U][1U]; + __Vtemp597[2U] = vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__tag_data_access__DOT__read_data_st1c + [0U][2U]; + __Vtemp597[3U] = vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__tag_data_access__DOT__read_data_st1c + [0U][3U]; + vcdp->fullBus(c+8633,((((0U == (0x1fU & (vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__wsel_st1 + [0U] + << 5U))) + ? 0U : (__Vtemp597[ + ((IData)(1U) + + (3U & vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__wsel_st1 + [0U]))] + << ((IData)(0x20U) + - (0x1fU + & (vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__wsel_st1 + [0U] + << 5U))))) + | (__Vtemp597[(3U & + vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__wsel_st1 + [0U])] + >> (0x1fU & (vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__wsel_st1 + [0U] + << 5U))))),32); + __Vtemp598[0U] = vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__tag_data_access__DOT__read_data_st1c + [0U][0U]; + __Vtemp598[1U] = vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__tag_data_access__DOT__read_data_st1c + [0U][1U]; + __Vtemp598[2U] = vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__tag_data_access__DOT__read_data_st1c + [0U][2U]; + __Vtemp598[3U] = vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__tag_data_access__DOT__read_data_st1c + [0U][3U]; + vcdp->fullArray(c+8641,(__Vtemp598),128); + vcdp->fullBus(c+8673,(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__tag_data_access__DOT__read_tag_st1c + [0U]),20); + vcdp->fullBit(c+8681,(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__miss_st1e)); + vcdp->fullBit(c+8689,(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__dirty_st1e)); + vcdp->fullBus(c+8697,(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__tag_data_access__DOT__read_dirtyb_st1c + [0U]),16); + vcdp->fullQuad(c+8705,((VL_ULL(0x3ffffffffff) + & (vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__inst_meta_st1 + [0U] >> 7U))),42); + vcdp->fullBus(c+8721,((3U & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__inst_meta_st1 + [0U]))),2); + vcdp->fullBit(c+8729,((1U & (IData)((vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__inst_meta_st1 + [0U] >> 6U))))); + vcdp->fullBus(c+8737,((0xfU & (IData)((vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__inst_meta_st1 + [0U] + >> 2U)))),4); + vcdp->fullBit(c+8745,(((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__tag_data_access__DOT__real_writefill) + & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__dirty_st1e)))); + vcdp->fullBit(c+8753,(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__is_snp_st1 + [0U])); + vcdp->fullBit(c+8761,(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__snp_invalidate_st1 + [0U])); + vcdp->fullBit(c+8769,(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__snp_to_mrvq_st1e)); + vcdp->fullBit(c+8777,(((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__snp_to_mrvq_st1e) + | ((((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__force_request_miss_st1e) + & (~ vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__is_snp_st1 + [0U])) & (~ + vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__is_fill_st1 + [0U])) + & vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__valid_st1 + [0U])))); + vcdp->fullBit(c+8785,(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__miss_add_because_miss)); + vcdp->fullBit(c+8793,(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__valid_st1 + [0U])); + vcdp->fullBit(c+8801,(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__is_mrvq_st1 + [0U])); + vcdp->fullBit(c+8809,((((vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__valid_st1 + [0U] & vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__is_mrvq_st1 + [0U]) & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__recover_mrvq_state_st2)) + & ((0x3ffffffU & ((vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__st_1e_2__DOT__value[9U] + << 7U) + | (vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__st_1e_2__DOT__value[8U] + >> 0x19U))) + == vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__addr_st1 + [0U])))); + vcdp->fullBus(c+8817,(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__addr_st1 + [0U]),26); + vcdp->fullBit(c+8825,((vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__valid_st1 + [0U] & (~ vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__is_fill_st1 + [0U])))); + vcdp->fullBit(c+8833,(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__mrvq_init_ready_state_st2)); + vcdp->fullBit(c+8841,((((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__miss_add_unqual) + & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__dfpq_pop_unqual)) + & ((0x3ffffffU & ((vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__st_1e_2__DOT__value[9U] + << 7U) + | (vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__st_1e_2__DOT__value[8U] + >> 0x19U))) + == (0x3ffffffU & + vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT____Vcellout__dfp_queue__data_out[4U]))))); + vcdp->fullBit(c+8849,((((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__miss_add_unqual) + & vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__is_fill_st1 + [0U]) & ((0x3ffffffU + & ((vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__st_1e_2__DOT__value[9U] + << 7U) + | (vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__st_1e_2__DOT__value[8U] + >> 0x19U))) + == vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__addr_st1 + [0U])))); + vcdp->fullBit(c+8857,(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__miss_add_unqual)); + vcdp->fullBit(c+8865,(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__miss_add)); + vcdp->fullBit(c+8873,(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__miss_add_is_mrvq)); + vcdp->fullBit(c+8881,(((((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cwbq_push_unqual) + & (~ (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cwb_queue__DOT__genblk3__DOT__genblk2__DOT__full_r))) + & (~ (vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__st_1e_2__DOT__value[0U] + >> 6U))) & (~ + (((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__dwbq_push_stall) + | (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__mrvq_push_stall)) + | (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__dram_fill_req_stall)))))); + vcdp->fullBit(c+8889,(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cwbq_push_unqual)); + vcdp->fullBit(c+8897,(((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__miss_add_unqual) + & ((~ (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__mrvq_init_ready_state_st2)) + | ((vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__st_1e_2__DOT__value[9U] + >> 0x1aU) & (~ + (vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__st_1e_2__DOT__value[9U] + >> 0x1bU))))))); + vcdp->fullBit(c+8905,((((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__dwbq_push_unqual) + & (~ (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__genblk2__DOT__full_r))) + & (~ (((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cwbq_push_stall) + | (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__mrvq_push_stall)) + | (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__dram_fill_req_stall)))))); + vcdp->fullBit(c+8913,(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__dwbq_is_dwb_in)); + vcdp->fullBit(c+8921,(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__dwbq_is_snp_in)); + vcdp->fullBit(c+8929,((1U & (vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT____Vcellout__dwb_queue__data_out[6U] + >> 7U)))); + vcdp->fullBit(c+8937,((1U & (vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT____Vcellout__dwb_queue__data_out[6U] + >> 6U)))); + vcdp->fullBit(c+8945,(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__dwbq_push_unqual)); + vcdp->fullQuad(c+8953,(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT____Vcellout__snp_req_queue__data_out),55); + vcdp->fullBit(c+8969,(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__snp_req_queue__DOT__reading)); + vcdp->fullArray(c+8977,(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT____Vcellout__dfp_queue__data_out),154); + vcdp->fullBit(c+9017,(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__dfp_queue__DOT__reading)); + vcdp->fullBus(c+9025,((0xfU & (vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__core_req_arb__DOT____Vcellout__reqq_queue__data_out[9U] + >> 0x16U))),4); + vcdp->fullBus(c+9033,((0xfU & (vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__core_req_arb__DOT____Vcellout__reqq_queue__data_out[9U] + >> 0x12U))),4); + vcdp->fullBus(c+9041,((0xffffU & (vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__core_req_arb__DOT____Vcellout__reqq_queue__data_out[9U] + >> 2U))),16); + __Vtemp601[0U] = ((vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__core_req_arb__DOT____Vcellout__reqq_queue__data_out[6U] + << 0x16U) | (vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__core_req_arb__DOT____Vcellout__reqq_queue__data_out[5U] + >> 0xaU)); + __Vtemp601[1U] = ((vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__core_req_arb__DOT____Vcellout__reqq_queue__data_out[7U] + << 0x16U) | (vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__core_req_arb__DOT____Vcellout__reqq_queue__data_out[6U] + >> 0xaU)); + __Vtemp601[2U] = ((vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__core_req_arb__DOT____Vcellout__reqq_queue__data_out[8U] + << 0x16U) | (vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__core_req_arb__DOT____Vcellout__reqq_queue__data_out[7U] + >> 0xaU)); + __Vtemp601[3U] = (0xffffffU & ((vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__core_req_arb__DOT____Vcellout__reqq_queue__data_out[9U] + << 0x16U) | + (vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__core_req_arb__DOT____Vcellout__reqq_queue__data_out[8U] + >> 0xaU))); + vcdp->fullArray(c+9049,(__Vtemp601),120); + __Vtemp602[0U] = ((vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__core_req_arb__DOT____Vcellout__reqq_queue__data_out[2U] + << 0x16U) | (vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__core_req_arb__DOT____Vcellout__reqq_queue__data_out[1U] + >> 0xaU)); + __Vtemp602[1U] = ((vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__core_req_arb__DOT____Vcellout__reqq_queue__data_out[3U] + << 0x16U) | (vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__core_req_arb__DOT____Vcellout__reqq_queue__data_out[2U] + >> 0xaU)); + __Vtemp602[2U] = ((vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__core_req_arb__DOT____Vcellout__reqq_queue__data_out[4U] + << 0x16U) | (vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__core_req_arb__DOT____Vcellout__reqq_queue__data_out[3U] + >> 0xaU)); + __Vtemp602[3U] = ((vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__core_req_arb__DOT____Vcellout__reqq_queue__data_out[5U] + << 0x16U) | (vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__core_req_arb__DOT____Vcellout__reqq_queue__data_out[4U] + >> 0xaU)); + vcdp->fullArray(c+9081,(__Vtemp602),128); + vcdp->fullQuad(c+9113,((VL_ULL(0x3ffffffffff) + & (((QData)((IData)( + vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__core_req_arb__DOT____Vcellout__reqq_queue__data_out[1U])) + << 0x20U) | (QData)((IData)( + vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__core_req_arb__DOT____Vcellout__reqq_queue__data_out[0U]))))),42); + vcdp->fullBit(c+9129,(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__core_req_arb__DOT__out_empty)); + vcdp->fullBit(c+9137,(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__core_req_arb__DOT__pop_qual)); + vcdp->fullBus(c+9145,((0xfU & ((vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__core_req_arb__DOT____Vcellout__reqq_queue__data_out[9U] + >> 0x16U) & + VL_NEGATE_I((IData)( + (1U + & (~ (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__core_req_arb__DOT__out_empty)))))))),4); + vcdp->fullArray(c+9153,(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__core_req_arb__DOT____Vcellout__reqq_queue__data_out),314); + vcdp->fullBit(c+9233,(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__reading)); + vcdp->fullBus(c+9241,(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__core_req_arb__DOT__sel_bank__DOT__genblk2__DOT__grant_onehot_r),4); + vcdp->fullBus(c+9249,(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__core_req_arb__DOT__sel_bank__DOT__genblk2__DOT__priority_encoder__DOT__i),32); + vcdp->fullArray(c+9257,(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT____Vcellinp__s0_1_c0__in),243); + vcdp->fullBus(c+9321,((0x3fU & vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__addr_st1 + [0U])),6); + vcdp->fullBit(c+9329,(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__is_fill_st1 + [0U])); + vcdp->fullBus(c+9337,(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__writeword_st1 + [0U]),32); + __Vtemp603[0U] = vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__writedata_st1 + [0U][0U]; + __Vtemp603[1U] = vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__writedata_st1 + [0U][1U]; + __Vtemp603[2U] = vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__writedata_st1 + [0U][2U]; + __Vtemp603[3U] = vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__writedata_st1 + [0U][3U]; + vcdp->fullArray(c+9345,(__Vtemp603),128); + vcdp->fullBus(c+9377,(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__wsel_st1 + [0U]),2); + vcdp->fullBit(c+9385,(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__tag_data_access__DOT__read_valid_st1c[0])); + vcdp->fullBit(c+9393,(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__tag_data_access__DOT__read_dirty_st1c[0])); + vcdp->fullBus(c+9401,(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__tag_data_access__DOT__read_dirtyb_st1c[0]),16); + vcdp->fullBus(c+9409,(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__tag_data_access__DOT__read_tag_st1c[0]),20); + vcdp->fullArray(c+9417,(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__tag_data_access__DOT__read_data_st1c[0]),128); + vcdp->fullBit(c+9449,((1U & (IData)((vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__valid + >> (0x3fU + & vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__addr_st1 + [0U])))))); + vcdp->fullBit(c+9457,((1U & (IData)((vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__dirty + >> (0x3fU + & vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__addr_st1 + [0U])))))); + vcdp->fullBus(c+9465,(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__dirtyb + [(0x3fU & vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__addr_st1 + [0U])]),16); + vcdp->fullBus(c+9473,(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__tag + [(0x3fU & vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__addr_st1 + [0U])]),20); + __Vtemp604[0U] = vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__data + [(0x3fU & vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__addr_st1 + [0U])][0U]; + __Vtemp604[1U] = vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__data + [(0x3fU & vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__addr_st1 + [0U])][1U]; + __Vtemp604[2U] = vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__data + [(0x3fU & vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__addr_st1 + [0U])][2U]; + __Vtemp604[3U] = vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__data + [(0x3fU & vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__addr_st1 + [0U])][3U]; + vcdp->fullArray(c+9481,(__Vtemp604),128); + vcdp->fullBit(c+9513,(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__tag_data_access__DOT__read_valid_st1c + [0U])); + vcdp->fullBit(c+9521,(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__tag_data_access__DOT__read_dirty_st1c + [0U])); + vcdp->fullBus(c+9529,(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__tag_data_access__DOT__use_write_enable),16); + vcdp->fullArray(c+9537,(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__tag_data_access__DOT__data_write),128); + vcdp->fullBit(c+9569,(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__tag_data_access__DOT__snoop_hit_no_pending)); + vcdp->fullBit(c+9577,(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__tag_data_access__DOT__tags_match)); + vcdp->fullBit(c+9585,(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__tag_data_access__DOT__real_writefill)); + vcdp->fullBus(c+9593,((0xfffffU & (vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__addr_st1 + [0U] >> 6U))),20); + vcdp->fullBus(c+9601,(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__tag_data_access__DOT__we),16); + vcdp->fullBit(c+9609,(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__tag_data_access__DOT__should_write)); + vcdp->fullBit(c+9617,((((vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__valid_st1 + [0U] & (~ vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__is_snp_st1 + [0U])) & (~ + vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__tag_data_access__DOT__read_valid_st1c + [0U])) + & (~ vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__is_fill_st1 + [0U])))); + vcdp->fullBit(c+9625,(((((vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__valid_st1 + [0U] & (~ vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__is_snp_st1 + [0U])) & + vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__tag_data_access__DOT__read_valid_st1c + [0U]) & (~ vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__is_fill_st1 + [0U])) & + (~ (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__tag_data_access__DOT__tags_match))))); + vcdp->fullBit(c+9633,(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__tag_data_access__DOT__real_miss)); + vcdp->fullBit(c+9641,((((((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__force_request_miss_st1e) + & (~ vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__is_snp_st1 + [0U])) & (~ vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__is_fill_st1 + [0U])) + & vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__valid_st1 + [0U]) & (~ (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__tag_data_access__DOT__real_miss))))); + vcdp->fullBit(c+9649,(((0U == vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__wsel_st1 + [0U]) & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__tag_data_access__DOT__should_write)))); + vcdp->fullBit(c+9657,(((1U == vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__wsel_st1 + [0U]) & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__tag_data_access__DOT__should_write)))); + vcdp->fullBit(c+9665,(((2U == vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__wsel_st1 + [0U]) & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__tag_data_access__DOT__should_write)))); + vcdp->fullBit(c+9673,(((3U == vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__wsel_st1 + [0U]) & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__tag_data_access__DOT__should_write)))); + vcdp->fullBit(c+9681,((0U != (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__tag_data_access__DOT__use_write_enable)))); + vcdp->fullArray(c+9689,(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__tag_data_access__DOT____Vcellinp__s0_1_c0__in),166); + vcdp->fullArray(c+9737,(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT____Vcellinp__st_1e_2__in),316); + vcdp->fullBus(c+9817,(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cache_miss_resrv__DOT__make_ready),16); + vcdp->fullBus(c+9825,((0xffffU & (((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cache_miss_resrv__DOT__mrvq_push) + & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__mrvq_init_ready_state_st2)) + << (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cache_miss_resrv__DOT__tail_ptr)))),16); + vcdp->fullBus(c+9833,(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cache_miss_resrv__DOT__valid_address_match),16); + vcdp->fullBit(c+9841,(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cache_miss_resrv__DOT__mrvq_push)); + vcdp->fullBit(c+9849,(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cache_miss_resrv__DOT__mrvq_pop)); + vcdp->fullBit(c+9857,(((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__miss_add) + & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__miss_add_is_mrvq)))); + vcdp->fullBit(c+9865,(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cache_miss_resrv__DOT__increment_head)); + vcdp->fullBit(c+9873,((0U != (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cache_miss_resrv__DOT__make_ready)))); + vcdp->fullBit(c+9881,(((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cache_miss_resrv__DOT__mrvq_push) + & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__mrvq_init_ready_state_st2)))); + vcdp->fullArray(c+9889,(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT____Vcellinp__cwb_queue__data_in),76); + vcdp->fullArray(c+9913,(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT____Vcellout__cwb_queue__data_out),76); + vcdp->fullBit(c+9937,(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cwb_queue__DOT__writing)); + vcdp->fullArray(c+9945,(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT____Vcellinp__dwb_queue__data_in),200); + vcdp->fullArray(c+10001,(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT____Vcellout__dwb_queue__data_out),200); + vcdp->fullBit(c+10057,(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__dwb_queue__DOT__writing)); + vcdp->fullBit(c+10065,((1U & (~ (IData)(vlTOPp->VX_cache__DOT__cache_dram_req_arb__DOT__dram_fill_arb__DOT__dfqq_queue__DOT__genblk3__DOT__genblk2__DOT__full_r))))); + vcdp->fullBit(c+10073,((1U & (~ (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cwb_queue__DOT__genblk3__DOT__genblk2__DOT__empty_r))))); + vcdp->fullBit(c+10081,((1U & (~ (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__dfp_queue__DOT__genblk3__DOT__genblk2__DOT__full_r))))); + vcdp->fullBus(c+10089,((0x3ffffffU & ((vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__st_1e_2__DOT__value[9U] + << 7U) + | (vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__st_1e_2__DOT__value[8U] + >> 0x19U)))),26); + vcdp->fullBit(c+10097,((1U & (~ (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__snp_req_queue__DOT__genblk3__DOT__genblk2__DOT__full_r))))); + vcdp->fullBit(c+10105,((1U & (~ (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__full_r))))); + vcdp->fullBit(c+10113,((1U & (~ (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__cwb_queue__DOT__genblk3__DOT__genblk2__DOT__empty_r))))); + vcdp->fullBit(c+10121,((1U & (~ (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__dfp_queue__DOT__genblk3__DOT__genblk2__DOT__full_r))))); + vcdp->fullBus(c+10129,((0x3ffffffU & ((vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__st_1e_2__DOT__value[9U] + << 7U) + | (vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__st_1e_2__DOT__value[8U] + >> 0x19U)))),26); + vcdp->fullBit(c+10137,((1U & (~ (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__snp_req_queue__DOT__genblk3__DOT__genblk2__DOT__full_r))))); + vcdp->fullBit(c+10145,((1U & (~ (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__full_r))))); + vcdp->fullBit(c+10153,((1U & (~ (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__cwb_queue__DOT__genblk3__DOT__genblk2__DOT__empty_r))))); + vcdp->fullBit(c+10161,((1U & (~ (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__dfp_queue__DOT__genblk3__DOT__genblk2__DOT__full_r))))); + vcdp->fullBus(c+10169,((0x3ffffffU & ((vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__st_1e_2__DOT__value[9U] + << 7U) + | (vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__st_1e_2__DOT__value[8U] + >> 0x19U)))),26); + vcdp->fullBit(c+10177,((1U & (~ (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__snp_req_queue__DOT__genblk3__DOT__genblk2__DOT__full_r))))); + vcdp->fullBit(c+10185,((1U & (~ (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__full_r))))); + vcdp->fullBit(c+10193,((1U & (~ (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cwb_queue__DOT__genblk3__DOT__genblk2__DOT__empty_r))))); + vcdp->fullBit(c+10201,((1U & (~ (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__dfp_queue__DOT__genblk3__DOT__genblk2__DOT__full_r))))); + vcdp->fullBus(c+10209,((0x3ffffffU & ((vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__st_1e_2__DOT__value[9U] + << 7U) + | (vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__st_1e_2__DOT__value[8U] + >> 0x19U)))),26); + vcdp->fullBit(c+10217,((1U & (~ (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__snp_req_queue__DOT__genblk3__DOT__genblk2__DOT__full_r))))); + vcdp->fullBit(c+10225,((1U & (~ (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__full_r))))); + vcdp->fullBus(c+10233,(vlTOPp->VX_cache__DOT__cache_dram_req_arb__DOT__prfqq__DOT__use_addr),28); + vcdp->fullBit(c+10241,(vlTOPp->VX_cache__DOT__cache_dram_req_arb__DOT__dram_fill_arb__DOT__dfqq_queue__DOT__genblk3__DOT__genblk2__DOT__full_r)); + vcdp->fullBus(c+10249,(vlTOPp->VX_cache__DOT__cache_dram_req_arb__DOT__prfqq__DOT__use_valid),2); + vcdp->fullBit(c+10257,(vlTOPp->VX_cache__DOT__cache_dram_req_arb__DOT__prfqq__DOT__pfq_queue__DOT__size_r)); + vcdp->fullBus(c+10265,(vlTOPp->VX_cache__DOT__cache_dram_req_arb__DOT__prfqq__DOT__pfq_queue__DOT__genblk2__DOT__head_r),28); + vcdp->fullBit(c+10273,((1U & (~ (IData)(vlTOPp->VX_cache__DOT__cache_dram_req_arb__DOT__prfqq__DOT__pfq_queue__DOT__size_r))))); + vcdp->fullBit(c+10281,(vlTOPp->VX_cache__DOT__cache_dram_req_arb__DOT__prfqq__DOT__pfq_queue__DOT__size_r)); + vcdp->fullBus(c+10289,(vlTOPp->VX_cache__DOT__cache_dram_req_arb__DOT__dram_fill_arb__DOT__use_per_bank_dram_fill_req_valid),4); + vcdp->fullArray(c+10297,(vlTOPp->VX_cache__DOT__cache_dram_req_arb__DOT__dram_fill_arb__DOT__use_per_bank_dram_fill_req_addr),112); + vcdp->fullBit(c+10329,(vlTOPp->VX_cache__DOT__cache_dram_req_arb__DOT__dram_fill_arb__DOT__dfqq_queue__DOT__genblk3__DOT__genblk2__DOT__empty_r)); + vcdp->fullBit(c+10337,((1U & (~ (IData)((0U + != (IData)(vlTOPp->VX_cache__DOT__cache_dram_req_arb__DOT__dram_fill_arb__DOT__use_per_bank_dram_fill_req_valid))))))); + vcdp->fullBus(c+10345,(vlTOPp->VX_cache__DOT__cache_dram_req_arb__DOT__dram_fill_arb__DOT__dfqq_queue__DOT__size_r),3); + vcdp->fullArray(c+10353,(vlTOPp->VX_cache__DOT__cache_dram_req_arb__DOT__dram_fill_arb__DOT__dfqq_queue__DOT__genblk3__DOT__data[0]),116); + vcdp->fullArray(c+10357,(vlTOPp->VX_cache__DOT__cache_dram_req_arb__DOT__dram_fill_arb__DOT__dfqq_queue__DOT__genblk3__DOT__data[1]),116); + vcdp->fullArray(c+10361,(vlTOPp->VX_cache__DOT__cache_dram_req_arb__DOT__dram_fill_arb__DOT__dfqq_queue__DOT__genblk3__DOT__data[2]),116); + vcdp->fullArray(c+10365,(vlTOPp->VX_cache__DOT__cache_dram_req_arb__DOT__dram_fill_arb__DOT__dfqq_queue__DOT__genblk3__DOT__data[3]),116); + vcdp->fullArray(c+10481,(vlTOPp->VX_cache__DOT__cache_dram_req_arb__DOT__dram_fill_arb__DOT__dfqq_queue__DOT__genblk3__DOT__genblk2__DOT__head_r),116); + vcdp->fullArray(c+10513,(vlTOPp->VX_cache__DOT__cache_dram_req_arb__DOT__dram_fill_arb__DOT__dfqq_queue__DOT__genblk3__DOT__genblk2__DOT__curr_r),116); + vcdp->fullBus(c+10545,(vlTOPp->VX_cache__DOT__cache_dram_req_arb__DOT__dram_fill_arb__DOT__dfqq_queue__DOT__genblk3__DOT__genblk2__DOT__wr_ptr_r),2); + vcdp->fullBus(c+10553,(vlTOPp->VX_cache__DOT__cache_dram_req_arb__DOT__dram_fill_arb__DOT__dfqq_queue__DOT__genblk3__DOT__genblk2__DOT__rd_ptr_r),2); + vcdp->fullBus(c+10561,(vlTOPp->VX_cache__DOT__cache_dram_req_arb__DOT__dram_fill_arb__DOT__dfqq_queue__DOT__genblk3__DOT__genblk2__DOT__rd_ptr_next_r),2); + vcdp->fullBit(c+10569,(vlTOPp->VX_cache__DOT__cache_dram_req_arb__DOT__dram_fill_arb__DOT__dfqq_queue__DOT__genblk3__DOT__genblk2__DOT__bypass_r)); + vcdp->fullBus(c+10577,(vlTOPp->VX_cache__DOT__cache_core_rsp_merge__DOT__sel_bank__DOT__genblk2__DOT__requests_use),4); + vcdp->fullBit(c+10585,((0U == (IData)(vlTOPp->VX_cache__DOT__cache_core_rsp_merge__DOT__sel_bank__DOT__genblk2__DOT__requests_use)))); + vcdp->fullBus(c+10593,(vlTOPp->VX_cache__DOT__cache_core_rsp_merge__DOT__sel_bank__DOT__genblk2__DOT__refill_original),4); + vcdp->fullBit(c+10601,(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__snp_req_queue__DOT__genblk3__DOT__genblk2__DOT__empty_r)); + vcdp->fullBit(c+10609,(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__snp_req_queue__DOT__genblk3__DOT__genblk2__DOT__full_r)); + vcdp->fullBit(c+10617,(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__dfp_queue__DOT__genblk3__DOT__genblk2__DOT__empty_r)); + vcdp->fullBit(c+10625,(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__dfp_queue__DOT__genblk3__DOT__genblk2__DOT__full_r)); + vcdp->fullBit(c+10633,(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__full_r)); + vcdp->fullQuad(c+10641,(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__core_req_arb__DOT__use_per_tag),42); + vcdp->fullBit(c+10657,((0x10U == (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cache_miss_resrv__DOT__size)))); + vcdp->fullBit(c+10665,((0xbU < (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cache_miss_resrv__DOT__size)))); + vcdp->fullBus(c+10673,((3U & ((vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cache_miss_resrv__DOT__metadata_table + [vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr][2U] + << 0xdU) | ( + vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cache_miss_resrv__DOT__metadata_table + [vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr][1U] + >> 0x13U)))),2); + vcdp->fullBus(c+10681,(((0x19fU >= (0x1ffU + & ((IData)(0x1aU) + * (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr)))) + ? (0x3ffffffU & (( + (0U + == + (0x1fU + & ((IData)(0x1aU) + * (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr)))) + ? 0U + : + (vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cache_miss_resrv__DOT__addr_table[ + ((IData)(1U) + + + (0xfU + & (((IData)(0x1aU) + * (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr)) + >> 5U)))] + << + ((IData)(0x20U) + - + (0x1fU + & ((IData)(0x1aU) + * (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr)))))) + | (vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cache_miss_resrv__DOT__addr_table[ + (0xfU + & (((IData)(0x1aU) + * (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr)) + >> 5U))] + >> + (0x1fU + & ((IData)(0x1aU) + * (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr)))))) + : 0U)),26); + vcdp->fullBus(c+10689,((3U & ((vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cache_miss_resrv__DOT__metadata_table + [vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr][1U] + << 0x1eU) | + (vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cache_miss_resrv__DOT__metadata_table + [vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr][0U] + >> 2U)))),2); + vcdp->fullBus(c+10697,(((vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cache_miss_resrv__DOT__metadata_table + [vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr][2U] + << 0xbU) | (vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cache_miss_resrv__DOT__metadata_table + [vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr][1U] + >> 0x15U))),32); + vcdp->fullQuad(c+10705,((VL_ULL(0x3ffffffffff) + & (((QData)((IData)( + vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cache_miss_resrv__DOT__metadata_table + [vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr][2U])) + << 0x37U) | (((QData)((IData)( + vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cache_miss_resrv__DOT__metadata_table + [vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr][1U])) + << 0x17U) + | ((QData)((IData)( + vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cache_miss_resrv__DOT__metadata_table + [vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr][0U])) + >> 9U))))),42); + vcdp->fullBus(c+10721,((0xfU & ((vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cache_miss_resrv__DOT__metadata_table + [vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr][1U] + << 0x1cU) + | (vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cache_miss_resrv__DOT__metadata_table + [vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr][0U] + >> 4U)))),4); + vcdp->fullBit(c+10729,((1U & (vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cache_miss_resrv__DOT__metadata_table + [vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr][0U] + >> 1U)))); + vcdp->fullBit(c+10737,((1U & vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cache_miss_resrv__DOT__metadata_table + [vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr][0U]))); + vcdp->fullBus(c+10745,((3U & vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__st_1e_2__DOT__value[0U])),2); + vcdp->fullQuad(c+10753,((VL_ULL(0x3ffffffffff) + & (((QData)((IData)( + vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__st_1e_2__DOT__value[2U])) + << 0x39U) | (((QData)((IData)( + vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__st_1e_2__DOT__value[1U])) + << 0x19U) + | ((QData)((IData)( + vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__st_1e_2__DOT__value[0U])) + >> 7U))))),42); + vcdp->fullBit(c+10769,((1U & (vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__st_1e_2__DOT__value[0U] + >> 6U)))); + vcdp->fullBus(c+10777,((0xfU & ((vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__st_1e_2__DOT__value[1U] + << 0x1eU) + | (vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__st_1e_2__DOT__value[0U] + >> 2U)))),4); + vcdp->fullBit(c+10785,((1U & (vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__st_1e_2__DOT__value[9U] + >> 0x14U)))); + vcdp->fullBit(c+10793,((1U & (vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__st_1e_2__DOT__value[9U] + >> 0x13U)))); + vcdp->fullBus(c+10801,((3U & ((vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__st_1e_2__DOT__value[9U] + << 9U) | (vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__st_1e_2__DOT__value[8U] + >> 0x17U)))),2); + vcdp->fullBus(c+10809,(((vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__st_1e_2__DOT__value[8U] + << 9U) | (vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__st_1e_2__DOT__value[7U] + >> 0x17U))),32); + vcdp->fullBus(c+10817,(((vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__st_1e_2__DOT__value[7U] + << 9U) | (vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__st_1e_2__DOT__value[6U] + >> 0x17U))),32); + __Vtemp612[0U] = ((vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__st_1e_2__DOT__value[3U] + << 9U) | (vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__st_1e_2__DOT__value[2U] + >> 0x17U)); + __Vtemp612[1U] = ((vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__st_1e_2__DOT__value[4U] + << 9U) | (vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__st_1e_2__DOT__value[3U] + >> 0x17U)); + __Vtemp612[2U] = ((vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__st_1e_2__DOT__value[5U] + << 9U) | (vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__st_1e_2__DOT__value[4U] + >> 0x17U)); + __Vtemp612[3U] = ((vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__st_1e_2__DOT__value[6U] + << 9U) | (vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__st_1e_2__DOT__value[5U] + >> 0x17U)); + vcdp->fullArray(c+10825,(__Vtemp612),128); + vcdp->fullBit(c+10857,((1U & (vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__st_1e_2__DOT__value[2U] + >> 2U)))); + vcdp->fullBit(c+10865,((1U & (vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__st_1e_2__DOT__value[2U] + >> 1U)))); + vcdp->fullBus(c+10873,((0xffffU & ((vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__st_1e_2__DOT__value[2U] + << 0xfU) + | (vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__st_1e_2__DOT__value[1U] + >> 0x11U)))),16); + vcdp->fullQuad(c+10881,((VL_ULL(0x1ffffffffffff) + & (((QData)((IData)( + vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__st_1e_2__DOT__value[1U])) + << 0x20U) | (QData)((IData)( + vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__st_1e_2__DOT__value[0U]))))),49); + vcdp->fullBus(c+10897,((0xfffffU & ((vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__st_1e_2__DOT__value[3U] + << 0x1dU) + | (vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__st_1e_2__DOT__value[2U] + >> 3U)))),20); + vcdp->fullBit(c+10905,((1U & (vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__st_1e_2__DOT__value[9U] + >> 0x15U)))); + vcdp->fullBit(c+10913,((1U & (vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__st_1e_2__DOT__value[9U] + >> 0x17U)))); + vcdp->fullBit(c+10921,((1U & (vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__st_1e_2__DOT__value[9U] + >> 0x16U)))); + vcdp->fullBit(c+10929,((1U & (vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__st_1e_2__DOT__value[9U] + >> 0x18U)))); + vcdp->fullBit(c+10937,((1U & (vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__st_1e_2__DOT__value[9U] + >> 0x1aU)))); + vcdp->fullBit(c+10945,((1U & (vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__st_1e_2__DOT__value[9U] + >> 0x1bU)))); + vcdp->fullBit(c+10953,((1U & (vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__st_1e_2__DOT__value[9U] + >> 0x19U)))); + vcdp->fullBit(c+10961,(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cwb_queue__DOT__genblk3__DOT__genblk2__DOT__empty_r)); + vcdp->fullBit(c+10969,(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cwb_queue__DOT__genblk3__DOT__genblk2__DOT__full_r)); + vcdp->fullBit(c+10977,(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__genblk2__DOT__empty_r)); + vcdp->fullBit(c+10985,(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__genblk2__DOT__full_r)); + vcdp->fullBus(c+10993,(((0x3ffffc0U & (vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__st_1e_2__DOT__value[2U] + << 3U)) + | (0x3fU & ((vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__st_1e_2__DOT__value[9U] + << 7U) + | (vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__st_1e_2__DOT__value[8U] + >> 0x19U))))),26); + vcdp->fullBus(c+11001,((0xfffffffU & ((vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__st_1e_2__DOT__value[1U] + << 0x19U) + | (vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__st_1e_2__DOT__value[0U] + >> 7U)))),28); + vcdp->fullBit(c+11009,(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__dwbq_dual_valid_sel)); + vcdp->fullBus(c+11017,(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__snp_req_queue__DOT__size_r),5); + vcdp->fullQuad(c+11025,(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__snp_req_queue__DOT__genblk3__DOT__data[0]),55); + vcdp->fullQuad(c+11027,(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__snp_req_queue__DOT__genblk3__DOT__data[1]),55); + vcdp->fullQuad(c+11029,(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__snp_req_queue__DOT__genblk3__DOT__data[2]),55); + vcdp->fullQuad(c+11031,(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__snp_req_queue__DOT__genblk3__DOT__data[3]),55); + vcdp->fullQuad(c+11033,(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__snp_req_queue__DOT__genblk3__DOT__data[4]),55); + vcdp->fullQuad(c+11035,(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__snp_req_queue__DOT__genblk3__DOT__data[5]),55); + vcdp->fullQuad(c+11037,(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__snp_req_queue__DOT__genblk3__DOT__data[6]),55); + vcdp->fullQuad(c+11039,(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__snp_req_queue__DOT__genblk3__DOT__data[7]),55); + vcdp->fullQuad(c+11041,(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__snp_req_queue__DOT__genblk3__DOT__data[8]),55); + vcdp->fullQuad(c+11043,(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__snp_req_queue__DOT__genblk3__DOT__data[9]),55); + vcdp->fullQuad(c+11045,(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__snp_req_queue__DOT__genblk3__DOT__data[10]),55); + vcdp->fullQuad(c+11047,(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__snp_req_queue__DOT__genblk3__DOT__data[11]),55); + vcdp->fullQuad(c+11049,(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__snp_req_queue__DOT__genblk3__DOT__data[12]),55); + vcdp->fullQuad(c+11051,(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__snp_req_queue__DOT__genblk3__DOT__data[13]),55); + vcdp->fullQuad(c+11053,(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__snp_req_queue__DOT__genblk3__DOT__data[14]),55); + vcdp->fullQuad(c+11055,(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__snp_req_queue__DOT__genblk3__DOT__data[15]),55); + vcdp->fullQuad(c+11281,(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__snp_req_queue__DOT__genblk3__DOT__genblk2__DOT__head_r),55); + vcdp->fullQuad(c+11297,(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__snp_req_queue__DOT__genblk3__DOT__genblk2__DOT__curr_r),55); + vcdp->fullBus(c+11313,(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__snp_req_queue__DOT__genblk3__DOT__genblk2__DOT__wr_ptr_r),4); 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+ vcdp->fullBit(c+12201,((1U & (~ (IData)((0U + != (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__core_req_arb__DOT__use_per_valids))))))); + vcdp->fullBus(c+12209,(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__size_r),3); + vcdp->fullArray(c+12217,(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__data[0]),314); + vcdp->fullArray(c+12227,(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__data[1]),314); + vcdp->fullArray(c+12237,(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__data[2]),314); + vcdp->fullArray(c+12247,(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__data[3]),314); + vcdp->fullArray(c+12537,(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__head_r),314); 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+ vcdp->fullQuad(c+12809,(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__valid),64); + vcdp->fullBus(c+12825,(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__i),32); + vcdp->fullBus(c+12833,(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__j),32); + vcdp->fullArray(c+12841,(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__tag_data_access__DOT__s0_1_c0__DOT__value),166); + vcdp->fullArray(c+12889,(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__st_1e_2__DOT__value),316); + vcdp->fullArray(c+12969,(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cache_miss_resrv__DOT__metadata_table[0]),85); + vcdp->fullArray(c+12972,(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cache_miss_resrv__DOT__metadata_table[1]),85); + vcdp->fullArray(c+12975,(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cache_miss_resrv__DOT__metadata_table[2]),85); + vcdp->fullArray(c+12978,(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cache_miss_resrv__DOT__metadata_table[3]),85); + vcdp->fullArray(c+12981,(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cache_miss_resrv__DOT__metadata_table[4]),85); + vcdp->fullArray(c+12984,(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cache_miss_resrv__DOT__metadata_table[5]),85); + vcdp->fullArray(c+12987,(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cache_miss_resrv__DOT__metadata_table[6]),85); + vcdp->fullArray(c+12990,(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cache_miss_resrv__DOT__metadata_table[7]),85); + vcdp->fullArray(c+12993,(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cache_miss_resrv__DOT__metadata_table[8]),85); + vcdp->fullArray(c+12996,(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cache_miss_resrv__DOT__metadata_table[9]),85); + vcdp->fullArray(c+12999,(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cache_miss_resrv__DOT__metadata_table[10]),85); + vcdp->fullArray(c+13002,(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cache_miss_resrv__DOT__metadata_table[11]),85); + vcdp->fullArray(c+13005,(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cache_miss_resrv__DOT__metadata_table[12]),85); + vcdp->fullArray(c+13008,(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cache_miss_resrv__DOT__metadata_table[13]),85); + vcdp->fullArray(c+13011,(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cache_miss_resrv__DOT__metadata_table[14]),85); + vcdp->fullArray(c+13014,(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cache_miss_resrv__DOT__metadata_table[15]),85); + vcdp->fullArray(c+13353,(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cache_miss_resrv__DOT__addr_table),416); + vcdp->fullBus(c+13457,(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cache_miss_resrv__DOT__valid_table),16); + vcdp->fullBus(c+13465,(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cache_miss_resrv__DOT__ready_table),16); + vcdp->fullBus(c+13473,(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr),4); + vcdp->fullBus(c+13481,(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cache_miss_resrv__DOT__head_ptr),4); + vcdp->fullBus(c+13489,(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cache_miss_resrv__DOT__tail_ptr),4); + vcdp->fullBus(c+13497,(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cache_miss_resrv__DOT__size),5); + vcdp->fullBit(c+13505,((0x10U != (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cache_miss_resrv__DOT__size)))); + vcdp->fullBus(c+13513,(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cwb_queue__DOT__size_r),3); + vcdp->fullArray(c+13521,(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cwb_queue__DOT__genblk3__DOT__data[0]),76); + vcdp->fullArray(c+13524,(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cwb_queue__DOT__genblk3__DOT__data[1]),76); + vcdp->fullArray(c+13527,(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cwb_queue__DOT__genblk3__DOT__data[2]),76); + vcdp->fullArray(c+13530,(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cwb_queue__DOT__genblk3__DOT__data[3]),76); + vcdp->fullArray(c+13617,(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cwb_queue__DOT__genblk3__DOT__genblk2__DOT__head_r),76); + vcdp->fullArray(c+13641,(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cwb_queue__DOT__genblk3__DOT__genblk2__DOT__curr_r),76); + vcdp->fullBus(c+13665,(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cwb_queue__DOT__genblk3__DOT__genblk2__DOT__wr_ptr_r),2); + vcdp->fullBus(c+13673,(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cwb_queue__DOT__genblk3__DOT__genblk2__DOT__rd_ptr_r),2); + vcdp->fullBus(c+13681,(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cwb_queue__DOT__genblk3__DOT__genblk2__DOT__rd_ptr_next_r),2); + vcdp->fullBit(c+13689,(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cwb_queue__DOT__genblk3__DOT__genblk2__DOT__bypass_r)); + vcdp->fullBus(c+13697,(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__dwb_queue__DOT__size_r),3); + vcdp->fullArray(c+13705,(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__data[0]),200); + vcdp->fullArray(c+13712,(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__data[1]),200); + vcdp->fullArray(c+13719,(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__data[2]),200); + vcdp->fullArray(c+13726,(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__data[3]),200); + vcdp->fullArray(c+13929,(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__genblk2__DOT__head_r),200); + vcdp->fullArray(c+13985,(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__genblk2__DOT__curr_r),200); + vcdp->fullBus(c+14041,(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__genblk2__DOT__wr_ptr_r),2); + vcdp->fullBus(c+14049,(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__genblk2__DOT__rd_ptr_r),2); + vcdp->fullBus(c+14057,(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__genblk2__DOT__rd_ptr_next_r),2); + vcdp->fullBit(c+14065,(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__genblk2__DOT__bypass_r)); + vcdp->fullBit(c+14073,(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__snp_req_queue__DOT__genblk3__DOT__genblk2__DOT__empty_r)); + vcdp->fullBit(c+14081,(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__snp_req_queue__DOT__genblk3__DOT__genblk2__DOT__full_r)); + vcdp->fullBit(c+14089,(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__dfp_queue__DOT__genblk3__DOT__genblk2__DOT__empty_r)); + vcdp->fullBit(c+14097,(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__dfp_queue__DOT__genblk3__DOT__genblk2__DOT__full_r)); + vcdp->fullBit(c+14105,(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__full_r)); + vcdp->fullQuad(c+14113,(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__core_req_arb__DOT__use_per_tag),42); + vcdp->fullBit(c+14129,((0x10U == (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__cache_miss_resrv__DOT__size)))); + vcdp->fullBit(c+14137,((0xbU < (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__cache_miss_resrv__DOT__size)))); + vcdp->fullBus(c+14145,((3U & ((vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__cache_miss_resrv__DOT__metadata_table + [vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr][2U] + << 0xdU) | ( + vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__cache_miss_resrv__DOT__metadata_table + [vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr][1U] + >> 0x13U)))),2); + vcdp->fullBus(c+14153,(((0x19fU >= (0x1ffU + & ((IData)(0x1aU) + * (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr)))) + ? (0x3ffffffU & (( + (0U + == + (0x1fU + & ((IData)(0x1aU) + * (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr)))) + ? 0U + : + (vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__cache_miss_resrv__DOT__addr_table[ + ((IData)(1U) + + + (0xfU + & (((IData)(0x1aU) + * (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr)) + >> 5U)))] + << + ((IData)(0x20U) + - + (0x1fU + & ((IData)(0x1aU) + * (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr)))))) + | (vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__cache_miss_resrv__DOT__addr_table[ + (0xfU + & (((IData)(0x1aU) + * (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr)) + >> 5U))] + >> + (0x1fU + & ((IData)(0x1aU) + * (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr)))))) + : 0U)),26); + vcdp->fullBus(c+14161,((3U & ((vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__cache_miss_resrv__DOT__metadata_table + [vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr][1U] + << 0x1eU) | + (vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__cache_miss_resrv__DOT__metadata_table + [vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr][0U] + >> 2U)))),2); + vcdp->fullBus(c+14169,(((vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__cache_miss_resrv__DOT__metadata_table + [vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr][2U] + << 0xbU) | (vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__cache_miss_resrv__DOT__metadata_table + [vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr][1U] + >> 0x15U))),32); + vcdp->fullQuad(c+14177,((VL_ULL(0x3ffffffffff) + & (((QData)((IData)( + vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__cache_miss_resrv__DOT__metadata_table + [vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr][2U])) + << 0x37U) | (((QData)((IData)( + vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__cache_miss_resrv__DOT__metadata_table + [vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr][1U])) + << 0x17U) + | ((QData)((IData)( + vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__cache_miss_resrv__DOT__metadata_table + [vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr][0U])) + >> 9U))))),42); + vcdp->fullBus(c+14193,((0xfU & ((vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__cache_miss_resrv__DOT__metadata_table + [vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr][1U] + << 0x1cU) + | (vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__cache_miss_resrv__DOT__metadata_table + [vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr][0U] + >> 4U)))),4); + vcdp->fullBit(c+14201,((1U & (vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__cache_miss_resrv__DOT__metadata_table + [vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr][0U] + >> 1U)))); + vcdp->fullBit(c+14209,((1U & vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__cache_miss_resrv__DOT__metadata_table + [vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr][0U]))); + vcdp->fullBus(c+14217,((3U & vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__st_1e_2__DOT__value[0U])),2); + vcdp->fullQuad(c+14225,((VL_ULL(0x3ffffffffff) + & (((QData)((IData)( + vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__st_1e_2__DOT__value[2U])) + << 0x39U) | (((QData)((IData)( + vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__st_1e_2__DOT__value[1U])) + << 0x19U) + | ((QData)((IData)( + vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__st_1e_2__DOT__value[0U])) + >> 7U))))),42); + vcdp->fullBit(c+14241,((1U & (vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__st_1e_2__DOT__value[0U] + >> 6U)))); + vcdp->fullBus(c+14249,((0xfU & ((vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__st_1e_2__DOT__value[1U] + << 0x1eU) + | (vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__st_1e_2__DOT__value[0U] + >> 2U)))),4); + vcdp->fullBit(c+14257,((1U & (vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__st_1e_2__DOT__value[9U] + >> 0x14U)))); + vcdp->fullBit(c+14265,((1U & (vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__st_1e_2__DOT__value[9U] + >> 0x13U)))); + vcdp->fullBus(c+14273,((3U & ((vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__st_1e_2__DOT__value[9U] + << 9U) | (vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__st_1e_2__DOT__value[8U] + >> 0x17U)))),2); + vcdp->fullBus(c+14281,(((vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__st_1e_2__DOT__value[8U] + << 9U) | (vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__st_1e_2__DOT__value[7U] + >> 0x17U))),32); + vcdp->fullBus(c+14289,(((vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__st_1e_2__DOT__value[7U] + << 9U) | (vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__st_1e_2__DOT__value[6U] + >> 0x17U))),32); + __Vtemp620[0U] = ((vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__st_1e_2__DOT__value[3U] + << 9U) | (vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__st_1e_2__DOT__value[2U] + >> 0x17U)); + __Vtemp620[1U] = ((vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__st_1e_2__DOT__value[4U] + << 9U) | (vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__st_1e_2__DOT__value[3U] + >> 0x17U)); + __Vtemp620[2U] = ((vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__st_1e_2__DOT__value[5U] + << 9U) | (vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__st_1e_2__DOT__value[4U] + >> 0x17U)); + __Vtemp620[3U] = ((vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__st_1e_2__DOT__value[6U] + << 9U) | (vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__st_1e_2__DOT__value[5U] + >> 0x17U)); + vcdp->fullArray(c+14297,(__Vtemp620),128); + vcdp->fullBit(c+14329,((1U & (vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__st_1e_2__DOT__value[2U] + >> 2U)))); + vcdp->fullBit(c+14337,((1U & (vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__st_1e_2__DOT__value[2U] + >> 1U)))); + vcdp->fullBus(c+14345,((0xffffU & ((vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__st_1e_2__DOT__value[2U] + << 0xfU) + | (vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__st_1e_2__DOT__value[1U] + >> 0x11U)))),16); + vcdp->fullQuad(c+14353,((VL_ULL(0x1ffffffffffff) + & (((QData)((IData)( + vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__st_1e_2__DOT__value[1U])) + << 0x20U) | (QData)((IData)( + vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__st_1e_2__DOT__value[0U]))))),49); + vcdp->fullBus(c+14369,((0xfffffU & ((vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__st_1e_2__DOT__value[3U] + << 0x1dU) + | (vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__st_1e_2__DOT__value[2U] + >> 3U)))),20); + vcdp->fullBit(c+14377,((1U & (vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__st_1e_2__DOT__value[9U] + >> 0x15U)))); + vcdp->fullBit(c+14385,((1U & (vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__st_1e_2__DOT__value[9U] + >> 0x17U)))); + vcdp->fullBit(c+14393,((1U & (vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__st_1e_2__DOT__value[9U] + >> 0x16U)))); + vcdp->fullBit(c+14401,((1U & (vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__st_1e_2__DOT__value[9U] + >> 0x18U)))); + vcdp->fullBit(c+14409,((1U & (vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__st_1e_2__DOT__value[9U] + >> 0x1aU)))); + vcdp->fullBit(c+14417,((1U & (vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__st_1e_2__DOT__value[9U] + >> 0x1bU)))); + vcdp->fullBit(c+14425,((1U & (vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__st_1e_2__DOT__value[9U] + >> 0x19U)))); + vcdp->fullBit(c+14433,(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__cwb_queue__DOT__genblk3__DOT__genblk2__DOT__empty_r)); + vcdp->fullBit(c+14441,(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__cwb_queue__DOT__genblk3__DOT__genblk2__DOT__full_r)); + vcdp->fullBit(c+14449,(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__genblk2__DOT__empty_r)); + vcdp->fullBit(c+14457,(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__genblk2__DOT__full_r)); + vcdp->fullBus(c+14465,(((0x3ffffc0U & (vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__st_1e_2__DOT__value[2U] + << 3U)) + | (0x3fU & ((vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__st_1e_2__DOT__value[9U] + << 7U) + | (vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__st_1e_2__DOT__value[8U] + >> 0x19U))))),26); + vcdp->fullBus(c+14473,((0xfffffffU & ((vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__st_1e_2__DOT__value[1U] + << 0x19U) + | (vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__st_1e_2__DOT__value[0U] + >> 7U)))),28); + vcdp->fullBit(c+14481,(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__dwbq_dual_valid_sel)); + vcdp->fullBus(c+14489,(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__snp_req_queue__DOT__size_r),5); + vcdp->fullQuad(c+14497,(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__snp_req_queue__DOT__genblk3__DOT__data[0]),55); + vcdp->fullQuad(c+14499,(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__snp_req_queue__DOT__genblk3__DOT__data[1]),55); + vcdp->fullQuad(c+14501,(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__snp_req_queue__DOT__genblk3__DOT__data[2]),55); + vcdp->fullQuad(c+14503,(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__snp_req_queue__DOT__genblk3__DOT__data[3]),55); + vcdp->fullQuad(c+14505,(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__snp_req_queue__DOT__genblk3__DOT__data[4]),55); + vcdp->fullQuad(c+14507,(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__snp_req_queue__DOT__genblk3__DOT__data[5]),55); + vcdp->fullQuad(c+14509,(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__snp_req_queue__DOT__genblk3__DOT__data[6]),55); + vcdp->fullQuad(c+14511,(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__snp_req_queue__DOT__genblk3__DOT__data[7]),55); + vcdp->fullQuad(c+14513,(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__snp_req_queue__DOT__genblk3__DOT__data[8]),55); + vcdp->fullQuad(c+14515,(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__snp_req_queue__DOT__genblk3__DOT__data[9]),55); + vcdp->fullQuad(c+14517,(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__snp_req_queue__DOT__genblk3__DOT__data[10]),55); + vcdp->fullQuad(c+14519,(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__snp_req_queue__DOT__genblk3__DOT__data[11]),55); + vcdp->fullQuad(c+14521,(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__snp_req_queue__DOT__genblk3__DOT__data[12]),55); + vcdp->fullQuad(c+14523,(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__snp_req_queue__DOT__genblk3__DOT__data[13]),55); + vcdp->fullQuad(c+14525,(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__snp_req_queue__DOT__genblk3__DOT__data[14]),55); + vcdp->fullQuad(c+14527,(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__snp_req_queue__DOT__genblk3__DOT__data[15]),55); + vcdp->fullQuad(c+14753,(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__snp_req_queue__DOT__genblk3__DOT__genblk2__DOT__head_r),55); + vcdp->fullQuad(c+14769,(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__snp_req_queue__DOT__genblk3__DOT__genblk2__DOT__curr_r),55); + vcdp->fullBus(c+14785,(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__snp_req_queue__DOT__genblk3__DOT__genblk2__DOT__wr_ptr_r),4); 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+ vcdp->fullArray(c+14845,(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__dfp_queue__DOT__genblk3__DOT__data[4]),154); + vcdp->fullArray(c+14850,(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__dfp_queue__DOT__genblk3__DOT__data[5]),154); + vcdp->fullArray(c+14855,(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__dfp_queue__DOT__genblk3__DOT__data[6]),154); + vcdp->fullArray(c+14860,(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__dfp_queue__DOT__genblk3__DOT__data[7]),154); + vcdp->fullArray(c+14865,(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__dfp_queue__DOT__genblk3__DOT__data[8]),154); + vcdp->fullArray(c+14870,(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__dfp_queue__DOT__genblk3__DOT__data[9]),154); + vcdp->fullArray(c+14875,(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__dfp_queue__DOT__genblk3__DOT__data[10]),154); + vcdp->fullArray(c+14880,(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__dfp_queue__DOT__genblk3__DOT__data[11]),154); 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+ vcdp->fullBus(c+15561,(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__dfp_queue__DOT__genblk3__DOT__genblk2__DOT__rd_ptr_next_r),4); + vcdp->fullBit(c+15569,(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__dfp_queue__DOT__genblk3__DOT__genblk2__DOT__bypass_r)); + vcdp->fullBus(c+15577,(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__core_req_arb__DOT__use_per_valids),4); + vcdp->fullBus(c+15585,(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__core_req_arb__DOT__use_per_rw),4); + vcdp->fullBus(c+15593,(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__core_req_arb__DOT__use_per_byteen),16); + vcdp->fullArray(c+15601,(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__core_req_arb__DOT__use_per_addr),120); + vcdp->fullArray(c+15633,(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__core_req_arb__DOT__use_per_writedata),128); + vcdp->fullBit(c+15665,(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__empty_r)); + vcdp->fullBit(c+15673,((1U & (~ (IData)((0U + != (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__core_req_arb__DOT__use_per_valids))))))); + vcdp->fullBus(c+15681,(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__size_r),3); + vcdp->fullArray(c+15689,(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__data[0]),314); + vcdp->fullArray(c+15699,(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__data[1]),314); + vcdp->fullArray(c+15709,(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__data[2]),314); + vcdp->fullArray(c+15719,(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__data[3]),314); + vcdp->fullArray(c+16009,(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__head_r),314); + vcdp->fullArray(c+16089,(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__curr_r),314); + vcdp->fullBus(c+16169,(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__wr_ptr_r),2); + vcdp->fullBus(c+16177,(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__rd_ptr_r),2); + vcdp->fullBus(c+16185,(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__rd_ptr_next_r),2); + vcdp->fullBit(c+16193,(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__bypass_r)); + vcdp->fullArray(c+16201,(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__s0_1_c0__DOT__value),243); + vcdp->fullQuad(c+16265,(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__dirty),64); + vcdp->fullQuad(c+16281,(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__valid),64); + vcdp->fullBus(c+16297,(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__i),32); + vcdp->fullBus(c+16305,(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__j),32); + vcdp->fullArray(c+16313,(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__tag_data_access__DOT__s0_1_c0__DOT__value),166); + vcdp->fullArray(c+16361,(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__st_1e_2__DOT__value),316); + vcdp->fullArray(c+16441,(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__cache_miss_resrv__DOT__metadata_table[0]),85); + vcdp->fullArray(c+16444,(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__cache_miss_resrv__DOT__metadata_table[1]),85); + vcdp->fullArray(c+16447,(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__cache_miss_resrv__DOT__metadata_table[2]),85); + vcdp->fullArray(c+16450,(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__cache_miss_resrv__DOT__metadata_table[3]),85); + vcdp->fullArray(c+16453,(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__cache_miss_resrv__DOT__metadata_table[4]),85); + vcdp->fullArray(c+16456,(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__cache_miss_resrv__DOT__metadata_table[5]),85); + vcdp->fullArray(c+16459,(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__cache_miss_resrv__DOT__metadata_table[6]),85); + vcdp->fullArray(c+16462,(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__cache_miss_resrv__DOT__metadata_table[7]),85); + vcdp->fullArray(c+16465,(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__cache_miss_resrv__DOT__metadata_table[8]),85); + vcdp->fullArray(c+16468,(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__cache_miss_resrv__DOT__metadata_table[9]),85); + vcdp->fullArray(c+16471,(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__cache_miss_resrv__DOT__metadata_table[10]),85); + vcdp->fullArray(c+16474,(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__cache_miss_resrv__DOT__metadata_table[11]),85); + vcdp->fullArray(c+16477,(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__cache_miss_resrv__DOT__metadata_table[12]),85); + vcdp->fullArray(c+16480,(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__cache_miss_resrv__DOT__metadata_table[13]),85); + vcdp->fullArray(c+16483,(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__cache_miss_resrv__DOT__metadata_table[14]),85); + vcdp->fullArray(c+16486,(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__cache_miss_resrv__DOT__metadata_table[15]),85); + vcdp->fullArray(c+16825,(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__cache_miss_resrv__DOT__addr_table),416); + vcdp->fullBus(c+16929,(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__cache_miss_resrv__DOT__valid_table),16); + vcdp->fullBus(c+16937,(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__cache_miss_resrv__DOT__ready_table),16); + vcdp->fullBus(c+16945,(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr),4); + vcdp->fullBus(c+16953,(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__cache_miss_resrv__DOT__head_ptr),4); + vcdp->fullBus(c+16961,(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__cache_miss_resrv__DOT__tail_ptr),4); + vcdp->fullBus(c+16969,(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__cache_miss_resrv__DOT__size),5); + vcdp->fullBit(c+16977,((0x10U != (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__cache_miss_resrv__DOT__size)))); + vcdp->fullBus(c+16985,(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__cwb_queue__DOT__size_r),3); + vcdp->fullArray(c+16993,(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__cwb_queue__DOT__genblk3__DOT__data[0]),76); + vcdp->fullArray(c+16996,(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__cwb_queue__DOT__genblk3__DOT__data[1]),76); + vcdp->fullArray(c+16999,(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__cwb_queue__DOT__genblk3__DOT__data[2]),76); + vcdp->fullArray(c+17002,(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__cwb_queue__DOT__genblk3__DOT__data[3]),76); + vcdp->fullArray(c+17089,(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__cwb_queue__DOT__genblk3__DOT__genblk2__DOT__head_r),76); + vcdp->fullArray(c+17113,(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__cwb_queue__DOT__genblk3__DOT__genblk2__DOT__curr_r),76); + vcdp->fullBus(c+17137,(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__cwb_queue__DOT__genblk3__DOT__genblk2__DOT__wr_ptr_r),2); + vcdp->fullBus(c+17145,(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__cwb_queue__DOT__genblk3__DOT__genblk2__DOT__rd_ptr_r),2); + vcdp->fullBus(c+17153,(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__cwb_queue__DOT__genblk3__DOT__genblk2__DOT__rd_ptr_next_r),2); + vcdp->fullBit(c+17161,(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__cwb_queue__DOT__genblk3__DOT__genblk2__DOT__bypass_r)); + vcdp->fullBus(c+17169,(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__dwb_queue__DOT__size_r),3); + vcdp->fullArray(c+17177,(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__data[0]),200); + vcdp->fullArray(c+17184,(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__data[1]),200); + vcdp->fullArray(c+17191,(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__data[2]),200); + vcdp->fullArray(c+17198,(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__data[3]),200); + vcdp->fullArray(c+17401,(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__genblk2__DOT__head_r),200); + vcdp->fullArray(c+17457,(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__genblk2__DOT__curr_r),200); + vcdp->fullBus(c+17513,(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__genblk2__DOT__wr_ptr_r),2); + vcdp->fullBus(c+17521,(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__genblk2__DOT__rd_ptr_r),2); + vcdp->fullBus(c+17529,(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__genblk2__DOT__rd_ptr_next_r),2); + vcdp->fullBit(c+17537,(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__genblk2__DOT__bypass_r)); + vcdp->fullBit(c+17545,(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__snp_req_queue__DOT__genblk3__DOT__genblk2__DOT__empty_r)); + vcdp->fullBit(c+17553,(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__snp_req_queue__DOT__genblk3__DOT__genblk2__DOT__full_r)); + vcdp->fullBit(c+17561,(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__dfp_queue__DOT__genblk3__DOT__genblk2__DOT__empty_r)); + vcdp->fullBit(c+17569,(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__dfp_queue__DOT__genblk3__DOT__genblk2__DOT__full_r)); + vcdp->fullBit(c+17577,(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__full_r)); + vcdp->fullQuad(c+17585,(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__core_req_arb__DOT__use_per_tag),42); + vcdp->fullBit(c+17601,((0x10U == (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__cache_miss_resrv__DOT__size)))); + vcdp->fullBit(c+17609,((0xbU < (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__cache_miss_resrv__DOT__size)))); + vcdp->fullBus(c+17617,((3U & ((vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__cache_miss_resrv__DOT__metadata_table + [vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr][2U] + << 0xdU) | ( + vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__cache_miss_resrv__DOT__metadata_table + [vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr][1U] + >> 0x13U)))),2); + vcdp->fullBus(c+17625,(((0x19fU >= (0x1ffU + & ((IData)(0x1aU) + * (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr)))) + ? (0x3ffffffU & (( + (0U + == + (0x1fU + & ((IData)(0x1aU) + * (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr)))) + ? 0U + : + (vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__cache_miss_resrv__DOT__addr_table[ + ((IData)(1U) + + + (0xfU + & (((IData)(0x1aU) + * (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr)) + >> 5U)))] + << + ((IData)(0x20U) + - + (0x1fU + & ((IData)(0x1aU) + * (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr)))))) + | (vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__cache_miss_resrv__DOT__addr_table[ + (0xfU + & (((IData)(0x1aU) + * (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr)) + >> 5U))] + >> + (0x1fU + & ((IData)(0x1aU) + * (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr)))))) + : 0U)),26); + vcdp->fullBus(c+17633,((3U & ((vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__cache_miss_resrv__DOT__metadata_table + [vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr][1U] + << 0x1eU) | + (vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__cache_miss_resrv__DOT__metadata_table + [vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr][0U] + >> 2U)))),2); + vcdp->fullBus(c+17641,(((vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__cache_miss_resrv__DOT__metadata_table + [vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr][2U] + << 0xbU) | (vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__cache_miss_resrv__DOT__metadata_table + [vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr][1U] + >> 0x15U))),32); + vcdp->fullQuad(c+17649,((VL_ULL(0x3ffffffffff) + & (((QData)((IData)( + vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__cache_miss_resrv__DOT__metadata_table + [vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr][2U])) + << 0x37U) | (((QData)((IData)( + vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__cache_miss_resrv__DOT__metadata_table + [vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr][1U])) + << 0x17U) + | ((QData)((IData)( + vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__cache_miss_resrv__DOT__metadata_table + [vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr][0U])) + >> 9U))))),42); + vcdp->fullBus(c+17665,((0xfU & ((vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__cache_miss_resrv__DOT__metadata_table + [vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr][1U] + << 0x1cU) + | (vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__cache_miss_resrv__DOT__metadata_table + [vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr][0U] + >> 4U)))),4); + vcdp->fullBit(c+17673,((1U & (vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__cache_miss_resrv__DOT__metadata_table + [vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr][0U] + >> 1U)))); + vcdp->fullBit(c+17681,((1U & vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__cache_miss_resrv__DOT__metadata_table + [vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr][0U]))); + vcdp->fullBus(c+17689,((3U & vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__st_1e_2__DOT__value[0U])),2); + vcdp->fullQuad(c+17697,((VL_ULL(0x3ffffffffff) + & (((QData)((IData)( + vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__st_1e_2__DOT__value[2U])) + << 0x39U) | (((QData)((IData)( + vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__st_1e_2__DOT__value[1U])) + << 0x19U) + | ((QData)((IData)( + vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__st_1e_2__DOT__value[0U])) + >> 7U))))),42); + vcdp->fullBit(c+17713,((1U & (vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__st_1e_2__DOT__value[0U] + >> 6U)))); + vcdp->fullBus(c+17721,((0xfU & ((vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__st_1e_2__DOT__value[1U] + << 0x1eU) + | (vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__st_1e_2__DOT__value[0U] + >> 2U)))),4); + vcdp->fullBit(c+17729,((1U & (vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__st_1e_2__DOT__value[9U] + >> 0x14U)))); + vcdp->fullBit(c+17737,((1U & (vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__st_1e_2__DOT__value[9U] + >> 0x13U)))); + vcdp->fullBus(c+17745,((3U & ((vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__st_1e_2__DOT__value[9U] + << 9U) | (vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__st_1e_2__DOT__value[8U] + >> 0x17U)))),2); + vcdp->fullBus(c+17753,(((vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__st_1e_2__DOT__value[8U] + << 9U) | (vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__st_1e_2__DOT__value[7U] + >> 0x17U))),32); + vcdp->fullBus(c+17761,(((vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__st_1e_2__DOT__value[7U] + << 9U) | (vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__st_1e_2__DOT__value[6U] + >> 0x17U))),32); + __Vtemp628[0U] = ((vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__st_1e_2__DOT__value[3U] + << 9U) | (vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__st_1e_2__DOT__value[2U] + >> 0x17U)); + __Vtemp628[1U] = ((vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__st_1e_2__DOT__value[4U] + << 9U) | (vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__st_1e_2__DOT__value[3U] + >> 0x17U)); + __Vtemp628[2U] = ((vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__st_1e_2__DOT__value[5U] + << 9U) | (vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__st_1e_2__DOT__value[4U] + >> 0x17U)); + __Vtemp628[3U] = ((vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__st_1e_2__DOT__value[6U] + << 9U) | (vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__st_1e_2__DOT__value[5U] + >> 0x17U)); + vcdp->fullArray(c+17769,(__Vtemp628),128); + vcdp->fullBit(c+17801,((1U & (vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__st_1e_2__DOT__value[2U] + >> 2U)))); + vcdp->fullBit(c+17809,((1U & (vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__st_1e_2__DOT__value[2U] + >> 1U)))); + vcdp->fullBus(c+17817,((0xffffU & ((vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__st_1e_2__DOT__value[2U] + << 0xfU) + | (vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__st_1e_2__DOT__value[1U] + >> 0x11U)))),16); + vcdp->fullQuad(c+17825,((VL_ULL(0x1ffffffffffff) + & (((QData)((IData)( + vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__st_1e_2__DOT__value[1U])) + << 0x20U) | (QData)((IData)( + vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__st_1e_2__DOT__value[0U]))))),49); + vcdp->fullBus(c+17841,((0xfffffU & ((vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__st_1e_2__DOT__value[3U] + << 0x1dU) + | (vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__st_1e_2__DOT__value[2U] + >> 3U)))),20); + vcdp->fullBit(c+17849,((1U & (vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__st_1e_2__DOT__value[9U] + >> 0x15U)))); + vcdp->fullBit(c+17857,((1U & (vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__st_1e_2__DOT__value[9U] + >> 0x17U)))); + vcdp->fullBit(c+17865,((1U & (vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__st_1e_2__DOT__value[9U] + >> 0x16U)))); + vcdp->fullBit(c+17873,((1U & (vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__st_1e_2__DOT__value[9U] + >> 0x18U)))); + vcdp->fullBit(c+17881,((1U & (vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__st_1e_2__DOT__value[9U] + >> 0x1aU)))); + vcdp->fullBit(c+17889,((1U & (vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__st_1e_2__DOT__value[9U] + >> 0x1bU)))); + vcdp->fullBit(c+17897,((1U & (vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__st_1e_2__DOT__value[9U] + >> 0x19U)))); + vcdp->fullBit(c+17905,(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__cwb_queue__DOT__genblk3__DOT__genblk2__DOT__empty_r)); + vcdp->fullBit(c+17913,(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__cwb_queue__DOT__genblk3__DOT__genblk2__DOT__full_r)); + vcdp->fullBit(c+17921,(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__genblk2__DOT__empty_r)); + vcdp->fullBit(c+17929,(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__genblk2__DOT__full_r)); + vcdp->fullBus(c+17937,(((0x3ffffc0U & (vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__st_1e_2__DOT__value[2U] + << 3U)) + | (0x3fU & ((vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__st_1e_2__DOT__value[9U] + << 7U) + | (vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__st_1e_2__DOT__value[8U] + >> 0x19U))))),26); + vcdp->fullBus(c+17945,((0xfffffffU & ((vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__st_1e_2__DOT__value[1U] + << 0x19U) + | (vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__st_1e_2__DOT__value[0U] + >> 7U)))),28); + vcdp->fullBit(c+17953,(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__dwbq_dual_valid_sel)); + vcdp->fullBus(c+17961,(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__snp_req_queue__DOT__size_r),5); + vcdp->fullQuad(c+17969,(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__snp_req_queue__DOT__genblk3__DOT__data[0]),55); + vcdp->fullQuad(c+17971,(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__snp_req_queue__DOT__genblk3__DOT__data[1]),55); + vcdp->fullQuad(c+17973,(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__snp_req_queue__DOT__genblk3__DOT__data[2]),55); + vcdp->fullQuad(c+17975,(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__snp_req_queue__DOT__genblk3__DOT__data[3]),55); + vcdp->fullQuad(c+17977,(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__snp_req_queue__DOT__genblk3__DOT__data[4]),55); + vcdp->fullQuad(c+17979,(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__snp_req_queue__DOT__genblk3__DOT__data[5]),55); + vcdp->fullQuad(c+17981,(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__snp_req_queue__DOT__genblk3__DOT__data[6]),55); + vcdp->fullQuad(c+17983,(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__snp_req_queue__DOT__genblk3__DOT__data[7]),55); + vcdp->fullQuad(c+17985,(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__snp_req_queue__DOT__genblk3__DOT__data[8]),55); + vcdp->fullQuad(c+17987,(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__snp_req_queue__DOT__genblk3__DOT__data[9]),55); + vcdp->fullQuad(c+17989,(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__snp_req_queue__DOT__genblk3__DOT__data[10]),55); + vcdp->fullQuad(c+17991,(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__snp_req_queue__DOT__genblk3__DOT__data[11]),55); + vcdp->fullQuad(c+17993,(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__snp_req_queue__DOT__genblk3__DOT__data[12]),55); + vcdp->fullQuad(c+17995,(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__snp_req_queue__DOT__genblk3__DOT__data[13]),55); + vcdp->fullQuad(c+17997,(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__snp_req_queue__DOT__genblk3__DOT__data[14]),55); + vcdp->fullQuad(c+17999,(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__snp_req_queue__DOT__genblk3__DOT__data[15]),55); + vcdp->fullQuad(c+18225,(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__snp_req_queue__DOT__genblk3__DOT__genblk2__DOT__head_r),55); + vcdp->fullQuad(c+18241,(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__snp_req_queue__DOT__genblk3__DOT__genblk2__DOT__curr_r),55); + vcdp->fullBus(c+18257,(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__snp_req_queue__DOT__genblk3__DOT__genblk2__DOT__wr_ptr_r),4); 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+ vcdp->fullArray(c+18317,(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__dfp_queue__DOT__genblk3__DOT__data[4]),154); + vcdp->fullArray(c+18322,(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__dfp_queue__DOT__genblk3__DOT__data[5]),154); + vcdp->fullArray(c+18327,(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__dfp_queue__DOT__genblk3__DOT__data[6]),154); + vcdp->fullArray(c+18332,(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__dfp_queue__DOT__genblk3__DOT__data[7]),154); + vcdp->fullArray(c+18337,(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__dfp_queue__DOT__genblk3__DOT__data[8]),154); + vcdp->fullArray(c+18342,(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__dfp_queue__DOT__genblk3__DOT__data[9]),154); + vcdp->fullArray(c+18347,(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__dfp_queue__DOT__genblk3__DOT__data[10]),154); + vcdp->fullArray(c+18352,(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__dfp_queue__DOT__genblk3__DOT__data[11]),154); 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+ vcdp->fullBus(c+19033,(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__dfp_queue__DOT__genblk3__DOT__genblk2__DOT__rd_ptr_next_r),4); + vcdp->fullBit(c+19041,(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__dfp_queue__DOT__genblk3__DOT__genblk2__DOT__bypass_r)); + vcdp->fullBus(c+19049,(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__core_req_arb__DOT__use_per_valids),4); + vcdp->fullBus(c+19057,(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__core_req_arb__DOT__use_per_rw),4); + vcdp->fullBus(c+19065,(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__core_req_arb__DOT__use_per_byteen),16); + vcdp->fullArray(c+19073,(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__core_req_arb__DOT__use_per_addr),120); + vcdp->fullArray(c+19105,(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__core_req_arb__DOT__use_per_writedata),128); + vcdp->fullBit(c+19137,(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__empty_r)); + vcdp->fullBit(c+19145,((1U & (~ (IData)((0U + != (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__core_req_arb__DOT__use_per_valids))))))); + vcdp->fullBus(c+19153,(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__size_r),3); + vcdp->fullArray(c+19161,(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__data[0]),314); + vcdp->fullArray(c+19171,(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__data[1]),314); + vcdp->fullArray(c+19181,(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__data[2]),314); + vcdp->fullArray(c+19191,(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__data[3]),314); + vcdp->fullArray(c+19481,(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__head_r),314); + vcdp->fullArray(c+19561,(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__curr_r),314); + vcdp->fullBus(c+19641,(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__wr_ptr_r),2); + vcdp->fullBus(c+19649,(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__rd_ptr_r),2); + vcdp->fullBus(c+19657,(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__rd_ptr_next_r),2); + vcdp->fullBit(c+19665,(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__bypass_r)); + vcdp->fullArray(c+19673,(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__s0_1_c0__DOT__value),243); + vcdp->fullQuad(c+19737,(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__dirty),64); + vcdp->fullQuad(c+19753,(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__valid),64); + vcdp->fullBus(c+19769,(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__i),32); + vcdp->fullBus(c+19777,(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__j),32); + vcdp->fullArray(c+19785,(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__tag_data_access__DOT__s0_1_c0__DOT__value),166); + vcdp->fullArray(c+19833,(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__st_1e_2__DOT__value),316); + vcdp->fullArray(c+19913,(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__cache_miss_resrv__DOT__metadata_table[0]),85); + vcdp->fullArray(c+19916,(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__cache_miss_resrv__DOT__metadata_table[1]),85); + vcdp->fullArray(c+19919,(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__cache_miss_resrv__DOT__metadata_table[2]),85); + vcdp->fullArray(c+19922,(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__cache_miss_resrv__DOT__metadata_table[3]),85); + vcdp->fullArray(c+19925,(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__cache_miss_resrv__DOT__metadata_table[4]),85); + vcdp->fullArray(c+19928,(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__cache_miss_resrv__DOT__metadata_table[5]),85); + vcdp->fullArray(c+19931,(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__cache_miss_resrv__DOT__metadata_table[6]),85); + vcdp->fullArray(c+19934,(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__cache_miss_resrv__DOT__metadata_table[7]),85); + vcdp->fullArray(c+19937,(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__cache_miss_resrv__DOT__metadata_table[8]),85); + vcdp->fullArray(c+19940,(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__cache_miss_resrv__DOT__metadata_table[9]),85); + vcdp->fullArray(c+19943,(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__cache_miss_resrv__DOT__metadata_table[10]),85); + vcdp->fullArray(c+19946,(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__cache_miss_resrv__DOT__metadata_table[11]),85); + vcdp->fullArray(c+19949,(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__cache_miss_resrv__DOT__metadata_table[12]),85); + vcdp->fullArray(c+19952,(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__cache_miss_resrv__DOT__metadata_table[13]),85); + vcdp->fullArray(c+19955,(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__cache_miss_resrv__DOT__metadata_table[14]),85); + vcdp->fullArray(c+19958,(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__cache_miss_resrv__DOT__metadata_table[15]),85); + vcdp->fullArray(c+20297,(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__cache_miss_resrv__DOT__addr_table),416); + vcdp->fullBus(c+20401,(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__cache_miss_resrv__DOT__valid_table),16); + vcdp->fullBus(c+20409,(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__cache_miss_resrv__DOT__ready_table),16); + vcdp->fullBus(c+20417,(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr),4); + vcdp->fullBus(c+20425,(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__cache_miss_resrv__DOT__head_ptr),4); + vcdp->fullBus(c+20433,(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__cache_miss_resrv__DOT__tail_ptr),4); + vcdp->fullBus(c+20441,(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__cache_miss_resrv__DOT__size),5); + vcdp->fullBit(c+20449,((0x10U != (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__cache_miss_resrv__DOT__size)))); + vcdp->fullBus(c+20457,(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__cwb_queue__DOT__size_r),3); + vcdp->fullArray(c+20465,(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__cwb_queue__DOT__genblk3__DOT__data[0]),76); + vcdp->fullArray(c+20468,(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__cwb_queue__DOT__genblk3__DOT__data[1]),76); + vcdp->fullArray(c+20471,(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__cwb_queue__DOT__genblk3__DOT__data[2]),76); + vcdp->fullArray(c+20474,(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__cwb_queue__DOT__genblk3__DOT__data[3]),76); + vcdp->fullArray(c+20561,(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__cwb_queue__DOT__genblk3__DOT__genblk2__DOT__head_r),76); + vcdp->fullArray(c+20585,(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__cwb_queue__DOT__genblk3__DOT__genblk2__DOT__curr_r),76); + vcdp->fullBus(c+20609,(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__cwb_queue__DOT__genblk3__DOT__genblk2__DOT__wr_ptr_r),2); + vcdp->fullBus(c+20617,(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__cwb_queue__DOT__genblk3__DOT__genblk2__DOT__rd_ptr_r),2); + vcdp->fullBus(c+20625,(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__cwb_queue__DOT__genblk3__DOT__genblk2__DOT__rd_ptr_next_r),2); + vcdp->fullBit(c+20633,(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__cwb_queue__DOT__genblk3__DOT__genblk2__DOT__bypass_r)); + vcdp->fullBus(c+20641,(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__dwb_queue__DOT__size_r),3); + vcdp->fullArray(c+20649,(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__data[0]),200); + vcdp->fullArray(c+20656,(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__data[1]),200); + vcdp->fullArray(c+20663,(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__data[2]),200); + vcdp->fullArray(c+20670,(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__data[3]),200); + vcdp->fullArray(c+20873,(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__genblk2__DOT__head_r),200); + vcdp->fullArray(c+20929,(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__genblk2__DOT__curr_r),200); + vcdp->fullBus(c+20985,(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__genblk2__DOT__wr_ptr_r),2); + vcdp->fullBus(c+20993,(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__genblk2__DOT__rd_ptr_r),2); + vcdp->fullBus(c+21001,(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__genblk2__DOT__rd_ptr_next_r),2); + vcdp->fullBit(c+21009,(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__genblk2__DOT__bypass_r)); + vcdp->fullBit(c+21017,(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__snp_req_queue__DOT__genblk3__DOT__genblk2__DOT__empty_r)); + vcdp->fullBit(c+21025,(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__snp_req_queue__DOT__genblk3__DOT__genblk2__DOT__full_r)); + vcdp->fullBit(c+21033,(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__dfp_queue__DOT__genblk3__DOT__genblk2__DOT__empty_r)); + vcdp->fullBit(c+21041,(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__dfp_queue__DOT__genblk3__DOT__genblk2__DOT__full_r)); + vcdp->fullBit(c+21049,(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__full_r)); + vcdp->fullQuad(c+21057,(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__core_req_arb__DOT__use_per_tag),42); + vcdp->fullBit(c+21073,((0x10U == (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cache_miss_resrv__DOT__size)))); + vcdp->fullBit(c+21081,((0xbU < (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cache_miss_resrv__DOT__size)))); + vcdp->fullBus(c+21089,((3U & ((vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cache_miss_resrv__DOT__metadata_table + [vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr][2U] + << 0xdU) | ( + vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cache_miss_resrv__DOT__metadata_table + [vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr][1U] + >> 0x13U)))),2); + vcdp->fullBus(c+21097,(((0x19fU >= (0x1ffU + & ((IData)(0x1aU) + * (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr)))) + ? (0x3ffffffU & (( + (0U + == + (0x1fU + & ((IData)(0x1aU) + * (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr)))) + ? 0U + : + (vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cache_miss_resrv__DOT__addr_table[ + ((IData)(1U) + + + (0xfU + & (((IData)(0x1aU) + * (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr)) + >> 5U)))] + << + ((IData)(0x20U) + - + (0x1fU + & ((IData)(0x1aU) + * (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr)))))) + | (vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cache_miss_resrv__DOT__addr_table[ + (0xfU + & (((IData)(0x1aU) + * (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr)) + >> 5U))] + >> + (0x1fU + & ((IData)(0x1aU) + * (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr)))))) + : 0U)),26); + vcdp->fullBus(c+21105,((3U & ((vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cache_miss_resrv__DOT__metadata_table + [vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr][1U] + << 0x1eU) | + (vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cache_miss_resrv__DOT__metadata_table + [vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr][0U] + >> 2U)))),2); + vcdp->fullBus(c+21113,(((vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cache_miss_resrv__DOT__metadata_table + [vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr][2U] + << 0xbU) | (vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cache_miss_resrv__DOT__metadata_table + [vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr][1U] + >> 0x15U))),32); + vcdp->fullQuad(c+21121,((VL_ULL(0x3ffffffffff) + & (((QData)((IData)( + vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cache_miss_resrv__DOT__metadata_table + [vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr][2U])) + << 0x37U) | (((QData)((IData)( + vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cache_miss_resrv__DOT__metadata_table + [vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr][1U])) + << 0x17U) + | ((QData)((IData)( + vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cache_miss_resrv__DOT__metadata_table + [vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr][0U])) + >> 9U))))),42); + vcdp->fullBus(c+21137,((0xfU & ((vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cache_miss_resrv__DOT__metadata_table + [vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr][1U] + << 0x1cU) + | (vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cache_miss_resrv__DOT__metadata_table + [vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr][0U] + >> 4U)))),4); + vcdp->fullBit(c+21145,((1U & (vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cache_miss_resrv__DOT__metadata_table + [vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr][0U] + >> 1U)))); + vcdp->fullBit(c+21153,((1U & vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cache_miss_resrv__DOT__metadata_table + [vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr][0U]))); + vcdp->fullBus(c+21161,((3U & vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__st_1e_2__DOT__value[0U])),2); + vcdp->fullQuad(c+21169,((VL_ULL(0x3ffffffffff) + & (((QData)((IData)( + vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__st_1e_2__DOT__value[2U])) + << 0x39U) | (((QData)((IData)( + vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__st_1e_2__DOT__value[1U])) + << 0x19U) + | ((QData)((IData)( + vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__st_1e_2__DOT__value[0U])) + >> 7U))))),42); + vcdp->fullBit(c+21185,((1U & (vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__st_1e_2__DOT__value[0U] + >> 6U)))); + vcdp->fullBus(c+21193,((0xfU & ((vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__st_1e_2__DOT__value[1U] + << 0x1eU) + | (vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__st_1e_2__DOT__value[0U] + >> 2U)))),4); + vcdp->fullBit(c+21201,((1U & (vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__st_1e_2__DOT__value[9U] + >> 0x14U)))); + vcdp->fullBit(c+21209,((1U & (vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__st_1e_2__DOT__value[9U] + >> 0x13U)))); + vcdp->fullBus(c+21217,((3U & ((vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__st_1e_2__DOT__value[9U] + << 9U) | (vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__st_1e_2__DOT__value[8U] + >> 0x17U)))),2); + vcdp->fullBus(c+21225,(((vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__st_1e_2__DOT__value[8U] + << 9U) | (vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__st_1e_2__DOT__value[7U] + >> 0x17U))),32); + vcdp->fullBus(c+21233,(((vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__st_1e_2__DOT__value[7U] + << 9U) | (vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__st_1e_2__DOT__value[6U] + >> 0x17U))),32); + __Vtemp636[0U] = ((vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__st_1e_2__DOT__value[3U] + << 9U) | (vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__st_1e_2__DOT__value[2U] + >> 0x17U)); + __Vtemp636[1U] = ((vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__st_1e_2__DOT__value[4U] + << 9U) | (vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__st_1e_2__DOT__value[3U] + >> 0x17U)); + __Vtemp636[2U] = ((vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__st_1e_2__DOT__value[5U] + << 9U) | (vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__st_1e_2__DOT__value[4U] + >> 0x17U)); + __Vtemp636[3U] = ((vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__st_1e_2__DOT__value[6U] + << 9U) | (vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__st_1e_2__DOT__value[5U] + >> 0x17U)); + vcdp->fullArray(c+21241,(__Vtemp636),128); + vcdp->fullBit(c+21273,((1U & (vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__st_1e_2__DOT__value[2U] + >> 2U)))); + vcdp->fullBit(c+21281,((1U & (vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__st_1e_2__DOT__value[2U] + >> 1U)))); + vcdp->fullBus(c+21289,((0xffffU & ((vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__st_1e_2__DOT__value[2U] + << 0xfU) + | (vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__st_1e_2__DOT__value[1U] + >> 0x11U)))),16); + vcdp->fullQuad(c+21297,((VL_ULL(0x1ffffffffffff) + & (((QData)((IData)( + vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__st_1e_2__DOT__value[1U])) + << 0x20U) | (QData)((IData)( + vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__st_1e_2__DOT__value[0U]))))),49); + vcdp->fullBus(c+21313,((0xfffffU & ((vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__st_1e_2__DOT__value[3U] + << 0x1dU) + | (vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__st_1e_2__DOT__value[2U] + >> 3U)))),20); + vcdp->fullBit(c+21321,((1U & (vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__st_1e_2__DOT__value[9U] + >> 0x15U)))); + vcdp->fullBit(c+21329,((1U & (vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__st_1e_2__DOT__value[9U] + >> 0x17U)))); + vcdp->fullBit(c+21337,((1U & (vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__st_1e_2__DOT__value[9U] + >> 0x16U)))); + vcdp->fullBit(c+21345,((1U & (vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__st_1e_2__DOT__value[9U] + >> 0x18U)))); + vcdp->fullBit(c+21353,((1U & (vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__st_1e_2__DOT__value[9U] + >> 0x1aU)))); + vcdp->fullBit(c+21361,((1U & (vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__st_1e_2__DOT__value[9U] + >> 0x1bU)))); + vcdp->fullBit(c+21369,((1U & (vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__st_1e_2__DOT__value[9U] + >> 0x19U)))); + vcdp->fullBit(c+21377,(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cwb_queue__DOT__genblk3__DOT__genblk2__DOT__empty_r)); + vcdp->fullBit(c+21385,(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cwb_queue__DOT__genblk3__DOT__genblk2__DOT__full_r)); + vcdp->fullBit(c+21393,(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__genblk2__DOT__empty_r)); + vcdp->fullBit(c+21401,(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__genblk2__DOT__full_r)); + vcdp->fullBus(c+21409,(((0x3ffffc0U & (vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__st_1e_2__DOT__value[2U] + << 3U)) + | (0x3fU & ((vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__st_1e_2__DOT__value[9U] + << 7U) + | (vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__st_1e_2__DOT__value[8U] + >> 0x19U))))),26); + vcdp->fullBus(c+21417,((0xfffffffU & ((vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__st_1e_2__DOT__value[1U] + << 0x19U) + | (vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__st_1e_2__DOT__value[0U] + >> 7U)))),28); + vcdp->fullBit(c+21425,(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__dwbq_dual_valid_sel)); + vcdp->fullBus(c+21433,(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__snp_req_queue__DOT__size_r),5); + vcdp->fullQuad(c+21441,(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__snp_req_queue__DOT__genblk3__DOT__data[0]),55); + vcdp->fullQuad(c+21443,(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__snp_req_queue__DOT__genblk3__DOT__data[1]),55); + vcdp->fullQuad(c+21445,(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__snp_req_queue__DOT__genblk3__DOT__data[2]),55); + vcdp->fullQuad(c+21447,(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__snp_req_queue__DOT__genblk3__DOT__data[3]),55); + vcdp->fullQuad(c+21449,(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__snp_req_queue__DOT__genblk3__DOT__data[4]),55); + vcdp->fullQuad(c+21451,(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__snp_req_queue__DOT__genblk3__DOT__data[5]),55); + vcdp->fullQuad(c+21453,(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__snp_req_queue__DOT__genblk3__DOT__data[6]),55); + vcdp->fullQuad(c+21455,(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__snp_req_queue__DOT__genblk3__DOT__data[7]),55); + vcdp->fullQuad(c+21457,(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__snp_req_queue__DOT__genblk3__DOT__data[8]),55); + vcdp->fullQuad(c+21459,(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__snp_req_queue__DOT__genblk3__DOT__data[9]),55); + vcdp->fullQuad(c+21461,(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__snp_req_queue__DOT__genblk3__DOT__data[10]),55); + vcdp->fullQuad(c+21463,(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__snp_req_queue__DOT__genblk3__DOT__data[11]),55); + vcdp->fullQuad(c+21465,(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__snp_req_queue__DOT__genblk3__DOT__data[12]),55); + vcdp->fullQuad(c+21467,(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__snp_req_queue__DOT__genblk3__DOT__data[13]),55); + vcdp->fullQuad(c+21469,(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__snp_req_queue__DOT__genblk3__DOT__data[14]),55); + vcdp->fullQuad(c+21471,(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__snp_req_queue__DOT__genblk3__DOT__data[15]),55); + vcdp->fullQuad(c+21697,(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__snp_req_queue__DOT__genblk3__DOT__genblk2__DOT__head_r),55); + vcdp->fullQuad(c+21713,(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__snp_req_queue__DOT__genblk3__DOT__genblk2__DOT__curr_r),55); + vcdp->fullBus(c+21729,(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__snp_req_queue__DOT__genblk3__DOT__genblk2__DOT__wr_ptr_r),4); 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+ vcdp->fullArray(c+21789,(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__dfp_queue__DOT__genblk3__DOT__data[4]),154); + vcdp->fullArray(c+21794,(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__dfp_queue__DOT__genblk3__DOT__data[5]),154); + vcdp->fullArray(c+21799,(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__dfp_queue__DOT__genblk3__DOT__data[6]),154); + vcdp->fullArray(c+21804,(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__dfp_queue__DOT__genblk3__DOT__data[7]),154); + vcdp->fullArray(c+21809,(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__dfp_queue__DOT__genblk3__DOT__data[8]),154); + vcdp->fullArray(c+21814,(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__dfp_queue__DOT__genblk3__DOT__data[9]),154); + vcdp->fullArray(c+21819,(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__dfp_queue__DOT__genblk3__DOT__data[10]),154); + vcdp->fullArray(c+21824,(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__dfp_queue__DOT__genblk3__DOT__data[11]),154); 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+ vcdp->fullBus(c+22505,(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__dfp_queue__DOT__genblk3__DOT__genblk2__DOT__rd_ptr_next_r),4); + vcdp->fullBit(c+22513,(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__dfp_queue__DOT__genblk3__DOT__genblk2__DOT__bypass_r)); + vcdp->fullBus(c+22521,(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__core_req_arb__DOT__use_per_valids),4); + vcdp->fullBus(c+22529,(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__core_req_arb__DOT__use_per_rw),4); + vcdp->fullBus(c+22537,(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__core_req_arb__DOT__use_per_byteen),16); + vcdp->fullArray(c+22545,(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__core_req_arb__DOT__use_per_addr),120); + vcdp->fullArray(c+22577,(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__core_req_arb__DOT__use_per_writedata),128); + vcdp->fullBit(c+22609,(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__empty_r)); + vcdp->fullBit(c+22617,((1U & (~ (IData)((0U + != (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__core_req_arb__DOT__use_per_valids))))))); + vcdp->fullBus(c+22625,(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__size_r),3); + vcdp->fullArray(c+22633,(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__data[0]),314); + vcdp->fullArray(c+22643,(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__data[1]),314); + vcdp->fullArray(c+22653,(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__data[2]),314); + vcdp->fullArray(c+22663,(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__data[3]),314); + vcdp->fullArray(c+22953,(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__head_r),314); + vcdp->fullArray(c+23033,(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__curr_r),314); + vcdp->fullBus(c+23113,(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__wr_ptr_r),2); + vcdp->fullBus(c+23121,(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__rd_ptr_r),2); + vcdp->fullBus(c+23129,(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__rd_ptr_next_r),2); + vcdp->fullBit(c+23137,(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__bypass_r)); + vcdp->fullArray(c+23145,(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__s0_1_c0__DOT__value),243); + vcdp->fullQuad(c+23209,(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__dirty),64); + vcdp->fullQuad(c+23225,(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__valid),64); + vcdp->fullBus(c+23241,(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__i),32); + vcdp->fullBus(c+23249,(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__j),32); + vcdp->fullArray(c+23257,(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__tag_data_access__DOT__s0_1_c0__DOT__value),166); + vcdp->fullArray(c+23305,(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__st_1e_2__DOT__value),316); + vcdp->fullArray(c+23385,(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cache_miss_resrv__DOT__metadata_table[0]),85); + vcdp->fullArray(c+23388,(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cache_miss_resrv__DOT__metadata_table[1]),85); + vcdp->fullArray(c+23391,(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cache_miss_resrv__DOT__metadata_table[2]),85); + vcdp->fullArray(c+23394,(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cache_miss_resrv__DOT__metadata_table[3]),85); + vcdp->fullArray(c+23397,(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cache_miss_resrv__DOT__metadata_table[4]),85); + vcdp->fullArray(c+23400,(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cache_miss_resrv__DOT__metadata_table[5]),85); + vcdp->fullArray(c+23403,(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cache_miss_resrv__DOT__metadata_table[6]),85); + vcdp->fullArray(c+23406,(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cache_miss_resrv__DOT__metadata_table[7]),85); + vcdp->fullArray(c+23409,(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cache_miss_resrv__DOT__metadata_table[8]),85); + vcdp->fullArray(c+23412,(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cache_miss_resrv__DOT__metadata_table[9]),85); + vcdp->fullArray(c+23415,(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cache_miss_resrv__DOT__metadata_table[10]),85); + vcdp->fullArray(c+23418,(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cache_miss_resrv__DOT__metadata_table[11]),85); + vcdp->fullArray(c+23421,(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cache_miss_resrv__DOT__metadata_table[12]),85); + vcdp->fullArray(c+23424,(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cache_miss_resrv__DOT__metadata_table[13]),85); + vcdp->fullArray(c+23427,(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cache_miss_resrv__DOT__metadata_table[14]),85); + vcdp->fullArray(c+23430,(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cache_miss_resrv__DOT__metadata_table[15]),85); + vcdp->fullArray(c+23769,(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cache_miss_resrv__DOT__addr_table),416); + vcdp->fullBus(c+23873,(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cache_miss_resrv__DOT__valid_table),16); + vcdp->fullBus(c+23881,(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cache_miss_resrv__DOT__ready_table),16); + vcdp->fullBus(c+23889,(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr),4); + vcdp->fullBus(c+23897,(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cache_miss_resrv__DOT__head_ptr),4); + vcdp->fullBus(c+23905,(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cache_miss_resrv__DOT__tail_ptr),4); + vcdp->fullBus(c+23913,(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cache_miss_resrv__DOT__size),5); + vcdp->fullBit(c+23921,((0x10U != (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cache_miss_resrv__DOT__size)))); + vcdp->fullBus(c+23929,(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cwb_queue__DOT__size_r),3); + vcdp->fullArray(c+23937,(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cwb_queue__DOT__genblk3__DOT__data[0]),76); + vcdp->fullArray(c+23940,(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cwb_queue__DOT__genblk3__DOT__data[1]),76); + vcdp->fullArray(c+23943,(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cwb_queue__DOT__genblk3__DOT__data[2]),76); + vcdp->fullArray(c+23946,(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cwb_queue__DOT__genblk3__DOT__data[3]),76); + vcdp->fullArray(c+24033,(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cwb_queue__DOT__genblk3__DOT__genblk2__DOT__head_r),76); + vcdp->fullArray(c+24057,(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cwb_queue__DOT__genblk3__DOT__genblk2__DOT__curr_r),76); + vcdp->fullBus(c+24081,(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cwb_queue__DOT__genblk3__DOT__genblk2__DOT__wr_ptr_r),2); + vcdp->fullBus(c+24089,(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cwb_queue__DOT__genblk3__DOT__genblk2__DOT__rd_ptr_r),2); + vcdp->fullBus(c+24097,(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cwb_queue__DOT__genblk3__DOT__genblk2__DOT__rd_ptr_next_r),2); + vcdp->fullBit(c+24105,(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cwb_queue__DOT__genblk3__DOT__genblk2__DOT__bypass_r)); + vcdp->fullBus(c+24113,(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__dwb_queue__DOT__size_r),3); + vcdp->fullArray(c+24121,(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__data[0]),200); + vcdp->fullArray(c+24128,(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__data[1]),200); + vcdp->fullArray(c+24135,(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__data[2]),200); + vcdp->fullArray(c+24142,(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__data[3]),200); + vcdp->fullArray(c+24345,(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__genblk2__DOT__head_r),200); + vcdp->fullArray(c+24401,(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__genblk2__DOT__curr_r),200); + vcdp->fullBus(c+24457,(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__genblk2__DOT__wr_ptr_r),2); + vcdp->fullBus(c+24465,(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__genblk2__DOT__rd_ptr_r),2); + vcdp->fullBus(c+24473,(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__genblk2__DOT__rd_ptr_next_r),2); + vcdp->fullBit(c+24481,(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__genblk2__DOT__bypass_r)); + vcdp->fullBit(c+24489,(vlTOPp->clk)); + vcdp->fullBit(c+24497,(vlTOPp->reset)); + vcdp->fullBus(c+24505,(vlTOPp->core_req_valid),4); + vcdp->fullBus(c+24513,(vlTOPp->core_req_rw),4); + vcdp->fullBus(c+24521,(vlTOPp->core_req_byteen),16); + vcdp->fullArray(c+24529,(vlTOPp->core_req_addr),120); + vcdp->fullArray(c+24561,(vlTOPp->core_req_data),128); + vcdp->fullQuad(c+24593,(vlTOPp->core_req_tag),42); + vcdp->fullBit(c+24609,(vlTOPp->core_req_ready)); + vcdp->fullBus(c+24617,(vlTOPp->core_rsp_valid),4); + vcdp->fullArray(c+24625,(vlTOPp->core_rsp_data),128); + vcdp->fullQuad(c+24657,(vlTOPp->core_rsp_tag),42); + vcdp->fullBit(c+24673,(vlTOPp->core_rsp_ready)); + vcdp->fullBit(c+24681,(vlTOPp->dram_req_valid)); + vcdp->fullBit(c+24689,(vlTOPp->dram_req_rw)); + vcdp->fullBus(c+24697,(vlTOPp->dram_req_byteen),16); + vcdp->fullBus(c+24705,(vlTOPp->dram_req_addr),28); + vcdp->fullArray(c+24713,(vlTOPp->dram_req_data),128); + vcdp->fullBus(c+24745,(vlTOPp->dram_req_tag),28); + vcdp->fullBit(c+24753,(vlTOPp->dram_req_ready)); + vcdp->fullBit(c+24761,(vlTOPp->dram_rsp_valid)); + vcdp->fullArray(c+24769,(vlTOPp->dram_rsp_data),128); + vcdp->fullBus(c+24801,(vlTOPp->dram_rsp_tag),28); + vcdp->fullBit(c+24809,(vlTOPp->dram_rsp_ready)); + vcdp->fullBit(c+24817,(vlTOPp->snp_req_valid)); + vcdp->fullBus(c+24825,(vlTOPp->snp_req_addr),28); + vcdp->fullBit(c+24833,(vlTOPp->snp_req_invalidate)); + vcdp->fullBus(c+24841,(vlTOPp->snp_req_tag),28); + vcdp->fullBit(c+24849,(vlTOPp->snp_req_ready)); + vcdp->fullBit(c+24857,(vlTOPp->snp_rsp_valid)); + vcdp->fullBus(c+24865,(vlTOPp->snp_rsp_tag),28); + vcdp->fullBit(c+24873,(vlTOPp->snp_rsp_ready)); + vcdp->fullBus(c+24881,(vlTOPp->snp_fwdout_valid),2); + vcdp->fullQuad(c+24889,(vlTOPp->snp_fwdout_addr),56); + vcdp->fullBus(c+24905,(vlTOPp->snp_fwdout_invalidate),2); + vcdp->fullBus(c+24913,(vlTOPp->snp_fwdout_tag),2); + vcdp->fullBus(c+24921,(vlTOPp->snp_fwdout_ready),2); + vcdp->fullBus(c+24929,(vlTOPp->snp_fwdin_valid),2); + vcdp->fullBus(c+24937,(vlTOPp->snp_fwdin_tag),2); + vcdp->fullBus(c+24945,(vlTOPp->snp_fwdin_ready),2); + vcdp->fullBit(c+24953,((1U & ((IData)(vlTOPp->VX_cache__DOT__per_bank_snp_req_ready) + >> (3U & vlTOPp->snp_req_addr))))); + vcdp->fullBit(c+24961,(((IData)(vlTOPp->dram_rsp_valid) + & (0U == (3U & vlTOPp->dram_rsp_tag))))); + vcdp->fullBus(c+24969,((0x3ffffffU & (vlTOPp->dram_rsp_tag + >> 2U))),26); + vcdp->fullBit(c+24977,(((IData)(vlTOPp->snp_req_valid) + & (0U == (3U & vlTOPp->snp_req_addr))))); + vcdp->fullBus(c+24985,((0x3ffffffU & (vlTOPp->snp_req_addr + >> 2U))),26); + vcdp->fullBit(c+24993,(((IData)(vlTOPp->dram_rsp_valid) + & (1U == (3U & vlTOPp->dram_rsp_tag))))); + vcdp->fullBit(c+25001,(((IData)(vlTOPp->snp_req_valid) + & (1U == (3U & vlTOPp->snp_req_addr))))); + vcdp->fullBit(c+25009,(((IData)(vlTOPp->dram_rsp_valid) + & (2U == (3U & vlTOPp->dram_rsp_tag))))); + vcdp->fullBit(c+25017,(((IData)(vlTOPp->snp_req_valid) + & (2U == (3U & vlTOPp->snp_req_addr))))); + vcdp->fullBit(c+25025,(((IData)(vlTOPp->dram_rsp_valid) + & (3U == (3U & vlTOPp->dram_rsp_tag))))); + vcdp->fullBit(c+25033,(((IData)(vlTOPp->snp_req_valid) + & (3U == (3U & vlTOPp->snp_req_addr))))); + vcdp->fullBit(c+25041,(((IData)(vlTOPp->dram_req_valid) + & (~ (IData)(vlTOPp->dram_req_rw))))); + vcdp->fullBit(c+25049,((((IData)(vlTOPp->dram_req_valid) + & (~ (IData)(vlTOPp->dram_req_rw))) + & (~ (IData)(vlTOPp->VX_cache__DOT__cache_dram_req_arb__DOT__prfqq__DOT__pfq_queue__DOT__size_r))))); + vcdp->fullBus(c+25057,(0U),32); + vcdp->fullBus(c+25065,(0x1000U),32); + vcdp->fullBus(c+25073,(0x10U),32); + vcdp->fullBus(c+25081,(4U),32); + vcdp->fullBus(c+25089,(1U),32); + vcdp->fullBus(c+25097,(0x2aU),32); + vcdp->fullBus(c+25105,(8U),32); + vcdp->fullBus(c+25113,(0x1cU),32); + vcdp->fullBus(c+25121,(2U),32); + vcdp->fullBus(c+25129,(4U),32); + vcdp->fullBit(c+25137,(0U)); + vcdp->fullBus(c+25145,(0x74U),32); + vcdp->fullBus(c+25153,(0U),32); + vcdp->fullBus(c+25161,(1U),32); + vcdp->fullBus(c+25169,(0x37U),32); + vcdp->fullBus(c+25177,(0x9aU),32); + vcdp->fullBus(c+25185,(0x13aU),32); + vcdp->fullBus(c+25193,(0xf3U),32); + vcdp->fullBus(c+25201,(0xa6U),32); + vcdp->fullBus(c+25209,(0x13cU),32); + vcdp->fullBus(c+25217,(0x4cU),32); + vcdp->fullBus(c+25225,(0xc8U),32); + vcdp->fullBus(c+25233,(2U),32); + vcdp->fullBus(c+25241,(3U),32); + } +} diff --git a/hw/unit_tests/cache/obj_dir/VVX_cache__ver.d b/hw/unit_tests/cache/obj_dir/VVX_cache__ver.d new file mode 100644 index 00000000..ddad5949 --- /dev/null +++ b/hw/unit_tests/cache/obj_dir/VVX_cache__ver.d @@ -0,0 +1 @@ +obj_dir/VVX_cache.cpp obj_dir/VVX_cache.h obj_dir/VVX_cache.mk obj_dir/VVX_cache__Syms.cpp obj_dir/VVX_cache__Syms.h obj_dir/VVX_cache__Trace.cpp obj_dir/VVX_cache__Trace__Slow.cpp obj_dir/VVX_cache__ver.d obj_dir/VVX_cache_classes.mk : /usr/local/bin/verilator_bin ../../rtl//VX_config.vh ../../rtl//VX_define.vh ../../rtl//VX_scope.vh ../../rtl//VX_user_config.vh ../../rtl/cache/VX_bank.v ../../rtl/cache/VX_bank_core_req_arb.v ../../rtl/cache/VX_cache.v ../../rtl/cache/VX_cache_config.vh ../../rtl/cache/VX_cache_core_req_bank_sel.v ../../rtl/cache/VX_cache_core_rsp_merge.v ../../rtl/cache/VX_cache_dram_fill_arb.v ../../rtl/cache/VX_cache_dram_req_arb.v ../../rtl/cache/VX_cache_miss_resrv.v ../../rtl/cache/VX_prefetcher.v ../../rtl/cache/VX_snp_forwarder.v ../../rtl/cache/VX_snp_rsp_arb.v ../../rtl/cache/VX_tag_data_access.v ../../rtl/cache/VX_tag_data_structure.v ../../rtl/libs/VX_fair_arbiter.v ../../rtl/libs/VX_fixed_arbiter.v ../../rtl/libs/VX_generic_queue.v ../../rtl/libs/VX_generic_register.v ../../rtl/libs/VX_indexable_queue.v ../../rtl/libs/VX_priority_encoder.v /usr/local/bin/verilator_bin diff --git a/hw/unit_tests/cache/obj_dir/VVX_cache__verFiles.dat b/hw/unit_tests/cache/obj_dir/VVX_cache__verFiles.dat new file mode 100644 index 00000000..105011a4 --- /dev/null +++ b/hw/unit_tests/cache/obj_dir/VVX_cache__verFiles.dat @@ -0,0 +1,37 @@ +# DESCRIPTION: Verilator output: Timestamp data for --skip-identical. Delete at will. +C "--language 1800-2009 --assert -Wall --trace -Wno-DECLFILENAME --x-initial unique -exe cachesim.cpp testbench.cpp -I../../rtl/ -I../../rtl/cache -I../../rtl/libs -DNDEBUG -cc VX_cache.v -DCACHE_SIZE=4096 -DWORD_SIZE=4 -DBANK_LINE_SIZE=16 -DNUM_BANKS=4 -DCREQ_SIZE=4 -DMRVQ_SIZE=16 -DDFPQ_SIZE=16 -DSNRQ_SIZE=16 -DCWBQ_SIZE=4 -DDWBQ_SIZE=4 -DFQQ_SIZE=4 -CFLAGS -std=c++11 -fms-extensions -I../.. -DNDEBUG -DCACHE_SIZE=4096 -DWORD_SIZE=4 -DBANK_LINE_SIZE=16 -DNUM_BANKS=4 -DCREQ_SIZE=4 -DMRVQ_SIZE=16 -DDFPQ_SIZE=16 -DSNRQ_SIZE=16 -DCWBQ_SIZE=4 -DDWBQ_SIZE=4 -DFQQ_SIZE=4 --exe cachesim.cpp testbench.cpp" +S 7349 4983714 1594698569 774801969 1594698569 774801969 "../../rtl//VX_config.vh" +S 9046 4983721 1594698569 778802144 1594698569 778802144 "../../rtl//VX_define.vh" +S 16028 4983736 1593571269 849188141 1593571269 849188141 "../../rtl//VX_scope.vh" +S 147 4980795 1592347024 921834494 1592347024 921834494 "../../rtl//VX_user_config.vh" +S 34555 4983741 1593571269 849188141 1593571269 849188141 "../../rtl/cache/VX_bank.v" +S 6128 4983742 1593571269 849188141 1593571269 849188141 "../../rtl/cache/VX_bank_core_req_arb.v" +S 22942 4985366 1594500482 317211549 1594500482 317211549 "../../rtl/cache/VX_cache.v" +S 2842 4983744 1593571269 849188141 1593571269 849188141 "../../rtl/cache/VX_cache_config.vh" +S 1745 4983745 1593571269 849188141 1593571269 849188141 "../../rtl/cache/VX_cache_core_req_bank_sel.v" +S 3649 4983746 1594698569 778802144 1594698569 778802144 "../../rtl/cache/VX_cache_core_rsp_merge.v" +S 3602 4983747 1593571269 849188141 1593571269 849188141 "../../rtl/cache/VX_cache_dram_fill_arb.v" +S 4396 4985343 1593571951 15994059 1593571951 7993214 "../../rtl/cache/VX_cache_dram_req_arb.v" +S 7304 4983749 1594698569 778802144 1594698569 778802144 "../../rtl/cache/VX_cache_miss_resrv.v" +S 1996 4983748 1593571988 408039126 1593571988 396037801 "../../rtl/cache/VX_prefetcher.v" +S 5067 4983751 1594698569 778802144 1594698569 778802144 "../../rtl/cache/VX_snp_forwarder.v" +S 1210 4983752 1593571269 849188141 1593571269 849188141 "../../rtl/cache/VX_snp_rsp_arb.v" +S 8840 4983753 1593571269 849188141 1593571269 849188141 "../../rtl/cache/VX_tag_data_access.v" +S 3211 4983754 1593571269 849188141 1593571269 849188141 "../../rtl/cache/VX_tag_data_structure.v" +S 1861 4983777 1594698569 778802144 1594698569 778802144 "../../rtl/libs/VX_fair_arbiter.v" +S 1022 4983778 1594698569 778802144 1594698569 778802144 "../../rtl/libs/VX_fixed_arbiter.v" +S 5977 4983779 1594698569 778802144 1594698569 778802144 "../../rtl/libs/VX_generic_queue.v" +S 586 4983780 1594698569 778802144 1594698569 778802144 "../../rtl/libs/VX_generic_register.v" +S 1560 4983782 1594698569 778802144 1594698569 778802144 "../../rtl/libs/VX_indexable_queue.v" +S 495 4983785 1594698569 778802144 1594698569 778802144 "../../rtl/libs/VX_priority_encoder.v" +S 8183216 2503059 1591812755 756668753 1591812755 756668753 "/usr/local/bin/verilator_bin" +T 2996411 4983824 1594698591 263742640 1594698591 263742640 "obj_dir/VVX_cache.cpp" +T 93498 4983825 1594698591 211740363 1594698591 211740363 "obj_dir/VVX_cache.h" +T 2104 4983826 1594698591 263742640 1594698591 263742640 "obj_dir/VVX_cache.mk" +T 8694 4983827 1594698591 179738962 1594698591 179738962 "obj_dir/VVX_cache__Syms.cpp" +T 4866 4983828 1594698591 179738962 1594698591 179738962 "obj_dir/VVX_cache__Syms.h" +T 429475 4983829 1594698591 207740187 1594698591 207740187 "obj_dir/VVX_cache__Trace.cpp" +T 700909 4983830 1594698591 195739663 1594698591 195739663 "obj_dir/VVX_cache__Trace__Slow.cpp" +T 1118 4980960 1594698591 263742640 1594698591 263742640 "obj_dir/VVX_cache__ver.d" +T 0 0 1594698591 263742640 1594698591 263742640 "obj_dir/VVX_cache__verFiles.dat" +T 1315 4983831 1594698591 263742640 1594698591 263742640 "obj_dir/VVX_cache_classes.mk" diff --git a/hw/unit_tests/cache/obj_dir/VVX_cache_classes.mk b/hw/unit_tests/cache/obj_dir/VVX_cache_classes.mk new file mode 100644 index 00000000..ddfe0f03 --- /dev/null +++ b/hw/unit_tests/cache/obj_dir/VVX_cache_classes.mk @@ -0,0 +1,43 @@ +# Verilated -*- Makefile -*- +# DESCRIPTION: Verilator output: Make include file with class lists +# +# This file lists generated Verilated files, for including in higher level makefiles. +# See VVX_cache.mk for the caller. + +### Switches... +# Coverage output mode? 0/1 (from --coverage) +VM_COVERAGE = 0 +# Threaded output mode? 0/1/N threads (from --threads) +VM_THREADS = 0 +# Tracing output mode? 0/1 (from --trace) +VM_TRACE = 1 +# Tracing threaded output mode? 0/1 (from --trace-fst-thread) +VM_TRACE_THREADED = 0 + +### Object file lists... +# Generated module classes, fast-path, compile with highest optimization +VM_CLASSES_FAST += \ + VVX_cache \ + +# Generated module classes, non-fast-path, compile with low/medium optimization +VM_CLASSES_SLOW += \ + +# Generated support classes, fast-path, compile with highest optimization +VM_SUPPORT_FAST += \ + VVX_cache__Trace \ + +# Generated support classes, non-fast-path, compile with low/medium optimization +VM_SUPPORT_SLOW += \ + VVX_cache__Syms \ + VVX_cache__Trace__Slow \ + +# Global classes, need linked once per executable, fast-path, compile with highest optimization +VM_GLOBAL_FAST += \ + verilated \ + verilated_vcd_c \ + +# Global classes, need linked once per executable, non-fast-path, compile with low/medium optimization +VM_GLOBAL_SLOW += \ + + +# Verilated -*- Makefile -*- diff --git a/hw/unit_tests/cache/obj_dir/cache_sim.d b/hw/unit_tests/cache/obj_dir/cache_sim.d new file mode 100644 index 00000000..55cd8534 --- /dev/null +++ b/hw/unit_tests/cache/obj_dir/cache_sim.d @@ -0,0 +1,6 @@ +cache_sim.o: ../cache_sim.cpp VVX_cache.h \ + /usr/local/share/verilator/include/verilated_heavy.h \ + /usr/local/share/verilator/include/verilated.h \ + /usr/local/share/verilator/include/verilatedos.h VVX_cache__Syms.h \ + VVX_cache.h /usr/local/share/verilator/include/verilated.h \ + /usr/local/share/verilator/include/verilated_vcd_c.h diff --git a/hw/unit_tests/cache/obj_dir/cache_sim.o b/hw/unit_tests/cache/obj_dir/cache_sim.o new file mode 100644 index 00000000..26536c9d Binary files /dev/null and b/hw/unit_tests/cache/obj_dir/cache_sim.o differ diff --git a/hw/unit_tests/cache/obj_dir/cachesim.d b/hw/unit_tests/cache/obj_dir/cachesim.d new file mode 100644 index 00000000..a04ca8a6 --- /dev/null +++ b/hw/unit_tests/cache/obj_dir/cachesim.d @@ -0,0 +1,6 @@ +cachesim.o: ../cachesim.cpp ../cachesim.h VVX_cache.h \ + /usr/local/share/verilator/include/verilated_heavy.h \ + /usr/local/share/verilator/include/verilated.h \ + /usr/local/share/verilator/include/verilatedos.h VVX_cache__Syms.h \ + VVX_cache.h /usr/local/share/verilator/include/verilated.h \ + /usr/local/share/verilator/include/verilated_vcd_c.h ../ram.h diff --git a/hw/unit_tests/cache/obj_dir/cachesim.o b/hw/unit_tests/cache/obj_dir/cachesim.o new file mode 100644 index 00000000..3f17c560 Binary files /dev/null and b/hw/unit_tests/cache/obj_dir/cachesim.o differ diff --git a/hw/unit_tests/cache/obj_dir/testbench.d b/hw/unit_tests/cache/obj_dir/testbench.d new file mode 100644 index 00000000..9ad98505 --- /dev/null +++ b/hw/unit_tests/cache/obj_dir/testbench.d @@ -0,0 +1,6 @@ +testbench.o: ../testbench.cpp ../cachesim.h VVX_cache.h \ + /usr/local/share/verilator/include/verilated_heavy.h \ + /usr/local/share/verilator/include/verilated.h \ + /usr/local/share/verilator/include/verilatedos.h VVX_cache__Syms.h \ + VVX_cache.h /usr/local/share/verilator/include/verilated.h \ + /usr/local/share/verilator/include/verilated_vcd_c.h ../ram.h diff --git a/hw/unit_tests/cache/obj_dir/testbench.o b/hw/unit_tests/cache/obj_dir/testbench.o new file mode 100644 index 00000000..d63e64eb Binary files /dev/null and b/hw/unit_tests/cache/obj_dir/testbench.o differ diff --git a/hw/unit_tests/cache/obj_dir/verilated.d b/hw/unit_tests/cache/obj_dir/verilated.d new file mode 100644 index 00000000..4f8241f8 --- /dev/null +++ b/hw/unit_tests/cache/obj_dir/verilated.d @@ -0,0 +1,8 @@ +verilated.o: /usr/local/share/verilator/include/verilated.cpp \ + /usr/local/share/verilator/include/verilatedos.h \ + /usr/local/share/verilator/include/verilated_imp.h \ + /usr/local/share/verilator/include/verilated.h \ + /usr/local/share/verilator/include/verilated_heavy.h \ + /usr/local/share/verilator/include/verilated_syms.h \ + /usr/local/share/verilator/include/verilated_sym_props.h \ + /usr/local/share/verilator/include/verilated_config.h diff --git a/hw/unit_tests/cache/obj_dir/verilated.o b/hw/unit_tests/cache/obj_dir/verilated.o new file mode 100644 index 00000000..ab682b8c Binary files /dev/null and b/hw/unit_tests/cache/obj_dir/verilated.o differ diff --git a/hw/unit_tests/cache/obj_dir/verilated_vcd_c.d b/hw/unit_tests/cache/obj_dir/verilated_vcd_c.d new file mode 100644 index 00000000..1240003b --- /dev/null +++ b/hw/unit_tests/cache/obj_dir/verilated_vcd_c.d @@ -0,0 +1,4 @@ +verilated_vcd_c.o: /usr/local/share/verilator/include/verilated_vcd_c.cpp \ + /usr/local/share/verilator/include/verilatedos.h \ + /usr/local/share/verilator/include/verilated.h \ + /usr/local/share/verilator/include/verilated_vcd_c.h diff --git a/hw/unit_tests/cache/obj_dir/verilated_vcd_c.o b/hw/unit_tests/cache/obj_dir/verilated_vcd_c.o new file mode 100644 index 00000000..5b89d1c5 Binary files /dev/null and b/hw/unit_tests/cache/obj_dir/verilated_vcd_c.o differ diff --git a/hw/unit_tests/cache/ram.h b/hw/unit_tests/cache/ram.h new file mode 100644 index 00000000..53df7e0f --- /dev/null +++ b/hw/unit_tests/cache/ram.h @@ -0,0 +1,64 @@ +#pragma once + +#include +#include + +class RAM { +private: + + mutable uint8_t *mem_[(1 << 12)]; + + uint8_t *get(uint32_t address) const { + uint32_t block_addr = address >> 20; + uint32_t block_offset = address & 0x000FFFFF; + if (mem_[block_addr] == NULL) { + mem_[block_addr] = new uint8_t[(1 << 20)]; + } + return mem_[block_addr] + block_offset; + } + +public: + + RAM() { + for (uint32_t i = 0; i < (1 << 12); i++) { + mem_[i] = NULL; + } + } + + ~RAM() { + this->clear(); + } + + size_t size() const { + return (1ull << 32); + } + + void clear() { + for (uint32_t i = 0; i < (1 << 12); i++) { + if (mem_[i]) { + delete mem_[i]; + mem_[i] = NULL; + } + } + } + + void read(uint32_t address, uint32_t length, uint8_t *data) const { + for (unsigned i = 0; i < length; i++) { + data[i] = *this->get(address + i); + } + } + + void write(uint32_t address, uint32_t length, const uint8_t *data) { + for (unsigned i = 0; i < length; i++) { + *this->get(address + i) = data[i]; + } + } + + uint8_t& operator[](uint32_t address) { + return *get(address); + } + + const uint8_t& operator[](uint32_t address) const { + return *get(address); + } +}; \ No newline at end of file diff --git a/hw/unit_tests/cache/testbench.cpp b/hw/unit_tests/cache/testbench.cpp new file mode 100644 index 00000000..c9f4e09f --- /dev/null +++ b/hw/unit_tests/cache/testbench.cpp @@ -0,0 +1,53 @@ +#include "cachesim.h" +#include +#include +#include + +#define VCD_OUTPUT 1 + +int main(int argc, char **argv) +{ + //init + RAM ram; + CacheSim cachesim; + cachesim.attach_ram(&ram); + + + // reset the device + cachesim.reset(); + + //write block to cache + cachesim.set_core_req(); + + for (int i = 0; i < 100; ++i){ + if(i == 1){ + cachesim.clear_req(); + } + cachesim.step(); + cachesim.get_core_rsp(); + } + + // read block + cachesim.set_core_req2(); + for (int i = 0; i < 100; ++i){ + if(i == 1){ + //read block from cache + cachesim.clear_req(); + + } + cachesim.step(); + cachesim.get_core_rsp(); + } + + /* + core_req_t *write; + write->valid = 1; + //write.tag = 0xff; //TODO: make a reasonable tag + //write.addr[0] = 0x11111111; + //write.addr[1] = 0x22222222; + //write.addr[2] = 0x33333333; + //write.addr[3] = 0x44444444; + //write. + */ + return 0; +} diff --git a/hw/unit_tests/cache/trace.vcd b/hw/unit_tests/cache/trace.vcd new file mode 100644 index 00000000..2b1cba44 --- /dev/null +++ b/hw/unit_tests/cache/trace.vcd @@ -0,0 +1,10541 @@ +$version Generated by VerilatedVcd $end +$date Mon Jul 13 23:53:11 2020 + $end +$timescale 1ns $end + + $scope module TOP $end + $var wire 1 Sh" clk $end + $var wire 120 {h" core_req_addr [119:0] $end + $var wire 16 sh" core_req_byteen [15:0] $end + $var wire 128 =i" core_req_data [127:0] $end + $var wire 1 mi" core_req_ready $end + $var wire 4 kh" core_req_rw [3:0] $end + $var wire 42 ]i" core_req_tag [41:0] $end + $var wire 4 ch" core_req_valid [3:0] $end + $var wire 128 }i" core_rsp_data [127:0] $end + $var wire 1 Oj" core_rsp_ready $end + $var wire 42 ?j" core_rsp_tag [41:0] $end + $var wire 4 ui" core_rsp_valid [3:0] $end + $var wire 28 oj" dram_req_addr [27:0] $end + $var wire 16 gj" dram_req_byteen [15:0] $end + $var wire 128 wj" dram_req_data [127:0] $end + $var wire 1 Ak" dram_req_ready $end + $var wire 1 _j" dram_req_rw $end + $var wire 28 9k" dram_req_tag [27:0] $end + $var wire 1 Wj" dram_req_valid $end + $var wire 128 Qk" dram_rsp_data [127:0] $end + $var wire 1 yk" dram_rsp_ready $end + $var wire 28 qk" dram_rsp_tag [27:0] $end + $var wire 1 Ik" dram_rsp_valid $end + $var wire 1 [h" reset $end + $var wire 2 Em" snp_fwdin_ready [1:0] $end + $var wire 2 =m" snp_fwdin_tag [1:0] $end + $var wire 2 5m" snp_fwdin_valid [1:0] $end + $var wire 56 kl" snp_fwdout_addr [55:0] $end + $var wire 2 {l" snp_fwdout_invalidate [1:0] $end + $var wire 2 -m" snp_fwdout_ready [1:0] $end + $var wire 2 %m" snp_fwdout_tag [1:0] $end + $var wire 2 cl" snp_fwdout_valid [1:0] $end + $var wire 28 +l" snp_req_addr [27:0] $end + $var wire 1 3l" snp_req_invalidate $end + $var wire 1 Cl" snp_req_ready $end + $var wire 28 ;l" snp_req_tag [27:0] $end + $var wire 1 #l" snp_req_valid $end + $var wire 1 [l" snp_rsp_ready $end + $var wire 28 Sl" snp_rsp_tag [27:0] $end + $var wire 1 Kl" snp_rsp_valid $end + $scope module VX_cache $end + $var wire 32 gn" BANK_LINE_SIZE [31:0] $end + $var wire 32 Wn" CACHE_ID [31:0] $end + $var wire 32 _n" CACHE_SIZE [31:0] $end + $var wire 32 )o" CORE_TAG_ID_BITS [31:0] $end + $var wire 32 !o" CORE_TAG_WIDTH [31:0] $end + $var wire 32 on" CREQ_SIZE [31:0] $end + $var wire 32 on" CWBQ_SIZE [31:0] $end + $var wire 32 gn" DFPQ_SIZE [31:0] $end + $var wire 32 on" DFQQ_SIZE [31:0] $end + $var wire 32 wn" DRAM_ENABLE [31:0] $end + $var wire 32 1o" DRAM_TAG_WIDTH [31:0] $end + $var wire 32 on" DWBQ_SIZE [31:0] $end + $var wire 32 gn" MRVQ_SIZE [31:0] $end + $var wire 32 on" NUM_BANKS [31:0] $end + $var wire 32 on" NUM_REQUESTS [31:0] $end + $var wire 32 9o" NUM_SNP_REQUESTS [31:0] $end + $var wire 32 wn" PRFQ_SIZE [31:0] $end + $var wire 32 Wn" PRFQ_STRIDE [31:0] $end + $var wire 32 Wn" SNOOP_FORWARDING [31:0] $end + $var wire 32 wn" SNP_FWD_TAG_WIDTH [31:0] $end + $var wire 32 1o" SNP_REQ_TAG_WIDTH [31:0] $end + $var wire 32 gn" SNRQ_SIZE [31:0] $end + $var wire 32 wn" STAGE_1_CYCLES [31:0] $end + $var wire 32 on" WORD_SIZE [31:0] $end + $var wire 32 wn" WRITE_ENABLE [31:0] $end + $var wire 1 Sh" clk $end + $var wire 120 {h" core_req_addr [119:0] $end + $var wire 16 sh" core_req_byteen [15:0] $end + $var wire 128 =i" core_req_data [127:0] $end + $var wire 1 mi" core_req_ready $end + $var wire 4 kh" core_req_rw [3:0] $end + $var wire 42 ]i" core_req_tag [41:0] $end + $var wire 4 ch" core_req_valid [3:0] $end + $var wire 128 }i" core_rsp_data [127:0] $end + $var wire 1 Oj" core_rsp_ready $end + $var wire 42 ?j" core_rsp_tag [41:0] $end + $var wire 4 ui" core_rsp_valid [3:0] $end + $var wire 1 )-! dram_fill_req_ready $end + $var wire 28 oj" dram_req_addr [27:0] $end + $var wire 16 gj" dram_req_byteen [15:0] $end + $var wire 128 wj" dram_req_data [127:0] $end + $var wire 1 Ak" dram_req_ready $end + $var wire 1 _j" dram_req_rw $end + $var wire 28 9k" dram_req_tag [27:0] $end + $var wire 1 Wj" dram_req_valid $end + $var wire 128 Qk" dram_rsp_data [127:0] $end + $var wire 1 yk" dram_rsp_ready $end + $var wire 28 qk" dram_rsp_tag [27:0] $end + $var wire 1 Ik" dram_rsp_valid $end + $var wire 4 Y+ per_bank_core_req_ready [3:0] $end + $var wire 128 q+ per_bank_core_rsp_data [127:0] $end + $var wire 4 + per_bank_core_rsp_ready [3:0] $end + $var wire 168 3, per_bank_core_rsp_tag [167:0] $end + $var wire 8 i+ per_bank_core_rsp_tid [7:0] $end + $var wire 4 a+ per_bank_core_rsp_valid [3:0] $end + $var wire 112 k, per_bank_dram_fill_req_addr [111:0] $end + $var wire 4 c, per_bank_dram_fill_req_valid [3:0] $end + $var wire 4 -- per_bank_dram_fill_rsp_ready [3:0] $end + $var wire 112 M- per_bank_dram_wb_req_addr [111:0] $end + $var wire 64 =- per_bank_dram_wb_req_byteen [63:0] $end + $var wire 512 m- per_bank_dram_wb_req_data [511:0] $end + $var wire 4 3 per_bank_dram_wb_req_ready [3:0] $end + $var wire 4 5- per_bank_dram_wb_req_valid [3:0] $end + $var wire 4 1/ per_bank_snp_req_ready [3:0] $end + $var wire 4 ; per_bank_snp_rsp_ready [3:0] $end + $var wire 112 A/ per_bank_snp_rsp_tag [111:0] $end + $var wire 4 9/ per_bank_snp_rsp_valid [3:0] $end + $var wire 16 # per_bank_valid [15:0] $end + $var wire 1 [h" reset $end + $var wire 2 Em" snp_fwdin_ready [1:0] $end + $var wire 2 =m" snp_fwdin_tag [1:0] $end + $var wire 2 5m" snp_fwdin_valid [1:0] $end + $var wire 56 kl" snp_fwdout_addr [55:0] $end + $var wire 2 {l" snp_fwdout_invalidate [1:0] $end + $var wire 2 -m" snp_fwdout_ready [1:0] $end + $var wire 2 %m" snp_fwdout_tag [1:0] $end + $var wire 2 cl" snp_fwdout_valid [1:0] $end + $var wire 28 +l" snp_req_addr [27:0] $end + $var wire 28 +l" snp_req_addr_qual [27:0] $end + $var wire 1 3l" snp_req_invalidate $end + $var wire 1 3l" snp_req_invalidate_qual $end + $var wire 1 Cl" snp_req_ready $end + $var wire 1 Mm" snp_req_ready_qual $end + $var wire 28 ;l" snp_req_tag [27:0] $end + $var wire 28 ;l" snp_req_tag_qual [27:0] $end + $var wire 1 #l" snp_req_valid $end + $var wire 1 #l" snp_req_valid_qual $end + $var wire 1 [l" snp_rsp_ready $end + $var wire 28 Sl" snp_rsp_tag [27:0] $end + $var wire 1 Kl" snp_rsp_valid $end + $scope module cache_core_req_bank_sel $end + $var wire 32 gn" BANK_LINE_SIZE [31:0] $end + $var wire 32 on" NUM_BANKS [31:0] $end + $var wire 32 on" NUM_REQUESTS [31:0] $end + $var wire 32 on" WORD_SIZE [31:0] $end + $var wire 120 {h" core_req_addr [119:0] $end + $var wire 1 mi" core_req_ready $end + $var wire 4 ch" core_req_valid [3:0] $end + $var wire 32 Ao" i [31:0] $end + $var wire 4 Y+ per_bank_ready [3:0] $end + $var wire 16 # per_bank_valid [15:0] $end + $scope module genblk2 $end + $var wire 4 e! per_bank_ready_sel [3:0] $end + $upscope $end + $upscope $end + $scope module cache_core_rsp_merge $end + $var wire 32 )o" CORE_TAG_ID_BITS [31:0] $end + $var wire 32 !o" CORE_TAG_WIDTH [31:0] $end + $var wire 32 on" NUM_BANKS [31:0] $end + $var wire 32 on" NUM_REQUESTS [31:0] $end + $var wire 32 on" WORD_SIZE [31:0] $end + $var wire 1 Sh" clk $end + $var wire 128 Y7 core_rsp_data [127:0] $end + $var wire 1 Oj" core_rsp_ready $end + $var wire 42 y7 core_rsp_tag [41:0] $end + $var wire 4 ui" core_rsp_valid [3:0] $end + $var wire 32 Ao" i [31:0] $end + $var wire 2 +8 main_bank_index [1:0] $end + $var wire 128 q+ per_bank_core_rsp_data [127:0] $end + $var wire 4 38 per_bank_core_rsp_pop_unqual [3:0] $end + $var wire 4 + per_bank_core_rsp_ready [3:0] $end + $var wire 168 3, per_bank_core_rsp_tag [167:0] $end + $var wire 8 i+ per_bank_core_rsp_tid [7:0] $end + $var wire 4 a+ per_bank_core_rsp_valid [3:0] $end + $var wire 1 [h" reset $end + $scope module sel_bank $end + $var wire 32 on" N [31:0] $end + $var wire 1 Sh" clk $end + $var wire 2 +8 grant_index [1:0] $end + $var wire 4 ;8 grant_onehot [3:0] $end + $var wire 1 C8 grant_valid $end + $var wire 4 a+ requests [3:0] $end + $var wire 1 [h" reset $end + $scope module genblk2 $end + $var wire 4 ;8 grant_onehot_r [3:0] $end + $var wire 4 S8 late_value [3:0] $end + $var wire 1 [2! refill $end + $var wire 4 c2! refill_original [3:0] $end + $var wire 4 a+ refill_value [3:0] $end + $var wire 4 S2! requests_use [3:0] $end + $var wire 4 K8 update_value [3:0] $end + $scope module priority_encoder $end + $var wire 32 on" N [31:0] $end + $var wire 4 S2! data_in [3:0] $end + $var wire 2 +8 data_out [1:0] $end + $var wire 32 [8 i [31:0] $end + $var wire 1 C8 valid_out $end + $upscope $end + $upscope $end + $upscope $end + $upscope $end + $scope module cache_dram_req_arb $end + $var wire 32 gn" BANK_LINE_SIZE [31:0] $end + $var wire 32 on" DFQQ_SIZE [31:0] $end + $var wire 32 on" NUM_BANKS [31:0] $end + $var wire 32 wn" PRFQ_SIZE [31:0] $end + $var wire 32 Wn" PRFQ_STRIDE [31:0] $end + $var wire 32 on" WORD_SIZE [31:0] $end + $var wire 1 Sh" clk $end + $var wire 1 c4 dfqq_empty $end + $var wire 1 {.! dfqq_full $end + $var wire 1 m! dfqq_pop $end + $var wire 1 k4 dfqq_push $end + $var wire 1 S4 dfqq_req $end + $var wire 28 [4 dfqq_req_addr [27:0] $end + $var wire 1 )-! dram_fill_req_ready $end + $var wire 28 oj" dram_req_addr [27:0] $end + $var wire 16 gj" dram_req_byteen [15:0] $end + $var wire 128 wj" dram_req_data [127:0] $end + $var wire 1 Ak" dram_req_ready $end + $var wire 1 _j" dram_req_rw $end + $var wire 1 Wj" dram_req_valid $end + $var wire 2 s4 dwb_bank [1:0] $end + $var wire 1 K4 dwb_valid $end + $var wire 112 k, per_bank_dram_fill_req_addr [111:0] $end + $var wire 4 c, per_bank_dram_fill_req_valid [3:0] $end + $var wire 112 M- per_bank_dram_wb_req_addr [111:0] $end + $var wire 64 =- per_bank_dram_wb_req_byteen [63:0] $end + $var wire 512 m- per_bank_dram_wb_req_data [511:0] $end + $var wire 4 3 per_bank_dram_wb_req_ready [3:0] $end + $var wire 4 5- per_bank_dram_wb_req_valid [3:0] $end + $var wire 28 s.! pref_addr [27:0] $end + $var wire 1 Io" pref_pop $end + $var wire 1 Io" pref_valid $end + $var wire 1 [h" reset $end + $scope module dram_fill_arb $end + $var wire 32 gn" BANK_LINE_SIZE [31:0] $end + $var wire 32 on" DFQQ_SIZE [31:0] $end + $var wire 32 on" NUM_BANKS [31:0] $end + $var wire 1 Sh" clk $end + $var wire 1 c4 dfqq_empty $end + $var wire 1 {.! dfqq_full $end + $var wire 1 m! dfqq_pop $end + $var wire 1 k4 dfqq_push $end + $var wire 1 S4 dfqq_req $end + $var wire 28 [4 dfqq_req_addr [27:0] $end + $var wire 1 u/! o_empty $end + $var wire 1 /6 out_empty $end + $var wire 112 =5 out_per_bank_dram_fill_req_addr [111:0] $end + $var wire 4 55 out_per_bank_dram_fill_req_valid [3:0] $end + $var wire 112 k, per_bank_dram_fill_req_addr [111:0] $end + $var wire 4 c, per_bank_dram_fill_req_valid [3:0] $end + $var wire 1 /* pop_qual $end + $var wire 1 76 push_qual $end + $var wire 112 e5 qual_bank_dram_fill_req_addr [111:0] $end + $var wire 1 G6 qual_has_request $end + $var wire 2 ?6 qual_request_index [1:0] $end + $var wire 1 [h" reset $end + $var wire 4 '6 updated_bank_dram_fill_req_valid [3:0] $end + $var wire 1 }/! use_empty $end + $var wire 112 U/! use_per_bank_dram_fill_req_addr [111:0] $end + $var wire 4 M/! use_per_bank_dram_fill_req_valid [3:0] $end + $var wire 4 ]5 use_per_bqual_bank_dram_fill_req_valid [3:0] $end + $scope module dfqq_queue $end + $var wire 32 wn" BUFFERED_OUTPUT [31:0] $end + $var wire 32 Qo" DATAW [31:0] $end + $var wire 32 on" SIZE [31:0] $end + $var wire 1 Sh" clk $end + $var wire 116 O6 data_in [115:0] $end + $var wire 116 o6 data_out [115:0] $end + $var wire 1 u/! empty $end + $var wire 1 {.! full $end + $var wire 1 /* pop $end + $var wire 1 76 push $end + $var wire 1 u! reading $end + $var wire 1 [h" reset $end + $var wire 3 '0! size [2:0] $end + $var wire 3 '0! size_r [2:0] $end + $var wire 1 17 writing $end + $scope module genblk3 $end + $var wire 116 /0! data(0) [115:0] $end + $var wire 116 30! data(1) [115:0] $end + $var wire 116 70! data(2) [115:0] $end + $var wire 116 ;0! data(3) [115:0] $end + $scope module genblk2 $end + $var wire 1 K2! bypass_r $end + $var wire 116 q1! curr_r [115:0] $end + $var wire 1 u/! empty_r $end + $var wire 1 {.! full_r $end + $var wire 116 Q1! head_r [115:0] $end + $var wire 2 C2! rd_ptr_next_r [1:0] $end + $var wire 2 ;2! rd_ptr_r [1:0] $end + $var wire 2 32! wr_ptr_r [1:0] $end + $upscope $end + $upscope $end + $upscope $end + $scope module sel_bank $end + $var wire 32 on" N [31:0] $end + $var wire 1 Sh" clk $end + $var wire 2 ?6 grant_index [1:0] $end + $var wire 4 97 grant_onehot [3:0] $end + $var wire 1 G6 grant_valid $end + $var wire 4 ]5 requests [3:0] $end + $var wire 1 [h" reset $end + $scope module genblk2 $end + $var wire 4 97 grant_onehot_r [3:0] $end + $scope module priority_encoder $end + $var wire 32 on" N [31:0] $end + $var wire 4 ]5 data_in [3:0] $end + $var wire 2 ?6 data_out [1:0] $end + $var wire 32 A7 i [31:0] $end + $var wire 1 G6 valid_out $end + $upscope $end + $upscope $end + $upscope $end + $upscope $end + $scope module prfqq $end + $var wire 32 gn" BANK_LINE_SIZE [31:0] $end + $var wire 32 wn" PRFQ_SIZE [31:0] $end + $var wire 32 Wn" PRFQ_STRIDE [31:0] $end + $var wire 32 on" WORD_SIZE [31:0] $end + $var wire 1 Sh" clk $end + $var wire 28 5/! current_addr [27:0] $end + $var wire 1 =/! current_empty $end + $var wire 1 -/! current_full $end + $var wire 1 -/! current_valid $end + $var wire 1 Gn" dram_req $end + $var wire 28 oj" dram_req_addr [27:0] $end + $var wire 28 s.! pref_addr [27:0] $end + $var wire 1 Io" pref_pop $end + $var wire 1 Io" pref_valid $end + $var wire 1 [h" reset $end + $var wire 1 {4 update_use $end + $var wire 28 s.! use_addr [27:0] $end + $var wire 2 %/! use_valid [1:0] $end + $scope module pfq_queue $end + $var wire 32 wn" BUFFERED_OUTPUT [31:0] $end + $var wire 32 1o" DATAW [31:0] $end + $var wire 32 wn" SIZE [31:0] $end + $var wire 1 Sh" clk $end + $var wire 28 oj" data_in [27:0] $end + $var wire 28 5/! data_out [27:0] $end + $var wire 1 =/! empty $end + $var wire 1 -/! full $end + $var wire 1 {4 pop $end + $var wire 1 On" push $end + $var wire 1 %5 reading $end + $var wire 1 [h" reset $end + $var wire 1 E/! size [0:0] $end + $var wire 1 E/! size_r [0:0] $end + $var wire 1 -5 writing $end + $scope module genblk2 $end + $var wire 28 5/! head_r [27:0] $end + $upscope $end + $upscope $end + $upscope $end + $scope module sel_dwb $end + $var wire 32 on" N [31:0] $end + $var wire 1 Sh" clk $end + $var wire 2 s4 grant_index [1:0] $end + $var wire 4 I7 grant_onehot [3:0] $end + $var wire 1 K4 grant_valid $end + $var wire 4 5- requests [3:0] $end + $var wire 1 [h" reset $end + $scope module genblk2 $end + $var wire 4 I7 grant_onehot_r [3:0] $end + $scope module priority_encoder $end + $var wire 32 on" N [31:0] $end + $var wire 4 5- data_in [3:0] $end + $var wire 2 s4 data_out [1:0] $end + $var wire 32 Q7 i [31:0] $end + $var wire 1 K4 valid_out $end + $upscope $end + $upscope $end + $upscope $end + $upscope $end + $scope module genblk5(0) $end + $var wire 120 {h" curr_bank_core_req_addr [119:0] $end + $var wire 16 sh" curr_bank_core_req_byteen [15:0] $end + $var wire 128 =i" curr_bank_core_req_data [127:0] $end + $var wire 1 Q-! curr_bank_core_req_ready $end + $var wire 4 kh" curr_bank_core_req_rw [3:0] $end + $var wire 42 ]i" curr_bank_core_req_tag [41:0] $end + $var wire 4 C curr_bank_core_req_valid [3:0] $end + $var wire 32 i/ curr_bank_core_rsp_data [31:0] $end + $var wire 1 K curr_bank_core_rsp_ready $end + $var wire 42 q/ curr_bank_core_rsp_tag [41:0] $end + $var wire 2 a/ curr_bank_core_rsp_tid [1:0] $end + $var wire 1 1-! curr_bank_core_rsp_valid $end + $var wire 26 A-! curr_bank_dram_fill_req_addr [25:0] $end + $var wire 1 )-! curr_bank_dram_fill_req_ready $end + $var wire 1 #0 curr_bank_dram_fill_req_valid $end + $var wire 26 ]m" curr_bank_dram_fill_rsp_addr [25:0] $end + $var wire 128 Qk" curr_bank_dram_fill_rsp_data [127:0] $end + $var wire 1 9-! curr_bank_dram_fill_rsp_ready $end + $var wire 1 Um" curr_bank_dram_fill_rsp_valid $end + $var wire 26 ;0 curr_bank_dram_wb_req_addr [25:0] $end + $var wire 16 30 curr_bank_dram_wb_req_byteen [15:0] $end + $var wire 128 C0 curr_bank_dram_wb_req_data [127:0] $end + $var wire 1 S curr_bank_dram_wb_req_ready $end + $var wire 1 +0 curr_bank_dram_wb_req_valid $end + $var wire 26 mm" curr_bank_snp_req_addr [25:0] $end + $var wire 1 3l" curr_bank_snp_req_invalidate $end + $var wire 1 I-! curr_bank_snp_req_ready $end + $var wire 28 ;l" curr_bank_snp_req_tag [27:0] $end + $var wire 1 em" curr_bank_snp_req_valid $end + $var wire 1 [ curr_bank_snp_rsp_ready $end + $var wire 28 k0 curr_bank_snp_rsp_tag [27:0] $end + $var wire 1 c0 curr_bank_snp_rsp_valid $end + $scope module bank $end + $var wire 32 Yo" BANK_ID [31:0] $end + $var wire 32 gn" BANK_LINE_SIZE [31:0] $end + $var wire 32 Wn" CACHE_ID [31:0] $end + $var wire 32 _n" CACHE_SIZE [31:0] $end + $var wire 32 )o" CORE_TAG_ID_BITS [31:0] $end + $var wire 32 !o" CORE_TAG_WIDTH [31:0] $end + $var wire 32 on" CREQ_SIZE [31:0] $end + $var wire 32 on" CWBQ_SIZE [31:0] $end + $var wire 32 gn" DFPQ_SIZE [31:0] $end + $var wire 32 on" DFQQ_SIZE [31:0] $end + $var wire 32 wn" DRAM_ENABLE [31:0] $end + $var wire 32 on" DWBQ_SIZE [31:0] $end + $var wire 32 gn" MRVQ_SIZE [31:0] $end + $var wire 32 on" NUM_BANKS [31:0] $end + $var wire 32 on" NUM_REQUESTS [31:0] $end + $var wire 32 Wn" SNOOP_FORWARDING [31:0] $end + $var wire 32 1o" SNP_REQ_TAG_WIDTH [31:0] $end + $var wire 32 gn" SNRQ_SIZE [31:0] $end + $var wire 32 wn" STAGE_1_CYCLES [31:0] $end + $var wire 32 on" WORD_SIZE [31:0] $end + $var wire 32 wn" WRITE_ENABLE [31:0] $end + $var wire 26 == addr_st1(0) [25:0] $end + $var wire 26 ;@ addr_st1e [25:0] $end + $var wire 26 A-! addr_st2 [25:0] $end + $var wire 1 Sh" clk $end + $var wire 120 {h" core_req_addr [119:0] $end + $var wire 16 sh" core_req_byteen [15:0] $end + $var wire 128 =i" core_req_data [127:0] $end + $var wire 1 Q-! core_req_ready $end + $var wire 4 kh" core_req_rw [3:0] $end + $var wire 42 ]i" core_req_tag [41:0] $end + $var wire 4 C core_req_valid [3:0] $end + $var wire 32 i/ core_rsp_data [31:0] $end + $var wire 1 K core_rsp_ready $end + $var wire 42 q/ core_rsp_tag [41:0] $end + $var wire 2 a/ core_rsp_tid [1:0] $end + $var wire 1 1-! core_rsp_valid $end + $var wire 32 )5! cwbq_data [31:0] $end + $var wire 1 [6! cwbq_empty $end + $var wire 1 c6! cwbq_full $end + $var wire 1 ?* cwbq_pop $end + $var wire 1 {@ cwbq_push $end + $var wire 1 9; cwbq_push_stall $end + $var wire 1 %A cwbq_push_unqual $end + $var wire 42 G4! cwbq_tag [41:0] $end + $var wire 2 ?4! cwbq_tid [1:0] $end + $var wire 26 M9 dfpq_addr_st0 [25:0] $end + $var wire 1 {2! dfpq_empty $end + $var wire 128 U9 dfpq_filldata_st0 [127:0] $end + $var wire 1 %3! dfpq_full $end + $var wire 1 E9 dfpq_pop $end + $var wire 1 q; dfpq_pop_unqual $end + $var wire 1 w> dirty_st1e $end + $var wire 1 Y5! dirty_st2 $end + $var wire 16 !? dirtyb_st1e [15:0] $end + $var wire 16 a5! dirtyb_st2 [15:0] $end + $var wire 26 A-! dram_fill_req_addr [25:0] $end + $var wire 1 c@ dram_fill_req_fast $end + $var wire 1 )-! dram_fill_req_ready $end + $var wire 1 I; dram_fill_req_stall $end + $var wire 1 -A dram_fill_req_unqual $end + $var wire 1 #0 dram_fill_req_valid $end + $var wire 26 ]m" dram_fill_rsp_addr [25:0] $end + $var wire 128 Qk" dram_fill_rsp_data [127:0] $end + $var wire 1 9-! dram_fill_rsp_ready $end + $var wire 1 Um" dram_fill_rsp_valid $end + $var wire 26 ;0 dram_wb_req_addr [25:0] $end + $var wire 16 30 dram_wb_req_byteen [15:0] $end + $var wire 128 C0 dram_wb_req_data [127:0] $end + $var wire 1 }! dram_wb_req_fire $end + $var wire 1 S dram_wb_req_ready $end + $var wire 1 +0 dram_wb_req_valid $end + $var wire 1 -7! dwbq_dual_valid_sel $end + $var wire 1 k6! dwbq_empty $end + $var wire 1 s6! dwbq_full $end + $var wire 1 =A dwbq_is_dwb_in $end + $var wire 1 MA dwbq_is_dwb_out $end + $var wire 1 EA dwbq_is_snp_in $end + $var wire 1 UA dwbq_is_snp_out $end + $var wire 1 G* dwbq_pop $end + $var wire 1 5A dwbq_push $end + $var wire 1 A; dwbq_push_stall $end + $var wire 1 ]A dwbq_push_unqual $end + $var wire 26 {6! dwbq_req_addr [25:0] $end + $var wire 1 Q? fill_saw_dirty_st1e $end + $var wire 1 #6! fill_saw_dirty_st2 $end + $var wire 1 !; force_request_miss_st1e $end + $var wire 1 i; going_to_write_st1(0) $end + $var wire 49 U= inst_meta_st1(0) [48:0] $end + $var wire 49 i5! inst_meta_st2 [48:0] $end + $var wire 1 Y; is_fill_in_pipe $end + $var wire 1 a; is_fill_st1(0) $end + $var wire 1 g4! is_fill_st2 $end + $var wire 1 7> is_mrvq_st1(0) $end + $var wire 1 +@ is_mrvq_st1e $end + $var wire 1 +@ is_mrvq_st1e_st2 $end + $var wire 1 C6! is_mrvq_st2 $end + $var wire 1 '> is_snp_st1(0) $end + $var wire 1 Y? is_snp_st1e $end + $var wire 1 +6! is_snp_st2 $end + $var wire 32 ao" j [31:0] $end + $var wire 4 I? mem_byteen_st1e [3:0] $end + $var wire 1 A? mem_rw_st1e $end + $var wire 1 k@ miss_add $end + $var wire 26 A-! miss_add_addr [25:0] $end + $var wire 1 y? miss_add_because_miss $end + $var wire 1 ;6! miss_add_because_pending $end + $var wire 4 _4! miss_add_byteen [3:0] $end + $var wire 32 !5! miss_add_data [31:0] $end + $var wire 1 s@ miss_add_is_mrvq $end + $var wire 1 +6! miss_add_is_snp $end + $var wire 1 W4! miss_add_rw $end + $var wire 1 36! miss_add_snp_invalidate $end + $var wire 42 G4! miss_add_tag [41:0] $end + $var wire 2 ?4! miss_add_tid [1:0] $end + $var wire 1 c@ miss_add_unqual $end + $var wire 2 w4! miss_add_wsel [1:0] $end + $var wire 1 o> miss_st1e $end + $var wire 1 Q5! miss_st2 $end + $var wire 26 ]3! mrvq_addr_st0 [25:0] $end + $var wire 4 '4! mrvq_byteen_st0 [3:0] $end + $var wire 1 E3! mrvq_full $end + $var wire 1 S@ mrvq_init_ready_state_hazard_st0_st1 $end + $var wire 1 [@ mrvq_init_ready_state_hazard_st1e_st1 $end + $var wire 1 q? mrvq_init_ready_state_st1e $end + $var wire 1 K@ mrvq_init_ready_state_st2 $end + $var wire 1 S6! mrvq_init_ready_state_unqual_st2 $end + $var wire 1 /4! mrvq_is_snp_st0 $end + $var wire 1 o: mrvq_pending_hazard_st1e $end + $var wire 1 W: mrvq_pop $end + $var wire 1 _: mrvq_pop_unqual $end + $var wire 1 1; mrvq_push_stall $end + $var wire 1 3@ mrvq_recover_ready_state_st1e $end + $var wire 1 K6! mrvq_recover_ready_state_st2 $end + $var wire 1 g: mrvq_rw_st0 $end + $var wire 1 74! mrvq_snp_invalidate_st0 $end + $var wire 1 M3! mrvq_stop $end + $var wire 42 u3! mrvq_tag_st0 [41:0] $end + $var wire 2 U3! mrvq_tid_st0 [1:0] $end + $var wire 1 _: mrvq_valid_st0 $end + $var wire 32 m3! mrvq_writeword_st0 [31:0] $end + $var wire 2 e3! mrvq_wsel_st0 [1:0] $end + $var wire 26 3< qual_addr_st0 [25:0] $end + $var wire 1 {< qual_going_to_write_st0 $end + $var wire 49 k< qual_inst_meta_st0 [48:0] $end + $var wire 1 q; qual_is_fill_st0 $end + $var wire 1 _: qual_is_mrvq_st0 $end + $var wire 1 %= qual_is_snp_st0 $end + $var wire 1 -= qual_snp_invalidate_st0 $end + $var wire 1 +< qual_valid_st0 $end + $var wire 1 C@ qual_valid_st1e_2 $end + $var wire 128 K< qual_writedata_st0 [127:0] $end + $var wire 32 C< qual_writeword_st0 [31:0] $end + $var wire 2 ;< qual_wsel_st0 [1:0] $end + $var wire 128 G> readdata_st1e [127:0] $end + $var wire 128 15! readdata_st2 [127:0] $end + $var wire 20 g> readtag_st1e [19:0] $end + $var wire 20 y5! readtag_st2 [19:0] $end + $var wire 32 ?> readword_st1e [31:0] $end + $var wire 32 )5! readword_st2 [31:0] $end + $var wire 1 ); recover_mrvq_state_st2 $end + $var wire 1 }9 reqq_empty $end + $var wire 1 -3! reqq_full $end + $var wire 1 u9 reqq_pop $end + $var wire 1 y; reqq_pop_unqual $end + $var wire 1 7* reqq_push $end + $var wire 30 G: reqq_req_addr_st0 [29:0] $end + $var wire 4 ?: reqq_req_byteen_st0 [3:0] $end + $var wire 1 7: reqq_req_rw_st0 $end + $var wire 1 ': reqq_req_st0 $end + $var wire 42 53! reqq_req_tag_st0 [41:0] $end + $var wire 2 /: reqq_req_tid_st0 [1:0] $end + $var wire 32 O: reqq_req_writeword_st0 [31:0] $end + $var wire 1 [h" reset $end + $var wire 1 /> snp_invalidate_st1(0) $end + $var wire 1 a? snp_invalidate_st1e $end + $var wire 1 36! snp_invalidate_st2 $end + $var wire 26 mm" snp_req_addr [25:0] $end + $var wire 1 3l" snp_req_invalidate $end + $var wire 1 I-! snp_req_ready $end + $var wire 28 ;l" snp_req_tag [27:0] $end + $var wire 1 em" snp_req_valid $end + $var wire 1 '" snp_rsp_fire $end + $var wire 1 [ snp_rsp_ready $end + $var wire 28 k0 snp_rsp_tag [27:0] $end + $var wire 1 c0 snp_rsp_valid $end + $var wire 1 i? snp_to_mrvq_st1e $end + $var wire 1 ;6! snp_to_mrvq_st2 $end + $var wire 26 -9 snrq_addr_st0 [25:0] $end + $var wire 1 k2! snrq_empty $end + $var wire 1 s2! snrq_full $end + $var wire 1 59 snrq_invalidate_st0 $end + $var wire 1 %9 snrq_pop $end + $var wire 1 #< snrq_pop_unqual $end + $var wire 28 =9 snrq_tag_st0 [27:0] $end + $var wire 28 %7! snrq_tag_st2 [27:0] $end + $var wire 1 w: st2_pending_hazard_st1e $end + $var wire 1 Q; stall_bank_pipe $end + $var wire 42 )? tag_st1e [41:0] $end + $var wire 2 9? tid_st1e [1:0] $end + $var wire 1 5= valid_st1(0) $end + $var wire 1 #@ valid_st1e $end + $var wire 1 o4! valid_st2 $end + $var wire 128 e= writedata_st1(0) [127:0] $end + $var wire 32 M= writeword_st1(0) [31:0] $end + $var wire 32 !5! writeword_st2 [31:0] $end + $var wire 2 E= wsel_st1(0) [1:0] $end + $var wire 2 w4! wsel_st2 [1:0] $end + $scope module cache_miss_resrv $end + $var wire 32 Yo" BANK_ID [31:0] $end + $var wire 32 gn" BANK_LINE_SIZE [31:0] $end + $var wire 32 Wn" CACHE_ID [31:0] $end + $var wire 32 !o" CORE_TAG_WIDTH [31:0] $end + $var wire 32 gn" MRVQ_SIZE [31:0] $end + $var wire 32 on" NUM_BANKS [31:0] $end + $var wire 32 on" NUM_REQUESTS [31:0] $end + $var wire 32 1o" SNP_REQ_TAG_WIDTH [31:0] $end + $var wire 32 on" WORD_SIZE [31:0] $end + $var wire 416 'P! addr_table [415:0] $end + $var wire 1 Sh" clk $end + $var wire 4 AQ! dequeue_index [3:0] $end + $var wire 1 _: dequeue_possible $end + $var wire 4 QQ! enqueue_index [3:0] $end + $var wire 1 aQ! enqueue_possible $end + $var wire 26 ;@ fill_addr_st1 [25:0] $end + $var wire 4 IQ! head_ptr [3:0] $end + $var wire 1 IK increment_head $end + $var wire 1 eE is_fill_st1 $end + $var wire 1 s@ is_mrvq $end + $var wire 16 wJ make_ready [15:0] $end + $var wire 16 !K make_ready_push [15:0] $end + $var wire 85 }K! metadata_table(0) [84:0] $end + $var wire 85 "L! metadata_table(1) [84:0] $end + $var wire 85 =L! metadata_table(10) [84:0] $end + $var wire 85 @L! metadata_table(11) [84:0] $end + $var wire 85 CL! metadata_table(12) [84:0] $end + $var wire 85 FL! metadata_table(13) [84:0] $end + $var wire 85 IL! metadata_table(14) [84:0] $end + $var wire 85 LL! metadata_table(15) [84:0] $end + $var wire 85 %L! metadata_table(2) [84:0] $end + $var wire 85 (L! metadata_table(3) [84:0] $end + $var wire 85 +L! metadata_table(4) [84:0] $end + $var wire 85 .L! metadata_table(5) [84:0] $end + $var wire 85 1L! metadata_table(6) [84:0] $end + $var wire 85 4L! metadata_table(7) [84:0] $end + $var wire 85 7L! metadata_table(8) [84:0] $end + $var wire 85 :L! metadata_table(9) [84:0] $end + $var wire 1 k@ miss_add $end + $var wire 26 A-! miss_add_addr [25:0] $end + $var wire 4 _4! miss_add_byteen [3:0] $end + $var wire 32 !5! miss_add_data [31:0] $end + $var wire 1 +6! miss_add_is_snp $end + $var wire 1 W4! miss_add_rw $end + $var wire 1 36! miss_add_snp_invalidate $end + $var wire 42 G4! miss_add_tag [41:0] $end + $var wire 2 ?4! miss_add_tid [1:0] $end + $var wire 2 w4! miss_add_wsel [1:0] $end + $var wire 26 ]3! miss_resrv_addr_st0 [25:0] $end + $var wire 4 '4! miss_resrv_byteen_st0 [3:0] $end + $var wire 32 m3! miss_resrv_data_st0 [31:0] $end + $var wire 1 E3! miss_resrv_full $end + $var wire 1 /4! miss_resrv_is_snp_st0 $end + $var wire 1 W: miss_resrv_pop $end + $var wire 1 g: miss_resrv_rw_st0 $end + $var wire 1 74! miss_resrv_snp_invalidate_st0 $end + $var wire 1 M3! miss_resrv_stop $end + $var wire 42 u3! miss_resrv_tag_st0 [41:0] $end + $var wire 2 U3! miss_resrv_tid_st0 [1:0] $end + $var wire 1 _: miss_resrv_valid_st0 $end + $var wire 2 e3! miss_resrv_wsel_st0 [1:0] $end + $var wire 1 K@ mrvq_init_ready_state $end + $var wire 1 9K mrvq_pop $end + $var wire 1 1K mrvq_push $end + $var wire 1 o: pending_hazard $end + $var wire 1 YK qual_mrvq_init $end + $var wire 16 9Q! ready_table [15:0] $end + $var wire 1 AK recover_state $end + $var wire 1 [h" reset $end + $var wire 4 AQ! schedule_ptr [3:0] $end + $var wire 5 YQ! size [4:0] $end + $var wire 4 QQ! tail_ptr [3:0] $end + $var wire 1 QK update_ready $end + $var wire 16 )K valid_address_match [15:0] $end + $var wire 16 1Q! valid_table [15:0] $end + $upscope $end + $scope module core_req_arb $end + $var wire 32 )o" CORE_TAG_ID_BITS [31:0] $end + $var wire 32 !o" CORE_TAG_WIDTH [31:0] $end + $var wire 32 on" CREQ_SIZE [31:0] $end + $var wire 32 on" NUM_REQUESTS [31:0] $end + $var wire 32 on" WORD_SIZE [31:0] $end + $var wire 120 {h" bank_addr [119:0] $end + $var wire 16 sh" bank_byteen [15:0] $end + $var wire 4 kh" bank_rw [3:0] $end + $var wire 42 ]i" bank_tag [41:0] $end + $var wire 4 C bank_valids [3:0] $end + $var wire 128 =i" bank_writedata [127:0] $end + $var wire 1 Sh" clk $end + $var wire 1 eC! o_empty $end + $var wire 1 YC out_empty $end + $var wire 120 gB out_per_addr [119:0] $end + $var wire 16 _B out_per_byteen [15:0] $end + $var wire 4 WB out_per_rw [3:0] $end + $var wire 42 IC out_per_tag [41:0] $end + $var wire 4 OB out_per_valids [3:0] $end + $var wire 128 )C out_per_writedata [127:0] $end + $var wire 1 aC pop_qual $end + $var wire 1 O* push_qual $end + $var wire 120 %C! qual_addr [119:0] $end + $var wire 16 {B! qual_byteen [15:0] $end + $var wire 1 ': qual_has_request $end + $var wire 2 /: qual_request_index [1:0] $end + $var wire 4 sB! qual_rw [3:0] $end + $var wire 42 53! qual_tag [41:0] $end + $var wire 4 kB! qual_valids [3:0] $end + $var wire 128 EC! qual_writedata [127:0] $end + $var wire 4 iC real_out_per_valids [3:0] $end + $var wire 1 }9 reqq_empty $end + $var wire 1 -3! reqq_full $end + $var wire 1 u9 reqq_pop $end + $var wire 1 7* reqq_push $end + $var wire 30 G: reqq_req_addr_st0 [29:0] $end + $var wire 4 ?: reqq_req_byteen_st0 [3:0] $end + $var wire 1 7: reqq_req_rw_st0 $end + $var wire 1 ': reqq_req_st0 $end + $var wire 42 53! reqq_req_tag_st0 [41:0] $end + $var wire 2 /: reqq_req_tid_st0 [1:0] $end + $var wire 32 O: reqq_req_writedata_st0 [31:0] $end + $var wire 1 [h" reset $end + $var wire 1 mC! use_empty $end + $var wire 120 %C! use_per_addr [119:0] $end + $var wire 16 {B! use_per_byteen [15:0] $end + $var wire 4 sB! use_per_rw [3:0] $end + $var wire 42 53! use_per_tag [41:0] $end + $var wire 4 kB! use_per_valids [3:0] $end + $var wire 128 EC! use_per_writedata [127:0] $end + $scope module reqq_queue $end + $var wire 32 wn" BUFFERED_OUTPUT [31:0] $end + $var wire 32 yo" DATAW [31:0] $end + $var wire 32 on" SIZE [31:0] $end + $var wire 1 Sh" clk $end + $var wire 314 w" data_in [313:0] $end + $var wire 314 qC data_out [313:0] $end + $var wire 1 eC! empty $end + $var wire 1 -3! full $end + $var wire 1 aC pop $end + $var wire 1 O* push $end + $var wire 1 cD reading $end + $var wire 1 [h" reset $end + $var wire 3 uC! size [2:0] $end + $var wire 3 uC! size_r [2:0] $end + $var wire 1 i# writing $end + $scope module genblk3 $end + $var wire 314 }C! data(0) [313:0] $end + $var wire 314 )D! data(1) [313:0] $end + $var wire 314 3D! data(2) [313:0] $end + $var wire 314 =D! data(3) [313:0] $end + $scope module genblk2 $end + $var wire 1 AI! bypass_r $end + $var wire 314 7H! curr_r [313:0] $end + $var wire 1 eC! empty_r $end + $var wire 1 -3! full_r $end + $var wire 314 EG! head_r [313:0] $end + $var wire 2 9I! rd_ptr_next_r [1:0] $end + $var wire 2 1I! rd_ptr_r [1:0] $end + $var wire 2 )I! wr_ptr_r [1:0] $end + $upscope $end + $upscope $end + $upscope $end + $scope module sel_bank $end + $var wire 32 on" N [31:0] $end + $var wire 1 Sh" clk $end + $var wire 2 /: grant_index [1:0] $end + $var wire 4 kD grant_onehot [3:0] $end + $var wire 1 ': grant_valid $end + $var wire 4 kB! requests [3:0] $end + $var wire 1 [h" reset $end + $scope module genblk2 $end + $var wire 4 kD grant_onehot_r [3:0] $end + $scope module priority_encoder $end + $var wire 32 on" N [31:0] $end + $var wire 4 kB! data_in [3:0] $end + $var wire 2 /: data_out [1:0] $end + $var wire 32 sD i [31:0] $end + $var wire 1 ': valid_out $end + $upscope $end + $upscope $end + $upscope $end + $upscope $end + $scope module cwb_queue $end + $var wire 32 wn" BUFFERED_OUTPUT [31:0] $end + $var wire 32 ;p" DATAW [31:0] $end + $var wire 32 on" SIZE [31:0] $end + $var wire 1 Sh" clk $end + $var wire 76 aK data_in [75:0] $end + $var wire 76 yK data_out [75:0] $end + $var wire 1 [6! empty $end + $var wire 1 c6! full $end + $var wire 1 ?* pop $end + $var wire 1 {@ push $end + $var wire 1 q# reading $end + $var wire 1 [h" reset $end + $var wire 3 iQ! size [2:0] $end + $var wire 3 iQ! size_r [2:0] $end + $var wire 1 3L writing $end + $scope module genblk3 $end + $var wire 76 qQ! data(0) [75:0] $end + $var wire 76 tQ! data(1) [75:0] $end + $var wire 76 wQ! data(2) [75:0] $end + $var wire 76 zQ! data(3) [75:0] $end + $scope module genblk2 $end + $var wire 1 ]S! bypass_r $end + $var wire 76 -S! curr_r [75:0] $end + $var wire 1 [6! empty_r $end + $var wire 1 c6! full_r $end + $var wire 76 sR! head_r [75:0] $end + $var wire 2 US! rd_ptr_next_r [1:0] $end + $var wire 2 MS! rd_ptr_r [1:0] $end + $var wire 2 ES! wr_ptr_r [1:0] $end + $upscope $end + $upscope $end + $upscope $end + $scope module dfp_queue $end + $var wire 32 wn" BUFFERED_OUTPUT [31:0] $end + $var wire 32 qo" DATAW [31:0] $end + $var wire 32 gn" SIZE [31:0] $end + $var wire 1 Sh" clk $end + $var wire 154 G" data_in [153:0] $end + $var wire 154 }A data_out [153:0] $end + $var wire 1 {2! empty $end + $var wire 1 %3! full $end + $var wire 1 E9 pop $end + $var wire 1 Um" push $end + $var wire 1 GB reading $end + $var wire 1 [h" reset $end + $var wire 5 c:! size [4:0] $end + $var wire 5 c:! size_r [4:0] $end + $var wire 1 o" writing $end + $scope module genblk3 $end + $var wire 154 k:! data(0) [153:0] $end + $var wire 154 p:! data(1) [153:0] $end + $var wire 154 ?;! data(10) [153:0] $end + $var wire 154 D;! data(11) [153:0] $end + $var wire 154 I;! data(12) [153:0] $end + $var wire 154 N;! data(13) [153:0] $end + $var wire 154 S;! data(14) [153:0] $end + $var wire 154 X;! data(15) [153:0] $end + $var wire 154 u:! data(2) [153:0] $end + $var wire 154 z:! data(3) [153:0] $end + $var wire 154 !;! data(4) [153:0] $end + $var wire 154 &;! data(5) [153:0] $end + $var wire 154 +;! data(6) [153:0] $end + $var wire 154 0;! data(7) [153:0] $end + $var wire 154 5;! data(8) [153:0] $end + $var wire 154 :;! data(9) [153:0] $end + $scope module genblk2 $end + $var wire 1 cB! bypass_r $end + $var wire 154 #B! curr_r [153:0] $end + $var wire 1 {2! empty_r $end + $var wire 1 %3! full_r $end + $var wire 154 YA! head_r [153:0] $end + $var wire 4 [B! rd_ptr_next_r [3:0] $end + $var wire 4 SB! rd_ptr_r [3:0] $end + $var wire 4 KB! wr_ptr_r [3:0] $end + $upscope $end + $upscope $end + $upscope $end + $scope module dwb_queue $end + $var wire 32 wn" BUFFERED_OUTPUT [31:0] $end + $var wire 32 Cp" DATAW [31:0] $end + $var wire 32 on" SIZE [31:0] $end + $var wire 1 Sh" clk $end + $var wire 200 ;L data_in [199:0] $end + $var wire 200 sL data_out [199:0] $end + $var wire 1 k6! empty $end + $var wire 1 s6! full $end + $var wire 1 G* pop $end + $var wire 1 5A push $end + $var wire 1 y# reading $end + $var wire 1 [h" reset $end + $var wire 3 eS! size [2:0] $end + $var wire 3 eS! size_r [2:0] $end + $var wire 1 MM writing $end + $scope module genblk3 $end + $var wire 200 mS! data(0) [199:0] $end + $var wire 200 tS! data(1) [199:0] $end + $var wire 200 {S! data(2) [199:0] $end + $var wire 200 $T! data(3) [199:0] $end + $scope module genblk2 $end + $var wire 1 ]W! bypass_r $end + $var wire 200 kV! curr_r [199:0] $end + $var wire 1 k6! empty_r $end + $var wire 1 s6! full_r $end + $var wire 200 3V! head_r [199:0] $end + $var wire 2 UW! rd_ptr_next_r [1:0] $end + $var wire 2 MW! rd_ptr_r [1:0] $end + $var wire 2 EW! wr_ptr_r [1:0] $end + $upscope $end + $upscope $end + $upscope $end + $scope module s0_1_c0 $end + $var wire 32 #p" N [31:0] $end + $var wire 32 Wn" PASSTHRU [31:0] $end + $var wire 1 Sh" clk $end + $var wire 1 Io" flush $end + $var wire 243 {D in [242:0] $end + $var wire 243 II! out [242:0] $end + $var wire 1 [h" reset $end + $var wire 1 Q; stall $end + $var wire 243 II! value [242:0] $end + $upscope $end + $scope module snp_req_queue $end + $var wire 32 wn" BUFFERED_OUTPUT [31:0] $end + $var wire 32 io" DATAW [31:0] $end + $var wire 32 gn" SIZE [31:0] $end + $var wire 1 Sh" clk $end + $var wire 55 /" data_in [54:0] $end + $var wire 55 eA data_out [54:0] $end + $var wire 1 k2! empty $end + $var wire 1 s2! full $end + $var wire 1 %9 pop $end + $var wire 1 em" push $end + $var wire 1 uA reading $end + $var wire 1 [h" reset $end + $var wire 5 57! size [4:0] $end + $var wire 5 57! size_r [4:0] $end + $var wire 1 ?" writing $end + $scope module genblk3 $end + $var wire 55 =7! data(0) [54:0] $end + $var wire 55 ?7! data(1) [54:0] $end + $var wire 55 Q7! data(10) [54:0] $end + $var wire 55 S7! data(11) [54:0] $end + $var wire 55 U7! data(12) [54:0] $end + $var wire 55 W7! data(13) [54:0] $end + $var wire 55 Y7! data(14) [54:0] $end + $var wire 55 [7! data(15) [54:0] $end + $var wire 55 A7! data(2) [54:0] $end + $var wire 55 C7! data(3) [54:0] $end + $var wire 55 E7! data(4) [54:0] $end + $var wire 55 G7! data(5) [54:0] $end + $var wire 55 I7! data(6) [54:0] $end + $var wire 55 K7! data(7) [54:0] $end + $var wire 55 M7! data(8) [54:0] $end + $var wire 55 O7! data(9) [54:0] $end + $scope module genblk2 $end + $var wire 1 [:! bypass_r $end + $var wire 55 3:! curr_r [54:0] $end + $var wire 1 k2! empty_r $end + $var wire 1 s2! full_r $end + $var wire 55 #:! head_r [54:0] $end + $var wire 4 S:! rd_ptr_next_r [3:0] $end + $var wire 4 K:! rd_ptr_r [3:0] $end + $var wire 4 C:! wr_ptr_r [3:0] $end + $upscope $end + $upscope $end + $upscope $end + $scope module st_1e_2 $end + $var wire 32 3p" N [31:0] $end + $var wire 32 Wn" PASSTHRU [31:0] $end + $var wire 1 Sh" clk $end + $var wire 1 Io" flush $end + $var wire 316 'J in [315:0] $end + $var wire 316 -K! out [315:0] $end + $var wire 1 [h" reset $end + $var wire 1 Q; stall $end + $var wire 316 -K! value [315:0] $end + $upscope $end + $scope module tag_data_access $end + $var wire 32 gn" BANK_LINE_SIZE [31:0] $end + $var wire 32 _n" CACHE_SIZE [31:0] $end + $var wire 32 wn" DRAM_ENABLE [31:0] $end + $var wire 32 on" NUM_BANKS [31:0] $end + $var wire 32 wn" STAGE_1_CYCLES [31:0] $end + $var wire 32 on" WORD_SIZE [31:0] $end + $var wire 32 wn" WRITE_ENABLE [31:0] $end + $var wire 1 Sh" clk $end + $var wire 128 yG data_write [127:0] $end + $var wire 1 w> dirty_st1e $end + $var wire 16 !? dirtyb_st1e [15:0] $end + $var wire 1 Q? fill_saw_dirty_st1e $end + $var wire 1 o> fill_sent $end + $var wire 1 %I force_core_miss $end + $var wire 1 !; force_request_miss_st1e $end + $var wire 1 ;H invalidate_line $end + $var wire 1 Y? is_snp_st1e $end + $var wire 4 I? mem_byteen_st1e [3:0] $end + $var wire 1 A? mem_rw_st1e $end + $var wire 1 o> miss_st1e $end + $var wire 1 q? mrvq_init_ready_state_st1e $end + $var wire 128 AG qual_read_data_st1 [127:0] $end + $var wire 1 )G qual_read_dirty_st1 $end + $var wire 16 1G qual_read_dirtyb_st1 [15:0] $end + $var wire 20 9G qual_read_tag_st1 [19:0] $end + $var wire 1 !G qual_read_valid_st1 $end + $var wire 128 _F read_data_st1c(0) [127:0] $end + $var wire 1 GF read_dirty_st1c(0) $end + $var wire 16 OF read_dirtyb_st1c(0) [15:0] $end + $var wire 20 WF read_tag_st1c(0) [19:0] $end + $var wire 1 ?F read_valid_st1c(0) $end + $var wire 6 ]E readaddr_st10 [5:0] $end + $var wire 128 G> readdata_st1e [127:0] $end + $var wire 20 g> readtag_st1e [19:0] $end + $var wire 32 ?> readword_st1e [31:0] $end + $var wire 1 {H real_miss $end + $var wire 1 KH real_writefill $end + $var wire 1 kH req_invalid $end + $var wire 1 sH req_miss $end + $var wire 1 [h" reset $end + $var wire 1 cH should_write $end + $var wire 1 ;H snoop_hit_no_pending $end + $var wire 1 a? snp_invalidate_st1e $end + $var wire 1 i? snp_to_mrvq_st1e $end + $var wire 1 Q; stall $end + $var wire 1 Q; stall_bank_pipe $end + $var wire 1 CH tags_match $end + $var wire 128 G> use_read_data_st1e [127:0] $end + $var wire 1 iG use_read_dirty_st1e $end + $var wire 16 !? use_read_dirtyb_st1e [15:0] $end + $var wire 20 g> use_read_tag_st1e [19:0] $end + $var wire 1 aG use_read_valid_st1e $end + $var wire 128 yG use_write_data [127:0] $end + $var wire 16 qG use_write_enable [15:0] $end + $var wire 1 #@ valid_req_st1e $end + $var wire 16 [H we [15:0] $end + $var wire 2 7F wordsel_st1e [1:0] $end + $var wire 26 ;@ writeaddr_st1e [25:0] $end + $var wire 128 uE writedata_st1e [127:0] $end + $var wire 1 eE writefill_st1e $end + $var wire 6 ]E writeladdr_st1e [5:0] $end + $var wire 20 SH writetag_st1e [19:0] $end + $var wire 32 mE writeword_st1e [31:0] $end + $scope module genblk4(0) $end + $var wire 1 -I normal_write $end + $upscope $end + $scope module genblk4(1) $end + $var wire 1 5I normal_write $end + $upscope $end + $scope module genblk4(2) $end + $var wire 1 =I normal_write $end + $upscope $end + $scope module genblk4(3) $end + $var wire 1 EI normal_write $end + $upscope $end + $scope module s0_1_c0 $end + $var wire 32 +p" N [31:0] $end + $var wire 32 wn" PASSTHRU [31:0] $end + $var wire 1 Sh" clk $end + $var wire 1 Io" flush $end + $var wire 166 UI in [165:0] $end + $var wire 166 UI out [165:0] $end + $var wire 1 [h" reset $end + $var wire 1 Q; stall $end + $var wire 166 [J! value [165:0] $end + $upscope $end + $scope module tag_data_structure $end + $var wire 32 gn" BANK_LINE_SIZE [31:0] $end + $var wire 32 _n" CACHE_SIZE [31:0] $end + $var wire 32 on" NUM_BANKS [31:0] $end + $var wire 32 on" WORD_SIZE [31:0] $end + $var wire 1 Sh" clk $end + $var wire 64 +J! dirty [63:0] $end + $var wire 1 MI do_write $end + $var wire 1 o> fill_sent $end + $var wire 32 KJ! i [31:0] $end + $var wire 1 ;H invalidate $end + $var wire 32 SJ! j [31:0] $end + $var wire 6 ]E read_addr [5:0] $end + $var wire 128 AG read_data [127:0] $end + $var wire 1 )G read_dirty $end + $var wire 16 1G read_dirtyb [15:0] $end + $var wire 20 9G read_tag [19:0] $end + $var wire 1 !G read_valid $end + $var wire 1 [h" reset $end + $var wire 1 Q; stall_bank_pipe $end + $var wire 20 SH tag_index [19:0] $end + $var wire 64 ;J! valid [63:0] $end + $var wire 6 ]E write_addr [5:0] $end + $var wire 128 yG write_data [127:0] $end + $var wire 16 qG write_enable [15:0] $end + $var wire 1 KH write_fill $end + $upscope $end + $upscope $end + $upscope $end + $upscope $end + $scope module genblk5(1) $end + $var wire 120 {h" curr_bank_core_req_addr [119:0] $end + $var wire 16 sh" curr_bank_core_req_byteen [15:0] $end + $var wire 128 =i" curr_bank_core_req_data [127:0] $end + $var wire 1 y-! curr_bank_core_req_ready $end + $var wire 4 kh" curr_bank_core_req_rw [3:0] $end + $var wire 42 ]i" curr_bank_core_req_tag [41:0] $end + $var wire 4 c curr_bank_core_req_valid [3:0] $end + $var wire 32 {0 curr_bank_core_rsp_data [31:0] $end + $var wire 1 k curr_bank_core_rsp_ready $end + $var wire 42 %1 curr_bank_core_rsp_tag [41:0] $end + $var wire 2 s0 curr_bank_core_rsp_tid [1:0] $end + $var wire 1 Y-! curr_bank_core_rsp_valid $end + $var wire 26 i-! curr_bank_dram_fill_req_addr [25:0] $end + $var wire 1 )-! curr_bank_dram_fill_req_ready $end + $var wire 1 51 curr_bank_dram_fill_req_valid $end + $var wire 26 ]m" curr_bank_dram_fill_rsp_addr [25:0] $end + $var wire 128 Qk" curr_bank_dram_fill_rsp_data [127:0] $end + $var wire 1 a-! curr_bank_dram_fill_rsp_ready $end + $var wire 1 um" curr_bank_dram_fill_rsp_valid $end + $var wire 26 M1 curr_bank_dram_wb_req_addr [25:0] $end + $var wire 16 E1 curr_bank_dram_wb_req_byteen [15:0] $end + $var wire 128 U1 curr_bank_dram_wb_req_data [127:0] $end + $var wire 1 s curr_bank_dram_wb_req_ready $end + $var wire 1 =1 curr_bank_dram_wb_req_valid $end + $var wire 26 mm" curr_bank_snp_req_addr [25:0] $end + $var wire 1 3l" curr_bank_snp_req_invalidate $end + $var wire 1 q-! curr_bank_snp_req_ready $end + $var wire 28 ;l" curr_bank_snp_req_tag [27:0] $end + $var wire 1 }m" curr_bank_snp_req_valid $end + $var wire 1 { curr_bank_snp_rsp_ready $end + $var wire 28 }1 curr_bank_snp_rsp_tag [27:0] $end + $var wire 1 u1 curr_bank_snp_rsp_valid $end + $scope module bank $end + $var wire 32 ao" BANK_ID [31:0] $end + $var wire 32 gn" BANK_LINE_SIZE [31:0] $end + $var wire 32 Wn" CACHE_ID [31:0] $end + $var wire 32 _n" CACHE_SIZE [31:0] $end + $var wire 32 )o" CORE_TAG_ID_BITS [31:0] $end + $var wire 32 !o" CORE_TAG_WIDTH [31:0] $end + $var wire 32 on" CREQ_SIZE [31:0] $end + $var wire 32 on" CWBQ_SIZE [31:0] $end + $var wire 32 gn" DFPQ_SIZE [31:0] $end + $var wire 32 on" DFQQ_SIZE [31:0] $end + $var wire 32 wn" DRAM_ENABLE [31:0] $end + $var wire 32 on" DWBQ_SIZE [31:0] $end + $var wire 32 gn" MRVQ_SIZE [31:0] $end + $var wire 32 on" NUM_BANKS [31:0] $end + $var wire 32 on" NUM_REQUESTS [31:0] $end + $var wire 32 Wn" SNOOP_FORWARDING [31:0] $end + $var wire 32 1o" SNP_REQ_TAG_WIDTH [31:0] $end + $var wire 32 gn" SNRQ_SIZE [31:0] $end + $var wire 32 wn" STAGE_1_CYCLES [31:0] $end + $var wire 32 on" WORD_SIZE [31:0] $end + $var wire 32 wn" WRITE_ENABLE [31:0] $end + $var wire 26 mQ addr_st1(0) [25:0] $end + $var wire 26 kT addr_st1e [25:0] $end + $var wire 26 i-! addr_st2 [25:0] $end + $var wire 1 Sh" clk $end + $var wire 120 {h" core_req_addr [119:0] $end + $var wire 16 sh" core_req_byteen [15:0] $end + $var wire 128 =i" core_req_data [127:0] $end + $var wire 1 y-! core_req_ready $end + $var wire 4 kh" core_req_rw [3:0] $end + $var wire 42 ]i" core_req_tag [41:0] $end + $var wire 4 c core_req_valid [3:0] $end + $var wire 32 {0 core_rsp_data [31:0] $end + $var wire 1 k core_rsp_ready $end + $var wire 42 %1 core_rsp_tag [41:0] $end + $var wire 2 s0 core_rsp_tid [1:0] $end + $var wire 1 Y-! core_rsp_valid $end + $var wire 32 #Z! cwbq_data [31:0] $end + $var wire 1 U[! cwbq_empty $end + $var wire 1 ][! cwbq_full $end + $var wire 1 _* cwbq_pop $end + $var wire 1 MU cwbq_push $end + $var wire 1 iO cwbq_push_stall $end + $var wire 1 UU cwbq_push_unqual $end + $var wire 42 AY! cwbq_tag [41:0] $end + $var wire 2 9Y! cwbq_tid [1:0] $end + $var wire 26 }M dfpq_addr_st0 [25:0] $end + $var wire 1 uW! dfpq_empty $end + $var wire 128 'N dfpq_filldata_st0 [127:0] $end + $var wire 1 }W! dfpq_full $end + $var wire 1 uM dfpq_pop $end + $var wire 1 CP dfpq_pop_unqual $end + $var wire 1 IS dirty_st1e $end + $var wire 1 SZ! dirty_st2 $end + $var wire 16 QS dirtyb_st1e [15:0] $end + $var wire 16 [Z! dirtyb_st2 [15:0] $end + $var wire 26 i-! dram_fill_req_addr [25:0] $end + $var wire 1 5U dram_fill_req_fast $end + $var wire 1 )-! dram_fill_req_ready $end + $var wire 1 yO dram_fill_req_stall $end + $var wire 1 ]U dram_fill_req_unqual $end + $var wire 1 51 dram_fill_req_valid $end + $var wire 26 ]m" dram_fill_rsp_addr [25:0] $end + $var wire 128 Qk" dram_fill_rsp_data [127:0] $end + $var wire 1 a-! dram_fill_rsp_ready $end + $var wire 1 um" dram_fill_rsp_valid $end + $var wire 26 M1 dram_wb_req_addr [25:0] $end + $var wire 16 E1 dram_wb_req_byteen [15:0] $end + $var wire 128 U1 dram_wb_req_data [127:0] $end + $var wire 1 #$ dram_wb_req_fire $end + $var wire 1 s dram_wb_req_ready $end + $var wire 1 =1 dram_wb_req_valid $end + $var wire 1 '\! dwbq_dual_valid_sel $end + $var wire 1 e[! dwbq_empty $end + $var wire 1 m[! dwbq_full $end + $var wire 1 mU dwbq_is_dwb_in $end + $var wire 1 }U dwbq_is_dwb_out $end + $var wire 1 uU dwbq_is_snp_in $end + $var wire 1 'V dwbq_is_snp_out $end + $var wire 1 g* dwbq_pop $end + $var wire 1 eU dwbq_push $end + $var wire 1 qO dwbq_push_stall $end + $var wire 1 /V dwbq_push_unqual $end + $var wire 26 u[! dwbq_req_addr [25:0] $end + $var wire 1 #T fill_saw_dirty_st1e $end + $var wire 1 {Z! fill_saw_dirty_st2 $end + $var wire 1 QO force_request_miss_st1e $end + $var wire 1 ;P going_to_write_st1(0) $end + $var wire 49 'R inst_meta_st1(0) [48:0] $end + $var wire 49 cZ! inst_meta_st2 [48:0] $end + $var wire 1 +P is_fill_in_pipe $end + $var wire 1 3P is_fill_st1(0) $end + $var wire 1 aY! is_fill_st2 $end + $var wire 1 gR is_mrvq_st1(0) $end + $var wire 1 [T is_mrvq_st1e $end + $var wire 1 [T is_mrvq_st1e_st2 $end + $var wire 1 =[! is_mrvq_st2 $end + $var wire 1 WR is_snp_st1(0) $end + $var wire 1 +T is_snp_st1e $end + $var wire 1 %[! is_snp_st2 $end + $var wire 32 ao" j [31:0] $end + $var wire 4 yS mem_byteen_st1e [3:0] $end + $var wire 1 qS mem_rw_st1e $end + $var wire 1 =U miss_add $end + $var wire 26 i-! miss_add_addr [25:0] $end + $var wire 1 KT miss_add_because_miss $end + $var wire 1 5[! miss_add_because_pending $end + $var wire 4 YY! miss_add_byteen [3:0] $end + $var wire 32 yY! miss_add_data [31:0] $end + $var wire 1 EU miss_add_is_mrvq $end + $var wire 1 %[! miss_add_is_snp $end + $var wire 1 QY! miss_add_rw $end + $var wire 1 -[! miss_add_snp_invalidate $end + $var wire 42 AY! miss_add_tag [41:0] $end + $var wire 2 9Y! miss_add_tid [1:0] $end + $var wire 1 5U miss_add_unqual $end + $var wire 2 qY! miss_add_wsel [1:0] $end + $var wire 1 AS miss_st1e $end + $var wire 1 KZ! miss_st2 $end + $var wire 26 WX! mrvq_addr_st0 [25:0] $end + $var wire 4 !Y! mrvq_byteen_st0 [3:0] $end + $var wire 1 ?X! mrvq_full $end + $var wire 1 %U mrvq_init_ready_state_hazard_st0_st1 $end + $var wire 1 -U mrvq_init_ready_state_hazard_st1e_st1 $end + $var wire 1 CT mrvq_init_ready_state_st1e $end + $var wire 1 {T mrvq_init_ready_state_st2 $end + $var wire 1 M[! mrvq_init_ready_state_unqual_st2 $end + $var wire 1 )Y! mrvq_is_snp_st0 $end + $var wire 1 AO mrvq_pending_hazard_st1e $end + $var wire 1 )O mrvq_pop $end + $var wire 1 1O mrvq_pop_unqual $end + $var wire 1 aO mrvq_push_stall $end + $var wire 1 cT mrvq_recover_ready_state_st1e $end + $var wire 1 E[! mrvq_recover_ready_state_st2 $end + $var wire 1 9O mrvq_rw_st0 $end + $var wire 1 1Y! mrvq_snp_invalidate_st0 $end + $var wire 1 GX! mrvq_stop $end + $var wire 42 oX! mrvq_tag_st0 [41:0] $end + $var wire 2 OX! mrvq_tid_st0 [1:0] $end + $var wire 1 1O mrvq_valid_st0 $end + $var wire 32 gX! mrvq_writeword_st0 [31:0] $end + $var wire 2 _X! mrvq_wsel_st0 [1:0] $end + $var wire 26 cP qual_addr_st0 [25:0] $end + $var wire 1 MQ qual_going_to_write_st0 $end + $var wire 49 =Q qual_inst_meta_st0 [48:0] $end + $var wire 1 CP qual_is_fill_st0 $end + $var wire 1 1O qual_is_mrvq_st0 $end + $var wire 1 UQ qual_is_snp_st0 $end + $var wire 1 ]Q qual_snp_invalidate_st0 $end + $var wire 1 [P qual_valid_st0 $end + $var wire 1 sT qual_valid_st1e_2 $end + $var wire 128 {P qual_writedata_st0 [127:0] $end + $var wire 32 sP qual_writeword_st0 [31:0] $end + $var wire 2 kP qual_wsel_st0 [1:0] $end + $var wire 128 wR readdata_st1e [127:0] $end + $var wire 128 +Z! readdata_st2 [127:0] $end + $var wire 20 9S readtag_st1e [19:0] $end + $var wire 20 sZ! readtag_st2 [19:0] $end + $var wire 32 oR readword_st1e [31:0] $end + $var wire 32 #Z! readword_st2 [31:0] $end + $var wire 1 YO recover_mrvq_state_st2 $end + $var wire 1 ON reqq_empty $end + $var wire 1 'X! reqq_full $end + $var wire 1 GN reqq_pop $end + $var wire 1 KP reqq_pop_unqual $end + $var wire 1 W* reqq_push $end + $var wire 30 wN reqq_req_addr_st0 [29:0] $end + $var wire 4 oN reqq_req_byteen_st0 [3:0] $end + $var wire 1 gN reqq_req_rw_st0 $end + $var wire 1 WN reqq_req_st0 $end + $var wire 42 /X! reqq_req_tag_st0 [41:0] $end + $var wire 2 _N reqq_req_tid_st0 [1:0] $end + $var wire 32 !O reqq_req_writeword_st0 [31:0] $end + $var wire 1 [h" reset $end + $var wire 1 _R snp_invalidate_st1(0) $end + $var wire 1 3T snp_invalidate_st1e $end + $var wire 1 -[! snp_invalidate_st2 $end + $var wire 26 mm" snp_req_addr [25:0] $end + $var wire 1 3l" snp_req_invalidate $end + $var wire 1 q-! snp_req_ready $end + $var wire 28 ;l" snp_req_tag [27:0] $end + $var wire 1 }m" snp_req_valid $end + $var wire 1 +$ snp_rsp_fire $end + $var wire 1 { snp_rsp_ready $end + $var wire 28 }1 snp_rsp_tag [27:0] $end + $var wire 1 u1 snp_rsp_valid $end + $var wire 1 ;T snp_to_mrvq_st1e $end + $var wire 1 5[! snp_to_mrvq_st2 $end + $var wire 26 ]M snrq_addr_st0 [25:0] $end + $var wire 1 eW! snrq_empty $end + $var wire 1 mW! snrq_full $end + $var wire 1 eM snrq_invalidate_st0 $end + $var wire 1 UM snrq_pop $end + $var wire 1 SP snrq_pop_unqual $end + $var wire 28 mM snrq_tag_st0 [27:0] $end + $var wire 28 }[! snrq_tag_st2 [27:0] $end + $var wire 1 IO st2_pending_hazard_st1e $end + $var wire 1 #P stall_bank_pipe $end + $var wire 42 YS tag_st1e [41:0] $end + $var wire 2 iS tid_st1e [1:0] $end + $var wire 1 eQ valid_st1(0) $end + $var wire 1 ST valid_st1e $end + $var wire 1 iY! valid_st2 $end + $var wire 128 7R writedata_st1(0) [127:0] $end + $var wire 32 }Q writeword_st1(0) [31:0] $end + $var wire 32 yY! writeword_st2 [31:0] $end + $var wire 2 uQ wsel_st1(0) [1:0] $end + $var wire 2 qY! wsel_st2 [1:0] $end + $scope module cache_miss_resrv $end + $var wire 32 ao" BANK_ID [31:0] $end + $var wire 32 gn" BANK_LINE_SIZE [31:0] $end + $var wire 32 Wn" CACHE_ID [31:0] $end + $var wire 32 !o" CORE_TAG_WIDTH [31:0] $end + $var wire 32 gn" MRVQ_SIZE [31:0] $end + $var wire 32 on" NUM_BANKS [31:0] $end + $var wire 32 on" NUM_REQUESTS [31:0] $end + $var wire 32 1o" SNP_REQ_TAG_WIDTH [31:0] $end + $var wire 32 on" WORD_SIZE [31:0] $end + $var wire 416 !u! addr_table [415:0] $end + $var wire 1 Sh" clk $end + $var wire 4 ;v! dequeue_index [3:0] $end + $var wire 1 1O dequeue_possible $end + $var wire 4 Kv! enqueue_index [3:0] $end + $var wire 1 [v! enqueue_possible $end + $var wire 26 kT fill_addr_st1 [25:0] $end + $var wire 4 Cv! head_ptr [3:0] $end + $var wire 1 y_ increment_head $end + $var wire 1 7Z is_fill_st1 $end + $var wire 1 EU is_mrvq $end + $var wire 16 I_ make_ready [15:0] $end + $var wire 16 Q_ make_ready_push [15:0] $end + $var wire 85 wp! metadata_table(0) [84:0] $end + $var wire 85 zp! metadata_table(1) [84:0] $end + $var wire 85 7q! metadata_table(10) [84:0] $end + $var wire 85 :q! metadata_table(11) [84:0] $end + $var wire 85 =q! metadata_table(12) [84:0] $end + $var wire 85 @q! metadata_table(13) [84:0] $end + $var wire 85 Cq! metadata_table(14) [84:0] $end + $var wire 85 Fq! metadata_table(15) [84:0] $end + $var wire 85 }p! metadata_table(2) [84:0] $end + $var wire 85 "q! metadata_table(3) [84:0] $end + $var wire 85 %q! metadata_table(4) [84:0] $end + $var wire 85 (q! metadata_table(5) [84:0] $end + $var wire 85 +q! metadata_table(6) [84:0] $end + $var wire 85 .q! metadata_table(7) [84:0] $end + $var wire 85 1q! metadata_table(8) [84:0] $end + $var wire 85 4q! metadata_table(9) [84:0] $end + $var wire 1 =U miss_add $end + $var wire 26 i-! miss_add_addr [25:0] $end + $var wire 4 YY! miss_add_byteen [3:0] $end + $var wire 32 yY! miss_add_data [31:0] $end + $var wire 1 %[! miss_add_is_snp $end + $var wire 1 QY! miss_add_rw $end + $var wire 1 -[! miss_add_snp_invalidate $end + $var wire 42 AY! miss_add_tag [41:0] $end + $var wire 2 9Y! miss_add_tid [1:0] $end + $var wire 2 qY! miss_add_wsel [1:0] $end + $var wire 26 WX! miss_resrv_addr_st0 [25:0] $end + $var wire 4 !Y! miss_resrv_byteen_st0 [3:0] $end + $var wire 32 gX! miss_resrv_data_st0 [31:0] $end + $var wire 1 ?X! miss_resrv_full $end + $var wire 1 )Y! miss_resrv_is_snp_st0 $end + $var wire 1 )O miss_resrv_pop $end + $var wire 1 9O miss_resrv_rw_st0 $end + $var wire 1 1Y! miss_resrv_snp_invalidate_st0 $end + $var wire 1 GX! miss_resrv_stop $end + $var wire 42 oX! miss_resrv_tag_st0 [41:0] $end + $var wire 2 OX! miss_resrv_tid_st0 [1:0] $end + $var wire 1 1O miss_resrv_valid_st0 $end + $var wire 2 _X! miss_resrv_wsel_st0 [1:0] $end + $var wire 1 {T mrvq_init_ready_state $end + $var wire 1 i_ mrvq_pop $end + $var wire 1 a_ mrvq_push $end + $var wire 1 AO pending_hazard $end + $var wire 1 +` qual_mrvq_init $end + $var wire 16 3v! ready_table [15:0] $end + $var wire 1 q_ recover_state $end + $var wire 1 [h" reset $end + $var wire 4 ;v! schedule_ptr [3:0] $end + $var wire 5 Sv! size [4:0] $end + $var wire 4 Kv! tail_ptr [3:0] $end + $var wire 1 #` update_ready $end + $var wire 16 Y_ valid_address_match [15:0] $end + $var wire 16 +v! valid_table [15:0] $end + $upscope $end + $scope module core_req_arb $end + $var wire 32 )o" CORE_TAG_ID_BITS [31:0] $end + $var wire 32 !o" CORE_TAG_WIDTH [31:0] $end + $var wire 32 on" CREQ_SIZE [31:0] $end + $var wire 32 on" NUM_REQUESTS [31:0] $end + $var wire 32 on" WORD_SIZE [31:0] $end + $var wire 120 {h" bank_addr [119:0] $end + $var wire 16 sh" bank_byteen [15:0] $end + $var wire 4 kh" bank_rw [3:0] $end + $var wire 42 ]i" bank_tag [41:0] $end + $var wire 4 c bank_valids [3:0] $end + $var wire 128 =i" bank_writedata [127:0] $end + $var wire 1 Sh" clk $end + $var wire 1 _h! o_empty $end + $var wire 1 +X out_empty $end + $var wire 120 9W out_per_addr [119:0] $end + $var wire 16 1W out_per_byteen [15:0] $end + $var wire 4 )W out_per_rw [3:0] $end + $var wire 42 yW out_per_tag [41:0] $end + $var wire 4 !W out_per_valids [3:0] $end + $var wire 128 YW out_per_writedata [127:0] $end + $var wire 1 3X pop_qual $end + $var wire 1 o* push_qual $end + $var wire 120 }g! qual_addr [119:0] $end + $var wire 16 ug! qual_byteen [15:0] $end + $var wire 1 WN qual_has_request $end + $var wire 2 _N qual_request_index [1:0] $end + $var wire 4 mg! qual_rw [3:0] $end + $var wire 42 /X! qual_tag [41:0] $end + $var wire 4 eg! qual_valids [3:0] $end + $var wire 128 ?h! qual_writedata [127:0] $end + $var wire 4 ;X real_out_per_valids [3:0] $end + $var wire 1 ON reqq_empty $end + $var wire 1 'X! reqq_full $end + $var wire 1 GN reqq_pop $end + $var wire 1 W* reqq_push $end + $var wire 30 wN reqq_req_addr_st0 [29:0] $end + $var wire 4 oN reqq_req_byteen_st0 [3:0] $end + $var wire 1 gN reqq_req_rw_st0 $end + $var wire 1 WN reqq_req_st0 $end + $var wire 42 /X! reqq_req_tag_st0 [41:0] $end + $var wire 2 _N reqq_req_tid_st0 [1:0] $end + $var wire 32 !O reqq_req_writedata_st0 [31:0] $end + $var wire 1 [h" reset $end + $var wire 1 gh! use_empty $end + $var wire 120 }g! use_per_addr [119:0] $end + $var wire 16 ug! use_per_byteen [15:0] $end + $var wire 4 mg! use_per_rw [3:0] $end + $var wire 42 /X! use_per_tag [41:0] $end + $var wire 4 eg! use_per_valids [3:0] $end + $var wire 128 ?h! use_per_writedata [127:0] $end + $scope module reqq_queue $end + $var wire 32 wn" BUFFERED_OUTPUT [31:0] $end + $var wire 32 yo" DATAW [31:0] $end + $var wire 32 on" SIZE [31:0] $end + $var wire 1 Sh" clk $end + $var wire 314 {$ data_in [313:0] $end + $var wire 314 CX data_out [313:0] $end + $var wire 1 _h! empty $end + $var wire 1 'X! full $end + $var wire 1 3X pop $end + $var wire 1 o* push $end + $var wire 1 5Y reading $end + $var wire 1 [h" reset $end + $var wire 3 oh! size [2:0] $end + $var wire 3 oh! size_r [2:0] $end + $var wire 1 m% writing $end + $scope module genblk3 $end + $var wire 314 wh! data(0) [313:0] $end + $var wire 314 #i! data(1) [313:0] $end + $var wire 314 -i! data(2) [313:0] $end + $var wire 314 7i! data(3) [313:0] $end + $scope module genblk2 $end + $var wire 1 ;n! bypass_r $end + $var wire 314 1m! curr_r [313:0] $end + $var wire 1 _h! empty_r $end + $var wire 1 'X! full_r $end + $var wire 314 ?l! head_r [313:0] $end + $var wire 2 3n! rd_ptr_next_r [1:0] $end + $var wire 2 +n! rd_ptr_r [1:0] $end + $var wire 2 #n! wr_ptr_r [1:0] $end + $upscope $end + $upscope $end + $upscope $end + $scope module sel_bank $end + $var wire 32 on" N [31:0] $end + $var wire 1 Sh" clk $end + $var wire 2 _N grant_index [1:0] $end + $var wire 4 =Y grant_onehot [3:0] $end + $var wire 1 WN grant_valid $end + $var wire 4 eg! requests [3:0] $end + $var wire 1 [h" reset $end + $scope module genblk2 $end + $var wire 4 =Y grant_onehot_r [3:0] $end + $scope module priority_encoder $end + $var wire 32 on" N [31:0] $end + $var wire 4 eg! data_in [3:0] $end + $var wire 2 _N data_out [1:0] $end + $var wire 32 EY i [31:0] $end + $var wire 1 WN valid_out $end + $upscope $end + $upscope $end + $upscope $end + $upscope $end + $scope module cwb_queue $end + $var wire 32 wn" BUFFERED_OUTPUT [31:0] $end + $var wire 32 ;p" DATAW [31:0] $end + $var wire 32 on" SIZE [31:0] $end + $var wire 1 Sh" clk $end + $var wire 76 3` data_in [75:0] $end + $var wire 76 K` data_out [75:0] $end + $var wire 1 U[! empty $end + $var wire 1 ][! full $end + $var wire 1 _* pop $end + $var wire 1 MU push $end + $var wire 1 u% reading $end + $var wire 1 [h" reset $end + $var wire 3 cv! size [2:0] $end + $var wire 3 cv! size_r [2:0] $end + $var wire 1 c` writing $end + $scope module genblk3 $end + $var wire 76 kv! data(0) [75:0] $end + $var wire 76 nv! data(1) [75:0] $end + $var wire 76 qv! data(2) [75:0] $end + $var wire 76 tv! data(3) [75:0] $end + $scope module genblk2 $end + $var wire 1 Wx! bypass_r $end + $var wire 76 'x! curr_r [75:0] $end + $var wire 1 U[! empty_r $end + $var wire 1 ][! full_r $end + $var wire 76 mw! head_r [75:0] $end + $var wire 2 Ox! rd_ptr_next_r [1:0] $end + $var wire 2 Gx! rd_ptr_r [1:0] $end + $var wire 2 ?x! wr_ptr_r [1:0] $end + $upscope $end + $upscope $end + $upscope $end + $scope module dfp_queue $end + $var wire 32 wn" BUFFERED_OUTPUT [31:0] $end + $var wire 32 qo" DATAW [31:0] $end + $var wire 32 gn" SIZE [31:0] $end + $var wire 1 Sh" clk $end + $var wire 154 K$ data_in [153:0] $end + $var wire 154 OV data_out [153:0] $end + $var wire 1 uW! empty $end + $var wire 1 }W! full $end + $var wire 1 uM pop $end + $var wire 1 um" push $end + $var wire 1 wV reading $end + $var wire 1 [h" reset $end + $var wire 5 ]_! size [4:0] $end + $var wire 5 ]_! size_r [4:0] $end + $var wire 1 s$ writing $end + $scope module genblk3 $end + $var wire 154 e_! data(0) [153:0] $end + $var wire 154 j_! data(1) [153:0] $end + $var wire 154 9`! data(10) [153:0] $end + $var wire 154 >`! data(11) [153:0] $end + $var wire 154 C`! data(12) [153:0] $end + $var wire 154 H`! data(13) [153:0] $end + $var wire 154 M`! data(14) [153:0] $end + $var wire 154 R`! data(15) [153:0] $end + $var wire 154 o_! data(2) [153:0] $end + $var wire 154 t_! data(3) [153:0] $end + $var wire 154 y_! data(4) [153:0] $end + $var wire 154 ~_! data(5) [153:0] $end + $var wire 154 %`! data(6) [153:0] $end + $var wire 154 *`! data(7) [153:0] $end + $var wire 154 /`! data(8) [153:0] $end + $var wire 154 4`! data(9) [153:0] $end + $scope module genblk2 $end + $var wire 1 ]g! bypass_r $end + $var wire 154 {f! curr_r [153:0] $end + $var wire 1 uW! empty_r $end + $var wire 1 }W! full_r $end + $var wire 154 Sf! head_r [153:0] $end + $var wire 4 Ug! rd_ptr_next_r [3:0] $end + $var wire 4 Mg! rd_ptr_r [3:0] $end + $var wire 4 Eg! wr_ptr_r [3:0] $end + $upscope $end + $upscope $end + $upscope $end + $scope module dwb_queue $end + $var wire 32 wn" BUFFERED_OUTPUT [31:0] $end + $var wire 32 Cp" DATAW [31:0] $end + $var wire 32 on" SIZE [31:0] $end + $var wire 1 Sh" clk $end + $var wire 200 k` data_in [199:0] $end + $var wire 200 Ea data_out [199:0] $end + $var wire 1 e[! empty $end + $var wire 1 m[! full $end + $var wire 1 g* pop $end + $var wire 1 eU push $end + $var wire 1 }% reading $end + $var wire 1 [h" reset $end + $var wire 3 _x! size [2:0] $end + $var wire 3 _x! size_r [2:0] $end + $var wire 1 }a writing $end + $scope module genblk3 $end + $var wire 200 gx! data(0) [199:0] $end + $var wire 200 nx! data(1) [199:0] $end + $var wire 200 ux! data(2) [199:0] $end + $var wire 200 |x! data(3) [199:0] $end + $scope module genblk2 $end + $var wire 1 W|! bypass_r $end + $var wire 200 e{! curr_r [199:0] $end + $var wire 1 e[! empty_r $end + $var wire 1 m[! full_r $end + $var wire 200 -{! head_r [199:0] $end + $var wire 2 O|! rd_ptr_next_r [1:0] $end + $var wire 2 G|! rd_ptr_r [1:0] $end + $var wire 2 ?|! wr_ptr_r [1:0] $end + $upscope $end + $upscope $end + $upscope $end + $scope module s0_1_c0 $end + $var wire 32 #p" N [31:0] $end + $var wire 32 Wn" PASSTHRU [31:0] $end + $var wire 1 Sh" clk $end + $var wire 1 Io" flush $end + $var wire 243 MY in [242:0] $end + $var wire 243 Cn! out [242:0] $end + $var wire 1 [h" reset $end + $var wire 1 #P stall $end + $var wire 243 Cn! value [242:0] $end + $upscope $end + $scope module snp_req_queue $end + $var wire 32 wn" BUFFERED_OUTPUT [31:0] $end + $var wire 32 io" DATAW [31:0] $end + $var wire 32 gn" SIZE [31:0] $end + $var wire 1 Sh" clk $end + $var wire 55 3$ data_in [54:0] $end + $var wire 55 7V data_out [54:0] $end + $var wire 1 eW! empty $end + $var wire 1 mW! full $end + $var wire 1 UM pop $end + $var wire 1 }m" push $end + $var wire 1 GV reading $end + $var wire 1 [h" reset $end + $var wire 5 /\! size [4:0] $end + $var wire 5 /\! size_r [4:0] $end + $var wire 1 C$ writing $end + $scope module genblk3 $end + $var wire 55 7\! data(0) [54:0] $end + $var wire 55 9\! data(1) [54:0] $end + $var wire 55 K\! data(10) [54:0] $end + $var wire 55 M\! data(11) [54:0] $end + $var wire 55 O\! data(12) [54:0] $end + $var wire 55 Q\! data(13) [54:0] $end + $var wire 55 S\! data(14) [54:0] $end + $var wire 55 U\! data(15) [54:0] $end + $var wire 55 ;\! data(2) [54:0] $end + $var wire 55 =\! data(3) [54:0] $end + $var wire 55 ?\! data(4) [54:0] $end + $var wire 55 A\! data(5) [54:0] $end + $var wire 55 C\! data(6) [54:0] $end + $var wire 55 E\! data(7) [54:0] $end + $var wire 55 G\! data(8) [54:0] $end + $var wire 55 I\! data(9) [54:0] $end + $scope module genblk2 $end + $var wire 1 U_! bypass_r $end + $var wire 55 -_! curr_r [54:0] $end + $var wire 1 eW! empty_r $end + $var wire 1 mW! full_r $end + $var wire 55 {^! head_r [54:0] $end + $var wire 4 M_! rd_ptr_next_r [3:0] $end + $var wire 4 E_! rd_ptr_r [3:0] $end + $var wire 4 =_! wr_ptr_r [3:0] $end + $upscope $end + $upscope $end + $upscope $end + $scope module st_1e_2 $end + $var wire 32 3p" N [31:0] $end + $var wire 32 Wn" PASSTHRU [31:0] $end + $var wire 1 Sh" clk $end + $var wire 1 Io" flush $end + $var wire 316 W^ in [315:0] $end + $var wire 316 'p! out [315:0] $end + $var wire 1 [h" reset $end + $var wire 1 #P stall $end + $var wire 316 'p! value [315:0] $end + $upscope $end + $scope module tag_data_access $end + $var wire 32 gn" BANK_LINE_SIZE [31:0] $end + $var wire 32 _n" CACHE_SIZE [31:0] $end + $var wire 32 wn" DRAM_ENABLE [31:0] $end + $var wire 32 on" NUM_BANKS [31:0] $end + $var wire 32 wn" STAGE_1_CYCLES [31:0] $end + $var wire 32 on" WORD_SIZE [31:0] $end + $var wire 32 wn" WRITE_ENABLE [31:0] $end + $var wire 1 Sh" clk $end + $var wire 128 K\ data_write [127:0] $end + $var wire 1 IS dirty_st1e $end + $var wire 16 QS dirtyb_st1e [15:0] $end + $var wire 1 #T fill_saw_dirty_st1e $end + $var wire 1 AS fill_sent $end + $var wire 1 U] force_core_miss $end + $var wire 1 QO force_request_miss_st1e $end + $var wire 1 k\ invalidate_line $end + $var wire 1 +T is_snp_st1e $end + $var wire 4 yS mem_byteen_st1e [3:0] $end + $var wire 1 qS mem_rw_st1e $end + $var wire 1 AS miss_st1e $end + $var wire 1 CT mrvq_init_ready_state_st1e $end + $var wire 128 q[ qual_read_data_st1 [127:0] $end + $var wire 1 Y[ qual_read_dirty_st1 $end + $var wire 16 a[ qual_read_dirtyb_st1 [15:0] $end + $var wire 20 i[ qual_read_tag_st1 [19:0] $end + $var wire 1 Q[ qual_read_valid_st1 $end + $var wire 128 1[ read_data_st1c(0) [127:0] $end + $var wire 1 wZ read_dirty_st1c(0) $end + $var wire 16 ![ read_dirtyb_st1c(0) [15:0] $end + $var wire 20 )[ read_tag_st1c(0) [19:0] $end + $var wire 1 oZ read_valid_st1c(0) $end + $var wire 6 /Z readaddr_st10 [5:0] $end + $var wire 128 wR readdata_st1e [127:0] $end + $var wire 20 9S readtag_st1e [19:0] $end + $var wire 32 oR readword_st1e [31:0] $end + $var wire 1 M] real_miss $end + $var wire 1 {\ real_writefill $end + $var wire 1 =] req_invalid $end + $var wire 1 E] req_miss $end + $var wire 1 [h" reset $end + $var wire 1 5] should_write $end + $var wire 1 k\ snoop_hit_no_pending $end + $var wire 1 3T snp_invalidate_st1e $end + $var wire 1 ;T snp_to_mrvq_st1e $end + $var wire 1 #P stall $end + $var wire 1 #P stall_bank_pipe $end + $var wire 1 s\ tags_match $end + $var wire 128 wR use_read_data_st1e [127:0] $end + $var wire 1 ;\ use_read_dirty_st1e $end + $var wire 16 QS use_read_dirtyb_st1e [15:0] $end + $var wire 20 9S use_read_tag_st1e [19:0] $end + $var wire 1 3\ use_read_valid_st1e $end + $var wire 128 K\ use_write_data [127:0] $end + $var wire 16 C\ use_write_enable [15:0] $end + $var wire 1 ST valid_req_st1e $end + $var wire 16 -] we [15:0] $end + $var wire 2 gZ wordsel_st1e [1:0] $end + $var wire 26 kT writeaddr_st1e [25:0] $end + $var wire 128 GZ writedata_st1e [127:0] $end + $var wire 1 7Z writefill_st1e $end + $var wire 6 /Z writeladdr_st1e [5:0] $end + $var wire 20 %] writetag_st1e [19:0] $end + $var wire 32 ?Z writeword_st1e [31:0] $end + $scope module genblk4(0) $end + $var wire 1 ]] normal_write $end + $upscope $end + $scope module genblk4(1) $end + $var wire 1 e] normal_write $end + $upscope $end + $scope module genblk4(2) $end + $var wire 1 m] normal_write $end + $upscope $end + $scope module genblk4(3) $end + $var wire 1 u] normal_write $end + $upscope $end + $scope module s0_1_c0 $end + $var wire 32 +p" N [31:0] $end + $var wire 32 wn" PASSTHRU [31:0] $end + $var wire 1 Sh" clk $end + $var wire 1 Io" flush $end + $var wire 166 '^ in [165:0] $end + $var wire 166 '^ out [165:0] $end + $var wire 1 [h" reset $end + $var wire 1 #P stall $end + $var wire 166 Uo! value [165:0] $end + $upscope $end + $scope module tag_data_structure $end + $var wire 32 gn" BANK_LINE_SIZE [31:0] $end + $var wire 32 _n" CACHE_SIZE [31:0] $end + $var wire 32 on" NUM_BANKS [31:0] $end + $var wire 32 on" WORD_SIZE [31:0] $end + $var wire 1 Sh" clk $end + $var wire 64 %o! dirty [63:0] $end + $var wire 1 }] do_write $end + $var wire 1 AS fill_sent $end + $var wire 32 Eo! i [31:0] $end + $var wire 1 k\ invalidate $end + $var wire 32 Mo! j [31:0] $end + $var wire 6 /Z read_addr [5:0] $end + $var wire 128 q[ read_data [127:0] $end + $var wire 1 Y[ read_dirty $end + $var wire 16 a[ read_dirtyb [15:0] $end + $var wire 20 i[ read_tag [19:0] $end + $var wire 1 Q[ read_valid $end + $var wire 1 [h" reset $end + $var wire 1 #P stall_bank_pipe $end + $var wire 20 %] tag_index [19:0] $end + $var wire 64 5o! valid [63:0] $end + $var wire 6 /Z write_addr [5:0] $end + $var wire 128 K\ write_data [127:0] $end + $var wire 16 C\ write_enable [15:0] $end + $var wire 1 {\ write_fill $end + $upscope $end + $upscope $end + $upscope $end + $upscope $end + $scope module genblk5(2) $end + $var wire 120 {h" curr_bank_core_req_addr [119:0] $end + $var wire 16 sh" curr_bank_core_req_byteen [15:0] $end + $var wire 128 =i" curr_bank_core_req_data [127:0] $end + $var wire 1 C.! curr_bank_core_req_ready $end + $var wire 4 kh" curr_bank_core_req_rw [3:0] $end + $var wire 42 ]i" curr_bank_core_req_tag [41:0] $end + $var wire 4 %! curr_bank_core_req_valid [3:0] $end + $var wire 32 /2 curr_bank_core_rsp_data [31:0] $end + $var wire 1 -! curr_bank_core_rsp_ready $end + $var wire 42 72 curr_bank_core_rsp_tag [41:0] $end + $var wire 2 '2 curr_bank_core_rsp_tid [1:0] $end + $var wire 1 #.! curr_bank_core_rsp_valid $end + $var wire 26 3.! curr_bank_dram_fill_req_addr [25:0] $end + $var wire 1 )-! curr_bank_dram_fill_req_ready $end + $var wire 1 G2 curr_bank_dram_fill_req_valid $end + $var wire 26 ]m" curr_bank_dram_fill_rsp_addr [25:0] $end + $var wire 128 Qk" curr_bank_dram_fill_rsp_data [127:0] $end + $var wire 1 +.! curr_bank_dram_fill_rsp_ready $end + $var wire 1 'n" curr_bank_dram_fill_rsp_valid $end + $var wire 26 _2 curr_bank_dram_wb_req_addr [25:0] $end + $var wire 16 W2 curr_bank_dram_wb_req_byteen [15:0] $end + $var wire 128 g2 curr_bank_dram_wb_req_data [127:0] $end + $var wire 1 5! curr_bank_dram_wb_req_ready $end + $var wire 1 O2 curr_bank_dram_wb_req_valid $end + $var wire 26 mm" curr_bank_snp_req_addr [25:0] $end + $var wire 1 3l" curr_bank_snp_req_invalidate $end + $var wire 1 ;.! curr_bank_snp_req_ready $end + $var wire 28 ;l" curr_bank_snp_req_tag [27:0] $end + $var wire 1 /n" curr_bank_snp_req_valid $end + $var wire 1 =! curr_bank_snp_rsp_ready $end + $var wire 28 13 curr_bank_snp_rsp_tag [27:0] $end + $var wire 1 )3 curr_bank_snp_rsp_valid $end + $scope module bank $end + $var wire 32 Kp" BANK_ID [31:0] $end + $var wire 32 gn" BANK_LINE_SIZE [31:0] $end + $var wire 32 Wn" CACHE_ID [31:0] $end + $var wire 32 _n" CACHE_SIZE [31:0] $end + $var wire 32 )o" CORE_TAG_ID_BITS [31:0] $end + $var wire 32 !o" CORE_TAG_WIDTH [31:0] $end + $var wire 32 on" CREQ_SIZE [31:0] $end + $var wire 32 on" CWBQ_SIZE [31:0] $end + $var wire 32 gn" DFPQ_SIZE [31:0] $end + $var wire 32 on" DFQQ_SIZE [31:0] $end + $var wire 32 wn" DRAM_ENABLE [31:0] $end + $var wire 32 on" DWBQ_SIZE [31:0] $end + $var wire 32 gn" MRVQ_SIZE [31:0] $end + $var wire 32 on" NUM_BANKS [31:0] $end + $var wire 32 on" NUM_REQUESTS [31:0] $end + $var wire 32 Wn" SNOOP_FORWARDING [31:0] $end + $var wire 32 1o" SNP_REQ_TAG_WIDTH [31:0] $end + $var wire 32 gn" SNRQ_SIZE [31:0] $end + $var wire 32 wn" STAGE_1_CYCLES [31:0] $end + $var wire 32 on" WORD_SIZE [31:0] $end + $var wire 32 wn" WRITE_ENABLE [31:0] $end + $var wire 26 ?f addr_st1(0) [25:0] $end + $var wire 26 =i addr_st1e [25:0] $end + $var wire 26 3.! addr_st2 [25:0] $end + $var wire 1 Sh" clk $end + $var wire 120 {h" core_req_addr [119:0] $end + $var wire 16 sh" core_req_byteen [15:0] $end + $var wire 128 =i" core_req_data [127:0] $end + $var wire 1 C.! core_req_ready $end + $var wire 4 kh" core_req_rw [3:0] $end + $var wire 42 ]i" core_req_tag [41:0] $end + $var wire 4 %! core_req_valid [3:0] $end + $var wire 32 /2 core_rsp_data [31:0] $end + $var wire 1 -! core_rsp_ready $end + $var wire 42 72 core_rsp_tag [41:0] $end + $var wire 2 '2 core_rsp_tid [1:0] $end + $var wire 1 #.! core_rsp_valid $end + $var wire 32 {~! cwbq_data [31:0] $end + $var wire 1 O"" cwbq_empty $end + $var wire 1 W"" cwbq_full $end + $var wire 1 !+ cwbq_pop $end + $var wire 1 }i cwbq_push $end + $var wire 1 ;d cwbq_push_stall $end + $var wire 1 'j cwbq_push_unqual $end + $var wire 42 ;~! cwbq_tag [41:0] $end + $var wire 2 3~! cwbq_tid [1:0] $end + $var wire 26 Ob dfpq_addr_st0 [25:0] $end + $var wire 1 o|! dfpq_empty $end + $var wire 128 Wb dfpq_filldata_st0 [127:0] $end + $var wire 1 w|! dfpq_full $end + $var wire 1 Gb dfpq_pop $end + $var wire 1 sd dfpq_pop_unqual $end + $var wire 1 yg dirty_st1e $end + $var wire 1 M!" dirty_st2 $end + $var wire 16 #h dirtyb_st1e [15:0] $end + $var wire 16 U!" dirtyb_st2 [15:0] $end + $var wire 26 3.! dram_fill_req_addr [25:0] $end + $var wire 1 ei dram_fill_req_fast $end + $var wire 1 )-! dram_fill_req_ready $end + $var wire 1 Kd dram_fill_req_stall $end + $var wire 1 /j dram_fill_req_unqual $end + $var wire 1 G2 dram_fill_req_valid $end + $var wire 26 ]m" dram_fill_rsp_addr [25:0] $end + $var wire 128 Qk" dram_fill_rsp_data [127:0] $end + $var wire 1 +.! dram_fill_rsp_ready $end + $var wire 1 'n" dram_fill_rsp_valid $end + $var wire 26 _2 dram_wb_req_addr [25:0] $end + $var wire 16 W2 dram_wb_req_byteen [15:0] $end + $var wire 128 g2 dram_wb_req_data [127:0] $end + $var wire 1 '& dram_wb_req_fire $end + $var wire 1 5! dram_wb_req_ready $end + $var wire 1 O2 dram_wb_req_valid $end + $var wire 1 !#" dwbq_dual_valid_sel $end + $var wire 1 _"" dwbq_empty $end + $var wire 1 g"" dwbq_full $end + $var wire 1 ?j dwbq_is_dwb_in $end + $var wire 1 Oj dwbq_is_dwb_out $end + $var wire 1 Gj dwbq_is_snp_in $end + $var wire 1 Wj dwbq_is_snp_out $end + $var wire 1 )+ dwbq_pop $end + $var wire 1 7j dwbq_push $end + $var wire 1 Cd dwbq_push_stall $end + $var wire 1 _j dwbq_push_unqual $end + $var wire 26 o"" dwbq_req_addr [25:0] $end + $var wire 1 Sh fill_saw_dirty_st1e $end + $var wire 1 u!" fill_saw_dirty_st2 $end + $var wire 1 #d force_request_miss_st1e $end + $var wire 1 kd going_to_write_st1(0) $end + $var wire 49 Wf inst_meta_st1(0) [48:0] $end + $var wire 49 ]!" inst_meta_st2 [48:0] $end + $var wire 1 [d is_fill_in_pipe $end + $var wire 1 cd is_fill_st1(0) $end + $var wire 1 [~! is_fill_st2 $end + $var wire 1 9g is_mrvq_st1(0) $end + $var wire 1 -i is_mrvq_st1e $end + $var wire 1 -i is_mrvq_st1e_st2 $end + $var wire 1 7"" is_mrvq_st2 $end + $var wire 1 )g is_snp_st1(0) $end + $var wire 1 [h is_snp_st1e $end + $var wire 1 }!" is_snp_st2 $end + $var wire 32 ao" j [31:0] $end + $var wire 4 Kh mem_byteen_st1e [3:0] $end + $var wire 1 Ch mem_rw_st1e $end + $var wire 1 mi miss_add $end + $var wire 26 3.! miss_add_addr [25:0] $end + $var wire 1 {h miss_add_because_miss $end + $var wire 1 /"" miss_add_because_pending $end + $var wire 4 S~! miss_add_byteen [3:0] $end + $var wire 32 s~! miss_add_data [31:0] $end + $var wire 1 ui miss_add_is_mrvq $end + $var wire 1 }!" miss_add_is_snp $end + $var wire 1 K~! miss_add_rw $end + $var wire 1 '"" miss_add_snp_invalidate $end + $var wire 42 ;~! miss_add_tag [41:0] $end + $var wire 2 3~! miss_add_tid [1:0] $end + $var wire 1 ei miss_add_unqual $end + $var wire 2 k~! miss_add_wsel [1:0] $end + $var wire 1 qg miss_st1e $end + $var wire 1 E!" miss_st2 $end + $var wire 26 Q}! mrvq_addr_st0 [25:0] $end + $var wire 4 y}! mrvq_byteen_st0 [3:0] $end + $var wire 1 9}! mrvq_full $end + $var wire 1 Ui mrvq_init_ready_state_hazard_st0_st1 $end + $var wire 1 ]i mrvq_init_ready_state_hazard_st1e_st1 $end + $var wire 1 sh mrvq_init_ready_state_st1e $end + $var wire 1 Mi mrvq_init_ready_state_st2 $end + $var wire 1 G"" mrvq_init_ready_state_unqual_st2 $end + $var wire 1 #~! mrvq_is_snp_st0 $end + $var wire 1 qc mrvq_pending_hazard_st1e $end + $var wire 1 Yc mrvq_pop $end + $var wire 1 ac mrvq_pop_unqual $end + $var wire 1 3d mrvq_push_stall $end + $var wire 1 5i mrvq_recover_ready_state_st1e $end + $var wire 1 ?"" mrvq_recover_ready_state_st2 $end + $var wire 1 ic mrvq_rw_st0 $end + $var wire 1 +~! mrvq_snp_invalidate_st0 $end + $var wire 1 A}! mrvq_stop $end + $var wire 42 i}! mrvq_tag_st0 [41:0] $end + $var wire 2 I}! mrvq_tid_st0 [1:0] $end + $var wire 1 ac mrvq_valid_st0 $end + $var wire 32 a}! mrvq_writeword_st0 [31:0] $end + $var wire 2 Y}! mrvq_wsel_st0 [1:0] $end + $var wire 26 5e qual_addr_st0 [25:0] $end + $var wire 1 }e qual_going_to_write_st0 $end + $var wire 49 me qual_inst_meta_st0 [48:0] $end + $var wire 1 sd qual_is_fill_st0 $end + $var wire 1 ac qual_is_mrvq_st0 $end + $var wire 1 'f qual_is_snp_st0 $end + $var wire 1 /f qual_snp_invalidate_st0 $end + $var wire 1 -e qual_valid_st0 $end + $var wire 1 Ei qual_valid_st1e_2 $end + $var wire 128 Me qual_writedata_st0 [127:0] $end + $var wire 32 Ee qual_writeword_st0 [31:0] $end + $var wire 2 =e qual_wsel_st0 [1:0] $end + $var wire 128 Ig readdata_st1e [127:0] $end + $var wire 128 %!" readdata_st2 [127:0] $end + $var wire 20 ig readtag_st1e [19:0] $end + $var wire 20 m!" readtag_st2 [19:0] $end + $var wire 32 Ag readword_st1e [31:0] $end + $var wire 32 {~! readword_st2 [31:0] $end + $var wire 1 +d recover_mrvq_state_st2 $end + $var wire 1 !c reqq_empty $end + $var wire 1 !}! reqq_full $end + $var wire 1 wb reqq_pop $end + $var wire 1 {d reqq_pop_unqual $end + $var wire 1 w* reqq_push $end + $var wire 30 Ic reqq_req_addr_st0 [29:0] $end + $var wire 4 Ac reqq_req_byteen_st0 [3:0] $end + $var wire 1 9c reqq_req_rw_st0 $end + $var wire 1 )c reqq_req_st0 $end + $var wire 42 )}! reqq_req_tag_st0 [41:0] $end + $var wire 2 1c reqq_req_tid_st0 [1:0] $end + $var wire 32 Qc reqq_req_writeword_st0 [31:0] $end + $var wire 1 [h" reset $end + $var wire 1 1g snp_invalidate_st1(0) $end + $var wire 1 ch snp_invalidate_st1e $end + $var wire 1 '"" snp_invalidate_st2 $end + $var wire 26 mm" snp_req_addr [25:0] $end + $var wire 1 3l" snp_req_invalidate $end + $var wire 1 ;.! snp_req_ready $end + $var wire 28 ;l" snp_req_tag [27:0] $end + $var wire 1 /n" snp_req_valid $end + $var wire 1 /& snp_rsp_fire $end + $var wire 1 =! snp_rsp_ready $end + $var wire 28 13 snp_rsp_tag [27:0] $end + $var wire 1 )3 snp_rsp_valid $end + $var wire 1 kh snp_to_mrvq_st1e $end + $var wire 1 /"" snp_to_mrvq_st2 $end + $var wire 26 /b snrq_addr_st0 [25:0] $end + $var wire 1 _|! snrq_empty $end + $var wire 1 g|! snrq_full $end + $var wire 1 7b snrq_invalidate_st0 $end + $var wire 1 'b snrq_pop $end + $var wire 1 %e snrq_pop_unqual $end + $var wire 28 ?b snrq_tag_st0 [27:0] $end + $var wire 28 w"" snrq_tag_st2 [27:0] $end + $var wire 1 yc st2_pending_hazard_st1e $end + $var wire 1 Sd stall_bank_pipe $end + $var wire 42 +h tag_st1e [41:0] $end + $var wire 2 ;h tid_st1e [1:0] $end + $var wire 1 7f valid_st1(0) $end + $var wire 1 %i valid_st1e $end + $var wire 1 c~! valid_st2 $end + $var wire 128 gf writedata_st1(0) [127:0] $end + $var wire 32 Of writeword_st1(0) [31:0] $end + $var wire 32 s~! writeword_st2 [31:0] $end + $var wire 2 Gf wsel_st1(0) [1:0] $end + $var wire 2 k~! wsel_st2 [1:0] $end + $scope module cache_miss_resrv $end + $var wire 32 Kp" BANK_ID [31:0] $end + $var wire 32 gn" BANK_LINE_SIZE [31:0] $end + $var wire 32 Wn" CACHE_ID [31:0] $end + $var wire 32 !o" CORE_TAG_WIDTH [31:0] $end + $var wire 32 gn" MRVQ_SIZE [31:0] $end + $var wire 32 on" NUM_BANKS [31:0] $end + $var wire 32 on" NUM_REQUESTS [31:0] $end + $var wire 32 1o" SNP_REQ_TAG_WIDTH [31:0] $end + $var wire 32 on" WORD_SIZE [31:0] $end + $var wire 416 y;" addr_table [415:0] $end + $var wire 1 Sh" clk $end + $var wire 4 5=" dequeue_index [3:0] $end + $var wire 1 ac dequeue_possible $end + $var wire 4 E=" enqueue_index [3:0] $end + $var wire 1 U=" enqueue_possible $end + $var wire 26 =i fill_addr_st1 [25:0] $end + $var wire 4 ==" head_ptr [3:0] $end + $var wire 1 Kt increment_head $end + $var wire 1 gn is_fill_st1 $end + $var wire 1 ui is_mrvq $end + $var wire 16 ys make_ready [15:0] $end + $var wire 16 #t make_ready_push [15:0] $end + $var wire 85 q7" metadata_table(0) [84:0] $end + $var wire 85 t7" metadata_table(1) [84:0] $end + $var wire 85 18" metadata_table(10) [84:0] $end + $var wire 85 48" metadata_table(11) [84:0] $end + $var wire 85 78" metadata_table(12) [84:0] $end + $var wire 85 :8" metadata_table(13) [84:0] $end + $var wire 85 =8" metadata_table(14) [84:0] $end + $var wire 85 @8" metadata_table(15) [84:0] $end + $var wire 85 w7" metadata_table(2) [84:0] $end + $var wire 85 z7" metadata_table(3) [84:0] $end + $var wire 85 }7" metadata_table(4) [84:0] $end + $var wire 85 "8" metadata_table(5) [84:0] $end + $var wire 85 %8" metadata_table(6) [84:0] $end + $var wire 85 (8" metadata_table(7) [84:0] $end + $var wire 85 +8" metadata_table(8) [84:0] $end + $var wire 85 .8" metadata_table(9) [84:0] $end + $var wire 1 mi miss_add $end + $var wire 26 3.! miss_add_addr [25:0] $end + $var wire 4 S~! miss_add_byteen [3:0] $end + $var wire 32 s~! miss_add_data [31:0] $end + $var wire 1 }!" miss_add_is_snp $end + $var wire 1 K~! miss_add_rw $end + $var wire 1 '"" miss_add_snp_invalidate $end + $var wire 42 ;~! miss_add_tag [41:0] $end + $var wire 2 3~! miss_add_tid [1:0] $end + $var wire 2 k~! miss_add_wsel [1:0] $end + $var wire 26 Q}! miss_resrv_addr_st0 [25:0] $end + $var wire 4 y}! miss_resrv_byteen_st0 [3:0] $end + $var wire 32 a}! miss_resrv_data_st0 [31:0] $end + $var wire 1 9}! miss_resrv_full $end + $var wire 1 #~! miss_resrv_is_snp_st0 $end + $var wire 1 Yc miss_resrv_pop $end + $var wire 1 ic miss_resrv_rw_st0 $end + $var wire 1 +~! miss_resrv_snp_invalidate_st0 $end + $var wire 1 A}! miss_resrv_stop $end + $var wire 42 i}! miss_resrv_tag_st0 [41:0] $end + $var wire 2 I}! miss_resrv_tid_st0 [1:0] $end + $var wire 1 ac miss_resrv_valid_st0 $end + $var wire 2 Y}! miss_resrv_wsel_st0 [1:0] $end + $var wire 1 Mi mrvq_init_ready_state $end + $var wire 1 ;t mrvq_pop $end + $var wire 1 3t mrvq_push $end + $var wire 1 qc pending_hazard $end + $var wire 1 [t qual_mrvq_init $end + $var wire 16 -=" ready_table [15:0] $end + $var wire 1 Ct recover_state $end + $var wire 1 [h" reset $end + $var wire 4 5=" schedule_ptr [3:0] $end + $var wire 5 M=" size [4:0] $end + $var wire 4 E=" tail_ptr [3:0] $end + $var wire 1 St update_ready $end + $var wire 16 +t valid_address_match [15:0] $end + $var wire 16 %=" valid_table [15:0] $end + $upscope $end + $scope module core_req_arb $end + $var wire 32 )o" CORE_TAG_ID_BITS [31:0] $end + $var wire 32 !o" CORE_TAG_WIDTH [31:0] $end + $var wire 32 on" CREQ_SIZE [31:0] $end + $var wire 32 on" NUM_REQUESTS [31:0] $end + $var wire 32 on" WORD_SIZE [31:0] $end + $var wire 120 {h" bank_addr [119:0] $end + $var wire 16 sh" bank_byteen [15:0] $end + $var wire 4 kh" bank_rw [3:0] $end + $var wire 42 ]i" bank_tag [41:0] $end + $var wire 4 %! bank_valids [3:0] $end + $var wire 128 =i" bank_writedata [127:0] $end + $var wire 1 Sh" clk $end + $var wire 1 Y/" o_empty $end + $var wire 1 [l out_empty $end + $var wire 120 ik out_per_addr [119:0] $end + $var wire 16 ak out_per_byteen [15:0] $end + $var wire 4 Yk out_per_rw [3:0] $end + $var wire 42 Kl out_per_tag [41:0] $end + $var wire 4 Qk out_per_valids [3:0] $end + $var wire 128 +l out_per_writedata [127:0] $end + $var wire 1 cl pop_qual $end + $var wire 1 1+ push_qual $end + $var wire 120 w." qual_addr [119:0] $end + $var wire 16 o." qual_byteen [15:0] $end + $var wire 1 )c qual_has_request $end + $var wire 2 1c qual_request_index [1:0] $end + $var wire 4 g." qual_rw [3:0] $end + $var wire 42 )}! qual_tag [41:0] $end + $var wire 4 _." qual_valids [3:0] $end + $var wire 128 9/" qual_writedata [127:0] $end + $var wire 4 kl real_out_per_valids [3:0] $end + $var wire 1 !c reqq_empty $end + $var wire 1 !}! reqq_full $end + $var wire 1 wb reqq_pop $end + $var wire 1 w* reqq_push $end + $var wire 30 Ic reqq_req_addr_st0 [29:0] $end + $var wire 4 Ac reqq_req_byteen_st0 [3:0] $end + $var wire 1 9c reqq_req_rw_st0 $end + $var wire 1 )c reqq_req_st0 $end + $var wire 42 )}! reqq_req_tag_st0 [41:0] $end + $var wire 2 1c reqq_req_tid_st0 [1:0] $end + $var wire 32 Qc reqq_req_writedata_st0 [31:0] $end + $var wire 1 [h" reset $end + $var wire 1 a/" use_empty $end + $var wire 120 w." use_per_addr [119:0] $end + $var wire 16 o." use_per_byteen [15:0] $end + $var wire 4 g." use_per_rw [3:0] $end + $var wire 42 )}! use_per_tag [41:0] $end + $var wire 4 _." use_per_valids [3:0] $end + $var wire 128 9/" use_per_writedata [127:0] $end + $scope module reqq_queue $end + $var wire 32 wn" BUFFERED_OUTPUT [31:0] $end + $var wire 32 yo" DATAW [31:0] $end + $var wire 32 on" SIZE [31:0] $end + $var wire 1 Sh" clk $end + $var wire 314 !' data_in [313:0] $end + $var wire 314 sl data_out [313:0] $end + $var wire 1 Y/" empty $end + $var wire 1 !}! full $end + $var wire 1 cl pop $end + $var wire 1 1+ push $end + $var wire 1 em reading $end + $var wire 1 [h" reset $end + $var wire 3 i/" size [2:0] $end + $var wire 3 i/" size_r [2:0] $end + $var wire 1 q' writing $end + $scope module genblk3 $end + $var wire 314 q/" data(0) [313:0] $end + $var wire 314 {/" data(1) [313:0] $end + $var wire 314 '0" data(2) [313:0] $end + $var wire 314 10" data(3) [313:0] $end + $scope module genblk2 $end + $var wire 1 55" bypass_r $end + $var wire 314 +4" curr_r [313:0] $end + $var wire 1 Y/" empty_r $end + $var wire 1 !}! full_r $end + $var wire 314 93" head_r [313:0] $end + $var wire 2 -5" rd_ptr_next_r [1:0] $end + $var wire 2 %5" rd_ptr_r [1:0] $end + $var wire 2 {4" wr_ptr_r [1:0] $end + $upscope $end + $upscope $end + $upscope $end + $scope module sel_bank $end + $var wire 32 on" N [31:0] $end + $var wire 1 Sh" clk $end + $var wire 2 1c grant_index [1:0] $end + $var wire 4 mm grant_onehot [3:0] $end + $var wire 1 )c grant_valid $end + $var wire 4 _." requests [3:0] $end + $var wire 1 [h" reset $end + $scope module genblk2 $end + $var wire 4 mm grant_onehot_r [3:0] $end + $scope module priority_encoder $end + $var wire 32 on" N [31:0] $end + $var wire 4 _." data_in [3:0] $end + $var wire 2 1c data_out [1:0] $end + $var wire 32 um i [31:0] $end + $var wire 1 )c valid_out $end + $upscope $end + $upscope $end + $upscope $end + $upscope $end + $scope module cwb_queue $end + $var wire 32 wn" BUFFERED_OUTPUT [31:0] $end + $var wire 32 ;p" DATAW [31:0] $end + $var wire 32 on" SIZE [31:0] $end + $var wire 1 Sh" clk $end + $var wire 76 ct data_in [75:0] $end + $var wire 76 {t data_out [75:0] $end + $var wire 1 O"" empty $end + $var wire 1 W"" full $end + $var wire 1 !+ pop $end + $var wire 1 }i push $end + $var wire 1 y' reading $end + $var wire 1 [h" reset $end + $var wire 3 ]=" size [2:0] $end + $var wire 3 ]=" size_r [2:0] $end + $var wire 1 5u writing $end + $scope module genblk3 $end + $var wire 76 e=" data(0) [75:0] $end + $var wire 76 h=" data(1) [75:0] $end + $var wire 76 k=" data(2) [75:0] $end + $var wire 76 n=" data(3) [75:0] $end + $scope module genblk2 $end + $var wire 1 Q?" bypass_r $end + $var wire 76 !?" curr_r [75:0] $end + $var wire 1 O"" empty_r $end + $var wire 1 W"" full_r $end + $var wire 76 g>" head_r [75:0] $end + $var wire 2 I?" rd_ptr_next_r [1:0] $end + $var wire 2 A?" rd_ptr_r [1:0] $end + $var wire 2 9?" wr_ptr_r [1:0] $end + $upscope $end + $upscope $end + $upscope $end + $scope module dfp_queue $end + $var wire 32 wn" BUFFERED_OUTPUT [31:0] $end + $var wire 32 qo" DATAW [31:0] $end + $var wire 32 gn" SIZE [31:0] $end + $var wire 1 Sh" clk $end + $var wire 154 O& data_in [153:0] $end + $var wire 154 !k data_out [153:0] $end + $var wire 1 o|! empty $end + $var wire 1 w|! full $end + $var wire 1 Gb pop $end + $var wire 1 'n" push $end + $var wire 1 Ik reading $end + $var wire 1 [h" reset $end + $var wire 5 W&" size [4:0] $end + $var wire 5 W&" size_r [4:0] $end + $var wire 1 w& writing $end + $scope module genblk3 $end + $var wire 154 _&" data(0) [153:0] $end + $var wire 154 d&" data(1) [153:0] $end + $var wire 154 3'" data(10) [153:0] $end + $var wire 154 8'" data(11) [153:0] $end + $var wire 154 ='" data(12) [153:0] $end + $var wire 154 B'" data(13) [153:0] $end + $var wire 154 G'" data(14) [153:0] $end + $var wire 154 L'" data(15) [153:0] $end + $var wire 154 i&" data(2) [153:0] $end + $var wire 154 n&" data(3) [153:0] $end + $var wire 154 s&" data(4) [153:0] $end + $var wire 154 x&" data(5) [153:0] $end + $var wire 154 }&" data(6) [153:0] $end + $var wire 154 $'" data(7) [153:0] $end + $var wire 154 )'" data(8) [153:0] $end + $var wire 154 .'" data(9) [153:0] $end + $scope module genblk2 $end + $var wire 1 W." bypass_r $end + $var wire 154 u-" curr_r [153:0] $end + $var wire 1 o|! empty_r $end + $var wire 1 w|! full_r $end + $var wire 154 M-" head_r [153:0] $end + $var wire 4 O." rd_ptr_next_r [3:0] $end + $var wire 4 G." rd_ptr_r [3:0] $end + $var wire 4 ?." wr_ptr_r [3:0] $end + $upscope $end + $upscope $end + $upscope $end + $scope module dwb_queue $end + $var wire 32 wn" BUFFERED_OUTPUT [31:0] $end + $var wire 32 Cp" DATAW [31:0] $end + $var wire 32 on" SIZE [31:0] $end + $var wire 1 Sh" clk $end + $var wire 200 =u data_in [199:0] $end + $var wire 200 uu data_out [199:0] $end + $var wire 1 _"" empty $end + $var wire 1 g"" full $end + $var wire 1 )+ pop $end + $var wire 1 7j push $end + $var wire 1 #( reading $end + $var wire 1 [h" reset $end + $var wire 3 Y?" size [2:0] $end + $var wire 3 Y?" size_r [2:0] $end + $var wire 1 Ov writing $end + $scope module genblk3 $end + $var wire 200 a?" data(0) [199:0] $end + $var wire 200 h?" data(1) [199:0] $end + $var wire 200 o?" data(2) [199:0] $end + $var wire 200 v?" data(3) [199:0] $end + $scope module genblk2 $end + $var wire 1 QC" bypass_r $end + $var wire 200 _B" curr_r [199:0] $end + $var wire 1 _"" empty_r $end + $var wire 1 g"" full_r $end + $var wire 200 'B" head_r [199:0] $end + $var wire 2 IC" rd_ptr_next_r [1:0] $end + $var wire 2 AC" rd_ptr_r [1:0] $end + $var wire 2 9C" wr_ptr_r [1:0] $end + $upscope $end + $upscope $end + $upscope $end + $scope module s0_1_c0 $end + $var wire 32 #p" N [31:0] $end + $var wire 32 Wn" PASSTHRU [31:0] $end + $var wire 1 Sh" clk $end + $var wire 1 Io" flush $end + $var wire 243 }m in [242:0] $end + $var wire 243 =5" out [242:0] $end + $var wire 1 [h" reset $end + $var wire 1 Sd stall $end + $var wire 243 =5" value [242:0] $end + $upscope $end + $scope module snp_req_queue $end + $var wire 32 wn" BUFFERED_OUTPUT [31:0] $end + $var wire 32 io" DATAW [31:0] $end + $var wire 32 gn" SIZE [31:0] $end + $var wire 1 Sh" clk $end + $var wire 55 7& data_in [54:0] $end + $var wire 55 gj data_out [54:0] $end + $var wire 1 _|! empty $end + $var wire 1 g|! full $end + $var wire 1 'b pop $end + $var wire 1 /n" push $end + $var wire 1 wj reading $end + $var wire 1 [h" reset $end + $var wire 5 )#" size [4:0] $end + $var wire 5 )#" size_r [4:0] $end + $var wire 1 G& writing $end + $scope module genblk3 $end + $var wire 55 1#" data(0) [54:0] $end + $var wire 55 3#" data(1) [54:0] $end + $var wire 55 E#" data(10) [54:0] $end + $var wire 55 G#" data(11) [54:0] $end + $var wire 55 I#" data(12) [54:0] $end + $var wire 55 K#" data(13) [54:0] $end + $var wire 55 M#" data(14) [54:0] $end + $var wire 55 O#" data(15) [54:0] $end + $var wire 55 5#" data(2) [54:0] $end + $var wire 55 7#" data(3) [54:0] $end + $var wire 55 9#" data(4) [54:0] $end + $var wire 55 ;#" data(5) [54:0] $end + $var wire 55 =#" data(6) [54:0] $end + $var wire 55 ?#" data(7) [54:0] $end + $var wire 55 A#" data(8) [54:0] $end + $var wire 55 C#" data(9) [54:0] $end + $scope module genblk2 $end + $var wire 1 O&" bypass_r $end + $var wire 55 '&" curr_r [54:0] $end + $var wire 1 _|! empty_r $end + $var wire 1 g|! full_r $end + $var wire 55 u%" head_r [54:0] $end + $var wire 4 G&" rd_ptr_next_r [3:0] $end + $var wire 4 ?&" rd_ptr_r [3:0] $end + $var wire 4 7&" wr_ptr_r [3:0] $end + $upscope $end + $upscope $end + $upscope $end + $scope module st_1e_2 $end + $var wire 32 3p" N [31:0] $end + $var wire 32 Wn" PASSTHRU [31:0] $end + $var wire 1 Sh" clk $end + $var wire 1 Io" flush $end + $var wire 316 )s in [315:0] $end + $var wire 316 !7" out [315:0] $end + $var wire 1 [h" reset $end + $var wire 1 Sd stall $end + $var wire 316 !7" value [315:0] $end + $upscope $end + $scope module tag_data_access $end + $var wire 32 gn" BANK_LINE_SIZE [31:0] $end + $var wire 32 _n" CACHE_SIZE [31:0] $end + $var wire 32 wn" DRAM_ENABLE [31:0] $end + $var wire 32 on" NUM_BANKS [31:0] $end + $var wire 32 wn" STAGE_1_CYCLES [31:0] $end + $var wire 32 on" WORD_SIZE [31:0] $end + $var wire 32 wn" WRITE_ENABLE [31:0] $end + $var wire 1 Sh" clk $end + $var wire 128 {p data_write [127:0] $end + $var wire 1 yg dirty_st1e $end + $var wire 16 #h dirtyb_st1e [15:0] $end + $var wire 1 Sh fill_saw_dirty_st1e $end + $var wire 1 qg fill_sent $end + $var wire 1 'r force_core_miss $end + $var wire 1 #d force_request_miss_st1e $end + $var wire 1 =q invalidate_line $end + $var wire 1 [h is_snp_st1e $end + $var wire 4 Kh mem_byteen_st1e [3:0] $end + $var wire 1 Ch mem_rw_st1e $end + $var wire 1 qg miss_st1e $end + $var wire 1 sh mrvq_init_ready_state_st1e $end + $var wire 128 Cp qual_read_data_st1 [127:0] $end + $var wire 1 +p qual_read_dirty_st1 $end + $var wire 16 3p qual_read_dirtyb_st1 [15:0] $end + $var wire 20 ;p qual_read_tag_st1 [19:0] $end + $var wire 1 #p qual_read_valid_st1 $end + $var wire 128 ao read_data_st1c(0) [127:0] $end + $var wire 1 Io read_dirty_st1c(0) $end + $var wire 16 Qo read_dirtyb_st1c(0) [15:0] $end + $var wire 20 Yo read_tag_st1c(0) [19:0] $end + $var wire 1 Ao read_valid_st1c(0) $end + $var wire 6 _n readaddr_st10 [5:0] $end + $var wire 128 Ig readdata_st1e [127:0] $end + $var wire 20 ig readtag_st1e [19:0] $end + $var wire 32 Ag readword_st1e [31:0] $end + $var wire 1 }q real_miss $end + $var wire 1 Mq real_writefill $end + $var wire 1 mq req_invalid $end + $var wire 1 uq req_miss $end + $var wire 1 [h" reset $end + $var wire 1 eq should_write $end + $var wire 1 =q snoop_hit_no_pending $end + $var wire 1 ch snp_invalidate_st1e $end + $var wire 1 kh snp_to_mrvq_st1e $end + $var wire 1 Sd stall $end + $var wire 1 Sd stall_bank_pipe $end + $var wire 1 Eq tags_match $end + $var wire 128 Ig use_read_data_st1e [127:0] $end + $var wire 1 kp use_read_dirty_st1e $end + $var wire 16 #h use_read_dirtyb_st1e [15:0] $end + $var wire 20 ig use_read_tag_st1e [19:0] $end + $var wire 1 cp use_read_valid_st1e $end + $var wire 128 {p use_write_data [127:0] $end + $var wire 16 sp use_write_enable [15:0] $end + $var wire 1 %i valid_req_st1e $end + $var wire 16 ]q we [15:0] $end + $var wire 2 9o wordsel_st1e [1:0] $end + $var wire 26 =i writeaddr_st1e [25:0] $end + $var wire 128 wn writedata_st1e [127:0] $end + $var wire 1 gn writefill_st1e $end + $var wire 6 _n writeladdr_st1e [5:0] $end + $var wire 20 Uq writetag_st1e [19:0] $end + $var wire 32 on writeword_st1e [31:0] $end + $scope module genblk4(0) $end + $var wire 1 /r normal_write $end + $upscope $end + $scope module genblk4(1) $end + $var wire 1 7r normal_write $end + $upscope $end + $scope module genblk4(2) $end + $var wire 1 ?r normal_write $end + $upscope $end + $scope module genblk4(3) $end + $var wire 1 Gr normal_write $end + $upscope $end + $scope module s0_1_c0 $end + $var wire 32 +p" N [31:0] $end + $var wire 32 wn" PASSTHRU [31:0] $end + $var wire 1 Sh" clk $end + $var wire 1 Io" flush $end + $var wire 166 Wr in [165:0] $end + $var wire 166 Wr out [165:0] $end + $var wire 1 [h" reset $end + $var wire 1 Sd stall $end + $var wire 166 O6" value [165:0] $end + $upscope $end + $scope module tag_data_structure $end + $var wire 32 gn" BANK_LINE_SIZE [31:0] $end + $var wire 32 _n" CACHE_SIZE [31:0] $end + $var wire 32 on" NUM_BANKS [31:0] $end + $var wire 32 on" WORD_SIZE [31:0] $end + $var wire 1 Sh" clk $end + $var wire 64 }5" dirty [63:0] $end + $var wire 1 Or do_write $end + $var wire 1 qg fill_sent $end + $var wire 32 ?6" i [31:0] $end + $var wire 1 =q invalidate $end + $var wire 32 G6" j [31:0] $end + $var wire 6 _n read_addr [5:0] $end + $var wire 128 Cp read_data [127:0] $end + $var wire 1 +p read_dirty $end + $var wire 16 3p read_dirtyb [15:0] $end + $var wire 20 ;p read_tag [19:0] $end + $var wire 1 #p read_valid $end + $var wire 1 [h" reset $end + $var wire 1 Sd stall_bank_pipe $end + $var wire 20 Uq tag_index [19:0] $end + $var wire 64 /6" valid [63:0] $end + $var wire 6 _n write_addr [5:0] $end + $var wire 128 {p write_data [127:0] $end + $var wire 16 sp write_enable [15:0] $end + $var wire 1 Mq write_fill $end + $upscope $end + $upscope $end + $upscope $end + $upscope $end + $scope module genblk5(3) $end + $var wire 120 {h" curr_bank_core_req_addr [119:0] $end + $var wire 16 sh" curr_bank_core_req_byteen [15:0] $end + $var wire 128 =i" curr_bank_core_req_data [127:0] $end + $var wire 1 k.! curr_bank_core_req_ready $end + $var wire 4 kh" curr_bank_core_req_rw [3:0] $end + $var wire 42 ]i" curr_bank_core_req_tag [41:0] $end + $var wire 4 E! curr_bank_core_req_valid [3:0] $end + $var wire 32 A3 curr_bank_core_rsp_data [31:0] $end + $var wire 1 M! curr_bank_core_rsp_ready $end + $var wire 42 I3 curr_bank_core_rsp_tag [41:0] $end + $var wire 2 93 curr_bank_core_rsp_tid [1:0] $end + $var wire 1 K.! curr_bank_core_rsp_valid $end + $var wire 26 [.! curr_bank_dram_fill_req_addr [25:0] $end + $var wire 1 )-! curr_bank_dram_fill_req_ready $end + $var wire 1 Y3 curr_bank_dram_fill_req_valid $end + $var wire 26 ]m" curr_bank_dram_fill_rsp_addr [25:0] $end + $var wire 128 Qk" curr_bank_dram_fill_rsp_data [127:0] $end + $var wire 1 S.! curr_bank_dram_fill_rsp_ready $end + $var wire 1 7n" curr_bank_dram_fill_rsp_valid $end + $var wire 26 q3 curr_bank_dram_wb_req_addr [25:0] $end + $var wire 16 i3 curr_bank_dram_wb_req_byteen [15:0] $end + $var wire 128 y3 curr_bank_dram_wb_req_data [127:0] $end + $var wire 1 U! curr_bank_dram_wb_req_ready $end + $var wire 1 a3 curr_bank_dram_wb_req_valid $end + $var wire 26 mm" curr_bank_snp_req_addr [25:0] $end + $var wire 1 3l" curr_bank_snp_req_invalidate $end + $var wire 1 c.! curr_bank_snp_req_ready $end + $var wire 28 ;l" curr_bank_snp_req_tag [27:0] $end + $var wire 1 ?n" curr_bank_snp_req_valid $end + $var wire 1 ]! curr_bank_snp_rsp_ready $end + $var wire 28 C4 curr_bank_snp_rsp_tag [27:0] $end + $var wire 1 ;4 curr_bank_snp_rsp_valid $end + $scope module bank $end + $var wire 32 Sp" BANK_ID [31:0] $end + $var wire 32 gn" BANK_LINE_SIZE [31:0] $end + $var wire 32 Wn" CACHE_ID [31:0] $end + $var wire 32 _n" CACHE_SIZE [31:0] $end + $var wire 32 )o" CORE_TAG_ID_BITS [31:0] $end + $var wire 32 !o" CORE_TAG_WIDTH [31:0] $end + $var wire 32 on" CREQ_SIZE [31:0] $end + $var wire 32 on" CWBQ_SIZE [31:0] $end + $var wire 32 gn" DFPQ_SIZE [31:0] $end + $var wire 32 on" DFQQ_SIZE [31:0] $end + $var wire 32 wn" DRAM_ENABLE [31:0] $end + $var wire 32 on" DWBQ_SIZE [31:0] $end + $var wire 32 gn" MRVQ_SIZE [31:0] $end + $var wire 32 on" NUM_BANKS [31:0] $end + $var wire 32 on" NUM_REQUESTS [31:0] $end + $var wire 32 Wn" SNOOP_FORWARDING [31:0] $end + $var wire 32 1o" SNP_REQ_TAG_WIDTH [31:0] $end + $var wire 32 gn" SNRQ_SIZE [31:0] $end + $var wire 32 wn" STAGE_1_CYCLES [31:0] $end + $var wire 32 on" WORD_SIZE [31:0] $end + $var wire 32 wn" WRITE_ENABLE [31:0] $end + $var wire 26 oz addr_st1(0) [25:0] $end + $var wire 26 m} addr_st1e [25:0] $end + $var wire 26 [.! addr_st2 [25:0] $end + $var wire 1 Sh" clk $end + $var wire 120 {h" core_req_addr [119:0] $end + $var wire 16 sh" core_req_byteen [15:0] $end + $var wire 128 =i" core_req_data [127:0] $end + $var wire 1 k.! core_req_ready $end + $var wire 4 kh" core_req_rw [3:0] $end + $var wire 42 ]i" core_req_tag [41:0] $end + $var wire 4 E! core_req_valid [3:0] $end + $var wire 32 A3 core_rsp_data [31:0] $end + $var wire 1 M! core_rsp_ready $end + $var wire 42 I3 core_rsp_tag [41:0] $end + $var wire 2 93 core_rsp_tid [1:0] $end + $var wire 1 K.! core_rsp_valid $end + $var wire 32 uE" cwbq_data [31:0] $end + $var wire 1 IG" cwbq_empty $end + $var wire 1 QG" cwbq_full $end + $var wire 1 A+ cwbq_pop $end + $var wire 1 O~ cwbq_push $end + $var wire 1 kx cwbq_push_stall $end + $var wire 1 W~ cwbq_push_unqual $end + $var wire 42 5E" cwbq_tag [41:0] $end + $var wire 2 -E" cwbq_tid [1:0] $end + $var wire 26 !w dfpq_addr_st0 [25:0] $end + $var wire 1 iC" dfpq_empty $end + $var wire 128 )w dfpq_filldata_st0 [127:0] $end + $var wire 1 qC" dfpq_full $end + $var wire 1 wv dfpq_pop $end + $var wire 1 Ey dfpq_pop_unqual $end + $var wire 1 K| dirty_st1e $end + $var wire 1 GF" dirty_st2 $end + $var wire 16 S| dirtyb_st1e [15:0] $end + $var wire 16 OF" dirtyb_st2 [15:0] $end + $var wire 26 [.! dram_fill_req_addr [25:0] $end + $var wire 1 7~ dram_fill_req_fast $end + $var wire 1 )-! dram_fill_req_ready $end + $var wire 1 {x dram_fill_req_stall $end + $var wire 1 _~ dram_fill_req_unqual $end + $var wire 1 Y3 dram_fill_req_valid $end + $var wire 26 ]m" dram_fill_rsp_addr [25:0] $end + $var wire 128 Qk" dram_fill_rsp_data [127:0] $end + $var wire 1 S.! dram_fill_rsp_ready $end + $var wire 1 7n" dram_fill_rsp_valid $end + $var wire 26 q3 dram_wb_req_addr [25:0] $end + $var wire 16 i3 dram_wb_req_byteen [15:0] $end + $var wire 128 y3 dram_wb_req_data [127:0] $end + $var wire 1 +( dram_wb_req_fire $end + $var wire 1 U! dram_wb_req_ready $end + $var wire 1 a3 dram_wb_req_valid $end + $var wire 1 yG" dwbq_dual_valid_sel $end + $var wire 1 YG" dwbq_empty $end + $var wire 1 aG" dwbq_full $end + $var wire 1 o~ dwbq_is_dwb_in $end + $var wire 1 !!! dwbq_is_dwb_out $end + $var wire 1 w~ dwbq_is_snp_in $end + $var wire 1 )!! dwbq_is_snp_out $end + $var wire 1 I+ dwbq_pop $end + $var wire 1 g~ dwbq_push $end + $var wire 1 sx dwbq_push_stall $end + $var wire 1 1!! dwbq_push_unqual $end + $var wire 26 iG" dwbq_req_addr [25:0] $end + $var wire 1 %} fill_saw_dirty_st1e $end + $var wire 1 oF" fill_saw_dirty_st2 $end + $var wire 1 Sx force_request_miss_st1e $end + $var wire 1 =y going_to_write_st1(0) $end + $var wire 49 ){ inst_meta_st1(0) [48:0] $end + $var wire 49 WF" inst_meta_st2 [48:0] $end + $var wire 1 -y is_fill_in_pipe $end + $var wire 1 5y is_fill_st1(0) $end + $var wire 1 UE" is_fill_st2 $end + $var wire 1 i{ is_mrvq_st1(0) $end + $var wire 1 ]} is_mrvq_st1e $end + $var wire 1 ]} is_mrvq_st1e_st2 $end + $var wire 1 1G" is_mrvq_st2 $end + $var wire 1 Y{ is_snp_st1(0) $end + $var wire 1 -} is_snp_st1e $end + $var wire 1 wF" is_snp_st2 $end + $var wire 32 ao" j [31:0] $end + $var wire 4 {| mem_byteen_st1e [3:0] $end + $var wire 1 s| mem_rw_st1e $end + $var wire 1 ?~ miss_add $end + $var wire 26 [.! miss_add_addr [25:0] $end + $var wire 1 M} miss_add_because_miss $end + $var wire 1 )G" miss_add_because_pending $end + $var wire 4 ME" miss_add_byteen [3:0] $end + $var wire 32 mE" miss_add_data [31:0] $end + $var wire 1 G~ miss_add_is_mrvq $end + $var wire 1 wF" miss_add_is_snp $end + $var wire 1 EE" miss_add_rw $end + $var wire 1 !G" miss_add_snp_invalidate $end + $var wire 42 5E" miss_add_tag [41:0] $end + $var wire 2 -E" miss_add_tid [1:0] $end + $var wire 1 7~ miss_add_unqual $end + $var wire 2 eE" miss_add_wsel [1:0] $end + $var wire 1 C| miss_st1e $end + $var wire 1 ?F" miss_st2 $end + $var wire 26 KD" mrvq_addr_st0 [25:0] $end + $var wire 4 sD" mrvq_byteen_st0 [3:0] $end + $var wire 1 3D" mrvq_full $end + $var wire 1 '~ mrvq_init_ready_state_hazard_st0_st1 $end + $var wire 1 /~ mrvq_init_ready_state_hazard_st1e_st1 $end + $var wire 1 E} mrvq_init_ready_state_st1e $end + $var wire 1 }} mrvq_init_ready_state_st2 $end + $var wire 1 AG" mrvq_init_ready_state_unqual_st2 $end + $var wire 1 {D" mrvq_is_snp_st0 $end + $var wire 1 Cx mrvq_pending_hazard_st1e $end + $var wire 1 +x mrvq_pop $end + $var wire 1 3x mrvq_pop_unqual $end + $var wire 1 cx mrvq_push_stall $end + $var wire 1 e} mrvq_recover_ready_state_st1e $end + $var wire 1 9G" mrvq_recover_ready_state_st2 $end + $var wire 1 ;x mrvq_rw_st0 $end + $var wire 1 %E" mrvq_snp_invalidate_st0 $end + $var wire 1 ;D" mrvq_stop $end + $var wire 42 cD" mrvq_tag_st0 [41:0] $end + $var wire 2 CD" mrvq_tid_st0 [1:0] $end + $var wire 1 3x mrvq_valid_st0 $end + $var wire 32 [D" mrvq_writeword_st0 [31:0] $end + $var wire 2 SD" mrvq_wsel_st0 [1:0] $end + $var wire 26 ey qual_addr_st0 [25:0] $end + $var wire 1 Oz qual_going_to_write_st0 $end + $var wire 49 ?z qual_inst_meta_st0 [48:0] $end + $var wire 1 Ey qual_is_fill_st0 $end + $var wire 1 3x qual_is_mrvq_st0 $end + $var wire 1 Wz qual_is_snp_st0 $end + $var wire 1 _z qual_snp_invalidate_st0 $end + $var wire 1 ]y qual_valid_st0 $end + $var wire 1 u} qual_valid_st1e_2 $end + $var wire 128 }y qual_writedata_st0 [127:0] $end + $var wire 32 uy qual_writeword_st0 [31:0] $end + $var wire 2 my qual_wsel_st0 [1:0] $end + $var wire 128 y{ readdata_st1e [127:0] $end + $var wire 128 }E" readdata_st2 [127:0] $end + $var wire 20 ;| readtag_st1e [19:0] $end + $var wire 20 gF" readtag_st2 [19:0] $end + $var wire 32 q{ readword_st1e [31:0] $end + $var wire 32 uE" readword_st2 [31:0] $end + $var wire 1 [x recover_mrvq_state_st2 $end + $var wire 1 Qw reqq_empty $end + $var wire 1 yC" reqq_full $end + $var wire 1 Iw reqq_pop $end + $var wire 1 My reqq_pop_unqual $end + $var wire 1 9+ reqq_push $end + $var wire 30 yw reqq_req_addr_st0 [29:0] $end + $var wire 4 qw reqq_req_byteen_st0 [3:0] $end + $var wire 1 iw reqq_req_rw_st0 $end + $var wire 1 Yw reqq_req_st0 $end + $var wire 42 #D" reqq_req_tag_st0 [41:0] $end + $var wire 2 aw reqq_req_tid_st0 [1:0] $end + $var wire 32 #x reqq_req_writeword_st0 [31:0] $end + $var wire 1 [h" reset $end + $var wire 1 a{ snp_invalidate_st1(0) $end + $var wire 1 5} snp_invalidate_st1e $end + $var wire 1 !G" snp_invalidate_st2 $end + $var wire 26 mm" snp_req_addr [25:0] $end + $var wire 1 3l" snp_req_invalidate $end + $var wire 1 c.! snp_req_ready $end + $var wire 28 ;l" snp_req_tag [27:0] $end + $var wire 1 ?n" snp_req_valid $end + $var wire 1 3( snp_rsp_fire $end + $var wire 1 ]! snp_rsp_ready $end + $var wire 28 C4 snp_rsp_tag [27:0] $end + $var wire 1 ;4 snp_rsp_valid $end + $var wire 1 =} snp_to_mrvq_st1e $end + $var wire 1 )G" snp_to_mrvq_st2 $end + $var wire 26 _v snrq_addr_st0 [25:0] $end + $var wire 1 YC" snrq_empty $end + $var wire 1 aC" snrq_full $end + $var wire 1 gv snrq_invalidate_st0 $end + $var wire 1 Wv snrq_pop $end + $var wire 1 Uy snrq_pop_unqual $end + $var wire 28 ov snrq_tag_st0 [27:0] $end + $var wire 28 qG" snrq_tag_st2 [27:0] $end + $var wire 1 Kx st2_pending_hazard_st1e $end + $var wire 1 %y stall_bank_pipe $end + $var wire 42 [| tag_st1e [41:0] $end + $var wire 2 k| tid_st1e [1:0] $end + $var wire 1 gz valid_st1(0) $end + $var wire 1 U} valid_st1e $end + $var wire 1 ]E" valid_st2 $end + $var wire 128 9{ writedata_st1(0) [127:0] $end + $var wire 32 !{ writeword_st1(0) [31:0] $end + $var wire 32 mE" writeword_st2 [31:0] $end + $var wire 2 wz wsel_st1(0) [1:0] $end + $var wire 2 eE" wsel_st2 [1:0] $end + $scope module cache_miss_resrv $end + $var wire 32 Sp" BANK_ID [31:0] $end + $var wire 32 gn" BANK_LINE_SIZE [31:0] $end + $var wire 32 Wn" CACHE_ID [31:0] $end + $var wire 32 !o" CORE_TAG_WIDTH [31:0] $end + $var wire 32 gn" MRVQ_SIZE [31:0] $end + $var wire 32 on" NUM_BANKS [31:0] $end + $var wire 32 on" NUM_REQUESTS [31:0] $end + $var wire 32 1o" SNP_REQ_TAG_WIDTH [31:0] $end + $var wire 32 on" WORD_SIZE [31:0] $end + $var wire 416 s`" addr_table [415:0] $end + $var wire 1 Sh" clk $end + $var wire 4 /b" dequeue_index [3:0] $end + $var wire 1 3x dequeue_possible $end + $var wire 4 ?b" enqueue_index [3:0] $end + $var wire 1 Ob" enqueue_possible $end + $var wire 26 m} fill_addr_st1 [25:0] $end + $var wire 4 7b" head_ptr [3:0] $end + $var wire 1 {*! increment_head $end + $var wire 1 9%! is_fill_st1 $end + $var wire 1 G~ is_mrvq $end + $var wire 16 K*! make_ready [15:0] $end + $var wire 16 S*! make_ready_push [15:0] $end + $var wire 85 k\" metadata_table(0) [84:0] $end + $var wire 85 n\" metadata_table(1) [84:0] $end + $var wire 85 +]" metadata_table(10) [84:0] $end + $var wire 85 .]" metadata_table(11) [84:0] $end + $var wire 85 1]" metadata_table(12) [84:0] $end + $var wire 85 4]" metadata_table(13) [84:0] $end + $var wire 85 7]" metadata_table(14) [84:0] $end + $var wire 85 :]" metadata_table(15) [84:0] $end + $var wire 85 q\" metadata_table(2) [84:0] $end + $var wire 85 t\" metadata_table(3) [84:0] $end + $var wire 85 w\" metadata_table(4) [84:0] $end + $var wire 85 z\" metadata_table(5) [84:0] $end + $var wire 85 }\" metadata_table(6) [84:0] $end + $var wire 85 "]" metadata_table(7) [84:0] $end + $var wire 85 %]" metadata_table(8) [84:0] $end + $var wire 85 (]" metadata_table(9) [84:0] $end + $var wire 1 ?~ miss_add $end + $var wire 26 [.! miss_add_addr [25:0] $end + $var wire 4 ME" miss_add_byteen [3:0] $end + $var wire 32 mE" miss_add_data [31:0] $end + $var wire 1 wF" miss_add_is_snp $end + $var wire 1 EE" miss_add_rw $end + $var wire 1 !G" miss_add_snp_invalidate $end + $var wire 42 5E" miss_add_tag [41:0] $end + $var wire 2 -E" miss_add_tid [1:0] $end + $var wire 2 eE" miss_add_wsel [1:0] $end + $var wire 26 KD" miss_resrv_addr_st0 [25:0] $end + $var wire 4 sD" miss_resrv_byteen_st0 [3:0] $end + $var wire 32 [D" miss_resrv_data_st0 [31:0] $end + $var wire 1 3D" miss_resrv_full $end + $var wire 1 {D" miss_resrv_is_snp_st0 $end + $var wire 1 +x miss_resrv_pop $end + $var wire 1 ;x miss_resrv_rw_st0 $end + $var wire 1 %E" miss_resrv_snp_invalidate_st0 $end + $var wire 1 ;D" miss_resrv_stop $end + $var wire 42 cD" miss_resrv_tag_st0 [41:0] $end + $var wire 2 CD" miss_resrv_tid_st0 [1:0] $end + $var wire 1 3x miss_resrv_valid_st0 $end + $var wire 2 SD" miss_resrv_wsel_st0 [1:0] $end + $var wire 1 }} mrvq_init_ready_state $end + $var wire 1 k*! mrvq_pop $end + $var wire 1 c*! mrvq_push $end + $var wire 1 Cx pending_hazard $end + $var wire 1 -+! qual_mrvq_init $end + $var wire 16 'b" ready_table [15:0] $end + $var wire 1 s*! recover_state $end + $var wire 1 [h" reset $end + $var wire 4 /b" schedule_ptr [3:0] $end + $var wire 5 Gb" size [4:0] $end + $var wire 4 ?b" tail_ptr [3:0] $end + $var wire 1 %+! update_ready $end + $var wire 16 [*! valid_address_match [15:0] $end + $var wire 16 }a" valid_table [15:0] $end + $upscope $end + $scope module core_req_arb $end + $var wire 32 )o" CORE_TAG_ID_BITS [31:0] $end + $var wire 32 !o" CORE_TAG_WIDTH [31:0] $end + $var wire 32 on" CREQ_SIZE [31:0] $end + $var wire 32 on" NUM_REQUESTS [31:0] $end + $var wire 32 on" WORD_SIZE [31:0] $end + $var wire 120 {h" bank_addr [119:0] $end + $var wire 16 sh" bank_byteen [15:0] $end + $var wire 4 kh" bank_rw [3:0] $end + $var wire 42 ]i" bank_tag [41:0] $end + $var wire 4 E! bank_valids [3:0] $end + $var wire 128 =i" bank_writedata [127:0] $end + $var wire 1 Sh" clk $end + $var wire 1 ST" o_empty $end + $var wire 1 -#! out_empty $end + $var wire 120 ;"! out_per_addr [119:0] $end + $var wire 16 3"! out_per_byteen [15:0] $end + $var wire 4 +"! out_per_rw [3:0] $end + $var wire 42 {"! out_per_tag [41:0] $end + $var wire 4 #"! out_per_valids [3:0] $end + $var wire 128 ["! out_per_writedata [127:0] $end + $var wire 1 5#! pop_qual $end + $var wire 1 Q+ push_qual $end + $var wire 120 qS" qual_addr [119:0] $end + $var wire 16 iS" qual_byteen [15:0] $end + $var wire 1 Yw qual_has_request $end + $var wire 2 aw qual_request_index [1:0] $end + $var wire 4 aS" qual_rw [3:0] $end + $var wire 42 #D" qual_tag [41:0] $end + $var wire 4 YS" qual_valids [3:0] $end + $var wire 128 3T" qual_writedata [127:0] $end + $var wire 4 =#! real_out_per_valids [3:0] $end + $var wire 1 Qw reqq_empty $end + $var wire 1 yC" reqq_full $end + $var wire 1 Iw reqq_pop $end + $var wire 1 9+ reqq_push $end + $var wire 30 yw reqq_req_addr_st0 [29:0] $end + $var wire 4 qw reqq_req_byteen_st0 [3:0] $end + $var wire 1 iw reqq_req_rw_st0 $end + $var wire 1 Yw reqq_req_st0 $end + $var wire 42 #D" reqq_req_tag_st0 [41:0] $end + $var wire 2 aw reqq_req_tid_st0 [1:0] $end + $var wire 32 #x reqq_req_writedata_st0 [31:0] $end + $var wire 1 [h" reset $end + $var wire 1 [T" use_empty $end + $var wire 120 qS" use_per_addr [119:0] $end + $var wire 16 iS" use_per_byteen [15:0] $end + $var wire 4 aS" use_per_rw [3:0] $end + $var wire 42 #D" use_per_tag [41:0] $end + $var wire 4 YS" use_per_valids [3:0] $end + $var wire 128 3T" use_per_writedata [127:0] $end + $scope module reqq_queue $end + $var wire 32 wn" BUFFERED_OUTPUT [31:0] $end + $var wire 32 yo" DATAW [31:0] $end + $var wire 32 on" SIZE [31:0] $end + $var wire 1 Sh" clk $end + $var wire 314 %) data_in [313:0] $end + $var wire 314 E#! data_out [313:0] $end + $var wire 1 ST" empty $end + $var wire 1 yC" full $end + $var wire 1 5#! pop $end + $var wire 1 Q+ push $end + $var wire 1 7$! reading $end + $var wire 1 [h" reset $end + $var wire 3 cT" size [2:0] $end + $var wire 3 cT" size_r [2:0] $end + $var wire 1 u) writing $end + $scope module genblk3 $end + $var wire 314 kT" data(0) [313:0] $end + $var wire 314 uT" data(1) [313:0] $end + $var wire 314 !U" data(2) [313:0] $end + $var wire 314 +U" data(3) [313:0] $end + $scope module genblk2 $end + $var wire 1 /Z" bypass_r $end + $var wire 314 %Y" curr_r [313:0] $end + $var wire 1 ST" empty_r $end + $var wire 1 yC" full_r $end + $var wire 314 3X" head_r [313:0] $end + $var wire 2 'Z" rd_ptr_next_r [1:0] $end + $var wire 2 }Y" rd_ptr_r [1:0] $end + $var wire 2 uY" wr_ptr_r [1:0] $end + $upscope $end + $upscope $end + $upscope $end + $scope module sel_bank $end + $var wire 32 on" N [31:0] $end + $var wire 1 Sh" clk $end + $var wire 2 aw grant_index [1:0] $end + $var wire 4 ?$! grant_onehot [3:0] $end + $var wire 1 Yw grant_valid $end + $var wire 4 YS" requests [3:0] $end + $var wire 1 [h" reset $end + $scope module genblk2 $end + $var wire 4 ?$! grant_onehot_r [3:0] $end + $scope module priority_encoder $end + $var wire 32 on" N [31:0] $end + $var wire 4 YS" data_in [3:0] $end + $var wire 2 aw data_out [1:0] $end + $var wire 32 G$! i [31:0] $end + $var wire 1 Yw valid_out $end + $upscope $end + $upscope $end + $upscope $end + $upscope $end + $scope module cwb_queue $end + $var wire 32 wn" BUFFERED_OUTPUT [31:0] $end + $var wire 32 ;p" DATAW [31:0] $end + $var wire 32 on" SIZE [31:0] $end + $var wire 1 Sh" clk $end + $var wire 76 5+! data_in [75:0] $end + $var wire 76 M+! data_out [75:0] $end + $var wire 1 IG" empty $end + $var wire 1 QG" full $end + $var wire 1 A+ pop $end + $var wire 1 O~ push $end + $var wire 1 }) reading $end + $var wire 1 [h" reset $end + $var wire 3 Wb" size [2:0] $end + $var wire 3 Wb" size_r [2:0] $end + $var wire 1 e+! writing $end + $scope module genblk3 $end + $var wire 76 _b" data(0) [75:0] $end + $var wire 76 bb" data(1) [75:0] $end + $var wire 76 eb" data(2) [75:0] $end + $var wire 76 hb" data(3) [75:0] $end + $scope module genblk2 $end + $var wire 1 Kd" bypass_r $end + $var wire 76 yc" curr_r [75:0] $end + $var wire 1 IG" empty_r $end + $var wire 1 QG" full_r $end + $var wire 76 ac" head_r [75:0] $end + $var wire 2 Cd" rd_ptr_next_r [1:0] $end + $var wire 2 ;d" rd_ptr_r [1:0] $end + $var wire 2 3d" wr_ptr_r [1:0] $end + $upscope $end + $upscope $end + $upscope $end + $scope module dfp_queue $end + $var wire 32 wn" BUFFERED_OUTPUT [31:0] $end + $var wire 32 qo" DATAW [31:0] $end + $var wire 32 gn" SIZE [31:0] $end + $var wire 1 Sh" clk $end + $var wire 154 S( data_in [153:0] $end + $var wire 154 Q!! data_out [153:0] $end + $var wire 1 iC" empty $end + $var wire 1 qC" full $end + $var wire 1 wv pop $end + $var wire 1 7n" push $end + $var wire 1 y!! reading $end + $var wire 1 [h" reset $end + $var wire 5 QK" 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+#382 +0Sh" +#383 +1Sh" +#384 +b0000 3 +0S +0Sh" +0Ak" +#385 +1Sh" +#386 +b0001 3 +1S +0Sh" +1Ak" +#387 +1Sh" +#388 +0Sh" +#389 +1Sh" +#390 +0Sh" +#391 +1Sh" +#392 +0Sh" +#393 +1Sh" +#394 +0Sh" +#395 +1Sh" +#396 +0Sh" +#397 +1Sh" +#398 +0Sh" +#399 +1Sh" +#400 +0Sh" +#401 +1Sh" +#402 +0Sh" +#403 +1Sh" diff --git a/hw/unit_tests/cache/trace2.vcd b/hw/unit_tests/cache/trace2.vcd new file mode 100644 index 00000000..16494c99 --- /dev/null +++ b/hw/unit_tests/cache/trace2.vcd @@ -0,0 +1,9265 @@ +$version Generated by VerilatedVcd $end +$date Mon Jul 13 23:43:12 2020 + $end +$timescale 1ns $end + + $scope module TOP $end + $var wire 1 Sh" clk $end + $var wire 120 {h" core_req_addr [119:0] $end + $var wire 16 sh" core_req_byteen [15:0] $end + $var wire 128 =i" core_req_data [127:0] $end + $var wire 1 mi" core_req_ready $end + $var wire 4 kh" core_req_rw [3:0] $end + $var wire 42 ]i" core_req_tag [41:0] $end + $var wire 4 ch" core_req_valid [3:0] $end + $var wire 128 }i" core_rsp_data [127:0] $end + $var wire 1 Oj" core_rsp_ready $end + $var wire 42 ?j" core_rsp_tag [41:0] $end + $var wire 4 ui" core_rsp_valid [3:0] $end + $var wire 28 oj" dram_req_addr [27:0] $end + $var wire 16 gj" dram_req_byteen [15:0] $end + $var wire 128 wj" dram_req_data [127:0] $end + $var wire 1 Ak" dram_req_ready $end + $var wire 1 _j" dram_req_rw $end + $var wire 28 9k" dram_req_tag [27:0] $end + $var wire 1 Wj" dram_req_valid $end + $var wire 128 Qk" dram_rsp_data [127:0] $end + $var wire 1 yk" dram_rsp_ready $end + $var wire 28 qk" dram_rsp_tag [27:0] $end + $var wire 1 Ik" dram_rsp_valid $end + $var wire 1 [h" reset $end + $var wire 2 Em" snp_fwdin_ready [1:0] $end + $var wire 2 =m" snp_fwdin_tag [1:0] $end + $var wire 2 5m" snp_fwdin_valid [1:0] $end + $var wire 56 kl" snp_fwdout_addr [55:0] $end + $var wire 2 {l" snp_fwdout_invalidate [1:0] $end + $var wire 2 -m" snp_fwdout_ready [1:0] $end + $var wire 2 %m" snp_fwdout_tag [1:0] $end + $var wire 2 cl" snp_fwdout_valid [1:0] $end + $var wire 28 +l" snp_req_addr [27:0] $end + $var wire 1 3l" snp_req_invalidate $end + $var wire 1 Cl" snp_req_ready $end + $var wire 28 ;l" snp_req_tag [27:0] $end + $var wire 1 #l" snp_req_valid $end + $var wire 1 [l" snp_rsp_ready $end + $var wire 28 Sl" snp_rsp_tag [27:0] $end + $var wire 1 Kl" snp_rsp_valid $end + $scope module VX_cache $end + $var wire 32 gn" BANK_LINE_SIZE [31:0] $end + $var wire 32 Wn" CACHE_ID [31:0] $end + $var wire 32 _n" CACHE_SIZE [31:0] $end + $var wire 32 )o" CORE_TAG_ID_BITS [31:0] $end + $var wire 32 !o" CORE_TAG_WIDTH [31:0] $end + $var wire 32 on" CREQ_SIZE [31:0] $end + $var wire 32 on" CWBQ_SIZE [31:0] $end + $var wire 32 gn" DFPQ_SIZE [31:0] $end + $var wire 32 on" DFQQ_SIZE [31:0] $end + $var wire 32 wn" DRAM_ENABLE [31:0] $end + $var wire 32 1o" DRAM_TAG_WIDTH [31:0] $end + $var wire 32 on" DWBQ_SIZE [31:0] $end + $var wire 32 gn" MRVQ_SIZE [31:0] $end + $var wire 32 on" NUM_BANKS [31:0] $end + $var wire 32 on" NUM_REQUESTS [31:0] $end + $var wire 32 9o" NUM_SNP_REQUESTS [31:0] $end + $var wire 32 wn" PRFQ_SIZE [31:0] $end + $var wire 32 Wn" PRFQ_STRIDE [31:0] $end + $var wire 32 Wn" SNOOP_FORWARDING [31:0] $end + $var wire 32 wn" SNP_FWD_TAG_WIDTH [31:0] $end + $var wire 32 1o" SNP_REQ_TAG_WIDTH [31:0] $end + $var wire 32 gn" SNRQ_SIZE [31:0] $end + $var wire 32 wn" STAGE_1_CYCLES [31:0] $end + $var wire 32 on" WORD_SIZE [31:0] $end + $var wire 32 wn" WRITE_ENABLE [31:0] $end + $var wire 1 Sh" clk $end + $var wire 120 {h" core_req_addr [119:0] $end + $var wire 16 sh" core_req_byteen [15:0] $end + $var wire 128 =i" core_req_data [127:0] $end + $var wire 1 mi" core_req_ready $end + $var wire 4 kh" core_req_rw [3:0] $end + $var wire 42 ]i" core_req_tag [41:0] $end + $var wire 4 ch" core_req_valid [3:0] $end + $var wire 128 }i" core_rsp_data [127:0] $end + $var wire 1 Oj" core_rsp_ready $end + $var wire 42 ?j" core_rsp_tag [41:0] $end + $var wire 4 ui" core_rsp_valid [3:0] $end + $var wire 1 )-! dram_fill_req_ready $end + $var wire 28 oj" dram_req_addr [27:0] $end + $var wire 16 gj" dram_req_byteen [15:0] $end + $var wire 128 wj" dram_req_data [127:0] $end + $var wire 1 Ak" dram_req_ready $end + $var wire 1 _j" dram_req_rw $end + $var wire 28 9k" dram_req_tag [27:0] $end + $var wire 1 Wj" dram_req_valid $end + $var wire 128 Qk" dram_rsp_data [127:0] $end + $var wire 1 yk" dram_rsp_ready $end + $var wire 28 qk" dram_rsp_tag [27:0] $end + $var wire 1 Ik" dram_rsp_valid $end + $var wire 4 Y+ per_bank_core_req_ready [3:0] $end + $var wire 128 q+ per_bank_core_rsp_data [127:0] $end + $var wire 4 + per_bank_core_rsp_ready [3:0] $end + $var wire 168 3, per_bank_core_rsp_tag [167:0] $end + $var wire 8 i+ per_bank_core_rsp_tid [7:0] $end + $var wire 4 a+ per_bank_core_rsp_valid [3:0] $end + $var wire 112 k, per_bank_dram_fill_req_addr [111:0] $end + $var wire 4 c, per_bank_dram_fill_req_valid [3:0] $end + $var wire 4 -- per_bank_dram_fill_rsp_ready [3:0] $end + $var wire 112 M- per_bank_dram_wb_req_addr [111:0] $end + $var wire 64 =- per_bank_dram_wb_req_byteen [63:0] $end + $var wire 512 m- per_bank_dram_wb_req_data [511:0] $end + $var wire 4 3 per_bank_dram_wb_req_ready [3:0] $end + $var wire 4 5- per_bank_dram_wb_req_valid [3:0] $end + $var wire 4 1/ per_bank_snp_req_ready [3:0] $end + $var wire 4 ; per_bank_snp_rsp_ready [3:0] $end + $var wire 112 A/ per_bank_snp_rsp_tag [111:0] $end + $var wire 4 9/ per_bank_snp_rsp_valid [3:0] $end + $var wire 16 # per_bank_valid [15:0] $end + $var wire 1 [h" reset $end + $var wire 2 Em" snp_fwdin_ready [1:0] $end + $var wire 2 =m" snp_fwdin_tag [1:0] $end + $var wire 2 5m" snp_fwdin_valid [1:0] $end + $var wire 56 kl" snp_fwdout_addr [55:0] $end + $var wire 2 {l" snp_fwdout_invalidate [1:0] $end + $var wire 2 -m" snp_fwdout_ready [1:0] $end + $var wire 2 %m" snp_fwdout_tag [1:0] $end + $var wire 2 cl" snp_fwdout_valid [1:0] $end + $var wire 28 +l" snp_req_addr [27:0] $end + $var wire 28 +l" snp_req_addr_qual [27:0] $end + $var wire 1 3l" snp_req_invalidate $end + $var wire 1 3l" snp_req_invalidate_qual $end + $var wire 1 Cl" snp_req_ready $end + $var wire 1 Mm" snp_req_ready_qual $end + $var wire 28 ;l" snp_req_tag [27:0] $end + $var wire 28 ;l" snp_req_tag_qual [27:0] $end + $var wire 1 #l" snp_req_valid $end + $var wire 1 #l" snp_req_valid_qual $end + $var wire 1 [l" snp_rsp_ready $end + $var wire 28 Sl" snp_rsp_tag [27:0] $end + $var wire 1 Kl" snp_rsp_valid $end + $scope module cache_core_req_bank_sel $end + $var wire 32 gn" BANK_LINE_SIZE [31:0] $end + $var wire 32 on" NUM_BANKS [31:0] $end + $var wire 32 on" NUM_REQUESTS [31:0] $end + $var wire 32 on" WORD_SIZE [31:0] $end + $var wire 120 {h" core_req_addr [119:0] $end + $var wire 1 mi" core_req_ready $end + $var wire 4 ch" core_req_valid [3:0] $end + $var wire 32 Ao" i [31:0] $end + $var wire 4 Y+ per_bank_ready [3:0] $end + $var wire 16 # per_bank_valid [15:0] $end + $scope module genblk2 $end + $var wire 4 e! per_bank_ready_sel [3:0] $end + $upscope $end + $upscope $end + $scope module cache_core_rsp_merge $end + $var wire 32 )o" CORE_TAG_ID_BITS [31:0] $end + $var wire 32 !o" CORE_TAG_WIDTH [31:0] $end + $var wire 32 on" NUM_BANKS [31:0] $end + $var wire 32 on" NUM_REQUESTS [31:0] $end + $var wire 32 on" WORD_SIZE [31:0] $end + $var wire 1 Sh" clk $end + $var wire 128 Y7 core_rsp_data [127:0] $end + $var wire 1 Oj" core_rsp_ready $end + $var wire 42 y7 core_rsp_tag [41:0] $end + $var wire 4 ui" core_rsp_valid [3:0] $end + $var wire 1 ;8 grant_valid $end + $var wire 32 Ao" i [31:0] $end + $var wire 2 38 main_bank_index [1:0] $end + $var wire 128 q+ per_bank_core_rsp_data [127:0] $end + $var wire 4 +8 per_bank_core_rsp_pop_unqual [3:0] $end + $var wire 4 + per_bank_core_rsp_ready [3:0] $end + $var wire 168 3, per_bank_core_rsp_tag [167:0] $end + $var wire 8 i+ per_bank_core_rsp_tid [7:0] $end + $var wire 4 a+ per_bank_core_rsp_valid [3:0] $end + $var wire 1 [h" reset $end + $scope module sel_bank $end + $var wire 32 on" N [31:0] $end + $var wire 1 Sh" clk $end + $var wire 2 38 grant_index [1:0] $end + $var wire 4 C8 grant_onehot [3:0] $end + $var wire 1 ;8 grant_valid $end + $var wire 4 a+ requests [3:0] $end + $var wire 1 [h" reset $end + $scope module genblk2 $end + $var wire 4 C8 grant_onehot_r [3:0] $end + $var wire 4 S8 late_value [3:0] $end + $var wire 1 [2! refill $end + $var wire 4 c2! refill_original [3:0] $end + $var wire 4 a+ refill_value [3:0] $end + $var wire 4 S2! requests_use [3:0] $end + $var wire 4 K8 update_value [3:0] $end + $scope module priority_encoder $end + $var wire 32 on" N [31:0] $end + $var wire 4 S2! data_in [3:0] $end + $var wire 2 38 data_out [1:0] $end + $var wire 32 [8 i [31:0] $end + $var wire 1 ;8 valid_out $end + $upscope $end + $upscope $end + $upscope $end + $upscope $end + $scope module cache_dram_req_arb $end + $var wire 32 gn" BANK_LINE_SIZE [31:0] $end + $var wire 32 on" DFQQ_SIZE [31:0] $end + $var wire 32 on" NUM_BANKS [31:0] $end + $var wire 32 wn" PRFQ_SIZE [31:0] $end + $var wire 32 Wn" PRFQ_STRIDE [31:0] $end + $var wire 32 on" WORD_SIZE [31:0] $end + $var wire 1 Sh" clk $end + $var wire 1 c4 dfqq_empty $end + $var wire 1 {.! dfqq_full $end + $var wire 1 m! dfqq_pop $end + $var wire 1 k4 dfqq_push $end + $var wire 1 S4 dfqq_req $end + $var wire 28 [4 dfqq_req_addr [27:0] $end + $var wire 1 )-! dram_fill_req_ready $end + $var wire 28 oj" dram_req_addr [27:0] $end + $var wire 16 gj" dram_req_byteen [15:0] $end + $var wire 128 wj" dram_req_data [127:0] $end + $var wire 1 Ak" dram_req_ready $end + $var wire 1 _j" dram_req_rw $end + $var wire 1 Wj" dram_req_valid $end + $var wire 2 s4 dwb_bank [1:0] $end + $var wire 1 K4 dwb_valid $end + $var wire 112 k, per_bank_dram_fill_req_addr [111:0] $end + $var wire 4 c, per_bank_dram_fill_req_valid [3:0] $end + $var wire 112 M- per_bank_dram_wb_req_addr [111:0] $end + $var wire 64 =- per_bank_dram_wb_req_byteen [63:0] $end + $var wire 512 m- per_bank_dram_wb_req_data [511:0] $end + $var wire 4 3 per_bank_dram_wb_req_ready [3:0] $end + $var wire 4 5- per_bank_dram_wb_req_valid [3:0] $end + $var wire 28 s.! pref_addr [27:0] $end + $var wire 1 Io" pref_pop $end + $var wire 1 Io" pref_valid $end + $var wire 1 [h" reset $end + $scope module dram_fill_arb $end + $var wire 32 gn" BANK_LINE_SIZE [31:0] $end + $var wire 32 on" DFQQ_SIZE [31:0] $end + $var wire 32 on" NUM_BANKS [31:0] $end + $var wire 1 Sh" clk $end + $var wire 1 c4 dfqq_empty $end + $var wire 1 {.! dfqq_full $end + $var wire 1 m! dfqq_pop $end + $var wire 1 k4 dfqq_push $end + $var wire 1 S4 dfqq_req $end + $var wire 28 [4 dfqq_req_addr [27:0] $end + $var wire 1 u/! o_empty $end + $var wire 1 /6 out_empty $end + $var wire 112 =5 out_per_bank_dram_fill_req_addr [111:0] $end + $var wire 4 55 out_per_bank_dram_fill_req_valid [3:0] $end + $var wire 112 k, per_bank_dram_fill_req_addr [111:0] $end + $var wire 4 c, per_bank_dram_fill_req_valid [3:0] $end + $var wire 1 /* pop_qual $end + $var wire 1 76 push_qual $end + $var wire 112 e5 qual_bank_dram_fill_req_addr [111:0] $end + $var wire 1 G6 qual_has_request $end + $var wire 2 ?6 qual_request_index [1:0] $end + $var wire 1 [h" reset $end + $var wire 4 '6 updated_bank_dram_fill_req_valid [3:0] $end + $var wire 1 }/! use_empty $end + $var wire 112 U/! use_per_bank_dram_fill_req_addr [111:0] $end + $var wire 4 M/! use_per_bank_dram_fill_req_valid [3:0] $end + $var wire 4 ]5 use_per_bqual_bank_dram_fill_req_valid [3:0] $end + $scope module dfqq_queue $end + $var wire 32 wn" BUFFERED_OUTPUT [31:0] $end + $var wire 32 Qo" DATAW [31:0] $end + $var wire 32 on" SIZE [31:0] $end + $var wire 1 Sh" clk $end + $var wire 116 O6 data_in [115:0] $end + $var wire 116 o6 data_out [115:0] $end + $var wire 1 u/! empty $end + $var wire 1 {.! full $end + $var wire 1 /* pop $end + $var wire 1 76 push $end + $var wire 1 u! reading $end + $var wire 1 [h" reset $end + $var wire 3 '0! size [2:0] $end + $var wire 3 '0! size_r [2:0] $end + $var wire 1 17 writing $end + $scope module genblk3 $end + $var wire 116 /0! data(0) [115:0] $end + $var wire 116 30! data(1) [115:0] $end + $var wire 116 70! data(2) [115:0] $end + $var wire 116 ;0! data(3) [115:0] $end + $scope module genblk2 $end + $var wire 1 K2! bypass_r $end + $var wire 116 q1! curr_r [115:0] $end + $var wire 1 u/! empty_r $end + $var wire 1 {.! full_r $end + $var wire 116 Q1! head_r [115:0] $end + $var wire 2 C2! rd_ptr_next_r [1:0] $end + $var wire 2 ;2! rd_ptr_r [1:0] $end + $var wire 2 32! wr_ptr_r [1:0] $end + $upscope $end + $upscope $end + $upscope $end + $scope module sel_bank $end + $var wire 32 on" N [31:0] $end + $var wire 1 Sh" clk $end + $var wire 2 ?6 grant_index [1:0] $end + $var wire 4 97 grant_onehot [3:0] $end + $var wire 1 G6 grant_valid $end + $var wire 4 ]5 requests [3:0] $end + $var wire 1 [h" reset $end + $scope module genblk2 $end + $var wire 4 97 grant_onehot_r [3:0] $end + $scope module priority_encoder $end + $var wire 32 on" N [31:0] $end + $var wire 4 ]5 data_in [3:0] $end + $var wire 2 ?6 data_out [1:0] $end + $var wire 32 A7 i [31:0] $end + $var wire 1 G6 valid_out $end + $upscope $end + $upscope $end + $upscope $end + $upscope $end + $scope module prfqq $end + $var wire 32 gn" BANK_LINE_SIZE [31:0] $end + $var wire 32 wn" PRFQ_SIZE [31:0] $end + $var wire 32 Wn" PRFQ_STRIDE [31:0] $end + $var wire 32 on" WORD_SIZE [31:0] $end + $var wire 1 Sh" clk $end + $var wire 28 5/! current_addr [27:0] $end + $var wire 1 =/! current_empty $end + $var wire 1 -/! current_full $end + $var wire 1 -/! current_valid $end + $var wire 1 Gn" dram_req $end + $var wire 28 oj" dram_req_addr [27:0] $end + $var wire 28 s.! pref_addr [27:0] $end + $var wire 1 Io" pref_pop $end + $var wire 1 Io" pref_valid $end + $var wire 1 [h" reset $end + $var wire 1 {4 update_use $end + $var wire 28 s.! use_addr [27:0] $end + $var wire 2 %/! use_valid [1:0] $end + $scope module pfq_queue $end + $var wire 32 wn" BUFFERED_OUTPUT [31:0] $end + $var wire 32 1o" DATAW [31:0] $end + $var wire 32 wn" SIZE [31:0] $end + $var wire 1 Sh" clk $end + $var wire 28 oj" data_in [27:0] $end + $var wire 28 5/! data_out [27:0] $end + $var wire 1 =/! empty $end + $var wire 1 -/! full $end + $var wire 1 {4 pop $end + $var wire 1 On" push $end + $var wire 1 %5 reading $end + $var wire 1 [h" reset $end + $var wire 1 E/! size [0:0] $end + $var wire 1 E/! size_r [0:0] $end + $var wire 1 -5 writing $end + $scope module genblk2 $end + $var wire 28 5/! head_r [27:0] $end + $upscope $end + $upscope $end + $upscope $end + $scope module sel_dwb $end + $var wire 32 on" N [31:0] $end + $var wire 1 Sh" clk $end + $var wire 2 s4 grant_index [1:0] $end + $var wire 4 I7 grant_onehot [3:0] $end + $var wire 1 K4 grant_valid $end + $var wire 4 5- requests [3:0] $end + $var wire 1 [h" reset $end + $scope module genblk2 $end + $var wire 4 I7 grant_onehot_r [3:0] $end + $scope module priority_encoder $end + $var wire 32 on" N [31:0] $end + $var wire 4 5- data_in [3:0] $end + $var wire 2 s4 data_out [1:0] $end + $var wire 32 Q7 i [31:0] $end + $var wire 1 K4 valid_out $end + $upscope $end + $upscope $end + $upscope $end + $upscope $end + $scope module genblk5(0) $end + $var wire 120 {h" curr_bank_core_req_addr [119:0] $end + $var wire 16 sh" curr_bank_core_req_byteen [15:0] $end + $var wire 128 =i" curr_bank_core_req_data [127:0] $end + $var wire 1 Q-! curr_bank_core_req_ready $end + $var wire 4 kh" curr_bank_core_req_rw [3:0] $end + $var wire 42 ]i" curr_bank_core_req_tag [41:0] $end + $var wire 4 C curr_bank_core_req_valid [3:0] $end + $var wire 32 i/ curr_bank_core_rsp_data [31:0] $end + $var wire 1 K curr_bank_core_rsp_ready $end + $var wire 42 q/ curr_bank_core_rsp_tag [41:0] $end + $var wire 2 a/ curr_bank_core_rsp_tid [1:0] $end + $var wire 1 1-! curr_bank_core_rsp_valid $end + $var wire 26 A-! curr_bank_dram_fill_req_addr [25:0] $end + $var wire 1 )-! curr_bank_dram_fill_req_ready $end + $var wire 1 #0 curr_bank_dram_fill_req_valid $end + $var wire 26 ]m" curr_bank_dram_fill_rsp_addr [25:0] $end + $var wire 128 Qk" curr_bank_dram_fill_rsp_data [127:0] $end + $var wire 1 9-! curr_bank_dram_fill_rsp_ready $end + $var wire 1 Um" curr_bank_dram_fill_rsp_valid $end + $var wire 26 ;0 curr_bank_dram_wb_req_addr [25:0] $end + $var wire 16 30 curr_bank_dram_wb_req_byteen [15:0] $end + $var wire 128 C0 curr_bank_dram_wb_req_data [127:0] $end + $var wire 1 S curr_bank_dram_wb_req_ready $end + $var wire 1 +0 curr_bank_dram_wb_req_valid $end + $var wire 26 mm" curr_bank_snp_req_addr [25:0] $end + $var wire 1 3l" curr_bank_snp_req_invalidate $end + $var wire 1 I-! curr_bank_snp_req_ready $end + $var wire 28 ;l" curr_bank_snp_req_tag [27:0] $end + $var wire 1 em" curr_bank_snp_req_valid $end + $var wire 1 [ curr_bank_snp_rsp_ready $end + $var wire 28 k0 curr_bank_snp_rsp_tag [27:0] $end + $var wire 1 c0 curr_bank_snp_rsp_valid $end + $scope module bank $end + $var wire 32 Yo" BANK_ID [31:0] $end + $var wire 32 gn" BANK_LINE_SIZE [31:0] $end + $var wire 32 Wn" CACHE_ID [31:0] $end + $var wire 32 _n" CACHE_SIZE [31:0] $end + $var wire 32 )o" CORE_TAG_ID_BITS [31:0] $end + $var wire 32 !o" CORE_TAG_WIDTH [31:0] $end + $var wire 32 on" CREQ_SIZE [31:0] $end + $var wire 32 on" CWBQ_SIZE [31:0] $end + $var wire 32 gn" DFPQ_SIZE [31:0] $end + $var wire 32 on" DFQQ_SIZE [31:0] $end + $var wire 32 wn" DRAM_ENABLE [31:0] $end + $var wire 32 on" DWBQ_SIZE [31:0] $end + $var wire 32 gn" MRVQ_SIZE [31:0] $end + $var wire 32 on" NUM_BANKS [31:0] $end + $var wire 32 on" NUM_REQUESTS [31:0] $end + $var wire 32 Wn" SNOOP_FORWARDING [31:0] $end + $var wire 32 1o" SNP_REQ_TAG_WIDTH [31:0] $end + $var wire 32 gn" SNRQ_SIZE [31:0] $end + $var wire 32 wn" STAGE_1_CYCLES [31:0] $end + $var wire 32 on" WORD_SIZE [31:0] $end + $var wire 32 wn" WRITE_ENABLE [31:0] $end + $var wire 26 == addr_st1(0) [25:0] $end + $var wire 26 ;@ addr_st1e [25:0] $end + $var wire 26 A-! addr_st2 [25:0] $end + $var wire 1 Sh" clk $end + $var wire 120 {h" core_req_addr [119:0] $end + $var wire 16 sh" core_req_byteen [15:0] $end + $var wire 128 =i" core_req_data [127:0] $end + $var wire 1 Q-! core_req_ready $end + $var wire 4 kh" core_req_rw [3:0] $end + $var wire 42 ]i" core_req_tag [41:0] $end + $var wire 4 C core_req_valid [3:0] $end + $var wire 32 i/ core_rsp_data [31:0] $end + $var wire 1 K core_rsp_ready $end + $var wire 42 q/ core_rsp_tag [41:0] $end + $var wire 2 a/ core_rsp_tid [1:0] $end + $var wire 1 1-! core_rsp_valid $end + $var wire 32 )5! cwbq_data [31:0] $end + $var wire 1 [6! cwbq_empty $end + $var wire 1 c6! cwbq_full $end + $var wire 1 ?* cwbq_pop $end + $var wire 1 {@ cwbq_push $end + $var wire 1 9; cwbq_push_stall $end + $var wire 1 %A cwbq_push_unqual $end + $var wire 42 G4! cwbq_tag [41:0] $end + $var wire 2 ?4! cwbq_tid [1:0] $end + $var wire 26 M9 dfpq_addr_st0 [25:0] $end + $var wire 1 {2! dfpq_empty $end + $var wire 128 U9 dfpq_filldata_st0 [127:0] $end + $var wire 1 %3! dfpq_full $end + $var wire 1 E9 dfpq_pop $end + $var wire 1 q; dfpq_pop_unqual $end + $var wire 1 w> dirty_st1e $end + $var wire 1 Y5! dirty_st2 $end + $var wire 16 !? dirtyb_st1e [15:0] $end + $var wire 16 a5! dirtyb_st2 [15:0] $end + $var wire 26 A-! dram_fill_req_addr [25:0] $end + $var wire 1 c@ dram_fill_req_fast $end + $var wire 1 )-! dram_fill_req_ready $end + $var wire 1 I; dram_fill_req_stall $end + $var wire 1 -A dram_fill_req_unqual $end + $var wire 1 #0 dram_fill_req_valid $end + $var wire 26 ]m" dram_fill_rsp_addr [25:0] $end + $var wire 128 Qk" dram_fill_rsp_data [127:0] $end + $var wire 1 9-! dram_fill_rsp_ready $end + $var wire 1 Um" dram_fill_rsp_valid $end + $var wire 26 ;0 dram_wb_req_addr [25:0] $end + $var wire 16 30 dram_wb_req_byteen [15:0] $end + $var wire 128 C0 dram_wb_req_data [127:0] $end + $var wire 1 }! dram_wb_req_fire $end + $var wire 1 S dram_wb_req_ready $end + $var wire 1 +0 dram_wb_req_valid $end + $var wire 1 -7! dwbq_dual_valid_sel $end + $var wire 1 k6! dwbq_empty $end + $var wire 1 s6! dwbq_full $end + $var wire 1 =A dwbq_is_dwb_in $end + $var wire 1 MA dwbq_is_dwb_out $end + $var wire 1 EA dwbq_is_snp_in $end + $var wire 1 UA dwbq_is_snp_out $end + $var wire 1 G* dwbq_pop $end + $var wire 1 5A dwbq_push $end + $var wire 1 A; dwbq_push_stall $end + $var wire 1 ]A dwbq_push_unqual $end + $var wire 26 {6! dwbq_req_addr [25:0] $end + $var wire 1 Q? fill_saw_dirty_st1e $end + $var wire 1 #6! fill_saw_dirty_st2 $end + $var wire 1 !; force_request_miss_st1e $end + $var wire 1 i; going_to_write_st1(0) $end + $var wire 49 U= inst_meta_st1(0) [48:0] $end + $var wire 49 i5! inst_meta_st2 [48:0] $end + $var wire 1 Y; is_fill_in_pipe $end + $var wire 1 a; is_fill_st1(0) $end + $var wire 1 g4! is_fill_st2 $end + $var wire 1 7> is_mrvq_st1(0) $end + $var wire 1 +@ is_mrvq_st1e $end + $var wire 1 +@ is_mrvq_st1e_st2 $end + $var wire 1 C6! is_mrvq_st2 $end + $var wire 1 '> is_snp_st1(0) $end + $var wire 1 Y? is_snp_st1e $end + $var wire 1 +6! is_snp_st2 $end + $var wire 32 ao" j [31:0] $end + $var wire 4 I? mem_byteen_st1e [3:0] $end + $var wire 1 A? mem_rw_st1e $end + $var wire 1 k@ miss_add $end + $var wire 26 A-! miss_add_addr [25:0] $end + $var wire 1 y? miss_add_because_miss $end + $var wire 1 ;6! miss_add_because_pending $end + $var wire 4 _4! miss_add_byteen [3:0] $end + $var wire 32 !5! miss_add_data [31:0] $end + $var wire 1 s@ miss_add_is_mrvq $end + $var wire 1 +6! miss_add_is_snp $end + $var wire 1 W4! miss_add_rw $end + $var wire 1 36! miss_add_snp_invalidate $end + $var wire 42 G4! miss_add_tag [41:0] $end + $var wire 2 ?4! miss_add_tid [1:0] $end + $var wire 1 c@ miss_add_unqual $end + $var wire 2 w4! miss_add_wsel [1:0] $end + $var wire 1 o> miss_st1e $end + $var wire 1 Q5! miss_st2 $end + $var wire 26 ]3! mrvq_addr_st0 [25:0] $end + $var wire 4 '4! mrvq_byteen_st0 [3:0] $end + $var wire 1 E3! mrvq_full $end + $var wire 1 S@ mrvq_init_ready_state_hazard_st0_st1 $end + $var wire 1 [@ mrvq_init_ready_state_hazard_st1e_st1 $end + $var wire 1 q? mrvq_init_ready_state_st1e $end + $var wire 1 K@ mrvq_init_ready_state_st2 $end + $var wire 1 S6! mrvq_init_ready_state_unqual_st2 $end + $var wire 1 /4! mrvq_is_snp_st0 $end + $var wire 1 o: mrvq_pending_hazard_st1e $end + $var wire 1 W: mrvq_pop $end + $var wire 1 _: mrvq_pop_unqual $end + $var wire 1 1; mrvq_push_stall $end + $var wire 1 3@ mrvq_recover_ready_state_st1e $end + $var wire 1 K6! mrvq_recover_ready_state_st2 $end + $var wire 1 g: mrvq_rw_st0 $end + $var wire 1 74! mrvq_snp_invalidate_st0 $end + $var wire 1 M3! mrvq_stop $end + $var wire 42 u3! mrvq_tag_st0 [41:0] $end + $var wire 2 U3! mrvq_tid_st0 [1:0] $end + $var wire 1 _: mrvq_valid_st0 $end + $var wire 32 m3! mrvq_writeword_st0 [31:0] $end + $var wire 2 e3! mrvq_wsel_st0 [1:0] $end + $var wire 26 3< qual_addr_st0 [25:0] $end + $var wire 1 {< qual_going_to_write_st0 $end + $var wire 49 k< qual_inst_meta_st0 [48:0] $end + $var wire 1 q; qual_is_fill_st0 $end + $var wire 1 _: qual_is_mrvq_st0 $end + $var wire 1 %= qual_is_snp_st0 $end + $var wire 1 -= qual_snp_invalidate_st0 $end + $var wire 1 +< qual_valid_st0 $end + $var wire 1 C@ qual_valid_st1e_2 $end + $var wire 128 K< qual_writedata_st0 [127:0] $end + $var wire 32 C< qual_writeword_st0 [31:0] $end + $var wire 2 ;< qual_wsel_st0 [1:0] $end + $var wire 128 G> readdata_st1e [127:0] $end + $var wire 128 15! readdata_st2 [127:0] $end + $var wire 20 g> readtag_st1e [19:0] $end + $var wire 20 y5! readtag_st2 [19:0] $end + $var wire 32 ?> readword_st1e [31:0] $end + $var wire 32 )5! readword_st2 [31:0] $end + $var wire 1 ); recover_mrvq_state_st2 $end + $var wire 1 }9 reqq_empty $end + $var wire 1 -3! reqq_full $end + $var wire 1 u9 reqq_pop $end + $var wire 1 y; reqq_pop_unqual $end + $var wire 1 7* reqq_push $end + $var wire 30 G: reqq_req_addr_st0 [29:0] $end + $var wire 4 ?: reqq_req_byteen_st0 [3:0] $end + $var wire 1 7: reqq_req_rw_st0 $end + $var wire 1 ': reqq_req_st0 $end + $var wire 42 53! reqq_req_tag_st0 [41:0] $end + $var wire 2 /: reqq_req_tid_st0 [1:0] $end + $var wire 32 O: reqq_req_writeword_st0 [31:0] $end + $var wire 1 [h" reset $end + $var wire 1 /> snp_invalidate_st1(0) $end + $var wire 1 a? snp_invalidate_st1e $end + $var wire 1 36! snp_invalidate_st2 $end + $var wire 26 mm" snp_req_addr [25:0] $end + $var wire 1 3l" snp_req_invalidate $end + $var wire 1 I-! snp_req_ready $end + $var wire 28 ;l" snp_req_tag [27:0] $end + $var wire 1 em" snp_req_valid $end + $var wire 1 '" snp_rsp_fire $end + $var wire 1 [ snp_rsp_ready $end + $var wire 28 k0 snp_rsp_tag [27:0] $end + $var wire 1 c0 snp_rsp_valid $end + $var wire 1 i? snp_to_mrvq_st1e $end + $var wire 1 ;6! snp_to_mrvq_st2 $end + $var wire 26 -9 snrq_addr_st0 [25:0] $end + $var wire 1 k2! snrq_empty $end + $var wire 1 s2! snrq_full $end + $var wire 1 59 snrq_invalidate_st0 $end + $var wire 1 %9 snrq_pop $end + $var wire 1 #< snrq_pop_unqual $end + $var wire 28 =9 snrq_tag_st0 [27:0] $end + $var wire 28 %7! snrq_tag_st2 [27:0] $end + $var wire 1 w: st2_pending_hazard_st1e $end + $var wire 1 Q; stall_bank_pipe $end + $var wire 42 )? tag_st1e [41:0] $end + $var wire 2 9? tid_st1e [1:0] $end + $var wire 1 5= valid_st1(0) $end + $var wire 1 #@ valid_st1e $end + $var wire 1 o4! valid_st2 $end + $var wire 128 e= writedata_st1(0) [127:0] $end + $var wire 32 M= writeword_st1(0) [31:0] $end + $var wire 32 !5! writeword_st2 [31:0] $end + $var wire 2 E= wsel_st1(0) [1:0] $end + $var wire 2 w4! wsel_st2 [1:0] $end + $scope module cache_miss_resrv $end + $var wire 32 Yo" BANK_ID [31:0] $end + $var wire 32 gn" BANK_LINE_SIZE [31:0] $end + $var wire 32 Wn" CACHE_ID [31:0] $end + $var wire 32 !o" CORE_TAG_WIDTH [31:0] $end + $var wire 32 gn" MRVQ_SIZE [31:0] $end + $var wire 32 on" NUM_BANKS [31:0] $end + $var wire 32 on" NUM_REQUESTS [31:0] $end + $var wire 32 1o" SNP_REQ_TAG_WIDTH [31:0] $end + $var wire 32 on" WORD_SIZE [31:0] $end + $var wire 416 'P! addr_table [415:0] $end + $var wire 1 Sh" clk $end + $var wire 4 AQ! dequeue_index [3:0] $end + $var wire 1 _: dequeue_possible $end + $var wire 4 QQ! enqueue_index [3:0] $end + $var wire 1 aQ! enqueue_possible $end + $var wire 26 ;@ fill_addr_st1 [25:0] $end + $var wire 4 IQ! head_ptr [3:0] $end + $var wire 1 IK increment_head $end + $var wire 1 eE is_fill_st1 $end + $var wire 1 s@ is_mrvq $end + $var wire 16 wJ make_ready [15:0] $end + $var wire 16 !K make_ready_push [15:0] $end + $var wire 85 }K! metadata_table(0) [84:0] $end + $var wire 85 "L! metadata_table(1) [84:0] $end + $var wire 85 =L! metadata_table(10) [84:0] $end + $var wire 85 @L! metadata_table(11) [84:0] $end + $var wire 85 CL! metadata_table(12) [84:0] $end + $var wire 85 FL! metadata_table(13) [84:0] $end + $var wire 85 IL! metadata_table(14) [84:0] $end + $var wire 85 LL! metadata_table(15) [84:0] $end + $var wire 85 %L! metadata_table(2) [84:0] $end + $var wire 85 (L! metadata_table(3) [84:0] $end + $var wire 85 +L! metadata_table(4) [84:0] $end + $var wire 85 .L! metadata_table(5) [84:0] $end + $var wire 85 1L! metadata_table(6) [84:0] $end + $var wire 85 4L! metadata_table(7) [84:0] $end + $var wire 85 7L! metadata_table(8) [84:0] $end + $var wire 85 :L! metadata_table(9) [84:0] $end + $var wire 1 k@ miss_add $end + $var wire 26 A-! miss_add_addr [25:0] $end + $var wire 4 _4! miss_add_byteen [3:0] $end + $var wire 32 !5! miss_add_data [31:0] $end + $var wire 1 +6! miss_add_is_snp $end + $var wire 1 W4! miss_add_rw $end + $var wire 1 36! miss_add_snp_invalidate $end + $var wire 42 G4! miss_add_tag [41:0] $end + $var wire 2 ?4! miss_add_tid [1:0] $end + $var wire 2 w4! miss_add_wsel [1:0] $end + $var wire 26 ]3! miss_resrv_addr_st0 [25:0] $end + $var wire 4 '4! miss_resrv_byteen_st0 [3:0] $end + $var wire 32 m3! miss_resrv_data_st0 [31:0] $end + $var wire 1 E3! miss_resrv_full $end + $var wire 1 /4! miss_resrv_is_snp_st0 $end + $var wire 1 W: miss_resrv_pop $end + $var wire 1 g: miss_resrv_rw_st0 $end + $var wire 1 74! miss_resrv_snp_invalidate_st0 $end + $var wire 1 M3! miss_resrv_stop $end + $var wire 42 u3! miss_resrv_tag_st0 [41:0] $end + $var wire 2 U3! miss_resrv_tid_st0 [1:0] $end + $var wire 1 _: miss_resrv_valid_st0 $end + $var wire 2 e3! miss_resrv_wsel_st0 [1:0] $end + $var wire 1 K@ mrvq_init_ready_state $end + $var wire 1 9K mrvq_pop $end + $var wire 1 1K mrvq_push $end + $var wire 1 o: pending_hazard $end + $var wire 1 YK qual_mrvq_init $end + $var wire 16 9Q! ready_table [15:0] $end + $var wire 1 AK recover_state $end + $var wire 1 [h" reset $end + $var wire 4 AQ! schedule_ptr [3:0] $end + $var wire 5 YQ! size [4:0] $end + $var wire 4 QQ! tail_ptr [3:0] $end + $var wire 1 QK update_ready $end + $var wire 16 )K valid_address_match [15:0] $end + $var wire 16 1Q! valid_table [15:0] $end + $upscope $end + $scope module core_req_arb $end + $var wire 32 )o" CORE_TAG_ID_BITS [31:0] $end + $var wire 32 !o" CORE_TAG_WIDTH [31:0] $end + $var wire 32 on" CREQ_SIZE [31:0] $end + $var wire 32 on" NUM_REQUESTS [31:0] $end + $var wire 32 on" WORD_SIZE [31:0] $end + $var wire 120 {h" bank_addr [119:0] $end + $var wire 16 sh" bank_byteen [15:0] $end + $var wire 4 kh" bank_rw [3:0] $end + $var wire 42 ]i" bank_tag [41:0] $end + $var wire 4 C bank_valids [3:0] $end + $var wire 128 =i" bank_writedata [127:0] $end + $var wire 1 Sh" clk $end + $var wire 1 eC! o_empty $end + $var wire 1 YC out_empty $end + $var wire 120 gB out_per_addr [119:0] $end + $var wire 16 _B out_per_byteen [15:0] $end + $var wire 4 WB out_per_rw [3:0] $end + $var wire 42 IC out_per_tag [41:0] $end + $var wire 4 OB out_per_valids [3:0] $end + $var wire 128 )C out_per_writedata [127:0] $end + $var wire 1 aC pop_qual $end + $var wire 1 O* push_qual $end + $var wire 120 %C! qual_addr [119:0] $end + $var wire 16 {B! qual_byteen [15:0] $end + $var wire 1 ': qual_has_request $end + $var wire 2 /: qual_request_index [1:0] $end + $var wire 4 sB! qual_rw [3:0] $end + $var wire 42 53! qual_tag [41:0] $end + $var wire 4 kB! qual_valids [3:0] $end + $var wire 128 EC! qual_writedata [127:0] $end + $var wire 4 iC real_out_per_valids [3:0] $end + $var wire 1 }9 reqq_empty $end + $var wire 1 -3! reqq_full $end + $var wire 1 u9 reqq_pop $end + $var wire 1 7* reqq_push $end + $var wire 30 G: reqq_req_addr_st0 [29:0] $end + $var wire 4 ?: reqq_req_byteen_st0 [3:0] $end + $var wire 1 7: reqq_req_rw_st0 $end + $var wire 1 ': reqq_req_st0 $end + $var wire 42 53! reqq_req_tag_st0 [41:0] $end + $var wire 2 /: reqq_req_tid_st0 [1:0] $end + $var wire 32 O: reqq_req_writedata_st0 [31:0] $end + $var wire 1 [h" reset $end + $var wire 1 mC! use_empty $end + $var wire 120 %C! use_per_addr [119:0] $end + $var wire 16 {B! use_per_byteen [15:0] $end + $var wire 4 sB! use_per_rw [3:0] $end + $var wire 42 53! use_per_tag [41:0] $end + $var wire 4 kB! use_per_valids [3:0] $end + $var wire 128 EC! use_per_writedata [127:0] $end + $scope module reqq_queue $end + $var wire 32 wn" BUFFERED_OUTPUT [31:0] $end + $var wire 32 yo" DATAW [31:0] $end + $var wire 32 on" SIZE [31:0] $end + $var wire 1 Sh" clk $end + $var wire 314 w" data_in [313:0] $end + $var wire 314 qC data_out [313:0] $end + $var wire 1 eC! empty $end + $var wire 1 -3! full $end + $var wire 1 aC pop $end + $var wire 1 O* push $end + $var wire 1 cD reading $end + $var wire 1 [h" reset $end + $var wire 3 uC! size [2:0] $end + $var wire 3 uC! size_r [2:0] $end + $var wire 1 i# writing $end + $scope module genblk3 $end + $var wire 314 }C! data(0) [313:0] $end + $var wire 314 )D! data(1) [313:0] $end + $var wire 314 3D! data(2) [313:0] $end + $var wire 314 =D! data(3) [313:0] $end + $scope module genblk2 $end + $var wire 1 AI! bypass_r $end + $var wire 314 7H! curr_r [313:0] $end + $var wire 1 eC! empty_r $end + $var wire 1 -3! full_r $end + $var wire 314 EG! head_r [313:0] $end + $var wire 2 9I! rd_ptr_next_r [1:0] $end + $var wire 2 1I! rd_ptr_r [1:0] $end + $var wire 2 )I! wr_ptr_r [1:0] $end + $upscope $end + $upscope $end + $upscope $end + $scope module sel_bank $end + $var wire 32 on" N [31:0] $end + $var wire 1 Sh" clk $end + $var wire 2 /: grant_index [1:0] $end + $var wire 4 kD grant_onehot [3:0] $end + $var wire 1 ': grant_valid $end + $var wire 4 kB! requests [3:0] $end + $var wire 1 [h" reset $end + $scope module genblk2 $end + $var wire 4 kD grant_onehot_r [3:0] $end + $scope module priority_encoder $end + $var wire 32 on" N [31:0] $end + $var wire 4 kB! data_in [3:0] $end + $var wire 2 /: data_out [1:0] $end + $var wire 32 sD i [31:0] $end + $var wire 1 ': valid_out $end + $upscope $end + $upscope $end + $upscope $end + $upscope $end + $scope module cwb_queue $end + $var wire 32 wn" BUFFERED_OUTPUT [31:0] $end + $var wire 32 ;p" DATAW [31:0] $end + $var wire 32 on" SIZE [31:0] $end + $var wire 1 Sh" clk $end + $var wire 76 aK data_in [75:0] $end + $var wire 76 yK data_out [75:0] $end + $var wire 1 [6! empty $end + $var wire 1 c6! full $end + $var wire 1 ?* pop $end + $var wire 1 {@ push $end + $var wire 1 q# reading $end + $var wire 1 [h" reset $end + $var wire 3 iQ! size [2:0] $end + $var wire 3 iQ! size_r [2:0] $end + $var wire 1 3L writing $end + $scope module genblk3 $end + $var wire 76 qQ! data(0) [75:0] $end + $var wire 76 tQ! data(1) [75:0] $end + $var wire 76 wQ! data(2) [75:0] $end + $var wire 76 zQ! data(3) [75:0] $end + $scope module genblk2 $end + $var wire 1 ]S! bypass_r $end + $var wire 76 -S! curr_r [75:0] $end + $var wire 1 [6! empty_r $end + $var wire 1 c6! full_r $end + $var wire 76 sR! head_r [75:0] $end + $var wire 2 US! rd_ptr_next_r [1:0] $end + $var wire 2 MS! rd_ptr_r [1:0] $end + $var wire 2 ES! wr_ptr_r [1:0] $end + $upscope $end + $upscope $end + $upscope $end + $scope module dfp_queue $end + $var wire 32 wn" BUFFERED_OUTPUT [31:0] $end + $var wire 32 qo" DATAW [31:0] $end + $var wire 32 gn" SIZE [31:0] $end + $var wire 1 Sh" clk $end + $var wire 154 G" data_in [153:0] $end + $var wire 154 }A data_out [153:0] $end + $var wire 1 {2! empty $end + $var wire 1 %3! full $end + $var wire 1 E9 pop $end + $var wire 1 Um" push $end + $var wire 1 GB reading $end + $var wire 1 [h" reset $end + $var wire 5 c:! size [4:0] $end + $var wire 5 c:! size_r [4:0] $end + $var wire 1 o" writing $end + $scope module genblk3 $end + $var wire 154 k:! data(0) [153:0] $end + $var wire 154 p:! data(1) [153:0] $end + $var wire 154 ?;! data(10) [153:0] $end + $var wire 154 D;! data(11) [153:0] $end + $var wire 154 I;! data(12) [153:0] $end + $var wire 154 N;! data(13) [153:0] $end + $var wire 154 S;! data(14) [153:0] $end + $var wire 154 X;! data(15) [153:0] $end + $var wire 154 u:! data(2) [153:0] $end + $var wire 154 z:! data(3) [153:0] $end + $var wire 154 !;! data(4) [153:0] $end + $var wire 154 &;! data(5) [153:0] $end + $var wire 154 +;! data(6) [153:0] $end + $var wire 154 0;! data(7) [153:0] $end + $var wire 154 5;! data(8) [153:0] $end + $var wire 154 :;! data(9) [153:0] $end + $scope module genblk2 $end + $var wire 1 cB! bypass_r $end + $var wire 154 #B! curr_r [153:0] $end + $var wire 1 {2! empty_r $end + $var wire 1 %3! full_r $end + $var wire 154 YA! head_r [153:0] $end + $var wire 4 [B! rd_ptr_next_r [3:0] $end + $var wire 4 SB! rd_ptr_r [3:0] $end + $var wire 4 KB! wr_ptr_r [3:0] $end + $upscope $end + $upscope $end + $upscope $end + $scope module dwb_queue $end + $var wire 32 wn" BUFFERED_OUTPUT [31:0] $end + $var wire 32 Cp" DATAW [31:0] $end + $var wire 32 on" SIZE [31:0] $end + $var wire 1 Sh" clk $end + $var wire 200 ;L data_in [199:0] $end + $var wire 200 sL data_out [199:0] $end + $var wire 1 k6! empty $end + $var wire 1 s6! full $end + $var wire 1 G* pop $end + $var wire 1 5A push $end + $var wire 1 y# reading $end + $var wire 1 [h" reset $end + $var wire 3 eS! size [2:0] $end + $var wire 3 eS! size_r [2:0] $end + $var wire 1 MM writing $end + $scope module genblk3 $end + $var wire 200 mS! data(0) [199:0] $end + $var wire 200 tS! data(1) [199:0] $end + $var wire 200 {S! data(2) [199:0] $end + $var wire 200 $T! data(3) [199:0] $end + $scope module genblk2 $end + $var wire 1 ]W! bypass_r $end + $var wire 200 kV! curr_r [199:0] $end + $var wire 1 k6! empty_r $end + $var wire 1 s6! full_r $end + $var wire 200 3V! head_r [199:0] $end + $var wire 2 UW! rd_ptr_next_r [1:0] $end + $var wire 2 MW! rd_ptr_r [1:0] $end + $var wire 2 EW! wr_ptr_r [1:0] $end + $upscope $end + $upscope $end + $upscope $end + $scope module s0_1_c0 $end + $var wire 32 #p" N [31:0] $end + $var wire 32 Wn" PASSTHRU [31:0] $end + $var wire 1 Sh" clk $end + $var wire 1 Io" flush $end + $var wire 243 {D in [242:0] $end + $var wire 243 II! out [242:0] $end + $var wire 1 [h" reset $end + $var wire 1 Q; stall $end + $var wire 243 II! value [242:0] $end + $upscope $end + $scope module snp_req_queue $end + $var wire 32 wn" BUFFERED_OUTPUT [31:0] $end + $var wire 32 io" DATAW [31:0] $end + $var wire 32 gn" SIZE [31:0] $end + $var wire 1 Sh" clk $end + $var wire 55 /" data_in [54:0] $end + $var wire 55 eA data_out [54:0] $end + $var wire 1 k2! empty $end + $var wire 1 s2! full $end + $var wire 1 %9 pop $end + $var wire 1 em" push $end + $var wire 1 uA reading $end + $var wire 1 [h" reset $end + $var wire 5 57! size [4:0] $end + $var wire 5 57! size_r [4:0] $end + $var wire 1 ?" writing $end + $scope module genblk3 $end + $var wire 55 =7! data(0) [54:0] $end + $var wire 55 ?7! data(1) [54:0] $end + $var wire 55 Q7! data(10) [54:0] $end + $var wire 55 S7! data(11) [54:0] $end + $var wire 55 U7! data(12) [54:0] $end + $var wire 55 W7! data(13) [54:0] $end + $var wire 55 Y7! data(14) [54:0] $end + $var wire 55 [7! data(15) [54:0] $end + $var wire 55 A7! data(2) [54:0] $end + $var wire 55 C7! data(3) [54:0] $end + $var wire 55 E7! data(4) [54:0] $end + $var wire 55 G7! data(5) [54:0] $end + $var wire 55 I7! data(6) [54:0] $end + $var wire 55 K7! data(7) [54:0] $end + $var wire 55 M7! data(8) [54:0] $end + $var wire 55 O7! data(9) [54:0] $end + $scope module genblk2 $end + $var wire 1 [:! bypass_r $end + $var wire 55 3:! curr_r [54:0] $end + $var wire 1 k2! empty_r $end + $var wire 1 s2! full_r $end + $var wire 55 #:! head_r [54:0] $end + $var wire 4 S:! rd_ptr_next_r [3:0] $end + $var wire 4 K:! rd_ptr_r [3:0] $end + $var wire 4 C:! wr_ptr_r [3:0] $end + $upscope $end + $upscope $end + $upscope $end + $scope module st_1e_2 $end + $var wire 32 3p" N [31:0] $end + $var wire 32 Wn" PASSTHRU [31:0] $end + $var wire 1 Sh" clk $end + $var wire 1 Io" flush $end + $var wire 316 'J in [315:0] $end + $var wire 316 -K! out [315:0] $end + $var wire 1 [h" reset $end + $var wire 1 Q; stall $end + $var wire 316 -K! value [315:0] $end + $upscope $end + $scope module tag_data_access $end + $var wire 32 gn" BANK_LINE_SIZE [31:0] $end + $var wire 32 _n" CACHE_SIZE [31:0] $end + $var wire 32 wn" DRAM_ENABLE [31:0] $end + $var wire 32 on" NUM_BANKS [31:0] $end + $var wire 32 wn" STAGE_1_CYCLES [31:0] $end + $var wire 32 on" WORD_SIZE [31:0] $end + $var wire 32 wn" WRITE_ENABLE [31:0] $end + $var wire 1 Sh" clk $end + $var wire 128 yG data_write [127:0] $end + $var wire 1 w> dirty_st1e $end + $var wire 16 !? dirtyb_st1e [15:0] $end + $var wire 1 Q? fill_saw_dirty_st1e $end + $var wire 1 o> fill_sent $end + $var wire 1 %I force_core_miss $end + $var wire 1 !; force_request_miss_st1e $end + $var wire 1 ;H invalidate_line $end + $var wire 1 Y? is_snp_st1e $end + $var wire 4 I? mem_byteen_st1e [3:0] $end + $var wire 1 A? mem_rw_st1e $end + $var wire 1 o> miss_st1e $end + $var wire 1 q? mrvq_init_ready_state_st1e $end + $var wire 128 AG qual_read_data_st1 [127:0] $end + $var wire 1 )G qual_read_dirty_st1 $end + $var wire 16 1G qual_read_dirtyb_st1 [15:0] $end + $var wire 20 9G qual_read_tag_st1 [19:0] $end + $var wire 1 !G qual_read_valid_st1 $end + $var wire 128 _F read_data_st1c(0) [127:0] $end + $var wire 1 GF read_dirty_st1c(0) $end + $var wire 16 OF read_dirtyb_st1c(0) [15:0] $end + $var wire 20 WF read_tag_st1c(0) [19:0] $end + $var wire 1 ?F read_valid_st1c(0) $end + $var wire 6 ]E readaddr_st10 [5:0] $end + $var wire 128 G> readdata_st1e [127:0] $end + $var wire 20 g> readtag_st1e [19:0] $end + $var wire 32 ?> readword_st1e [31:0] $end + $var wire 1 {H real_miss $end + $var wire 1 KH real_writefill $end + $var wire 1 kH req_invalid $end + $var wire 1 sH req_miss $end + $var wire 1 [h" reset $end + $var wire 1 cH should_write $end + $var wire 1 ;H snoop_hit_no_pending $end + $var wire 1 a? snp_invalidate_st1e $end + $var wire 1 i? snp_to_mrvq_st1e $end + $var wire 1 Q; stall $end + $var wire 1 Q; stall_bank_pipe $end + $var wire 1 CH tags_match $end + $var wire 128 G> use_read_data_st1e [127:0] $end + $var wire 1 iG use_read_dirty_st1e $end + $var wire 16 !? use_read_dirtyb_st1e [15:0] $end + $var wire 20 g> use_read_tag_st1e [19:0] $end + $var wire 1 aG use_read_valid_st1e $end + $var wire 128 yG use_write_data [127:0] $end + $var wire 16 qG use_write_enable [15:0] $end + $var wire 1 #@ valid_req_st1e $end + $var wire 16 [H we [15:0] $end + $var wire 2 7F wordsel_st1e [1:0] $end + $var wire 26 ;@ writeaddr_st1e [25:0] $end + $var wire 128 uE writedata_st1e [127:0] $end + $var wire 1 eE writefill_st1e $end + $var wire 6 ]E writeladdr_st1e [5:0] $end + $var wire 20 SH writetag_st1e [19:0] $end + $var wire 32 mE writeword_st1e [31:0] $end + $scope module genblk4(0) $end + $var wire 1 -I normal_write $end + $upscope $end + $scope module genblk4(1) $end + $var wire 1 5I normal_write $end + $upscope $end + $scope module genblk4(2) $end + $var wire 1 =I normal_write $end + $upscope $end + $scope module genblk4(3) $end + $var wire 1 EI normal_write $end + $upscope $end + $scope module s0_1_c0 $end + $var wire 32 +p" N [31:0] $end + $var wire 32 wn" PASSTHRU [31:0] $end + $var wire 1 Sh" clk $end + $var wire 1 Io" flush $end + $var wire 166 UI in [165:0] $end + $var wire 166 UI out [165:0] $end + $var wire 1 [h" reset $end + $var wire 1 Q; stall $end + $var wire 166 [J! value [165:0] $end + $upscope $end + $scope module tag_data_structure $end + $var wire 32 gn" BANK_LINE_SIZE [31:0] $end + $var wire 32 _n" CACHE_SIZE [31:0] $end + $var wire 32 on" NUM_BANKS [31:0] $end + $var wire 32 on" WORD_SIZE [31:0] $end + $var wire 1 Sh" clk $end + $var wire 64 +J! dirty [63:0] $end + $var wire 1 MI do_write $end + $var wire 1 o> fill_sent $end + $var wire 32 KJ! i [31:0] $end + $var wire 1 ;H invalidate $end + $var wire 32 SJ! j [31:0] $end + $var wire 6 ]E read_addr [5:0] $end + $var wire 128 AG read_data [127:0] $end + $var wire 1 )G read_dirty $end + $var wire 16 1G read_dirtyb [15:0] $end + $var wire 20 9G read_tag [19:0] $end + $var wire 1 !G read_valid $end + $var wire 1 [h" reset $end + $var wire 1 Q; stall_bank_pipe $end + $var wire 20 SH tag_index [19:0] $end + $var wire 64 ;J! valid [63:0] $end + $var wire 6 ]E write_addr [5:0] $end + $var wire 128 yG write_data [127:0] $end + $var wire 16 qG write_enable [15:0] $end + $var wire 1 KH write_fill $end + $upscope $end + $upscope $end + $upscope $end + $upscope $end + $scope module genblk5(1) $end + $var wire 120 {h" curr_bank_core_req_addr [119:0] $end + $var wire 16 sh" curr_bank_core_req_byteen [15:0] $end + $var wire 128 =i" curr_bank_core_req_data [127:0] $end + $var wire 1 y-! curr_bank_core_req_ready $end + $var wire 4 kh" curr_bank_core_req_rw [3:0] $end + $var wire 42 ]i" curr_bank_core_req_tag [41:0] $end + $var wire 4 c curr_bank_core_req_valid [3:0] $end + $var wire 32 {0 curr_bank_core_rsp_data [31:0] $end + $var wire 1 k curr_bank_core_rsp_ready $end + $var wire 42 %1 curr_bank_core_rsp_tag [41:0] $end + $var wire 2 s0 curr_bank_core_rsp_tid [1:0] $end + $var wire 1 Y-! curr_bank_core_rsp_valid $end + $var wire 26 i-! curr_bank_dram_fill_req_addr [25:0] $end + $var wire 1 )-! curr_bank_dram_fill_req_ready $end + $var wire 1 51 curr_bank_dram_fill_req_valid $end + $var wire 26 ]m" curr_bank_dram_fill_rsp_addr [25:0] $end + $var wire 128 Qk" curr_bank_dram_fill_rsp_data [127:0] $end + $var wire 1 a-! curr_bank_dram_fill_rsp_ready $end + $var wire 1 um" curr_bank_dram_fill_rsp_valid $end + $var wire 26 M1 curr_bank_dram_wb_req_addr [25:0] $end + $var wire 16 E1 curr_bank_dram_wb_req_byteen [15:0] $end + $var wire 128 U1 curr_bank_dram_wb_req_data [127:0] $end + $var wire 1 s curr_bank_dram_wb_req_ready $end + $var wire 1 =1 curr_bank_dram_wb_req_valid $end + $var wire 26 mm" curr_bank_snp_req_addr [25:0] $end + $var wire 1 3l" curr_bank_snp_req_invalidate $end + $var wire 1 q-! curr_bank_snp_req_ready $end + $var wire 28 ;l" curr_bank_snp_req_tag [27:0] $end + $var wire 1 }m" curr_bank_snp_req_valid $end + $var wire 1 { curr_bank_snp_rsp_ready $end + $var wire 28 }1 curr_bank_snp_rsp_tag [27:0] $end + $var wire 1 u1 curr_bank_snp_rsp_valid $end + $scope module bank $end + $var wire 32 ao" BANK_ID [31:0] $end + $var wire 32 gn" BANK_LINE_SIZE [31:0] $end + $var wire 32 Wn" CACHE_ID [31:0] $end + $var wire 32 _n" CACHE_SIZE [31:0] $end + $var wire 32 )o" CORE_TAG_ID_BITS [31:0] $end + $var wire 32 !o" CORE_TAG_WIDTH [31:0] $end + $var wire 32 on" CREQ_SIZE [31:0] $end + $var wire 32 on" CWBQ_SIZE [31:0] $end + $var wire 32 gn" DFPQ_SIZE [31:0] $end + $var wire 32 on" DFQQ_SIZE [31:0] $end + $var wire 32 wn" DRAM_ENABLE [31:0] $end + $var wire 32 on" DWBQ_SIZE [31:0] $end + $var wire 32 gn" MRVQ_SIZE [31:0] $end + $var wire 32 on" NUM_BANKS [31:0] $end + $var wire 32 on" NUM_REQUESTS [31:0] $end + $var wire 32 Wn" SNOOP_FORWARDING [31:0] $end + $var wire 32 1o" SNP_REQ_TAG_WIDTH [31:0] $end + $var wire 32 gn" SNRQ_SIZE [31:0] $end + $var wire 32 wn" STAGE_1_CYCLES [31:0] $end + $var wire 32 on" WORD_SIZE [31:0] $end + $var wire 32 wn" WRITE_ENABLE [31:0] $end + $var wire 26 mQ addr_st1(0) [25:0] $end + $var wire 26 kT addr_st1e [25:0] $end + $var wire 26 i-! addr_st2 [25:0] $end + $var wire 1 Sh" clk $end + $var wire 120 {h" core_req_addr [119:0] $end + $var wire 16 sh" core_req_byteen [15:0] $end + $var wire 128 =i" core_req_data [127:0] $end + $var wire 1 y-! core_req_ready $end + $var wire 4 kh" core_req_rw [3:0] $end + $var wire 42 ]i" core_req_tag [41:0] $end + $var wire 4 c core_req_valid [3:0] $end + $var wire 32 {0 core_rsp_data [31:0] $end + $var wire 1 k core_rsp_ready $end + $var wire 42 %1 core_rsp_tag [41:0] $end + $var wire 2 s0 core_rsp_tid [1:0] $end + $var wire 1 Y-! core_rsp_valid $end + $var wire 32 #Z! cwbq_data [31:0] $end + $var wire 1 U[! cwbq_empty $end + $var wire 1 ][! cwbq_full $end + $var wire 1 _* cwbq_pop $end + $var wire 1 MU cwbq_push $end + $var wire 1 iO cwbq_push_stall $end + $var wire 1 UU cwbq_push_unqual $end + $var wire 42 AY! cwbq_tag [41:0] $end + $var wire 2 9Y! cwbq_tid [1:0] $end + $var wire 26 }M dfpq_addr_st0 [25:0] $end + $var wire 1 uW! dfpq_empty $end + $var wire 128 'N dfpq_filldata_st0 [127:0] $end + $var wire 1 }W! dfpq_full $end + $var wire 1 uM dfpq_pop $end + $var wire 1 CP dfpq_pop_unqual $end + $var wire 1 IS dirty_st1e $end + $var wire 1 SZ! dirty_st2 $end + $var wire 16 QS dirtyb_st1e [15:0] $end + $var wire 16 [Z! dirtyb_st2 [15:0] $end + $var wire 26 i-! dram_fill_req_addr [25:0] $end + $var wire 1 5U dram_fill_req_fast $end + $var wire 1 )-! dram_fill_req_ready $end + $var wire 1 yO dram_fill_req_stall $end + $var wire 1 ]U dram_fill_req_unqual $end + $var wire 1 51 dram_fill_req_valid $end + $var wire 26 ]m" dram_fill_rsp_addr [25:0] $end + $var wire 128 Qk" dram_fill_rsp_data [127:0] $end + $var wire 1 a-! dram_fill_rsp_ready $end + $var wire 1 um" dram_fill_rsp_valid $end + $var wire 26 M1 dram_wb_req_addr [25:0] $end + $var wire 16 E1 dram_wb_req_byteen [15:0] $end + $var wire 128 U1 dram_wb_req_data [127:0] $end + $var wire 1 #$ dram_wb_req_fire $end + $var wire 1 s dram_wb_req_ready $end + $var wire 1 =1 dram_wb_req_valid $end + $var wire 1 '\! dwbq_dual_valid_sel $end + $var wire 1 e[! dwbq_empty $end + $var wire 1 m[! dwbq_full $end + $var wire 1 mU dwbq_is_dwb_in $end + $var wire 1 }U dwbq_is_dwb_out $end + $var wire 1 uU dwbq_is_snp_in $end + $var wire 1 'V dwbq_is_snp_out $end + $var wire 1 g* dwbq_pop $end + $var wire 1 eU dwbq_push $end + $var wire 1 qO dwbq_push_stall $end + $var wire 1 /V dwbq_push_unqual $end + $var wire 26 u[! dwbq_req_addr [25:0] $end + $var wire 1 #T fill_saw_dirty_st1e $end + $var wire 1 {Z! fill_saw_dirty_st2 $end + $var wire 1 QO force_request_miss_st1e $end + $var wire 1 ;P going_to_write_st1(0) $end + $var wire 49 'R inst_meta_st1(0) [48:0] $end + $var wire 49 cZ! inst_meta_st2 [48:0] $end + $var wire 1 +P is_fill_in_pipe $end + $var wire 1 3P is_fill_st1(0) $end + $var wire 1 aY! is_fill_st2 $end + $var wire 1 gR is_mrvq_st1(0) $end + $var wire 1 [T is_mrvq_st1e $end + $var wire 1 [T is_mrvq_st1e_st2 $end + $var wire 1 =[! is_mrvq_st2 $end + $var wire 1 WR is_snp_st1(0) $end + $var wire 1 +T is_snp_st1e $end + $var wire 1 %[! is_snp_st2 $end + $var wire 32 ao" j [31:0] $end + $var wire 4 yS mem_byteen_st1e [3:0] $end + $var wire 1 qS mem_rw_st1e $end + $var wire 1 =U miss_add $end + $var wire 26 i-! miss_add_addr [25:0] $end + $var wire 1 KT miss_add_because_miss $end + $var wire 1 5[! miss_add_because_pending $end + $var wire 4 YY! miss_add_byteen [3:0] $end + $var wire 32 yY! miss_add_data [31:0] $end + $var wire 1 EU miss_add_is_mrvq $end + $var wire 1 %[! miss_add_is_snp $end + $var wire 1 QY! miss_add_rw $end + $var wire 1 -[! miss_add_snp_invalidate $end + $var wire 42 AY! miss_add_tag [41:0] $end + $var wire 2 9Y! miss_add_tid [1:0] $end + $var wire 1 5U miss_add_unqual $end + $var wire 2 qY! miss_add_wsel [1:0] $end + $var wire 1 AS miss_st1e $end + $var wire 1 KZ! miss_st2 $end + $var wire 26 WX! mrvq_addr_st0 [25:0] $end + $var wire 4 !Y! mrvq_byteen_st0 [3:0] $end + $var wire 1 ?X! mrvq_full $end + $var wire 1 %U mrvq_init_ready_state_hazard_st0_st1 $end + $var wire 1 -U mrvq_init_ready_state_hazard_st1e_st1 $end + $var wire 1 CT mrvq_init_ready_state_st1e $end + $var wire 1 {T mrvq_init_ready_state_st2 $end + $var wire 1 M[! mrvq_init_ready_state_unqual_st2 $end + $var wire 1 )Y! mrvq_is_snp_st0 $end + $var wire 1 AO mrvq_pending_hazard_st1e $end + $var wire 1 )O mrvq_pop $end + $var wire 1 1O mrvq_pop_unqual $end + $var wire 1 aO mrvq_push_stall $end + $var wire 1 cT mrvq_recover_ready_state_st1e $end + $var wire 1 E[! mrvq_recover_ready_state_st2 $end + $var wire 1 9O mrvq_rw_st0 $end + $var wire 1 1Y! mrvq_snp_invalidate_st0 $end + $var wire 1 GX! mrvq_stop $end + $var wire 42 oX! mrvq_tag_st0 [41:0] $end + $var wire 2 OX! mrvq_tid_st0 [1:0] $end + $var wire 1 1O mrvq_valid_st0 $end + $var wire 32 gX! mrvq_writeword_st0 [31:0] $end + $var wire 2 _X! mrvq_wsel_st0 [1:0] $end + $var wire 26 cP qual_addr_st0 [25:0] $end + $var wire 1 MQ qual_going_to_write_st0 $end + $var wire 49 =Q qual_inst_meta_st0 [48:0] $end + $var wire 1 CP qual_is_fill_st0 $end + $var wire 1 1O qual_is_mrvq_st0 $end + $var wire 1 UQ qual_is_snp_st0 $end + $var wire 1 ]Q qual_snp_invalidate_st0 $end + $var wire 1 [P qual_valid_st0 $end + $var wire 1 sT qual_valid_st1e_2 $end + $var wire 128 {P qual_writedata_st0 [127:0] $end + $var wire 32 sP qual_writeword_st0 [31:0] $end + $var wire 2 kP qual_wsel_st0 [1:0] $end + $var wire 128 wR readdata_st1e [127:0] $end + $var wire 128 +Z! readdata_st2 [127:0] $end + $var wire 20 9S readtag_st1e [19:0] $end + $var wire 20 sZ! readtag_st2 [19:0] $end + $var wire 32 oR readword_st1e [31:0] $end + $var wire 32 #Z! readword_st2 [31:0] $end + $var wire 1 YO recover_mrvq_state_st2 $end + $var wire 1 ON reqq_empty $end + $var wire 1 'X! reqq_full $end + $var wire 1 GN reqq_pop $end + $var wire 1 KP reqq_pop_unqual $end + $var wire 1 W* reqq_push $end + $var wire 30 wN reqq_req_addr_st0 [29:0] $end + $var wire 4 oN reqq_req_byteen_st0 [3:0] $end + $var wire 1 gN reqq_req_rw_st0 $end + $var wire 1 WN reqq_req_st0 $end + $var wire 42 /X! reqq_req_tag_st0 [41:0] $end + $var wire 2 _N reqq_req_tid_st0 [1:0] $end + $var wire 32 !O reqq_req_writeword_st0 [31:0] $end + $var wire 1 [h" reset $end + $var wire 1 _R snp_invalidate_st1(0) $end + $var wire 1 3T snp_invalidate_st1e $end + $var wire 1 -[! snp_invalidate_st2 $end + $var wire 26 mm" snp_req_addr [25:0] $end + $var wire 1 3l" snp_req_invalidate $end + $var wire 1 q-! snp_req_ready $end + $var wire 28 ;l" snp_req_tag [27:0] $end + $var wire 1 }m" snp_req_valid $end + $var wire 1 +$ snp_rsp_fire $end + $var wire 1 { snp_rsp_ready $end + $var wire 28 }1 snp_rsp_tag [27:0] $end + $var wire 1 u1 snp_rsp_valid $end + $var wire 1 ;T snp_to_mrvq_st1e $end + $var wire 1 5[! snp_to_mrvq_st2 $end + $var wire 26 ]M snrq_addr_st0 [25:0] $end + $var wire 1 eW! snrq_empty $end + $var wire 1 mW! snrq_full $end + $var wire 1 eM snrq_invalidate_st0 $end + $var wire 1 UM snrq_pop $end + $var wire 1 SP snrq_pop_unqual $end + $var wire 28 mM snrq_tag_st0 [27:0] $end + $var wire 28 }[! snrq_tag_st2 [27:0] $end + $var wire 1 IO st2_pending_hazard_st1e $end + $var wire 1 #P stall_bank_pipe $end + $var wire 42 YS tag_st1e [41:0] $end + $var wire 2 iS tid_st1e [1:0] $end + $var wire 1 eQ valid_st1(0) $end + $var wire 1 ST valid_st1e $end + $var wire 1 iY! valid_st2 $end + $var wire 128 7R writedata_st1(0) [127:0] $end + $var wire 32 }Q writeword_st1(0) [31:0] $end + $var wire 32 yY! writeword_st2 [31:0] $end + $var wire 2 uQ wsel_st1(0) [1:0] $end + $var wire 2 qY! wsel_st2 [1:0] $end + $scope module cache_miss_resrv $end + $var wire 32 ao" BANK_ID [31:0] $end + $var wire 32 gn" BANK_LINE_SIZE [31:0] $end + $var wire 32 Wn" CACHE_ID [31:0] $end + $var wire 32 !o" CORE_TAG_WIDTH [31:0] $end + $var wire 32 gn" MRVQ_SIZE [31:0] $end + $var wire 32 on" NUM_BANKS [31:0] $end + $var wire 32 on" NUM_REQUESTS [31:0] $end + $var wire 32 1o" SNP_REQ_TAG_WIDTH [31:0] $end + $var wire 32 on" WORD_SIZE [31:0] $end + $var wire 416 !u! addr_table [415:0] $end + $var wire 1 Sh" clk $end + $var wire 4 ;v! dequeue_index [3:0] $end + $var wire 1 1O dequeue_possible $end + $var wire 4 Kv! enqueue_index [3:0] $end + $var wire 1 [v! enqueue_possible $end + $var wire 26 kT fill_addr_st1 [25:0] $end + $var wire 4 Cv! head_ptr [3:0] $end + $var wire 1 y_ increment_head $end + $var wire 1 7Z is_fill_st1 $end + $var wire 1 EU is_mrvq $end + $var wire 16 I_ make_ready [15:0] $end + $var wire 16 Q_ make_ready_push [15:0] $end + $var wire 85 wp! metadata_table(0) [84:0] $end + $var wire 85 zp! metadata_table(1) [84:0] $end + $var wire 85 7q! metadata_table(10) [84:0] $end + $var wire 85 :q! metadata_table(11) [84:0] $end + $var wire 85 =q! metadata_table(12) [84:0] $end + $var wire 85 @q! metadata_table(13) [84:0] $end + $var wire 85 Cq! metadata_table(14) [84:0] $end + $var wire 85 Fq! metadata_table(15) [84:0] $end + $var wire 85 }p! metadata_table(2) [84:0] $end + $var wire 85 "q! metadata_table(3) [84:0] $end + $var wire 85 %q! metadata_table(4) [84:0] $end + $var wire 85 (q! metadata_table(5) [84:0] $end + $var wire 85 +q! metadata_table(6) [84:0] $end + $var wire 85 .q! metadata_table(7) [84:0] $end + $var wire 85 1q! metadata_table(8) [84:0] $end + $var wire 85 4q! metadata_table(9) [84:0] $end + $var wire 1 =U miss_add $end + $var wire 26 i-! miss_add_addr [25:0] $end + $var wire 4 YY! miss_add_byteen [3:0] $end + $var wire 32 yY! miss_add_data [31:0] $end + $var wire 1 %[! miss_add_is_snp $end + $var wire 1 QY! miss_add_rw $end + $var wire 1 -[! miss_add_snp_invalidate $end + $var wire 42 AY! miss_add_tag [41:0] $end + $var wire 2 9Y! miss_add_tid [1:0] $end + $var wire 2 qY! miss_add_wsel [1:0] $end + $var wire 26 WX! miss_resrv_addr_st0 [25:0] $end + $var wire 4 !Y! miss_resrv_byteen_st0 [3:0] $end + $var wire 32 gX! miss_resrv_data_st0 [31:0] $end + $var wire 1 ?X! miss_resrv_full $end + $var wire 1 )Y! miss_resrv_is_snp_st0 $end + $var wire 1 )O miss_resrv_pop $end + $var wire 1 9O miss_resrv_rw_st0 $end + $var wire 1 1Y! miss_resrv_snp_invalidate_st0 $end + $var wire 1 GX! miss_resrv_stop $end + $var wire 42 oX! miss_resrv_tag_st0 [41:0] $end + $var wire 2 OX! miss_resrv_tid_st0 [1:0] $end + $var wire 1 1O miss_resrv_valid_st0 $end + $var wire 2 _X! miss_resrv_wsel_st0 [1:0] $end + $var wire 1 {T mrvq_init_ready_state $end + $var wire 1 i_ mrvq_pop $end + $var wire 1 a_ mrvq_push $end + $var wire 1 AO pending_hazard $end + $var wire 1 +` qual_mrvq_init $end + $var wire 16 3v! ready_table [15:0] $end + $var wire 1 q_ recover_state $end + $var wire 1 [h" reset $end + $var wire 4 ;v! schedule_ptr [3:0] $end + $var wire 5 Sv! size [4:0] $end + $var wire 4 Kv! tail_ptr [3:0] $end + $var wire 1 #` update_ready $end + $var wire 16 Y_ valid_address_match [15:0] $end + $var wire 16 +v! valid_table [15:0] $end + $upscope $end + $scope module core_req_arb $end + $var wire 32 )o" CORE_TAG_ID_BITS [31:0] $end + $var wire 32 !o" CORE_TAG_WIDTH [31:0] $end + $var wire 32 on" CREQ_SIZE [31:0] $end + $var wire 32 on" NUM_REQUESTS [31:0] $end + $var wire 32 on" WORD_SIZE [31:0] $end + $var wire 120 {h" bank_addr [119:0] $end + $var wire 16 sh" bank_byteen [15:0] $end + $var wire 4 kh" bank_rw [3:0] $end + $var wire 42 ]i" bank_tag [41:0] $end + $var wire 4 c bank_valids [3:0] $end + $var wire 128 =i" bank_writedata [127:0] $end + $var wire 1 Sh" clk $end + $var wire 1 _h! o_empty $end + $var wire 1 +X out_empty $end + $var wire 120 9W out_per_addr [119:0] $end + $var wire 16 1W out_per_byteen [15:0] $end + $var wire 4 )W out_per_rw [3:0] $end + $var wire 42 yW out_per_tag [41:0] $end + $var wire 4 !W out_per_valids [3:0] $end + $var wire 128 YW out_per_writedata [127:0] $end + $var wire 1 3X pop_qual $end + $var wire 1 o* push_qual $end + $var wire 120 }g! qual_addr [119:0] $end + $var wire 16 ug! qual_byteen [15:0] $end + $var wire 1 WN qual_has_request $end + $var wire 2 _N qual_request_index [1:0] $end + $var wire 4 mg! qual_rw [3:0] $end + $var wire 42 /X! qual_tag [41:0] $end + $var wire 4 eg! qual_valids [3:0] $end + $var wire 128 ?h! qual_writedata [127:0] $end + $var wire 4 ;X real_out_per_valids [3:0] $end + $var wire 1 ON reqq_empty $end + $var wire 1 'X! reqq_full $end + $var wire 1 GN reqq_pop $end + $var wire 1 W* reqq_push $end + $var wire 30 wN reqq_req_addr_st0 [29:0] $end + $var wire 4 oN reqq_req_byteen_st0 [3:0] $end + $var wire 1 gN reqq_req_rw_st0 $end + $var wire 1 WN reqq_req_st0 $end + $var wire 42 /X! reqq_req_tag_st0 [41:0] $end + $var wire 2 _N reqq_req_tid_st0 [1:0] $end + $var wire 32 !O reqq_req_writedata_st0 [31:0] $end + $var wire 1 [h" reset $end + $var wire 1 gh! use_empty $end + $var wire 120 }g! use_per_addr [119:0] $end + $var wire 16 ug! use_per_byteen [15:0] $end + $var wire 4 mg! use_per_rw [3:0] $end + $var wire 42 /X! use_per_tag [41:0] $end + $var wire 4 eg! use_per_valids [3:0] $end + $var wire 128 ?h! use_per_writedata [127:0] $end + $scope module reqq_queue $end + $var wire 32 wn" BUFFERED_OUTPUT [31:0] $end + $var wire 32 yo" DATAW [31:0] $end + $var wire 32 on" SIZE [31:0] $end + $var wire 1 Sh" clk $end + $var wire 314 {$ data_in [313:0] $end + $var wire 314 CX data_out [313:0] $end + $var wire 1 _h! empty $end + $var wire 1 'X! full $end + $var wire 1 3X pop $end + $var wire 1 o* push $end + $var wire 1 5Y reading $end + $var wire 1 [h" reset $end + $var wire 3 oh! size [2:0] $end + $var wire 3 oh! size_r [2:0] $end + $var wire 1 m% writing $end + $scope module genblk3 $end + $var wire 314 wh! data(0) [313:0] $end + $var wire 314 #i! data(1) [313:0] $end + $var wire 314 -i! data(2) [313:0] $end + $var wire 314 7i! data(3) [313:0] $end + $scope module genblk2 $end + $var wire 1 ;n! bypass_r $end + $var wire 314 1m! curr_r [313:0] $end + $var wire 1 _h! empty_r $end + $var wire 1 'X! full_r $end + $var wire 314 ?l! head_r [313:0] $end + $var wire 2 3n! rd_ptr_next_r [1:0] $end + $var wire 2 +n! rd_ptr_r [1:0] $end + $var wire 2 #n! wr_ptr_r [1:0] $end + $upscope $end + $upscope $end + $upscope $end + $scope module sel_bank $end + $var wire 32 on" N [31:0] $end + $var wire 1 Sh" clk $end + $var wire 2 _N grant_index [1:0] $end + $var wire 4 =Y grant_onehot [3:0] $end + $var wire 1 WN grant_valid $end + $var wire 4 eg! requests [3:0] $end + $var wire 1 [h" reset $end + $scope module genblk2 $end + $var wire 4 =Y grant_onehot_r [3:0] $end + $scope module priority_encoder $end + $var wire 32 on" N [31:0] $end + $var wire 4 eg! data_in [3:0] $end + $var wire 2 _N data_out [1:0] $end + $var wire 32 EY i [31:0] $end + $var wire 1 WN valid_out $end + $upscope $end + $upscope $end + $upscope $end + $upscope $end + $scope module cwb_queue $end + $var wire 32 wn" BUFFERED_OUTPUT [31:0] $end + $var wire 32 ;p" DATAW [31:0] $end + $var wire 32 on" SIZE [31:0] $end + $var wire 1 Sh" clk $end + $var wire 76 3` data_in [75:0] $end + $var wire 76 K` data_out [75:0] $end + $var wire 1 U[! empty $end + $var wire 1 ][! full $end + $var wire 1 _* pop $end + $var wire 1 MU push $end + $var wire 1 u% reading $end + $var wire 1 [h" reset $end + $var wire 3 cv! size [2:0] $end + $var wire 3 cv! size_r [2:0] $end + $var wire 1 c` writing $end + $scope module genblk3 $end + $var wire 76 kv! data(0) [75:0] $end + $var wire 76 nv! data(1) [75:0] $end + $var wire 76 qv! data(2) [75:0] $end + $var wire 76 tv! data(3) [75:0] $end + $scope module genblk2 $end + $var wire 1 Wx! bypass_r $end + $var wire 76 'x! curr_r [75:0] $end + $var wire 1 U[! empty_r $end + $var wire 1 ][! full_r $end + $var wire 76 mw! head_r [75:0] $end + $var wire 2 Ox! rd_ptr_next_r [1:0] $end + $var wire 2 Gx! rd_ptr_r [1:0] $end + $var wire 2 ?x! wr_ptr_r [1:0] $end + $upscope $end + $upscope $end + $upscope $end + $scope module dfp_queue $end + $var wire 32 wn" BUFFERED_OUTPUT [31:0] $end + $var wire 32 qo" DATAW [31:0] $end + $var wire 32 gn" SIZE [31:0] $end + $var wire 1 Sh" clk $end + $var wire 154 K$ data_in [153:0] $end + $var wire 154 OV data_out [153:0] $end + $var wire 1 uW! empty $end + $var wire 1 }W! full $end + $var wire 1 uM pop $end + $var wire 1 um" push $end + $var wire 1 wV reading $end + $var wire 1 [h" reset $end + $var wire 5 ]_! size [4:0] $end + $var wire 5 ]_! size_r [4:0] $end + $var wire 1 s$ writing $end + $scope module genblk3 $end + $var wire 154 e_! data(0) [153:0] $end + $var wire 154 j_! data(1) [153:0] $end + $var wire 154 9`! data(10) [153:0] $end + $var wire 154 >`! data(11) [153:0] $end + $var wire 154 C`! data(12) [153:0] $end + $var wire 154 H`! data(13) [153:0] $end + $var wire 154 M`! data(14) [153:0] $end + $var wire 154 R`! data(15) [153:0] $end + $var wire 154 o_! data(2) [153:0] $end + $var wire 154 t_! data(3) [153:0] $end + $var wire 154 y_! data(4) [153:0] $end + $var wire 154 ~_! data(5) [153:0] $end + $var wire 154 %`! data(6) [153:0] $end + $var wire 154 *`! data(7) [153:0] $end + $var wire 154 /`! data(8) [153:0] $end + $var wire 154 4`! data(9) [153:0] $end + $scope module genblk2 $end + $var wire 1 ]g! bypass_r $end + $var wire 154 {f! curr_r [153:0] $end + $var wire 1 uW! empty_r $end + $var wire 1 }W! full_r $end + $var wire 154 Sf! head_r [153:0] $end + $var wire 4 Ug! rd_ptr_next_r [3:0] $end + $var wire 4 Mg! rd_ptr_r [3:0] $end + $var wire 4 Eg! wr_ptr_r [3:0] $end + $upscope $end + $upscope $end + $upscope $end + $scope module dwb_queue $end + $var wire 32 wn" BUFFERED_OUTPUT [31:0] $end + $var wire 32 Cp" DATAW [31:0] $end + $var wire 32 on" SIZE [31:0] $end + $var wire 1 Sh" clk $end + $var wire 200 k` data_in [199:0] $end + $var wire 200 Ea data_out [199:0] $end + $var wire 1 e[! empty $end + $var wire 1 m[! full $end + $var wire 1 g* pop $end + $var wire 1 eU push $end + $var wire 1 }% reading $end + $var wire 1 [h" reset $end + $var wire 3 _x! size [2:0] $end + $var wire 3 _x! size_r [2:0] $end + $var wire 1 }a writing $end + $scope module genblk3 $end + $var wire 200 gx! data(0) [199:0] $end + $var wire 200 nx! data(1) [199:0] $end + $var wire 200 ux! data(2) [199:0] $end + $var wire 200 |x! data(3) [199:0] $end + $scope module genblk2 $end + $var wire 1 W|! bypass_r $end + $var wire 200 e{! curr_r [199:0] $end + $var wire 1 e[! empty_r $end + $var wire 1 m[! full_r $end + $var wire 200 -{! head_r [199:0] $end + $var wire 2 O|! rd_ptr_next_r [1:0] $end + $var wire 2 G|! rd_ptr_r [1:0] $end + $var wire 2 ?|! wr_ptr_r [1:0] $end + $upscope $end + $upscope $end + $upscope $end + $scope module s0_1_c0 $end + $var wire 32 #p" N [31:0] $end + $var wire 32 Wn" PASSTHRU [31:0] $end + $var wire 1 Sh" clk $end + $var wire 1 Io" flush $end + $var wire 243 MY in [242:0] $end + $var wire 243 Cn! out [242:0] $end + $var wire 1 [h" reset $end + $var wire 1 #P stall $end + $var wire 243 Cn! value [242:0] $end + $upscope $end + $scope module snp_req_queue $end + $var wire 32 wn" BUFFERED_OUTPUT [31:0] $end + $var wire 32 io" DATAW [31:0] $end + $var wire 32 gn" SIZE [31:0] $end + $var wire 1 Sh" clk $end + $var wire 55 3$ data_in [54:0] $end + $var wire 55 7V data_out [54:0] $end + $var wire 1 eW! empty $end + $var wire 1 mW! full $end + $var wire 1 UM pop $end + $var wire 1 }m" push $end + $var wire 1 GV reading $end + $var wire 1 [h" reset $end + $var wire 5 /\! size [4:0] $end + $var wire 5 /\! size_r [4:0] $end + $var wire 1 C$ writing $end + $scope module genblk3 $end + $var wire 55 7\! data(0) [54:0] $end + $var wire 55 9\! data(1) [54:0] $end + $var wire 55 K\! data(10) [54:0] $end + $var wire 55 M\! data(11) [54:0] $end + $var wire 55 O\! data(12) [54:0] $end + $var wire 55 Q\! data(13) [54:0] $end + $var wire 55 S\! data(14) [54:0] $end + $var wire 55 U\! data(15) [54:0] $end + $var wire 55 ;\! data(2) [54:0] $end + $var wire 55 =\! data(3) [54:0] $end + $var wire 55 ?\! data(4) [54:0] $end + $var wire 55 A\! data(5) [54:0] $end + $var wire 55 C\! data(6) [54:0] $end + $var wire 55 E\! data(7) [54:0] $end + $var wire 55 G\! data(8) [54:0] $end + $var wire 55 I\! data(9) [54:0] $end + $scope module genblk2 $end + $var wire 1 U_! bypass_r $end + $var wire 55 -_! curr_r [54:0] $end + $var wire 1 eW! empty_r $end + $var wire 1 mW! full_r $end + $var wire 55 {^! head_r [54:0] $end + $var wire 4 M_! rd_ptr_next_r [3:0] $end + $var wire 4 E_! rd_ptr_r [3:0] $end + $var wire 4 =_! wr_ptr_r [3:0] $end + $upscope $end + $upscope $end + $upscope $end + $scope module st_1e_2 $end + $var wire 32 3p" N [31:0] $end + $var wire 32 Wn" PASSTHRU [31:0] $end + $var wire 1 Sh" clk $end + $var wire 1 Io" flush $end + $var wire 316 W^ in [315:0] $end + $var wire 316 'p! out [315:0] $end + $var wire 1 [h" reset $end + $var wire 1 #P stall $end + $var wire 316 'p! value [315:0] $end + $upscope $end + $scope module tag_data_access $end + $var wire 32 gn" BANK_LINE_SIZE [31:0] $end + $var wire 32 _n" CACHE_SIZE [31:0] $end + $var wire 32 wn" DRAM_ENABLE [31:0] $end + $var wire 32 on" NUM_BANKS [31:0] $end + $var wire 32 wn" STAGE_1_CYCLES [31:0] $end + $var wire 32 on" WORD_SIZE [31:0] $end + $var wire 32 wn" WRITE_ENABLE [31:0] $end + $var wire 1 Sh" clk $end + $var wire 128 K\ data_write [127:0] $end + $var wire 1 IS dirty_st1e $end + $var wire 16 QS dirtyb_st1e [15:0] $end + $var wire 1 #T fill_saw_dirty_st1e $end + $var wire 1 AS fill_sent $end + $var wire 1 U] force_core_miss $end + $var wire 1 QO force_request_miss_st1e $end + $var wire 1 k\ invalidate_line $end + $var wire 1 +T is_snp_st1e $end + $var wire 4 yS mem_byteen_st1e [3:0] $end + $var wire 1 qS mem_rw_st1e $end + $var wire 1 AS miss_st1e $end + $var wire 1 CT mrvq_init_ready_state_st1e $end + $var wire 128 q[ qual_read_data_st1 [127:0] $end + $var wire 1 Y[ qual_read_dirty_st1 $end + $var wire 16 a[ qual_read_dirtyb_st1 [15:0] $end + $var wire 20 i[ qual_read_tag_st1 [19:0] $end + $var wire 1 Q[ qual_read_valid_st1 $end + $var wire 128 1[ read_data_st1c(0) [127:0] $end + $var wire 1 wZ read_dirty_st1c(0) $end + $var wire 16 ![ read_dirtyb_st1c(0) [15:0] $end + $var wire 20 )[ read_tag_st1c(0) [19:0] $end + $var wire 1 oZ read_valid_st1c(0) $end + $var wire 6 /Z readaddr_st10 [5:0] $end + $var wire 128 wR readdata_st1e [127:0] $end + $var wire 20 9S readtag_st1e [19:0] $end + $var wire 32 oR readword_st1e [31:0] $end + $var wire 1 M] real_miss $end + $var wire 1 {\ real_writefill $end + $var wire 1 =] req_invalid $end + $var wire 1 E] req_miss $end + $var wire 1 [h" reset $end + $var wire 1 5] should_write $end + $var wire 1 k\ snoop_hit_no_pending $end + $var wire 1 3T snp_invalidate_st1e $end + $var wire 1 ;T snp_to_mrvq_st1e $end + $var wire 1 #P stall $end + $var wire 1 #P stall_bank_pipe $end + $var wire 1 s\ tags_match $end + $var wire 128 wR use_read_data_st1e [127:0] $end + $var wire 1 ;\ use_read_dirty_st1e $end + $var wire 16 QS use_read_dirtyb_st1e [15:0] $end + $var wire 20 9S use_read_tag_st1e [19:0] $end + $var wire 1 3\ use_read_valid_st1e $end + $var wire 128 K\ use_write_data [127:0] $end + $var wire 16 C\ use_write_enable [15:0] $end + $var wire 1 ST valid_req_st1e $end + $var wire 16 -] we [15:0] $end + $var wire 2 gZ wordsel_st1e [1:0] $end + $var wire 26 kT writeaddr_st1e [25:0] $end + $var wire 128 GZ writedata_st1e [127:0] $end + $var wire 1 7Z writefill_st1e $end + $var wire 6 /Z writeladdr_st1e [5:0] $end + $var wire 20 %] writetag_st1e [19:0] $end + $var wire 32 ?Z writeword_st1e [31:0] $end + $scope module genblk4(0) $end + $var wire 1 ]] normal_write $end + $upscope $end + $scope module genblk4(1) $end + $var wire 1 e] normal_write $end + $upscope $end + $scope module genblk4(2) $end + $var wire 1 m] normal_write $end + $upscope $end + $scope module genblk4(3) $end + $var wire 1 u] normal_write $end + $upscope $end + $scope module s0_1_c0 $end + $var wire 32 +p" N [31:0] $end + $var wire 32 wn" PASSTHRU [31:0] $end + $var wire 1 Sh" clk $end + $var wire 1 Io" flush $end + $var wire 166 '^ in [165:0] $end + $var wire 166 '^ out [165:0] $end + $var wire 1 [h" reset $end + $var wire 1 #P stall $end + $var wire 166 Uo! value [165:0] $end + $upscope $end + $scope module tag_data_structure $end + $var wire 32 gn" BANK_LINE_SIZE [31:0] $end + $var wire 32 _n" CACHE_SIZE [31:0] $end + $var wire 32 on" NUM_BANKS [31:0] $end + $var wire 32 on" WORD_SIZE [31:0] $end + $var wire 1 Sh" clk $end + $var wire 64 %o! dirty [63:0] $end + $var wire 1 }] do_write $end + $var wire 1 AS fill_sent $end + $var wire 32 Eo! i [31:0] $end + $var wire 1 k\ invalidate $end + $var wire 32 Mo! j [31:0] $end + $var wire 6 /Z read_addr [5:0] $end + $var wire 128 q[ read_data [127:0] $end + $var wire 1 Y[ read_dirty $end + $var wire 16 a[ read_dirtyb [15:0] $end + $var wire 20 i[ read_tag [19:0] $end + $var wire 1 Q[ read_valid $end + $var wire 1 [h" reset $end + $var wire 1 #P stall_bank_pipe $end + $var wire 20 %] tag_index [19:0] $end + $var wire 64 5o! valid [63:0] $end + $var wire 6 /Z write_addr [5:0] $end + $var wire 128 K\ write_data [127:0] $end + $var wire 16 C\ write_enable [15:0] $end + $var wire 1 {\ write_fill $end + $upscope $end + $upscope $end + $upscope $end + $upscope $end + $scope module genblk5(2) $end + $var wire 120 {h" curr_bank_core_req_addr [119:0] $end + $var wire 16 sh" curr_bank_core_req_byteen [15:0] $end + $var wire 128 =i" curr_bank_core_req_data [127:0] $end + $var wire 1 C.! curr_bank_core_req_ready $end + $var wire 4 kh" curr_bank_core_req_rw [3:0] $end + $var wire 42 ]i" curr_bank_core_req_tag [41:0] $end + $var wire 4 %! curr_bank_core_req_valid [3:0] $end + $var wire 32 /2 curr_bank_core_rsp_data [31:0] $end + $var wire 1 -! curr_bank_core_rsp_ready $end + $var wire 42 72 curr_bank_core_rsp_tag [41:0] $end + $var wire 2 '2 curr_bank_core_rsp_tid [1:0] $end + $var wire 1 #.! curr_bank_core_rsp_valid $end + $var wire 26 3.! curr_bank_dram_fill_req_addr [25:0] $end + $var wire 1 )-! curr_bank_dram_fill_req_ready $end + $var wire 1 G2 curr_bank_dram_fill_req_valid $end + $var wire 26 ]m" curr_bank_dram_fill_rsp_addr [25:0] $end + $var wire 128 Qk" curr_bank_dram_fill_rsp_data [127:0] $end + $var wire 1 +.! curr_bank_dram_fill_rsp_ready $end + $var wire 1 'n" curr_bank_dram_fill_rsp_valid $end + $var wire 26 _2 curr_bank_dram_wb_req_addr [25:0] $end + $var wire 16 W2 curr_bank_dram_wb_req_byteen [15:0] $end + $var wire 128 g2 curr_bank_dram_wb_req_data [127:0] $end + $var wire 1 5! curr_bank_dram_wb_req_ready $end + $var wire 1 O2 curr_bank_dram_wb_req_valid $end + $var wire 26 mm" curr_bank_snp_req_addr [25:0] $end + $var wire 1 3l" curr_bank_snp_req_invalidate $end + $var wire 1 ;.! curr_bank_snp_req_ready $end + $var wire 28 ;l" curr_bank_snp_req_tag [27:0] $end + $var wire 1 /n" curr_bank_snp_req_valid $end + $var wire 1 =! curr_bank_snp_rsp_ready $end + $var wire 28 13 curr_bank_snp_rsp_tag [27:0] $end + $var wire 1 )3 curr_bank_snp_rsp_valid $end + $scope module bank $end + $var wire 32 Kp" BANK_ID [31:0] $end + $var wire 32 gn" BANK_LINE_SIZE [31:0] $end + $var wire 32 Wn" CACHE_ID [31:0] $end + $var wire 32 _n" CACHE_SIZE [31:0] $end + $var wire 32 )o" CORE_TAG_ID_BITS [31:0] $end + $var wire 32 !o" CORE_TAG_WIDTH [31:0] $end + $var wire 32 on" CREQ_SIZE [31:0] $end + $var wire 32 on" CWBQ_SIZE [31:0] $end + $var wire 32 gn" DFPQ_SIZE [31:0] $end + $var wire 32 on" DFQQ_SIZE [31:0] $end + $var wire 32 wn" DRAM_ENABLE [31:0] $end + $var wire 32 on" DWBQ_SIZE [31:0] $end + $var wire 32 gn" MRVQ_SIZE [31:0] $end + $var wire 32 on" NUM_BANKS [31:0] $end + $var wire 32 on" NUM_REQUESTS [31:0] $end + $var wire 32 Wn" SNOOP_FORWARDING [31:0] $end + $var wire 32 1o" SNP_REQ_TAG_WIDTH [31:0] $end + $var wire 32 gn" SNRQ_SIZE [31:0] $end + $var wire 32 wn" STAGE_1_CYCLES [31:0] $end + $var wire 32 on" WORD_SIZE [31:0] $end + $var wire 32 wn" WRITE_ENABLE [31:0] $end + $var wire 26 ?f addr_st1(0) [25:0] $end + $var wire 26 =i addr_st1e [25:0] $end + $var wire 26 3.! addr_st2 [25:0] $end + $var wire 1 Sh" clk $end + $var wire 120 {h" core_req_addr [119:0] $end + $var wire 16 sh" core_req_byteen [15:0] $end + $var wire 128 =i" core_req_data [127:0] $end + $var wire 1 C.! core_req_ready $end + $var wire 4 kh" core_req_rw [3:0] $end + $var wire 42 ]i" core_req_tag [41:0] $end + $var wire 4 %! core_req_valid [3:0] $end + $var wire 32 /2 core_rsp_data [31:0] $end + $var wire 1 -! core_rsp_ready $end + $var wire 42 72 core_rsp_tag [41:0] $end + $var wire 2 '2 core_rsp_tid [1:0] $end + $var wire 1 #.! core_rsp_valid $end + $var wire 32 {~! cwbq_data [31:0] $end + $var wire 1 O"" cwbq_empty $end + $var wire 1 W"" cwbq_full $end + $var wire 1 !+ cwbq_pop $end + $var wire 1 }i cwbq_push $end + $var wire 1 ;d cwbq_push_stall $end + $var wire 1 'j cwbq_push_unqual $end + $var wire 42 ;~! cwbq_tag [41:0] $end + $var wire 2 3~! cwbq_tid [1:0] $end + $var wire 26 Ob dfpq_addr_st0 [25:0] $end + $var wire 1 o|! dfpq_empty $end + $var wire 128 Wb dfpq_filldata_st0 [127:0] $end + $var wire 1 w|! dfpq_full $end + $var wire 1 Gb dfpq_pop $end + $var wire 1 sd dfpq_pop_unqual $end + $var wire 1 yg dirty_st1e $end + $var wire 1 M!" dirty_st2 $end + $var wire 16 #h dirtyb_st1e [15:0] $end + $var wire 16 U!" dirtyb_st2 [15:0] $end + $var wire 26 3.! dram_fill_req_addr [25:0] $end + $var wire 1 ei dram_fill_req_fast $end + $var wire 1 )-! dram_fill_req_ready $end + $var wire 1 Kd dram_fill_req_stall $end + $var wire 1 /j dram_fill_req_unqual $end + $var wire 1 G2 dram_fill_req_valid $end + $var wire 26 ]m" dram_fill_rsp_addr [25:0] $end + $var wire 128 Qk" dram_fill_rsp_data [127:0] $end + $var wire 1 +.! dram_fill_rsp_ready $end + $var wire 1 'n" dram_fill_rsp_valid $end + $var wire 26 _2 dram_wb_req_addr [25:0] $end + $var wire 16 W2 dram_wb_req_byteen [15:0] $end + $var wire 128 g2 dram_wb_req_data [127:0] $end + $var wire 1 '& dram_wb_req_fire $end + $var wire 1 5! dram_wb_req_ready $end + $var wire 1 O2 dram_wb_req_valid $end + $var wire 1 !#" dwbq_dual_valid_sel $end + $var wire 1 _"" dwbq_empty $end + $var wire 1 g"" dwbq_full $end + $var wire 1 ?j dwbq_is_dwb_in $end + $var wire 1 Oj dwbq_is_dwb_out $end + $var wire 1 Gj dwbq_is_snp_in $end + $var wire 1 Wj dwbq_is_snp_out $end + $var wire 1 )+ dwbq_pop $end + $var wire 1 7j dwbq_push $end + $var wire 1 Cd dwbq_push_stall $end + $var wire 1 _j dwbq_push_unqual $end + $var wire 26 o"" dwbq_req_addr [25:0] $end + $var wire 1 Sh fill_saw_dirty_st1e $end + $var wire 1 u!" fill_saw_dirty_st2 $end + $var wire 1 #d force_request_miss_st1e $end + $var wire 1 kd going_to_write_st1(0) $end + $var wire 49 Wf inst_meta_st1(0) [48:0] $end + $var wire 49 ]!" inst_meta_st2 [48:0] $end + $var wire 1 [d is_fill_in_pipe $end + $var wire 1 cd is_fill_st1(0) $end + $var wire 1 [~! is_fill_st2 $end + $var wire 1 9g is_mrvq_st1(0) $end + $var wire 1 -i is_mrvq_st1e $end + $var wire 1 -i is_mrvq_st1e_st2 $end + $var wire 1 7"" is_mrvq_st2 $end + $var wire 1 )g is_snp_st1(0) $end + $var wire 1 [h is_snp_st1e $end + $var wire 1 }!" is_snp_st2 $end + $var wire 32 ao" j [31:0] $end + $var wire 4 Kh mem_byteen_st1e [3:0] $end + $var wire 1 Ch mem_rw_st1e $end + $var wire 1 mi miss_add $end + $var wire 26 3.! miss_add_addr [25:0] $end + $var wire 1 {h miss_add_because_miss $end + $var wire 1 /"" miss_add_because_pending $end + $var wire 4 S~! miss_add_byteen [3:0] $end + $var wire 32 s~! miss_add_data [31:0] $end + $var wire 1 ui miss_add_is_mrvq $end + $var wire 1 }!" miss_add_is_snp $end + $var wire 1 K~! miss_add_rw $end + $var wire 1 '"" miss_add_snp_invalidate $end + $var wire 42 ;~! miss_add_tag [41:0] $end + $var wire 2 3~! miss_add_tid [1:0] $end + $var wire 1 ei miss_add_unqual $end + $var wire 2 k~! miss_add_wsel [1:0] $end + $var wire 1 qg miss_st1e $end + $var wire 1 E!" miss_st2 $end + $var wire 26 Q}! mrvq_addr_st0 [25:0] $end + $var wire 4 y}! mrvq_byteen_st0 [3:0] $end + $var wire 1 9}! mrvq_full $end + $var wire 1 Ui mrvq_init_ready_state_hazard_st0_st1 $end + $var wire 1 ]i mrvq_init_ready_state_hazard_st1e_st1 $end + $var wire 1 sh mrvq_init_ready_state_st1e $end + $var wire 1 Mi mrvq_init_ready_state_st2 $end + $var wire 1 G"" mrvq_init_ready_state_unqual_st2 $end + $var wire 1 #~! mrvq_is_snp_st0 $end + $var wire 1 qc mrvq_pending_hazard_st1e $end + $var wire 1 Yc mrvq_pop $end + $var wire 1 ac mrvq_pop_unqual $end + $var wire 1 3d mrvq_push_stall $end + $var wire 1 5i mrvq_recover_ready_state_st1e $end + $var wire 1 ?"" mrvq_recover_ready_state_st2 $end + $var wire 1 ic mrvq_rw_st0 $end + $var wire 1 +~! mrvq_snp_invalidate_st0 $end + $var wire 1 A}! mrvq_stop $end + $var wire 42 i}! mrvq_tag_st0 [41:0] $end + $var wire 2 I}! mrvq_tid_st0 [1:0] $end + $var wire 1 ac mrvq_valid_st0 $end + $var wire 32 a}! mrvq_writeword_st0 [31:0] $end + $var wire 2 Y}! mrvq_wsel_st0 [1:0] $end + $var wire 26 5e qual_addr_st0 [25:0] $end + $var wire 1 }e qual_going_to_write_st0 $end + $var wire 49 me qual_inst_meta_st0 [48:0] $end + $var wire 1 sd qual_is_fill_st0 $end + $var wire 1 ac qual_is_mrvq_st0 $end + $var wire 1 'f qual_is_snp_st0 $end + $var wire 1 /f qual_snp_invalidate_st0 $end + $var wire 1 -e qual_valid_st0 $end + $var wire 1 Ei qual_valid_st1e_2 $end + $var wire 128 Me qual_writedata_st0 [127:0] $end + $var wire 32 Ee qual_writeword_st0 [31:0] $end + $var wire 2 =e qual_wsel_st0 [1:0] $end + $var wire 128 Ig readdata_st1e [127:0] $end + $var wire 128 %!" readdata_st2 [127:0] $end + $var wire 20 ig readtag_st1e [19:0] $end + $var wire 20 m!" readtag_st2 [19:0] $end + $var wire 32 Ag readword_st1e [31:0] $end + $var wire 32 {~! readword_st2 [31:0] $end + $var wire 1 +d recover_mrvq_state_st2 $end + $var wire 1 !c reqq_empty $end + $var wire 1 !}! reqq_full $end + $var wire 1 wb reqq_pop $end + $var wire 1 {d reqq_pop_unqual $end + $var wire 1 w* reqq_push $end + $var wire 30 Ic reqq_req_addr_st0 [29:0] $end + $var wire 4 Ac reqq_req_byteen_st0 [3:0] $end + $var wire 1 9c reqq_req_rw_st0 $end + $var wire 1 )c reqq_req_st0 $end + $var wire 42 )}! reqq_req_tag_st0 [41:0] $end + $var wire 2 1c reqq_req_tid_st0 [1:0] $end + $var wire 32 Qc reqq_req_writeword_st0 [31:0] $end + $var wire 1 [h" reset $end + $var wire 1 1g snp_invalidate_st1(0) $end + $var wire 1 ch snp_invalidate_st1e $end + $var wire 1 '"" snp_invalidate_st2 $end + $var wire 26 mm" snp_req_addr [25:0] $end + $var wire 1 3l" snp_req_invalidate $end + $var wire 1 ;.! snp_req_ready $end + $var wire 28 ;l" snp_req_tag [27:0] $end + $var wire 1 /n" snp_req_valid $end + $var wire 1 /& snp_rsp_fire $end + $var wire 1 =! snp_rsp_ready $end + $var wire 28 13 snp_rsp_tag [27:0] $end + $var wire 1 )3 snp_rsp_valid $end + $var wire 1 kh snp_to_mrvq_st1e $end + $var wire 1 /"" snp_to_mrvq_st2 $end + $var wire 26 /b snrq_addr_st0 [25:0] $end + $var wire 1 _|! snrq_empty $end + $var wire 1 g|! snrq_full $end + $var wire 1 7b snrq_invalidate_st0 $end + $var wire 1 'b snrq_pop $end + $var wire 1 %e snrq_pop_unqual $end + $var wire 28 ?b snrq_tag_st0 [27:0] $end + $var wire 28 w"" snrq_tag_st2 [27:0] $end + $var wire 1 yc st2_pending_hazard_st1e $end + $var wire 1 Sd stall_bank_pipe $end + $var wire 42 +h tag_st1e [41:0] $end + $var wire 2 ;h tid_st1e [1:0] $end + $var wire 1 7f valid_st1(0) $end + $var wire 1 %i valid_st1e $end + $var wire 1 c~! valid_st2 $end + $var wire 128 gf writedata_st1(0) [127:0] $end + $var wire 32 Of writeword_st1(0) [31:0] $end + $var wire 32 s~! writeword_st2 [31:0] $end + $var wire 2 Gf wsel_st1(0) [1:0] $end + $var wire 2 k~! wsel_st2 [1:0] $end + $scope module cache_miss_resrv $end + $var wire 32 Kp" BANK_ID [31:0] $end + $var wire 32 gn" BANK_LINE_SIZE [31:0] $end + $var wire 32 Wn" CACHE_ID [31:0] $end + $var wire 32 !o" CORE_TAG_WIDTH [31:0] $end + $var wire 32 gn" MRVQ_SIZE [31:0] $end + $var wire 32 on" NUM_BANKS [31:0] $end + $var wire 32 on" NUM_REQUESTS [31:0] $end + $var wire 32 1o" SNP_REQ_TAG_WIDTH [31:0] $end + $var wire 32 on" WORD_SIZE [31:0] $end + $var wire 416 y;" addr_table [415:0] $end + $var wire 1 Sh" clk $end + $var wire 4 5=" dequeue_index [3:0] $end + $var wire 1 ac dequeue_possible $end + $var wire 4 E=" enqueue_index [3:0] $end + $var wire 1 U=" enqueue_possible $end + $var wire 26 =i fill_addr_st1 [25:0] $end + $var wire 4 ==" head_ptr [3:0] $end + $var wire 1 Kt increment_head $end + $var wire 1 gn is_fill_st1 $end + $var wire 1 ui is_mrvq $end + $var wire 16 ys make_ready [15:0] $end + $var wire 16 #t make_ready_push [15:0] $end + $var wire 85 q7" metadata_table(0) [84:0] $end + $var wire 85 t7" metadata_table(1) [84:0] $end + $var wire 85 18" metadata_table(10) [84:0] $end + $var wire 85 48" metadata_table(11) [84:0] $end + $var wire 85 78" metadata_table(12) [84:0] $end + $var wire 85 :8" metadata_table(13) [84:0] $end + $var wire 85 =8" metadata_table(14) [84:0] $end + $var wire 85 @8" metadata_table(15) [84:0] $end + $var wire 85 w7" metadata_table(2) [84:0] $end + $var wire 85 z7" metadata_table(3) [84:0] $end + $var wire 85 }7" metadata_table(4) [84:0] $end + $var wire 85 "8" metadata_table(5) [84:0] $end + $var wire 85 %8" metadata_table(6) [84:0] $end + $var wire 85 (8" metadata_table(7) [84:0] $end + $var wire 85 +8" metadata_table(8) [84:0] $end + $var wire 85 .8" metadata_table(9) [84:0] $end + $var wire 1 mi miss_add $end + $var wire 26 3.! miss_add_addr [25:0] $end + $var wire 4 S~! miss_add_byteen [3:0] $end + $var wire 32 s~! miss_add_data [31:0] $end + $var wire 1 }!" miss_add_is_snp $end + $var wire 1 K~! miss_add_rw $end + $var wire 1 '"" miss_add_snp_invalidate $end + $var wire 42 ;~! miss_add_tag [41:0] $end + $var wire 2 3~! miss_add_tid [1:0] $end + $var wire 2 k~! miss_add_wsel [1:0] $end + $var wire 26 Q}! miss_resrv_addr_st0 [25:0] $end + $var wire 4 y}! miss_resrv_byteen_st0 [3:0] $end + $var wire 32 a}! miss_resrv_data_st0 [31:0] $end + $var wire 1 9}! miss_resrv_full $end + $var wire 1 #~! miss_resrv_is_snp_st0 $end + $var wire 1 Yc miss_resrv_pop $end + $var wire 1 ic miss_resrv_rw_st0 $end + $var wire 1 +~! miss_resrv_snp_invalidate_st0 $end + $var wire 1 A}! miss_resrv_stop $end + $var wire 42 i}! miss_resrv_tag_st0 [41:0] $end + $var wire 2 I}! miss_resrv_tid_st0 [1:0] $end + $var wire 1 ac miss_resrv_valid_st0 $end + $var wire 2 Y}! miss_resrv_wsel_st0 [1:0] $end + $var wire 1 Mi mrvq_init_ready_state $end + $var wire 1 ;t mrvq_pop $end + $var wire 1 3t mrvq_push $end + $var wire 1 qc pending_hazard $end + $var wire 1 [t qual_mrvq_init $end + $var wire 16 -=" ready_table [15:0] $end + $var wire 1 Ct recover_state $end + $var wire 1 [h" reset $end + $var wire 4 5=" schedule_ptr [3:0] $end + $var wire 5 M=" size [4:0] $end + $var wire 4 E=" tail_ptr [3:0] $end + $var wire 1 St update_ready $end + $var wire 16 +t valid_address_match [15:0] $end + $var wire 16 %=" valid_table [15:0] $end + $upscope $end + $scope module core_req_arb $end + $var wire 32 )o" CORE_TAG_ID_BITS [31:0] $end + $var wire 32 !o" CORE_TAG_WIDTH [31:0] $end + $var wire 32 on" CREQ_SIZE [31:0] $end + $var wire 32 on" NUM_REQUESTS [31:0] $end + $var wire 32 on" WORD_SIZE [31:0] $end + $var wire 120 {h" bank_addr [119:0] $end + $var wire 16 sh" bank_byteen [15:0] $end + $var wire 4 kh" bank_rw [3:0] $end + $var wire 42 ]i" bank_tag [41:0] $end + $var wire 4 %! bank_valids [3:0] $end + $var wire 128 =i" bank_writedata [127:0] $end + $var wire 1 Sh" clk $end + $var wire 1 Y/" o_empty $end + $var wire 1 [l out_empty $end + $var wire 120 ik out_per_addr [119:0] $end + $var wire 16 ak out_per_byteen [15:0] $end + $var wire 4 Yk out_per_rw [3:0] $end + $var wire 42 Kl out_per_tag [41:0] $end + $var wire 4 Qk out_per_valids [3:0] $end + $var wire 128 +l out_per_writedata [127:0] $end + $var wire 1 cl pop_qual $end + $var wire 1 1+ push_qual $end + $var wire 120 w." qual_addr [119:0] $end + $var wire 16 o." qual_byteen [15:0] $end + $var wire 1 )c qual_has_request $end + $var wire 2 1c qual_request_index [1:0] $end + $var wire 4 g." qual_rw [3:0] $end + $var wire 42 )}! qual_tag [41:0] $end + $var wire 4 _." qual_valids [3:0] $end + $var wire 128 9/" qual_writedata [127:0] $end + $var wire 4 kl real_out_per_valids [3:0] $end + $var wire 1 !c reqq_empty $end + $var wire 1 !}! reqq_full $end + $var wire 1 wb reqq_pop $end + $var wire 1 w* reqq_push $end + $var wire 30 Ic reqq_req_addr_st0 [29:0] $end + $var wire 4 Ac reqq_req_byteen_st0 [3:0] $end + $var wire 1 9c reqq_req_rw_st0 $end + $var wire 1 )c reqq_req_st0 $end + $var wire 42 )}! reqq_req_tag_st0 [41:0] $end + $var wire 2 1c reqq_req_tid_st0 [1:0] $end + $var wire 32 Qc reqq_req_writedata_st0 [31:0] $end + $var wire 1 [h" reset $end + $var wire 1 a/" use_empty $end + $var wire 120 w." use_per_addr [119:0] $end + $var wire 16 o." use_per_byteen [15:0] $end + $var wire 4 g." use_per_rw [3:0] $end + $var wire 42 )}! use_per_tag [41:0] $end + $var wire 4 _." use_per_valids [3:0] $end + $var wire 128 9/" use_per_writedata [127:0] $end + $scope module reqq_queue $end + $var wire 32 wn" BUFFERED_OUTPUT [31:0] $end + $var wire 32 yo" DATAW [31:0] $end + $var wire 32 on" SIZE [31:0] $end + $var wire 1 Sh" clk $end + $var wire 314 !' data_in [313:0] $end + $var wire 314 sl data_out [313:0] $end + $var wire 1 Y/" empty $end + $var wire 1 !}! full $end + $var wire 1 cl pop $end + $var wire 1 1+ push $end + $var wire 1 em reading $end + $var wire 1 [h" reset $end + $var wire 3 i/" size [2:0] $end + $var wire 3 i/" size_r [2:0] $end + $var wire 1 q' writing $end + $scope module genblk3 $end + $var wire 314 q/" data(0) [313:0] $end + $var wire 314 {/" data(1) [313:0] $end + $var wire 314 '0" data(2) [313:0] $end + $var wire 314 10" data(3) [313:0] $end + $scope module genblk2 $end + $var wire 1 55" bypass_r $end + $var wire 314 +4" curr_r [313:0] $end + $var wire 1 Y/" empty_r $end + $var wire 1 !}! full_r $end + $var wire 314 93" head_r [313:0] $end + $var wire 2 -5" rd_ptr_next_r [1:0] $end + $var wire 2 %5" rd_ptr_r [1:0] $end + $var wire 2 {4" wr_ptr_r [1:0] $end + $upscope $end + $upscope $end + $upscope $end + $scope module sel_bank $end + $var wire 32 on" N [31:0] $end + $var wire 1 Sh" clk $end + $var wire 2 1c grant_index [1:0] $end + $var wire 4 mm grant_onehot [3:0] $end + $var wire 1 )c grant_valid $end + $var wire 4 _." requests [3:0] $end + $var wire 1 [h" reset $end + $scope module genblk2 $end + $var wire 4 mm grant_onehot_r [3:0] $end + $scope module priority_encoder $end + $var wire 32 on" N [31:0] $end + $var wire 4 _." data_in [3:0] $end + $var wire 2 1c data_out [1:0] $end + $var wire 32 um i [31:0] $end + $var wire 1 )c valid_out $end + $upscope $end + $upscope $end + $upscope $end + $upscope $end + $scope module cwb_queue $end + $var wire 32 wn" BUFFERED_OUTPUT [31:0] $end + $var wire 32 ;p" DATAW [31:0] $end + $var wire 32 on" SIZE [31:0] $end + $var wire 1 Sh" clk $end + $var wire 76 ct data_in [75:0] $end + $var wire 76 {t data_out [75:0] $end + $var wire 1 O"" empty $end + $var wire 1 W"" full $end + $var wire 1 !+ pop $end + $var wire 1 }i push $end + $var wire 1 y' reading $end + $var wire 1 [h" reset $end + $var wire 3 ]=" size [2:0] $end + $var wire 3 ]=" size_r [2:0] $end + $var wire 1 5u writing $end + $scope module genblk3 $end + $var wire 76 e=" data(0) [75:0] $end + $var wire 76 h=" data(1) [75:0] $end + $var wire 76 k=" data(2) [75:0] $end + $var wire 76 n=" data(3) [75:0] $end + $scope module genblk2 $end + $var wire 1 Q?" bypass_r $end + $var wire 76 !?" curr_r [75:0] $end + $var wire 1 O"" empty_r $end + $var wire 1 W"" full_r $end + $var wire 76 g>" head_r [75:0] $end + $var wire 2 I?" rd_ptr_next_r [1:0] $end + $var wire 2 A?" rd_ptr_r [1:0] $end + $var wire 2 9?" wr_ptr_r [1:0] $end + $upscope $end + $upscope $end + $upscope $end + $scope module dfp_queue $end + $var wire 32 wn" BUFFERED_OUTPUT [31:0] $end + $var wire 32 qo" DATAW [31:0] $end + $var wire 32 gn" SIZE [31:0] $end + $var wire 1 Sh" clk $end + $var wire 154 O& data_in [153:0] $end + $var wire 154 !k data_out [153:0] $end + $var wire 1 o|! empty $end + $var wire 1 w|! full $end + $var wire 1 Gb pop $end + $var wire 1 'n" push $end + $var wire 1 Ik reading $end + $var wire 1 [h" reset $end + $var wire 5 W&" size [4:0] $end + $var wire 5 W&" size_r [4:0] $end + $var wire 1 w& writing $end + $scope module genblk3 $end + $var wire 154 _&" data(0) [153:0] $end + $var wire 154 d&" data(1) [153:0] $end + $var wire 154 3'" data(10) [153:0] $end + $var wire 154 8'" data(11) [153:0] $end + $var wire 154 ='" data(12) [153:0] $end + $var wire 154 B'" data(13) [153:0] $end + $var wire 154 G'" data(14) [153:0] $end + $var wire 154 L'" data(15) [153:0] $end + $var wire 154 i&" data(2) [153:0] $end + $var wire 154 n&" data(3) [153:0] $end + $var wire 154 s&" data(4) [153:0] $end + $var wire 154 x&" data(5) [153:0] $end + $var wire 154 }&" data(6) [153:0] $end + $var wire 154 $'" data(7) [153:0] $end + $var wire 154 )'" data(8) [153:0] $end + $var wire 154 .'" data(9) [153:0] $end + $scope module genblk2 $end + $var wire 1 W." bypass_r $end + $var wire 154 u-" curr_r [153:0] $end + $var wire 1 o|! empty_r $end + $var wire 1 w|! full_r $end + $var wire 154 M-" head_r [153:0] $end + $var wire 4 O." rd_ptr_next_r [3:0] $end + $var wire 4 G." rd_ptr_r [3:0] $end + $var wire 4 ?." wr_ptr_r [3:0] $end + $upscope $end + $upscope $end + $upscope $end + $scope module dwb_queue $end + $var wire 32 wn" BUFFERED_OUTPUT [31:0] $end + $var wire 32 Cp" DATAW [31:0] $end + $var wire 32 on" SIZE [31:0] $end + $var wire 1 Sh" clk $end + $var wire 200 =u data_in [199:0] $end + $var wire 200 uu data_out [199:0] $end + $var wire 1 _"" empty $end + $var wire 1 g"" full $end + $var wire 1 )+ pop $end + $var wire 1 7j push $end + $var wire 1 #( reading $end + $var wire 1 [h" reset $end + $var wire 3 Y?" size [2:0] $end + $var wire 3 Y?" size_r [2:0] $end + $var wire 1 Ov writing $end + $scope module genblk3 $end + $var wire 200 a?" data(0) [199:0] $end + $var wire 200 h?" data(1) [199:0] $end + $var wire 200 o?" data(2) [199:0] $end + $var wire 200 v?" data(3) [199:0] $end + $scope module genblk2 $end + $var wire 1 QC" bypass_r $end + $var wire 200 _B" curr_r [199:0] $end + $var wire 1 _"" empty_r $end + $var wire 1 g"" full_r $end + $var wire 200 'B" head_r [199:0] $end + $var wire 2 IC" rd_ptr_next_r [1:0] $end + $var wire 2 AC" rd_ptr_r [1:0] $end + $var wire 2 9C" wr_ptr_r [1:0] $end + $upscope $end + $upscope $end + $upscope $end + $scope module s0_1_c0 $end + $var wire 32 #p" N [31:0] $end + $var wire 32 Wn" PASSTHRU [31:0] $end + $var wire 1 Sh" clk $end + $var wire 1 Io" flush $end + $var wire 243 }m in [242:0] $end + $var wire 243 =5" out [242:0] $end + $var wire 1 [h" reset $end + $var wire 1 Sd stall $end + $var wire 243 =5" value [242:0] $end + $upscope $end + $scope module snp_req_queue $end + $var wire 32 wn" BUFFERED_OUTPUT [31:0] $end + $var wire 32 io" DATAW [31:0] $end + $var wire 32 gn" SIZE [31:0] $end + $var wire 1 Sh" clk $end + $var wire 55 7& data_in [54:0] $end + $var wire 55 gj data_out [54:0] $end + $var wire 1 _|! empty $end + $var wire 1 g|! full $end + $var wire 1 'b pop $end + $var wire 1 /n" push $end + $var wire 1 wj reading $end + $var wire 1 [h" reset $end + $var wire 5 )#" size [4:0] $end + $var wire 5 )#" size_r [4:0] $end + $var wire 1 G& writing $end + $scope module genblk3 $end + $var wire 55 1#" data(0) [54:0] $end + $var wire 55 3#" data(1) [54:0] $end + $var wire 55 E#" data(10) [54:0] $end + $var wire 55 G#" data(11) [54:0] $end + $var wire 55 I#" data(12) [54:0] $end + $var wire 55 K#" data(13) [54:0] $end + $var wire 55 M#" data(14) [54:0] $end + $var wire 55 O#" data(15) [54:0] $end + $var wire 55 5#" data(2) [54:0] $end + $var wire 55 7#" data(3) [54:0] $end + $var wire 55 9#" data(4) [54:0] $end + $var wire 55 ;#" data(5) [54:0] $end + $var wire 55 =#" data(6) [54:0] $end + $var wire 55 ?#" data(7) [54:0] $end + $var wire 55 A#" data(8) [54:0] $end + $var wire 55 C#" data(9) [54:0] $end + $scope module genblk2 $end + $var wire 1 O&" bypass_r $end + $var wire 55 '&" curr_r [54:0] $end + $var wire 1 _|! empty_r $end + $var wire 1 g|! full_r $end + $var wire 55 u%" head_r [54:0] $end + $var wire 4 G&" rd_ptr_next_r [3:0] $end + $var wire 4 ?&" rd_ptr_r [3:0] $end + $var wire 4 7&" wr_ptr_r [3:0] $end + $upscope $end + $upscope $end + $upscope $end + $scope module st_1e_2 $end + $var wire 32 3p" N [31:0] $end + $var wire 32 Wn" PASSTHRU [31:0] $end + $var wire 1 Sh" clk $end + $var wire 1 Io" flush $end + $var wire 316 )s in [315:0] $end + $var wire 316 !7" out [315:0] $end + $var wire 1 [h" reset $end + $var wire 1 Sd stall $end + $var wire 316 !7" value [315:0] $end + $upscope $end + $scope module tag_data_access $end + $var wire 32 gn" BANK_LINE_SIZE [31:0] $end + $var wire 32 _n" CACHE_SIZE [31:0] $end + $var wire 32 wn" DRAM_ENABLE [31:0] $end + $var wire 32 on" NUM_BANKS [31:0] $end + $var wire 32 wn" STAGE_1_CYCLES [31:0] $end + $var wire 32 on" WORD_SIZE [31:0] $end + $var wire 32 wn" WRITE_ENABLE [31:0] $end + $var wire 1 Sh" clk $end + $var wire 128 {p data_write [127:0] $end + $var wire 1 yg dirty_st1e $end + $var wire 16 #h dirtyb_st1e [15:0] $end + $var wire 1 Sh fill_saw_dirty_st1e $end + $var wire 1 qg fill_sent $end + $var wire 1 'r force_core_miss $end + $var wire 1 #d force_request_miss_st1e $end + $var wire 1 =q invalidate_line $end + $var wire 1 [h is_snp_st1e $end + $var wire 4 Kh mem_byteen_st1e [3:0] $end + $var wire 1 Ch mem_rw_st1e $end + $var wire 1 qg miss_st1e $end + $var wire 1 sh mrvq_init_ready_state_st1e $end + $var wire 128 Cp qual_read_data_st1 [127:0] $end + $var wire 1 +p qual_read_dirty_st1 $end + $var wire 16 3p qual_read_dirtyb_st1 [15:0] $end + $var wire 20 ;p qual_read_tag_st1 [19:0] $end + $var wire 1 #p qual_read_valid_st1 $end + $var wire 128 ao read_data_st1c(0) [127:0] $end + $var wire 1 Io read_dirty_st1c(0) $end + $var wire 16 Qo read_dirtyb_st1c(0) [15:0] $end + $var wire 20 Yo read_tag_st1c(0) [19:0] $end + $var wire 1 Ao read_valid_st1c(0) $end + $var wire 6 _n readaddr_st10 [5:0] $end + $var wire 128 Ig readdata_st1e [127:0] $end + $var wire 20 ig readtag_st1e [19:0] $end + $var wire 32 Ag readword_st1e [31:0] $end + $var wire 1 }q real_miss $end + $var wire 1 Mq real_writefill $end + $var wire 1 mq req_invalid $end + $var wire 1 uq req_miss $end + $var wire 1 [h" reset $end + $var wire 1 eq should_write $end + $var wire 1 =q snoop_hit_no_pending $end + $var wire 1 ch snp_invalidate_st1e $end + $var wire 1 kh snp_to_mrvq_st1e $end + $var wire 1 Sd stall $end + $var wire 1 Sd stall_bank_pipe $end + $var wire 1 Eq tags_match $end + $var wire 128 Ig use_read_data_st1e [127:0] $end + $var wire 1 kp use_read_dirty_st1e $end + $var wire 16 #h use_read_dirtyb_st1e [15:0] $end + $var wire 20 ig use_read_tag_st1e [19:0] $end + $var wire 1 cp use_read_valid_st1e $end + $var wire 128 {p use_write_data [127:0] $end + $var wire 16 sp use_write_enable [15:0] $end + $var wire 1 %i valid_req_st1e $end + $var wire 16 ]q we [15:0] $end + $var wire 2 9o wordsel_st1e [1:0] $end + $var wire 26 =i writeaddr_st1e [25:0] $end + $var wire 128 wn writedata_st1e [127:0] $end + $var wire 1 gn writefill_st1e $end + $var wire 6 _n writeladdr_st1e [5:0] $end + $var wire 20 Uq writetag_st1e [19:0] $end + $var wire 32 on writeword_st1e [31:0] $end + $scope module genblk4(0) $end + $var wire 1 /r normal_write $end + $upscope $end + $scope module genblk4(1) $end + $var wire 1 7r normal_write $end + $upscope $end + $scope module genblk4(2) $end + $var wire 1 ?r normal_write $end + $upscope $end + $scope module genblk4(3) $end + $var wire 1 Gr normal_write $end + $upscope $end + $scope module s0_1_c0 $end + $var wire 32 +p" N [31:0] $end + $var wire 32 wn" PASSTHRU [31:0] $end + $var wire 1 Sh" clk $end + $var wire 1 Io" flush $end + $var wire 166 Wr in [165:0] $end + $var wire 166 Wr out [165:0] $end + $var wire 1 [h" reset $end + $var wire 1 Sd stall $end + $var wire 166 O6" value [165:0] $end + $upscope $end + $scope module tag_data_structure $end + $var wire 32 gn" BANK_LINE_SIZE [31:0] $end + $var wire 32 _n" CACHE_SIZE [31:0] $end + $var wire 32 on" NUM_BANKS [31:0] $end + $var wire 32 on" WORD_SIZE [31:0] $end + $var wire 1 Sh" clk $end + $var wire 64 }5" dirty [63:0] $end + $var wire 1 Or do_write $end + $var wire 1 qg fill_sent $end + $var wire 32 ?6" i [31:0] $end + $var wire 1 =q invalidate $end + $var wire 32 G6" j [31:0] $end + $var wire 6 _n read_addr [5:0] $end + $var wire 128 Cp read_data [127:0] $end + $var wire 1 +p read_dirty $end + $var wire 16 3p read_dirtyb [15:0] $end + $var wire 20 ;p read_tag [19:0] $end + $var wire 1 #p read_valid $end + $var wire 1 [h" reset $end + $var wire 1 Sd stall_bank_pipe $end + $var wire 20 Uq tag_index [19:0] $end + $var wire 64 /6" valid [63:0] $end + $var wire 6 _n write_addr [5:0] $end + $var wire 128 {p write_data [127:0] $end + $var wire 16 sp write_enable [15:0] $end + $var wire 1 Mq write_fill $end + $upscope $end + $upscope $end + $upscope $end + $upscope $end + $scope module genblk5(3) $end + $var wire 120 {h" curr_bank_core_req_addr [119:0] $end + $var wire 16 sh" curr_bank_core_req_byteen [15:0] $end + $var wire 128 =i" curr_bank_core_req_data [127:0] $end + $var wire 1 k.! curr_bank_core_req_ready $end + $var wire 4 kh" curr_bank_core_req_rw [3:0] $end + $var wire 42 ]i" curr_bank_core_req_tag [41:0] $end + $var wire 4 E! curr_bank_core_req_valid [3:0] $end + $var wire 32 A3 curr_bank_core_rsp_data [31:0] $end + $var wire 1 M! curr_bank_core_rsp_ready $end + $var wire 42 I3 curr_bank_core_rsp_tag [41:0] $end + $var wire 2 93 curr_bank_core_rsp_tid [1:0] $end + $var wire 1 K.! curr_bank_core_rsp_valid $end + $var wire 26 [.! curr_bank_dram_fill_req_addr [25:0] $end + $var wire 1 )-! curr_bank_dram_fill_req_ready $end + $var wire 1 Y3 curr_bank_dram_fill_req_valid $end + $var wire 26 ]m" curr_bank_dram_fill_rsp_addr [25:0] $end + $var wire 128 Qk" curr_bank_dram_fill_rsp_data [127:0] $end + $var wire 1 S.! curr_bank_dram_fill_rsp_ready $end + $var wire 1 7n" curr_bank_dram_fill_rsp_valid $end + $var wire 26 q3 curr_bank_dram_wb_req_addr [25:0] $end + $var wire 16 i3 curr_bank_dram_wb_req_byteen [15:0] $end + $var wire 128 y3 curr_bank_dram_wb_req_data [127:0] $end + $var wire 1 U! curr_bank_dram_wb_req_ready $end + $var wire 1 a3 curr_bank_dram_wb_req_valid $end + $var wire 26 mm" curr_bank_snp_req_addr [25:0] $end + $var wire 1 3l" curr_bank_snp_req_invalidate $end + $var wire 1 c.! curr_bank_snp_req_ready $end + $var wire 28 ;l" curr_bank_snp_req_tag [27:0] $end + $var wire 1 ?n" curr_bank_snp_req_valid $end + $var wire 1 ]! curr_bank_snp_rsp_ready $end + $var wire 28 C4 curr_bank_snp_rsp_tag [27:0] $end + $var wire 1 ;4 curr_bank_snp_rsp_valid $end + $scope module bank $end + $var wire 32 Sp" BANK_ID [31:0] $end + $var wire 32 gn" BANK_LINE_SIZE [31:0] $end + $var wire 32 Wn" CACHE_ID [31:0] $end + $var wire 32 _n" CACHE_SIZE [31:0] $end + $var wire 32 )o" CORE_TAG_ID_BITS [31:0] $end + $var wire 32 !o" CORE_TAG_WIDTH [31:0] $end + $var wire 32 on" CREQ_SIZE [31:0] $end + $var wire 32 on" CWBQ_SIZE [31:0] $end + $var wire 32 gn" DFPQ_SIZE [31:0] $end + $var wire 32 on" DFQQ_SIZE [31:0] $end + $var wire 32 wn" DRAM_ENABLE [31:0] $end + $var wire 32 on" DWBQ_SIZE [31:0] $end + $var wire 32 gn" MRVQ_SIZE [31:0] $end + $var wire 32 on" NUM_BANKS [31:0] $end + $var wire 32 on" NUM_REQUESTS [31:0] $end + $var wire 32 Wn" SNOOP_FORWARDING [31:0] $end + $var wire 32 1o" SNP_REQ_TAG_WIDTH [31:0] $end + $var wire 32 gn" SNRQ_SIZE [31:0] $end + $var wire 32 wn" STAGE_1_CYCLES [31:0] $end + $var wire 32 on" WORD_SIZE [31:0] $end + $var wire 32 wn" WRITE_ENABLE [31:0] $end + $var wire 26 oz addr_st1(0) [25:0] $end + $var wire 26 m} addr_st1e [25:0] $end + $var wire 26 [.! addr_st2 [25:0] $end + $var wire 1 Sh" clk $end + $var wire 120 {h" core_req_addr [119:0] $end + $var wire 16 sh" core_req_byteen [15:0] $end + $var wire 128 =i" core_req_data [127:0] $end + $var wire 1 k.! core_req_ready $end + $var wire 4 kh" core_req_rw [3:0] $end + $var wire 42 ]i" core_req_tag [41:0] $end + $var wire 4 E! core_req_valid [3:0] $end + $var wire 32 A3 core_rsp_data [31:0] $end + $var wire 1 M! core_rsp_ready $end + $var wire 42 I3 core_rsp_tag [41:0] $end + $var wire 2 93 core_rsp_tid [1:0] $end + $var wire 1 K.! core_rsp_valid $end + $var wire 32 uE" cwbq_data [31:0] $end + $var wire 1 IG" cwbq_empty $end + $var wire 1 QG" cwbq_full $end + $var wire 1 A+ cwbq_pop $end + $var wire 1 O~ cwbq_push $end + $var wire 1 kx cwbq_push_stall $end + $var wire 1 W~ cwbq_push_unqual $end + $var wire 42 5E" cwbq_tag [41:0] $end + $var wire 2 -E" cwbq_tid [1:0] $end + $var wire 26 !w dfpq_addr_st0 [25:0] $end + $var wire 1 iC" dfpq_empty $end + $var wire 128 )w dfpq_filldata_st0 [127:0] $end + $var wire 1 qC" dfpq_full $end + $var wire 1 wv dfpq_pop $end + $var wire 1 Ey dfpq_pop_unqual $end + $var wire 1 K| dirty_st1e $end + $var wire 1 GF" dirty_st2 $end + $var wire 16 S| dirtyb_st1e [15:0] $end + $var wire 16 OF" dirtyb_st2 [15:0] $end + $var wire 26 [.! dram_fill_req_addr [25:0] $end + $var wire 1 7~ dram_fill_req_fast $end + $var wire 1 )-! dram_fill_req_ready $end + $var wire 1 {x dram_fill_req_stall $end + $var wire 1 _~ dram_fill_req_unqual $end + $var wire 1 Y3 dram_fill_req_valid $end + $var wire 26 ]m" dram_fill_rsp_addr [25:0] $end + $var wire 128 Qk" dram_fill_rsp_data [127:0] $end + $var wire 1 S.! dram_fill_rsp_ready $end + $var wire 1 7n" dram_fill_rsp_valid $end + $var wire 26 q3 dram_wb_req_addr [25:0] $end + $var wire 16 i3 dram_wb_req_byteen [15:0] $end + $var wire 128 y3 dram_wb_req_data [127:0] $end + $var wire 1 +( dram_wb_req_fire $end + $var wire 1 U! dram_wb_req_ready $end + $var wire 1 a3 dram_wb_req_valid $end + $var wire 1 yG" dwbq_dual_valid_sel $end + $var wire 1 YG" dwbq_empty $end + $var wire 1 aG" dwbq_full $end + $var wire 1 o~ dwbq_is_dwb_in $end + $var wire 1 !!! dwbq_is_dwb_out $end + $var wire 1 w~ dwbq_is_snp_in $end + $var wire 1 )!! dwbq_is_snp_out $end + $var wire 1 I+ dwbq_pop $end + $var wire 1 g~ dwbq_push $end + $var wire 1 sx dwbq_push_stall $end + $var wire 1 1!! dwbq_push_unqual $end + $var wire 26 iG" dwbq_req_addr [25:0] $end + $var wire 1 %} fill_saw_dirty_st1e $end + $var wire 1 oF" fill_saw_dirty_st2 $end + $var wire 1 Sx force_request_miss_st1e $end + $var wire 1 =y going_to_write_st1(0) $end + $var wire 49 ){ inst_meta_st1(0) [48:0] $end + $var wire 49 WF" inst_meta_st2 [48:0] $end + $var wire 1 -y is_fill_in_pipe $end + $var wire 1 5y is_fill_st1(0) $end + $var wire 1 UE" is_fill_st2 $end + $var wire 1 i{ is_mrvq_st1(0) $end + $var wire 1 ]} is_mrvq_st1e $end + $var wire 1 ]} is_mrvq_st1e_st2 $end + $var wire 1 1G" is_mrvq_st2 $end + $var wire 1 Y{ is_snp_st1(0) $end + $var wire 1 -} is_snp_st1e $end + $var wire 1 wF" is_snp_st2 $end + $var wire 32 ao" j [31:0] $end + $var wire 4 {| mem_byteen_st1e [3:0] $end + $var wire 1 s| mem_rw_st1e $end + $var wire 1 ?~ miss_add $end + $var wire 26 [.! miss_add_addr [25:0] $end + $var wire 1 M} miss_add_because_miss $end + $var wire 1 )G" miss_add_because_pending $end + $var wire 4 ME" miss_add_byteen [3:0] $end + $var wire 32 mE" miss_add_data [31:0] $end + $var wire 1 G~ miss_add_is_mrvq $end + $var wire 1 wF" miss_add_is_snp $end + $var wire 1 EE" miss_add_rw $end + $var wire 1 !G" miss_add_snp_invalidate $end + $var wire 42 5E" miss_add_tag [41:0] $end + $var wire 2 -E" miss_add_tid [1:0] $end + $var wire 1 7~ miss_add_unqual $end + $var wire 2 eE" miss_add_wsel [1:0] $end + $var wire 1 C| miss_st1e $end + $var wire 1 ?F" miss_st2 $end + $var wire 26 KD" mrvq_addr_st0 [25:0] $end + $var wire 4 sD" mrvq_byteen_st0 [3:0] $end + $var wire 1 3D" mrvq_full $end + $var wire 1 '~ mrvq_init_ready_state_hazard_st0_st1 $end + $var wire 1 /~ mrvq_init_ready_state_hazard_st1e_st1 $end + $var wire 1 E} mrvq_init_ready_state_st1e $end + $var wire 1 }} mrvq_init_ready_state_st2 $end + $var wire 1 AG" mrvq_init_ready_state_unqual_st2 $end + $var wire 1 {D" mrvq_is_snp_st0 $end + $var wire 1 Cx mrvq_pending_hazard_st1e $end + $var wire 1 +x mrvq_pop $end + $var wire 1 3x mrvq_pop_unqual $end + $var wire 1 cx mrvq_push_stall $end + $var wire 1 e} mrvq_recover_ready_state_st1e $end + $var wire 1 9G" mrvq_recover_ready_state_st2 $end + $var wire 1 ;x mrvq_rw_st0 $end + $var wire 1 %E" mrvq_snp_invalidate_st0 $end + $var wire 1 ;D" mrvq_stop $end + $var wire 42 cD" mrvq_tag_st0 [41:0] $end + $var wire 2 CD" mrvq_tid_st0 [1:0] $end + $var wire 1 3x mrvq_valid_st0 $end + $var wire 32 [D" mrvq_writeword_st0 [31:0] $end + $var wire 2 SD" mrvq_wsel_st0 [1:0] $end + $var wire 26 ey qual_addr_st0 [25:0] $end + $var wire 1 Oz qual_going_to_write_st0 $end + $var wire 49 ?z qual_inst_meta_st0 [48:0] $end + $var wire 1 Ey qual_is_fill_st0 $end + $var wire 1 3x qual_is_mrvq_st0 $end + $var wire 1 Wz qual_is_snp_st0 $end + $var wire 1 _z qual_snp_invalidate_st0 $end + $var wire 1 ]y qual_valid_st0 $end + $var wire 1 u} qual_valid_st1e_2 $end + $var wire 128 }y qual_writedata_st0 [127:0] $end + $var wire 32 uy qual_writeword_st0 [31:0] $end + $var wire 2 my qual_wsel_st0 [1:0] $end + $var wire 128 y{ readdata_st1e [127:0] $end + $var wire 128 }E" readdata_st2 [127:0] $end + $var wire 20 ;| readtag_st1e [19:0] $end + $var wire 20 gF" readtag_st2 [19:0] $end + $var wire 32 q{ readword_st1e [31:0] $end + $var wire 32 uE" readword_st2 [31:0] $end + $var wire 1 [x recover_mrvq_state_st2 $end + $var wire 1 Qw reqq_empty $end + $var wire 1 yC" reqq_full $end + $var wire 1 Iw reqq_pop $end + $var wire 1 My reqq_pop_unqual $end + $var wire 1 9+ reqq_push $end + $var wire 30 yw reqq_req_addr_st0 [29:0] $end + $var wire 4 qw reqq_req_byteen_st0 [3:0] $end + $var wire 1 iw reqq_req_rw_st0 $end + $var wire 1 Yw reqq_req_st0 $end + $var wire 42 #D" reqq_req_tag_st0 [41:0] $end + $var wire 2 aw reqq_req_tid_st0 [1:0] $end + $var wire 32 #x reqq_req_writeword_st0 [31:0] $end + $var wire 1 [h" reset $end + $var wire 1 a{ snp_invalidate_st1(0) $end + $var wire 1 5} snp_invalidate_st1e $end + $var wire 1 !G" snp_invalidate_st2 $end + $var wire 26 mm" snp_req_addr [25:0] $end + $var wire 1 3l" snp_req_invalidate $end + $var wire 1 c.! snp_req_ready $end + $var wire 28 ;l" snp_req_tag [27:0] $end + $var wire 1 ?n" snp_req_valid $end + $var wire 1 3( snp_rsp_fire $end + $var wire 1 ]! snp_rsp_ready $end + $var wire 28 C4 snp_rsp_tag [27:0] $end + $var wire 1 ;4 snp_rsp_valid $end + $var wire 1 =} snp_to_mrvq_st1e $end + $var wire 1 )G" snp_to_mrvq_st2 $end + $var wire 26 _v snrq_addr_st0 [25:0] $end + $var wire 1 YC" snrq_empty $end + $var wire 1 aC" snrq_full $end + $var wire 1 gv snrq_invalidate_st0 $end + $var wire 1 Wv snrq_pop $end + $var wire 1 Uy snrq_pop_unqual $end + $var wire 28 ov snrq_tag_st0 [27:0] $end + $var wire 28 qG" snrq_tag_st2 [27:0] $end + $var wire 1 Kx st2_pending_hazard_st1e $end + $var wire 1 %y stall_bank_pipe $end + $var wire 42 [| tag_st1e [41:0] $end + $var wire 2 k| tid_st1e [1:0] $end + $var wire 1 gz valid_st1(0) $end + $var wire 1 U} valid_st1e $end + $var wire 1 ]E" valid_st2 $end + $var wire 128 9{ writedata_st1(0) [127:0] $end + $var wire 32 !{ writeword_st1(0) [31:0] $end + $var wire 32 mE" writeword_st2 [31:0] $end + $var wire 2 wz wsel_st1(0) [1:0] $end + $var wire 2 eE" wsel_st2 [1:0] $end + $scope module cache_miss_resrv $end + $var wire 32 Sp" BANK_ID [31:0] $end + $var wire 32 gn" BANK_LINE_SIZE [31:0] $end + $var wire 32 Wn" CACHE_ID [31:0] $end + $var wire 32 !o" CORE_TAG_WIDTH [31:0] $end + $var wire 32 gn" MRVQ_SIZE [31:0] $end + $var wire 32 on" NUM_BANKS [31:0] $end + $var wire 32 on" NUM_REQUESTS [31:0] $end + $var wire 32 1o" SNP_REQ_TAG_WIDTH [31:0] $end + $var wire 32 on" WORD_SIZE [31:0] $end + $var wire 416 s`" addr_table [415:0] $end + $var wire 1 Sh" clk $end + $var wire 4 /b" dequeue_index [3:0] $end + $var wire 1 3x dequeue_possible $end + $var wire 4 ?b" enqueue_index [3:0] $end + $var wire 1 Ob" enqueue_possible $end + $var wire 26 m} fill_addr_st1 [25:0] $end + $var wire 4 7b" head_ptr [3:0] $end + $var wire 1 {*! increment_head $end + $var wire 1 9%! is_fill_st1 $end + $var wire 1 G~ is_mrvq $end + $var wire 16 K*! make_ready [15:0] $end + $var wire 16 S*! make_ready_push [15:0] $end + $var wire 85 k\" metadata_table(0) [84:0] $end + $var wire 85 n\" metadata_table(1) [84:0] $end + $var wire 85 +]" metadata_table(10) [84:0] $end + $var wire 85 .]" metadata_table(11) [84:0] $end + $var wire 85 1]" metadata_table(12) [84:0] $end + $var wire 85 4]" metadata_table(13) [84:0] $end + $var wire 85 7]" metadata_table(14) [84:0] $end + $var wire 85 :]" metadata_table(15) [84:0] $end + $var wire 85 q\" metadata_table(2) [84:0] $end + $var wire 85 t\" metadata_table(3) [84:0] $end + $var wire 85 w\" metadata_table(4) [84:0] $end + $var wire 85 z\" metadata_table(5) [84:0] $end + $var wire 85 }\" metadata_table(6) [84:0] $end + $var wire 85 "]" metadata_table(7) [84:0] $end + $var wire 85 %]" metadata_table(8) [84:0] $end + $var wire 85 (]" metadata_table(9) [84:0] $end + $var wire 1 ?~ miss_add $end + $var wire 26 [.! miss_add_addr [25:0] $end + $var wire 4 ME" miss_add_byteen [3:0] $end + $var wire 32 mE" miss_add_data [31:0] $end + $var wire 1 wF" miss_add_is_snp $end + $var wire 1 EE" miss_add_rw $end + $var wire 1 !G" miss_add_snp_invalidate $end + $var wire 42 5E" miss_add_tag [41:0] $end + $var wire 2 -E" miss_add_tid [1:0] $end + $var wire 2 eE" miss_add_wsel [1:0] $end + $var wire 26 KD" miss_resrv_addr_st0 [25:0] $end + $var wire 4 sD" miss_resrv_byteen_st0 [3:0] $end + $var wire 32 [D" miss_resrv_data_st0 [31:0] $end + $var wire 1 3D" miss_resrv_full $end + $var wire 1 {D" miss_resrv_is_snp_st0 $end + $var wire 1 +x miss_resrv_pop $end + $var wire 1 ;x miss_resrv_rw_st0 $end + $var wire 1 %E" miss_resrv_snp_invalidate_st0 $end + $var wire 1 ;D" miss_resrv_stop $end + $var wire 42 cD" miss_resrv_tag_st0 [41:0] $end + $var wire 2 CD" miss_resrv_tid_st0 [1:0] $end + $var wire 1 3x miss_resrv_valid_st0 $end + $var wire 2 SD" miss_resrv_wsel_st0 [1:0] $end + $var wire 1 }} mrvq_init_ready_state $end + $var wire 1 k*! mrvq_pop $end + $var wire 1 c*! mrvq_push $end + $var wire 1 Cx pending_hazard $end + $var wire 1 -+! qual_mrvq_init $end + $var wire 16 'b" ready_table [15:0] $end + $var wire 1 s*! recover_state $end + $var wire 1 [h" reset $end + $var wire 4 /b" schedule_ptr [3:0] $end + $var wire 5 Gb" size [4:0] $end + $var wire 4 ?b" tail_ptr [3:0] $end + $var wire 1 %+! update_ready $end + $var wire 16 [*! valid_address_match [15:0] $end + $var wire 16 }a" valid_table [15:0] $end + $upscope $end + $scope module core_req_arb $end + $var wire 32 )o" CORE_TAG_ID_BITS [31:0] $end + $var wire 32 !o" CORE_TAG_WIDTH [31:0] $end + $var wire 32 on" CREQ_SIZE [31:0] $end + $var wire 32 on" NUM_REQUESTS [31:0] $end + $var wire 32 on" WORD_SIZE [31:0] $end + $var wire 120 {h" bank_addr [119:0] $end + $var wire 16 sh" bank_byteen [15:0] $end + $var wire 4 kh" bank_rw [3:0] $end + $var wire 42 ]i" bank_tag [41:0] $end + $var wire 4 E! bank_valids [3:0] $end + $var wire 128 =i" bank_writedata [127:0] $end + $var wire 1 Sh" clk $end + $var wire 1 ST" o_empty $end + $var wire 1 -#! out_empty $end + $var wire 120 ;"! out_per_addr [119:0] $end + $var wire 16 3"! out_per_byteen [15:0] $end + $var wire 4 +"! out_per_rw [3:0] $end + $var wire 42 {"! out_per_tag [41:0] $end + $var wire 4 #"! out_per_valids [3:0] $end + $var wire 128 ["! out_per_writedata [127:0] $end + $var wire 1 5#! pop_qual $end + $var wire 1 Q+ push_qual $end + $var wire 120 qS" qual_addr [119:0] $end + $var wire 16 iS" qual_byteen [15:0] $end + $var wire 1 Yw qual_has_request $end + $var wire 2 aw qual_request_index [1:0] $end + $var wire 4 aS" qual_rw [3:0] $end + $var wire 42 #D" qual_tag [41:0] $end + $var wire 4 YS" qual_valids [3:0] $end + $var wire 128 3T" qual_writedata [127:0] $end + $var wire 4 =#! real_out_per_valids [3:0] $end + $var wire 1 Qw reqq_empty $end + $var wire 1 yC" reqq_full $end + $var wire 1 Iw reqq_pop $end + $var wire 1 9+ reqq_push $end + $var wire 30 yw reqq_req_addr_st0 [29:0] $end + $var wire 4 qw reqq_req_byteen_st0 [3:0] $end + $var wire 1 iw reqq_req_rw_st0 $end + $var wire 1 Yw reqq_req_st0 $end + $var wire 42 #D" reqq_req_tag_st0 [41:0] $end + $var wire 2 aw reqq_req_tid_st0 [1:0] $end + $var wire 32 #x reqq_req_writedata_st0 [31:0] $end + $var wire 1 [h" reset $end + $var wire 1 [T" use_empty $end + $var wire 120 qS" use_per_addr [119:0] $end + $var wire 16 iS" use_per_byteen [15:0] $end + $var wire 4 aS" use_per_rw [3:0] $end + $var wire 42 #D" use_per_tag [41:0] $end + $var wire 4 YS" use_per_valids [3:0] $end + $var wire 128 3T" use_per_writedata [127:0] $end + $scope module reqq_queue $end + $var wire 32 wn" BUFFERED_OUTPUT [31:0] $end + $var wire 32 yo" DATAW [31:0] $end + $var wire 32 on" SIZE [31:0] $end + $var wire 1 Sh" clk $end + $var wire 314 %) data_in [313:0] $end + $var wire 314 E#! data_out [313:0] $end + $var wire 1 ST" empty $end + $var wire 1 yC" full $end + $var wire 1 5#! pop $end + $var wire 1 Q+ push $end + $var wire 1 7$! reading $end + $var wire 1 [h" reset $end + $var wire 3 cT" size [2:0] $end + $var wire 3 cT" size_r [2:0] $end + $var wire 1 u) writing $end + $scope module genblk3 $end + $var wire 314 kT" data(0) [313:0] $end + $var wire 314 uT" data(1) [313:0] $end + $var wire 314 !U" data(2) [313:0] $end + $var wire 314 +U" data(3) [313:0] $end + $scope module genblk2 $end + $var wire 1 /Z" bypass_r $end + $var wire 314 %Y" curr_r [313:0] $end + $var wire 1 ST" empty_r $end + $var wire 1 yC" full_r $end + $var wire 314 3X" head_r [313:0] $end + $var wire 2 'Z" rd_ptr_next_r [1:0] $end + $var wire 2 }Y" rd_ptr_r [1:0] $end + $var wire 2 uY" wr_ptr_r [1:0] $end + $upscope $end + $upscope $end + $upscope $end + $scope module sel_bank $end + $var wire 32 on" N [31:0] $end + $var wire 1 Sh" clk $end + $var wire 2 aw grant_index [1:0] $end + $var wire 4 ?$! grant_onehot [3:0] $end + $var wire 1 Yw grant_valid $end + $var wire 4 YS" requests [3:0] $end + $var wire 1 [h" reset $end + $scope module genblk2 $end + $var wire 4 ?$! grant_onehot_r [3:0] $end + $scope module priority_encoder $end + $var wire 32 on" N [31:0] $end + $var wire 4 YS" data_in [3:0] $end + $var wire 2 aw data_out [1:0] $end + $var wire 32 G$! i [31:0] $end + $var wire 1 Yw valid_out $end + $upscope $end + $upscope $end + $upscope $end + $upscope $end + $scope module cwb_queue $end + $var wire 32 wn" BUFFERED_OUTPUT [31:0] $end + $var wire 32 ;p" DATAW [31:0] $end + $var wire 32 on" SIZE [31:0] $end + $var wire 1 Sh" clk $end + $var wire 76 5+! data_in [75:0] $end + $var wire 76 M+! data_out [75:0] $end + $var wire 1 IG" empty $end + $var wire 1 QG" full $end + $var wire 1 A+ pop $end + $var wire 1 O~ push $end + $var wire 1 }) reading $end + $var wire 1 [h" reset $end + $var wire 3 Wb" size [2:0] $end + $var wire 3 Wb" size_r [2:0] $end + $var wire 1 e+! writing $end + $scope module genblk3 $end + $var wire 76 _b" data(0) [75:0] $end + $var wire 76 bb" data(1) [75:0] $end + $var wire 76 eb" data(2) [75:0] $end + $var wire 76 hb" data(3) [75:0] $end + $scope module genblk2 $end + $var wire 1 Kd" bypass_r $end + $var wire 76 yc" curr_r [75:0] $end + $var wire 1 IG" empty_r $end + $var wire 1 QG" full_r $end + $var wire 76 ac" head_r [75:0] $end + $var wire 2 Cd" rd_ptr_next_r [1:0] $end + $var wire 2 ;d" rd_ptr_r [1:0] $end + $var wire 2 3d" wr_ptr_r [1:0] $end + $upscope $end + $upscope $end + $upscope $end + $scope module dfp_queue $end + $var wire 32 wn" BUFFERED_OUTPUT [31:0] $end + $var wire 32 qo" DATAW [31:0] $end + $var wire 32 gn" SIZE [31:0] $end + $var wire 1 Sh" clk $end + $var wire 154 S( data_in [153:0] $end + $var wire 154 Q!! data_out [153:0] $end + $var wire 1 iC" empty $end + $var wire 1 qC" full $end + $var wire 1 wv pop $end + $var wire 1 7n" push $end + $var wire 1 y!! reading $end + $var wire 1 [h" reset $end + $var wire 5 QK" size [4:0] $end + $var wire 5 QK" size_r [4:0] $end + $var wire 1 {( writing $end + $scope module genblk3 $end + $var wire 154 YK" data(0) [153:0] $end + $var wire 154 ^K" data(1) [153:0] $end + $var wire 154 -L" data(10) [153:0] $end + $var wire 154 2L" data(11) [153:0] $end + $var wire 154 7L" data(12) [153:0] $end + $var wire 154 +1/> +07> +b01011101000110100011001011000110 ?> +b10000010001001110000101010100010010111010001101000110010110001100001111001001011010000100001010110111100111101011010111101111001 G> +b10111010110111000010 g> +0o> +0w> +b1011100010011000 !? +b101100111101000001011011100100101111001111 )? +b11 9? +1A? +b1100 I? +0Q? +0Y? +1a? +0i? +0q? +0y? +1#@ +0+@ +03@ +b01111001001010010011001110 ;@ +0C@ +1K@ +0S@ +0[@ +1c@ +0k@ +0s@ +0{@ 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