Before ISA2.0

2019-10-18 04:15:34 -04:00
parent 559c64cb36
commit 629ed3f8f9
5 changed files with 7 additions and 28 deletions
--- a/rtl/VX_scheduler.v
+++ b/rtl/VX_scheduler.v
@@ -4,6 +4,7 @@

 module VX_scheduler (
 	input wire                clk,
+	input wire                memory_delay,
 	VX_frE_to_bckE_req_inter  VX_bckE_req,
 	VX_wb_inter               VX_writeback_inter,

@@ -38,7 +39,7 @@ module VX_scheduler (
 	wire rename_valid = rs1_rename_qual || rs2_rename_qual ;


-	assign schedule_delay = (rename_valid) && (|VX_bckE_req.valid);
+	assign schedule_delay = (rename_valid) && (|VX_bckE_req.valid) || memory_delay;


 	always @(posedge clk) begin