wu-arch/vortex
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Before ISA2.0

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This commit is contained in:
felsabbagh3
2019-10-18 04:15:34 -04:00
parent 559c64cb36
commit 629ed3f8f9
5 changed files with 7 additions and 28 deletions
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9
rtl/VX_back_end.v
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@@ -1,7 +1,6 @@
module VX_back_end (
input wire clk,
input wire reset,
input wire fetch_delay,
input wire schedule_delay,
input wire[31:0] csr_decode_csr_data,
@@ -23,12 +22,6 @@ module VX_back_end (
VX_csr_write_request_inter VX_csr_w_req
);
wire memory_delay;
assign out_mem_delay = memory_delay;
wire total_freeze = fetch_delay || memory_delay;
wire[11:0] execute_csr_address;
wire execute_is_csr;
@@ -84,7 +77,7 @@ VX_lsu load_store_unit(
.VX_mem_wb (VX_mem_wb),
.VX_dcache_rsp(VX_dcache_rsp),
.VX_dcache_req(VX_dcache_req),
.out_delay (memory_delay)
.out_delay (out_mem_delay)
);