From 61add25d9652d6e916980aebd04ca6fefaa9ed0a Mon Sep 17 00:00:00 2001 From: Blaise Tine Date: Mon, 16 Nov 2020 08:23:16 -0800 Subject: [PATCH] minor fix --- driver/opae/vlsim/Makefile | 2 +- driver/rtlsim/Makefile | 2 +- hw/rtl/cache/VX_data_access.v | 2 +- hw/rtl/cache/VX_tag_access.v | 12 +++++++----- 4 files changed, 10 insertions(+), 8 deletions(-) diff --git a/driver/opae/vlsim/Makefile b/driver/opae/vlsim/Makefile index f1ec2435..0da26503 100644 --- a/driver/opae/vlsim/Makefile +++ b/driver/opae/vlsim/Makefile @@ -20,7 +20,7 @@ DBG_PRINT_FLAGS += -DDBG_PRINT_SCOPE DBG_FLAGS += $(DBG_PRINT_FLAGS) DBG_FLAGS += -DDBG_CACHE_REQ_INFO -#CONFIGS ?= -DNUM_CLUSTERS=2 -DNUM_CORES=4 -DL2_ENABLE=1 -DL3_ENABLE=1 +#CONFIGS ?= -DNUM_CLUSTERS=2 -DNUM_CORES=4 -DL2_ENABLE=1 #CONFIGS ?= -DNUM_CLUSTERS=1 -DNUM_CORES=4 -DL2_ENABLE=1 CONFIGS ?= -DNUM_CLUSTERS=1 -DNUM_CORES=2 -DL2_ENABLE=0 #CONFIGS ?= -DNUM_CLUSTERS=1 -DNUM_CORES=1 diff --git a/driver/rtlsim/Makefile b/driver/rtlsim/Makefile index a6da4390..acbcfd44 100644 --- a/driver/rtlsim/Makefile +++ b/driver/rtlsim/Makefile @@ -20,7 +20,7 @@ DBG_PRINT_FLAGS += -DDBG_PRINT_SCOPE DBG_FLAGS += $(DBG_PRINT_FLAGS) DBG_FLAGS += -DDBG_CACHE_REQ_INFO -#CONFIGS ?= -DNUM_CLUSTERS=2 -DNUM_CORES=4 -DL2_ENABLE=1 -DL3_ENABLE=1 +#CONFIGS ?= -DNUM_CLUSTERS=2 -DNUM_CORES=4 -DL2_ENABLE=1 #CONFIGS ?= -DNUM_CLUSTERS=1 -DNUM_CORES=4 -DL2_ENABLE=1 CONFIGS ?= -DNUM_CLUSTERS=1 -DNUM_CORES=2 -DL2_ENABLE=0 #CONFIGS ?= -DNUM_CLUSTERS=1 -DNUM_CORES=1 diff --git a/hw/rtl/cache/VX_data_access.v b/hw/rtl/cache/VX_data_access.v index 3b78271d..d0284445 100644 --- a/hw/rtl/cache/VX_data_access.v +++ b/hw/rtl/cache/VX_data_access.v @@ -86,7 +86,7 @@ module VX_data_access #( .write_data (use_write_data) ); - assign use_read_dirtyb_out= qual_read_dirtyb_out; + assign use_read_dirtyb_out = qual_read_dirtyb_out; assign use_read_data = qual_read_data; if (`WORD_SELECT_WIDTH != 0) begin diff --git a/hw/rtl/cache/VX_tag_access.v b/hw/rtl/cache/VX_tag_access.v index fe87f0f6..3f0f0804 100644 --- a/hw/rtl/cache/VX_tag_access.v +++ b/hw/rtl/cache/VX_tag_access.v @@ -119,19 +119,21 @@ module VX_tag_access #( assign miss_out = core_req_miss; assign dirty_out = valid_in && use_read_valid && use_read_dirty - && !(is_fill_in && tags_match); // disable writeback for redundant fills + && !(is_fill_in && tags_match); // discard writeback for redundant fills assign readtag_out = use_read_tag; - assign writeen_out = (use_do_write || use_do_fill); + + assign writeen_out = use_do_write || (use_do_fill + && !tags_match); // discard data update for redundant fills `ifdef DBG_PRINT_CACHE_TAG always @(posedge clk) begin if (valid_in && !stall) begin - if (use_do_fill && tags_match) begin - $display("%t: warning: redundant fill - addr=%0h", $time, `LINE_TO_BYTE_ADDR(addr_in, BANK_ID)); - end if (use_do_fill) begin $display("%t: cache%0d:%0d tag-fill: addr=%0h, blk_addr=%0d, tag_id=%0h, old_tag_id=%0h", $time, CACHE_ID, BANK_ID, `LINE_TO_BYTE_ADDR(addr_in, BANK_ID), addrline, addrtag, qual_read_tag); + if (tags_match) begin + $display("%t: warning: redundant fill - addr=%0h", $time, `LINE_TO_BYTE_ADDR(addr_in, BANK_ID)); + end end else if (tags_match) begin $display("%t: cache%0d:%0d tag-hit: addr=%0h, wid=%0d, PC=%0h, dirty=%b, blk_addr=%0d, tag_id=%0h", $time, CACHE_ID, BANK_ID, `LINE_TO_BYTE_ADDR(addr_in, BANK_ID), debug_wid, debug_pc, use_read_dirty, addrline, addrtag); end else begin