wu-arch/vortex
1
0
Fork 0
Code Issues Pull Requests Actions Packages Projects Releases Wiki Activity

Migrating fpga_synthesis_temp to main

Browse Source
This commit is contained in:
felsabbagh3
2020-03-27 13:15:23 -07:00
parent 6dc3d0d371
commit 614797e52f
5 changed files with 25 additions and 13 deletions
Download Patch File Download Diff File Expand all files Collapse all files

12
rtl/VX_lsu.v
View File

@@ -69,7 +69,16 @@ module VX_lsu (
assign VX_mem_wb.wb_valid = VX_dcache_rsp.core_wb_valid;
assign VX_mem_wb.wb_warp_num = VX_dcache_rsp.core_wb_warp_num;
assign VX_mem_wb.loaded_data = VX_dcache_rsp.core_wb_readdata;
assign VX_mem_wb.mem_wb_pc = VX_dcache_rsp.core_wb_pc[0];
wire[(`CLOG2(`NT))-1:0] use_pc_index;
wire found;
VX_generic_priority_encoder #(.N(`NT)) pick_first_pc(
.valids(VX_dcache_rsp.core_wb_valid),
.index (use_pc_index),
.found (found)
);
assign VX_mem_wb.mem_wb_pc = VX_dcache_rsp.core_wb_pc[use_pc_index];
@@ -78,3 +87,4 @@ module VX_lsu (
endmodule // Memory