OPAE rtl fixes
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5
hw/rtl/cache/VX_bank.v
vendored
5
hw/rtl/cache/VX_bank.v
vendored
@@ -245,6 +245,8 @@ module VX_bank #(
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wire[`LINE_ADDR_WIDTH-1:0] addr_st2;
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wire is_fill_st2;
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wire recover_mrvq_state_st2;
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wire mrvq_push_stall;
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wire cwbq_push_stall;
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wire dwbq_push_stall;
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@@ -471,8 +473,7 @@ module VX_bank #(
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wire mrvq_init_ready_state_unqual_st2;
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wire mrvq_init_ready_state_hazard_st0_st1;
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wire mrvq_init_ready_state_hazard_st1e_st1;
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wire recover_mrvq_state_st2;
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VX_generic_register #(
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.N(1+ 1+ 1 + 1 + 1 + 1 + 1 + 1 + `LINE_ADDR_WIDTH + `BASE_ADDR_BITS + `WORD_WIDTH + `WORD_WIDTH + `BANK_LINE_WIDTH + `TAG_SELECT_BITS + 1 + 1 + `REQ_INST_META_WIDTH)
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) st_1e_2 (
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