diff --git a/hw/opae/sources.txt b/hw/opae/sources.txt index a4eb9bdf..e71c2d79 100644 --- a/hw/opae/sources.txt +++ b/hw/opae/sources.txt @@ -74,9 +74,9 @@ QI:vortex_afu.qsf ../rtl/libs/VX_countones.v ../rtl/libs/VX_scope.v -../rtl/Vortex_Socket.v -../rtl/Vortex_Cluster.v ../rtl/Vortex.v +../rtl/VX_cluster.v +../rtl/VX_core.v ../rtl/VX_mem_unit.v ../rtl/VX_pipeline.v ../rtl/VX_front_end.v diff --git a/hw/opae/vortex_afu.sv b/hw/opae/vortex_afu.sv index 09805c37..a39b9691 100644 --- a/hw/opae/vortex_afu.sv +++ b/hw/opae/vortex_afu.sv @@ -883,7 +883,7 @@ VX_scope #( assign cmd_run_done = !vx_busy; -Vortex_Socket #() vx_socket ( +Vortex #() vortex ( `SCOPE_SIGNALS_ISTAGE_BIND `SCOPE_SIGNALS_LSU_BIND `SCOPE_SIGNALS_CORE_BIND diff --git a/hw/rtl/Vortex_Cluster.v b/hw/rtl/VX_cluster.v similarity index 99% rename from hw/rtl/Vortex_Cluster.v rename to hw/rtl/VX_cluster.v index 7237bc02..cb7ff4db 100644 --- a/hw/rtl/Vortex_Cluster.v +++ b/hw/rtl/VX_cluster.v @@ -1,6 +1,6 @@ `include "VX_define.vh" -module Vortex_Cluster #( +module VX_cluster #( parameter CLUSTER_ID = 0 ) ( `SCOPE_SIGNALS_ISTAGE_IO @@ -114,9 +114,9 @@ module Vortex_Cluster #( genvar i; for (i = 0; i < `NUM_CORES; i++) begin - Vortex #( + VX_core #( .CORE_ID(i + (CLUSTER_ID * `NUM_CORES)) - ) vortex_core ( + ) core ( `SCOPE_SIGNALS_ISTAGE_BIND `SCOPE_SIGNALS_LSU_BIND `SCOPE_SIGNALS_CORE_BIND diff --git a/hw/rtl/VX_core.v b/hw/rtl/VX_core.v new file mode 100644 index 00000000..7ce25bbd --- /dev/null +++ b/hw/rtl/VX_core.v @@ -0,0 +1,283 @@ +`include "VX_define.vh" + +module VX_core #( + parameter CORE_ID = 0 +) ( + `SCOPE_SIGNALS_ISTAGE_IO + `SCOPE_SIGNALS_LSU_IO + `SCOPE_SIGNALS_CORE_IO + `SCOPE_SIGNALS_ICACHE_IO + `SCOPE_SIGNALS_PIPELINE_IO + `SCOPE_SIGNALS_BE_IO + + // Clock + input wire clk, + input wire reset, + + // DRAM Dcache request + output wire D_dram_req_valid, + output wire D_dram_req_rw, + output wire [`DDRAM_BYTEEN_WIDTH-1:0] D_dram_req_byteen, + output wire [`DDRAM_ADDR_WIDTH-1:0] D_dram_req_addr, + output wire [`DDRAM_LINE_WIDTH-1:0] D_dram_req_data, + output wire [`DDRAM_TAG_WIDTH-1:0] D_dram_req_tag, + input wire D_dram_req_ready, + + // DRAM Dcache reponse + input wire D_dram_rsp_valid, + input wire [`DDRAM_LINE_WIDTH-1:0] D_dram_rsp_data, + input wire [`DDRAM_TAG_WIDTH-1:0] D_dram_rsp_tag, + output wire D_dram_rsp_ready, + + // DRAM Icache request + output wire I_dram_req_valid, + output wire I_dram_req_rw, + output wire [`IDRAM_BYTEEN_WIDTH-1:0] I_dram_req_byteen, + output wire [`IDRAM_ADDR_WIDTH-1:0] I_dram_req_addr, + output wire [`IDRAM_LINE_WIDTH-1:0] I_dram_req_data, + output wire [`IDRAM_TAG_WIDTH-1:0] I_dram_req_tag, + input wire I_dram_req_ready, + + // DRAM Icache response + input wire I_dram_rsp_valid, + input wire [`IDRAM_LINE_WIDTH-1:0] I_dram_rsp_data, + input wire [`IDRAM_TAG_WIDTH-1:0] I_dram_rsp_tag, + output wire I_dram_rsp_ready, + + // Snoop request + input wire snp_req_valid, + input wire [`DDRAM_ADDR_WIDTH-1:0] snp_req_addr, + input wire snp_req_invalidate, + input wire [`DSNP_TAG_WIDTH-1:0] snp_req_tag, + output wire snp_req_ready, + + output wire snp_rsp_valid, + output wire [`DSNP_TAG_WIDTH-1:0] snp_rsp_tag, + input wire snp_rsp_ready, + + // I/O request + output wire io_req_valid, + output wire io_req_rw, + output wire [3:0] io_req_byteen, + output wire [29:0] io_req_addr, + output wire [31:0] io_req_data, + output wire [`DCORE_TAG_WIDTH-1:0] io_req_tag, + input wire io_req_ready, + + // I/O response + input wire io_rsp_valid, + input wire [31:0] io_rsp_data, + input wire [`DCORE_TAG_WIDTH-1:0] io_rsp_tag, + output wire io_rsp_ready, + + // Status + output wire busy, + output wire ebreak +); + // Dcache Interfaces + + VX_cache_dram_req_if #( + .DRAM_LINE_WIDTH(`DDRAM_LINE_WIDTH), + .DRAM_ADDR_WIDTH(`DDRAM_ADDR_WIDTH), + .DRAM_TAG_WIDTH(`DDRAM_TAG_WIDTH) + ) dcache_dram_req_if(); + + VX_cache_dram_rsp_if #( + .DRAM_LINE_WIDTH(`DDRAM_LINE_WIDTH), + .DRAM_TAG_WIDTH(`DDRAM_TAG_WIDTH) + ) dcache_dram_rsp_if(); + + assign D_dram_req_valid = dcache_dram_req_if.dram_req_valid; + assign D_dram_req_rw = dcache_dram_req_if.dram_req_rw; + assign D_dram_req_byteen= dcache_dram_req_if.dram_req_byteen; + assign D_dram_req_addr = dcache_dram_req_if.dram_req_addr; + assign D_dram_req_data = dcache_dram_req_if.dram_req_data; + assign D_dram_req_tag = dcache_dram_req_if.dram_req_tag; + assign dcache_dram_req_if.dram_req_ready = D_dram_req_ready; + + assign dcache_dram_rsp_if.dram_rsp_valid = D_dram_rsp_valid; + assign dcache_dram_rsp_if.dram_rsp_data = D_dram_rsp_data; + assign dcache_dram_rsp_if.dram_rsp_tag = D_dram_rsp_tag; + assign D_dram_rsp_ready = dcache_dram_rsp_if.dram_rsp_ready; + + VX_cache_core_req_if #( + .NUM_REQUESTS(`DNUM_REQUESTS), + .WORD_SIZE(`DWORD_SIZE), + .CORE_TAG_WIDTH(`DCORE_TAG_WIDTH), + .CORE_TAG_ID_BITS(`DCORE_TAG_ID_BITS) + ) core_dcache_req_if(),arb_dcache_req_if(), arb_io_req_if(); + + VX_cache_core_rsp_if #( + .NUM_REQUESTS(`DNUM_REQUESTS), + .WORD_SIZE(`DWORD_SIZE), + .CORE_TAG_WIDTH(`DCORE_TAG_WIDTH), + .CORE_TAG_ID_BITS(`DCORE_TAG_ID_BITS) + ) core_dcache_rsp_if(), arb_dcache_rsp_if(), arb_io_rsp_if(); + + assign io_req_valid = arb_io_req_if.core_req_valid[0]; + assign io_req_rw = arb_io_req_if.core_req_rw[0]; + assign io_req_byteen = arb_io_req_if.core_req_byteen[0]; + assign io_req_addr = arb_io_req_if.core_req_addr[0]; + assign io_req_data = arb_io_req_if.core_req_data[0]; + assign io_req_tag = arb_io_req_if.core_req_tag[0]; + assign arb_io_req_if.core_req_ready = io_req_ready; + + assign arb_io_rsp_if.core_rsp_valid = {{(`NUM_THREADS-1){1'b0}}, io_rsp_valid}; + assign arb_io_rsp_if.core_rsp_data[0] = io_rsp_data; + assign arb_io_rsp_if.core_rsp_tag = io_rsp_tag; + assign io_rsp_ready = arb_io_rsp_if.core_rsp_ready; + + // Icache interfaces + + VX_cache_dram_req_if #( + .DRAM_LINE_WIDTH(`IDRAM_LINE_WIDTH), + .DRAM_ADDR_WIDTH(`IDRAM_ADDR_WIDTH), + .DRAM_TAG_WIDTH(`IDRAM_TAG_WIDTH) + ) icache_dram_req_if(); + + VX_cache_dram_rsp_if #( + .DRAM_LINE_WIDTH(`IDRAM_LINE_WIDTH), + .DRAM_TAG_WIDTH(`IDRAM_TAG_WIDTH) + ) icache_dram_rsp_if(); + + assign I_dram_req_valid = icache_dram_req_if.dram_req_valid; + assign I_dram_req_rw = icache_dram_req_if.dram_req_rw; + assign I_dram_req_byteen= icache_dram_req_if.dram_req_byteen; + assign I_dram_req_addr = icache_dram_req_if.dram_req_addr; + assign I_dram_req_data = icache_dram_req_if.dram_req_data; + assign I_dram_req_tag = icache_dram_req_if.dram_req_tag; + assign icache_dram_req_if.dram_req_ready = I_dram_req_ready; + + assign icache_dram_rsp_if.dram_rsp_valid = I_dram_rsp_valid; + assign icache_dram_rsp_if.dram_rsp_data = I_dram_rsp_data; + assign icache_dram_rsp_if.dram_rsp_tag = I_dram_rsp_tag; + assign I_dram_rsp_ready = icache_dram_rsp_if.dram_rsp_ready; + + VX_cache_core_req_if #( + .NUM_REQUESTS(`INUM_REQUESTS), + .WORD_SIZE(`IWORD_SIZE), + .CORE_TAG_WIDTH(`DCORE_TAG_WIDTH), + .CORE_TAG_ID_BITS(`DCORE_TAG_ID_BITS) + ) core_icache_req_if(); + + VX_cache_core_rsp_if #( + .NUM_REQUESTS(`INUM_REQUESTS), + .WORD_SIZE(`IWORD_SIZE), + .CORE_TAG_WIDTH(`DCORE_TAG_WIDTH), + .CORE_TAG_ID_BITS(`DCORE_TAG_ID_BITS) + ) core_icache_rsp_if(); + + VX_pipeline #( + .CORE_ID(CORE_ID) + ) pipeline ( + `SCOPE_SIGNALS_ISTAGE_BIND + `SCOPE_SIGNALS_LSU_BIND + `SCOPE_SIGNALS_PIPELINE_BIND + `SCOPE_SIGNALS_BE_BIND + + .clk(clk), + .reset(reset), + + // Dcache core request + .dcache_req_valid (core_dcache_req_if.core_req_valid), + .dcache_req_rw (core_dcache_req_if.core_req_rw), + .dcache_req_byteen (core_dcache_req_if.core_req_byteen), + .dcache_req_addr (core_dcache_req_if.core_req_addr), + .dcache_req_data (core_dcache_req_if.core_req_data), + .dcache_req_tag (core_dcache_req_if.core_req_tag), + .dcache_req_ready (core_dcache_req_if.core_req_ready), + + // Dcache core reponse + .dcache_rsp_valid (core_dcache_rsp_if.core_rsp_valid), + .dcache_rsp_data (core_dcache_rsp_if.core_rsp_data), + .dcache_rsp_tag (core_dcache_rsp_if.core_rsp_tag), + .dcache_rsp_ready (core_dcache_rsp_if.core_rsp_ready), + + // Dcache core request + .icache_req_valid (core_icache_req_if.core_req_valid), + .icache_req_rw (core_icache_req_if.core_req_rw), + .icache_req_byteen (core_icache_req_if.core_req_byteen), + .icache_req_addr (core_icache_req_if.core_req_addr), + .icache_req_data (core_icache_req_if.core_req_data), + .icache_req_tag (core_icache_req_if.core_req_tag), + .icache_req_ready (core_icache_req_if.core_req_ready), + + // Dcache core reponse + .icache_rsp_valid (core_icache_rsp_if.core_rsp_valid), + .icache_rsp_data (core_icache_rsp_if.core_rsp_data), + .icache_rsp_tag (core_icache_rsp_if.core_rsp_tag), + .icache_rsp_ready (core_icache_rsp_if.core_rsp_ready), + + // Status + .busy(busy), + .ebreak(ebreak) + ); + + // Cache snooping interfaces + + VX_cache_snp_req_if #( + .DRAM_ADDR_WIDTH(`DDRAM_ADDR_WIDTH), + .SNP_TAG_WIDTH(`DSNP_TAG_WIDTH) + ) dcache_snp_req_if(); + + VX_cache_snp_rsp_if #( + .SNP_TAG_WIDTH(`DSNP_TAG_WIDTH) + ) dcache_snp_rsp_if(); + + assign dcache_snp_req_if.snp_req_valid = snp_req_valid; + assign dcache_snp_req_if.snp_req_addr = snp_req_addr; + assign dcache_snp_req_if.snp_req_invalidate = snp_req_invalidate; + assign dcache_snp_req_if.snp_req_tag = snp_req_tag; + assign snp_req_ready = dcache_snp_req_if.snp_req_ready; + + assign snp_rsp_valid = dcache_snp_rsp_if.snp_rsp_valid; + assign snp_rsp_tag = dcache_snp_rsp_if.snp_rsp_tag; + assign dcache_snp_rsp_if.snp_rsp_ready = snp_rsp_ready; + + VX_mem_unit #( + .CORE_ID(CORE_ID) + ) mem_unit ( + `SCOPE_SIGNALS_ICACHE_BIND + + .clk (clk), + .reset (reset), + + // Core <-> Dcache + .core_dcache_req_if (arb_dcache_req_if), + .core_dcache_rsp_if (arb_dcache_rsp_if), + + // Dram <-> Dcache + .dcache_dram_req_if (dcache_dram_req_if), + .dcache_dram_rsp_if (dcache_dram_rsp_if), + .dcache_snp_req_if (dcache_snp_req_if), + .dcache_snp_rsp_if (dcache_snp_rsp_if), + + // Core <-> Icache + .core_icache_req_if (core_icache_req_if), + .core_icache_rsp_if (core_icache_rsp_if), + + // Dram <-> Icache + .icache_dram_req_if (icache_dram_req_if), + .icache_dram_rsp_if (icache_dram_rsp_if) + ); + + // select io address + wire is_io_addr = ({core_dcache_req_if.core_req_addr[0], 2'b0} >= `IO_BUS_BASE_ADDR); + wire io_select = (| core_dcache_req_if.core_req_valid) ? is_io_addr : 0; + + VX_dcache_arb dcache_io_arb ( + .req_select (io_select), + .in_core_req_if (core_dcache_req_if), + .out0_core_req_if (arb_dcache_req_if), + .out1_core_req_if (arb_io_req_if), + .in0_core_rsp_if (arb_dcache_rsp_if), + .in1_core_rsp_if (arb_io_rsp_if), + .out_core_rsp_if (core_dcache_rsp_if) + ); + +endmodule + + + + + diff --git a/hw/rtl/VX_pipeline.v b/hw/rtl/VX_pipeline.v index a6e99394..282a38ff 100644 --- a/hw/rtl/VX_pipeline.v +++ b/hw/rtl/VX_pipeline.v @@ -191,4 +191,4 @@ module VX_pipeline #( end `endif -endmodule // Vortex \ No newline at end of file +endmodule \ No newline at end of file diff --git a/hw/rtl/Vortex.v b/hw/rtl/Vortex.v index f95acee0..a4a961b3 100644 --- a/hw/rtl/Vortex.v +++ b/hw/rtl/Vortex.v @@ -1,283 +1,406 @@ -`include "VX_define.vh" - -module Vortex #( - parameter CORE_ID = 0 -) ( - `SCOPE_SIGNALS_ISTAGE_IO - `SCOPE_SIGNALS_LSU_IO - `SCOPE_SIGNALS_CORE_IO - `SCOPE_SIGNALS_ICACHE_IO - `SCOPE_SIGNALS_PIPELINE_IO - `SCOPE_SIGNALS_BE_IO - - // Clock - input wire clk, - input wire reset, - - // DRAM Dcache request - output wire D_dram_req_valid, - output wire D_dram_req_rw, - output wire [`DDRAM_BYTEEN_WIDTH-1:0] D_dram_req_byteen, - output wire [`DDRAM_ADDR_WIDTH-1:0] D_dram_req_addr, - output wire [`DDRAM_LINE_WIDTH-1:0] D_dram_req_data, - output wire [`DDRAM_TAG_WIDTH-1:0] D_dram_req_tag, - input wire D_dram_req_ready, - - // DRAM Dcache reponse - input wire D_dram_rsp_valid, - input wire [`DDRAM_LINE_WIDTH-1:0] D_dram_rsp_data, - input wire [`DDRAM_TAG_WIDTH-1:0] D_dram_rsp_tag, - output wire D_dram_rsp_ready, - - // DRAM Icache request - output wire I_dram_req_valid, - output wire I_dram_req_rw, - output wire [`IDRAM_BYTEEN_WIDTH-1:0] I_dram_req_byteen, - output wire [`IDRAM_ADDR_WIDTH-1:0] I_dram_req_addr, - output wire [`IDRAM_LINE_WIDTH-1:0] I_dram_req_data, - output wire [`IDRAM_TAG_WIDTH-1:0] I_dram_req_tag, - input wire I_dram_req_ready, - - // DRAM Icache response - input wire I_dram_rsp_valid, - input wire [`IDRAM_LINE_WIDTH-1:0] I_dram_rsp_data, - input wire [`IDRAM_TAG_WIDTH-1:0] I_dram_rsp_tag, - output wire I_dram_rsp_ready, - - // Snoop request - input wire snp_req_valid, - input wire [`DDRAM_ADDR_WIDTH-1:0] snp_req_addr, - input wire snp_req_invalidate, - input wire [`DSNP_TAG_WIDTH-1:0] snp_req_tag, - output wire snp_req_ready, - - output wire snp_rsp_valid, - output wire [`DSNP_TAG_WIDTH-1:0] snp_rsp_tag, - input wire snp_rsp_ready, - - // I/O request - output wire io_req_valid, - output wire io_req_rw, - output wire [3:0] io_req_byteen, - output wire [29:0] io_req_addr, - output wire [31:0] io_req_data, - output wire [`DCORE_TAG_WIDTH-1:0] io_req_tag, - input wire io_req_ready, - - // I/O response - input wire io_rsp_valid, - input wire [31:0] io_rsp_data, - input wire [`DCORE_TAG_WIDTH-1:0] io_rsp_tag, - output wire io_rsp_ready, - - // Status - output wire busy, - output wire ebreak -); - // Dcache Interfaces - - VX_cache_dram_req_if #( - .DRAM_LINE_WIDTH(`DDRAM_LINE_WIDTH), - .DRAM_ADDR_WIDTH(`DDRAM_ADDR_WIDTH), - .DRAM_TAG_WIDTH(`DDRAM_TAG_WIDTH) - ) dcache_dram_req_if(); - - VX_cache_dram_rsp_if #( - .DRAM_LINE_WIDTH(`DDRAM_LINE_WIDTH), - .DRAM_TAG_WIDTH(`DDRAM_TAG_WIDTH) - ) dcache_dram_rsp_if(); - - assign D_dram_req_valid = dcache_dram_req_if.dram_req_valid; - assign D_dram_req_rw = dcache_dram_req_if.dram_req_rw; - assign D_dram_req_byteen= dcache_dram_req_if.dram_req_byteen; - assign D_dram_req_addr = dcache_dram_req_if.dram_req_addr; - assign D_dram_req_data = dcache_dram_req_if.dram_req_data; - assign D_dram_req_tag = dcache_dram_req_if.dram_req_tag; - assign dcache_dram_req_if.dram_req_ready = D_dram_req_ready; - - assign dcache_dram_rsp_if.dram_rsp_valid = D_dram_rsp_valid; - assign dcache_dram_rsp_if.dram_rsp_data = D_dram_rsp_data; - assign dcache_dram_rsp_if.dram_rsp_tag = D_dram_rsp_tag; - assign D_dram_rsp_ready = dcache_dram_rsp_if.dram_rsp_ready; - - VX_cache_core_req_if #( - .NUM_REQUESTS(`DNUM_REQUESTS), - .WORD_SIZE(`DWORD_SIZE), - .CORE_TAG_WIDTH(`DCORE_TAG_WIDTH), - .CORE_TAG_ID_BITS(`DCORE_TAG_ID_BITS) - ) core_dcache_req_if(),arb_dcache_req_if(), arb_io_req_if(); - - VX_cache_core_rsp_if #( - .NUM_REQUESTS(`DNUM_REQUESTS), - .WORD_SIZE(`DWORD_SIZE), - .CORE_TAG_WIDTH(`DCORE_TAG_WIDTH), - .CORE_TAG_ID_BITS(`DCORE_TAG_ID_BITS) - ) core_dcache_rsp_if(), arb_dcache_rsp_if(), arb_io_rsp_if(); - - assign io_req_valid = arb_io_req_if.core_req_valid[0]; - assign io_req_rw = arb_io_req_if.core_req_rw[0]; - assign io_req_byteen = arb_io_req_if.core_req_byteen[0]; - assign io_req_addr = arb_io_req_if.core_req_addr[0]; - assign io_req_data = arb_io_req_if.core_req_data[0]; - assign io_req_tag = arb_io_req_if.core_req_tag[0]; - assign arb_io_req_if.core_req_ready = io_req_ready; - - assign arb_io_rsp_if.core_rsp_valid = {{(`NUM_THREADS-1){1'b0}}, io_rsp_valid}; - assign arb_io_rsp_if.core_rsp_data[0] = io_rsp_data; - assign arb_io_rsp_if.core_rsp_tag = io_rsp_tag; - assign io_rsp_ready = arb_io_rsp_if.core_rsp_ready; - - // Icache interfaces - - VX_cache_dram_req_if #( - .DRAM_LINE_WIDTH(`IDRAM_LINE_WIDTH), - .DRAM_ADDR_WIDTH(`IDRAM_ADDR_WIDTH), - .DRAM_TAG_WIDTH(`IDRAM_TAG_WIDTH) - ) icache_dram_req_if(); - - VX_cache_dram_rsp_if #( - .DRAM_LINE_WIDTH(`IDRAM_LINE_WIDTH), - .DRAM_TAG_WIDTH(`IDRAM_TAG_WIDTH) - ) icache_dram_rsp_if(); - - assign I_dram_req_valid = icache_dram_req_if.dram_req_valid; - assign I_dram_req_rw = icache_dram_req_if.dram_req_rw; - assign I_dram_req_byteen= icache_dram_req_if.dram_req_byteen; - assign I_dram_req_addr = icache_dram_req_if.dram_req_addr; - assign I_dram_req_data = icache_dram_req_if.dram_req_data; - assign I_dram_req_tag = icache_dram_req_if.dram_req_tag; - assign icache_dram_req_if.dram_req_ready = I_dram_req_ready; - - assign icache_dram_rsp_if.dram_rsp_valid = I_dram_rsp_valid; - assign icache_dram_rsp_if.dram_rsp_data = I_dram_rsp_data; - assign icache_dram_rsp_if.dram_rsp_tag = I_dram_rsp_tag; - assign I_dram_rsp_ready = icache_dram_rsp_if.dram_rsp_ready; - - VX_cache_core_req_if #( - .NUM_REQUESTS(`INUM_REQUESTS), - .WORD_SIZE(`IWORD_SIZE), - .CORE_TAG_WIDTH(`DCORE_TAG_WIDTH), - .CORE_TAG_ID_BITS(`DCORE_TAG_ID_BITS) - ) core_icache_req_if(); - - VX_cache_core_rsp_if #( - .NUM_REQUESTS(`INUM_REQUESTS), - .WORD_SIZE(`IWORD_SIZE), - .CORE_TAG_WIDTH(`DCORE_TAG_WIDTH), - .CORE_TAG_ID_BITS(`DCORE_TAG_ID_BITS) - ) core_icache_rsp_if(); - - // Vortex pipeline - VX_pipeline #( - .CORE_ID(CORE_ID) - ) pipeline ( - `SCOPE_SIGNALS_ISTAGE_BIND - `SCOPE_SIGNALS_LSU_BIND - `SCOPE_SIGNALS_PIPELINE_BIND - `SCOPE_SIGNALS_BE_BIND - - .clk(clk), - .reset(reset), - - // Dcache core request - .dcache_req_valid (core_dcache_req_if.core_req_valid), - .dcache_req_rw (core_dcache_req_if.core_req_rw), - .dcache_req_byteen (core_dcache_req_if.core_req_byteen), - .dcache_req_addr (core_dcache_req_if.core_req_addr), - .dcache_req_data (core_dcache_req_if.core_req_data), - .dcache_req_tag (core_dcache_req_if.core_req_tag), - .dcache_req_ready (core_dcache_req_if.core_req_ready), - - // Dcache core reponse - .dcache_rsp_valid (core_dcache_rsp_if.core_rsp_valid), - .dcache_rsp_data (core_dcache_rsp_if.core_rsp_data), - .dcache_rsp_tag (core_dcache_rsp_if.core_rsp_tag), - .dcache_rsp_ready (core_dcache_rsp_if.core_rsp_ready), - - // Dcache core request - .icache_req_valid (core_icache_req_if.core_req_valid), - .icache_req_rw (core_icache_req_if.core_req_rw), - .icache_req_byteen (core_icache_req_if.core_req_byteen), - .icache_req_addr (core_icache_req_if.core_req_addr), - .icache_req_data (core_icache_req_if.core_req_data), - .icache_req_tag (core_icache_req_if.core_req_tag), - .icache_req_ready (core_icache_req_if.core_req_ready), - - // Dcache core reponse - .icache_rsp_valid (core_icache_rsp_if.core_rsp_valid), - .icache_rsp_data (core_icache_rsp_if.core_rsp_data), - .icache_rsp_tag (core_icache_rsp_if.core_rsp_tag), - .icache_rsp_ready (core_icache_rsp_if.core_rsp_ready), - - // Status - .busy(busy), - .ebreak(ebreak) - ); - - // Cache snooping - VX_cache_snp_req_if #( - .DRAM_ADDR_WIDTH(`DDRAM_ADDR_WIDTH), - .SNP_TAG_WIDTH(`DSNP_TAG_WIDTH) - ) dcache_snp_req_if(); - - VX_cache_snp_rsp_if #( - .SNP_TAG_WIDTH(`DSNP_TAG_WIDTH) - ) dcache_snp_rsp_if(); - - assign dcache_snp_req_if.snp_req_valid = snp_req_valid; - assign dcache_snp_req_if.snp_req_addr = snp_req_addr; - assign dcache_snp_req_if.snp_req_invalidate = snp_req_invalidate; - assign dcache_snp_req_if.snp_req_tag = snp_req_tag; - assign snp_req_ready = dcache_snp_req_if.snp_req_ready; - - assign snp_rsp_valid = dcache_snp_rsp_if.snp_rsp_valid; - assign snp_rsp_tag = dcache_snp_rsp_if.snp_rsp_tag; - assign dcache_snp_rsp_if.snp_rsp_ready = snp_rsp_ready; - - VX_mem_unit #( - .CORE_ID(CORE_ID) - ) mem_unit ( - `SCOPE_SIGNALS_ICACHE_BIND - - .clk (clk), - .reset (reset), - - // Core <-> Dcache - .core_dcache_req_if (arb_dcache_req_if), - .core_dcache_rsp_if (arb_dcache_rsp_if), - - // Dram <-> Dcache - .dcache_dram_req_if (dcache_dram_req_if), - .dcache_dram_rsp_if (dcache_dram_rsp_if), - .dcache_snp_req_if (dcache_snp_req_if), - .dcache_snp_rsp_if (dcache_snp_rsp_if), - - // Core <-> Icache - .core_icache_req_if (core_icache_req_if), - .core_icache_rsp_if (core_icache_rsp_if), - - // Dram <-> Icache - .icache_dram_req_if (icache_dram_req_if), - .icache_dram_rsp_if (icache_dram_rsp_if) - ); - - // select io address - wire is_io_addr = ({core_dcache_req_if.core_req_addr[0], 2'b0} >= `IO_BUS_BASE_ADDR); - wire io_select = (| core_dcache_req_if.core_req_valid) ? is_io_addr : 0; - - VX_dcache_arb dcache_io_arb ( - .req_select (io_select), - .in_core_req_if (core_dcache_req_if), - .out0_core_req_if (arb_dcache_req_if), - .out1_core_req_if (arb_io_req_if), - .in0_core_rsp_if (arb_dcache_rsp_if), - .in1_core_rsp_if (arb_io_rsp_if), - .out_core_rsp_if (core_dcache_rsp_if) - ); - -endmodule // Vortex - - - - - +`include "VX_define.vh" + +module Vortex ( + `SCOPE_SIGNALS_ISTAGE_IO + `SCOPE_SIGNALS_LSU_IO + `SCOPE_SIGNALS_CORE_IO + `SCOPE_SIGNALS_ICACHE_IO + `SCOPE_SIGNALS_PIPELINE_IO + `SCOPE_SIGNALS_BE_IO + + // Clock + input wire clk, + input wire reset, + + // DRAM request + output wire dram_req_valid, + output wire dram_req_rw, + output wire [`VX_DRAM_BYTEEN_WIDTH-1:0] dram_req_byteen, + output wire [`VX_DRAM_ADDR_WIDTH-1:0] dram_req_addr, + output wire [`VX_DRAM_LINE_WIDTH-1:0] dram_req_data, + output wire [`VX_DRAM_TAG_WIDTH-1:0] dram_req_tag, + input wire dram_req_ready, + + // DRAM response + input wire dram_rsp_valid, + input wire [`VX_DRAM_LINE_WIDTH-1:0] dram_rsp_data, + input wire [`VX_DRAM_TAG_WIDTH-1:0] dram_rsp_tag, + output wire dram_rsp_ready, + + // Snoop request + input wire snp_req_valid, + input wire [`VX_DRAM_ADDR_WIDTH-1:0] snp_req_addr, + input wire snp_req_invalidate, + input wire [`VX_SNP_TAG_WIDTH-1:0] snp_req_tag, + output wire snp_req_ready, + + // Snoop response + output wire snp_rsp_valid, + output wire [`VX_SNP_TAG_WIDTH-1:0] snp_rsp_tag, + input wire snp_rsp_ready, + + // I/O request + output wire io_req_valid, + output wire io_req_rw, + output wire [3:0] io_req_byteen, + output wire [29:0] io_req_addr, + output wire [31:0] io_req_data, + output wire [`VX_CORE_TAG_WIDTH-1:0] io_req_tag, + input wire io_req_ready, + + // I/O response + input wire io_rsp_valid, + input wire [31:0] io_rsp_data, + input wire [`VX_CORE_TAG_WIDTH-1:0] io_rsp_tag, + output wire io_rsp_ready, + + // Status + output wire busy, + output wire ebreak +); + if (`NUM_CLUSTERS == 1) begin + + VX_cluster #( + .CLUSTER_ID(`L3CACHE_ID) + ) cluster ( + `SCOPE_SIGNALS_ISTAGE_BIND + `SCOPE_SIGNALS_LSU_BIND + `SCOPE_SIGNALS_CORE_BIND + `SCOPE_SIGNALS_ICACHE_BIND + `SCOPE_SIGNALS_PIPELINE_BIND + `SCOPE_SIGNALS_BE_BIND + + .clk (clk), + .reset (reset), + + .dram_req_valid (dram_req_valid), + .dram_req_rw (dram_req_rw), + .dram_req_byteen (dram_req_byteen), + .dram_req_addr (dram_req_addr), + .dram_req_data (dram_req_data), + .dram_req_tag (dram_req_tag), + .dram_req_ready (dram_req_ready), + + .dram_rsp_valid (dram_rsp_valid), + .dram_rsp_data (dram_rsp_data), + .dram_rsp_tag (dram_rsp_tag), + .dram_rsp_ready (dram_rsp_ready), + + .snp_req_valid (snp_req_valid), + .snp_req_addr (snp_req_addr), + .snp_req_invalidate (snp_req_invalidate), + .snp_req_tag (snp_req_tag), + .snp_req_ready (snp_req_ready), + + .snp_rsp_valid (snp_rsp_valid), + .snp_rsp_tag (snp_rsp_tag), + .snp_rsp_ready (snp_rsp_ready), + + .io_req_valid (io_req_valid), + .io_req_rw (io_req_rw), + .io_req_byteen (io_req_byteen), + .io_req_addr (io_req_addr), + .io_req_data (io_req_data), + .io_req_tag (io_req_tag), + .io_req_ready (io_req_ready), + + .io_rsp_valid (io_rsp_valid), + .io_rsp_data (io_rsp_data), + .io_rsp_tag (io_rsp_tag), + .io_rsp_ready (io_rsp_ready), + + .busy (busy), + .ebreak (ebreak) + ); + + end else begin + + wire [`NUM_CLUSTERS-1:0] per_cluster_dram_req_valid; + wire [`NUM_CLUSTERS-1:0] per_cluster_dram_req_rw; + wire [`NUM_CLUSTERS-1:0][`L2DRAM_BYTEEN_WIDTH-1:0] per_cluster_dram_req_byteen; + wire [`NUM_CLUSTERS-1:0][`L2DRAM_ADDR_WIDTH-1:0] per_cluster_dram_req_addr; + wire [`NUM_CLUSTERS-1:0][`L2DRAM_LINE_WIDTH-1:0] per_cluster_dram_req_data; + wire [`NUM_CLUSTERS-1:0][`L2DRAM_TAG_WIDTH-1:0] per_cluster_dram_req_tag; + wire l3_core_req_ready; + + wire [`NUM_CLUSTERS-1:0] per_cluster_dram_rsp_valid; + wire [`NUM_CLUSTERS-1:0][`L3DRAM_LINE_WIDTH-1:0] per_cluster_dram_rsp_data; + wire [`NUM_CLUSTERS-1:0][`L3DRAM_TAG_WIDTH-1:0] per_cluster_dram_rsp_tag; + wire [`NUM_CLUSTERS-1:0] per_cluster_dram_rsp_ready; + + wire [`NUM_CLUSTERS-1:0] per_cluster_snp_req_valid; + wire [`NUM_CLUSTERS-1:0][`L2DRAM_ADDR_WIDTH-1:0] per_cluster_snp_req_addr; + wire [`NUM_CLUSTERS-1:0] per_cluster_snp_req_invalidate; + wire [`NUM_CLUSTERS-1:0][`L2SNP_TAG_WIDTH-1:0] per_cluster_snp_req_tag; + wire [`NUM_CLUSTERS-1:0] per_cluster_snp_req_ready; + + wire [`NUM_CLUSTERS-1:0] per_cluster_snp_rsp_valid; + wire [`NUM_CLUSTERS-1:0][`L2SNP_TAG_WIDTH-1:0] per_cluster_snp_rsp_tag; + wire [`NUM_CLUSTERS-1:0] per_cluster_snp_rsp_ready; + + wire [`NUM_CLUSTERS-1:0] per_cluster_io_req_valid; + wire [`NUM_CLUSTERS-1:0] per_cluster_io_req_rw; + wire [`NUM_CLUSTERS-1:0][3:0] per_cluster_io_req_byteen; + wire [`NUM_CLUSTERS-1:0][29:0] per_cluster_io_req_addr; + wire [`NUM_CLUSTERS-1:0][31:0] per_cluster_io_req_data; + wire [`NUM_CLUSTERS-1:0][`L2CORE_TAG_WIDTH-1:0] per_cluster_io_req_tag; + wire [`NUM_CLUSTERS-1:0] per_cluster_io_req_ready; + + wire [`NUM_CLUSTERS-1:0] per_cluster_io_rsp_valid; + wire [`NUM_CLUSTERS-1:0][`L2CORE_TAG_WIDTH-1:0] per_cluster_io_rsp_tag; + wire [`NUM_CLUSTERS-1:0][31:0] per_cluster_io_rsp_data; + wire [`NUM_CLUSTERS-1:0] per_cluster_io_rsp_ready; + + wire [`NUM_CLUSTERS-1:0] per_cluster_busy; + wire [`NUM_CLUSTERS-1:0] per_cluster_ebreak; + + genvar i; + for (i = 0; i < `NUM_CLUSTERS; i++) begin + VX_cluster #( + .CLUSTER_ID(i) + ) cluster ( + `SCOPE_SIGNALS_ISTAGE_BIND + `SCOPE_SIGNALS_LSU_BIND + `SCOPE_SIGNALS_CORE_BIND + `SCOPE_SIGNALS_ICACHE_BIND + `SCOPE_SIGNALS_PIPELINE_BIND + `SCOPE_SIGNALS_BE_BIND + + .clk (clk), + .reset (reset), + + .dram_req_valid (per_cluster_dram_req_valid [i]), + .dram_req_rw (per_cluster_dram_req_rw [i]), + .dram_req_byteen (per_cluster_dram_req_byteen[i]), + .dram_req_addr (per_cluster_dram_req_addr [i]), + .dram_req_data (per_cluster_dram_req_data [i]), + .dram_req_tag (per_cluster_dram_req_tag [i]), + .dram_req_ready (l3_core_req_ready), + + .dram_rsp_valid (per_cluster_dram_rsp_valid [i]), + .dram_rsp_data (per_cluster_dram_rsp_data [i]), + .dram_rsp_tag (per_cluster_dram_rsp_tag [i]), + .dram_rsp_ready (per_cluster_dram_rsp_ready [i]), + + .snp_req_valid (per_cluster_snp_req_valid [i]), + .snp_req_addr (per_cluster_snp_req_addr [i]), + .snp_req_invalidate (per_cluster_snp_req_invalidate[i]), + .snp_req_tag (per_cluster_snp_req_tag [i]), + .snp_req_ready (per_cluster_snp_req_ready [i]), + + .snp_rsp_valid (per_cluster_snp_rsp_valid [i]), + .snp_rsp_tag (per_cluster_snp_rsp_tag [i]), + .snp_rsp_ready (per_cluster_snp_rsp_ready [i]), + + .io_req_valid (per_cluster_io_req_valid [i]), + .io_req_rw (per_cluster_io_req_rw [i]), + .io_req_byteen (per_cluster_io_req_byteen [i]), + .io_req_addr (per_cluster_io_req_addr [i]), + .io_req_data (per_cluster_io_req_data [i]), + .io_req_tag (per_cluster_io_req_tag [i]), + .io_req_ready (per_cluster_io_req_ready [i]), + + .io_rsp_valid (per_cluster_io_rsp_valid [i]), + .io_rsp_data (per_cluster_io_rsp_data [i]), + .io_rsp_tag (per_cluster_io_rsp_tag [i]), + .io_rsp_ready (per_cluster_io_rsp_ready [i]), + + .busy (per_cluster_busy [i]), + .ebreak (per_cluster_ebreak [i]) + ); + end + + VX_mem_arb #( + .NUM_REQUESTS (`NUM_CLUSTERS), + .WORD_SIZE (4), + .TAG_IN_WIDTH (`L2CORE_TAG_WIDTH), + .TAG_OUT_WIDTH (`L3CORE_TAG_WIDTH) + ) io_arb ( + .clk (clk), + .reset (reset), + + // input requests + .in_mem_req_valid (per_cluster_io_req_valid), + .in_mem_req_rw (per_cluster_io_req_rw), + .in_mem_req_byteen (per_cluster_io_req_byteen), + .in_mem_req_addr (per_cluster_io_req_addr), + .in_mem_req_data (per_cluster_io_req_data), + .in_mem_req_tag (per_cluster_io_req_tag), + .in_mem_req_ready (per_cluster_io_req_ready), + + // input responses + .in_mem_rsp_valid (per_cluster_io_rsp_valid), + .in_mem_rsp_data (per_cluster_io_rsp_data), + .in_mem_rsp_tag (per_cluster_io_rsp_tag), + .in_mem_rsp_ready (per_cluster_io_rsp_ready), + + // output request + .out_mem_req_valid (io_req_valid), + .out_mem_req_rw (io_req_rw), + .out_mem_req_byteen (io_req_byteen), + .out_mem_req_addr (io_req_addr), + .out_mem_req_data (io_req_data), + .out_mem_req_tag (io_req_tag), + .out_mem_req_ready (io_req_ready), + + // output response + .out_mem_rsp_valid (io_rsp_valid), + .out_mem_rsp_tag (io_rsp_tag), + .out_mem_rsp_data (io_rsp_data), + .out_mem_rsp_ready (io_rsp_ready) + ); + + assign busy = (| per_cluster_busy); + assign ebreak = (& per_cluster_ebreak); + + // L3 Cache /////////////////////////////////////////////////////////// + + wire [`L3NUM_REQUESTS-1:0] l3_core_req_valid; + wire [`L3NUM_REQUESTS-1:0] l3_core_req_rw; + wire [`L3NUM_REQUESTS-1:0][`L2DRAM_BYTEEN_WIDTH-1:0] l3_core_req_byteen; + wire [`L3NUM_REQUESTS-1:0][`L2DRAM_ADDR_WIDTH-1:0] l3_core_req_addr; + wire [`L3NUM_REQUESTS-1:0][`L2DRAM_LINE_WIDTH-1:0] l3_core_req_data; + wire [`L3NUM_REQUESTS-1:0][`L2DRAM_TAG_WIDTH-1:0] l3_core_req_tag; + + wire [`L3NUM_REQUESTS-1:0] l3_core_rsp_valid; + wire [`L3NUM_REQUESTS-1:0][`L2DRAM_LINE_WIDTH-1:0] l3_core_rsp_data; + wire [`L3NUM_REQUESTS-1:0][`L2DRAM_TAG_WIDTH-1:0] l3_core_rsp_tag; + wire l3_core_rsp_ready; + + wire [`NUM_CLUSTERS-1:0] l3_snp_fwdout_valid; + wire [`NUM_CLUSTERS-1:0][`L2DRAM_ADDR_WIDTH-1:0] l3_snp_fwdout_addr; + wire [`NUM_CLUSTERS-1:0] l3_snp_fwdout_invalidate; + wire [`NUM_CLUSTERS-1:0][`L2SNP_TAG_WIDTH-1:0] l3_snp_fwdout_tag; + wire [`NUM_CLUSTERS-1:0] l3_snp_fwdout_ready; + + wire [`NUM_CLUSTERS-1:0] l3_snp_fwdin_valid; + wire [`NUM_CLUSTERS-1:0][`L2SNP_TAG_WIDTH-1:0] l3_snp_fwdin_tag; + wire [`NUM_CLUSTERS-1:0] l3_snp_fwdin_ready; + + for (i = 0; i < `L3NUM_REQUESTS; i++) begin + // Core Request + assign l3_core_req_valid [i] = per_cluster_dram_req_valid [i]; + assign l3_core_req_rw [i] = per_cluster_dram_req_rw [i]; + assign l3_core_req_byteen [i] = per_cluster_dram_req_byteen[i]; + assign l3_core_req_addr [i] = per_cluster_dram_req_addr [i]; + assign l3_core_req_tag [i] = per_cluster_dram_req_tag [i]; + assign l3_core_req_data [i] = per_cluster_dram_req_data [i]; + + // Core Response + assign per_cluster_dram_rsp_valid [i] = l3_core_rsp_valid [i] && l3_core_rsp_ready; + assign per_cluster_dram_rsp_data [i] = l3_core_rsp_data [i]; + assign per_cluster_dram_rsp_tag [i] = l3_core_rsp_tag [i]; + + // Snoop Forwarding out + assign per_cluster_snp_req_valid [i] = l3_snp_fwdout_valid[i]; + assign per_cluster_snp_req_addr [i] = l3_snp_fwdout_addr[i]; + assign per_cluster_snp_req_invalidate [i] = l3_snp_fwdout_invalidate[i]; + assign per_cluster_snp_req_tag [i] = l3_snp_fwdout_tag[i]; + assign l3_snp_fwdout_ready [i] = per_cluster_snp_req_ready[i]; + + // Snoop Forwarding in + assign l3_snp_fwdin_valid [i] = per_cluster_snp_rsp_valid [i]; + assign l3_snp_fwdin_tag [i] = per_cluster_snp_rsp_tag [i]; + assign per_cluster_snp_rsp_ready [i] = l3_snp_fwdin_ready [i]; + end + + assign l3_core_rsp_ready = (& per_cluster_dram_rsp_ready); + + VX_cache #( + .CACHE_ID (0), + .CACHE_SIZE (`L3CACHE_SIZE), + .BANK_LINE_SIZE (`L3BANK_LINE_SIZE), + .NUM_BANKS (`L3NUM_BANKS), + .WORD_SIZE (`L3WORD_SIZE), + .NUM_REQUESTS (`L3NUM_REQUESTS), + .STAGE_1_CYCLES (`L3STAGE_1_CYCLES), + .CREQ_SIZE (`L3CREQ_SIZE), + .MRVQ_SIZE (`L3MRVQ_SIZE), + .DFPQ_SIZE (`L3DFPQ_SIZE), + .SNRQ_SIZE (`L3SNRQ_SIZE), + .CWBQ_SIZE (`L3CWBQ_SIZE), + .DWBQ_SIZE (`L3DWBQ_SIZE), + .DFQQ_SIZE (`L3DFQQ_SIZE), + .PRFQ_SIZE (`L3PRFQ_SIZE), + .PRFQ_STRIDE (`L3PRFQ_STRIDE), + .DRAM_ENABLE (1), + .WRITE_ENABLE (1), + .SNOOP_FORWARDING (1), + .CORE_TAG_WIDTH (`L2DRAM_TAG_WIDTH), + .CORE_TAG_ID_BITS (0), + .DRAM_TAG_WIDTH (`L3DRAM_TAG_WIDTH), + .NUM_SNP_REQUESTS (`NUM_CLUSTERS), + .SNP_REQ_TAG_WIDTH (`L3SNP_TAG_WIDTH), + .SNP_FWD_TAG_WIDTH (`L2SNP_TAG_WIDTH) + ) gpu_l3cache ( + .clk (clk), + .reset (reset), + + // Core request + .core_req_valid (l3_core_req_valid), + .core_req_rw (l3_core_req_rw), + .core_req_byteen (l3_core_req_byteen), + .core_req_addr (l3_core_req_addr), + .core_req_data (l3_core_req_data), + .core_req_tag (l3_core_req_tag), + .core_req_ready (l3_core_req_ready), + + // Core response + .core_rsp_valid (l3_core_rsp_valid), + .core_rsp_data (l3_core_rsp_data), + .core_rsp_tag (l3_core_rsp_tag), + .core_rsp_ready (l3_core_rsp_ready), + + // DRAM request + .dram_req_valid (dram_req_valid), + .dram_req_rw (dram_req_rw), + .dram_req_byteen (dram_req_byteen), + .dram_req_addr (dram_req_addr), + .dram_req_data (dram_req_data), + .dram_req_tag (dram_req_tag), + .dram_req_ready (dram_req_ready), + + // DRAM response + .dram_rsp_valid (dram_rsp_valid), + .dram_rsp_data (dram_rsp_data), + .dram_rsp_tag (dram_rsp_tag), + .dram_rsp_ready (dram_rsp_ready), + + // Snoop request + .snp_req_valid (snp_req_valid), + .snp_req_addr (snp_req_addr), + .snp_req_invalidate (snp_req_invalidate), + .snp_req_tag (snp_req_tag), + .snp_req_ready (snp_req_ready), + + // Snoop response + .snp_rsp_valid (snp_rsp_valid), + .snp_rsp_tag (snp_rsp_tag), + .snp_rsp_ready (snp_rsp_ready), + + // Snoop forwarding out + .snp_fwdout_valid (l3_snp_fwdout_valid), + .snp_fwdout_addr (l3_snp_fwdout_addr), + .snp_fwdout_invalidate(l3_snp_fwdout_invalidate), + .snp_fwdout_tag (l3_snp_fwdout_tag), + .snp_fwdout_ready (l3_snp_fwdout_ready), + + // Snoop forwarding in + .snp_fwdin_valid (l3_snp_fwdin_valid), + .snp_fwdin_tag (l3_snp_fwdin_tag), + .snp_fwdin_ready (l3_snp_fwdin_ready) + ); + end + +`ifdef DBG_PRINT_DRAM + always @(posedge clk) begin + if (dram_req_valid && dram_req_ready) begin + $display("%t: DRAM req: rw=%b addr=%0h, tag=%0h, byteen=%0h data=%0h", $time, dram_req_rw, `DRAM_TO_BYTE_ADDR(dram_req_addr), dram_req_tag, dram_req_byteen, dram_req_data); + end + if (dram_rsp_valid && dram_rsp_ready) begin + $display("%t: DRAM rsp: tag=%0h, data=%0h", $time, dram_rsp_tag, dram_rsp_data); + end + end +`endif + +endmodule \ No newline at end of file diff --git a/hw/rtl/Vortex_Socket.v b/hw/rtl/Vortex_Socket.v deleted file mode 100644 index 01e4a96c..00000000 --- a/hw/rtl/Vortex_Socket.v +++ /dev/null @@ -1,406 +0,0 @@ -`include "VX_define.vh" - -module Vortex_Socket ( - `SCOPE_SIGNALS_ISTAGE_IO - `SCOPE_SIGNALS_LSU_IO - `SCOPE_SIGNALS_CORE_IO - `SCOPE_SIGNALS_ICACHE_IO - `SCOPE_SIGNALS_PIPELINE_IO - `SCOPE_SIGNALS_BE_IO - - // Clock - input wire clk, - input wire reset, - - // DRAM request - output wire dram_req_valid, - output wire dram_req_rw, - output wire [`VX_DRAM_BYTEEN_WIDTH-1:0] dram_req_byteen, - output wire [`VX_DRAM_ADDR_WIDTH-1:0] dram_req_addr, - output wire [`VX_DRAM_LINE_WIDTH-1:0] dram_req_data, - output wire [`VX_DRAM_TAG_WIDTH-1:0] dram_req_tag, - input wire dram_req_ready, - - // DRAM response - input wire dram_rsp_valid, - input wire [`VX_DRAM_LINE_WIDTH-1:0] dram_rsp_data, - input wire [`VX_DRAM_TAG_WIDTH-1:0] dram_rsp_tag, - output wire dram_rsp_ready, - - // Snoop request - input wire snp_req_valid, - input wire [`VX_DRAM_ADDR_WIDTH-1:0] snp_req_addr, - input wire snp_req_invalidate, - input wire [`VX_SNP_TAG_WIDTH-1:0] snp_req_tag, - output wire snp_req_ready, - - // Snoop response - output wire snp_rsp_valid, - output wire [`VX_SNP_TAG_WIDTH-1:0] snp_rsp_tag, - input wire snp_rsp_ready, - - // I/O request - output wire io_req_valid, - output wire io_req_rw, - output wire [3:0] io_req_byteen, - output wire [29:0] io_req_addr, - output wire [31:0] io_req_data, - output wire [`VX_CORE_TAG_WIDTH-1:0] io_req_tag, - input wire io_req_ready, - - // I/O response - input wire io_rsp_valid, - input wire [31:0] io_rsp_data, - input wire [`VX_CORE_TAG_WIDTH-1:0] io_rsp_tag, - output wire io_rsp_ready, - - // Status - output wire busy, - output wire ebreak -); - if (`NUM_CLUSTERS == 1) begin - - Vortex_Cluster #( - .CLUSTER_ID(`L3CACHE_ID) - ) Vortex_Cluster ( - `SCOPE_SIGNALS_ISTAGE_BIND - `SCOPE_SIGNALS_LSU_BIND - `SCOPE_SIGNALS_CORE_BIND - `SCOPE_SIGNALS_ICACHE_BIND - `SCOPE_SIGNALS_PIPELINE_BIND - `SCOPE_SIGNALS_BE_BIND - - .clk (clk), - .reset (reset), - - .dram_req_valid (dram_req_valid), - .dram_req_rw (dram_req_rw), - .dram_req_byteen (dram_req_byteen), - .dram_req_addr (dram_req_addr), - .dram_req_data (dram_req_data), - .dram_req_tag (dram_req_tag), - .dram_req_ready (dram_req_ready), - - .dram_rsp_valid (dram_rsp_valid), - .dram_rsp_data (dram_rsp_data), - .dram_rsp_tag (dram_rsp_tag), - .dram_rsp_ready (dram_rsp_ready), - - .snp_req_valid (snp_req_valid), - .snp_req_addr (snp_req_addr), - .snp_req_invalidate (snp_req_invalidate), - .snp_req_tag (snp_req_tag), - .snp_req_ready (snp_req_ready), - - .snp_rsp_valid (snp_rsp_valid), - .snp_rsp_tag (snp_rsp_tag), - .snp_rsp_ready (snp_rsp_ready), - - .io_req_valid (io_req_valid), - .io_req_rw (io_req_rw), - .io_req_byteen (io_req_byteen), - .io_req_addr (io_req_addr), - .io_req_data (io_req_data), - .io_req_tag (io_req_tag), - .io_req_ready (io_req_ready), - - .io_rsp_valid (io_rsp_valid), - .io_rsp_data (io_rsp_data), - .io_rsp_tag (io_rsp_tag), - .io_rsp_ready (io_rsp_ready), - - .busy (busy), - .ebreak (ebreak) - ); - - end else begin - - wire [`NUM_CLUSTERS-1:0] per_cluster_dram_req_valid; - wire [`NUM_CLUSTERS-1:0] per_cluster_dram_req_rw; - wire [`NUM_CLUSTERS-1:0][`L2DRAM_BYTEEN_WIDTH-1:0] per_cluster_dram_req_byteen; - wire [`NUM_CLUSTERS-1:0][`L2DRAM_ADDR_WIDTH-1:0] per_cluster_dram_req_addr; - wire [`NUM_CLUSTERS-1:0][`L2DRAM_LINE_WIDTH-1:0] per_cluster_dram_req_data; - wire [`NUM_CLUSTERS-1:0][`L2DRAM_TAG_WIDTH-1:0] per_cluster_dram_req_tag; - wire l3_core_req_ready; - - wire [`NUM_CLUSTERS-1:0] per_cluster_dram_rsp_valid; - wire [`NUM_CLUSTERS-1:0][`L3DRAM_LINE_WIDTH-1:0] per_cluster_dram_rsp_data; - wire [`NUM_CLUSTERS-1:0][`L3DRAM_TAG_WIDTH-1:0] per_cluster_dram_rsp_tag; - wire [`NUM_CLUSTERS-1:0] per_cluster_dram_rsp_ready; - - wire [`NUM_CLUSTERS-1:0] per_cluster_snp_req_valid; - wire [`NUM_CLUSTERS-1:0][`L2DRAM_ADDR_WIDTH-1:0] per_cluster_snp_req_addr; - wire [`NUM_CLUSTERS-1:0] per_cluster_snp_req_invalidate; - wire [`NUM_CLUSTERS-1:0][`L2SNP_TAG_WIDTH-1:0] per_cluster_snp_req_tag; - wire [`NUM_CLUSTERS-1:0] per_cluster_snp_req_ready; - - wire [`NUM_CLUSTERS-1:0] per_cluster_snp_rsp_valid; - wire [`NUM_CLUSTERS-1:0][`L2SNP_TAG_WIDTH-1:0] per_cluster_snp_rsp_tag; - wire [`NUM_CLUSTERS-1:0] per_cluster_snp_rsp_ready; - - wire [`NUM_CLUSTERS-1:0] per_cluster_io_req_valid; - wire [`NUM_CLUSTERS-1:0] per_cluster_io_req_rw; - wire [`NUM_CLUSTERS-1:0][3:0] per_cluster_io_req_byteen; - wire [`NUM_CLUSTERS-1:0][29:0] per_cluster_io_req_addr; - wire [`NUM_CLUSTERS-1:0][31:0] per_cluster_io_req_data; - wire [`NUM_CLUSTERS-1:0][`L2CORE_TAG_WIDTH-1:0] per_cluster_io_req_tag; - wire [`NUM_CLUSTERS-1:0] per_cluster_io_req_ready; - - wire [`NUM_CLUSTERS-1:0] per_cluster_io_rsp_valid; - wire [`NUM_CLUSTERS-1:0][`L2CORE_TAG_WIDTH-1:0] per_cluster_io_rsp_tag; - wire [`NUM_CLUSTERS-1:0][31:0] per_cluster_io_rsp_data; - wire [`NUM_CLUSTERS-1:0] per_cluster_io_rsp_ready; - - wire [`NUM_CLUSTERS-1:0] per_cluster_busy; - wire [`NUM_CLUSTERS-1:0] per_cluster_ebreak; - - genvar i; - for (i = 0; i < `NUM_CLUSTERS; i++) begin - Vortex_Cluster #( - .CLUSTER_ID(i) - ) Vortex_Cluster ( - `SCOPE_SIGNALS_ISTAGE_BIND - `SCOPE_SIGNALS_LSU_BIND - `SCOPE_SIGNALS_CORE_BIND - `SCOPE_SIGNALS_ICACHE_BIND - `SCOPE_SIGNALS_PIPELINE_BIND - `SCOPE_SIGNALS_BE_BIND - - .clk (clk), - .reset (reset), - - .dram_req_valid (per_cluster_dram_req_valid [i]), - .dram_req_rw (per_cluster_dram_req_rw [i]), - .dram_req_byteen (per_cluster_dram_req_byteen[i]), - .dram_req_addr (per_cluster_dram_req_addr [i]), - .dram_req_data (per_cluster_dram_req_data [i]), - .dram_req_tag (per_cluster_dram_req_tag [i]), - .dram_req_ready (l3_core_req_ready), - - .dram_rsp_valid (per_cluster_dram_rsp_valid [i]), - .dram_rsp_data (per_cluster_dram_rsp_data [i]), - .dram_rsp_tag (per_cluster_dram_rsp_tag [i]), - .dram_rsp_ready (per_cluster_dram_rsp_ready [i]), - - .snp_req_valid (per_cluster_snp_req_valid [i]), - .snp_req_addr (per_cluster_snp_req_addr [i]), - .snp_req_invalidate (per_cluster_snp_req_invalidate[i]), - .snp_req_tag (per_cluster_snp_req_tag [i]), - .snp_req_ready (per_cluster_snp_req_ready [i]), - - .snp_rsp_valid (per_cluster_snp_rsp_valid [i]), - .snp_rsp_tag (per_cluster_snp_rsp_tag [i]), - .snp_rsp_ready (per_cluster_snp_rsp_ready [i]), - - .io_req_valid (per_cluster_io_req_valid [i]), - .io_req_rw (per_cluster_io_req_rw [i]), - .io_req_byteen (per_cluster_io_req_byteen [i]), - .io_req_addr (per_cluster_io_req_addr [i]), - .io_req_data (per_cluster_io_req_data [i]), - .io_req_tag (per_cluster_io_req_tag [i]), - .io_req_ready (per_cluster_io_req_ready [i]), - - .io_rsp_valid (per_cluster_io_rsp_valid [i]), - .io_rsp_data (per_cluster_io_rsp_data [i]), - .io_rsp_tag (per_cluster_io_rsp_tag [i]), - .io_rsp_ready (per_cluster_io_rsp_ready [i]), - - .busy (per_cluster_busy [i]), - .ebreak (per_cluster_ebreak [i]) - ); - end - - VX_mem_arb #( - .NUM_REQUESTS (`NUM_CLUSTERS), - .WORD_SIZE (4), - .TAG_IN_WIDTH (`L2CORE_TAG_WIDTH), - .TAG_OUT_WIDTH (`L3CORE_TAG_WIDTH) - ) io_arb ( - .clk (clk), - .reset (reset), - - // input requests - .in_mem_req_valid (per_cluster_io_req_valid), - .in_mem_req_rw (per_cluster_io_req_rw), - .in_mem_req_byteen (per_cluster_io_req_byteen), - .in_mem_req_addr (per_cluster_io_req_addr), - .in_mem_req_data (per_cluster_io_req_data), - .in_mem_req_tag (per_cluster_io_req_tag), - .in_mem_req_ready (per_cluster_io_req_ready), - - // input responses - .in_mem_rsp_valid (per_cluster_io_rsp_valid), - .in_mem_rsp_data (per_cluster_io_rsp_data), - .in_mem_rsp_tag (per_cluster_io_rsp_tag), - .in_mem_rsp_ready (per_cluster_io_rsp_ready), - - // output request - .out_mem_req_valid (io_req_valid), - .out_mem_req_rw (io_req_rw), - .out_mem_req_byteen (io_req_byteen), - .out_mem_req_addr (io_req_addr), - .out_mem_req_data (io_req_data), - .out_mem_req_tag (io_req_tag), - .out_mem_req_ready (io_req_ready), - - // output response - .out_mem_rsp_valid (io_rsp_valid), - .out_mem_rsp_tag (io_rsp_tag), - .out_mem_rsp_data (io_rsp_data), - .out_mem_rsp_ready (io_rsp_ready) - ); - - assign busy = (| per_cluster_busy); - assign ebreak = (& per_cluster_ebreak); - - // L3 Cache /////////////////////////////////////////////////////////// - - wire [`L3NUM_REQUESTS-1:0] l3_core_req_valid; - wire [`L3NUM_REQUESTS-1:0] l3_core_req_rw; - wire [`L3NUM_REQUESTS-1:0][`L2DRAM_BYTEEN_WIDTH-1:0] l3_core_req_byteen; - wire [`L3NUM_REQUESTS-1:0][`L2DRAM_ADDR_WIDTH-1:0] l3_core_req_addr; - wire [`L3NUM_REQUESTS-1:0][`L2DRAM_LINE_WIDTH-1:0] l3_core_req_data; - wire [`L3NUM_REQUESTS-1:0][`L2DRAM_TAG_WIDTH-1:0] l3_core_req_tag; - - wire [`L3NUM_REQUESTS-1:0] l3_core_rsp_valid; - wire [`L3NUM_REQUESTS-1:0][`L2DRAM_LINE_WIDTH-1:0] l3_core_rsp_data; - wire [`L3NUM_REQUESTS-1:0][`L2DRAM_TAG_WIDTH-1:0] l3_core_rsp_tag; - wire l3_core_rsp_ready; - - wire [`NUM_CLUSTERS-1:0] l3_snp_fwdout_valid; - wire [`NUM_CLUSTERS-1:0][`L2DRAM_ADDR_WIDTH-1:0] l3_snp_fwdout_addr; - wire [`NUM_CLUSTERS-1:0] l3_snp_fwdout_invalidate; - wire [`NUM_CLUSTERS-1:0][`L2SNP_TAG_WIDTH-1:0] l3_snp_fwdout_tag; - wire [`NUM_CLUSTERS-1:0] l3_snp_fwdout_ready; - - wire [`NUM_CLUSTERS-1:0] l3_snp_fwdin_valid; - wire [`NUM_CLUSTERS-1:0][`L2SNP_TAG_WIDTH-1:0] l3_snp_fwdin_tag; - wire [`NUM_CLUSTERS-1:0] l3_snp_fwdin_ready; - - for (i = 0; i < `L3NUM_REQUESTS; i++) begin - // Core Request - assign l3_core_req_valid [i] = per_cluster_dram_req_valid [i]; - assign l3_core_req_rw [i] = per_cluster_dram_req_rw [i]; - assign l3_core_req_byteen [i] = per_cluster_dram_req_byteen[i]; - assign l3_core_req_addr [i] = per_cluster_dram_req_addr [i]; - assign l3_core_req_tag [i] = per_cluster_dram_req_tag [i]; - assign l3_core_req_data [i] = per_cluster_dram_req_data [i]; - - // Core Response - assign per_cluster_dram_rsp_valid [i] = l3_core_rsp_valid [i] && l3_core_rsp_ready; - assign per_cluster_dram_rsp_data [i] = l3_core_rsp_data [i]; - assign per_cluster_dram_rsp_tag [i] = l3_core_rsp_tag [i]; - - // Snoop Forwarding out - assign per_cluster_snp_req_valid [i] = l3_snp_fwdout_valid[i]; - assign per_cluster_snp_req_addr [i] = l3_snp_fwdout_addr[i]; - assign per_cluster_snp_req_invalidate [i] = l3_snp_fwdout_invalidate[i]; - assign per_cluster_snp_req_tag [i] = l3_snp_fwdout_tag[i]; - assign l3_snp_fwdout_ready [i] = per_cluster_snp_req_ready[i]; - - // Snoop Forwarding in - assign l3_snp_fwdin_valid [i] = per_cluster_snp_rsp_valid [i]; - assign l3_snp_fwdin_tag [i] = per_cluster_snp_rsp_tag [i]; - assign per_cluster_snp_rsp_ready [i] = l3_snp_fwdin_ready [i]; - end - - assign l3_core_rsp_ready = (& per_cluster_dram_rsp_ready); - - VX_cache #( - .CACHE_ID (0), - .CACHE_SIZE (`L3CACHE_SIZE), - .BANK_LINE_SIZE (`L3BANK_LINE_SIZE), - .NUM_BANKS (`L3NUM_BANKS), - .WORD_SIZE (`L3WORD_SIZE), - .NUM_REQUESTS (`L3NUM_REQUESTS), - .STAGE_1_CYCLES (`L3STAGE_1_CYCLES), - .CREQ_SIZE (`L3CREQ_SIZE), - .MRVQ_SIZE (`L3MRVQ_SIZE), - .DFPQ_SIZE (`L3DFPQ_SIZE), - .SNRQ_SIZE (`L3SNRQ_SIZE), - .CWBQ_SIZE (`L3CWBQ_SIZE), - .DWBQ_SIZE (`L3DWBQ_SIZE), - .DFQQ_SIZE (`L3DFQQ_SIZE), - .PRFQ_SIZE (`L3PRFQ_SIZE), - .PRFQ_STRIDE (`L3PRFQ_STRIDE), - .DRAM_ENABLE (1), - .WRITE_ENABLE (1), - .SNOOP_FORWARDING (1), - .CORE_TAG_WIDTH (`L2DRAM_TAG_WIDTH), - .CORE_TAG_ID_BITS (0), - .DRAM_TAG_WIDTH (`L3DRAM_TAG_WIDTH), - .NUM_SNP_REQUESTS (`NUM_CLUSTERS), - .SNP_REQ_TAG_WIDTH (`L3SNP_TAG_WIDTH), - .SNP_FWD_TAG_WIDTH (`L2SNP_TAG_WIDTH) - ) gpu_l3cache ( - .clk (clk), - .reset (reset), - - // Core request - .core_req_valid (l3_core_req_valid), - .core_req_rw (l3_core_req_rw), - .core_req_byteen (l3_core_req_byteen), - .core_req_addr (l3_core_req_addr), - .core_req_data (l3_core_req_data), - .core_req_tag (l3_core_req_tag), - .core_req_ready (l3_core_req_ready), - - // Core response - .core_rsp_valid (l3_core_rsp_valid), - .core_rsp_data (l3_core_rsp_data), - .core_rsp_tag (l3_core_rsp_tag), - .core_rsp_ready (l3_core_rsp_ready), - - // DRAM request - .dram_req_valid (dram_req_valid), - .dram_req_rw (dram_req_rw), - .dram_req_byteen (dram_req_byteen), - .dram_req_addr (dram_req_addr), - .dram_req_data (dram_req_data), - .dram_req_tag (dram_req_tag), - .dram_req_ready (dram_req_ready), - - // DRAM response - .dram_rsp_valid (dram_rsp_valid), - .dram_rsp_data (dram_rsp_data), - .dram_rsp_tag (dram_rsp_tag), - .dram_rsp_ready (dram_rsp_ready), - - // Snoop request - .snp_req_valid (snp_req_valid), - .snp_req_addr (snp_req_addr), - .snp_req_invalidate (snp_req_invalidate), - .snp_req_tag (snp_req_tag), - .snp_req_ready (snp_req_ready), - - // Snoop response - .snp_rsp_valid (snp_rsp_valid), - .snp_rsp_tag (snp_rsp_tag), - .snp_rsp_ready (snp_rsp_ready), - - // Snoop forwarding out - .snp_fwdout_valid (l3_snp_fwdout_valid), - .snp_fwdout_addr (l3_snp_fwdout_addr), - .snp_fwdout_invalidate(l3_snp_fwdout_invalidate), - .snp_fwdout_tag (l3_snp_fwdout_tag), - .snp_fwdout_ready (l3_snp_fwdout_ready), - - // Snoop forwarding in - .snp_fwdin_valid (l3_snp_fwdin_valid), - .snp_fwdin_tag (l3_snp_fwdin_tag), - .snp_fwdin_ready (l3_snp_fwdin_ready) - ); - end - -`ifdef DBG_PRINT_DRAM - always @(posedge clk) begin - if (dram_req_valid && dram_req_ready) begin - $display("%t: DRAM req: rw=%b addr=%0h, tag=%0h, byteen=%0h data=%0h", $time, dram_req_rw, `DRAM_TO_BYTE_ADDR(dram_req_addr), dram_req_tag, dram_req_byteen, dram_req_data); - end - if (dram_rsp_valid && dram_rsp_ready) begin - $display("%t: DRAM rsp: tag=%0h, data=%0h", $time, dram_rsp_tag, dram_rsp_data); - end - end -`endif - -endmodule \ No newline at end of file diff --git a/hw/simulate/simulator.cpp b/hw/simulate/simulator.cpp index ecab551d..731ff8fc 100644 --- a/hw/simulate/simulator.cpp +++ b/hw/simulate/simulator.cpp @@ -14,7 +14,7 @@ Simulator::Simulator() { Verilated::randReset(2); ram_ = nullptr; - vortex_ = new VVortex_Socket(); + vortex_ = new VVortex(); dram_rsp_active_ = false; snp_req_active_ = false; @@ -241,12 +241,12 @@ bool Simulator::run() { // check riscv-tests PASSED/FAILED status #if (NUM_CLUSTERS == 1 && NUM_CORES == 1) - int status = (int)vortex_->Vortex_Socket->genblk1__DOT__Vortex_Cluster->genblk1__BRA__0__KET____DOT__vortex_core->pipeline->back_end->writeback->last_data_wb & 0xf; + int status = (int)vortex_->Vortex->genblk1__DOT__cluster->genblk1__BRA__0__KET____DOT__core->pipeline->back_end->writeback->last_data_wb & 0xf; #else #if (NUM_CLUSTERS == 1) - int status = (int)vortex_->Vortex_Socket->genblk1__DOT__Vortex_Cluster->genblk1__BRA__0__KET____DOT__vortex_core->pipeline->back_end->writeback->last_data_wb & 0xf; + int status = (int)vortex_->Vortex->genblk1__DOT__cluster->genblk1__BRA__0__KET____DOT__core->pipeline->back_end->writeback->last_data_wb & 0xf; #else - int status = (int)vortex_->Vortex_Socket->genblk2__DOT__genblk1__BRA__0__KET____DOT__Vortex_Cluster->genblk1__BRA__0__KET____DOT__vortex_core->pipeline->back_end->writeback->last_data_wb & 0xf; + int status = (int)vortex_->Vortex->genblk2__DOT__genblk1__BRA__0__KET____DOT__cluster->genblk1__BRA__0__KET____DOT__core->pipeline->back_end->writeback->last_data_wb & 0xf; #endif #endif diff --git a/hw/simulate/simulator.h b/hw/simulate/simulator.h index 1a5a9b6c..27803754 100644 --- a/hw/simulate/simulator.h +++ b/hw/simulate/simulator.h @@ -1,7 +1,7 @@ #pragma once -#include "VVortex_Socket.h" -#include "VVortex_Socket__Syms.h" +#include "VVortex.h" +#include "VVortex__Syms.h" #include "verilated.h" #ifdef VCD_OUTPUT @@ -62,7 +62,7 @@ private: uint32_t pending_snp_reqs_; RAM *ram_; - VVortex_Socket *vortex_; + VVortex *vortex_; #ifdef VCD_OUTPUT VerilatedVcdC *trace_; #endif diff --git a/hw/syn/quartus/vortex/Makefile b/hw/syn/quartus/vortex/Makefile index 618e3a32..c566ee4e 100644 --- a/hw/syn/quartus/vortex/Makefile +++ b/hw/syn/quartus/vortex/Makefile @@ -1,6 +1,6 @@ -PROJECT = VX_vortex -TOP_LEVEL_ENTITY = VX_vortex -SRC_FILE = VX_vortex.v +PROJECT = Vortex +TOP_LEVEL_ENTITY = Vortex +SRC_FILE = Vortex.v PROJECT_FILES = $(PROJECT).qpf $(PROJECT).qsf # Part, Family