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Fixed two variabled driving the dram_delay signal

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This commit is contained in:
felsabbagh3
2020-04-20 00:33:24 -07:00
parent 460aabf6b1
commit 5e570d95d8
1 changed files with 21 additions and 21 deletions
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42
hw/simulate/simulator.cpp
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@@ -51,7 +51,7 @@ void Simulator::ibus_driver() {
}
}
if (vortex_->I_dram_req && !I_dram_stalled_) {
if (vortex_->I_dram_req && !dram_stalled_) {
// std::cout << "Icache Dram Request received!\n";
if (vortex_->I_dram_req_read) {
// std::cout << "Icache Dram Request is read!\n";
@@ -102,17 +102,17 @@ void Simulator::ibus_driver() {
vortex_->I_dram_fill_rsp_addr = 0;
}
#ifdef ENABLE_DRAM_STALLS
I_dram_stalled_ = false;
if (0 == (total_cycles_ % DRAM_STALLS_MODULO)) {
I_dram_stalled_ = true;
} else
if (I_dram_req_vec_.size() >= DRAM_RQ_SIZE) {
I_dram_stalled_ = true;
}
#endif
// #ifdef ENABLE_DRAM_STALLS
// I_dram_stalled_ = false;
// if (0 == (total_cycles_ % DRAM_STALLS_MODULO)) {
// I_dram_stalled_ = true;
// } else
// if (I_dram_req_vec_.size() >= DRAM_RQ_SIZE) {
// I_dram_stalled_ = true;
// }
// #endif
vortex_->dram_req_delay = I_dram_stalled_;
// vortex_->dram_req_delay = I_dram_stalled_;
}
#endif
@@ -132,16 +132,6 @@ void Simulator::dbus_driver() {
}
}
#ifdef ENABLE_DRAM_STALLS
dram_stalled_ = false;
if (0 == (total_cycles_ % DRAM_STALLS_MODULO)) {
dram_stalled_ = true;
} else
if (dram_req_vec_.size() >= DRAM_RQ_SIZE) {
dram_stalled_ = true;
}
#endif
#ifdef USE_MULTICORE
if (vortex_->out_dram_req && !dram_stalled_) {
@@ -286,6 +276,16 @@ void Simulator::step() {
vortex_->clk = 1;
vortex_->eval();
#ifdef ENABLE_DRAM_STALLS
dram_stalled_ = false;
if (0 == (total_cycles_ % DRAM_STALLS_MODULO)) {
dram_stalled_ = true;
} else
if (dram_req_vec_.size() >= DRAM_RQ_SIZE) {
dram_stalled_ = true;
}
#endif
#ifndef USE_MULTICORE
ibus_driver();
#endif