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ALL tests passing - handshake

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This commit is contained in:
felsabbagh3
2020-03-27 21:34:49 -07:00
parent 614797e52f
commit 5dc9493c61
11 changed files with 28470 additions and 28214 deletions
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20
rtl/VX_cache/VX_cache_miss_resrv.v
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@@ -118,6 +118,10 @@ module VX_cache_miss_resrv
assign miss_resrv_addr_st0 = addr_table[dequeue_index];
assign {miss_resrv_data_st0, miss_resrv_tid_st0, miss_resrv_rd_st0, miss_resrv_wb_st0, miss_resrv_warp_num_st0, miss_resrv_mem_read_st0, miss_resrv_mem_write_st0} = metadata_table[dequeue_index];
wire mrvq_push = miss_add && enqueue_possible && (MRVQ_SIZE != 2);
wire mrvq_pop = miss_resrv_pop && dequeue_possible;
wire update_ready = (|make_ready);
integer i;
always @(posedge clk) begin
@@ -128,8 +132,7 @@ module VX_cache_miss_resrv
addr_table <= 0;
pc_table <= 0;
end else begin
if (miss_add && enqueue_possible && (MRVQ_SIZE != 2)) begin
size <= size + 1;
if (mrvq_push) begin
valid_table[enqueue_index] <= 1;
ready_table[enqueue_index] <= 0;
pc_table[enqueue_index] <= miss_add_pc;
@@ -142,8 +145,7 @@ module VX_cache_miss_resrv
ready_table <= ready_table | make_ready;
end
if (miss_resrv_pop && dequeue_possible) begin
size <= size - 1;
if (mrvq_pop) begin
valid_table[dequeue_index] <= 0;
ready_table[dequeue_index] <= 0;
addr_table[dequeue_index] <= 0;
@@ -152,6 +154,16 @@ module VX_cache_miss_resrv
head_ptr <= head_ptr + 1;
end
if (!(mrvq_push && mrvq_pop)) begin
if (mrvq_push) begin
size <= size + 1;
end
if (mrvq_pop) begin
size <= size - 1;
end
end
end
end

4
rtl/VX_cache/VX_tag_data_access.v
View File

@@ -239,7 +239,7 @@ module VX_tag_data_access
wire[3:0] sh_mask = (b0 ? 4'b0011 : 4'b1100);
wire should_write = (sw || sb || sh) && valid_req_st1e && use_read_valid_st1e && !miss_st1e;
wire force_write = real_writefill && valid_req_st1e && miss_st1e && (!use_read_valid_st1e || (use_read_valid_st1e && !miss_st1e));
wire force_write = real_writefill;
wire[`DBANK_LINE_SIZE_RNG][3:0] we;
wire[`DBANK_LINE_SIZE_RNG][31:0] data_write;
@@ -277,7 +277,7 @@ module VX_tag_data_access
assign readdata_st1e = use_read_data_st1e;
assign readtag_st1e = use_read_tag_st1e;
assign fill_sent = miss_st1e;
assign fill_saw_dirty_st1e = force_write && dirty_st1e && miss_st1e;
assign fill_saw_dirty_st1e = real_writefill && dirty_st1e;
assign invalidate_line = is_snp_st1e && !miss_st1e;
endmodule

2
rtl/VX_cache/VX_tag_data_structure.v
View File

@@ -93,7 +93,7 @@ module VX_tag_data_structure
end
end else if (fill_sent) begin
dirty[write_addr[`LINE_SELECT_ADDR_RNG]] <= 0;
valid[write_addr[`LINE_SELECT_ADDR_RNG]] <= 0;
// valid[write_addr[`LINE_SELECT_ADDR_RNG]] <= 0;
end
if (invalidate) begin