diff --git a/hw/rtl/VX_core_wrapper.sv b/hw/rtl/VX_core_wrapper.sv
index 79507dd9..ea1ed8a6 100644
--- a/hw/rtl/VX_core_wrapper.sv
+++ b/hw/rtl/VX_core_wrapper.sv
@@ -152,7 +152,7 @@ module Vortex import VX_gpu_pkg::*; #(
       if (reset) begin
         busy_prev <= 1'b0;
         finished_reg <= 1'b0;
-        intr_counter <= 4'h0;
+        intr_counter <= 4'h8;
       end else begin
         // Vortex core's busy signal goes up some cycles after the reset,
         // so we can't simply use ~busy as finished because of the initial
@@ -165,8 +165,8 @@ module Vortex import VX_gpu_pkg::*; #(
 
         if (~msip_1d && interrupts_msip) begin
           // rising edge
-          intr_counter <= 4'h6;
-        end else begin
+          intr_counter <= 4'h7;
+        end else if (intr_counter <= 4'h7) begin
           intr_counter <= intr_counter > 0 ? intr_counter - 4'h1 : 4'h0;
         end
       end
@@ -310,7 +310,6 @@ module Vortex import VX_gpu_pkg::*; #(
 
     logic [3:0] reset_start_counter;
     logic core_reset;
-    logic dcr_reset;
 
     always @(posedge clock) begin
       if (reset) begin
@@ -323,8 +322,7 @@ module Vortex import VX_gpu_pkg::*; #(
     end
     // Delay reset signal by a few cycles to make time for resetting the DCR
     // (device configuration registers).
-    assign core_reset = reset || (reset_start_counter != 4'h0); // || intr_reset;
-    assign dcr_reset = !reset && (reset_start_counter != 4'h0);
+    assign core_reset = reset || (reset_start_counter != 4'h0) || intr_reset;
 
     // A small FSM that tries to set DCR "properly" in the same order as
     // defined in VX_types.vh.
@@ -500,6 +498,12 @@ module Vortex import VX_gpu_pkg::*; #(
     always @(*) begin
         if (busy === 1'b0) begin
             $display("---------------- no more active warps ----------------");
+            `ifdef SIMULATION
+            if ($time >= 60000) begin
+              $display("simulation has probably ended. exiting");
+              @(posedge clock) $finish();
+            end
+            `endif
             // TODO: lane assumed to be 4
             // `ifndef SYNTHESIS
             // for (integer j = 0; j < `NUM_WARPS; j++) begin
diff --git a/hw/rtl/VX_platform.vh b/hw/rtl/VX_platform.vh
index e3e15751..b25503ac 100644
--- a/hw/rtl/VX_platform.vh
+++ b/hw/rtl/VX_platform.vh
@@ -207,7 +207,7 @@
 `define UNUSED_ARG(x)   /* verilator lint_off UNUSED */ \
                         x \
                         /* verilator lint_on UNUSED */
-`define TRACE(level, args) dpi_trace(level, $sformatf args)
+`define TRACE(level, args) $display args
 `endif
 `endif
 
diff --git a/hw/rtl/libs/VX_mem_scheduler.sv b/hw/rtl/libs/VX_mem_scheduler.sv
index c7a46535..4138c6c8 100644
--- a/hw/rtl/libs/VX_mem_scheduler.sv
+++ b/hw/rtl/libs/VX_mem_scheduler.sv
@@ -572,6 +572,28 @@ module VX_mem_scheduler #(
             `TRACE(1, (", ibuf_idx=%0d, batch_idx=%0d (#%0d)\n", ibuf_raddr, rsp_batch_idx, mem_rsp_dbg_uuid));
         end
     end
+`else
+    always @(posedge clk) begin
+        if (req_valid && req_ready) begin
+            if (req_rw) begin
+                `TRACE(1, ("%d: %s-core-req-wr: valid=%b, addr=", $time, INST_ID, req_mask));
+                `TRACE_ARRAY1D(1, req_addr, NUM_REQS);
+                `TRACE(1, (", byteen="));
+                `TRACE_ARRAY1D(1, req_byteen, NUM_REQS);
+                `TRACE(1, (", data="));
+                `TRACE_ARRAY1D(1, req_data, NUM_REQS);
+            end else begin
+                `TRACE(1, ("%d: %s-core-req-rd: valid=%b, addr=", $time, INST_ID, req_mask));
+                `TRACE_ARRAY1D(1, req_addr, NUM_REQS);
+            end
+            `TRACE(1, (", tag=0x%0h, tag_only=0x%0h\n", req_tag, req_tag[TAG_ONLY_WIDTH-1:0]));
+        end
+        if (rsp_valid && rsp_ready) begin
+            `TRACE(1, ("%d: %s-rsp: valid=%b, sop=%b, eop=%b, data=", $time, INST_ID, rsp_mask, rsp_sop, rsp_eop));
+            `TRACE_ARRAY1D(1, rsp_data, NUM_REQS);
+            `TRACE(1, (", tag=0x%0h, tag_only=0x%0h\n", rsp_tag, rsp_tag[TAG_ONLY_WIDTH-1:0]));
+        end
+    end
 `endif
   
 endmodule