Gather FPGA perf stats
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@@ -35,7 +35,7 @@ module VX_divide #(
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quartus_div.lpm_widthd = WIDTHD,
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quartus_div.lpm_nrepresentation = NSIGNED ? "SIGNED" : "UNSIGNED",
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quartus_div.lpm_drepresentation = DSIGNED ? "SIGNED" : "UNSIGNED",
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quartus_div.lpm_hint = "LPM_REMAINDERPOSITIVE=FALSE,MAXIMIZE_SPEED=9",
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quartus_div.lpm_hint = "MAXIMIZE_SPEED=6,LPM_REMAINDERPOSITIVE=FALSE",
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quartus_div.lpm_pipeline = PIPELINE;
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`else
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