Gather FPGA perf stats

This commit is contained in:
Blaise Tine
2020-07-01 09:30:12 -07:00
parent e92029c31a
commit 5d088d67c8
12 changed files with 55 additions and 51 deletions

View File

@@ -35,7 +35,7 @@ module VX_divide #(
quartus_div.lpm_widthd = WIDTHD,
quartus_div.lpm_nrepresentation = NSIGNED ? "SIGNED" : "UNSIGNED",
quartus_div.lpm_drepresentation = DSIGNED ? "SIGNED" : "UNSIGNED",
quartus_div.lpm_hint = "LPM_REMAINDERPOSITIVE=FALSE,MAXIMIZE_SPEED=9",
quartus_div.lpm_hint = "MAXIMIZE_SPEED=6,LPM_REMAINDERPOSITIVE=FALSE",
quartus_div.lpm_pipeline = PIPELINE;
`else

View File

@@ -23,9 +23,9 @@ module VX_mult #(
.dataa (dataa),
.datab (datab),
.result (result),
.sclr (reset),
.aclr (1'b0),
.clken (1'b1),
.sclr (1'b0),
.sum (1'b0)
);
@@ -35,7 +35,7 @@ module VX_mult #(
quartus_mult.lpm_widthp = WIDTHP,
quartus_mult.lpm_representation = SIGNED ? "SIGNED" : "UNSIGNED",
quartus_mult.lpm_pipeline = PIPELINE,
quartus_mult.lpm_hint = "MAXIMIZE_SPEED=9";
quartus_mult.lpm_hint = "DEDICATED_MULTIPLIER_CIRCUITRY=YES,MAXIMIZE_SPEED=9";
`else
wire [WIDTHP-1:0] result_unqual;