Gather FPGA perf stats
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@@ -35,7 +35,7 @@ module VX_divide #(
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quartus_div.lpm_widthd = WIDTHD,
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quartus_div.lpm_nrepresentation = NSIGNED ? "SIGNED" : "UNSIGNED",
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quartus_div.lpm_drepresentation = DSIGNED ? "SIGNED" : "UNSIGNED",
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quartus_div.lpm_hint = "LPM_REMAINDERPOSITIVE=FALSE,MAXIMIZE_SPEED=9",
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quartus_div.lpm_hint = "MAXIMIZE_SPEED=6,LPM_REMAINDERPOSITIVE=FALSE",
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quartus_div.lpm_pipeline = PIPELINE;
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`else
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@@ -23,9 +23,9 @@ module VX_mult #(
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.dataa (dataa),
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.datab (datab),
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.result (result),
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.sclr (reset),
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.aclr (1'b0),
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.clken (1'b1),
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.sclr (1'b0),
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.sum (1'b0)
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);
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@@ -35,7 +35,7 @@ module VX_mult #(
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quartus_mult.lpm_widthp = WIDTHP,
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quartus_mult.lpm_representation = SIGNED ? "SIGNED" : "UNSIGNED",
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quartus_mult.lpm_pipeline = PIPELINE,
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quartus_mult.lpm_hint = "MAXIMIZE_SPEED=9";
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quartus_mult.lpm_hint = "DEDICATED_MULTIPLIER_CIRCUITRY=YES,MAXIMIZE_SPEED=9";
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`else
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wire [WIDTHP-1:0] result_unqual;
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