Gather FPGA perf stats

hw/rtl/VX_csr_arb.v

@@ -18,24 +18,21 @@ module VX_csr_arb (
     `UNUSED_VAR (clk)
     `UNUSED_VAR (reset)
 
-    wire pick_core = (| csr_core_req_if.valid);
-
-    // Which request to pick
-    assign issued_csr_req_if.is_io       = !pick_core;
+    wire pick_core = (| csr_core_req_if.valid);    
    
     // Mux between core and io
 	assign issued_csr_req_if.valid       = pick_core ? csr_core_req_if.valid       : {`NUM_THREADS{csr_io_req_if.valid}};
     assign issued_csr_req_if.is_csr      = pick_core ? csr_core_req_if.is_csr      : 1'b1;
 	assign issued_csr_req_if.alu_op      = pick_core ? csr_core_req_if.alu_op      : (csr_io_req_if.rw ? `ALU_CSR_RW : `ALU_CSR_RS);
-	assign issued_csr_req_if.csr_address = pick_core ? csr_core_req_if.csr_address : csr_io_req_if.addr;
-	assign issued_csr_req_if.csr_mask    = pick_core ? csr_core_req_if.csr_mask    : (csr_io_req_if.rw ? csr_io_req_if.data : 32'b0);
-
-    assign csr_io_req_if.ready = !(csr_pipe_stall || pick_core);
-
-    // Core arguments
-    assign issued_csr_req_if.warp_num    = csr_core_req_if.warp_num;
+	assign issued_csr_req_if.csr_address = pick_core ? csr_core_req_if.csr_address : csr_io_req_if.addr;	
+    assign issued_csr_req_if.csr_immed   = pick_core ? csr_core_req_if.csr_immed   : 0;  
+    assign issued_csr_req_if.csr_mask    = pick_core ? csr_core_req_if.csr_mask    : (csr_io_req_if.rw ? csr_io_req_if.data : 32'b0);
+    assign issued_csr_req_if.is_io       = !pick_core;
+    assign issued_csr_req_if.warp_num    = csr_core_req_if.warp_num;    
 	assign issued_csr_req_if.rd          = csr_core_req_if.rd;
-	assign issued_csr_req_if.wb          = csr_core_req_if.wb;
+	assign issued_csr_req_if.wb          = csr_core_req_if.wb;    
+
+    assign csr_io_req_if.ready = !(csr_pipe_stall || pick_core);    
 
     // Core Writeback    
     assign csr_wb_if.valid    = csr_pipe_rsp_if.valid & {`NUM_THREADS{~csr_pipe_rsp_if.is_io}};