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minor update

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This commit is contained in:
Blaise Tine
2021-01-07 17:25:59 -08:00
parent ac2242b51f
commit 5c83c594c1
4 changed files with 20 additions and 11 deletions
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24
driver/rtlsim/vortex.cpp
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@@ -84,10 +84,14 @@ public:
if (dest_addr + asize > ram_.size()) if (dest_addr + asize > ram_.size())
return -1; return -1;
/*printf("VXDRV: upload %d bytes to 0x%x\n", size, dest_addr); /*printf("VXDRV: upload %d bytes from 0x%lx to 0x%lx", size, (uint8_t*)src + src_offset, dest_addr);
for (int i = 0; i < size; i += 4) { if (size <= 1024) {
printf("mem-write: 0x%x <- 0x%x\n", uint32_t(dest_addr + i), *(uint32_t*)((uint8_t*)src + src_offset + i)); printf(": ");
}*/ for (int i = asize-1; i >= 0; --i) {
printf("%x", *((uint8_t*)src + src_offset + i));
}
}
printf("\n");*/
ram_.write(dest_addr, asize, (uint8_t*)src + src_offset); ram_.write(dest_addr, asize, (uint8_t*)src + src_offset);
return 0; return 0;
@@ -100,10 +104,14 @@ public:
ram_.read(src_addr, asize, (uint8_t*)dest + dest_offset); ram_.read(src_addr, asize, (uint8_t*)dest + dest_offset);
/*printf("VXDRV: download %d bytes from 0x%x\n", size, src_addr); /*printf("VXDRV: download %d bytes from 0x%lx to 0x%lx", size, src_addr, (uint8_t*)dest + dest_offset);
for (int i = 0; i < size; i += 4) { if (size <= 1024) {
printf("mem-read: 0x%x -> 0x%x\n", uint32_t(src_addr + i), *(uint32_t*)((uint8_t*)dest + dest_offset + i)); printf(": ");
}*/ for (int i = asize-1; i >= 0; --i) {
printf("%x", *((uint8_t*)dest + dest_offset + i));
}
}
printf("\n");*/
return 0; return 0;
} }

2
hw/rtl/VX_cluster.v
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@@ -72,7 +72,7 @@ module VX_cluster #(
wire core_reset; wire core_reset;
VX_reset_relay #( VX_reset_relay #(
.PASSTHRU (`NUM_CORES == 1) .PASSTHRU (`NUM_CORES <= 2)
) reset_relay ( ) reset_relay (
.clk (clk), .clk (clk),
.reset (reset), .reset (reset),

2
hw/rtl/Vortex.v
View File

@@ -73,7 +73,7 @@ module Vortex (
wire cluster_reset; wire cluster_reset;
VX_reset_relay #( VX_reset_relay #(
.PASSTHRU (`NUM_CLUSTERS == 1) .PASSTHRU (`NUM_CLUSTERS <= 2)
) reset_relay ( ) reset_relay (
.clk (clk), .clk (clk),
.reset (reset), .reset (reset),

3
hw/rtl/libs/VX_skid_buffer.v
View File

@@ -72,11 +72,12 @@ module VX_skid_buffer #(
valid_out_r <= valid_in || use_buffer; valid_out_r <= valid_in || use_buffer;
end end
end end
end
always @(posedge clk) begin
if (push) begin if (push) begin
buffer <= data_in; buffer <= data_in;
end end
if (!valid_out_r || ready_out) begin if (!valid_out_r || ready_out) begin
data_out_r <= use_buffer ? buffer : data_in; data_out_r <= use_buffer ? buffer : data_in;
end end