minor update
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@@ -72,7 +72,7 @@ module VX_cluster #(
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wire core_reset;
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VX_reset_relay #(
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.PASSTHRU (`NUM_CORES == 1)
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.PASSTHRU (`NUM_CORES <= 2)
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) reset_relay (
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.clk (clk),
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.reset (reset),
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@@ -73,7 +73,7 @@ module Vortex (
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wire cluster_reset;
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VX_reset_relay #(
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.PASSTHRU (`NUM_CLUSTERS == 1)
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.PASSTHRU (`NUM_CLUSTERS <= 2)
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) reset_relay (
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.clk (clk),
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.reset (reset),
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@@ -72,11 +72,12 @@ module VX_skid_buffer #(
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valid_out_r <= valid_in || use_buffer;
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end
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end
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end
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always @(posedge clk) begin
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if (push) begin
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buffer <= data_in;
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end
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if (!valid_out_r || ready_out) begin
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data_out_r <= use_buffer ? buffer : data_in;
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end
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