diff --git a/hw/rtl/VX_alu_unit.v b/hw/rtl/VX_alu_unit.v
index 9e126d0c..5a11e40f 100644
--- a/hw/rtl/VX_alu_unit.v
+++ b/hw/rtl/VX_alu_unit.v
@@ -199,4 +199,13 @@ module VX_alu_unit #(
     // can accept new request?
     assign alu_req_if.ready = ~stall_in;
 
+`ifdef DBG_PRINT_PIPELINE
+    always @(posedge clk) begin
+        if (branch_ctl_if.valid) begin
+            $display("%t: core%0d-branch: wid=%0d, PC=%0h, taken=%b, dest=%0h", $time, CORE_ID, 
+                branch_ctl_if.wid, alu_commit_if.PC, branch_ctl_if.taken, branch_ctl_if.dest);
+        end
+    end
+`endif
+
 endmodule
\ No newline at end of file
diff --git a/hw/rtl/libs/VX_elastic_buffer.v b/hw/rtl/libs/VX_elastic_buffer.v
index a515c836..8e6562ed 100644
--- a/hw/rtl/libs/VX_elastic_buffer.v
+++ b/hw/rtl/libs/VX_elastic_buffer.v
@@ -17,6 +17,8 @@ module VX_elastic_buffer #(
     input  wire             ready_out,
     output wire             valid_out
 );
+    `STATIC_ASSERT (SIZE != 1, ("invalid value"))
+
     if (SIZE == 0) begin
 
         `UNUSED_VAR (clk)
diff --git a/hw/simulate/Makefile b/hw/simulate/Makefile
index 31025c4e..69a78505 100644
--- a/hw/simulate/Makefile
+++ b/hw/simulate/Makefile
@@ -95,25 +95,5 @@ build-md: gen-md
 build-mt: gen-mt
 	make -j -C obj_dir -f VVortex.mk
 
-run: run-s
-
-run-s: build-s
-	(cd obj_dir && ./VVortex)
-
-run-sd: build-sd
-	(cd obj_dir && ./VVortex)
-
-run-st: build-st
-	(cd obj_dir && ./VVortex)
-
-run-m: build-m
-	(cd obj_dir && ./VVortex)
-
-run-md: build-md
-	(cd obj_dir && ./VVortex)
-
-run-mt: build-mt
-	(cd obj_dir && ./VVortex)
-
 clean:
 	rm -rf obj_dir
diff --git a/hw/syn/opae/README b/hw/syn/opae/README
index 1c61ca16..6c419892 100644
--- a/hw/syn/opae/README
+++ b/hw/syn/opae/README
@@ -81,7 +81,6 @@ tar -zcvf output_files_1c.tar.gz `find ./build_fpga_1c -type f \( -iname \*.rpt
 
 # compress VCD trace
 tar -zcvf run.log.tar.gz run.log
-tar -cvjf vx_scope.vcd.tar.bz2 vx_scope.vcd
 tar -cvjf trace.vcd.tar.bz2 trace.vcd run.log
 tar -cvjf trace.vcd.tar.bz2 build_ase_arria10_1c/work/run.log build_ase_arria10_1c/work/trace.vcd