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dcache response bus optimization

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Blaise Tine
2021-07-12 10:14:48 -07:00
parent b99fb41d52
commit 5c40422e4f
16 changed files with 350 additions and 259 deletions
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4
hw/syn/quartus/unittest/Makefile
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@@ -1,6 +1,6 @@
PROJECT = Unittest
TOP_LEVEL_ENTITY = VX_cache_core_req_bank_sel
SRC_FILE = VX_cache_core_req_bank_sel.v
TOP_LEVEL_ENTITY = VX_core_req_bank_sel
SRC_FILE = VX_core_req_bank_sel.v
RTL_DIR = ../../../../rtl
FAMILY = "Arria 10"